1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
38 #include "opcode/mips.h"
41 /* Clean up namespace so we can include obj-elf.h too. */
42 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
43 #undef OBJ_PROCESS_STAB
49 #undef TARGET_SYMBOL_FIELDS
51 #undef obj_frob_file_after_relocs
52 #undef obj_frob_symbol
54 #undef obj_sec_sym_ok_for_reloc
57 /* Fix any of them that we actually care about. */
59 #define OUTPUT_FLAVOR mips_output_flavor()
66 #ifndef ECOFF_DEBUGGING
67 #define NO_ECOFF_DEBUGGING
68 #define ECOFF_DEBUGGING 0
73 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
74 static char *mips_regmask_frag
;
79 #define PIC_CALL_REG 25
87 #define ILLEGAL_REG (32)
89 extern int target_big_endian
;
91 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
92 32 bit ABI. This has no meaning for ECOFF. */
95 /* The default target format to use. */
99 switch (OUTPUT_FLAVOR
)
101 case bfd_target_aout_flavour
:
102 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
103 case bfd_target_ecoff_flavour
:
104 return target_big_endian
? "ecoff-bigmips" : "ecoff-littlemips";
105 case bfd_target_elf_flavour
:
106 return (target_big_endian
107 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
108 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
114 /* The name of the readonly data section. */
115 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
117 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
119 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
123 /* These variables are filled in with the masks of registers used.
124 The object format code reads them and puts them in the appropriate
126 unsigned long mips_gprmask
;
127 unsigned long mips_cprmask
[4];
129 /* MIPS ISA (Instruction Set Architecture) level (may be changed
130 temporarily using .set mipsN). */
131 static int mips_isa
= -1;
133 /* MIPS ISA we are using for this output file. */
134 static int file_mips_isa
;
136 /* Whether we are assembling for the mips16 processor. */
137 static int mips16
= -1;
139 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
140 static int mips_cpu
= -1;
142 /* Whether the 4650 instructions (mad/madu) are permitted. */
143 static int mips_4650
= -1;
145 /* Whether the 4010 instructions are permitted. */
146 static int mips_4010
= -1;
148 /* Whether the 4100 MADD16 and DMADD16 are permitted. */
149 static int mips_4100
= -1;
151 /* start-sanitize-r5900 */
152 /* Whether Toshiba r5900 instructions are permitted. */
153 static int mips_5900
= -1;
154 /* end-sanitize-r5900 */
156 /* Whether the processor uses hardware interlocks, and thus does not
157 require nops to be inserted. */
158 static int interlocks
= -1;
160 /* As with "interlocks" this is used by hardware that has FP
161 (co-processor) interlocks. */
162 static int cop_interlocks
= -1;
164 /* MIPS PIC level. */
168 /* Do not generate PIC code. */
171 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
172 not sure what it is supposed to do. */
175 /* Generate PIC code as in the SVR4 MIPS ABI. */
178 /* Generate PIC code without using a global offset table: the data
179 segment has a maximum size of 64K, all data references are off
180 the $gp register, and all text references are PC relative. This
181 is used on some embedded systems. */
185 static enum mips_pic_level mips_pic
;
187 /* 1 if we should generate 32 bit offsets from the GP register in
188 SVR4_PIC mode. Currently has no meaning in other modes. */
189 static int mips_big_got
;
191 /* 1 if trap instructions should used for overflow rather than break
193 static int mips_trap
;
195 /* 1 if we should autoextend mips16 instructions. */
196 static int mips16_autoextend
= 1;
198 static int mips_warn_about_macros
;
199 static int mips_noreorder
;
200 static int mips_any_noreorder
;
201 static int mips_nomove
;
202 static int mips_noat
;
203 static int mips_nobopt
;
205 /* The size of the small data section. */
206 static int g_switch_value
= 8;
207 /* Whether the -G option was used. */
208 static int g_switch_seen
= 0;
213 /* If we can determine in advance that GP optimization won't be
214 possible, we can skip the relaxation stuff that tries to produce
215 GP-relative references. This makes delay slot optimization work
218 This function can only provide a guess, but it seems to work for
219 gcc output. If it guesses wrong, the only loss should be in
220 efficiency; it shouldn't introduce any bugs.
222 I don't know if a fix is needed for the SVR4_PIC mode. I've only
223 fixed it for the non-PIC mode. KR 95/04/07 */
224 static int nopic_need_relax
PARAMS ((symbolS
*));
226 /* handle of the OPCODE hash table */
227 static struct hash_control
*op_hash
= NULL
;
229 /* The opcode hash table we use for the mips16. */
230 static struct hash_control
*mips16_op_hash
= NULL
;
232 /* This array holds the chars that always start a comment. If the
233 pre-processor is disabled, these aren't very useful */
234 const char comment_chars
[] = "#";
236 /* This array holds the chars that only start a comment at the beginning of
237 a line. If the line seems to have the form '# 123 filename'
238 .line and .file directives will appear in the pre-processed output */
239 /* Note that input_file.c hand checks for '#' at the beginning of the
240 first line of the input file. This is because the compiler outputs
241 #NO_APP at the beginning of its output. */
242 /* Also note that C style comments are always supported. */
243 const char line_comment_chars
[] = "#";
245 /* This array holds machine specific line separator characters. */
246 const char line_separator_chars
[] = "";
248 /* Chars that can be used to separate mant from exp in floating point nums */
249 const char EXP_CHARS
[] = "eE";
251 /* Chars that mean this number is a floating point constant */
254 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
256 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
257 changed in read.c . Ideally it shouldn't have to know about it at all,
258 but nothing is ideal around here.
261 static char *insn_error
;
263 static int auto_align
= 1;
265 /* When outputting SVR4 PIC code, the assembler needs to know the
266 offset in the stack frame from which to restore the $gp register.
267 This is set by the .cprestore pseudo-op, and saved in this
269 static offsetT mips_cprestore_offset
= -1;
271 /* This is the register which holds the stack frame, as set by the
272 .frame pseudo-op. This is needed to implement .cprestore. */
273 static int mips_frame_reg
= SP
;
275 /* To output NOP instructions correctly, we need to keep information
276 about the previous two instructions. */
278 /* Whether we are optimizing. The default value of 2 means to remove
279 unneeded NOPs and swap branch instructions when possible. A value
280 of 1 means to not swap branches. A value of 0 means to always
282 static int mips_optimize
= 2;
284 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
285 equivalent to seeing no -g option at all. */
286 static int mips_debug
= 0;
288 /* The previous instruction. */
289 static struct mips_cl_insn prev_insn
;
291 /* The instruction before prev_insn. */
292 static struct mips_cl_insn prev_prev_insn
;
294 /* If we don't want information for prev_insn or prev_prev_insn, we
295 point the insn_mo field at this dummy integer. */
296 static const struct mips_opcode dummy_opcode
= { 0 };
298 /* Non-zero if prev_insn is valid. */
299 static int prev_insn_valid
;
301 /* The frag for the previous instruction. */
302 static struct frag
*prev_insn_frag
;
304 /* The offset into prev_insn_frag for the previous instruction. */
305 static long prev_insn_where
;
307 /* The reloc type for the previous instruction, if any. */
308 static bfd_reloc_code_real_type prev_insn_reloc_type
;
310 /* The reloc for the previous instruction, if any. */
311 static fixS
*prev_insn_fixp
;
313 /* Non-zero if the previous instruction was in a delay slot. */
314 static int prev_insn_is_delay_slot
;
316 /* Non-zero if the previous instruction was in a .set noreorder. */
317 static int prev_insn_unreordered
;
319 /* Non-zero if the previous instruction uses an extend opcode (if
321 static int prev_insn_extended
;
323 /* Non-zero if the previous previous instruction was in a .set
325 static int prev_prev_insn_unreordered
;
327 /* For ECOFF and ELF, relocations against symbols are done in two
328 parts, with a HI relocation and a LO relocation. Each relocation
329 has only 16 bits of space to store an addend. This means that in
330 order for the linker to handle carries correctly, it must be able
331 to locate both the HI and the LO relocation. This means that the
332 relocations must appear in order in the relocation table.
334 In order to implement this, we keep track of each unmatched HI
335 relocation. We then sort them so that they immediately precede the
336 corresponding LO relocation. */
341 struct mips_hi_fixup
*next
;
344 /* The section this fixup is in. */
348 /* The list of unmatched HI relocs. */
350 static struct mips_hi_fixup
*mips_hi_fixup_list
;
352 /* Map normal MIPS register numbers to mips16 register numbers. */
354 #define X ILLEGAL_REG
355 static const int mips32_to_16_reg_map
[] =
357 X
, X
, 2, 3, 4, 5, 6, 7,
358 X
, X
, X
, X
, X
, X
, X
, X
,
359 0, 1, X
, X
, X
, X
, X
, X
,
360 X
, X
, X
, X
, X
, X
, X
, X
364 /* Map mips16 register numbers to normal MIPS register numbers. */
366 static const int mips16_to_32_reg_map
[] =
368 16, 17, 2, 3, 4, 5, 6, 7
371 /* Since the MIPS does not have multiple forms of PC relative
372 instructions, we do not have to do relaxing as is done on other
373 platforms. However, we do have to handle GP relative addressing
374 correctly, which turns out to be a similar problem.
376 Every macro that refers to a symbol can occur in (at least) two
377 forms, one with GP relative addressing and one without. For
378 example, loading a global variable into a register generally uses
379 a macro instruction like this:
381 If i can be addressed off the GP register (this is true if it is in
382 the .sbss or .sdata section, or if it is known to be smaller than
383 the -G argument) this will generate the following instruction:
385 This instruction will use a GPREL reloc. If i can not be addressed
386 off the GP register, the following instruction sequence will be used:
389 In this case the first instruction will have a HI16 reloc, and the
390 second reloc will have a LO16 reloc. Both relocs will be against
393 The issue here is that we may not know whether i is GP addressable
394 until after we see the instruction that uses it. Therefore, we
395 want to be able to choose the final instruction sequence only at
396 the end of the assembly. This is similar to the way other
397 platforms choose the size of a PC relative instruction only at the
400 When generating position independent code we do not use GP
401 addressing in quite the same way, but the issue still arises as
402 external symbols and local symbols must be handled differently.
404 We handle these issues by actually generating both possible
405 instruction sequences. The longer one is put in a frag_var with
406 type rs_machine_dependent. We encode what to do with the frag in
407 the subtype field. We encode (1) the number of existing bytes to
408 replace, (2) the number of new bytes to use, (3) the offset from
409 the start of the existing bytes to the first reloc we must generate
410 (that is, the offset is applied from the start of the existing
411 bytes after they are replaced by the new bytes, if any), (4) the
412 offset from the start of the existing bytes to the second reloc,
413 (5) whether a third reloc is needed (the third reloc is always four
414 bytes after the second reloc), and (6) whether to warn if this
415 variant is used (this is sometimes needed if .set nomacro or .set
416 noat is in effect). All these numbers are reasonably small.
418 Generating two instruction sequences must be handled carefully to
419 ensure that delay slots are handled correctly. Fortunately, there
420 are a limited number of cases. When the second instruction
421 sequence is generated, append_insn is directed to maintain the
422 existing delay slot information, so it continues to apply to any
423 code after the second instruction sequence. This means that the
424 second instruction sequence must not impose any requirements not
425 required by the first instruction sequence.
427 These variant frags are then handled in functions called by the
428 machine independent code. md_estimate_size_before_relax returns
429 the final size of the frag. md_convert_frag sets up the final form
430 of the frag. tc_gen_reloc adjust the first reloc and adds a second
432 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
436 | (((reloc1) + 64) << 9) \
437 | (((reloc2) + 64) << 2) \
438 | ((reloc3) ? (1 << 1) : 0) \
440 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
441 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
442 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
443 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
444 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
445 #define RELAX_WARN(i) ((i) & 1)
447 /* For mips16 code, we use an entirely different form of relaxation.
448 mips16 supports two versions of most instructions which take
449 immediate values: a small one which takes some small value, and a
450 larger one which takes a 16 bit value. Since branches also follow
451 this pattern, relaxing these values is required.
453 We can assemble both mips16 and normal MIPS code in a single
454 object. Therefore, we need to support this type of relaxation at
455 the same time that we support the relaxation described above. We
456 use the high bit of the subtype field to distinguish these cases.
458 The information we store for this type of relaxation is the
459 argument code found in the opcode file for this relocation, whether
460 the user explicitly requested a small or extended form, and whether
461 the relocation is in a jump or jal delay slot. That tells us the
462 size of the value, and how it should be stored. We also store
463 whether the fragment is considered to be extended or not. We also
464 store whether this is known to be a branch to a different section,
465 whether we have tried to relax this frag yet, and whether we have
466 ever extended a PC relative fragment because of a shift count. */
467 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
470 | ((small) ? 0x100 : 0) \
471 | ((ext) ? 0x200 : 0) \
472 | ((dslot) ? 0x400 : 0) \
473 | ((jal_dslot) ? 0x800 : 0))
474 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
475 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
476 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
477 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
478 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
479 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
480 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
481 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
482 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
483 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
484 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
485 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
487 /* Prototypes for static functions. */
490 #define internalError() \
491 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
493 #define internalError() as_fatal ("MIPS internal Error");
496 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
498 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
499 unsigned int reg
, enum mips_regclass
class));
500 static int reg_needs_delay
PARAMS ((int));
501 static void append_insn
PARAMS ((char *place
,
502 struct mips_cl_insn
* ip
,
504 bfd_reloc_code_real_type r
,
506 static void mips_no_prev_insn
PARAMS ((void));
507 static void mips_emit_delays
PARAMS ((boolean
));
509 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
510 const char *name
, const char *fmt
,
513 static void macro_build ();
515 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
516 const char *, const char *,
518 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
519 expressionS
* ep
, int regnum
));
520 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
521 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
523 static void load_register
PARAMS ((int *, int, expressionS
*, int));
524 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
525 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
526 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
527 #ifdef LOSING_COMPILER
528 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
530 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
531 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
532 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
533 boolean
, boolean
, unsigned long *,
534 boolean
*, unsigned short *));
535 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
536 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
537 static symbolS
*get_symbol
PARAMS ((void));
538 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
539 static void s_align
PARAMS ((int));
540 static void s_change_sec
PARAMS ((int));
541 static void s_cons
PARAMS ((int));
542 static void s_float_cons
PARAMS ((int));
543 static void s_mips_globl
PARAMS ((int));
544 static void s_option
PARAMS ((int));
545 static void s_mipsset
PARAMS ((int));
546 static void s_abicalls
PARAMS ((int));
547 static void s_cpload
PARAMS ((int));
548 static void s_cprestore
PARAMS ((int));
549 static void s_gpword
PARAMS ((int));
550 static void s_cpadd
PARAMS ((int));
551 static void md_obj_begin
PARAMS ((void));
552 static void md_obj_end
PARAMS ((void));
553 static long get_number
PARAMS ((void));
554 static void s_ent
PARAMS ((int));
555 static void s_mipsend
PARAMS ((int));
556 static void s_file
PARAMS ((int));
557 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
561 The following pseudo-ops from the Kane and Heinrich MIPS book
562 should be defined here, but are currently unsupported: .alias,
563 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
565 The following pseudo-ops from the Kane and Heinrich MIPS book are
566 specific to the type of debugging information being generated, and
567 should be defined by the object format: .aent, .begin, .bend,
568 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
571 The following pseudo-ops from the Kane and Heinrich MIPS book are
572 not MIPS CPU specific, but are also not specific to the object file
573 format. This file is probably the best place to define them, but
574 they are not currently supported: .asm0, .endr, .lab, .repeat,
575 .struct, .weakext. */
577 static const pseudo_typeS mips_pseudo_table
[] =
579 /* MIPS specific pseudo-ops. */
580 {"option", s_option
, 0},
581 {"set", s_mipsset
, 0},
582 {"rdata", s_change_sec
, 'r'},
583 {"sdata", s_change_sec
, 's'},
584 {"livereg", s_ignore
, 0},
585 {"abicalls", s_abicalls
, 0},
586 {"cpload", s_cpload
, 0},
587 {"cprestore", s_cprestore
, 0},
588 {"gpword", s_gpword
, 0},
589 {"cpadd", s_cpadd
, 0},
591 /* Relatively generic pseudo-ops that happen to be used on MIPS
593 {"asciiz", stringer
, 1},
594 {"bss", s_change_sec
, 'b'},
597 {"dword", s_cons
, 3},
599 /* These pseudo-ops are defined in read.c, but must be overridden
600 here for one reason or another. */
601 {"align", s_align
, 0},
603 {"data", s_change_sec
, 'd'},
604 {"double", s_float_cons
, 'd'},
605 {"float", s_float_cons
, 'f'},
606 {"globl", s_mips_globl
, 0},
607 {"global", s_mips_globl
, 0},
608 {"hword", s_cons
, 1},
613 {"short", s_cons
, 1},
614 {"single", s_float_cons
, 'f'},
615 {"text", s_change_sec
, 't'},
620 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
621 /* These pseudo-ops should be defined by the object file format.
622 However, a.out doesn't support them, so we have versions here. */
624 {"bgnb", s_ignore
, 0},
625 {"end", s_mipsend
, 0},
626 {"endb", s_ignore
, 0},
629 {"fmask", s_ignore
, 'F'},
630 {"frame", s_ignore
, 0},
631 {"loc", s_ignore
, 0},
632 {"mask", s_ignore
, 'R'},
633 {"verstamp", s_ignore
, 0},
637 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
642 pop_insert (mips_pseudo_table
);
643 if (! ECOFF_DEBUGGING
)
644 pop_insert (mips_nonecoff_pseudo_table
);
647 /* Symbols labelling the current insn. */
649 struct insn_label_list
651 struct insn_label_list
*next
;
655 static struct insn_label_list
*insn_labels
;
656 static struct insn_label_list
*free_insn_labels
;
658 static void mips_clear_insn_labels
PARAMS ((void));
661 mips_clear_insn_labels ()
663 register struct insn_label_list
**pl
;
665 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
671 static char *expr_end
;
673 /* Expressions which appear in instructions. These are set by
676 static expressionS imm_expr
;
677 static expressionS offset_expr
;
679 /* Relocs associated with imm_expr and offset_expr. */
681 static bfd_reloc_code_real_type imm_reloc
;
682 static bfd_reloc_code_real_type offset_reloc
;
684 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
686 static boolean imm_unmatched_hi
;
688 /* These are set by mips16_ip if an explicit extension is used. */
690 static boolean mips16_small
, mips16_ext
;
693 * This function is called once, at assembler startup time. It should
694 * set up all the tables, etc. that the MD part of the assembler will need.
700 register const char *retval
= NULL
;
701 register unsigned int i
= 0;
709 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
711 a
= xmalloc (sizeof TARGET_CPU
);
712 strcpy (a
, TARGET_CPU
);
713 a
[(sizeof TARGET_CPU
) - 3] = '\0';
717 if (strcmp (cpu
, "mips") == 0)
723 else if (strcmp (cpu
, "r6000") == 0
724 || strcmp (cpu
, "mips2") == 0)
730 else if (strcmp (cpu
, "mips64") == 0
731 || strcmp (cpu
, "r4000") == 0
732 || strcmp (cpu
, "mips3") == 0)
738 else if (strcmp (cpu
, "r4400") == 0)
744 else if (strcmp (cpu
, "mips64orion") == 0
745 || strcmp (cpu
, "r4600") == 0)
751 else if (strcmp (cpu
, "r4650") == 0)
759 else if (strcmp (cpu
, "mips64vr4300") == 0)
765 else if (strcmp (cpu
, "mips64vr4100") == 0)
773 else if (strcmp (cpu
, "r4010") == 0)
781 else if (strcmp (cpu
, "r5000") == 0
782 || strcmp (cpu
, "mips64vr5000") == 0)
788 /* start-sanitize-r5900 */
789 else if (strcmp (cpu
, "r5900") == 0
790 || strcmp (cpu
, "mips64vr5900") == 0
791 || strcmp (cpu
, "mips64vr5900el") == 0)
799 /* end-sanitize-r5900 */
800 else if (strcmp (cpu
, "r8000") == 0
801 || strcmp (cpu
, "mips4") == 0)
807 else if (strcmp (cpu
, "r10000") == 0)
813 else if (strcmp (cpu
, "mips16") == 0)
817 mips_cpu
= 0; /* FIXME */
832 if (strncmp (TARGET_CPU
, "mips16", sizeof "mips16" - 1) == 0)
847 /* start-sanitize-r5900 */
850 /* end-sanitize-r5900 */
852 if (mips_4010
|| mips_4100
|| mips_cpu
== 4300)
857 if (mips_cpu
== 4300)
862 if (mips_isa
< 2 && mips_trap
)
863 as_bad ("trap exception not supported at ISA 1");
868 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
871 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
874 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
877 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
881 as_warn ("Could not set architecture and machine");
883 file_mips_isa
= mips_isa
;
885 op_hash
= hash_new ();
887 for (i
= 0; i
< NUMOPCODES
;)
889 const char *name
= mips_opcodes
[i
].name
;
891 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
894 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
895 mips_opcodes
[i
].name
, retval
);
896 as_fatal ("Broken assembler. No assembly attempted.");
900 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
901 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
902 != mips_opcodes
[i
].match
))
904 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
905 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
906 as_fatal ("Broken assembler. No assembly attempted.");
910 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
913 mips16_op_hash
= hash_new ();
916 while (i
< bfd_mips16_num_opcodes
)
918 const char *name
= mips16_opcodes
[i
].name
;
920 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
922 as_fatal ("internal error: can't hash `%s': %s\n",
923 mips16_opcodes
[i
].name
, retval
);
926 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
927 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
928 != mips16_opcodes
[i
].match
))
929 as_fatal ("internal error: bad opcode: `%s' \"%s\"\n",
930 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
933 while (i
< bfd_mips16_num_opcodes
934 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
937 /* We add all the general register names to the symbol table. This
938 helps us detect invalid uses of them. */
939 for (i
= 0; i
< 32; i
++)
943 sprintf (buf
, "$%d", i
);
944 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
945 &zero_address_frag
));
947 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
948 &zero_address_frag
));
949 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
950 &zero_address_frag
));
951 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
952 &zero_address_frag
));
953 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
954 &zero_address_frag
));
955 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
956 &zero_address_frag
));
957 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
958 &zero_address_frag
));
959 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
960 &zero_address_frag
));
962 mips_no_prev_insn ();
970 /* set the default alignment for the text section (2**2) */
971 record_alignment (text_section
, 2);
973 if (USE_GLOBAL_POINTER_OPT
)
974 bfd_set_gp_size (stdoutput
, g_switch_value
);
976 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
978 /* On a native system, sections must be aligned to 16 byte
979 boundaries. When configured for an embedded ELF target, we
981 if (strcmp (TARGET_OS
, "elf") != 0)
983 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
984 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
985 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
988 /* Create a .reginfo section for register masks and a .mdebug
989 section for debugging information. */
999 /* The ABI says this section should be loaded so that the
1000 running program can access it. However, we don't load it
1001 if we are configured for an embedded target */
1002 flags
= SEC_READONLY
| SEC_DATA
;
1003 if (strcmp (TARGET_OS
, "elf") != 0)
1004 flags
|= SEC_ALLOC
| SEC_LOAD
;
1008 sec
= subseg_new (".reginfo", (subsegT
) 0);
1011 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1012 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1015 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1020 /* The 64-bit ABI uses a .MIPS.options section rather than
1021 .reginfo section. */
1022 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1023 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1024 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
1027 /* Set up the option header. */
1029 Elf_Internal_Options opthdr
;
1032 opthdr
.kind
= ODK_REGINFO
;
1033 opthdr
.size
= (sizeof (Elf_External_Options
)
1034 + sizeof (Elf64_External_RegInfo
));
1037 f
= frag_more (sizeof (Elf_External_Options
));
1038 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1039 (Elf_External_Options
*) f
);
1041 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1046 if (ECOFF_DEBUGGING
)
1048 sec
= subseg_new (".mdebug", (subsegT
) 0);
1049 (void) bfd_set_section_flags (stdoutput
, sec
,
1050 SEC_HAS_CONTENTS
| SEC_READONLY
);
1051 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1054 subseg_set (seg
, subseg
);
1058 if (! ECOFF_DEBUGGING
)
1065 if (! ECOFF_DEBUGGING
)
1073 struct mips_cl_insn insn
;
1075 imm_expr
.X_op
= O_absent
;
1076 imm_reloc
= BFD_RELOC_UNUSED
;
1077 imm_unmatched_hi
= false;
1078 offset_expr
.X_op
= O_absent
;
1079 offset_reloc
= BFD_RELOC_UNUSED
;
1082 mips16_ip (str
, &insn
);
1084 mips_ip (str
, &insn
);
1088 as_bad ("%s `%s'", insn_error
, str
);
1092 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1095 mips16_macro (&insn
);
1101 if (imm_expr
.X_op
!= O_absent
)
1102 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1104 else if (offset_expr
.X_op
!= O_absent
)
1105 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1107 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
1111 /* See whether instruction IP reads register REG. CLASS is the type
1115 insn_uses_reg (ip
, reg
, class)
1116 struct mips_cl_insn
*ip
;
1118 enum mips_regclass
class;
1120 if (class == MIPS16_REG
)
1123 reg
= mips16_to_32_reg_map
[reg
];
1124 class = MIPS_GR_REG
;
1127 /* Don't report on general register 0, since it never changes. */
1128 if (class == MIPS_GR_REG
&& reg
== 0)
1131 if (class == MIPS_FP_REG
)
1134 /* If we are called with either $f0 or $f1, we must check $f0.
1135 This is not optimal, because it will introduce an unnecessary
1136 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1137 need to distinguish reading both $f0 and $f1 or just one of
1138 them. Note that we don't have to check the other way,
1139 because there is no instruction that sets both $f0 and $f1
1140 and requires a delay. */
1141 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1142 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
1143 == (reg
&~ (unsigned) 1)))
1145 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1146 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
1147 == (reg
&~ (unsigned) 1)))
1152 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1153 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1155 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1156 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1161 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1162 && ((ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
) == reg
)
1164 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1165 && ((ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
) == reg
)
1167 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1168 && ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1169 & MIPS16OP_MASK_MOVE32Z
) == reg
)
1171 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1173 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1175 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1177 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1178 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1179 & MIPS16OP_MASK_REGR32
) == reg
)
1186 /* This function returns true if modifying a register requires a
1190 reg_needs_delay (reg
)
1193 unsigned long prev_pinfo
;
1195 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1196 if (! mips_noreorder
1198 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1200 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1202 /* A load from a coprocessor or from memory. All load
1203 delays delay the use of general register rt for one
1204 instruction on the r3000. The r6000 and r4000 use
1206 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1207 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1214 /* Output an instruction. PLACE is where to put the instruction; if
1215 it is NULL, this uses frag_more to get room. IP is the instruction
1216 information. ADDRESS_EXPR is an operand of the instruction to be
1217 used with RELOC_TYPE. */
1220 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1222 struct mips_cl_insn
*ip
;
1223 expressionS
*address_expr
;
1224 bfd_reloc_code_real_type reloc_type
;
1225 boolean unmatched_hi
;
1227 register unsigned long prev_pinfo
, pinfo
;
1232 /* Mark instruction labels in mips16 mode. This permits the linker
1233 to handle them specially, such as generating jalx instructions
1234 when needed. We also make them odd for the duration of the
1235 assembly, in order to generate the right sort of code. We will
1236 make them even in the adjust_symtab routine, while leaving them
1237 marked. This is convenient for the debugger and the
1238 disassembler. The linker knows to make them odd again. */
1241 struct insn_label_list
*l
;
1243 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1246 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1247 S_SET_OTHER (l
->label
, STO_MIPS16
);
1249 ++l
->label
->sy_value
.X_add_number
;
1253 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1254 pinfo
= ip
->insn_mo
->pinfo
;
1256 if (place
== NULL
&& ! mips_noreorder
)
1258 /* If the previous insn required any delay slots, see if we need
1259 to insert a NOP or two. There are eight kinds of possible
1260 hazards, of which an instruction can have at most one type.
1261 (1) a load from memory delay
1262 (2) a load from a coprocessor delay
1263 (3) an unconditional branch delay
1264 (4) a conditional branch delay
1265 (5) a move to coprocessor register delay
1266 (6) a load coprocessor register from memory delay
1267 (7) a coprocessor condition code delay
1268 (8) a HI/LO special register delay
1270 There are a lot of optimizations we could do that we don't.
1271 In particular, we do not, in general, reorder instructions.
1272 If you use gcc with optimization, it will reorder
1273 instructions and generally do much more optimization then we
1274 do here; repeating all that work in the assembler would only
1275 benefit hand written assembly code, and does not seem worth
1278 /* This is how a NOP is emitted. */
1279 #define emit_nop() \
1281 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1282 : md_number_to_chars (frag_more (4), 0, 4))
1284 /* The previous insn might require a delay slot, depending upon
1285 the contents of the current insn. */
1288 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1289 && ! cop_interlocks
)
1291 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1293 /* A load from a coprocessor or from memory. All load
1294 delays delay the use of general register rt for one
1295 instruction on the r3000. The r6000 and r4000 use
1297 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1298 if (mips_optimize
== 0
1299 || insn_uses_reg (ip
,
1300 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1307 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1308 && ! cop_interlocks
)
1310 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1312 /* A generic coprocessor delay. The previous instruction
1313 modified a coprocessor general or control register. If
1314 it modified a control register, we need to avoid any
1315 coprocessor instruction (this is probably not always
1316 required, but it sometimes is). If it modified a general
1317 register, we avoid using that register.
1319 On the r6000 and r4000 loading a coprocessor register
1320 from memory is interlocked, and does not require a delay.
1322 This case is not handled very well. There is no special
1323 knowledge of CP0 handling, and the coprocessors other
1324 than the floating point unit are not distinguished at
1326 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1328 if (mips_optimize
== 0
1329 || insn_uses_reg (ip
,
1330 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1335 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1337 if (mips_optimize
== 0
1338 || insn_uses_reg (ip
,
1339 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1346 /* We don't know exactly what the previous instruction
1347 does. If the current instruction uses a coprocessor
1348 register, we must insert a NOP. If previous
1349 instruction may set the condition codes, and the
1350 current instruction uses them, we must insert two
1352 if (mips_optimize
== 0
1353 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1354 && (pinfo
& INSN_READ_COND_CODE
)))
1356 else if (pinfo
& INSN_COP
)
1362 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1363 && ! cop_interlocks
)
1365 /* The previous instruction sets the coprocessor condition
1366 codes, but does not require a general coprocessor delay
1367 (this means it is a floating point comparison
1368 instruction). If this instruction uses the condition
1369 codes, we need to insert a single NOP. */
1370 if (mips_optimize
== 0
1371 || (pinfo
& INSN_READ_COND_CODE
))
1374 else if (prev_pinfo
& INSN_READ_LO
)
1376 /* The previous instruction reads the LO register; if the
1377 current instruction writes to the LO register, we must
1378 insert two NOPS. Some newer processors have interlocks. */
1380 && (mips_optimize
== 0
1381 || (pinfo
& INSN_WRITE_LO
)))
1384 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1386 /* The previous instruction reads the HI register; if the
1387 current instruction writes to the HI register, we must
1388 insert a NOP. Some newer processors have interlocks. */
1390 && (mips_optimize
== 0
1391 || (pinfo
& INSN_WRITE_HI
)))
1395 /* There are two cases which require two intervening
1396 instructions: 1) setting the condition codes using a move to
1397 coprocessor instruction which requires a general coprocessor
1398 delay and then reading the condition codes 2) reading the HI
1399 or LO register and then writing to it (except on processors
1400 which have interlocks). If we are not already emitting a NOP
1401 instruction, we must check for these cases compared to the
1402 instruction previous to the previous instruction. */
1406 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1407 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1408 && (pinfo
& INSN_READ_COND_CODE
)
1409 && ! cop_interlocks
)
1410 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1411 && (pinfo
& INSN_WRITE_LO
)
1413 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1414 && (pinfo
& INSN_WRITE_HI
)
1418 /* If we are being given a nop instruction, don't bother with
1419 one of the nops we would otherwise output. This will only
1420 happen when a nop instruction is used with mips_optimize set
1422 if (nops
> 0 && ip
->insn_opcode
== (mips16
? 0x6500 : 0))
1425 /* Now emit the right number of NOP instructions. */
1429 unsigned long old_frag_offset
;
1431 struct insn_label_list
*l
;
1433 old_frag
= frag_now
;
1434 old_frag_offset
= frag_now_fix ();
1436 for (i
= 0; i
< nops
; i
++)
1441 listing_prev_line ();
1442 /* We may be at the start of a variant frag. In case we
1443 are, make sure there is enough space for the frag
1444 after the frags created by listing_prev_line. The
1445 argument to frag_grow here must be at least as large
1446 as the argument to all other calls to frag_grow in
1447 this file. We don't have to worry about being in the
1448 middle of a variant frag, because the variants insert
1449 all needed nop instructions themselves. */
1453 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1455 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1456 l
->label
->sy_frag
= frag_now
;
1457 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
1458 /* mips16 text labels are stored as odd. */
1460 ++l
->label
->sy_value
.X_add_number
;
1463 #ifndef NO_ECOFF_DEBUGGING
1464 if (ECOFF_DEBUGGING
)
1465 ecoff_fix_loc (old_frag
, old_frag_offset
);
1470 if (reloc_type
> BFD_RELOC_UNUSED
)
1472 /* We need to set up a variant frag. */
1473 assert (mips16
&& address_expr
!= NULL
);
1474 f
= frag_var (rs_machine_dependent
, 4, 0,
1475 RELAX_MIPS16_ENCODE (reloc_type
- BFD_RELOC_UNUSED
,
1476 mips16_small
, mips16_ext
,
1478 & INSN_UNCOND_BRANCH_DELAY
),
1479 (prev_insn_reloc_type
1480 == BFD_RELOC_MIPS16_JMP
)),
1481 make_expr_symbol (address_expr
), (long) 0,
1484 else if (place
!= NULL
)
1486 else if (mips16
&& ! ip
->use_extend
&& reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1488 /* Make sure there is enough room to swap this instruction with
1489 a following jump instruction. */
1496 if (address_expr
!= NULL
&& reloc_type
< BFD_RELOC_UNUSED
)
1498 if (address_expr
->X_op
== O_constant
)
1503 ip
->insn_opcode
|= address_expr
->X_add_number
;
1506 case BFD_RELOC_LO16
:
1507 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1510 case BFD_RELOC_MIPS_JMP
:
1511 if ((address_expr
->X_add_number
& 3) != 0)
1512 as_bad ("jump to misaligned address (0x%lx)",
1513 (unsigned long) address_expr
->X_add_number
);
1514 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1517 case BFD_RELOC_MIPS16_JMP
:
1518 if ((address_expr
->X_add_number
& 3) != 0)
1519 as_bad ("jump to misaligned address (0x%lx)",
1520 (unsigned long) address_expr
->X_add_number
);
1522 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1523 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1524 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1527 case BFD_RELOC_16_PCREL_S2
:
1537 /* Don't generate a reloc if we are writing into a variant
1541 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1543 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1547 struct mips_hi_fixup
*hi_fixup
;
1549 assert (reloc_type
== BFD_RELOC_HI16_S
);
1550 hi_fixup
= ((struct mips_hi_fixup
*)
1551 xmalloc (sizeof (struct mips_hi_fixup
)));
1552 hi_fixup
->fixp
= fixp
;
1553 hi_fixup
->seg
= now_seg
;
1554 hi_fixup
->next
= mips_hi_fixup_list
;
1555 mips_hi_fixup_list
= hi_fixup
;
1562 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1563 else if (reloc_type
== BFD_RELOC_MIPS16_JMP
)
1565 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
1566 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
1572 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
1575 md_number_to_chars (f
, ip
->insn_opcode
, 2);
1578 /* Update the register mask information. */
1581 if (pinfo
& INSN_WRITE_GPR_D
)
1582 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1583 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1584 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1585 if (pinfo
& INSN_READ_GPR_S
)
1586 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1587 if (pinfo
& INSN_WRITE_GPR_31
)
1588 mips_gprmask
|= 1 << 31;
1589 if (pinfo
& INSN_WRITE_FPR_D
)
1590 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1591 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1592 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1593 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1594 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1595 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1596 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1597 if (pinfo
& INSN_COP
)
1599 /* We don't keep enough information to sort these cases out. */
1601 /* Never set the bit for $0, which is always zero. */
1602 mips_gprmask
&=~ 1 << 0;
1606 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
1607 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1608 & MIPS16OP_MASK_RX
);
1609 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
1610 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1611 & MIPS16OP_MASK_RY
);
1612 if (pinfo
& MIPS16_INSN_WRITE_Z
)
1613 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
1614 & MIPS16OP_MASK_RZ
);
1615 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
1616 mips_gprmask
|= 1 << TREG
;
1617 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
1618 mips_gprmask
|= 1 << SP
;
1619 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
1620 mips_gprmask
|= 1 << RA
;
1621 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1622 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
1623 if (pinfo
& MIPS16_INSN_READ_Z
)
1624 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1625 & MIPS16OP_MASK_MOVE32Z
);
1626 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
1627 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1628 & MIPS16OP_MASK_REGR32
);
1631 if (place
== NULL
&& ! mips_noreorder
)
1633 /* Filling the branch delay slot is more complex. We try to
1634 switch the branch with the previous instruction, which we can
1635 do if the previous instruction does not set up a condition
1636 that the branch tests and if the branch is not itself the
1637 target of any branch. */
1638 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1639 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1641 if (mips_optimize
< 2
1642 /* If we have seen .set volatile or .set nomove, don't
1645 /* If we had to emit any NOP instructions, then we
1646 already know we can not swap. */
1648 /* If we don't even know the previous insn, we can not
1650 || ! prev_insn_valid
1651 /* If the previous insn is already in a branch delay
1652 slot, then we can not swap. */
1653 || prev_insn_is_delay_slot
1654 /* If the previous previous insn was in a .set
1655 noreorder, we can't swap. Actually, the MIPS
1656 assembler will swap in this situation. However, gcc
1657 configured -with-gnu-as will generate code like
1663 in which we can not swap the bne and INSN. If gcc is
1664 not configured -with-gnu-as, it does not output the
1665 .set pseudo-ops. We don't have to check
1666 prev_insn_unreordered, because prev_insn_valid will
1667 be 0 in that case. We don't want to use
1668 prev_prev_insn_valid, because we do want to be able
1669 to swap at the start of a function. */
1670 || prev_prev_insn_unreordered
1671 /* If the branch is itself the target of a branch, we
1672 can not swap. We cheat on this; all we check for is
1673 whether there is a label on this instruction. If
1674 there are any branches to anything other than a
1675 label, users must use .set noreorder. */
1676 || insn_labels
!= NULL
1677 /* If the previous instruction is in a variant frag, we
1678 can not do the swap. This does not apply to the
1679 mips16, which uses variant frags for different
1682 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
1683 /* If the branch reads the condition codes, we don't
1684 even try to swap, because in the sequence
1689 we can not swap, and I don't feel like handling that
1693 && (pinfo
& INSN_READ_COND_CODE
))
1694 /* We can not swap with an instruction that requires a
1695 delay slot, becase the target of the branch might
1696 interfere with that instruction. */
1700 & (INSN_LOAD_COPROC_DELAY
1701 | INSN_COPROC_MOVE_DELAY
1702 | INSN_WRITE_COND_CODE
)))
1710 & (INSN_LOAD_MEMORY_DELAY
1711 | INSN_COPROC_MEMORY_DELAY
)))
1712 /* We can not swap with a branch instruction. */
1714 & (INSN_UNCOND_BRANCH_DELAY
1715 | INSN_COND_BRANCH_DELAY
1716 | INSN_COND_BRANCH_LIKELY
))
1717 /* We do not swap with a trap instruction, since it
1718 complicates trap handlers to have the trap
1719 instruction be in a delay slot. */
1720 || (prev_pinfo
& INSN_TRAP
)
1721 /* If the branch reads a register that the previous
1722 instruction sets, we can not swap. */
1724 && (prev_pinfo
& INSN_WRITE_GPR_T
)
1725 && insn_uses_reg (ip
,
1726 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1730 && (prev_pinfo
& INSN_WRITE_GPR_D
)
1731 && insn_uses_reg (ip
,
1732 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1736 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
1737 && insn_uses_reg (ip
,
1738 ((prev_insn
.insn_opcode
1740 & MIPS16OP_MASK_RX
),
1742 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
1743 && insn_uses_reg (ip
,
1744 ((prev_insn
.insn_opcode
1746 & MIPS16OP_MASK_RY
),
1748 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
1749 && insn_uses_reg (ip
,
1750 ((prev_insn
.insn_opcode
1752 & MIPS16OP_MASK_RZ
),
1754 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
1755 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
1756 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
1757 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
1758 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1759 && insn_uses_reg (ip
,
1760 MIPS16OP_EXTRACT_REG32R (prev_insn
.
1763 /* If the branch writes a register that the previous
1764 instruction sets, we can not swap (we know that
1765 branches write only to RD or to $31). */
1767 && (prev_pinfo
& INSN_WRITE_GPR_T
)
1768 && (((pinfo
& INSN_WRITE_GPR_D
)
1769 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1770 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1771 || ((pinfo
& INSN_WRITE_GPR_31
)
1772 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1776 && (prev_pinfo
& INSN_WRITE_GPR_D
)
1777 && (((pinfo
& INSN_WRITE_GPR_D
)
1778 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1779 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1780 || ((pinfo
& INSN_WRITE_GPR_31
)
1781 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1785 && (pinfo
& MIPS16_INSN_WRITE_31
)
1786 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
1787 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1788 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
1790 /* If the branch writes a register that the previous
1791 instruction reads, we can not swap (we know that
1792 branches only write to RD or to $31). */
1794 && (pinfo
& INSN_WRITE_GPR_D
)
1795 && insn_uses_reg (&prev_insn
,
1796 ((ip
->insn_opcode
>> OP_SH_RD
)
1800 && (pinfo
& INSN_WRITE_GPR_31
)
1801 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
1803 && (pinfo
& MIPS16_INSN_WRITE_31
)
1804 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
1805 /* If we are generating embedded PIC code, the branch
1806 might be expanded into a sequence which uses $at, so
1807 we can't swap with an instruction which reads it. */
1808 || (mips_pic
== EMBEDDED_PIC
1809 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
1810 /* If the previous previous instruction has a load
1811 delay, and sets a register that the branch reads, we
1815 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1817 && (prev_prev_insn
.insn_mo
->pinfo
1818 & INSN_LOAD_MEMORY_DELAY
)))
1819 && insn_uses_reg (ip
,
1820 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1823 /* If one instruction sets a condition code and the
1824 other one uses a condition code, we can not swap. */
1825 || ((pinfo
& INSN_READ_COND_CODE
)
1826 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
1827 || ((pinfo
& INSN_WRITE_COND_CODE
)
1828 && (prev_pinfo
& INSN_READ_COND_CODE
))
1829 /* If the previous instruction uses the PC, we can not
1832 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
1833 /* If the previous instruction was extended, we can not
1835 || (mips16
&& prev_insn_extended
)
1836 /* If the previous instruction had a fixup in mips16
1837 mode, we can not swap. This normally means that the
1838 previous instruction was a 4 byte branch anyhow. */
1839 || (mips16
&& prev_insn_fixp
))
1841 /* We could do even better for unconditional branches to
1842 portions of this object file; we could pick up the
1843 instruction at the destination, put it in the delay
1844 slot, and bump the destination address. */
1846 /* Update the previous insn information. */
1847 prev_prev_insn
= *ip
;
1848 prev_insn
.insn_mo
= &dummy_opcode
;
1852 /* It looks like we can actually do the swap. */
1858 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1859 memcpy (temp
, prev_f
, 4);
1860 memcpy (prev_f
, f
, 4);
1861 memcpy (f
, temp
, 4);
1864 prev_insn_fixp
->fx_frag
= frag_now
;
1865 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1869 fixp
->fx_frag
= prev_insn_frag
;
1870 fixp
->fx_where
= prev_insn_where
;
1873 else if (reloc_type
> BFD_RELOC_UNUSED
)
1878 /* We are in mips16 mode, and we have just created a
1879 variant frag. We need to extract the old
1880 instruction from the end of the previous frag,
1881 and add it to a new frag. */
1882 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1883 memcpy (temp
, prev_f
, 2);
1884 prev_insn_frag
->fr_fix
-= 2;
1885 if (prev_insn_frag
->fr_type
== rs_machine_dependent
)
1887 assert (prev_insn_where
== prev_insn_frag
->fr_fix
);
1888 memcpy (prev_f
, prev_f
+ 2, 2);
1890 memcpy (frag_more (2), temp
, 2);
1897 assert (prev_insn_fixp
== NULL
);
1898 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1899 memcpy (temp
, prev_f
, 2);
1900 memcpy (prev_f
, f
, 2);
1901 if (reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1902 memcpy (f
, temp
, 2);
1905 memcpy (f
, f
+ 2, 2);
1906 memcpy (f
+ 2, temp
, 2);
1910 fixp
->fx_frag
= prev_insn_frag
;
1911 fixp
->fx_where
= prev_insn_where
;
1915 /* Update the previous insn information; leave prev_insn
1917 prev_prev_insn
= *ip
;
1919 prev_insn_is_delay_slot
= 1;
1921 /* If that was an unconditional branch, forget the previous
1922 insn information. */
1923 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1925 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1926 prev_insn
.insn_mo
= &dummy_opcode
;
1929 prev_insn_fixp
= NULL
;
1930 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
1931 prev_insn_extended
= 0;
1933 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1935 /* We don't yet optimize a branch likely. What we should do
1936 is look at the target, copy the instruction found there
1937 into the delay slot, and increment the branch to jump to
1938 the next instruction. */
1940 /* Update the previous insn information. */
1941 prev_prev_insn
= *ip
;
1942 prev_insn
.insn_mo
= &dummy_opcode
;
1943 prev_insn_fixp
= NULL
;
1944 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
1945 prev_insn_extended
= 0;
1949 /* Update the previous insn information. */
1951 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1953 prev_prev_insn
= prev_insn
;
1956 /* Any time we see a branch, we always fill the delay slot
1957 immediately; since this insn is not a branch, we know it
1958 is not in a delay slot. */
1959 prev_insn_is_delay_slot
= 0;
1961 prev_insn_fixp
= fixp
;
1962 prev_insn_reloc_type
= reloc_type
;
1964 prev_insn_extended
= (ip
->use_extend
1965 || reloc_type
> BFD_RELOC_UNUSED
);
1968 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1969 prev_insn_unreordered
= 0;
1970 prev_insn_frag
= frag_now
;
1971 prev_insn_where
= f
- frag_now
->fr_literal
;
1972 prev_insn_valid
= 1;
1974 else if (place
== NULL
)
1976 /* We need to record a bit of information even when we are not
1977 reordering, in order to determine the base address for mips16
1978 PC relative relocs. */
1980 prev_insn_reloc_type
= reloc_type
;
1983 /* We just output an insn, so the next one doesn't have a label. */
1984 mips_clear_insn_labels ();
1987 /* This function forgets that there was any previous instruction or
1991 mips_no_prev_insn ()
1993 prev_insn
.insn_mo
= &dummy_opcode
;
1994 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1995 prev_insn_valid
= 0;
1996 prev_insn_is_delay_slot
= 0;
1997 prev_insn_unreordered
= 0;
1998 prev_insn_extended
= 0;
1999 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2000 prev_prev_insn_unreordered
= 0;
2001 mips_clear_insn_labels ();
2004 /* This function must be called whenever we turn on noreorder or emit
2005 something other than instructions. It inserts any NOPS which might
2006 be needed by the previous instruction, and clears the information
2007 kept for the previous instructions. The INSNS parameter is true if
2008 instructions are to follow. */
2011 mips_emit_delays (insns
)
2014 if (! mips_noreorder
)
2021 && (! cop_interlocks
2022 && (prev_insn
.insn_mo
->pinfo
2023 & (INSN_LOAD_COPROC_DELAY
2024 | INSN_COPROC_MOVE_DELAY
2025 | INSN_WRITE_COND_CODE
))))
2027 && (prev_insn
.insn_mo
->pinfo
2032 && (prev_insn
.insn_mo
->pinfo
2033 & (INSN_LOAD_MEMORY_DELAY
2034 | INSN_COPROC_MEMORY_DELAY
))))
2039 && (! cop_interlocks
2040 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2042 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2043 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2048 && (! cop_interlocks
2049 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2051 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2052 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2056 struct insn_label_list
*l
;
2059 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2061 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2062 l
->label
->sy_frag
= frag_now
;
2063 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
2064 /* mips16 text labels are stored as odd. */
2066 ++l
->label
->sy_value
.X_add_number
;
2071 /* Mark instruction labels in mips16 mode. This permits the linker
2072 to handle them specially, such as generating jalx instructions
2073 when needed. We also make them odd for the duration of the
2074 assembly, in order to generate the right sort of code. We will
2075 make them even in the adjust_symtab routine, while leaving them
2076 marked. This is convenient for the debugger and the
2077 disassembler. The linker knows to make them odd again. */
2078 if (mips16
&& insns
)
2080 struct insn_label_list
*l
;
2082 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2085 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
2086 S_SET_OTHER (l
->label
, STO_MIPS16
);
2088 if ((l
->label
->sy_value
.X_add_number
& 1) == 0)
2089 ++l
->label
->sy_value
.X_add_number
;
2093 mips_no_prev_insn ();
2096 /* Build an instruction created by a macro expansion. This is passed
2097 a pointer to the count of instructions created so far, an
2098 expression, the name of the instruction to build, an operand format
2099 string, and corresponding arguments. */
2103 macro_build (char *place
,
2111 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2120 struct mips_cl_insn insn
;
2121 bfd_reloc_code_real_type r
;
2125 va_start (args
, fmt
);
2131 * If the macro is about to expand into a second instruction,
2132 * print a warning if needed. We need to pass ip as a parameter
2133 * to generate a better warning message here...
2135 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
2136 as_warn ("Macro instruction expanded into multiple instructions");
2139 *counter
+= 1; /* bump instruction counter */
2143 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2148 r
= BFD_RELOC_UNUSED
;
2149 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2150 assert (insn
.insn_mo
);
2151 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2153 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2154 || insn
.insn_mo
->pinfo
== INSN_MACRO
2155 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA2
2157 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA3
2159 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA4
2161 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4650
2163 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4010
2165 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4100
2167 /* start-sanitize-r5900 */
2168 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_5900
2170 /* end-sanitize-r5900 */
2174 assert (insn
.insn_mo
->name
);
2175 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2177 insn
.insn_opcode
= insn
.insn_mo
->match
;
2193 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2199 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2204 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2209 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2216 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2220 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2224 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2231 insn
.insn_opcode
|= va_arg (args
, int) << 21;
2237 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2238 assert (r
== BFD_RELOC_MIPS_GPREL
2239 || r
== BFD_RELOC_MIPS_LITERAL
2240 || r
== BFD_RELOC_LO16
2241 || r
== BFD_RELOC_MIPS_GOT16
2242 || r
== BFD_RELOC_MIPS_CALL16
2243 || r
== BFD_RELOC_MIPS_GOT_LO16
2244 || r
== BFD_RELOC_MIPS_CALL_LO16
2245 || (ep
->X_op
== O_subtract
2246 && now_seg
== text_section
2247 && r
== BFD_RELOC_PCREL_LO16
));
2251 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2253 && (ep
->X_op
== O_constant
2254 || (ep
->X_op
== O_symbol
2255 && (r
== BFD_RELOC_HI16_S
2256 || r
== BFD_RELOC_HI16
2257 || r
== BFD_RELOC_MIPS_GOT_HI16
2258 || r
== BFD_RELOC_MIPS_CALL_HI16
))
2259 || (ep
->X_op
== O_subtract
2260 && now_seg
== text_section
2261 && r
== BFD_RELOC_PCREL_HI16_S
)));
2262 if (ep
->X_op
== O_constant
)
2264 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
2266 r
= BFD_RELOC_UNUSED
;
2271 assert (ep
!= NULL
);
2273 * This allows macro() to pass an immediate expression for
2274 * creating short branches without creating a symbol.
2275 * Note that the expression still might come from the assembly
2276 * input, in which case the value is not checked for range nor
2277 * is a relocation entry generated (yuck).
2279 if (ep
->X_op
== O_constant
)
2281 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2285 r
= BFD_RELOC_16_PCREL_S2
;
2289 assert (ep
!= NULL
);
2290 r
= BFD_RELOC_MIPS_JMP
;
2299 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2301 append_insn (place
, &insn
, ep
, r
, false);
2305 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2313 struct mips_cl_insn insn
;
2314 bfd_reloc_code_real_type r
;
2316 r
= BFD_RELOC_UNUSED
;
2317 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2318 assert (insn
.insn_mo
);
2319 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2321 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2322 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2325 assert (insn
.insn_mo
->name
);
2326 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2329 insn
.insn_opcode
= insn
.insn_mo
->match
;
2330 insn
.use_extend
= false;
2349 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2354 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2358 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2362 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2372 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2379 regno
= va_arg (args
, int);
2380 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2381 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2402 assert (ep
!= NULL
);
2404 if (ep
->X_op
!= O_constant
)
2405 r
= BFD_RELOC_UNUSED
+ c
;
2408 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
2409 false, false, &insn
.insn_opcode
,
2410 &insn
.use_extend
, &insn
.extend
);
2412 r
= BFD_RELOC_UNUSED
;
2418 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
2425 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2427 append_insn (place
, &insn
, ep
, r
, false);
2431 * Generate a "lui" instruction.
2434 macro_build_lui (place
, counter
, ep
, regnum
)
2440 expressionS high_expr
;
2441 struct mips_cl_insn insn
;
2442 bfd_reloc_code_real_type r
;
2443 CONST
char *name
= "lui";
2444 CONST
char *fmt
= "t,u";
2452 high_expr
.X_op
= O_constant
;
2453 high_expr
.X_add_number
= ep
->X_add_number
;
2456 if (high_expr
.X_op
== O_constant
)
2458 /* we can compute the instruction now without a relocation entry */
2459 if (high_expr
.X_add_number
& 0x8000)
2460 high_expr
.X_add_number
+= 0x10000;
2461 high_expr
.X_add_number
=
2462 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
2463 r
= BFD_RELOC_UNUSED
;
2467 assert (ep
->X_op
== O_symbol
);
2468 /* _gp_disp is a special case, used from s_cpload. */
2469 assert (mips_pic
== NO_PIC
2470 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
2471 r
= BFD_RELOC_HI16_S
;
2475 * If the macro is about to expand into a second instruction,
2476 * print a warning if needed. We need to pass ip as a parameter
2477 * to generate a better warning message here...
2479 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
2480 as_warn ("Macro instruction expanded into multiple instructions");
2483 *counter
+= 1; /* bump instruction counter */
2485 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2486 assert (insn
.insn_mo
);
2487 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2488 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
2490 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
2491 if (r
== BFD_RELOC_UNUSED
)
2493 insn
.insn_opcode
|= high_expr
.X_add_number
;
2494 append_insn (place
, &insn
, NULL
, r
, false);
2497 append_insn (place
, &insn
, &high_expr
, r
, false);
2501 * Generates code to set the $at register to true (one)
2502 * if reg is less than the immediate expression.
2505 set_at (counter
, reg
, unsignedp
)
2510 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2511 macro_build ((char *) NULL
, counter
, &imm_expr
,
2512 unsignedp
? "sltiu" : "slti",
2513 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
2516 load_register (counter
, AT
, &imm_expr
, 0);
2517 macro_build ((char *) NULL
, counter
, NULL
,
2518 unsignedp
? "sltu" : "slt",
2519 "d,v,t", AT
, reg
, AT
);
2523 /* Warn if an expression is not a constant. */
2526 check_absolute_expr (ip
, ex
)
2527 struct mips_cl_insn
*ip
;
2530 if (ex
->X_op
!= O_constant
)
2531 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
2534 /* Count the leading zeroes by performing a binary chop. This is a
2535 bulky bit of source, but performance is a LOT better for the
2536 majority of values than a simple loop to count the bits:
2537 for (lcnt = 0; (lcnt < 32); lcnt++)
2538 if ((v) & (1 << (31 - lcnt)))
2540 However it is not code size friendly, and the gain will drop a bit
2541 on certain cached systems.
2543 #define COUNT_TOP_ZEROES(v) \
2544 (((v) & ~0xffff) == 0 \
2545 ? ((v) & ~0xff) == 0 \
2546 ? ((v) & ~0xf) == 0 \
2547 ? ((v) & ~0x3) == 0 \
2548 ? ((v) & ~0x1) == 0 \
2553 : ((v) & ~0x7) == 0 \
2556 : ((v) & ~0x3f) == 0 \
2557 ? ((v) & ~0x1f) == 0 \
2560 : ((v) & ~0x7f) == 0 \
2563 : ((v) & ~0xfff) == 0 \
2564 ? ((v) & ~0x3ff) == 0 \
2565 ? ((v) & ~0x1ff) == 0 \
2568 : ((v) & ~0x7ff) == 0 \
2571 : ((v) & ~0x3fff) == 0 \
2572 ? ((v) & ~0x1fff) == 0 \
2575 : ((v) & ~0x7fff) == 0 \
2578 : ((v) & ~0xffffff) == 0 \
2579 ? ((v) & ~0xfffff) == 0 \
2580 ? ((v) & ~0x3ffff) == 0 \
2581 ? ((v) & ~0x1ffff) == 0 \
2584 : ((v) & ~0x7ffff) == 0 \
2587 : ((v) & ~0x3fffff) == 0 \
2588 ? ((v) & ~0x1fffff) == 0 \
2591 : ((v) & ~0x7fffff) == 0 \
2594 : ((v) & ~0xfffffff) == 0 \
2595 ? ((v) & ~0x3ffffff) == 0 \
2596 ? ((v) & ~0x1ffffff) == 0 \
2599 : ((v) & ~0x7ffffff) == 0 \
2602 : ((v) & ~0x3fffffff) == 0 \
2603 ? ((v) & ~0x1fffffff) == 0 \
2606 : ((v) & ~0x7fffffff) == 0 \
2611 * This routine generates the least number of instructions neccessary to load
2612 * an absolute expression value into a register.
2615 load_register (counter
, reg
, ep
, dbl
)
2622 expressionS hi32
, lo32
;
2624 if (ep
->X_op
!= O_big
)
2626 assert (ep
->X_op
== O_constant
);
2627 if (ep
->X_add_number
< 0x8000
2628 && (ep
->X_add_number
>= 0
2629 || (ep
->X_add_number
>= -0x8000
2632 || sizeof (ep
->X_add_number
) > 4))))
2634 /* We can handle 16 bit signed values with an addiu to
2635 $zero. No need to ever use daddiu here, since $zero and
2636 the result are always correct in 32 bit mode. */
2637 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2638 (int) BFD_RELOC_LO16
);
2641 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
2643 /* We can handle 16 bit unsigned values with an ori to
2645 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
2646 (int) BFD_RELOC_LO16
);
2649 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
2650 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
2651 == ~ (offsetT
) 0x7fffffff))
2654 || sizeof (ep
->X_add_number
) > 4
2655 || (ep
->X_add_number
& 0x80000000) == 0))
2656 || ((mips_isa
< 3 || !dbl
)
2657 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0))
2659 /* 32 bit values require an lui. */
2660 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2661 (int) BFD_RELOC_HI16
);
2662 if ((ep
->X_add_number
& 0xffff) != 0)
2663 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
2664 (int) BFD_RELOC_LO16
);
2669 /* The value is larger than 32 bits. */
2673 as_bad ("Number larger than 32 bits");
2674 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2675 (int) BFD_RELOC_LO16
);
2679 if (ep
->X_op
!= O_big
)
2682 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
2683 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
2684 hi32
.X_add_number
&= 0xffffffff;
2686 lo32
.X_add_number
&= 0xffffffff;
2690 assert (ep
->X_add_number
> 2);
2691 if (ep
->X_add_number
== 3)
2692 generic_bignum
[3] = 0;
2693 else if (ep
->X_add_number
> 4)
2694 as_bad ("Number larger than 64 bits");
2695 lo32
.X_op
= O_constant
;
2696 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
2697 hi32
.X_op
= O_constant
;
2698 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
2701 if (hi32
.X_add_number
== 0)
2706 unsigned long hi
, lo
;
2708 if (hi32
.X_add_number
== 0xffffffff)
2710 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
2712 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
2713 reg
, 0, (int) BFD_RELOC_LO16
);
2716 if (lo32
.X_add_number
& 0x80000000)
2718 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2719 (int) BFD_RELOC_HI16
);
2720 if (lo32
.X_add_number
& 0xffff)
2721 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
2722 reg
, reg
, (int) BFD_RELOC_LO16
);
2727 /* Check for 16bit shifted constant. We know that hi32 is
2728 non-zero, so start the mask on the first bit of the hi32
2733 unsigned long himask
, lomask
;
2737 himask
= 0xffff >> (32 - shift
);
2738 lomask
= (0xffff << shift
) & 0xffffffff;
2742 himask
= 0xffff << (shift
- 32);
2745 if ((hi32
.X_add_number
& ~ (offsetT
) himask
) == 0
2746 && (lo32
.X_add_number
& ~ (offsetT
) lomask
) == 0)
2750 tmp
.X_op
= O_constant
;
2752 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
2753 | (lo32
.X_add_number
>> shift
));
2755 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
2756 macro_build ((char *) NULL
, counter
, &tmp
, "ori", "t,r,i", reg
, 0,
2757 (int) BFD_RELOC_LO16
);
2758 macro_build ((char *) NULL
, counter
, NULL
,
2759 (shift
>= 32) ? "dsll32" : "dsll",
2761 (shift
>= 32) ? shift
- 32 : shift
);
2765 } while (shift
<= (64 - 16));
2767 /* Find the bit number of the lowest one bit, and store the
2768 shifted value in hi/lo. */
2769 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
2770 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
2774 while ((lo
& 1) == 0)
2779 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
2785 while ((hi
& 1) == 0)
2794 /* Optimize if the shifted value is a (power of 2) - 1. */
2795 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
2796 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
2798 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
2803 /* This instruction will set the register to be all
2805 tmp
.X_op
= O_constant
;
2806 tmp
.X_add_number
= (offsetT
) -1;
2807 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
2808 reg
, 0, (int) BFD_RELOC_LO16
);
2812 macro_build ((char *) NULL
, counter
, NULL
,
2813 (bit
>= 32) ? "dsll32" : "dsll",
2815 (bit
>= 32) ? bit
- 32 : bit
);
2817 macro_build ((char *) NULL
, counter
, NULL
,
2818 (shift
>= 32) ? "dsrl32" : "dsrl",
2820 (shift
>= 32) ? shift
- 32 : shift
);
2825 /* Sign extend hi32 before calling load_register, because we can
2826 generally get better code when we load a sign extended value. */
2827 if ((hi32
.X_add_number
& 0x80000000) != 0)
2828 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
2829 load_register (counter
, reg
, &hi32
, 0);
2832 if ((lo32
.X_add_number
& 0xffff0000) == 0)
2836 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
2845 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
2847 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2848 (int) BFD_RELOC_HI16
);
2849 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
2856 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
2861 mid16
.X_add_number
>>= 16;
2862 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
2863 freg
, (int) BFD_RELOC_LO16
);
2864 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
2868 if ((lo32
.X_add_number
& 0xffff) != 0)
2869 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
2870 (int) BFD_RELOC_LO16
);
2873 /* Load an address into a register. */
2876 load_address (counter
, reg
, ep
)
2883 if (ep
->X_op
!= O_constant
2884 && ep
->X_op
!= O_symbol
)
2886 as_bad ("expression too complex");
2887 ep
->X_op
= O_constant
;
2890 if (ep
->X_op
== O_constant
)
2892 load_register (counter
, reg
, ep
, 0);
2896 if (mips_pic
== NO_PIC
)
2898 /* If this is a reference to a GP relative symbol, we want
2899 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2901 lui $reg,<sym> (BFD_RELOC_HI16_S)
2902 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2903 If we have an addend, we always use the latter form. */
2904 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
2905 || nopic_need_relax (ep
->X_add_symbol
))
2910 macro_build ((char *) NULL
, counter
, ep
,
2911 mips_isa
< 3 ? "addiu" : "daddiu",
2912 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2913 p
= frag_var (rs_machine_dependent
, 8, 0,
2914 RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros
),
2915 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2917 macro_build_lui (p
, counter
, ep
, reg
);
2920 macro_build (p
, counter
, ep
,
2921 mips_isa
< 3 ? "addiu" : "daddiu",
2922 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2924 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
2928 /* If this is a reference to an external symbol, we want
2929 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2931 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2933 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2934 If there is a constant, it must be added in after. */
2935 ex
.X_add_number
= ep
->X_add_number
;
2936 ep
->X_add_number
= 0;
2938 macro_build ((char *) NULL
, counter
, ep
,
2939 mips_isa
< 3 ? "lw" : "ld",
2940 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2941 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
2942 p
= frag_var (rs_machine_dependent
, 4, 0,
2943 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
2944 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2945 macro_build (p
, counter
, ep
,
2946 mips_isa
< 3 ? "addiu" : "daddiu",
2947 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2948 if (ex
.X_add_number
!= 0)
2950 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2951 as_bad ("PIC code offset overflow (max 16 signed bits)");
2952 ex
.X_op
= O_constant
;
2953 macro_build ((char *) NULL
, counter
, &ex
,
2954 mips_isa
< 3 ? "addiu" : "daddiu",
2955 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2958 else if (mips_pic
== SVR4_PIC
)
2963 /* This is the large GOT case. If this is a reference to an
2964 external symbol, we want
2965 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
2967 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
2968 Otherwise, for a reference to a local symbol, we want
2969 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2971 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2972 If there is a constant, it must be added in after. */
2973 ex
.X_add_number
= ep
->X_add_number
;
2974 ep
->X_add_number
= 0;
2975 if (reg_needs_delay (GP
))
2980 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2981 (int) BFD_RELOC_MIPS_GOT_HI16
);
2982 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
2983 mips_isa
< 3 ? "addu" : "daddu",
2984 "d,v,t", reg
, reg
, GP
);
2985 macro_build ((char *) NULL
, counter
, ep
,
2986 mips_isa
< 3 ? "lw" : "ld",
2987 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
2988 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
2989 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
2990 mips_warn_about_macros
),
2991 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2994 /* We need a nop before loading from $gp. This special
2995 check is required because the lui which starts the main
2996 instruction stream does not refer to $gp, and so will not
2997 insert the nop which may be required. */
2998 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3001 macro_build (p
, counter
, ep
,
3002 mips_isa
< 3 ? "lw" : "ld",
3003 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3005 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3007 macro_build (p
, counter
, ep
,
3008 mips_isa
< 3 ? "addiu" : "daddiu",
3009 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3010 if (ex
.X_add_number
!= 0)
3012 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3013 as_bad ("PIC code offset overflow (max 16 signed bits)");
3014 ex
.X_op
= O_constant
;
3015 macro_build ((char *) NULL
, counter
, &ex
,
3016 mips_isa
< 3 ? "addiu" : "daddiu",
3017 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3020 else if (mips_pic
== EMBEDDED_PIC
)
3023 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3025 macro_build ((char *) NULL
, counter
, ep
,
3026 mips_isa
< 3 ? "addiu" : "daddiu",
3027 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3035 * This routine implements the seemingly endless macro or synthesized
3036 * instructions and addressing modes in the mips assembly language. Many
3037 * of these macros are simple and are similar to each other. These could
3038 * probably be handled by some kind of table or grammer aproach instead of
3039 * this verbose method. Others are not simple macros but are more like
3040 * optimizing code generation.
3041 * One interesting optimization is when several store macros appear
3042 * consecutivly that would load AT with the upper half of the same address.
3043 * The ensuing load upper instructions are ommited. This implies some kind
3044 * of global optimization. We currently only optimize within a single macro.
3045 * For many of the load and store macros if the address is specified as a
3046 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3047 * first load register 'at' with zero and use it as the base register. The
3048 * mips assembler simply uses register $zero. Just one tiny optimization
3053 struct mips_cl_insn
*ip
;
3055 register int treg
, sreg
, dreg
, breg
;
3070 bfd_reloc_code_real_type r
;
3072 int hold_mips_optimize
;
3076 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3077 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3078 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3079 mask
= ip
->insn_mo
->mask
;
3081 expr1
.X_op
= O_constant
;
3082 expr1
.X_op_symbol
= NULL
;
3083 expr1
.X_add_symbol
= NULL
;
3084 expr1
.X_add_number
= 1;
3096 mips_emit_delays (true);
3098 mips_any_noreorder
= 1;
3100 expr1
.X_add_number
= 8;
3101 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3103 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3105 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
3106 macro_build ((char *) NULL
, &icnt
, NULL
,
3107 dbl
? "dsub" : "sub",
3108 "d,v,t", dreg
, 0, sreg
);
3131 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3133 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3134 (int) BFD_RELOC_LO16
);
3137 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3138 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3157 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3159 if (mask
!= M_NOR_I
)
3160 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3161 sreg
, (int) BFD_RELOC_LO16
);
3164 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3165 treg
, sreg
, (int) BFD_RELOC_LO16
);
3166 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
3172 load_register (&icnt
, AT
, &imm_expr
, 0);
3173 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3190 if (imm_expr
.X_add_number
== 0)
3192 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3196 load_register (&icnt
, AT
, &imm_expr
, 0);
3197 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3205 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3206 likely
? "bgezl" : "bgez",
3212 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3213 likely
? "blezl" : "blez",
3217 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3218 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3219 likely
? "beql" : "beq",
3226 /* check for > max integer */
3227 maxnum
= 0x7fffffff;
3235 if (imm_expr
.X_add_number
>= maxnum
3236 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
3239 /* result is always false */
3242 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
3243 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3247 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
3248 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3253 imm_expr
.X_add_number
++;
3257 if (mask
== M_BGEL_I
)
3259 if (imm_expr
.X_add_number
== 0)
3261 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3262 likely
? "bgezl" : "bgez",
3266 if (imm_expr
.X_add_number
== 1)
3268 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3269 likely
? "bgtzl" : "bgtz",
3273 maxnum
= 0x7fffffff;
3281 maxnum
= - maxnum
- 1;
3282 if (imm_expr
.X_add_number
<= maxnum
3283 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
3286 /* result is always true */
3287 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
3288 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3291 set_at (&icnt
, sreg
, 0);
3292 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3293 likely
? "beql" : "beq",
3304 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3305 likely
? "beql" : "beq",
3309 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3311 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3312 likely
? "beql" : "beq",
3319 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
3321 imm_expr
.X_add_number
++;
3325 if (mask
== M_BGEUL_I
)
3327 if (imm_expr
.X_add_number
== 0)
3329 if (imm_expr
.X_add_number
== 1)
3331 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3332 likely
? "bnel" : "bne",
3336 set_at (&icnt
, sreg
, 1);
3337 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3338 likely
? "beql" : "beq",
3347 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3348 likely
? "bgtzl" : "bgtz",
3354 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3355 likely
? "bltzl" : "bltz",
3359 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3360 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3361 likely
? "bnel" : "bne",
3370 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3371 likely
? "bnel" : "bne",
3377 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3379 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3380 likely
? "bnel" : "bne",
3389 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3390 likely
? "blezl" : "blez",
3396 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3397 likely
? "bgezl" : "bgez",
3401 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3402 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3403 likely
? "beql" : "beq",
3410 maxnum
= 0x7fffffff;
3418 if (imm_expr
.X_add_number
>= maxnum
3419 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
3421 imm_expr
.X_add_number
++;
3425 if (mask
== M_BLTL_I
)
3427 if (imm_expr
.X_add_number
== 0)
3429 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3430 likely
? "bltzl" : "bltz",
3434 if (imm_expr
.X_add_number
== 1)
3436 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3437 likely
? "blezl" : "blez",
3441 set_at (&icnt
, sreg
, 0);
3442 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3443 likely
? "bnel" : "bne",
3452 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3453 likely
? "beql" : "beq",
3459 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3461 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3462 likely
? "beql" : "beq",
3469 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
3471 imm_expr
.X_add_number
++;
3475 if (mask
== M_BLTUL_I
)
3477 if (imm_expr
.X_add_number
== 0)
3479 if (imm_expr
.X_add_number
== 1)
3481 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3482 likely
? "beql" : "beq",
3486 set_at (&icnt
, sreg
, 1);
3487 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3488 likely
? "bnel" : "bne",
3497 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3498 likely
? "bltzl" : "bltz",
3504 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3505 likely
? "bgtzl" : "bgtz",
3509 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3510 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3511 likely
? "bnel" : "bne",
3522 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3523 likely
? "bnel" : "bne",
3527 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3529 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3530 likely
? "bnel" : "bne",
3546 as_warn ("Divide by zero.");
3548 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3550 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3554 mips_emit_delays (true);
3556 mips_any_noreorder
= 1;
3557 macro_build ((char *) NULL
, &icnt
, NULL
,
3558 dbl
? "ddiv" : "div",
3559 "z,s,t", sreg
, treg
);
3561 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3564 expr1
.X_add_number
= 8;
3565 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3566 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3567 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3569 expr1
.X_add_number
= -1;
3570 macro_build ((char *) NULL
, &icnt
, &expr1
,
3571 dbl
? "daddiu" : "addiu",
3572 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
3573 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
3574 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
3577 expr1
.X_add_number
= 1;
3578 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
3579 (int) BFD_RELOC_LO16
);
3580 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
3585 expr1
.X_add_number
= 0x80000000;
3586 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
3587 (int) BFD_RELOC_HI16
);
3590 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
3593 expr1
.X_add_number
= 8;
3594 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
3595 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3596 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3599 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
3638 if (imm_expr
.X_add_number
== 0)
3640 as_warn ("Divide by zero.");
3642 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3644 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3647 if (imm_expr
.X_add_number
== 1)
3649 if (strcmp (s2
, "mflo") == 0)
3650 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
3653 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3656 if (imm_expr
.X_add_number
== -1
3657 && s
[strlen (s
) - 1] != 'u')
3659 if (strcmp (s2
, "mflo") == 0)
3662 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
3665 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
3669 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3673 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3674 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
3675 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
3694 mips_emit_delays (true);
3696 mips_any_noreorder
= 1;
3697 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
3699 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3702 expr1
.X_add_number
= 8;
3703 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3704 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3705 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3708 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
3714 /* Load the address of a symbol into a register. If breg is not
3715 zero, we then add a base register to it. */
3717 /* When generating embedded PIC code, we permit expressions of
3720 where bar is an address in the .text section. These are used
3721 when getting the addresses of functions. We don't permit
3722 X_add_number to be non-zero, because if the symbol is
3723 external the relaxing code needs to know that any addend is
3724 purely the offset to X_op_symbol. */
3725 if (mips_pic
== EMBEDDED_PIC
3726 && offset_expr
.X_op
== O_subtract
3727 && now_seg
== text_section
3728 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
3729 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
3730 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
3731 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
3732 ->sy_value
.X_add_symbol
)
3735 && offset_expr
.X_add_number
== 0)
3737 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3738 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
3739 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3740 mips_isa
< 3 ? "addiu" : "daddiu",
3741 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
3745 if (offset_expr
.X_op
!= O_symbol
3746 && offset_expr
.X_op
!= O_constant
)
3748 as_bad ("expression too complex");
3749 offset_expr
.X_op
= O_constant
;
3763 if (offset_expr
.X_op
== O_constant
)
3764 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
3765 else if (mips_pic
== NO_PIC
)
3767 /* If this is a reference to an GP relative symbol, we want
3768 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3770 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3771 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3772 If we have a constant, we need two instructions anyhow,
3773 so we may as well always use the latter form. */
3774 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
3775 || nopic_need_relax (offset_expr
.X_add_symbol
))
3780 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3781 mips_isa
< 3 ? "addiu" : "daddiu",
3782 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3783 p
= frag_var (rs_machine_dependent
, 8, 0,
3784 RELAX_ENCODE (4, 8, 0, 4, 0,
3785 mips_warn_about_macros
),
3786 offset_expr
.X_add_symbol
, (long) 0,
3789 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3792 macro_build (p
, &icnt
, &offset_expr
,
3793 mips_isa
< 3 ? "addiu" : "daddiu",
3794 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3796 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3798 /* If this is a reference to an external symbol, and there
3799 is no constant, we want
3800 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3801 For a local symbol, we want
3802 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3804 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3806 If we have a small constant, and this is a reference to
3807 an external symbol, we want
3808 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3810 addiu $tempreg,$tempreg,<constant>
3811 For a local symbol, we want the same instruction
3812 sequence, but we output a BFD_RELOC_LO16 reloc on the
3815 If we have a large constant, and this is a reference to
3816 an external symbol, we want
3817 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3818 lui $at,<hiconstant>
3819 addiu $at,$at,<loconstant>
3820 addu $tempreg,$tempreg,$at
3821 For a local symbol, we want the same instruction
3822 sequence, but we output a BFD_RELOC_LO16 reloc on the
3823 addiu instruction. */
3824 expr1
.X_add_number
= offset_expr
.X_add_number
;
3825 offset_expr
.X_add_number
= 0;
3827 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3829 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3830 if (expr1
.X_add_number
== 0)
3838 /* We're going to put in an addu instruction using
3839 tempreg, so we may as well insert the nop right
3841 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3845 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
3846 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
3848 ? mips_warn_about_macros
3850 offset_expr
.X_add_symbol
, (long) 0,
3854 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3857 macro_build (p
, &icnt
, &expr1
,
3858 mips_isa
< 3 ? "addiu" : "daddiu",
3859 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3860 /* FIXME: If breg == 0, and the next instruction uses
3861 $tempreg, then if this variant case is used an extra
3862 nop will be generated. */
3864 else if (expr1
.X_add_number
>= -0x8000
3865 && expr1
.X_add_number
< 0x8000)
3867 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3869 macro_build ((char *) NULL
, &icnt
, &expr1
,
3870 mips_isa
< 3 ? "addiu" : "daddiu",
3871 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3872 (void) frag_var (rs_machine_dependent
, 0, 0,
3873 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
3874 offset_expr
.X_add_symbol
, (long) 0,
3881 /* If we are going to add in a base register, and the
3882 target register and the base register are the same,
3883 then we are using AT as a temporary register. Since
3884 we want to load the constant into AT, we add our
3885 current AT (from the global offset table) and the
3886 register into the register now, and pretend we were
3887 not using a base register. */
3892 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3894 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3895 mips_isa
< 3 ? "addu" : "daddu",
3896 "d,v,t", treg
, AT
, breg
);
3902 /* Set mips_optimize around the lui instruction to avoid
3903 inserting an unnecessary nop after the lw. */
3904 hold_mips_optimize
= mips_optimize
;
3906 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
3907 mips_optimize
= hold_mips_optimize
;
3909 macro_build ((char *) NULL
, &icnt
, &expr1
,
3910 mips_isa
< 3 ? "addiu" : "daddiu",
3911 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3912 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3913 mips_isa
< 3 ? "addu" : "daddu",
3914 "d,v,t", tempreg
, tempreg
, AT
);
3915 (void) frag_var (rs_machine_dependent
, 0, 0,
3916 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
3917 offset_expr
.X_add_symbol
, (long) 0,
3922 else if (mips_pic
== SVR4_PIC
)
3926 /* This is the large GOT case. If this is a reference to an
3927 external symbol, and there is no constant, we want
3928 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3929 addu $tempreg,$tempreg,$gp
3930 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3931 For a local symbol, we want
3932 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3934 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3936 If we have a small constant, and this is a reference to
3937 an external symbol, we want
3938 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3939 addu $tempreg,$tempreg,$gp
3940 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3942 addiu $tempreg,$tempreg,<constant>
3943 For a local symbol, we want
3944 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3946 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
3948 If we have a large constant, and this is a reference to
3949 an external symbol, we want
3950 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3951 addu $tempreg,$tempreg,$gp
3952 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3953 lui $at,<hiconstant>
3954 addiu $at,$at,<loconstant>
3955 addu $tempreg,$tempreg,$at
3956 For a local symbol, we want
3957 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3958 lui $at,<hiconstant>
3959 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
3960 addu $tempreg,$tempreg,$at
3962 expr1
.X_add_number
= offset_expr
.X_add_number
;
3963 offset_expr
.X_add_number
= 0;
3965 if (reg_needs_delay (GP
))
3969 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3970 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
3971 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3972 mips_isa
< 3 ? "addu" : "daddu",
3973 "d,v,t", tempreg
, tempreg
, GP
);
3974 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3976 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
3978 if (expr1
.X_add_number
== 0)
3986 /* We're going to put in an addu instruction using
3987 tempreg, so we may as well insert the nop right
3989 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3994 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3995 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
3998 ? mips_warn_about_macros
4000 offset_expr
.X_add_symbol
, (long) 0,
4003 else if (expr1
.X_add_number
>= -0x8000
4004 && expr1
.X_add_number
< 0x8000)
4006 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4008 macro_build ((char *) NULL
, &icnt
, &expr1
,
4009 mips_isa
< 3 ? "addiu" : "daddiu",
4010 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4012 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4013 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4015 ? mips_warn_about_macros
4017 offset_expr
.X_add_symbol
, (long) 0,
4024 /* If we are going to add in a base register, and the
4025 target register and the base register are the same,
4026 then we are using AT as a temporary register. Since
4027 we want to load the constant into AT, we add our
4028 current AT (from the global offset table) and the
4029 register into the register now, and pretend we were
4030 not using a base register. */
4038 assert (tempreg
== AT
);
4039 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4041 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4042 mips_isa
< 3 ? "addu" : "daddu",
4043 "d,v,t", treg
, AT
, breg
);
4048 /* Set mips_optimize around the lui instruction to avoid
4049 inserting an unnecessary nop after the lw. */
4050 hold_mips_optimize
= mips_optimize
;
4052 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4053 mips_optimize
= hold_mips_optimize
;
4055 macro_build ((char *) NULL
, &icnt
, &expr1
,
4056 mips_isa
< 3 ? "addiu" : "daddiu",
4057 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4058 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4059 mips_isa
< 3 ? "addu" : "daddu",
4060 "d,v,t", dreg
, dreg
, AT
);
4062 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4063 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4066 ? mips_warn_about_macros
4068 offset_expr
.X_add_symbol
, (long) 0,
4076 /* This is needed because this instruction uses $gp, but
4077 the first instruction on the main stream does not. */
4078 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4081 macro_build (p
, &icnt
, &offset_expr
,
4083 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4085 if (expr1
.X_add_number
>= -0x8000
4086 && expr1
.X_add_number
< 0x8000)
4088 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4090 macro_build (p
, &icnt
, &expr1
,
4091 mips_isa
< 3 ? "addiu" : "daddiu",
4092 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4093 /* FIXME: If add_number is 0, and there was no base
4094 register, the external symbol case ended with a load,
4095 so if the symbol turns out to not be external, and
4096 the next instruction uses tempreg, an unnecessary nop
4097 will be inserted. */
4103 /* We must add in the base register now, as in the
4104 external symbol case. */
4105 assert (tempreg
== AT
);
4106 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4108 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4109 mips_isa
< 3 ? "addu" : "daddu",
4110 "d,v,t", treg
, AT
, breg
);
4113 /* We set breg to 0 because we have arranged to add
4114 it in in both cases. */
4118 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4120 macro_build (p
, &icnt
, &expr1
,
4121 mips_isa
< 3 ? "addiu" : "daddiu",
4122 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4124 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4125 mips_isa
< 3 ? "addu" : "daddu",
4126 "d,v,t", tempreg
, tempreg
, AT
);
4130 else if (mips_pic
== EMBEDDED_PIC
)
4133 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4135 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4136 mips_isa
< 3 ? "addiu" : "daddiu",
4137 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4143 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4144 mips_isa
< 3 ? "addu" : "daddu",
4145 "d,v,t", treg
, tempreg
, breg
);
4153 /* The j instruction may not be used in PIC code, since it
4154 requires an absolute address. We convert it to a b
4156 if (mips_pic
== NO_PIC
)
4157 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
4159 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4162 /* The jal instructions must be handled as macros because when
4163 generating PIC code they expand to multi-instruction
4164 sequences. Normally they are simple instructions. */
4169 if (mips_pic
== NO_PIC
4170 || mips_pic
== EMBEDDED_PIC
)
4171 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4173 else if (mips_pic
== SVR4_PIC
)
4175 if (sreg
!= PIC_CALL_REG
)
4176 as_warn ("MIPS PIC call to register other than $25");
4178 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4180 if (mips_cprestore_offset
< 0)
4181 as_warn ("No .cprestore pseudo-op used in PIC code");
4184 expr1
.X_add_number
= mips_cprestore_offset
;
4185 macro_build ((char *) NULL
, &icnt
, &expr1
,
4186 mips_isa
< 3 ? "lw" : "ld",
4187 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
4196 if (mips_pic
== NO_PIC
)
4197 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
4198 else if (mips_pic
== SVR4_PIC
)
4200 /* If this is a reference to an external symbol, and we are
4201 using a small GOT, we want
4202 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4206 lw $gp,cprestore($sp)
4207 The cprestore value is set using the .cprestore
4208 pseudo-op. If we are using a big GOT, we want
4209 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4211 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
4215 lw $gp,cprestore($sp)
4216 If the symbol is not external, we want
4217 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4219 addiu $25,$25,<sym> (BFD_RELOC_LO16)
4222 lw $gp,cprestore($sp) */
4226 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4227 mips_isa
< 3 ? "lw" : "ld",
4228 "t,o(b)", PIC_CALL_REG
,
4229 (int) BFD_RELOC_MIPS_CALL16
, GP
);
4230 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4232 p
= frag_var (rs_machine_dependent
, 4, 0,
4233 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4234 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
4240 if (reg_needs_delay (GP
))
4244 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4245 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4246 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4247 mips_isa
< 3 ? "addu" : "daddu",
4248 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4249 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4250 mips_isa
< 3 ? "lw" : "ld",
4251 "t,o(b)", PIC_CALL_REG
,
4252 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4253 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4255 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4256 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4258 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
4261 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4264 macro_build (p
, &icnt
, &offset_expr
,
4265 mips_isa
< 3 ? "lw" : "ld",
4266 "t,o(b)", PIC_CALL_REG
,
4267 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4269 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4272 macro_build (p
, &icnt
, &offset_expr
,
4273 mips_isa
< 3 ? "addiu" : "daddiu",
4274 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4275 (int) BFD_RELOC_LO16
);
4276 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4277 "jalr", "s", PIC_CALL_REG
);
4278 if (mips_cprestore_offset
< 0)
4279 as_warn ("No .cprestore pseudo-op used in PIC code");
4283 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4285 expr1
.X_add_number
= mips_cprestore_offset
;
4286 macro_build ((char *) NULL
, &icnt
, &expr1
,
4287 mips_isa
< 3 ? "lw" : "ld",
4288 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4292 else if (mips_pic
== EMBEDDED_PIC
)
4294 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4295 /* The linker may expand the call to a longer sequence which
4296 uses $at, so we must break rather than return. */
4372 if (breg
== treg
|| coproc
|| lr
)
4441 if (mask
== M_LWC1_AB
4442 || mask
== M_SWC1_AB
4443 || mask
== M_LDC1_AB
4444 || mask
== M_SDC1_AB
4453 if (offset_expr
.X_op
!= O_constant
4454 && offset_expr
.X_op
!= O_symbol
)
4456 as_bad ("expression too complex");
4457 offset_expr
.X_op
= O_constant
;
4460 /* A constant expression in PIC code can be handled just as it
4461 is in non PIC code. */
4462 if (mips_pic
== NO_PIC
4463 || offset_expr
.X_op
== O_constant
)
4465 /* If this is a reference to a GP relative symbol, and there
4466 is no base register, we want
4467 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4468 Otherwise, if there is no base register, we want
4469 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4470 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4471 If we have a constant, we need two instructions anyhow,
4472 so we always use the latter form.
4474 If we have a base register, and this is a reference to a
4475 GP relative symbol, we want
4476 addu $tempreg,$breg,$gp
4477 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4479 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4480 addu $tempreg,$tempreg,$breg
4481 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4482 With a constant we always use the latter case. */
4485 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4486 || nopic_need_relax (offset_expr
.X_add_symbol
))
4491 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4492 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4493 p
= frag_var (rs_machine_dependent
, 8, 0,
4494 RELAX_ENCODE (4, 8, 0, 4, 0,
4495 (mips_warn_about_macros
4496 || (used_at
&& mips_noat
))),
4497 offset_expr
.X_add_symbol
, (long) 0,
4501 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4504 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4505 (int) BFD_RELOC_LO16
, tempreg
);
4509 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4510 || nopic_need_relax (offset_expr
.X_add_symbol
))
4515 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4516 mips_isa
< 3 ? "addu" : "daddu",
4517 "d,v,t", tempreg
, breg
, GP
);
4518 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4519 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4520 p
= frag_var (rs_machine_dependent
, 12, 0,
4521 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
4522 offset_expr
.X_add_symbol
, (long) 0,
4525 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4528 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4529 mips_isa
< 3 ? "addu" : "daddu",
4530 "d,v,t", tempreg
, tempreg
, breg
);
4533 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4534 (int) BFD_RELOC_LO16
, tempreg
);
4537 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4539 /* If this is a reference to an external symbol, we want
4540 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4542 <op> $treg,0($tempreg)
4544 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4546 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4547 <op> $treg,0($tempreg)
4548 If there is a base register, we add it to $tempreg before
4549 the <op>. If there is a constant, we stick it in the
4550 <op> instruction. We don't handle constants larger than
4551 16 bits, because we have no way to load the upper 16 bits
4552 (actually, we could handle them for the subset of cases
4553 in which we are not using $at). */
4554 assert (offset_expr
.X_op
== O_symbol
);
4555 expr1
.X_add_number
= offset_expr
.X_add_number
;
4556 offset_expr
.X_add_number
= 0;
4557 if (expr1
.X_add_number
< -0x8000
4558 || expr1
.X_add_number
>= 0x8000)
4559 as_bad ("PIC code offset overflow (max 16 signed bits)");
4561 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4562 mips_isa
< 3 ? "lw" : "ld",
4563 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4564 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4565 p
= frag_var (rs_machine_dependent
, 4, 0,
4566 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4567 offset_expr
.X_add_symbol
, (long) 0,
4569 macro_build (p
, &icnt
, &offset_expr
,
4570 mips_isa
< 3 ? "addiu" : "daddiu",
4571 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4573 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4574 mips_isa
< 3 ? "addu" : "daddu",
4575 "d,v,t", tempreg
, tempreg
, breg
);
4576 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
4577 (int) BFD_RELOC_LO16
, tempreg
);
4579 else if (mips_pic
== SVR4_PIC
)
4583 /* If this is a reference to an external symbol, we want
4584 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4585 addu $tempreg,$tempreg,$gp
4586 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4587 <op> $treg,0($tempreg)
4589 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4591 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4592 <op> $treg,0($tempreg)
4593 If there is a base register, we add it to $tempreg before
4594 the <op>. If there is a constant, we stick it in the
4595 <op> instruction. We don't handle constants larger than
4596 16 bits, because we have no way to load the upper 16 bits
4597 (actually, we could handle them for the subset of cases
4598 in which we are not using $at). */
4599 assert (offset_expr
.X_op
== O_symbol
);
4600 expr1
.X_add_number
= offset_expr
.X_add_number
;
4601 offset_expr
.X_add_number
= 0;
4602 if (expr1
.X_add_number
< -0x8000
4603 || expr1
.X_add_number
>= 0x8000)
4604 as_bad ("PIC code offset overflow (max 16 signed bits)");
4605 if (reg_needs_delay (GP
))
4610 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4611 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4612 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4613 mips_isa
< 3 ? "addu" : "daddu",
4614 "d,v,t", tempreg
, tempreg
, GP
);
4615 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4616 mips_isa
< 3 ? "lw" : "ld",
4617 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4619 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4620 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
4621 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
4624 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4627 macro_build (p
, &icnt
, &offset_expr
,
4628 mips_isa
< 3 ? "lw" : "ld",
4629 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4631 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4633 macro_build (p
, &icnt
, &offset_expr
,
4634 mips_isa
< 3 ? "addiu" : "daddiu",
4635 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4637 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4638 mips_isa
< 3 ? "addu" : "daddu",
4639 "d,v,t", tempreg
, tempreg
, breg
);
4640 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
4641 (int) BFD_RELOC_LO16
, tempreg
);
4643 else if (mips_pic
== EMBEDDED_PIC
)
4645 /* If there is no base register, we want
4646 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4647 If there is a base register, we want
4648 addu $tempreg,$breg,$gp
4649 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4651 assert (offset_expr
.X_op
== O_symbol
);
4654 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4655 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4660 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4661 mips_isa
< 3 ? "addu" : "daddu",
4662 "d,v,t", tempreg
, breg
, GP
);
4663 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4664 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4677 load_register (&icnt
, treg
, &imm_expr
, 0);
4681 load_register (&icnt
, treg
, &imm_expr
, 1);
4685 if (imm_expr
.X_op
== O_constant
)
4687 load_register (&icnt
, AT
, &imm_expr
, 0);
4688 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4689 "mtc1", "t,G", AT
, treg
);
4694 assert (offset_expr
.X_op
== O_symbol
4695 && strcmp (segment_name (S_GET_SEGMENT
4696 (offset_expr
.X_add_symbol
)),
4698 && offset_expr
.X_add_number
== 0);
4699 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4700 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
4705 /* We know that sym is in the .rdata section. First we get the
4706 upper 16 bits of the address. */
4707 if (mips_pic
== NO_PIC
)
4709 /* FIXME: This won't work for a 64 bit address. */
4710 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
4712 else if (mips_pic
== SVR4_PIC
)
4714 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4715 mips_isa
< 3 ? "lw" : "ld",
4716 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4718 else if (mips_pic
== EMBEDDED_PIC
)
4720 /* For embedded PIC we pick up the entire address off $gp in
4721 a single instruction. */
4722 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4723 mips_isa
< 3 ? "addiu" : "daddiu",
4724 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4725 offset_expr
.X_op
= O_constant
;
4726 offset_expr
.X_add_number
= 0;
4731 /* Now we load the register(s). */
4733 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
4734 treg
, (int) BFD_RELOC_LO16
, AT
);
4737 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
4738 treg
, (int) BFD_RELOC_LO16
, AT
);
4741 /* FIXME: How in the world do we deal with the possible
4743 offset_expr
.X_add_number
+= 4;
4744 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
4745 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
4749 /* To avoid confusion in tc_gen_reloc, we must ensure that this
4750 does not become a variant frag. */
4751 frag_wane (frag_now
);
4757 assert (offset_expr
.X_op
== O_symbol
4758 && offset_expr
.X_add_number
== 0);
4759 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
4760 if (strcmp (s
, ".lit8") == 0)
4764 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
4765 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
4769 r
= BFD_RELOC_MIPS_LITERAL
;
4774 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
4775 if (mips_pic
== SVR4_PIC
)
4776 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4777 mips_isa
< 3 ? "lw" : "ld",
4778 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4781 /* FIXME: This won't work for a 64 bit address. */
4782 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
4787 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
4788 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
4790 /* To avoid confusion in tc_gen_reloc, we must ensure
4791 that this does not become a variant frag. */
4792 frag_wane (frag_now
);
4803 /* Even on a big endian machine $fn comes before $fn+1. We have
4804 to adjust when loading from memory. */
4807 assert (mips_isa
< 2);
4808 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4809 target_big_endian
? treg
+ 1 : treg
,
4811 /* FIXME: A possible overflow which I don't know how to deal
4813 offset_expr
.X_add_number
+= 4;
4814 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4815 target_big_endian
? treg
: treg
+ 1,
4818 /* To avoid confusion in tc_gen_reloc, we must ensure that this
4819 does not become a variant frag. */
4820 frag_wane (frag_now
);
4829 * The MIPS assembler seems to check for X_add_number not
4830 * being double aligned and generating:
4833 * addiu at,at,%lo(foo+1)
4836 * But, the resulting address is the same after relocation so why
4837 * generate the extra instruction?
4884 if (offset_expr
.X_op
!= O_symbol
4885 && offset_expr
.X_op
!= O_constant
)
4887 as_bad ("expression too complex");
4888 offset_expr
.X_op
= O_constant
;
4891 /* Even on a big endian machine $fn comes before $fn+1. We have
4892 to adjust when loading from memory. We set coproc if we must
4893 load $fn+1 first. */
4894 if (! target_big_endian
)
4897 if (mips_pic
== NO_PIC
4898 || offset_expr
.X_op
== O_constant
)
4900 /* If this is a reference to a GP relative symbol, we want
4901 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4902 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
4903 If we have a base register, we use this
4905 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
4906 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
4907 If this is not a GP relative symbol, we want
4908 lui $at,<sym> (BFD_RELOC_HI16_S)
4909 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4910 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4911 If there is a base register, we add it to $at after the
4912 lui instruction. If there is a constant, we always use
4914 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4915 || nopic_need_relax (offset_expr
.X_add_symbol
))
4934 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4935 mips_isa
< 3 ? "addu" : "daddu",
4936 "d,v,t", AT
, breg
, GP
);
4942 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4943 coproc
? treg
+ 1 : treg
,
4944 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4945 offset_expr
.X_add_number
+= 4;
4947 /* Set mips_optimize to 2 to avoid inserting an
4949 hold_mips_optimize
= mips_optimize
;
4951 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4952 coproc
? treg
: treg
+ 1,
4953 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4954 mips_optimize
= hold_mips_optimize
;
4956 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
4957 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
4958 used_at
&& mips_noat
),
4959 offset_expr
.X_add_symbol
, (long) 0,
4962 /* We just generated two relocs. When tc_gen_reloc
4963 handles this case, it will skip the first reloc and
4964 handle the second. The second reloc already has an
4965 extra addend of 4, which we added above. We must
4966 subtract it out, and then subtract another 4 to make
4967 the first reloc come out right. The second reloc
4968 will come out right because we are going to add 4 to
4969 offset_expr when we build its instruction below. */
4970 offset_expr
.X_add_number
-= 8;
4971 offset_expr
.X_op
= O_constant
;
4973 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
4978 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4979 mips_isa
< 3 ? "addu" : "daddu",
4980 "d,v,t", AT
, breg
, AT
);
4984 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4985 coproc
? treg
+ 1 : treg
,
4986 (int) BFD_RELOC_LO16
, AT
);
4989 /* FIXME: How do we handle overflow here? */
4990 offset_expr
.X_add_number
+= 4;
4991 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4992 coproc
? treg
: treg
+ 1,
4993 (int) BFD_RELOC_LO16
, AT
);
4995 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4999 /* If this is a reference to an external symbol, we want
5000 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5005 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5007 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5008 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5009 If there is a base register we add it to $at before the
5010 lwc1 instructions. If there is a constant we include it
5011 in the lwc1 instructions. */
5013 expr1
.X_add_number
= offset_expr
.X_add_number
;
5014 offset_expr
.X_add_number
= 0;
5015 if (expr1
.X_add_number
< -0x8000
5016 || expr1
.X_add_number
>= 0x8000 - 4)
5017 as_bad ("PIC code offset overflow (max 16 signed bits)");
5022 frag_grow (24 + off
);
5023 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5024 mips_isa
< 3 ? "lw" : "ld",
5025 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5026 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5028 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5029 mips_isa
< 3 ? "addu" : "daddu",
5030 "d,v,t", AT
, breg
, AT
);
5031 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5032 coproc
? treg
+ 1 : treg
,
5033 (int) BFD_RELOC_LO16
, AT
);
5034 expr1
.X_add_number
+= 4;
5036 /* Set mips_optimize to 2 to avoid inserting an undesired
5038 hold_mips_optimize
= mips_optimize
;
5040 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5041 coproc
? treg
: treg
+ 1,
5042 (int) BFD_RELOC_LO16
, AT
);
5043 mips_optimize
= hold_mips_optimize
;
5045 (void) frag_var (rs_machine_dependent
, 0, 0,
5046 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
5047 offset_expr
.X_add_symbol
, (long) 0,
5050 else if (mips_pic
== SVR4_PIC
)
5054 /* If this is a reference to an external symbol, we want
5055 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5057 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
5062 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5064 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5065 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5066 If there is a base register we add it to $at before the
5067 lwc1 instructions. If there is a constant we include it
5068 in the lwc1 instructions. */
5070 expr1
.X_add_number
= offset_expr
.X_add_number
;
5071 offset_expr
.X_add_number
= 0;
5072 if (expr1
.X_add_number
< -0x8000
5073 || expr1
.X_add_number
>= 0x8000 - 4)
5074 as_bad ("PIC code offset overflow (max 16 signed bits)");
5075 if (reg_needs_delay (GP
))
5084 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5085 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5086 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5087 mips_isa
< 3 ? "addu" : "daddu",
5088 "d,v,t", AT
, AT
, GP
);
5089 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5090 mips_isa
< 3 ? "lw" : "ld",
5091 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
5092 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5094 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5095 mips_isa
< 3 ? "addu" : "daddu",
5096 "d,v,t", AT
, breg
, AT
);
5097 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5098 coproc
? treg
+ 1 : treg
,
5099 (int) BFD_RELOC_LO16
, AT
);
5100 expr1
.X_add_number
+= 4;
5102 /* Set mips_optimize to 2 to avoid inserting an undesired
5104 hold_mips_optimize
= mips_optimize
;
5106 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5107 coproc
? treg
: treg
+ 1,
5108 (int) BFD_RELOC_LO16
, AT
);
5109 mips_optimize
= hold_mips_optimize
;
5110 expr1
.X_add_number
-= 4;
5112 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
5113 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
5114 8 + gpdel
+ off
, 1, 0),
5115 offset_expr
.X_add_symbol
, (long) 0,
5119 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5122 macro_build (p
, &icnt
, &offset_expr
,
5123 mips_isa
< 3 ? "lw" : "ld",
5124 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5126 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5130 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5131 mips_isa
< 3 ? "addu" : "daddu",
5132 "d,v,t", AT
, breg
, AT
);
5135 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5136 coproc
? treg
+ 1 : treg
,
5137 (int) BFD_RELOC_LO16
, AT
);
5139 expr1
.X_add_number
+= 4;
5141 /* Set mips_optimize to 2 to avoid inserting an undesired
5143 hold_mips_optimize
= mips_optimize
;
5145 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5146 coproc
? treg
: treg
+ 1,
5147 (int) BFD_RELOC_LO16
, AT
);
5148 mips_optimize
= hold_mips_optimize
;
5150 else if (mips_pic
== EMBEDDED_PIC
)
5152 /* If there is no base register, we use
5153 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5154 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5155 If we have a base register, we use
5157 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5158 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5167 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5168 mips_isa
< 3 ? "addu" : "daddu",
5169 "d,v,t", AT
, breg
, GP
);
5174 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5175 coproc
? treg
+ 1 : treg
,
5176 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5177 offset_expr
.X_add_number
+= 4;
5178 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5179 coproc
? treg
: treg
+ 1,
5180 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5196 assert (mips_isa
< 3);
5197 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5198 (int) BFD_RELOC_LO16
, breg
);
5199 offset_expr
.X_add_number
+= 4;
5200 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
5201 (int) BFD_RELOC_LO16
, breg
);
5203 #ifdef LOSING_COMPILER
5209 as_warn ("Macro used $at after \".set noat\"");
5214 struct mips_cl_insn
*ip
;
5216 register int treg
, sreg
, dreg
, breg
;
5231 bfd_reloc_code_real_type r
;
5234 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
5235 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
5236 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
5237 mask
= ip
->insn_mo
->mask
;
5239 expr1
.X_op
= O_constant
;
5240 expr1
.X_op_symbol
= NULL
;
5241 expr1
.X_add_symbol
= NULL
;
5242 expr1
.X_add_number
= 1;
5246 #endif /* LOSING_COMPILER */
5251 macro_build ((char *) NULL
, &icnt
, NULL
,
5252 dbl
? "dmultu" : "multu",
5254 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5260 /* The MIPS assembler some times generates shifts and adds. I'm
5261 not trying to be that fancy. GCC should do this for us
5263 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5264 macro_build ((char *) NULL
, &icnt
, NULL
,
5265 dbl
? "dmult" : "mult",
5267 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5273 mips_emit_delays (true);
5275 mips_any_noreorder
= 1;
5276 macro_build ((char *) NULL
, &icnt
, NULL
,
5277 dbl
? "dmult" : "mult",
5279 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5280 macro_build ((char *) NULL
, &icnt
, NULL
,
5281 dbl
? "dsra32" : "sra",
5282 "d,w,<", dreg
, dreg
, 31);
5283 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5285 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
5288 expr1
.X_add_number
= 8;
5289 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
5290 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5291 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5294 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5300 mips_emit_delays (true);
5302 mips_any_noreorder
= 1;
5303 macro_build ((char *) NULL
, &icnt
, NULL
,
5304 dbl
? "dmultu" : "multu",
5306 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5307 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5309 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
5312 expr1
.X_add_number
= 8;
5313 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
5314 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5315 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5321 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
5322 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
5323 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
5325 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5329 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
5330 (int) (imm_expr
.X_add_number
& 0x1f));
5331 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
5332 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
5333 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5337 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
5338 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
5339 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
5341 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5345 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
5346 (int) (imm_expr
.X_add_number
& 0x1f));
5347 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
5348 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
5349 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5353 assert (mips_isa
< 2);
5354 /* Even on a big endian machine $fn comes before $fn+1. We have
5355 to adjust when storing to memory. */
5356 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
5357 target_big_endian
? treg
+ 1 : treg
,
5358 (int) BFD_RELOC_LO16
, breg
);
5359 offset_expr
.X_add_number
+= 4;
5360 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
5361 target_big_endian
? treg
: treg
+ 1,
5362 (int) BFD_RELOC_LO16
, breg
);
5367 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5368 treg
, (int) BFD_RELOC_LO16
);
5370 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5371 sreg
, (int) BFD_RELOC_LO16
);
5374 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5376 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5377 dreg
, (int) BFD_RELOC_LO16
);
5382 if (imm_expr
.X_add_number
== 0)
5384 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5385 sreg
, (int) BFD_RELOC_LO16
);
5390 as_warn ("Instruction %s: result is always false",
5392 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
5395 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
5397 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
5398 sreg
, (int) BFD_RELOC_LO16
);
5401 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
5403 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5404 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5405 mips_isa
< 3 ? "addiu" : "daddiu",
5406 "t,r,j", dreg
, sreg
,
5407 (int) BFD_RELOC_LO16
);
5412 load_register (&icnt
, AT
, &imm_expr
, 0);
5413 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5417 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
5418 (int) BFD_RELOC_LO16
);
5423 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
5429 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
5430 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5431 (int) BFD_RELOC_LO16
);
5434 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
5436 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5438 macro_build ((char *) NULL
, &icnt
, &expr1
,
5439 mask
== M_SGE_I
? "slti" : "sltiu",
5440 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5445 load_register (&icnt
, AT
, &imm_expr
, 0);
5446 macro_build ((char *) NULL
, &icnt
, NULL
,
5447 mask
== M_SGE_I
? "slt" : "sltu",
5448 "d,v,t", dreg
, sreg
, AT
);
5451 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5452 (int) BFD_RELOC_LO16
);
5457 case M_SGT
: /* sreg > treg <==> treg < sreg */
5463 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
5466 case M_SGT_I
: /* sreg > I <==> I < sreg */
5472 load_register (&icnt
, AT
, &imm_expr
, 0);
5473 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
5476 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
5482 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
5483 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5484 (int) BFD_RELOC_LO16
);
5487 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
5493 load_register (&icnt
, AT
, &imm_expr
, 0);
5494 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
5495 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5496 (int) BFD_RELOC_LO16
);
5500 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5502 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
5503 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5506 load_register (&icnt
, AT
, &imm_expr
, 0);
5507 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
5511 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5513 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
5514 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5517 load_register (&icnt
, AT
, &imm_expr
, 0);
5518 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
5524 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5527 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5531 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5533 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5539 if (imm_expr
.X_add_number
== 0)
5541 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5547 as_warn ("Instruction %s: result is always true",
5549 macro_build ((char *) NULL
, &icnt
, &expr1
,
5550 mips_isa
< 3 ? "addiu" : "daddiu",
5551 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
5554 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
5556 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
5557 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5560 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
5562 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5563 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5564 mips_isa
< 3 ? "addiu" : "daddiu",
5565 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5570 load_register (&icnt
, AT
, &imm_expr
, 0);
5571 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5575 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
5583 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
5585 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5586 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5587 dbl
? "daddi" : "addi",
5588 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5591 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5592 macro_build ((char *) NULL
, &icnt
, NULL
,
5593 dbl
? "dsub" : "sub",
5594 "d,v,t", dreg
, sreg
, AT
);
5600 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
5602 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5603 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5604 dbl
? "daddiu" : "addiu",
5605 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5608 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5609 macro_build ((char *) NULL
, &icnt
, NULL
,
5610 dbl
? "dsubu" : "subu",
5611 "d,v,t", dreg
, sreg
, AT
);
5632 load_register (&icnt
, AT
, &imm_expr
, 0);
5633 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
5638 assert (mips_isa
< 2);
5639 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
5640 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
5643 * Is the double cfc1 instruction a bug in the mips assembler;
5644 * or is there a reason for it?
5646 mips_emit_delays (true);
5648 mips_any_noreorder
= 1;
5649 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
5650 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
5651 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5652 expr1
.X_add_number
= 3;
5653 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
5654 (int) BFD_RELOC_LO16
);
5655 expr1
.X_add_number
= 2;
5656 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
5657 (int) BFD_RELOC_LO16
);
5658 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
5659 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5660 macro_build ((char *) NULL
, &icnt
, NULL
,
5661 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
5662 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
5663 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5673 if (offset_expr
.X_add_number
>= 0x7fff)
5674 as_bad ("operand overflow");
5675 /* avoid load delay */
5676 if (! target_big_endian
)
5677 offset_expr
.X_add_number
+= 1;
5678 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5679 (int) BFD_RELOC_LO16
, breg
);
5680 if (! target_big_endian
)
5681 offset_expr
.X_add_number
-= 1;
5683 offset_expr
.X_add_number
+= 1;
5684 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
5685 (int) BFD_RELOC_LO16
, breg
);
5686 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
5687 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
5700 if (offset_expr
.X_add_number
>= 0x8000 - off
)
5701 as_bad ("operand overflow");
5702 if (! target_big_endian
)
5703 offset_expr
.X_add_number
+= off
;
5704 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5705 (int) BFD_RELOC_LO16
, breg
);
5706 if (! target_big_endian
)
5707 offset_expr
.X_add_number
-= off
;
5709 offset_expr
.X_add_number
+= off
;
5710 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
5711 (int) BFD_RELOC_LO16
, breg
);
5724 load_address (&icnt
, AT
, &offset_expr
);
5726 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5727 mips_isa
< 3 ? "addu" : "daddu",
5728 "d,v,t", AT
, AT
, breg
);
5729 if (! target_big_endian
)
5730 expr1
.X_add_number
= off
;
5732 expr1
.X_add_number
= 0;
5733 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
5734 (int) BFD_RELOC_LO16
, AT
);
5735 if (! target_big_endian
)
5736 expr1
.X_add_number
= 0;
5738 expr1
.X_add_number
= off
;
5739 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
5740 (int) BFD_RELOC_LO16
, AT
);
5745 load_address (&icnt
, AT
, &offset_expr
);
5747 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5748 mips_isa
< 3 ? "addu" : "daddu",
5749 "d,v,t", AT
, AT
, breg
);
5750 if (target_big_endian
)
5751 expr1
.X_add_number
= 0;
5752 macro_build ((char *) NULL
, &icnt
, &expr1
,
5753 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
5754 (int) BFD_RELOC_LO16
, AT
);
5755 if (target_big_endian
)
5756 expr1
.X_add_number
= 1;
5758 expr1
.X_add_number
= 0;
5759 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
5760 (int) BFD_RELOC_LO16
, AT
);
5761 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
5763 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
5768 if (offset_expr
.X_add_number
>= 0x7fff)
5769 as_bad ("operand overflow");
5770 if (target_big_endian
)
5771 offset_expr
.X_add_number
+= 1;
5772 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
5773 (int) BFD_RELOC_LO16
, breg
);
5774 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
5775 if (target_big_endian
)
5776 offset_expr
.X_add_number
-= 1;
5778 offset_expr
.X_add_number
+= 1;
5779 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
5780 (int) BFD_RELOC_LO16
, breg
);
5793 if (offset_expr
.X_add_number
>= 0x8000 - off
)
5794 as_bad ("operand overflow");
5795 if (! target_big_endian
)
5796 offset_expr
.X_add_number
+= off
;
5797 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5798 (int) BFD_RELOC_LO16
, breg
);
5799 if (! target_big_endian
)
5800 offset_expr
.X_add_number
-= off
;
5802 offset_expr
.X_add_number
+= off
;
5803 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
5804 (int) BFD_RELOC_LO16
, breg
);
5817 load_address (&icnt
, AT
, &offset_expr
);
5819 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5820 mips_isa
< 3 ? "addu" : "daddu",
5821 "d,v,t", AT
, AT
, breg
);
5822 if (! target_big_endian
)
5823 expr1
.X_add_number
= off
;
5825 expr1
.X_add_number
= 0;
5826 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
5827 (int) BFD_RELOC_LO16
, AT
);
5828 if (! target_big_endian
)
5829 expr1
.X_add_number
= 0;
5831 expr1
.X_add_number
= off
;
5832 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
5833 (int) BFD_RELOC_LO16
, AT
);
5837 load_address (&icnt
, AT
, &offset_expr
);
5839 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5840 mips_isa
< 3 ? "addu" : "daddu",
5841 "d,v,t", AT
, AT
, breg
);
5842 if (! target_big_endian
)
5843 expr1
.X_add_number
= 0;
5844 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
5845 (int) BFD_RELOC_LO16
, AT
);
5846 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
5848 if (! target_big_endian
)
5849 expr1
.X_add_number
= 1;
5851 expr1
.X_add_number
= 0;
5852 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
5853 (int) BFD_RELOC_LO16
, AT
);
5854 if (! target_big_endian
)
5855 expr1
.X_add_number
= 0;
5857 expr1
.X_add_number
= 1;
5858 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
5859 (int) BFD_RELOC_LO16
, AT
);
5860 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
5862 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
5867 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
5871 as_warn ("Macro used $at after \".set noat\"");
5874 /* Implement macros in mips16 mode. */
5878 struct mips_cl_insn
*ip
;
5881 int xreg
, yreg
, zreg
, tmp
;
5885 const char *s
, *s2
, *s3
;
5887 mask
= ip
->insn_mo
->mask
;
5889 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
5890 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
5891 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
5895 expr1
.X_op
= O_constant
;
5896 expr1
.X_op_symbol
= NULL
;
5897 expr1
.X_add_symbol
= NULL
;
5898 expr1
.X_add_number
= 1;
5917 mips_emit_delays (true);
5919 mips_any_noreorder
= 1;
5920 macro_build ((char *) NULL
, &icnt
, NULL
,
5921 dbl
? "ddiv" : "div",
5922 "0,x,y", xreg
, yreg
);
5923 expr1
.X_add_number
= 2;
5924 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
5925 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
5926 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
5927 since that causes an overflow. We should do that as well,
5928 but I don't see how to do the comparisons without a temporary
5931 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
5950 mips_emit_delays (true);
5952 mips_any_noreorder
= 1;
5953 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
5954 expr1
.X_add_number
= 2;
5955 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
5956 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
5958 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
5966 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5967 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5968 dbl
? "daddiu" : "addiu",
5969 "y,x,4", yreg
, xreg
);
5973 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5974 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
5979 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5980 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
6003 goto do_reverse_branch
;
6007 goto do_reverse_branch
;
6019 goto do_reverse_branch
;
6030 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
6032 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6059 goto do_addone_branch_i
;
6064 goto do_addone_branch_i
;
6079 goto do_addone_branch_i
;
6086 ++imm_expr
.X_add_number
;
6089 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
6090 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6094 expr1
.X_add_number
= 0;
6095 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
6097 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6098 "move", "y,X", xreg
, yreg
);
6099 expr1
.X_add_number
= 2;
6100 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
6101 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6102 "neg", "x,w", xreg
, xreg
);
6106 /* This routine assembles an instruction into its binary format. As a
6107 side effect, it sets one of the global variables imm_reloc or
6108 offset_reloc to the type of relocation to do if one of the operands
6109 is an address expression. */
6114 struct mips_cl_insn
*ip
;
6119 struct mips_opcode
*insn
;
6122 unsigned int lastregno
= 0;
6127 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '6' || *s
== '.'; ++s
)
6139 as_fatal ("Unknown opcode: `%s'", str
);
6141 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
6143 insn_error
= "unrecognized opcode";
6151 assert (strcmp (insn
->name
, str
) == 0);
6153 if (insn
->pinfo
== INSN_MACRO
)
6154 insn_isa
= insn
->match
;
6155 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA2
)
6157 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA3
)
6159 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA4
)
6164 if (insn_isa
> mips_isa
6165 || (insn
->pinfo
!= INSN_MACRO
6166 && (((insn
->pinfo
& INSN_ISA
) == INSN_4650
6168 || ((insn
->pinfo
& INSN_ISA
) == INSN_4010
6170 || ((insn
->pinfo
& INSN_ISA
) == INSN_4100
6172 /* start-sanitize-r5900 */
6173 || ((insn
->pinfo
& INSN_ISA
) == INSN_5900
6175 /* end-sanitize-r5900 */
6178 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
6179 && strcmp (insn
->name
, insn
[1].name
) == 0)
6184 if (insn_isa
<= mips_isa
)
6185 insn_error
= "opcode not supported on this processor";
6188 static char buf
[100];
6190 sprintf (buf
, "opcode requires -mips%d or greater", insn_isa
);
6197 ip
->insn_opcode
= insn
->match
;
6198 for (args
= insn
->args
;; ++args
)
6204 case '\0': /* end of args */
6217 ip
->insn_opcode
|= lastregno
<< 21;
6222 ip
->insn_opcode
|= lastregno
<< 16;
6226 ip
->insn_opcode
|= lastregno
<< 11;
6232 /* handle optional base register.
6233 Either the base register is omitted or
6234 we must have a left paren. */
6235 /* this is dependent on the next operand specifier
6236 is a 'b' for base register */
6237 assert (args
[1] == 'b');
6241 case ')': /* these must match exactly */
6246 case '<': /* must be at least one digit */
6248 * According to the manual, if the shift amount is greater
6249 * than 31 or less than 0 the the shift amount should be
6250 * mod 32. In reality the mips assembler issues an error.
6251 * We issue a warning and mask out all but the low 5 bits.
6253 my_getExpression (&imm_expr
, s
);
6254 check_absolute_expr (ip
, &imm_expr
);
6255 if ((unsigned long) imm_expr
.X_add_number
> 31)
6257 as_warn ("Improper shift amount (%ld)",
6258 (long) imm_expr
.X_add_number
);
6259 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
6261 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
6262 imm_expr
.X_op
= O_absent
;
6266 case '>': /* shift amount minus 32 */
6267 my_getExpression (&imm_expr
, s
);
6268 check_absolute_expr (ip
, &imm_expr
);
6269 if ((unsigned long) imm_expr
.X_add_number
< 32
6270 || (unsigned long) imm_expr
.X_add_number
> 63)
6272 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
6273 imm_expr
.X_op
= O_absent
;
6277 case 'k': /* cache code */
6278 case 'h': /* prefx code */
6279 my_getExpression (&imm_expr
, s
);
6280 check_absolute_expr (ip
, &imm_expr
);
6281 if ((unsigned long) imm_expr
.X_add_number
> 31)
6283 as_warn ("Invalid value for `%s' (%lu)",
6285 (unsigned long) imm_expr
.X_add_number
);
6286 imm_expr
.X_add_number
&= 0x1f;
6289 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
6291 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
6292 imm_expr
.X_op
= O_absent
;
6296 case 'c': /* break code */
6297 my_getExpression (&imm_expr
, s
);
6298 check_absolute_expr (ip
, &imm_expr
);
6299 if ((unsigned) imm_expr
.X_add_number
> 1023)
6300 as_warn ("Illegal break code (%ld)",
6301 (long) imm_expr
.X_add_number
);
6302 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
6303 imm_expr
.X_op
= O_absent
;
6307 case 'B': /* syscall code */
6308 my_getExpression (&imm_expr
, s
);
6309 check_absolute_expr (ip
, &imm_expr
);
6310 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
6311 as_warn ("Illegal syscall code (%ld)",
6312 (long) imm_expr
.X_add_number
);
6313 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
6314 imm_expr
.X_op
= O_absent
;
6318 case 'C': /* Coprocessor code */
6319 my_getExpression (&imm_expr
, s
);
6320 check_absolute_expr (ip
, &imm_expr
);
6321 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
6323 as_warn ("Coproccesor code > 25 bits (%ld)",
6324 (long) imm_expr
.X_add_number
);
6325 imm_expr
.X_add_number
&= ((1<<25) - 1);
6327 ip
->insn_opcode
|= imm_expr
.X_add_number
;
6328 imm_expr
.X_op
= O_absent
;
6332 case 'b': /* base register */
6333 case 'd': /* destination register */
6334 case 's': /* source register */
6335 case 't': /* target register */
6336 case 'r': /* both target and source */
6337 case 'v': /* both dest and source */
6338 case 'w': /* both dest and target */
6339 case 'E': /* coprocessor target register */
6340 case 'G': /* coprocessor destination register */
6341 case 'x': /* ignore register name */
6342 case 'z': /* must be zero register */
6356 while (isdigit (*s
));
6358 as_bad ("Invalid register number (%d)", regno
);
6360 else if (*args
== 'E' || *args
== 'G')
6364 if (s
[1] == 'f' && s
[2] == 'p')
6369 else if (s
[1] == 's' && s
[2] == 'p')
6374 else if (s
[1] == 'g' && s
[2] == 'p')
6379 else if (s
[1] == 'a' && s
[2] == 't')
6384 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
6389 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
6401 as_warn ("Used $at without \".set noat\"");
6407 if (c
== 'r' || c
== 'v' || c
== 'w')
6414 /* 'z' only matches $0. */
6415 if (c
== 'z' && regno
!= 0)
6423 ip
->insn_opcode
|= regno
<< 21;
6427 ip
->insn_opcode
|= regno
<< 11;
6432 ip
->insn_opcode
|= regno
<< 16;
6435 /* This case exists because on the r3000 trunc
6436 expands into a macro which requires a gp
6437 register. On the r6000 or r4000 it is
6438 assembled into a single instruction which
6439 ignores the register. Thus the insn version
6440 is MIPS_ISA2 and uses 'x', and the macro
6441 version is MIPS_ISA1 and uses 't'. */
6444 /* This case is for the div instruction, which
6445 acts differently if the destination argument
6446 is $0. This only matches $0, and is checked
6447 outside the switch. */
6458 ip
->insn_opcode
|= lastregno
<< 21;
6461 ip
->insn_opcode
|= lastregno
<< 16;
6466 case 'D': /* floating point destination register */
6467 case 'S': /* floating point source register */
6468 case 'T': /* floating point target register */
6469 case 'R': /* floating point source register */
6473 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
6483 while (isdigit (*s
));
6486 as_bad ("Invalid float register number (%d)", regno
);
6488 if ((regno
& 1) != 0
6490 && ! (strcmp (str
, "mtc1") == 0
6491 || strcmp (str
, "mfc1") == 0
6492 || strcmp (str
, "lwc1") == 0
6493 || strcmp (str
, "swc1") == 0
6494 || strcmp (str
, "l.s") == 0
6495 || strcmp (str
, "s.s") == 0))
6496 as_warn ("Float register should be even, was %d",
6504 if (c
== 'V' || c
== 'W')
6514 ip
->insn_opcode
|= regno
<< 6;
6518 ip
->insn_opcode
|= regno
<< 11;
6522 ip
->insn_opcode
|= regno
<< 16;
6525 ip
->insn_opcode
|= regno
<< 21;
6534 ip
->insn_opcode
|= lastregno
<< 11;
6537 ip
->insn_opcode
|= lastregno
<< 16;
6543 my_getExpression (&imm_expr
, s
);
6544 if (imm_expr
.X_op
!= O_big
6545 && imm_expr
.X_op
!= O_constant
)
6546 insn_error
= "absolute expression required";
6551 my_getExpression (&offset_expr
, s
);
6552 imm_reloc
= BFD_RELOC_32
;
6564 unsigned char temp
[8];
6566 unsigned int length
;
6571 /* These only appear as the last operand in an
6572 instruction, and every instruction that accepts
6573 them in any variant accepts them in all variants.
6574 This means we don't have to worry about backing out
6575 any changes if the instruction does not match.
6577 The difference between them is the size of the
6578 floating point constant and where it goes. For 'F'
6579 and 'L' the constant is 64 bits; for 'f' and 'l' it
6580 is 32 bits. Where the constant is placed is based
6581 on how the MIPS assembler does things:
6584 f -- immediate value
6587 The .lit4 and .lit8 sections are only used if
6588 permitted by the -G argument.
6590 When generating embedded PIC code, we use the
6591 .lit8 section but not the .lit4 section (we can do
6592 .lit4 inline easily; we need to put .lit8
6593 somewhere in the data segment, and using .lit8
6594 permits the linker to eventually combine identical
6597 f64
= *args
== 'F' || *args
== 'L';
6599 save_in
= input_line_pointer
;
6600 input_line_pointer
= s
;
6601 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
6603 s
= input_line_pointer
;
6604 input_line_pointer
= save_in
;
6605 if (err
!= NULL
&& *err
!= '\0')
6607 as_bad ("Bad floating point constant: %s", err
);
6608 memset (temp
, '\0', sizeof temp
);
6609 length
= f64
? 8 : 4;
6612 assert (length
== (f64
? 8 : 4));
6616 && (! USE_GLOBAL_POINTER_OPT
6617 || mips_pic
== EMBEDDED_PIC
6618 || g_switch_value
< 4)
6621 imm_expr
.X_op
= O_constant
;
6622 if (! target_big_endian
)
6623 imm_expr
.X_add_number
=
6624 (((((((int) temp
[3] << 8)
6629 imm_expr
.X_add_number
=
6630 (((((((int) temp
[0] << 8)
6637 const char *newname
;
6640 /* Switch to the right section. */
6642 subseg
= now_subseg
;
6645 default: /* unused default case avoids warnings. */
6647 newname
= RDATA_SECTION_NAME
;
6648 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
6652 newname
= RDATA_SECTION_NAME
;
6655 assert (!USE_GLOBAL_POINTER_OPT
6656 || g_switch_value
>= 4);
6660 new_seg
= subseg_new (newname
, (subsegT
) 0);
6661 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6662 bfd_set_section_flags (stdoutput
, new_seg
,
6667 frag_align (*args
== 'l' ? 2 : 3, 0);
6668 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6669 record_alignment (new_seg
, 4);
6671 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
6673 as_bad ("Can't use floating point insn in this section");
6675 /* Set the argument to the current address in the
6677 offset_expr
.X_op
= O_symbol
;
6678 offset_expr
.X_add_symbol
=
6679 symbol_new ("L0\001", now_seg
,
6680 (valueT
) frag_now_fix (), frag_now
);
6681 offset_expr
.X_add_number
= 0;
6683 /* Put the floating point number into the section. */
6684 p
= frag_more ((int) length
);
6685 memcpy (p
, temp
, length
);
6687 /* Switch back to the original section. */
6688 subseg_set (seg
, subseg
);
6693 case 'i': /* 16 bit unsigned immediate */
6694 case 'j': /* 16 bit signed immediate */
6695 imm_reloc
= BFD_RELOC_LO16
;
6696 c
= my_getSmallExpression (&imm_expr
, s
);
6701 if (imm_expr
.X_op
== O_constant
)
6702 imm_expr
.X_add_number
=
6703 (imm_expr
.X_add_number
>> 16) & 0xffff;
6706 imm_reloc
= BFD_RELOC_HI16_S
;
6707 imm_unmatched_hi
= true;
6710 imm_reloc
= BFD_RELOC_HI16
;
6715 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
6716 || ((imm_expr
.X_add_number
< 0
6717 || imm_expr
.X_add_number
>= 0x10000)
6718 && imm_expr
.X_op
== O_constant
))
6720 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
6721 !strcmp (insn
->name
, insn
[1].name
))
6723 if (imm_expr
.X_op
!= O_constant
6724 && imm_expr
.X_op
!= O_big
)
6725 insn_error
= "absolute expression required";
6727 as_bad ("16 bit expression not in range 0..65535");
6735 /* The upper bound should be 0x8000, but
6736 unfortunately the MIPS assembler accepts numbers
6737 from 0x8000 to 0xffff and sign extends them, and
6738 we want to be compatible. We only permit this
6739 extended range for an instruction which does not
6740 provide any further alternates, since those
6741 alternates may handle other cases. People should
6742 use the numbers they mean, rather than relying on
6743 a mysterious sign extension. */
6744 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
6745 strcmp (insn
->name
, insn
[1].name
) == 0);
6750 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
6751 || ((imm_expr
.X_add_number
< -0x8000
6752 || imm_expr
.X_add_number
>= max
)
6753 && imm_expr
.X_op
== O_constant
)
6755 && imm_expr
.X_add_number
< 0
6757 && imm_expr
.X_unsigned
6758 && sizeof (imm_expr
.X_add_number
) <= 4))
6762 if (imm_expr
.X_op
!= O_constant
6763 && imm_expr
.X_op
!= O_big
)
6764 insn_error
= "absolute expression required";
6766 as_bad ("16 bit expression not in range -32768..32767");
6772 case 'o': /* 16 bit offset */
6773 c
= my_getSmallExpression (&offset_expr
, s
);
6775 /* If this value won't fit into a 16 bit offset, then go
6776 find a macro that will generate the 32 bit offset
6777 code pattern. As a special hack, we accept the
6778 difference of two local symbols as a constant. This
6779 is required to suppose embedded PIC switches, which
6780 use an instruction which looks like
6781 lw $4,$L12-$LS12($4)
6782 The problem with handling this in a more general
6783 fashion is that the macro function doesn't expect to
6784 see anything which can be handled in a single
6785 constant instruction. */
6787 && (offset_expr
.X_op
!= O_constant
6788 || offset_expr
.X_add_number
>= 0x8000
6789 || offset_expr
.X_add_number
< -0x8000)
6790 && (mips_pic
!= EMBEDDED_PIC
6791 || offset_expr
.X_op
!= O_subtract
6792 || now_seg
!= text_section
6793 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
6797 offset_reloc
= BFD_RELOC_LO16
;
6798 if (c
== 'h' || c
== 'H')
6800 assert (offset_expr
.X_op
== O_constant
);
6801 offset_expr
.X_add_number
=
6802 (offset_expr
.X_add_number
>> 16) & 0xffff;
6807 case 'p': /* pc relative offset */
6808 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
6809 my_getExpression (&offset_expr
, s
);
6813 case 'u': /* upper 16 bits */
6814 c
= my_getSmallExpression (&imm_expr
, s
);
6815 if (imm_expr
.X_op
== O_constant
6816 && (imm_expr
.X_add_number
< 0
6817 || imm_expr
.X_add_number
>= 0x10000))
6818 as_bad ("lui expression not in range 0..65535");
6819 imm_reloc
= BFD_RELOC_LO16
;
6824 if (imm_expr
.X_op
== O_constant
)
6825 imm_expr
.X_add_number
=
6826 (imm_expr
.X_add_number
>> 16) & 0xffff;
6829 imm_reloc
= BFD_RELOC_HI16_S
;
6830 imm_unmatched_hi
= true;
6833 imm_reloc
= BFD_RELOC_HI16
;
6839 case 'a': /* 26 bit address */
6840 my_getExpression (&offset_expr
, s
);
6842 offset_reloc
= BFD_RELOC_MIPS_JMP
;
6845 case 'N': /* 3 bit branch condition code */
6846 case 'M': /* 3 bit compare condition code */
6847 if (strncmp (s
, "$fcc", 4) != 0)
6857 while (isdigit (*s
));
6859 as_bad ("invalid condition code register $fcc%d", regno
);
6861 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
6863 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
6867 fprintf (stderr
, "bad char = '%c'\n", *args
);
6872 /* Args don't match. */
6873 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
6874 !strcmp (insn
->name
, insn
[1].name
))
6880 insn_error
= "illegal operands";
6885 /* This routine assembles an instruction into its binary format when
6886 assembling for the mips16. As a side effect, it sets one of the
6887 global variables imm_reloc or offset_reloc to the type of
6888 relocation to do if one of the operands is an address expression.
6889 It also sets mips16_small and mips16_ext if the user explicitly
6890 requested a small or extended instruction. */
6895 struct mips_cl_insn
*ip
;
6899 struct mips_opcode
*insn
;
6902 unsigned int lastregno
= 0;
6907 mips16_small
= false;
6910 for (s
= str
; islower (*s
); ++s
)
6922 if (s
[1] == 't' && s
[2] == ' ')
6925 mips16_small
= true;
6929 else if (s
[1] == 'e' && s
[2] == ' ')
6938 insn_error
= "unknown opcode";
6942 if (! mips16_autoextend
&& ! mips16_ext
)
6943 mips16_small
= true;
6945 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
6947 insn_error
= "unrecognized opcode";
6954 assert (strcmp (insn
->name
, str
) == 0);
6957 ip
->insn_opcode
= insn
->match
;
6958 ip
->use_extend
= false;
6959 imm_expr
.X_op
= O_absent
;
6960 imm_reloc
= BFD_RELOC_UNUSED
;
6961 offset_expr
.X_op
= O_absent
;
6962 offset_reloc
= BFD_RELOC_UNUSED
;
6963 for (args
= insn
->args
; 1; ++args
)
6970 /* In this switch statement we call break if we did not find
6971 a match, continue if we did find a match, or return if we
6980 /* Stuff the immediate value in now, if we can. */
6981 if (imm_expr
.X_op
== O_constant
6982 && imm_reloc
> BFD_RELOC_UNUSED
6983 && insn
->pinfo
!= INSN_MACRO
)
6985 mips16_immed ((char *) NULL
, 0,
6986 imm_reloc
- BFD_RELOC_UNUSED
,
6987 imm_expr
.X_add_number
, true, mips16_small
,
6988 mips16_ext
, &ip
->insn_opcode
,
6989 &ip
->use_extend
, &ip
->extend
);
6990 imm_expr
.X_op
= O_absent
;
6991 imm_reloc
= BFD_RELOC_UNUSED
;
7005 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
7008 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
7024 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
7026 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
7053 while (isdigit (*s
));
7056 as_bad ("invalid register number (%d)", regno
);
7062 if (s
[1] == 'f' && s
[2] == 'p')
7067 else if (s
[1] == 's' && s
[2] == 'p')
7072 else if (s
[1] == 'g' && s
[2] == 'p')
7077 else if (s
[1] == 'a' && s
[2] == 't')
7082 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7087 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7100 if (c
== 'v' || c
== 'w')
7102 regno
= mips16_to_32_reg_map
[lastregno
];
7116 regno
= mips32_to_16_reg_map
[regno
];
7121 regno
= ILLEGAL_REG
;
7126 regno
= ILLEGAL_REG
;
7131 regno
= ILLEGAL_REG
;
7136 if (regno
== AT
&& ! mips_noat
)
7137 as_warn ("used $at without \".set noat\"");
7144 if (regno
== ILLEGAL_REG
)
7151 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
7155 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
7158 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
7161 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
7167 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
7170 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
7171 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
7181 if (strncmp (s
, "$pc", 3) == 0)
7205 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
7207 /* This is %gprel(SYMBOL). We need to read SYMBOL,
7208 and generate the appropriate reloc. If the text
7209 inside %gprel is not a symbol name with an
7210 optional offset, then we generate a normal reloc
7211 and will probably fail later. */
7212 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
7213 if (imm_expr
.X_op
== O_symbol
)
7216 imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
7218 ip
->use_extend
= true;
7225 /* Just pick up a normal expression. */
7226 my_getExpression (&imm_expr
, s
);
7229 if (imm_expr
.X_op
== O_register
)
7231 /* What we thought was an expression turned out to
7234 if (s
[0] == '(' && args
[1] == '(')
7236 /* It looks like the expression was omitted
7237 before a register indirection, which means
7238 that the expression is implicitly zero. We
7239 still set up imm_expr, so that we handle
7240 explicit extensions correctly. */
7241 imm_expr
.X_op
= O_constant
;
7242 imm_expr
.X_add_number
= 0;
7243 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7250 /* We need to relax this instruction. */
7251 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7260 /* We use offset_reloc rather than imm_reloc for the PC
7261 relative operands. This lets macros with both
7262 immediate and address operands work correctly. */
7263 my_getExpression (&offset_expr
, s
);
7265 if (offset_expr
.X_op
== O_register
)
7268 /* We need to relax this instruction. */
7269 offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7273 case '6': /* break code */
7274 my_getExpression (&imm_expr
, s
);
7275 check_absolute_expr (ip
, &imm_expr
);
7276 if ((unsigned long) imm_expr
.X_add_number
> 63)
7278 as_warn ("Invalid value for `%s' (%lu)",
7280 (unsigned long) imm_expr
.X_add_number
);
7281 imm_expr
.X_add_number
&= 0x3f;
7283 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
7284 imm_expr
.X_op
= O_absent
;
7288 case 'a': /* 26 bit address */
7289 my_getExpression (&offset_expr
, s
);
7291 offset_reloc
= BFD_RELOC_MIPS16_JMP
;
7292 ip
->insn_opcode
<<= 16;
7295 case 'l': /* register list for entry macro */
7296 case 'L': /* register list for exit macro */
7306 int freg
, reg1
, reg2
;
7308 while (*s
== ' ' || *s
== ',')
7312 as_bad ("can't parse register list");
7324 while (isdigit (*s
))
7346 as_bad ("invalid register list");
7351 while (isdigit (*s
))
7358 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
7363 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
7368 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
7369 mask
|= (reg2
- 3) << 3;
7370 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
7371 mask
|= (reg2
- 15) << 1;
7372 else if (reg1
== 31 && reg2
== 31)
7376 as_bad ("invalid register list");
7380 /* The mask is filled in in the opcode table for the
7381 benefit of the disassembler. We remove it before
7382 applying the actual mask. */
7383 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
7384 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
7394 /* Args don't match. */
7395 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
7396 strcmp (insn
->name
, insn
[1].name
) == 0)
7403 insn_error
= "illegal operands";
7409 /* This structure holds information we know about a mips16 immediate
7412 struct mips16_immed_operand
7414 /* The type code used in the argument string in the opcode table. */
7416 /* The number of bits in the short form of the opcode. */
7418 /* The number of bits in the extended form of the opcode. */
7420 /* The amount by which the short form is shifted when it is used;
7421 for example, the sw instruction has a shift count of 2. */
7423 /* The amount by which the short form is shifted when it is stored
7424 into the instruction code. */
7426 /* Non-zero if the short form is unsigned. */
7428 /* Non-zero if the extended form is unsigned. */
7430 /* Non-zero if the value is PC relative. */
7434 /* The mips16 immediate operand types. */
7436 static const struct mips16_immed_operand mips16_immed_operands
[] =
7438 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
7439 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
7440 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
7441 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
7442 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
7443 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7444 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7445 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7446 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7447 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
7448 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7449 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7450 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7451 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
7452 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
7453 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
7454 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
7455 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
7456 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
7457 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
7458 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
7461 #define MIPS16_NUM_IMMED \
7462 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
7464 /* Handle a mips16 instruction with an immediate value. This or's the
7465 small immediate value into *INSN. It sets *USE_EXTEND to indicate
7466 whether an extended value is needed; if one is needed, it sets
7467 *EXTEND to the value. The argument type is TYPE. The value is VAL.
7468 If SMALL is true, an unextended opcode was explicitly requested.
7469 If EXT is true, an extended opcode was explicitly requested. If
7470 WARN is true, warn if EXT does not match reality. */
7473 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
7482 unsigned long *insn
;
7483 boolean
*use_extend
;
7484 unsigned short *extend
;
7486 register const struct mips16_immed_operand
*op
;
7487 int mintiny
, maxtiny
;
7490 op
= mips16_immed_operands
;
7491 while (op
->type
!= type
)
7494 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
7499 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
7502 maxtiny
= 1 << op
->nbits
;
7507 maxtiny
= (1 << op
->nbits
) - 1;
7512 mintiny
= - (1 << (op
->nbits
- 1));
7513 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
7516 /* Branch offsets have an implicit 0 in the lowest bit. */
7517 if (type
== 'p' || type
== 'q')
7520 if ((val
& ((1 << op
->shift
) - 1)) != 0
7521 || val
< (mintiny
<< op
->shift
)
7522 || val
> (maxtiny
<< op
->shift
))
7527 if (warn
&& ext
&& ! needext
)
7528 as_warn_where (file
, line
, "extended operand requested but not required");
7529 if (small
&& needext
)
7530 as_bad_where (file
, line
, "invalid unextended operand value");
7532 if (small
|| (! ext
&& ! needext
))
7536 *use_extend
= false;
7537 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
7538 insnval
<<= op
->op_shift
;
7543 long minext
, maxext
;
7549 maxext
= (1 << op
->extbits
) - 1;
7553 minext
= - (1 << (op
->extbits
- 1));
7554 maxext
= (1 << (op
->extbits
- 1)) - 1;
7556 if (val
< minext
|| val
> maxext
)
7557 as_bad_where (file
, line
,
7558 "operand value out of range for instruction");
7561 if (op
->extbits
== 16)
7563 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
7566 else if (op
->extbits
== 15)
7568 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
7573 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
7577 *extend
= (unsigned short) extval
;
7586 my_getSmallExpression (ep
, str
)
7597 ((str
[1] == 'h' && str
[2] == 'i')
7598 || (str
[1] == 'H' && str
[2] == 'I')
7599 || (str
[1] == 'l' && str
[2] == 'o'))
7611 * A small expression may be followed by a base register.
7612 * Scan to the end of this operand, and then back over a possible
7613 * base register. Then scan the small expression up to that
7614 * point. (Based on code in sparc.c...)
7616 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
7618 if (sp
- 4 >= str
&& sp
[-1] == RP
)
7620 if (isdigit (sp
[-2]))
7622 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
7624 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
7630 else if (sp
- 5 >= str
7633 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
7634 || (sp
[-3] == 's' && sp
[-2] == 'p')
7635 || (sp
[-3] == 'g' && sp
[-2] == 'p')
7636 || (sp
[-3] == 'a' && sp
[-2] == 't')))
7642 /* no expression means zero offset */
7645 /* %xx(reg) is an error */
7646 ep
->X_op
= O_absent
;
7651 ep
->X_op
= O_constant
;
7654 ep
->X_add_symbol
= NULL
;
7655 ep
->X_op_symbol
= NULL
;
7656 ep
->X_add_number
= 0;
7661 my_getExpression (ep
, str
);
7668 my_getExpression (ep
, str
);
7669 return c
; /* => %hi or %lo encountered */
7673 my_getExpression (ep
, str
)
7679 save_in
= input_line_pointer
;
7680 input_line_pointer
= str
;
7682 expr_end
= input_line_pointer
;
7683 input_line_pointer
= save_in
;
7686 /* Turn a string in input_line_pointer into a floating point constant
7687 of type type, and store the appropriate bytes in *litP. The number
7688 of LITTLENUMS emitted is stored in *sizeP . An error message is
7689 returned, or NULL on OK. */
7692 md_atof (type
, litP
, sizeP
)
7698 LITTLENUM_TYPE words
[4];
7714 return "bad call to md_atof";
7717 t
= atof_ieee (input_line_pointer
, type
, words
);
7719 input_line_pointer
= t
;
7723 if (! target_big_endian
)
7725 for (i
= prec
- 1; i
>= 0; i
--)
7727 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
7733 for (i
= 0; i
< prec
; i
++)
7735 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
7744 md_number_to_chars (buf
, val
, n
)
7749 if (target_big_endian
)
7750 number_to_chars_bigendian (buf
, val
, n
);
7752 number_to_chars_littleendian (buf
, val
, n
);
7755 CONST
char *md_shortopts
= "O::g::G:";
7757 struct option md_longopts
[] = {
7758 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
7759 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
7760 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
7761 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
7762 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
7763 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
7764 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
7765 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
7766 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
7767 #define OPTION_MCPU (OPTION_MD_BASE + 5)
7768 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
7769 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
7770 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
7771 #define OPTION_TRAP (OPTION_MD_BASE + 9)
7772 {"trap", no_argument
, NULL
, OPTION_TRAP
},
7773 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
7774 #define OPTION_BREAK (OPTION_MD_BASE + 10)
7775 {"break", no_argument
, NULL
, OPTION_BREAK
},
7776 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
7777 #define OPTION_EB (OPTION_MD_BASE + 11)
7778 {"EB", no_argument
, NULL
, OPTION_EB
},
7779 #define OPTION_EL (OPTION_MD_BASE + 12)
7780 {"EL", no_argument
, NULL
, OPTION_EL
},
7781 #define OPTION_M4650 (OPTION_MD_BASE + 13)
7782 {"m4650", no_argument
, NULL
, OPTION_M4650
},
7783 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
7784 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
7785 #define OPTION_M4010 (OPTION_MD_BASE + 15)
7786 {"m4010", no_argument
, NULL
, OPTION_M4010
},
7787 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
7788 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
7789 #define OPTION_M4100 (OPTION_MD_BASE + 17)
7790 {"m4100", no_argument
, NULL
, OPTION_M4100
},
7791 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
7792 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
7793 #define OPTION_MIPS16 (OPTION_MD_BASE + 22)
7794 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
7795 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23)
7796 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
7797 /* start-sanitize-5900 */
7798 #define OPTION_M5900 (OPTION_MD_BASE + 24)
7799 {"m5900", no_argument
, NULL
, OPTION_M5900
},
7800 #define OPTION_NO_M5900 (OPTION_MD_BASE + 25)
7801 {"no-m5900", no_argument
, NULL
, OPTION_NO_M5900
},
7802 /* end-sanitize-5900 */
7804 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
7805 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
7806 #define OPTION_XGOT (OPTION_MD_BASE + 19)
7807 #define OPTION_32 (OPTION_MD_BASE + 20)
7808 #define OPTION_64 (OPTION_MD_BASE + 21)
7810 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
7811 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
7812 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
7813 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
7814 {"32", no_argument
, NULL
, OPTION_32
},
7815 {"64", no_argument
, NULL
, OPTION_64
},
7818 {NULL
, no_argument
, NULL
, 0}
7820 size_t md_longopts_size
= sizeof(md_longopts
);
7823 md_parse_option (c
, arg
)
7838 target_big_endian
= 1;
7842 target_big_endian
= 0;
7846 if (arg
&& arg
[1] == '0')
7856 mips_debug
= atoi (arg
);
7857 /* When the MIPS assembler sees -g or -g2, it does not do
7858 optimizations which limit full symbolic debugging. We take
7859 that to be equivalent to -O0. */
7860 if (mips_debug
== 2)
7892 /* Identify the processor type */
7894 if (strcmp (p
, "default") == 0
7895 || strcmp (p
, "DEFAULT") == 0)
7901 /* We need to cope with the various "vr" prefixes for the 4300
7903 if (*p
== 'v' || *p
== 'V')
7909 if (*p
== 'r' || *p
== 'R')
7916 if (strcmp (p
, "10000") == 0
7917 || strcmp (p
, "10k") == 0
7918 || strcmp (p
, "10K") == 0)
7923 if (strcmp (p
, "2000") == 0
7924 || strcmp (p
, "2k") == 0
7925 || strcmp (p
, "2K") == 0)
7930 if (strcmp (p
, "3000") == 0
7931 || strcmp (p
, "3k") == 0
7932 || strcmp (p
, "3K") == 0)
7937 if (strcmp (p
, "4000") == 0
7938 || strcmp (p
, "4k") == 0
7939 || strcmp (p
, "4K") == 0)
7941 else if (strcmp (p
, "4100") == 0)
7947 else if (strcmp (p
, "4300") == 0)
7949 else if (strcmp (p
, "4400") == 0)
7951 else if (strcmp (p
, "4600") == 0)
7953 else if (strcmp (p
, "4650") == 0)
7959 else if (strcmp (p
, "4010") == 0)
7968 if (strcmp (p
, "5000") == 0
7969 || strcmp (p
, "5k") == 0
7970 || strcmp (p
, "5K") == 0)
7972 /* start-sanitize-r5900 */
7973 else if (strcmp (p
, "5900") == 0)
7975 /* end-sanitize-r5900 */
7979 if (strcmp (p
, "6000") == 0
7980 || strcmp (p
, "6k") == 0
7981 || strcmp (p
, "6K") == 0)
7986 if (strcmp (p
, "8000") == 0
7987 || strcmp (p
, "8k") == 0
7988 || strcmp (p
, "8K") == 0)
7993 if (strcmp (p
, "orion") == 0)
7998 if (sv
&& mips_cpu
!= 4300 && mips_cpu
!= 4100 && mips_cpu
!= 5000)
8000 as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg
);
8006 as_bad ("invalid architecture -mcpu=%s", arg
);
8017 case OPTION_NO_M4650
:
8025 case OPTION_NO_M4010
:
8033 case OPTION_NO_M4100
:
8037 /* start-sanitize-r5900 */
8042 case OPTION_NO_M5900
:
8045 /* end-sanitize-r5900 */
8049 mips_no_prev_insn ();
8052 case OPTION_NO_MIPS16
:
8054 mips_no_prev_insn ();
8057 case OPTION_MEMBEDDED_PIC
:
8058 mips_pic
= EMBEDDED_PIC
;
8059 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
8061 as_bad ("-G may not be used with embedded PIC code");
8064 g_switch_value
= 0x7fffffff;
8067 /* When generating ELF code, we permit -KPIC and -call_shared to
8068 select SVR4_PIC, and -non_shared to select no PIC. This is
8069 intended to be compatible with Irix 5. */
8070 case OPTION_CALL_SHARED
:
8071 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
8073 as_bad ("-call_shared is supported only for ELF format");
8076 mips_pic
= SVR4_PIC
;
8077 if (g_switch_seen
&& g_switch_value
!= 0)
8079 as_bad ("-G may not be used with SVR4 PIC code");
8085 case OPTION_NON_SHARED
:
8086 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
8088 as_bad ("-non_shared is supported only for ELF format");
8094 /* The -xgot option tells the assembler to use 32 offsets when
8095 accessing the got in SVR4_PIC mode. It is for Irix
8102 if (! USE_GLOBAL_POINTER_OPT
)
8104 as_bad ("-G is not supported for this configuration");
8107 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
8109 as_bad ("-G may not be used with SVR4 or embedded PIC code");
8113 g_switch_value
= atoi (arg
);
8117 /* The -32 and -64 options tell the assembler to output the 32
8118 bit or the 64 bit MIPS ELF format. */
8125 const char **list
, **l
;
8127 list
= bfd_target_list ();
8128 for (l
= list
; *l
!= NULL
; l
++)
8129 if (strcmp (*l
, "elf64-bigmips") == 0
8130 || strcmp (*l
, "elf64-littlemips") == 0)
8133 as_fatal ("No compiled in support for 64 bit object file format");
8147 md_show_usage (stream
)
8152 -membedded-pic generate embedded position independent code\n\
8153 -EB generate big endian output\n\
8154 -EL generate little endian output\n\
8155 -g, -g2 do not remove uneeded NOPs or swap branches\n\
8156 -G NUM allow referencing objects up to NUM bytes\n\
8157 implicitly with the gp register [default 8]\n");
8159 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
8160 -mips2, -mcpu=r6000 generate code for r6000\n\
8161 -mips3, -mcpu=r4000 generate code for r4000\n\
8162 -mips4, -mcpu=r8000 generate code for r8000\n\
8163 -mcpu=vr4300 generate code for vr4300\n\
8164 -mcpu=vr4100 generate code for vr4100\n\
8165 -m4650 permit R4650 instructions\n\
8166 -no-m4650 do not permit R4650 instructions\n\
8167 -m4010 permit R4010 instructions\n\
8168 -no-m4010 do not permit R4010 instructions\n\
8169 -m4100 permit VR4100 instructions\n\
8170 -no-m4100 do not permit VR4100 instructions\n");
8172 -mips16 generate mips16 instructions\n\
8173 -no-mips16 do not generate mips16 instructions\n");
8175 -O0 remove unneeded NOPs, do not swap branches\n\
8176 -O remove unneeded NOPs and swap branches\n\
8177 --trap, --no-break trap exception on div by 0 and mult overflow\n\
8178 --break, --no-trap break exception on div by 0 and mult overflow\n");
8181 -KPIC, -call_shared generate SVR4 position independent code\n\
8182 -non_shared do not generate position independent code\n\
8183 -xgot assume a 32 bit GOT\n\
8184 -32 create 32 bit object file (default)\n\
8185 -64 create 64 bit object file\n");
8190 md_pcrel_from (fixP
)
8193 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
8194 && fixP
->fx_addsy
!= (symbolS
*) NULL
8195 && ! S_IS_DEFINED (fixP
->fx_addsy
))
8197 /* This makes a branch to an undefined symbol be a branch to the
8198 current location. */
8202 /* return the address of the delay slot */
8203 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8206 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
8207 reloc for a cons. We could use the definition there, except that
8208 we want to handle 64 bit relocs specially. */
8211 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
8214 unsigned int nbytes
;
8218 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
8220 if (nbytes
== 8 && ! mips_64
)
8222 if (target_big_endian
)
8228 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
8229 as_bad ("Unsupported reloc size %d", nbytes
);
8231 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
8234 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
8237 /* Sort any unmatched HI16_S relocs so that they immediately precede
8238 the corresponding LO reloc. This is called before md_apply_fix and
8239 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
8240 explicit use of the %hi modifier. */
8245 struct mips_hi_fixup
*l
;
8247 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
8249 segment_info_type
*seginfo
;
8252 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
8254 /* Check quickly whether the next fixup happens to be a matching
8256 if (l
->fixp
->fx_next
!= NULL
8257 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
8258 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
8259 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
8262 /* Look through the fixups for this segment for a matching %lo.
8263 When we find one, move the %hi just in front of it. We do
8264 this in two passes. In the first pass, we try to find a
8265 unique %lo. In the second pass, we permit multiple %hi
8266 relocs for a single %lo (this is a GNU extension). */
8267 seginfo
= seg_info (l
->seg
);
8268 for (pass
= 0; pass
< 2; pass
++)
8273 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
8275 /* Check whether this is a %lo fixup which matches l->fixp. */
8276 if (f
->fx_r_type
== BFD_RELOC_LO16
8277 && f
->fx_addsy
== l
->fixp
->fx_addsy
8278 && f
->fx_offset
== l
->fixp
->fx_offset
8281 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
8282 || prev
->fx_addsy
!= f
->fx_addsy
8283 || prev
->fx_offset
!= f
->fx_offset
))
8287 /* Move l->fixp before f. */
8288 for (pf
= &seginfo
->fix_root
;
8290 pf
= &(*pf
)->fx_next
)
8291 assert (*pf
!= NULL
);
8293 *pf
= l
->fixp
->fx_next
;
8295 l
->fixp
->fx_next
= f
;
8297 seginfo
->fix_root
= l
->fixp
;
8299 prev
->fx_next
= l
->fixp
;
8311 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
8312 "Unmatched %%hi reloc");
8317 /* When generating embedded PIC code we need to use a special
8318 relocation to represent the difference of two symbols in the .text
8319 section (switch tables use a difference of this sort). See
8320 include/coff/mips.h for details. This macro checks whether this
8321 fixup requires the special reloc. */
8322 #define SWITCH_TABLE(fixp) \
8323 ((fixp)->fx_r_type == BFD_RELOC_32 \
8324 && (fixp)->fx_addsy != NULL \
8325 && (fixp)->fx_subsy != NULL \
8326 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
8327 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
8329 /* When generating embedded PIC code we must keep all PC relative
8330 relocations, in case the linker has to relax a call. We also need
8331 to keep relocations for switch table entries. */
8335 mips_force_relocation (fixp
)
8338 return (mips_pic
== EMBEDDED_PIC
8340 || SWITCH_TABLE (fixp
)
8341 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
8342 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
8345 /* Apply a fixup to the object file. */
8348 md_apply_fix (fixP
, valueP
)
8355 assert (fixP
->fx_size
== 4
8356 || fixP
->fx_r_type
== BFD_RELOC_16
8357 || fixP
->fx_r_type
== BFD_RELOC_64
);
8361 /* If we aren't adjusting this fixup to be against the section
8362 symbol, we need to adjust the value. */
8364 if (fixP
->fx_addsy
!= NULL
8365 && OUTPUT_FLAVOR
== bfd_target_elf_flavour
8366 && S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
)
8368 value
-= S_GET_VALUE (fixP
->fx_addsy
);
8369 if (value
!= 0 && ! fixP
->fx_pcrel
)
8371 /* In this case, the bfd_install_relocation routine will
8372 incorrectly add the symbol value back in. We just want
8373 the addend to appear in the object file. */
8374 value
-= S_GET_VALUE (fixP
->fx_addsy
);
8379 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
8381 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
8384 switch (fixP
->fx_r_type
)
8386 case BFD_RELOC_MIPS_JMP
:
8387 case BFD_RELOC_HI16
:
8388 case BFD_RELOC_HI16_S
:
8389 case BFD_RELOC_MIPS_GPREL
:
8390 case BFD_RELOC_MIPS_LITERAL
:
8391 case BFD_RELOC_MIPS_CALL16
:
8392 case BFD_RELOC_MIPS_GOT16
:
8393 case BFD_RELOC_MIPS_GPREL32
:
8394 case BFD_RELOC_MIPS_GOT_HI16
:
8395 case BFD_RELOC_MIPS_GOT_LO16
:
8396 case BFD_RELOC_MIPS_CALL_HI16
:
8397 case BFD_RELOC_MIPS_CALL_LO16
:
8398 case BFD_RELOC_MIPS16_GPREL
:
8400 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8401 "Invalid PC relative reloc");
8402 /* Nothing needed to do. The value comes from the reloc entry */
8405 case BFD_RELOC_MIPS16_JMP
:
8406 /* We currently always generate a reloc against a symbol, which
8407 means that we don't want an addend even if the symbol is
8409 fixP
->fx_addnumber
= 0;
8412 case BFD_RELOC_PCREL_HI16_S
:
8413 /* The addend for this is tricky if it is internal, so we just
8414 do everything here rather than in bfd_perform_relocation. */
8415 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
8417 /* For an external symbol adjust by the address to make it
8418 pcrel_offset. We use the address of the RELLO reloc
8419 which follows this one. */
8420 value
+= (fixP
->fx_next
->fx_frag
->fr_address
8421 + fixP
->fx_next
->fx_where
);
8426 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8427 if (target_big_endian
)
8429 md_number_to_chars (buf
, value
, 2);
8432 case BFD_RELOC_PCREL_LO16
:
8433 /* The addend for this is tricky if it is internal, so we just
8434 do everything here rather than in bfd_perform_relocation. */
8435 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
8436 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
8437 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8438 if (target_big_endian
)
8440 md_number_to_chars (buf
, value
, 2);
8444 /* This is handled like BFD_RELOC_32, but we output a sign
8445 extended value if we are only 32 bits. */
8447 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
8449 if (8 <= sizeof (valueT
))
8450 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8457 w1
= w2
= fixP
->fx_where
;
8458 if (target_big_endian
)
8462 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
8463 if ((value
& 0x80000000) != 0)
8467 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
8473 /* If we are deleting this reloc entry, we must fill in the
8474 value now. This can happen if we have a .word which is not
8475 resolved when it appears but is later defined. We also need
8476 to fill in the value if this is an embedded PIC switch table
8479 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
8480 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8485 /* If we are deleting this reloc entry, we must fill in the
8487 assert (fixP
->fx_size
== 2);
8489 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8493 case BFD_RELOC_LO16
:
8494 /* When handling an embedded PIC switch statement, we can wind
8495 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
8498 if (value
< -0x8000 || value
> 0x7fff)
8499 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8500 "relocation overflow");
8501 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8502 if (target_big_endian
)
8504 md_number_to_chars (buf
, value
, 2);
8508 case BFD_RELOC_16_PCREL_S2
:
8510 * We need to save the bits in the instruction since fixup_segment()
8511 * might be deleting the relocation entry (i.e., a branch within
8512 * the current segment).
8514 if ((value
& 0x3) != 0)
8515 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8516 "Branch to odd address (%lx)", value
);
8519 /* update old instruction data */
8520 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
8521 if (target_big_endian
)
8522 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
8524 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
8526 if (value
>= -0x8000 && value
< 0x8000)
8527 insn
|= value
& 0xffff;
8530 /* The branch offset is too large. If this is an
8531 unconditional branch, and we are not generating PIC code,
8532 we can convert it to an absolute jump instruction. */
8533 if (mips_pic
== NO_PIC
8535 && fixP
->fx_frag
->fr_address
>= text_section
->vma
8536 && (fixP
->fx_frag
->fr_address
8537 < text_section
->vma
+ text_section
->_raw_size
)
8538 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
8539 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
8540 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
8542 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
8543 insn
= 0x0c000000; /* jal */
8545 insn
= 0x08000000; /* j */
8546 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
8548 fixP
->fx_addsy
= section_symbol (text_section
);
8549 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
8553 /* FIXME. It would be possible in principle to handle
8554 conditional branches which overflow. They could be
8555 transformed into a branch around a jump. This would
8556 require setting up variant frags for each different
8557 branch type. The native MIPS assembler attempts to
8558 handle these cases, but it appears to do it
8560 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8561 "Relocation overflow");
8565 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
8580 const struct mips_opcode
*p
;
8581 int treg
, sreg
, dreg
, shamt
;
8586 for (i
= 0; i
< NUMOPCODES
; ++i
)
8588 p
= &mips_opcodes
[i
];
8589 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
8591 printf ("%08lx %s\t", oc
, p
->name
);
8592 treg
= (oc
>> 16) & 0x1f;
8593 sreg
= (oc
>> 21) & 0x1f;
8594 dreg
= (oc
>> 11) & 0x1f;
8595 shamt
= (oc
>> 6) & 0x1f;
8597 for (args
= p
->args
;; ++args
)
8608 printf ("%c", *args
);
8612 assert (treg
== sreg
);
8613 printf ("$%d,$%d", treg
, sreg
);
8618 printf ("$%d", dreg
);
8623 printf ("$%d", treg
);
8627 printf ("0x%x", treg
);
8632 printf ("$%d", sreg
);
8636 printf ("0x%08lx", oc
& 0x1ffffff);
8648 printf ("$%d", shamt
);
8659 printf ("%08lx UNDEFINED\n", oc
);
8670 name
= input_line_pointer
;
8671 c
= get_symbol_end ();
8672 p
= (symbolS
*) symbol_find_or_make (name
);
8673 *input_line_pointer
= c
;
8677 /* Align the current frag to a given power of two. The MIPS assembler
8678 also automatically adjusts any preceding label. */
8681 mips_align (to
, fill
, label
)
8686 mips_emit_delays (false);
8687 frag_align (to
, fill
);
8688 record_alignment (now_seg
, to
);
8691 assert (S_GET_SEGMENT (label
) == now_seg
);
8692 label
->sy_frag
= frag_now
;
8693 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
8697 /* Align to a given power of two. .align 0 turns off the automatic
8698 alignment used by the data creating pseudo-ops. */
8705 register long temp_fill
;
8706 long max_alignment
= 15;
8710 o Note that the assembler pulls down any immediately preceeding label
8711 to the aligned address.
8712 o It's not documented but auto alignment is reinstated by
8713 a .align pseudo instruction.
8714 o Note also that after auto alignment is turned off the mips assembler
8715 issues an error on attempt to assemble an improperly aligned data item.
8720 temp
= get_absolute_expression ();
8721 if (temp
> max_alignment
)
8722 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
8725 as_warn ("Alignment negative: 0 assumed.");
8728 if (*input_line_pointer
== ',')
8730 input_line_pointer
++;
8731 temp_fill
= get_absolute_expression ();
8738 mips_align (temp
, (int) temp_fill
,
8739 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
8746 demand_empty_rest_of_line ();
8750 mips_flush_pending_output ()
8752 mips_emit_delays (false);
8753 mips_clear_insn_labels ();
8762 /* When generating embedded PIC code, we only use the .text, .lit8,
8763 .sdata and .sbss sections. We change the .data and .rdata
8764 pseudo-ops to use .sdata. */
8765 if (mips_pic
== EMBEDDED_PIC
8766 && (sec
== 'd' || sec
== 'r'))
8769 mips_emit_delays (false);
8779 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
8780 demand_empty_rest_of_line ();
8784 if (USE_GLOBAL_POINTER_OPT
)
8786 seg
= subseg_new (RDATA_SECTION_NAME
,
8787 (subsegT
) get_absolute_expression ());
8788 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8790 bfd_set_section_flags (stdoutput
, seg
,
8796 if (strcmp (TARGET_OS
, "elf") != 0)
8797 bfd_set_section_alignment (stdoutput
, seg
, 4);
8799 demand_empty_rest_of_line ();
8803 as_bad ("No read only data section in this object file format");
8804 demand_empty_rest_of_line ();
8810 if (USE_GLOBAL_POINTER_OPT
)
8812 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
8813 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8815 bfd_set_section_flags (stdoutput
, seg
,
8816 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
8818 if (strcmp (TARGET_OS
, "elf") != 0)
8819 bfd_set_section_alignment (stdoutput
, seg
, 4);
8821 demand_empty_rest_of_line ();
8826 as_bad ("Global pointers not supported; recompile -G 0");
8827 demand_empty_rest_of_line ();
8836 mips_enable_auto_align ()
8847 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
8848 mips_emit_delays (false);
8849 if (log_size
> 0 && auto_align
)
8850 mips_align (log_size
, 0, label
);
8851 mips_clear_insn_labels ();
8852 cons (1 << log_size
);
8861 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
8863 mips_emit_delays (false);
8867 mips_align (3, 0, label
);
8869 mips_align (2, 0, label
);
8871 mips_clear_insn_labels ();
8876 /* Handle .globl. We need to override it because on Irix 5 you are
8879 where foo is an undefined symbol, to mean that foo should be
8880 considered to be the address of a function. */
8891 name
= input_line_pointer
;
8892 c
= get_symbol_end ();
8893 symbolP
= symbol_find_or_make (name
);
8894 *input_line_pointer
= c
;
8897 /* On Irix 5, every global symbol that is not explicitly labelled as
8898 being a function is apparently labelled as being an object. */
8901 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
8906 secname
= input_line_pointer
;
8907 c
= get_symbol_end ();
8908 sec
= bfd_get_section_by_name (stdoutput
, secname
);
8910 as_bad ("%s: no such section", secname
);
8911 *input_line_pointer
= c
;
8913 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
8914 flag
= BSF_FUNCTION
;
8917 symbolP
->bsym
->flags
|= flag
;
8919 S_SET_EXTERNAL (symbolP
);
8920 demand_empty_rest_of_line ();
8930 opt
= input_line_pointer
;
8931 c
= get_symbol_end ();
8935 /* FIXME: What does this mean? */
8937 else if (strncmp (opt
, "pic", 3) == 0)
8945 mips_pic
= SVR4_PIC
;
8947 as_bad (".option pic%d not supported", i
);
8949 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
8951 if (g_switch_seen
&& g_switch_value
!= 0)
8952 as_warn ("-G may not be used with SVR4 PIC code");
8954 bfd_set_gp_size (stdoutput
, 0);
8958 as_warn ("Unrecognized option \"%s\"", opt
);
8960 *input_line_pointer
= c
;
8961 demand_empty_rest_of_line ();
8968 char *name
= input_line_pointer
, ch
;
8970 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
8971 input_line_pointer
++;
8972 ch
= *input_line_pointer
;
8973 *input_line_pointer
= '\0';
8975 if (strcmp (name
, "reorder") == 0)
8979 prev_insn_unreordered
= 1;
8980 prev_prev_insn_unreordered
= 1;
8984 else if (strcmp (name
, "noreorder") == 0)
8986 mips_emit_delays (true);
8988 mips_any_noreorder
= 1;
8990 else if (strcmp (name
, "at") == 0)
8994 else if (strcmp (name
, "noat") == 0)
8998 else if (strcmp (name
, "macro") == 0)
9000 mips_warn_about_macros
= 0;
9002 else if (strcmp (name
, "nomacro") == 0)
9004 if (mips_noreorder
== 0)
9005 as_bad ("`noreorder' must be set before `nomacro'");
9006 mips_warn_about_macros
= 1;
9008 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
9012 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
9016 else if (strcmp (name
, "bopt") == 0)
9020 else if (strcmp (name
, "nobopt") == 0)
9024 else if (strcmp (name
, "mips16") == 0
9025 || strcmp (name
, "MIPS-16") == 0)
9027 else if (strcmp (name
, "nomips16") == 0
9028 || strcmp (name
, "noMIPS-16") == 0)
9030 else if (strncmp (name
, "mips", 4) == 0)
9034 /* Permit the user to change the ISA on the fly. Needless to
9035 say, misuse can cause serious problems. */
9036 isa
= atoi (name
+ 4);
9038 mips_isa
= file_mips_isa
;
9039 else if (isa
< 1 || isa
> 4)
9040 as_bad ("unknown ISA level");
9044 else if (strcmp (name
, "autoextend") == 0)
9045 mips16_autoextend
= 1;
9046 else if (strcmp (name
, "noautoextend") == 0)
9047 mips16_autoextend
= 0;
9050 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
9052 *input_line_pointer
= ch
;
9053 demand_empty_rest_of_line ();
9056 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
9057 .option pic2. It means to generate SVR4 PIC calls. */
9063 mips_pic
= SVR4_PIC
;
9064 if (USE_GLOBAL_POINTER_OPT
)
9066 if (g_switch_seen
&& g_switch_value
!= 0)
9067 as_warn ("-G may not be used with SVR4 PIC code");
9070 bfd_set_gp_size (stdoutput
, 0);
9071 demand_empty_rest_of_line ();
9074 /* Handle the .cpload pseudo-op. This is used when generating SVR4
9075 PIC code. It sets the $gp register for the function based on the
9076 function address, which is in the register named in the argument.
9077 This uses a relocation against _gp_disp, which is handled specially
9078 by the linker. The result is:
9079 lui $gp,%hi(_gp_disp)
9080 addiu $gp,$gp,%lo(_gp_disp)
9081 addu $gp,$gp,.cpload argument
9082 The .cpload argument is normally $25 == $t9. */
9091 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
9092 if (mips_pic
!= SVR4_PIC
)
9098 /* .cpload should be a in .set noreorder section. */
9099 if (mips_noreorder
== 0)
9100 as_warn (".cpload not in noreorder section");
9103 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
9104 ex
.X_op_symbol
= NULL
;
9105 ex
.X_add_number
= 0;
9107 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
9108 ex
.X_add_symbol
->bsym
->flags
|= BSF_OBJECT
;
9110 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
9111 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
9112 (int) BFD_RELOC_LO16
);
9114 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
9115 GP
, GP
, tc_get_register (0));
9117 demand_empty_rest_of_line ();
9120 /* Handle the .cprestore pseudo-op. This stores $gp into a given
9121 offset from $sp. The offset is remembered, and after making a PIC
9122 call $gp is restored from that location. */
9125 s_cprestore (ignore
)
9131 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
9132 if (mips_pic
!= SVR4_PIC
)
9138 mips_cprestore_offset
= get_absolute_expression ();
9140 ex
.X_op
= O_constant
;
9141 ex
.X_add_symbol
= NULL
;
9142 ex
.X_op_symbol
= NULL
;
9143 ex
.X_add_number
= mips_cprestore_offset
;
9145 macro_build ((char *) NULL
, &icnt
, &ex
,
9146 mips_isa
< 3 ? "sw" : "sd",
9147 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
9149 demand_empty_rest_of_line ();
9152 /* Handle the .gpword pseudo-op. This is used when generating PIC
9153 code. It generates a 32 bit GP relative reloc. */
9163 /* When not generating PIC code, this is treated as .word. */
9164 if (mips_pic
!= SVR4_PIC
)
9170 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
9171 mips_emit_delays (true);
9173 mips_align (2, 0, label
);
9174 mips_clear_insn_labels ();
9178 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
9180 as_bad ("Unsupported use of .gpword");
9181 ignore_rest_of_line ();
9185 md_number_to_chars (p
, (valueT
) 0, 4);
9186 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
9187 BFD_RELOC_MIPS_GPREL32
);
9189 demand_empty_rest_of_line ();
9192 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
9193 tables in SVR4 PIC code. */
9202 /* This is ignored when not generating SVR4 PIC code. */
9203 if (mips_pic
!= SVR4_PIC
)
9209 /* Add $gp to the register named as an argument. */
9210 reg
= tc_get_register (0);
9211 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
9212 mips_isa
< 3 ? "addu" : "daddu",
9213 "d,v,t", reg
, reg
, GP
);
9215 demand_empty_rest_of_line ();
9218 /* Parse a register string into a number. Called from the ECOFF code
9219 to parse .frame. The argument is non-zero if this is the frame
9220 register, so that we can record it in mips_frame_reg. */
9223 tc_get_register (frame
)
9229 if (*input_line_pointer
++ != '$')
9231 as_warn ("expected `$'");
9234 else if (isdigit ((unsigned char) *input_line_pointer
))
9236 reg
= get_absolute_expression ();
9237 if (reg
< 0 || reg
>= 32)
9239 as_warn ("Bad register number");
9245 if (strncmp (input_line_pointer
, "fp", 2) == 0)
9247 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
9249 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
9251 else if (strncmp (input_line_pointer
, "at", 2) == 0)
9255 as_warn ("Unrecognized register name");
9258 input_line_pointer
+= 2;
9261 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
9266 md_section_align (seg
, addr
)
9270 int align
= bfd_get_section_alignment (stdoutput
, seg
);
9273 /* We don't need to align ELF sections to the full alignment.
9274 However, Irix 5 may prefer that we align them at least to a 16
9275 byte boundary. We don't bother to align the sections if we are
9276 targeted for an embedded system. */
9277 if (strcmp (TARGET_OS
, "elf") == 0)
9283 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
9286 /* Utility routine, called from above as well. If called while the
9287 input file is still being read, it's only an approximation. (For
9288 example, a symbol may later become defined which appeared to be
9289 undefined earlier.) */
9292 nopic_need_relax (sym
)
9298 if (USE_GLOBAL_POINTER_OPT
)
9300 const char *symname
;
9303 /* Find out whether this symbol can be referenced off the GP
9304 register. It can be if it is smaller than the -G size or if
9305 it is in the .sdata or .sbss section. Certain symbols can
9306 not be referenced off the GP, although it appears as though
9308 symname
= S_GET_NAME (sym
);
9309 if (symname
!= (const char *) NULL
9310 && (strcmp (symname
, "eprol") == 0
9311 || strcmp (symname
, "etext") == 0
9312 || strcmp (symname
, "_gp") == 0
9313 || strcmp (symname
, "edata") == 0
9314 || strcmp (symname
, "_fbss") == 0
9315 || strcmp (symname
, "_fdata") == 0
9316 || strcmp (symname
, "_ftext") == 0
9317 || strcmp (symname
, "end") == 0
9318 || strcmp (symname
, "_gp_disp") == 0))
9320 else if (! S_IS_DEFINED (sym
)
9322 #ifndef NO_ECOFF_DEBUGGING
9323 || (sym
->ecoff_extern_size
!= 0
9324 && sym
->ecoff_extern_size
<= g_switch_value
)
9326 || (S_GET_VALUE (sym
) != 0
9327 && S_GET_VALUE (sym
) <= g_switch_value
)))
9331 const char *segname
;
9333 segname
= segment_name (S_GET_SEGMENT (sym
));
9334 assert (strcmp (segname
, ".lit8") != 0
9335 && strcmp (segname
, ".lit4") != 0);
9336 change
= (strcmp (segname
, ".sdata") != 0
9337 && strcmp (segname
, ".sbss") != 0);
9342 /* We are not optimizing for the GP register. */
9346 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
9347 extended opcode. SEC is the section the frag is in. */
9350 mips16_extended_frag (fragp
, sec
, stretch
)
9356 register const struct mips16_immed_operand
*op
;
9358 int mintiny
, maxtiny
;
9361 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
9363 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
9366 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
9367 op
= mips16_immed_operands
;
9368 while (op
->type
!= type
)
9371 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9376 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9379 maxtiny
= 1 << op
->nbits
;
9384 maxtiny
= (1 << op
->nbits
) - 1;
9389 mintiny
= - (1 << (op
->nbits
- 1));
9390 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9393 /* We can't call S_GET_VALUE here, because we don't want to lock in
9394 a particular frag address. */
9395 if (fragp
->fr_symbol
->sy_value
.X_op
== O_constant
)
9397 val
= (fragp
->fr_symbol
->sy_value
.X_add_number
9398 + fragp
->fr_symbol
->sy_frag
->fr_address
);
9399 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
9401 else if (fragp
->fr_symbol
->sy_value
.X_op
== O_symbol
9402 && (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_op
9405 val
= (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_add_number
9406 + fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_frag
->fr_address
9407 + fragp
->fr_symbol
->sy_value
.X_add_number
9408 + fragp
->fr_symbol
->sy_frag
->fr_address
);
9409 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
->sy_value
.X_add_symbol
);
9418 /* We won't have the section when we are called from
9419 mips_relax_frag. However, we will always have been called
9420 from md_estimate_size_before_relax first. If this is a
9421 branch to a different section, we mark it as such. If SEC is
9422 NULL, and the frag is not marked, then it must be a branch to
9423 the same section. */
9426 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
9434 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9436 /* FIXME: We should support this, and let the linker
9437 catch branches and loads that are out of range. */
9438 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
9439 "unsupported PC relative reference to different section");
9445 /* In this case, we know for sure that the symbol fragment is in
9446 the same section. If the fr_address of the symbol fragment
9447 is greater then the address of this fragment we want to add
9448 in STRETCH in order to get a better estimate of the address.
9449 This particularly matters because of the shift bits. */
9451 && fragp
->fr_symbol
->sy_frag
->fr_address
>= fragp
->fr_address
)
9455 /* Adjust stretch for any alignment frag. */
9456 for (f
= fragp
; f
!= fragp
->fr_symbol
->sy_frag
; f
= f
->fr_next
)
9459 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
9462 stretch
= - ((- stretch
)
9463 & ~ ((1 << (int) f
->fr_offset
) - 1));
9465 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
9473 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
9475 /* The base address rules are complicated. The base address of
9476 a branch is the following instruction. The base address of a
9477 PC relative load or add is the instruction itself, but if it
9478 is extended add 2, and if it is in a delay slot (in which
9479 case it can not be extended) use the address of the
9480 instruction whose delay slot it is in. */
9481 if (type
== 'p' || type
== 'q')
9484 /* Ignore the low bit in the target, since it will be set
9485 for a text label. */
9489 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
9491 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
9494 /* If we are currently assuming that this frag should be
9495 extended, then the current address is two bytes higher. */
9496 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9499 val
-= addr
& ~ ((1 << op
->shift
) - 1);
9501 /* Branch offsets have an implicit 0 in the lowest bit. */
9502 if (type
== 'p' || type
== 'q')
9505 /* If any of the shifted bits are set, we must use an extended
9506 opcode. If the address depends on the size of this
9507 instruction, this can lead to a loop, so we arrange to always
9508 use an extended opcode. We only check this when we are in
9509 the main relaxation loop, when SEC is NULL. */
9510 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
9513 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9517 /* If we are about to mark a frag as extended because the value
9518 is precisely maxtiny + 1, then there is a chance of an
9519 infinite loop as in the following code:
9524 In this case when the la is extended, foo is 0x3fc bytes
9525 away, so the la can be shrunk, but then foo is 0x400 away, so
9526 the la must be extended. To avoid this loop, we mark the
9527 frag as extended if it was small, and is about to become
9528 extended with a value of maxtiny + 1. */
9529 if (val
== ((maxtiny
+ 1) << op
->shift
)
9530 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
9534 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9538 else if (symsec
!= absolute_section
&& sec
!= NULL
)
9539 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, "unsupported relocation");
9541 if ((val
& ((1 << op
->shift
) - 1)) != 0
9542 || val
< (mintiny
<< op
->shift
)
9543 || val
> (maxtiny
<< op
->shift
))
9549 /* Estimate the size of a frag before relaxing. Unless this is the
9550 mips16, we are not really relaxing here, and the final size is
9551 encoded in the subtype information. For the mips16, we have to
9552 decide whether we are using an extended opcode or not. */
9556 md_estimate_size_before_relax (fragp
, segtype
)
9562 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
9564 if (mips16_extended_frag (fragp
, segtype
, 0))
9566 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
9571 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
9576 if (mips_pic
== NO_PIC
)
9578 change
= nopic_need_relax (fragp
->fr_symbol
);
9580 else if (mips_pic
== SVR4_PIC
)
9582 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
9584 /* This must duplicate the test in adjust_reloc_syms. */
9585 change
= (symsec
!= &bfd_und_section
9586 && symsec
!= &bfd_abs_section
9587 && ! bfd_is_com_section (symsec
));
9594 /* Record the offset to the first reloc in the fr_opcode field.
9595 This lets md_convert_frag and tc_gen_reloc know that the code
9596 must be expanded. */
9597 fragp
->fr_opcode
= (fragp
->fr_literal
9599 - RELAX_OLD (fragp
->fr_subtype
)
9600 + RELAX_RELOC1 (fragp
->fr_subtype
));
9601 /* FIXME: This really needs as_warn_where. */
9602 if (RELAX_WARN (fragp
->fr_subtype
))
9603 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
9609 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
9612 /* This is called to see whether a reloc against a defined symbol
9613 should be converted into a reloc against a section. Don't adjust
9614 MIPS16 jump relocations, so we don't have to worry about the format
9615 of the offset in the .o file. Don't adjust relocations against
9616 mips16 symbols, so that the linker can find them if it needs to set
9620 mips_fix_adjustable (fixp
)
9623 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
9625 if (fixp
->fx_addsy
== NULL
)
9628 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
9629 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
)
9635 /* Translate internal representation of relocation info to BFD target
9639 tc_gen_reloc (section
, fixp
)
9643 static arelent
*retval
[4];
9645 bfd_reloc_code_real_type code
;
9647 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
9650 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
9651 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9653 if (mips_pic
== EMBEDDED_PIC
9654 && SWITCH_TABLE (fixp
))
9656 /* For a switch table entry we use a special reloc. The addend
9657 is actually the difference between the reloc address and the
9659 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
9660 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
9661 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
9662 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
9664 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
9666 /* We use a special addend for an internal RELLO reloc. */
9667 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
9668 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
9670 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
9672 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
9674 assert (fixp
->fx_next
!= NULL
9675 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
9676 /* We use a special addend for an internal RELHI reloc. The
9677 reloc is relative to the RELLO; adjust the addend
9679 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
9680 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
9681 + fixp
->fx_next
->fx_where
9682 - S_GET_VALUE (fixp
->fx_subsy
));
9684 reloc
->addend
= (fixp
->fx_addnumber
9685 + fixp
->fx_next
->fx_frag
->fr_address
9686 + fixp
->fx_next
->fx_where
);
9688 else if (fixp
->fx_pcrel
== 0)
9689 reloc
->addend
= fixp
->fx_addnumber
;
9692 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
9693 /* A gruesome hack which is a result of the gruesome gas reloc
9695 reloc
->addend
= reloc
->address
;
9697 reloc
->addend
= -reloc
->address
;
9700 /* If this is a variant frag, we may need to adjust the existing
9701 reloc and generate a new one. */
9702 if (fixp
->fx_frag
->fr_opcode
!= NULL
9703 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
9704 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
9705 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
9706 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
9707 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
9708 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
9709 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
9713 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
9715 /* If this is not the last reloc in this frag, then we have two
9716 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
9717 CALL_HI16/CALL_LO16, both of which are being replaced. Let
9718 the second one handle all of them. */
9719 if (fixp
->fx_next
!= NULL
9720 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
9722 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
9723 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
9724 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
9725 && (fixp
->fx_next
->fx_r_type
9726 == BFD_RELOC_MIPS_GOT_LO16
))
9727 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
9728 && (fixp
->fx_next
->fx_r_type
9729 == BFD_RELOC_MIPS_CALL_LO16
)));
9734 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
9735 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9736 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
9738 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
9739 reloc2
->address
= (reloc
->address
9740 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
9741 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
9742 reloc2
->addend
= fixp
->fx_addnumber
;
9743 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
9744 assert (reloc2
->howto
!= NULL
);
9746 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
9750 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
9753 reloc3
->address
+= 4;
9756 if (mips_pic
== NO_PIC
)
9758 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
9759 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
9761 else if (mips_pic
== SVR4_PIC
)
9763 switch (fixp
->fx_r_type
)
9767 case BFD_RELOC_MIPS_GOT16
:
9769 case BFD_RELOC_MIPS_CALL16
:
9770 case BFD_RELOC_MIPS_GOT_LO16
:
9771 case BFD_RELOC_MIPS_CALL_LO16
:
9772 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
9780 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
9781 fixup_segment converted a non-PC relative reloc into a PC
9782 relative reloc. In such a case, we need to convert the reloc
9784 code
= fixp
->fx_r_type
;
9790 code
= BFD_RELOC_8_PCREL
;
9793 code
= BFD_RELOC_16_PCREL
;
9796 code
= BFD_RELOC_32_PCREL
;
9799 code
= BFD_RELOC_64_PCREL
;
9801 case BFD_RELOC_8_PCREL
:
9802 case BFD_RELOC_16_PCREL
:
9803 case BFD_RELOC_32_PCREL
:
9804 case BFD_RELOC_64_PCREL
:
9805 case BFD_RELOC_16_PCREL_S2
:
9806 case BFD_RELOC_PCREL_HI16_S
:
9807 case BFD_RELOC_PCREL_LO16
:
9810 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9811 "Cannot make %s relocation PC relative",
9812 bfd_get_reloc_code_name (code
));
9816 /* To support a PC relative reloc when generating embedded PIC code
9817 for ECOFF, we use a Cygnus extension. We check for that here to
9818 make sure that we don't let such a reloc escape normally. */
9819 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
9820 && code
== BFD_RELOC_16_PCREL_S2
9821 && mips_pic
!= EMBEDDED_PIC
)
9822 reloc
->howto
= NULL
;
9824 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
9826 if (reloc
->howto
== NULL
)
9828 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9829 "Can not represent %s relocation in this object file format",
9830 bfd_get_reloc_code_name (code
));
9837 /* Relax a machine dependent frag. This returns the amount by which
9838 the current size of the frag should change. */
9841 mips_relax_frag (fragp
, stretch
)
9845 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
9848 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
9850 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9852 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
9857 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9859 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
9866 /* Convert a machine dependent frag. */
9869 md_convert_frag (abfd
, asec
, fragp
)
9877 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
9880 register const struct mips16_immed_operand
*op
;
9886 unsigned short extend
;
9888 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
9889 op
= mips16_immed_operands
;
9890 while (op
->type
!= type
)
9893 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9904 resolve_symbol_value (fragp
->fr_symbol
);
9905 val
= S_GET_VALUE (fragp
->fr_symbol
);
9910 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
9912 /* The rules for the base address of a PC relative reloc are
9913 complicated; see mips16_extended_frag. */
9914 if (type
== 'p' || type
== 'q')
9917 /* Ignore the low bit in the target, since it will be
9918 set for a text label. */
9922 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
9924 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
9929 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
9932 /* Make sure the section winds up with the alignment we have
9935 record_alignment (asec
, op
->shift
);
9938 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
9940 if (target_big_endian
)
9941 insn
= bfd_getb16 (buf
);
9943 insn
= bfd_getl16 (buf
);
9945 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
9946 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
9947 small
, ext
, &insn
, &use_extend
, &extend
);
9951 md_number_to_chars (buf
, 0xf000 | extend
, 2);
9956 md_number_to_chars (buf
, insn
, 2);
9962 if (fragp
->fr_opcode
== NULL
)
9965 old
= RELAX_OLD (fragp
->fr_subtype
);
9966 new = RELAX_NEW (fragp
->fr_subtype
);
9967 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
9970 memcpy (fixptr
- old
, fixptr
, new);
9972 fragp
->fr_fix
+= new - old
;
9978 /* This function is called after the relocs have been generated.
9979 We've been storing mips16 text labels as odd. Here we convert them
9980 back to even for the convenience of the debugger. */
9983 mips_frob_file_after_relocs ()
9986 unsigned int count
, i
;
9988 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9991 syms
= bfd_get_outsymbols (stdoutput
);
9992 count
= bfd_get_symcount (stdoutput
);
9993 for (i
= 0; i
< count
; i
++, syms
++)
9995 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
9996 && ((*syms
)->value
& 1) != 0)
9998 (*syms
)->value
&= ~1;
9999 /* If the symbol has an odd size, it was probably computed
10000 incorrectly, so adjust that as well. */
10001 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
10002 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
10009 /* This function is called whenever a label is defined. It is used
10010 when handling branch delays; if a branch has a label, we assume we
10011 can not move it. */
10014 mips_define_label (sym
)
10017 struct insn_label_list
*l
;
10019 if (free_insn_labels
== NULL
)
10020 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
10023 l
= free_insn_labels
;
10024 free_insn_labels
= l
->next
;
10028 l
->next
= insn_labels
;
10032 /* Decide whether a label is local. This is called by LOCAL_LABEL.
10033 In order to work with gcc when using mips-tfile, we must keep all
10034 local labels. However, in other cases, we want to discard them,
10035 since they are useless. */
10038 mips_local_label (name
)
10041 #ifndef NO_ECOFF_DEBUGGING
10042 if (ECOFF_DEBUGGING
10044 && ! ecoff_debugging_seen
)
10046 /* We were called with -g, but we didn't see any debugging
10047 information. That may mean that gcc is smuggling debugging
10048 information through to mips-tfile, in which case we must
10049 generate all local labels. */
10054 /* Here it's OK to discard local labels. */
10056 return name
[0] == '$';
10059 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10061 /* Some special processing for a MIPS ELF file. */
10064 mips_elf_final_processing ()
10066 /* Write out the register information. */
10071 s
.ri_gprmask
= mips_gprmask
;
10072 s
.ri_cprmask
[0] = mips_cprmask
[0];
10073 s
.ri_cprmask
[1] = mips_cprmask
[1];
10074 s
.ri_cprmask
[2] = mips_cprmask
[2];
10075 s
.ri_cprmask
[3] = mips_cprmask
[3];
10076 /* The gp_value field is set by the MIPS ELF backend. */
10078 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
10079 ((Elf32_External_RegInfo
*)
10080 mips_regmask_frag
));
10084 Elf64_Internal_RegInfo s
;
10086 s
.ri_gprmask
= mips_gprmask
;
10088 s
.ri_cprmask
[0] = mips_cprmask
[0];
10089 s
.ri_cprmask
[1] = mips_cprmask
[1];
10090 s
.ri_cprmask
[2] = mips_cprmask
[2];
10091 s
.ri_cprmask
[3] = mips_cprmask
[3];
10092 /* The gp_value field is set by the MIPS ELF backend. */
10094 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
10095 ((Elf64_External_RegInfo
*)
10096 mips_regmask_frag
));
10099 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
10100 sort of BFD interface for this. */
10101 if (mips_any_noreorder
)
10102 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
10103 if (mips_pic
!= NO_PIC
)
10104 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
10107 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
10109 /* These functions should really be defined by the object file format,
10110 since they are related to debugging information. However, this
10111 code has to work for the a.out format, which does not define them,
10112 so we provide simple versions here. These don't actually generate
10113 any debugging information, but they do simple checking and someday
10114 somebody may make them useful. */
10118 struct loc
*loc_next
;
10119 unsigned long loc_fileno
;
10120 unsigned long loc_lineno
;
10121 unsigned long loc_offset
;
10122 unsigned short loc_delta
;
10123 unsigned short loc_count
;
10130 typedef struct proc
10132 struct proc
*proc_next
;
10133 struct symbol
*proc_isym
;
10134 struct symbol
*proc_end
;
10135 unsigned long proc_reg_mask
;
10136 unsigned long proc_reg_offset
;
10137 unsigned long proc_fpreg_mask
;
10138 unsigned long proc_fpreg_offset
;
10139 unsigned long proc_frameoffset
;
10140 unsigned long proc_framereg
;
10141 unsigned long proc_pcreg
;
10143 struct file
*proc_file
;
10148 typedef struct file
10150 struct file
*file_next
;
10151 unsigned long file_fileno
;
10152 struct symbol
*file_symbol
;
10153 struct symbol
*file_end
;
10154 struct proc
*file_proc
;
10159 static struct obstack proc_frags
;
10160 static procS
*proc_lastP
;
10161 static procS
*proc_rootP
;
10162 static int numprocs
;
10167 obstack_begin (&proc_frags
, 0x2000);
10173 /* check for premature end, nesting errors, etc */
10174 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
10175 as_warn ("missing `.end' at end of assembly");
10184 if (*input_line_pointer
== '-')
10186 ++input_line_pointer
;
10189 if (!isdigit (*input_line_pointer
))
10190 as_bad ("Expected simple number.");
10191 if (input_line_pointer
[0] == '0')
10193 if (input_line_pointer
[1] == 'x')
10195 input_line_pointer
+= 2;
10196 while (isxdigit (*input_line_pointer
))
10199 val
|= hex_value (*input_line_pointer
++);
10201 return negative
? -val
: val
;
10205 ++input_line_pointer
;
10206 while (isdigit (*input_line_pointer
))
10209 val
|= *input_line_pointer
++ - '0';
10211 return negative
? -val
: val
;
10214 if (!isdigit (*input_line_pointer
))
10216 printf (" *input_line_pointer == '%c' 0x%02x\n",
10217 *input_line_pointer
, *input_line_pointer
);
10218 as_warn ("Invalid number");
10221 while (isdigit (*input_line_pointer
))
10224 val
+= *input_line_pointer
++ - '0';
10226 return negative
? -val
: val
;
10229 /* The .file directive; just like the usual .file directive, but there
10230 is an initial number which is the ECOFF file index. */
10238 line
= get_number ();
10243 /* The .end directive. */
10251 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
10254 demand_empty_rest_of_line ();
10258 if (now_seg
!= text_section
)
10259 as_warn (".end not in text section");
10262 as_warn (".end and no .ent seen yet.");
10268 assert (S_GET_NAME (p
));
10269 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
10270 as_warn (".end symbol does not match .ent symbol.");
10273 proc_lastP
->proc_end
= (symbolS
*) 1;
10276 /* The .aent and .ent directives. */
10286 symbolP
= get_symbol ();
10287 if (*input_line_pointer
== ',')
10288 input_line_pointer
++;
10289 SKIP_WHITESPACE ();
10290 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
10291 number
= get_number ();
10292 if (now_seg
!= text_section
)
10293 as_warn (".ent or .aent not in text section.");
10295 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
10296 as_warn ("missing `.end'");
10300 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
10301 procP
->proc_isym
= symbolP
;
10302 procP
->proc_reg_mask
= 0;
10303 procP
->proc_reg_offset
= 0;
10304 procP
->proc_fpreg_mask
= 0;
10305 procP
->proc_fpreg_offset
= 0;
10306 procP
->proc_frameoffset
= 0;
10307 procP
->proc_framereg
= 0;
10308 procP
->proc_pcreg
= 0;
10309 procP
->proc_end
= NULL
;
10310 procP
->proc_next
= NULL
;
10312 proc_lastP
->proc_next
= procP
;
10314 proc_rootP
= procP
;
10315 proc_lastP
= procP
;
10318 demand_empty_rest_of_line ();
10321 /* The .frame directive. */
10334 frame_reg
= tc_get_register (1);
10335 if (*input_line_pointer
== ',')
10336 input_line_pointer
++;
10337 frame_off
= get_absolute_expression ();
10338 if (*input_line_pointer
== ',')
10339 input_line_pointer
++;
10340 pcreg
= tc_get_register (0);
10342 /* bob third eye */
10343 assert (proc_rootP
);
10344 proc_rootP
->proc_framereg
= frame_reg
;
10345 proc_rootP
->proc_frameoffset
= frame_off
;
10346 proc_rootP
->proc_pcreg
= pcreg
;
10347 /* bob macho .frame */
10349 /* We don't have to write out a frame stab for unoptimized code. */
10350 if (!(frame_reg
== FP
&& frame_off
== 0))
10353 as_warn ("No .ent for .frame to use.");
10354 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
10355 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
10356 S_SET_TYPE (symP
, N_RMASK
);
10357 S_SET_OTHER (symP
, 0);
10358 S_SET_DESC (symP
, 0);
10359 symP
->sy_forward
= proc_lastP
->proc_isym
;
10360 /* bob perhaps I should have used pseudo set */
10362 demand_empty_rest_of_line ();
10366 /* The .fmask and .mask directives. */
10373 char str
[100], *strP
;
10379 mask
= get_number ();
10380 if (*input_line_pointer
== ',')
10381 input_line_pointer
++;
10382 off
= get_absolute_expression ();
10384 /* bob only for coff */
10385 assert (proc_rootP
);
10386 if (reg_type
== 'F')
10388 proc_rootP
->proc_fpreg_mask
= mask
;
10389 proc_rootP
->proc_fpreg_offset
= off
;
10393 proc_rootP
->proc_reg_mask
= mask
;
10394 proc_rootP
->proc_reg_offset
= off
;
10397 /* bob macho .mask + .fmask */
10399 /* We don't have to write out a mask stab if no saved regs. */
10403 as_warn ("No .ent for .mask to use.");
10405 for (i
= 0; i
< 32; i
++)
10409 sprintf (strP
, "%c%d,", reg_type
, i
);
10410 strP
+= strlen (strP
);
10414 sprintf (strP
, ";%d,", off
);
10415 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
10416 S_SET_TYPE (symP
, N_RMASK
);
10417 S_SET_OTHER (symP
, 0);
10418 S_SET_DESC (symP
, 0);
10419 symP
->sy_forward
= proc_lastP
->proc_isym
;
10420 /* bob perhaps I should have used pseudo set */
10425 /* The .loc directive. */
10436 assert (now_seg
== text_section
);
10438 lineno
= get_number ();
10439 addroff
= frag_now_fix ();
10441 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
10442 S_SET_TYPE (symbolP
, N_SLINE
);
10443 S_SET_OTHER (symbolP
, 0);
10444 S_SET_DESC (symbolP
, lineno
);
10445 symbolP
->sy_segment
= now_seg
;