1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 1995, 1996 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
38 #include "opcode/mips.h"
41 /* Clean up namespace so we can include obj-elf.h too. */
42 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
43 #undef OBJ_PROCESS_STAB
49 #undef TARGET_SYMBOL_FIELDS
51 #undef obj_frob_file_after_relocs
52 #undef obj_frob_symbol
54 #undef obj_sec_sym_ok_for_reloc
57 /* Fix any of them that we actually care about. */
59 #define OUTPUT_FLAVOR mips_output_flavor()
66 #ifndef ECOFF_DEBUGGING
67 #define NO_ECOFF_DEBUGGING
68 #define ECOFF_DEBUGGING 0
73 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
74 static char *mips_regmask_frag
;
79 #define PIC_CALL_REG 25
87 #define ILLEGAL_REG (32)
89 extern int target_big_endian
;
91 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
92 32 bit ABI. This has no meaning for ECOFF. */
95 /* The default target format to use. */
99 switch (OUTPUT_FLAVOR
)
101 case bfd_target_aout_flavour
:
102 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
103 case bfd_target_ecoff_flavour
:
104 return target_big_endian
? "ecoff-bigmips" : "ecoff-littlemips";
105 case bfd_target_elf_flavour
:
106 return (target_big_endian
107 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
108 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
114 /* The name of the readonly data section. */
115 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
117 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
119 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
123 /* These variables are filled in with the masks of registers used.
124 The object format code reads them and puts them in the appropriate
126 unsigned long mips_gprmask
;
127 unsigned long mips_cprmask
[4];
129 /* MIPS ISA (Instruction Set Architecture) level (may be changed
130 temporarily using .set mipsN). */
131 static int mips_isa
= -1;
133 /* MIPS ISA we are using for this output file. */
134 static int file_mips_isa
;
136 /* Whether we are assembling for the mips16 processor. */
137 static int mips16
= -1;
139 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
140 static int mips_cpu
= -1;
142 /* Whether the 4650 instructions (mad/madu) are permitted. */
143 static int mips_4650
= -1;
145 /* Whether the 4010 instructions are permitted. */
146 static int mips_4010
= -1;
148 /* Whether the 4100 MADD16 and DMADD16 are permitted. */
149 static int mips_4100
= -1;
151 /* Whether the processor uses hardware interlocks, and thus does not
152 require nops to be inserted. */
153 static int interlocks
= -1;
155 /* As with "interlocks" this is used by hardware that has FP
156 (co-processor) interlocks. */
157 static int cop_interlocks
= -1;
159 /* MIPS PIC level. */
163 /* Do not generate PIC code. */
166 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
167 not sure what it is supposed to do. */
170 /* Generate PIC code as in the SVR4 MIPS ABI. */
173 /* Generate PIC code without using a global offset table: the data
174 segment has a maximum size of 64K, all data references are off
175 the $gp register, and all text references are PC relative. This
176 is used on some embedded systems. */
180 static enum mips_pic_level mips_pic
;
182 /* 1 if we should generate 32 bit offsets from the GP register in
183 SVR4_PIC mode. Currently has no meaning in other modes. */
184 static int mips_big_got
;
186 /* 1 if trap instructions should used for overflow rather than break
188 static int mips_trap
;
190 /* 1 if we should autoextend mips16 instructions. */
191 static int mips16_autoextend
= 1;
193 static int mips_warn_about_macros
;
194 static int mips_noreorder
;
195 static int mips_any_noreorder
;
196 static int mips_nomove
;
197 static int mips_noat
;
198 static int mips_nobopt
;
200 /* The size of the small data section. */
201 static int g_switch_value
= 8;
202 /* Whether the -G option was used. */
203 static int g_switch_seen
= 0;
208 /* If we can determine in advance that GP optimization won't be
209 possible, we can skip the relaxation stuff that tries to produce
210 GP-relative references. This makes delay slot optimization work
213 This function can only provide a guess, but it seems to work for
214 gcc output. If it guesses wrong, the only loss should be in
215 efficiency; it shouldn't introduce any bugs.
217 I don't know if a fix is needed for the SVR4_PIC mode. I've only
218 fixed it for the non-PIC mode. KR 95/04/07 */
219 static int nopic_need_relax
PARAMS ((symbolS
*));
221 /* handle of the OPCODE hash table */
222 static struct hash_control
*op_hash
= NULL
;
224 /* The opcode hash table we use for the mips16. */
225 static struct hash_control
*mips16_op_hash
= NULL
;
227 /* This array holds the chars that always start a comment. If the
228 pre-processor is disabled, these aren't very useful */
229 const char comment_chars
[] = "#";
231 /* This array holds the chars that only start a comment at the beginning of
232 a line. If the line seems to have the form '# 123 filename'
233 .line and .file directives will appear in the pre-processed output */
234 /* Note that input_file.c hand checks for '#' at the beginning of the
235 first line of the input file. This is because the compiler outputs
236 #NO_APP at the beginning of its output. */
237 /* Also note that C style comments are always supported. */
238 const char line_comment_chars
[] = "#";
240 /* This array holds machine specific line separator characters. */
241 const char line_separator_chars
[] = "";
243 /* Chars that can be used to separate mant from exp in floating point nums */
244 const char EXP_CHARS
[] = "eE";
246 /* Chars that mean this number is a floating point constant */
249 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
251 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
252 changed in read.c . Ideally it shouldn't have to know about it at all,
253 but nothing is ideal around here.
256 static char *insn_error
;
258 static int byte_order
;
260 static int auto_align
= 1;
262 /* When outputting SVR4 PIC code, the assembler needs to know the
263 offset in the stack frame from which to restore the $gp register.
264 This is set by the .cprestore pseudo-op, and saved in this
266 static offsetT mips_cprestore_offset
= -1;
268 /* This is the register which holds the stack frame, as set by the
269 .frame pseudo-op. This is needed to implement .cprestore. */
270 static int mips_frame_reg
= SP
;
272 /* To output NOP instructions correctly, we need to keep information
273 about the previous two instructions. */
275 /* Whether we are optimizing. The default value of 2 means to remove
276 unneeded NOPs and swap branch instructions when possible. A value
277 of 1 means to not swap branches. A value of 0 means to always
279 static int mips_optimize
= 2;
281 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
282 equivalent to seeing no -g option at all. */
283 static int mips_debug
= 0;
285 /* The previous instruction. */
286 static struct mips_cl_insn prev_insn
;
288 /* The instruction before prev_insn. */
289 static struct mips_cl_insn prev_prev_insn
;
291 /* If we don't want information for prev_insn or prev_prev_insn, we
292 point the insn_mo field at this dummy integer. */
293 static const struct mips_opcode dummy_opcode
= { 0 };
295 /* Non-zero if prev_insn is valid. */
296 static int prev_insn_valid
;
298 /* The frag for the previous instruction. */
299 static struct frag
*prev_insn_frag
;
301 /* The offset into prev_insn_frag for the previous instruction. */
302 static long prev_insn_where
;
304 /* The reloc type for the previous instruction, if any. */
305 static bfd_reloc_code_real_type prev_insn_reloc_type
;
307 /* The reloc for the previous instruction, if any. */
308 static fixS
*prev_insn_fixp
;
310 /* Non-zero if the previous instruction was in a delay slot. */
311 static int prev_insn_is_delay_slot
;
313 /* Non-zero if the previous instruction was in a .set noreorder. */
314 static int prev_insn_unreordered
;
316 /* Non-zero if the previous instruction uses an extend opcode (if
318 static int prev_insn_extended
;
320 /* Non-zero if the previous previous instruction was in a .set
322 static int prev_prev_insn_unreordered
;
324 /* For ECOFF and ELF, relocations against symbols are done in two
325 parts, with a HI relocation and a LO relocation. Each relocation
326 has only 16 bits of space to store an addend. This means that in
327 order for the linker to handle carries correctly, it must be able
328 to locate both the HI and the LO relocation. This means that the
329 relocations must appear in order in the relocation table.
331 In order to implement this, we keep track of each unmatched HI
332 relocation. We then sort them so that they immediately precede the
333 corresponding LO relocation. */
338 struct mips_hi_fixup
*next
;
341 /* The section this fixup is in. */
345 /* The list of unmatched HI relocs. */
347 static struct mips_hi_fixup
*mips_hi_fixup_list
;
349 /* Map normal MIPS register numbers to mips16 register numbers. */
351 #define X ILLEGAL_REG
352 static const int mips32_to_16_reg_map
[] =
354 X
, X
, 2, 3, 4, 5, 6, 7,
355 X
, X
, X
, X
, X
, X
, X
, X
,
356 0, 1, X
, X
, X
, X
, X
, X
,
357 X
, X
, X
, X
, X
, X
, X
, X
361 /* Map mips16 register numbers to normal MIPS register numbers. */
363 static const int mips16_to_32_reg_map
[] =
365 16, 17, 2, 3, 4, 5, 6, 7
368 /* Since the MIPS does not have multiple forms of PC relative
369 instructions, we do not have to do relaxing as is done on other
370 platforms. However, we do have to handle GP relative addressing
371 correctly, which turns out to be a similar problem.
373 Every macro that refers to a symbol can occur in (at least) two
374 forms, one with GP relative addressing and one without. For
375 example, loading a global variable into a register generally uses
376 a macro instruction like this:
378 If i can be addressed off the GP register (this is true if it is in
379 the .sbss or .sdata section, or if it is known to be smaller than
380 the -G argument) this will generate the following instruction:
382 This instruction will use a GPREL reloc. If i can not be addressed
383 off the GP register, the following instruction sequence will be used:
386 In this case the first instruction will have a HI16 reloc, and the
387 second reloc will have a LO16 reloc. Both relocs will be against
390 The issue here is that we may not know whether i is GP addressable
391 until after we see the instruction that uses it. Therefore, we
392 want to be able to choose the final instruction sequence only at
393 the end of the assembly. This is similar to the way other
394 platforms choose the size of a PC relative instruction only at the
397 When generating position independent code we do not use GP
398 addressing in quite the same way, but the issue still arises as
399 external symbols and local symbols must be handled differently.
401 We handle these issues by actually generating both possible
402 instruction sequences. The longer one is put in a frag_var with
403 type rs_machine_dependent. We encode what to do with the frag in
404 the subtype field. We encode (1) the number of existing bytes to
405 replace, (2) the number of new bytes to use, (3) the offset from
406 the start of the existing bytes to the first reloc we must generate
407 (that is, the offset is applied from the start of the existing
408 bytes after they are replaced by the new bytes, if any), (4) the
409 offset from the start of the existing bytes to the second reloc,
410 (5) whether a third reloc is needed (the third reloc is always four
411 bytes after the second reloc), and (6) whether to warn if this
412 variant is used (this is sometimes needed if .set nomacro or .set
413 noat is in effect). All these numbers are reasonably small.
415 Generating two instruction sequences must be handled carefully to
416 ensure that delay slots are handled correctly. Fortunately, there
417 are a limited number of cases. When the second instruction
418 sequence is generated, append_insn is directed to maintain the
419 existing delay slot information, so it continues to apply to any
420 code after the second instruction sequence. This means that the
421 second instruction sequence must not impose any requirements not
422 required by the first instruction sequence.
424 These variant frags are then handled in functions called by the
425 machine independent code. md_estimate_size_before_relax returns
426 the final size of the frag. md_convert_frag sets up the final form
427 of the frag. tc_gen_reloc adjust the first reloc and adds a second
429 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
433 | (((reloc1) + 64) << 9) \
434 | (((reloc2) + 64) << 2) \
435 | ((reloc3) ? (1 << 1) : 0) \
437 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
438 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
439 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
440 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
441 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
442 #define RELAX_WARN(i) ((i) & 1)
444 /* For mips16 code, we use an entirely different form of relaxation.
445 mips16 supports two versions of most instructions which take
446 immediate values: a small one which takes some small value, and a
447 larger one which takes a 16 bit value. Since branches also follow
448 this pattern, relaxing these values is required.
450 We can assemble both mips16 and normal MIPS code in a single
451 object. Therefore, we need to support this type of relaxation at
452 the same time that we support the relaxation described above. We
453 use the high bit of the subtype field to distinguish these cases.
455 The information we store for this type of relaxation is the
456 argument code found in the opcode file for this relocation, whether
457 the user explicitly requested a small or extended form, and whether
458 the relocation is in a jump or jal delay slot. That tells us the
459 size of the value, and how it should be stored. We also store
460 whether the fragment is considered to be extended or not. We also
461 store whether this is known to be a branch to a different section,
462 whether we have tried to relax this frag yet, and whether we have
463 ever extended a PC relative fragment because of a shift count. */
464 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
467 | ((small) ? 0x100 : 0) \
468 | ((ext) ? 0x200 : 0) \
469 | ((dslot) ? 0x400 : 0) \
470 | ((jal_dslot) ? 0x800 : 0))
471 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
472 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
473 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
474 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
475 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
476 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
477 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
478 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
479 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
480 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
481 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
482 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
484 /* Prototypes for static functions. */
487 #define internalError() \
488 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
490 #define internalError() as_fatal ("MIPS internal Error");
493 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
495 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
496 unsigned int reg
, enum mips_regclass
class));
497 static int reg_needs_delay
PARAMS ((int));
498 static void append_insn
PARAMS ((char *place
,
499 struct mips_cl_insn
* ip
,
501 bfd_reloc_code_real_type r
,
503 static void mips_no_prev_insn
PARAMS ((void));
504 static void mips_emit_delays
PARAMS ((boolean
));
506 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
507 const char *name
, const char *fmt
,
510 static void macro_build ();
512 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
513 const char *, const char *,
515 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
516 expressionS
* ep
, int regnum
));
517 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
518 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
520 static void load_register
PARAMS ((int *, int, expressionS
*, int));
521 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
522 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
523 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
524 #ifdef LOSING_COMPILER
525 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
527 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
528 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
529 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
530 boolean
, boolean
, unsigned long *,
531 boolean
*, unsigned short *));
532 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
533 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
534 static symbolS
*get_symbol
PARAMS ((void));
535 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
536 static void s_align
PARAMS ((int));
537 static void s_change_sec
PARAMS ((int));
538 static void s_cons
PARAMS ((int));
539 static void s_float_cons
PARAMS ((int));
540 static void s_mips_globl
PARAMS ((int));
541 static void s_option
PARAMS ((int));
542 static void s_mipsset
PARAMS ((int));
543 static void s_abicalls
PARAMS ((int));
544 static void s_cpload
PARAMS ((int));
545 static void s_cprestore
PARAMS ((int));
546 static void s_gpword
PARAMS ((int));
547 static void s_cpadd
PARAMS ((int));
548 static void md_obj_begin
PARAMS ((void));
549 static void md_obj_end
PARAMS ((void));
550 static long get_number
PARAMS ((void));
551 static void s_ent
PARAMS ((int));
552 static void s_mipsend
PARAMS ((int));
553 static void s_file
PARAMS ((int));
554 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
558 The following pseudo-ops from the Kane and Heinrich MIPS book
559 should be defined here, but are currently unsupported: .alias,
560 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
562 The following pseudo-ops from the Kane and Heinrich MIPS book are
563 specific to the type of debugging information being generated, and
564 should be defined by the object format: .aent, .begin, .bend,
565 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
568 The following pseudo-ops from the Kane and Heinrich MIPS book are
569 not MIPS CPU specific, but are also not specific to the object file
570 format. This file is probably the best place to define them, but
571 they are not currently supported: .asm0, .endr, .lab, .repeat,
572 .struct, .weakext. */
574 static const pseudo_typeS mips_pseudo_table
[] =
576 /* MIPS specific pseudo-ops. */
577 {"option", s_option
, 0},
578 {"set", s_mipsset
, 0},
579 {"rdata", s_change_sec
, 'r'},
580 {"sdata", s_change_sec
, 's'},
581 {"livereg", s_ignore
, 0},
582 {"abicalls", s_abicalls
, 0},
583 {"cpload", s_cpload
, 0},
584 {"cprestore", s_cprestore
, 0},
585 {"gpword", s_gpword
, 0},
586 {"cpadd", s_cpadd
, 0},
588 /* Relatively generic pseudo-ops that happen to be used on MIPS
590 {"asciiz", stringer
, 1},
591 {"bss", s_change_sec
, 'b'},
594 {"dword", s_cons
, 3},
596 /* These pseudo-ops are defined in read.c, but must be overridden
597 here for one reason or another. */
598 {"align", s_align
, 0},
600 {"data", s_change_sec
, 'd'},
601 {"double", s_float_cons
, 'd'},
602 {"float", s_float_cons
, 'f'},
603 {"globl", s_mips_globl
, 0},
604 {"global", s_mips_globl
, 0},
605 {"hword", s_cons
, 1},
610 {"short", s_cons
, 1},
611 {"single", s_float_cons
, 'f'},
612 {"text", s_change_sec
, 't'},
617 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
618 /* These pseudo-ops should be defined by the object file format.
619 However, a.out doesn't support them, so we have versions here. */
621 {"bgnb", s_ignore
, 0},
622 {"end", s_mipsend
, 0},
623 {"endb", s_ignore
, 0},
626 {"fmask", s_ignore
, 'F'},
627 {"frame", s_ignore
, 0},
628 {"loc", s_ignore
, 0},
629 {"mask", s_ignore
, 'R'},
630 {"verstamp", s_ignore
, 0},
634 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
639 pop_insert (mips_pseudo_table
);
640 if (! ECOFF_DEBUGGING
)
641 pop_insert (mips_nonecoff_pseudo_table
);
644 /* Symbols labelling the current insn. */
646 struct insn_label_list
648 struct insn_label_list
*next
;
652 static struct insn_label_list
*insn_labels
;
653 static struct insn_label_list
*free_insn_labels
;
655 static void mips_clear_insn_labels
PARAMS ((void));
658 mips_clear_insn_labels ()
660 register struct insn_label_list
**pl
;
662 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
668 static char *expr_end
;
670 /* Expressions which appear in instructions. These are set by
673 static expressionS imm_expr
;
674 static expressionS offset_expr
;
676 /* Relocs associated with imm_expr and offset_expr. */
678 static bfd_reloc_code_real_type imm_reloc
;
679 static bfd_reloc_code_real_type offset_reloc
;
681 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
683 static boolean imm_unmatched_hi
;
685 /* These are set by mips16_ip if an explicit extension is used. */
687 static boolean mips16_small
, mips16_ext
;
690 * This function is called once, at assembler startup time. It should
691 * set up all the tables, etc. that the MD part of the assembler will need.
697 register const char *retval
= NULL
;
698 register unsigned int i
= 0;
706 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
708 a
= xmalloc (sizeof TARGET_CPU
);
709 strcpy (a
, TARGET_CPU
);
710 a
[(sizeof TARGET_CPU
) - 3] = '\0';
714 if (strcmp (cpu
, "mips") == 0)
720 else if (strcmp (cpu
, "r6000") == 0
721 || strcmp (cpu
, "mips2") == 0)
727 else if (strcmp (cpu
, "mips64") == 0
728 || strcmp (cpu
, "r4000") == 0
729 || strcmp (cpu
, "mips3") == 0)
735 else if (strcmp (cpu
, "r4400") == 0)
741 else if (strcmp (cpu
, "mips64orion") == 0
742 || strcmp (cpu
, "r4600") == 0)
748 else if (strcmp (cpu
, "r4650") == 0)
756 else if (strcmp (cpu
, "mips64vr4300") == 0)
762 else if (strcmp (cpu
, "mips64vr4100") == 0)
770 else if (strcmp (cpu
, "r4010") == 0)
778 else if (strcmp (cpu
, "r5000") == 0
779 || strcmp (cpu
, "mips64vr5000") == 0)
785 else if (strcmp (cpu
, "r8000") == 0
786 || strcmp (cpu
, "mips4") == 0)
792 else if (strcmp (cpu
, "r10000") == 0)
798 else if (strcmp (cpu
, "mips16") == 0)
802 mips_cpu
= 0; /* FIXME */
817 if (strncmp (TARGET_CPU
, "mips16", sizeof "mips16" - 1) == 0)
832 if (mips_4650
|| mips_4010
|| mips_4100
|| mips_cpu
== 4300)
837 if (mips_cpu
== 4300)
842 if (mips_isa
< 2 && mips_trap
)
843 as_bad ("trap exception not supported at ISA 1");
848 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
851 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
854 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
857 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
861 as_warn ("Could not set architecture and machine");
863 file_mips_isa
= mips_isa
;
865 op_hash
= hash_new ();
867 for (i
= 0; i
< NUMOPCODES
;)
869 const char *name
= mips_opcodes
[i
].name
;
871 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
874 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
875 mips_opcodes
[i
].name
, retval
);
876 as_fatal ("Broken assembler. No assembly attempted.");
880 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
881 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
882 != mips_opcodes
[i
].match
))
884 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
885 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
886 as_fatal ("Broken assembler. No assembly attempted.");
890 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
893 mips16_op_hash
= hash_new ();
896 while (i
< bfd_mips16_num_opcodes
)
898 const char *name
= mips16_opcodes
[i
].name
;
900 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
902 as_fatal ("internal error: can't hash `%s': %s\n",
903 mips16_opcodes
[i
].name
, retval
);
906 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
907 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
908 != mips16_opcodes
[i
].match
))
909 as_fatal ("internal error: bad opcode: `%s' \"%s\"\n",
910 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
913 while (i
< bfd_mips16_num_opcodes
914 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
917 mips_no_prev_insn ();
925 /* set the default alignment for the text section (2**2) */
926 record_alignment (text_section
, 2);
928 if (USE_GLOBAL_POINTER_OPT
)
929 bfd_set_gp_size (stdoutput
, g_switch_value
);
931 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
933 /* On a native system, sections must be aligned to 16 byte
934 boundaries. When configured for an embedded ELF target, we
936 if (strcmp (TARGET_OS
, "elf") != 0)
938 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
939 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
940 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
943 /* Create a .reginfo section for register masks and a .mdebug
944 section for debugging information. */
955 sec
= subseg_new (".reginfo", (subsegT
) 0);
957 /* The ABI says this section should be loaded so that the
958 running program can access it. */
959 (void) bfd_set_section_flags (stdoutput
, sec
,
960 (SEC_ALLOC
| SEC_LOAD
961 | SEC_READONLY
| SEC_DATA
));
962 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
965 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
970 /* The 64-bit ABI uses a .MIPS.options section rather than
972 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
973 (void) bfd_set_section_flags (stdoutput
, sec
,
974 (SEC_ALLOC
| SEC_LOAD
975 | SEC_READONLY
| SEC_DATA
));
976 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
979 /* Set up the option header. */
981 Elf_Internal_Options opthdr
;
984 opthdr
.kind
= ODK_REGINFO
;
985 opthdr
.size
= (sizeof (Elf_External_Options
)
986 + sizeof (Elf64_External_RegInfo
));
989 f
= frag_more (sizeof (Elf_External_Options
));
990 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
991 (Elf_External_Options
*) f
);
993 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1000 sec
= subseg_new (".mdebug", (subsegT
) 0);
1001 (void) bfd_set_section_flags (stdoutput
, sec
,
1002 SEC_HAS_CONTENTS
| SEC_READONLY
);
1003 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1006 subseg_set (seg
, subseg
);
1010 if (! ECOFF_DEBUGGING
)
1017 if (! ECOFF_DEBUGGING
)
1025 struct mips_cl_insn insn
;
1027 imm_expr
.X_op
= O_absent
;
1028 imm_reloc
= BFD_RELOC_UNUSED
;
1029 imm_unmatched_hi
= false;
1030 offset_expr
.X_op
= O_absent
;
1031 offset_reloc
= BFD_RELOC_UNUSED
;
1034 mips16_ip (str
, &insn
);
1036 mips_ip (str
, &insn
);
1040 as_bad ("%s `%s'", insn_error
, str
);
1044 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1047 mips16_macro (&insn
);
1053 if (imm_expr
.X_op
!= O_absent
)
1054 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1056 else if (offset_expr
.X_op
!= O_absent
)
1057 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1059 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
1063 /* See whether instruction IP reads register REG. CLASS is the type
1067 insn_uses_reg (ip
, reg
, class)
1068 struct mips_cl_insn
*ip
;
1070 enum mips_regclass
class;
1072 if (class == MIPS16_REG
)
1075 reg
= mips16_to_32_reg_map
[reg
];
1076 class = MIPS_GR_REG
;
1079 /* Don't report on general register 0, since it never changes. */
1080 if (class == MIPS_GR_REG
&& reg
== 0)
1083 if (class == MIPS_FP_REG
)
1086 /* If we are called with either $f0 or $f1, we must check $f0.
1087 This is not optimal, because it will introduce an unnecessary
1088 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1089 need to distinguish reading both $f0 and $f1 or just one of
1090 them. Note that we don't have to check the other way,
1091 because there is no instruction that sets both $f0 and $f1
1092 and requires a delay. */
1093 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1094 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
1095 == (reg
&~ (unsigned) 1)))
1097 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1098 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
1099 == (reg
&~ (unsigned) 1)))
1104 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1105 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1107 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1108 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1113 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1114 && ((ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
) == reg
)
1116 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1117 && ((ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
) == reg
)
1119 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1120 && ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1121 & MIPS16OP_MASK_MOVE32Z
) == reg
)
1123 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1125 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1127 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1129 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1130 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1131 & MIPS16OP_MASK_REGR32
) == reg
)
1138 /* This function returns true if modifying a register requires a
1142 reg_needs_delay (reg
)
1145 unsigned long prev_pinfo
;
1147 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1148 if (! mips_noreorder
1150 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1152 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1154 /* A load from a coprocessor or from memory. All load
1155 delays delay the use of general register rt for one
1156 instruction on the r3000. The r6000 and r4000 use
1158 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1159 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1166 /* Output an instruction. PLACE is where to put the instruction; if
1167 it is NULL, this uses frag_more to get room. IP is the instruction
1168 information. ADDRESS_EXPR is an operand of the instruction to be
1169 used with RELOC_TYPE. */
1172 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1174 struct mips_cl_insn
*ip
;
1175 expressionS
*address_expr
;
1176 bfd_reloc_code_real_type reloc_type
;
1177 boolean unmatched_hi
;
1179 register unsigned long prev_pinfo
, pinfo
;
1184 /* Mark instruction labels in mips16 mode. This permits the linker
1185 to handle them specially, such as generating jalx instructions
1186 when needed. We also make them odd for the duration of the
1187 assembly, in order to generate the right sort of code. We will
1188 make them even in the adjust_symtab routine, while leaving them
1189 marked. This is convenient for the debugger and the
1190 disassembler. The linker knows to make them odd again. */
1193 struct insn_label_list
*l
;
1195 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1198 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1199 S_SET_OTHER (l
->label
, STO_MIPS16
);
1201 ++l
->label
->sy_value
.X_add_number
;
1205 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1206 pinfo
= ip
->insn_mo
->pinfo
;
1208 if (place
== NULL
&& ! mips_noreorder
)
1210 /* If the previous insn required any delay slots, see if we need
1211 to insert a NOP or two. There are eight kinds of possible
1212 hazards, of which an instruction can have at most one type.
1213 (1) a load from memory delay
1214 (2) a load from a coprocessor delay
1215 (3) an unconditional branch delay
1216 (4) a conditional branch delay
1217 (5) a move to coprocessor register delay
1218 (6) a load coprocessor register from memory delay
1219 (7) a coprocessor condition code delay
1220 (8) a HI/LO special register delay
1222 There are a lot of optimizations we could do that we don't.
1223 In particular, we do not, in general, reorder instructions.
1224 If you use gcc with optimization, it will reorder
1225 instructions and generally do much more optimization then we
1226 do here; repeating all that work in the assembler would only
1227 benefit hand written assembly code, and does not seem worth
1230 /* This is how a NOP is emitted. */
1231 #define emit_nop() \
1233 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1234 : md_number_to_chars (frag_more (4), 0, 4))
1236 /* The previous insn might require a delay slot, depending upon
1237 the contents of the current insn. */
1240 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1241 && ! cop_interlocks
)
1243 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1245 /* A load from a coprocessor or from memory. All load
1246 delays delay the use of general register rt for one
1247 instruction on the r3000. The r6000 and r4000 use
1249 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1250 if (mips_optimize
== 0
1251 || insn_uses_reg (ip
,
1252 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1259 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1260 && ! cop_interlocks
)
1262 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1264 /* A generic coprocessor delay. The previous instruction
1265 modified a coprocessor general or control register. If
1266 it modified a control register, we need to avoid any
1267 coprocessor instruction (this is probably not always
1268 required, but it sometimes is). If it modified a general
1269 register, we avoid using that register.
1271 On the r6000 and r4000 loading a coprocessor register
1272 from memory is interlocked, and does not require a delay.
1274 This case is not handled very well. There is no special
1275 knowledge of CP0 handling, and the coprocessors other
1276 than the floating point unit are not distinguished at
1278 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1280 if (mips_optimize
== 0
1281 || insn_uses_reg (ip
,
1282 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1287 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1289 if (mips_optimize
== 0
1290 || insn_uses_reg (ip
,
1291 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1298 /* We don't know exactly what the previous instruction
1299 does. If the current instruction uses a coprocessor
1300 register, we must insert a NOP. If previous
1301 instruction may set the condition codes, and the
1302 current instruction uses them, we must insert two
1304 if (mips_optimize
== 0
1305 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1306 && (pinfo
& INSN_READ_COND_CODE
)))
1308 else if (pinfo
& INSN_COP
)
1314 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1315 && ! cop_interlocks
)
1317 /* The previous instruction sets the coprocessor condition
1318 codes, but does not require a general coprocessor delay
1319 (this means it is a floating point comparison
1320 instruction). If this instruction uses the condition
1321 codes, we need to insert a single NOP. */
1322 if (mips_optimize
== 0
1323 || (pinfo
& INSN_READ_COND_CODE
))
1326 else if (prev_pinfo
& INSN_READ_LO
)
1328 /* The previous instruction reads the LO register; if the
1329 current instruction writes to the LO register, we must
1330 insert two NOPS. Some newer processors have interlocks. */
1332 && (mips_optimize
== 0
1333 || (pinfo
& INSN_WRITE_LO
)))
1336 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1338 /* The previous instruction reads the HI register; if the
1339 current instruction writes to the HI register, we must
1340 insert a NOP. Some newer processors have interlocks. */
1342 && (mips_optimize
== 0
1343 || (pinfo
& INSN_WRITE_HI
)))
1347 /* There are two cases which require two intervening
1348 instructions: 1) setting the condition codes using a move to
1349 coprocessor instruction which requires a general coprocessor
1350 delay and then reading the condition codes 2) reading the HI
1351 or LO register and then writing to it (except on processors
1352 which have interlocks). If we are not already emitting a NOP
1353 instruction, we must check for these cases compared to the
1354 instruction previous to the previous instruction. */
1358 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1359 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1360 && (pinfo
& INSN_READ_COND_CODE
)
1361 && ! cop_interlocks
)
1362 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1363 && (pinfo
& INSN_WRITE_LO
)
1365 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1366 && (pinfo
& INSN_WRITE_HI
)
1370 /* If we are being given a nop instruction, don't bother with
1371 one of the nops we would otherwise output. This will only
1372 happen when a nop instruction is used with mips_optimize set
1374 if (nops
> 0 && ip
->insn_opcode
== (mips16
? 0x6500 : 0))
1377 /* Now emit the right number of NOP instructions. */
1381 unsigned long old_frag_offset
;
1383 struct insn_label_list
*l
;
1385 old_frag
= frag_now
;
1386 old_frag_offset
= frag_now_fix ();
1388 for (i
= 0; i
< nops
; i
++)
1393 listing_prev_line ();
1394 /* We may be at the start of a variant frag. In case we
1395 are, make sure there is enough space for the frag
1396 after the frags created by listing_prev_line. The
1397 argument to frag_grow here must be at least as large
1398 as the argument to all other calls to frag_grow in
1399 this file. We don't have to worry about being in the
1400 middle of a variant frag, because the variants insert
1401 all needed nop instructions themselves. */
1405 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1407 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1408 l
->label
->sy_frag
= frag_now
;
1409 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
1410 /* mips16 text labels are stored as odd. */
1412 ++l
->label
->sy_value
.X_add_number
;
1415 #ifndef NO_ECOFF_DEBUGGING
1416 if (ECOFF_DEBUGGING
)
1417 ecoff_fix_loc (old_frag
, old_frag_offset
);
1422 if (reloc_type
> BFD_RELOC_UNUSED
)
1424 /* We need to set up a variant frag. */
1425 assert (mips16
&& address_expr
!= NULL
);
1426 f
= frag_var (rs_machine_dependent
, 4, 0,
1427 RELAX_MIPS16_ENCODE (reloc_type
- BFD_RELOC_UNUSED
,
1428 mips16_small
, mips16_ext
,
1430 & INSN_UNCOND_BRANCH_DELAY
),
1431 (prev_insn_reloc_type
1432 == BFD_RELOC_MIPS16_JMP
)),
1433 make_expr_symbol (address_expr
), (long) 0,
1436 else if (place
!= NULL
)
1438 else if (mips16
&& ! ip
->use_extend
&& reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1440 /* Make sure there is enough room to swap this instruction with
1441 a following jump instruction. */
1448 if (address_expr
!= NULL
&& reloc_type
< BFD_RELOC_UNUSED
)
1450 if (address_expr
->X_op
== O_constant
)
1455 ip
->insn_opcode
|= address_expr
->X_add_number
;
1458 case BFD_RELOC_LO16
:
1459 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1462 case BFD_RELOC_MIPS_JMP
:
1463 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1466 case BFD_RELOC_MIPS16_JMP
:
1468 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1469 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1470 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1473 case BFD_RELOC_16_PCREL_S2
:
1483 /* Don't generate a reloc if we are writing into a variant
1487 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1489 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1493 struct mips_hi_fixup
*hi_fixup
;
1495 assert (reloc_type
== BFD_RELOC_HI16_S
);
1496 hi_fixup
= ((struct mips_hi_fixup
*)
1497 xmalloc (sizeof (struct mips_hi_fixup
)));
1498 hi_fixup
->fixp
= fixp
;
1499 hi_fixup
->seg
= now_seg
;
1500 hi_fixup
->next
= mips_hi_fixup_list
;
1501 mips_hi_fixup_list
= hi_fixup
;
1507 if (! mips16
|| reloc_type
== BFD_RELOC_MIPS16_JMP
)
1508 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1513 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
1516 md_number_to_chars (f
, ip
->insn_opcode
, 2);
1519 /* Update the register mask information. */
1522 if (pinfo
& INSN_WRITE_GPR_D
)
1523 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1524 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1525 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1526 if (pinfo
& INSN_READ_GPR_S
)
1527 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1528 if (pinfo
& INSN_WRITE_GPR_31
)
1529 mips_gprmask
|= 1 << 31;
1530 if (pinfo
& INSN_WRITE_FPR_D
)
1531 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1532 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1533 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1534 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1535 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1536 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1537 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1538 if (pinfo
& INSN_COP
)
1540 /* We don't keep enough information to sort these cases out. */
1542 /* Never set the bit for $0, which is always zero. */
1543 mips_gprmask
&=~ 1 << 0;
1547 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
1548 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1549 & MIPS16OP_MASK_RX
);
1550 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
1551 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1552 & MIPS16OP_MASK_RY
);
1553 if (pinfo
& MIPS16_INSN_WRITE_Z
)
1554 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
1555 & MIPS16OP_MASK_RZ
);
1556 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
1557 mips_gprmask
|= 1 << TREG
;
1558 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
1559 mips_gprmask
|= 1 << SP
;
1560 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
1561 mips_gprmask
|= 1 << RA
;
1562 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1563 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
1564 if (pinfo
& MIPS16_INSN_READ_Z
)
1565 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1566 & MIPS16OP_MASK_MOVE32Z
);
1567 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
1568 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1569 & MIPS16OP_MASK_REGR32
);
1572 if (place
== NULL
&& ! mips_noreorder
)
1574 /* Filling the branch delay slot is more complex. We try to
1575 switch the branch with the previous instruction, which we can
1576 do if the previous instruction does not set up a condition
1577 that the branch tests and if the branch is not itself the
1578 target of any branch. */
1579 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1580 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1582 if (mips_optimize
< 2
1583 /* If we have seen .set volatile or .set nomove, don't
1586 /* If we had to emit any NOP instructions, then we
1587 already know we can not swap. */
1589 /* If we don't even know the previous insn, we can not
1591 || ! prev_insn_valid
1592 /* If the previous insn is already in a branch delay
1593 slot, then we can not swap. */
1594 || prev_insn_is_delay_slot
1595 /* If the previous previous insn was in a .set
1596 noreorder, we can't swap. Actually, the MIPS
1597 assembler will swap in this situation. However, gcc
1598 configured -with-gnu-as will generate code like
1604 in which we can not swap the bne and INSN. If gcc is
1605 not configured -with-gnu-as, it does not output the
1606 .set pseudo-ops. We don't have to check
1607 prev_insn_unreordered, because prev_insn_valid will
1608 be 0 in that case. We don't want to use
1609 prev_prev_insn_valid, because we do want to be able
1610 to swap at the start of a function. */
1611 || prev_prev_insn_unreordered
1612 /* If the branch is itself the target of a branch, we
1613 can not swap. We cheat on this; all we check for is
1614 whether there is a label on this instruction. If
1615 there are any branches to anything other than a
1616 label, users must use .set noreorder. */
1617 || insn_labels
!= NULL
1618 /* If the previous instruction is in a variant frag, we
1619 can not do the swap. This does not apply to the
1620 mips16, which uses variant frags for different
1623 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
1624 /* If the branch reads the condition codes, we don't
1625 even try to swap, because in the sequence
1630 we can not swap, and I don't feel like handling that
1634 && (pinfo
& INSN_READ_COND_CODE
))
1635 /* We can not swap with an instruction that requires a
1636 delay slot, becase the target of the branch might
1637 interfere with that instruction. */
1641 & (INSN_LOAD_COPROC_DELAY
1642 | INSN_COPROC_MOVE_DELAY
1643 | INSN_WRITE_COND_CODE
)))
1651 & (INSN_LOAD_MEMORY_DELAY
1652 | INSN_COPROC_MEMORY_DELAY
)))
1653 /* We can not swap with a branch instruction. */
1655 & (INSN_UNCOND_BRANCH_DELAY
1656 | INSN_COND_BRANCH_DELAY
1657 | INSN_COND_BRANCH_LIKELY
))
1658 /* We do not swap with a trap instruction, since it
1659 complicates trap handlers to have the trap
1660 instruction be in a delay slot. */
1661 || (prev_pinfo
& INSN_TRAP
)
1662 /* If the branch reads a register that the previous
1663 instruction sets, we can not swap. */
1665 && (prev_pinfo
& INSN_WRITE_GPR_T
)
1666 && insn_uses_reg (ip
,
1667 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1671 && (prev_pinfo
& INSN_WRITE_GPR_D
)
1672 && insn_uses_reg (ip
,
1673 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1677 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
1678 && insn_uses_reg (ip
,
1679 ((prev_insn
.insn_opcode
1681 & MIPS16OP_MASK_RX
),
1683 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
1684 && insn_uses_reg (ip
,
1685 ((prev_insn
.insn_opcode
1687 & MIPS16OP_MASK_RY
),
1689 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
1690 && insn_uses_reg (ip
,
1691 ((prev_insn
.insn_opcode
1693 & MIPS16OP_MASK_RZ
),
1695 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
1696 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
1697 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
1698 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
1699 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1700 && insn_uses_reg (ip
,
1701 MIPS16OP_EXTRACT_REG32R (prev_insn
.
1704 /* If the branch writes a register that the previous
1705 instruction sets, we can not swap (we know that
1706 branches write only to RD or to $31). */
1708 && (prev_pinfo
& INSN_WRITE_GPR_T
)
1709 && (((pinfo
& INSN_WRITE_GPR_D
)
1710 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1711 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1712 || ((pinfo
& INSN_WRITE_GPR_31
)
1713 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1717 && (prev_pinfo
& INSN_WRITE_GPR_D
)
1718 && (((pinfo
& INSN_WRITE_GPR_D
)
1719 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1720 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1721 || ((pinfo
& INSN_WRITE_GPR_31
)
1722 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1726 && (pinfo
& MIPS16_INSN_WRITE_31
)
1727 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
1728 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1729 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
1731 /* If the branch writes a register that the previous
1732 instruction reads, we can not swap (we know that
1733 branches only write to RD or to $31). */
1735 && (pinfo
& INSN_WRITE_GPR_D
)
1736 && insn_uses_reg (&prev_insn
,
1737 ((ip
->insn_opcode
>> OP_SH_RD
)
1741 && (pinfo
& INSN_WRITE_GPR_31
)
1742 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
1744 && (pinfo
& MIPS16_INSN_WRITE_31
)
1745 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
1746 /* If we are generating embedded PIC code, the branch
1747 might be expanded into a sequence which uses $at, so
1748 we can't swap with an instruction which reads it. */
1749 || (mips_pic
== EMBEDDED_PIC
1750 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
1751 /* If the previous previous instruction has a load
1752 delay, and sets a register that the branch reads, we
1756 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1758 && (prev_prev_insn
.insn_mo
->pinfo
1759 & INSN_LOAD_MEMORY_DELAY
)))
1760 && insn_uses_reg (ip
,
1761 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1764 /* If one instruction sets a condition code and the
1765 other one uses a condition code, we can not swap. */
1766 || ((pinfo
& INSN_READ_COND_CODE
)
1767 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
1768 || ((pinfo
& INSN_WRITE_COND_CODE
)
1769 && (prev_pinfo
& INSN_READ_COND_CODE
))
1770 /* If the previous instruction uses the PC, we can not
1773 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
1774 /* If the previous instruction was extended, we can not
1776 || (mips16
&& prev_insn_extended
)
1777 /* If the previous instruction had a fixup in mips16
1778 mode, we can not swap. This normally means that the
1779 previous instruction was a 4 byte branch anyhow. */
1780 || (mips16
&& prev_insn_fixp
))
1782 /* We could do even better for unconditional branches to
1783 portions of this object file; we could pick up the
1784 instruction at the destination, put it in the delay
1785 slot, and bump the destination address. */
1787 /* Update the previous insn information. */
1788 prev_prev_insn
= *ip
;
1789 prev_insn
.insn_mo
= &dummy_opcode
;
1793 /* It looks like we can actually do the swap. */
1799 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1800 memcpy (temp
, prev_f
, 4);
1801 memcpy (prev_f
, f
, 4);
1802 memcpy (f
, temp
, 4);
1805 prev_insn_fixp
->fx_frag
= frag_now
;
1806 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1810 fixp
->fx_frag
= prev_insn_frag
;
1811 fixp
->fx_where
= prev_insn_where
;
1814 else if (reloc_type
> BFD_RELOC_UNUSED
)
1819 /* We are in mips16 mode, and we have just created a
1820 variant frag. We need to extract the old
1821 instruction from the end of the previous frag,
1822 and add it to a new frag. */
1823 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1824 memcpy (temp
, prev_f
, 2);
1825 prev_insn_frag
->fr_fix
-= 2;
1826 if (prev_insn_frag
->fr_type
== rs_machine_dependent
)
1828 assert (prev_insn_where
== prev_insn_frag
->fr_fix
);
1829 memcpy (prev_f
, prev_f
+ 2, 2);
1831 memcpy (frag_more (2), temp
, 2);
1838 assert (prev_insn_fixp
== NULL
);
1839 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1840 memcpy (temp
, prev_f
, 2);
1841 memcpy (prev_f
, f
, 2);
1842 if (reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1843 memcpy (f
, temp
, 2);
1846 memcpy (f
, f
+ 2, 2);
1847 memcpy (f
+ 2, temp
, 2);
1851 fixp
->fx_frag
= prev_insn_frag
;
1852 fixp
->fx_where
= prev_insn_where
;
1856 /* Update the previous insn information; leave prev_insn
1858 prev_prev_insn
= *ip
;
1860 prev_insn_is_delay_slot
= 1;
1862 /* If that was an unconditional branch, forget the previous
1863 insn information. */
1864 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1866 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1867 prev_insn
.insn_mo
= &dummy_opcode
;
1870 prev_insn_fixp
= NULL
;
1871 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
1872 prev_insn_extended
= 0;
1874 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1876 /* We don't yet optimize a branch likely. What we should do
1877 is look at the target, copy the instruction found there
1878 into the delay slot, and increment the branch to jump to
1879 the next instruction. */
1881 /* Update the previous insn information. */
1882 prev_prev_insn
= *ip
;
1883 prev_insn
.insn_mo
= &dummy_opcode
;
1884 prev_insn_fixp
= NULL
;
1885 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
1886 prev_insn_extended
= 0;
1890 /* Update the previous insn information. */
1892 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1894 prev_prev_insn
= prev_insn
;
1897 /* Any time we see a branch, we always fill the delay slot
1898 immediately; since this insn is not a branch, we know it
1899 is not in a delay slot. */
1900 prev_insn_is_delay_slot
= 0;
1902 prev_insn_fixp
= fixp
;
1903 prev_insn_reloc_type
= reloc_type
;
1905 prev_insn_extended
= (ip
->use_extend
1906 || reloc_type
> BFD_RELOC_UNUSED
);
1909 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1910 prev_insn_unreordered
= 0;
1911 prev_insn_frag
= frag_now
;
1912 prev_insn_where
= f
- frag_now
->fr_literal
;
1913 prev_insn_valid
= 1;
1915 else if (place
== NULL
)
1917 /* We need to record a bit of information even when we are not
1918 reordering, in order to determine the base address for mips16
1919 PC relative relocs. */
1921 prev_insn_reloc_type
= reloc_type
;
1924 /* We just output an insn, so the next one doesn't have a label. */
1925 mips_clear_insn_labels ();
1928 /* This function forgets that there was any previous instruction or
1932 mips_no_prev_insn ()
1934 prev_insn
.insn_mo
= &dummy_opcode
;
1935 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1936 prev_insn_valid
= 0;
1937 prev_insn_is_delay_slot
= 0;
1938 prev_insn_unreordered
= 0;
1939 prev_insn_extended
= 0;
1940 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
1941 prev_prev_insn_unreordered
= 0;
1942 mips_clear_insn_labels ();
1945 /* This function must be called whenever we turn on noreorder or emit
1946 something other than instructions. It inserts any NOPS which might
1947 be needed by the previous instruction, and clears the information
1948 kept for the previous instructions. The INSNS parameter is true if
1949 instructions are to follow. */
1952 mips_emit_delays (insns
)
1955 if (! mips_noreorder
)
1962 && (! cop_interlocks
1963 && (prev_insn
.insn_mo
->pinfo
1964 & (INSN_LOAD_COPROC_DELAY
1965 | INSN_COPROC_MOVE_DELAY
1966 | INSN_WRITE_COND_CODE
))))
1968 && (prev_insn
.insn_mo
->pinfo
1973 && (prev_insn
.insn_mo
->pinfo
1974 & (INSN_LOAD_MEMORY_DELAY
1975 | INSN_COPROC_MEMORY_DELAY
))))
1980 && (! cop_interlocks
1981 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1983 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1984 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1989 && (! cop_interlocks
1990 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1992 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1993 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1997 struct insn_label_list
*l
;
2000 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2002 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2003 l
->label
->sy_frag
= frag_now
;
2004 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
2005 /* mips16 text labels are stored as odd. */
2007 ++l
->label
->sy_value
.X_add_number
;
2012 /* Mark instruction labels in mips16 mode. This permits the linker
2013 to handle them specially, such as generating jalx instructions
2014 when needed. We also make them odd for the duration of the
2015 assembly, in order to generate the right sort of code. We will
2016 make them even in the adjust_symtab routine, while leaving them
2017 marked. This is convenient for the debugger and the
2018 disassembler. The linker knows to make them odd again. */
2019 if (mips16
&& insns
)
2021 struct insn_label_list
*l
;
2023 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2026 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
2027 S_SET_OTHER (l
->label
, STO_MIPS16
);
2029 if ((l
->label
->sy_value
.X_add_number
& 1) == 0)
2030 ++l
->label
->sy_value
.X_add_number
;
2034 mips_no_prev_insn ();
2037 /* Build an instruction created by a macro expansion. This is passed
2038 a pointer to the count of instructions created so far, an
2039 expression, the name of the instruction to build, an operand format
2040 string, and corresponding arguments. */
2044 macro_build (char *place
,
2052 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2061 struct mips_cl_insn insn
;
2062 bfd_reloc_code_real_type r
;
2066 va_start (args
, fmt
);
2072 * If the macro is about to expand into a second instruction,
2073 * print a warning if needed. We need to pass ip as a parameter
2074 * to generate a better warning message here...
2076 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
2077 as_warn ("Macro instruction expanded into multiple instructions");
2080 *counter
+= 1; /* bump instruction counter */
2084 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2089 r
= BFD_RELOC_UNUSED
;
2090 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2091 assert (insn
.insn_mo
);
2092 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2094 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2095 || insn
.insn_mo
->pinfo
== INSN_MACRO
2096 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA2
2098 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA3
2100 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA4
2102 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4650
2104 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4010
2106 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4100
2110 assert (insn
.insn_mo
->name
);
2111 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2113 insn
.insn_opcode
= insn
.insn_mo
->match
;
2129 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2135 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2140 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2145 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2152 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2156 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2160 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2167 insn
.insn_opcode
|= va_arg (args
, int) << 21;
2173 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2174 assert (r
== BFD_RELOC_MIPS_GPREL
2175 || r
== BFD_RELOC_MIPS_LITERAL
2176 || r
== BFD_RELOC_LO16
2177 || r
== BFD_RELOC_MIPS_GOT16
2178 || r
== BFD_RELOC_MIPS_CALL16
2179 || r
== BFD_RELOC_MIPS_GOT_LO16
2180 || r
== BFD_RELOC_MIPS_CALL_LO16
2181 || (ep
->X_op
== O_subtract
2182 && now_seg
== text_section
2183 && r
== BFD_RELOC_PCREL_LO16
));
2187 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2189 && (ep
->X_op
== O_constant
2190 || (ep
->X_op
== O_symbol
2191 && (r
== BFD_RELOC_HI16_S
2192 || r
== BFD_RELOC_HI16
2193 || r
== BFD_RELOC_MIPS_GOT_HI16
2194 || r
== BFD_RELOC_MIPS_CALL_HI16
))
2195 || (ep
->X_op
== O_subtract
2196 && now_seg
== text_section
2197 && r
== BFD_RELOC_PCREL_HI16_S
)));
2198 if (ep
->X_op
== O_constant
)
2200 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
2202 r
= BFD_RELOC_UNUSED
;
2207 assert (ep
!= NULL
);
2209 * This allows macro() to pass an immediate expression for
2210 * creating short branches without creating a symbol.
2211 * Note that the expression still might come from the assembly
2212 * input, in which case the value is not checked for range nor
2213 * is a relocation entry generated (yuck).
2215 if (ep
->X_op
== O_constant
)
2217 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2221 r
= BFD_RELOC_16_PCREL_S2
;
2225 assert (ep
!= NULL
);
2226 r
= BFD_RELOC_MIPS_JMP
;
2235 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2237 append_insn (place
, &insn
, ep
, r
, false);
2241 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2249 struct mips_cl_insn insn
;
2250 bfd_reloc_code_real_type r
;
2252 r
= BFD_RELOC_UNUSED
;
2253 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2254 assert (insn
.insn_mo
);
2255 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2257 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2258 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2261 assert (insn
.insn_mo
->name
);
2262 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2265 insn
.insn_opcode
= insn
.insn_mo
->match
;
2266 insn
.use_extend
= false;
2285 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2290 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2294 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2298 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2308 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2315 regno
= va_arg (args
, int);
2316 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2317 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2338 assert (ep
!= NULL
);
2340 if (ep
->X_op
!= O_constant
)
2341 r
= BFD_RELOC_UNUSED
+ c
;
2344 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
2345 false, false, &insn
.insn_opcode
,
2346 &insn
.use_extend
, &insn
.extend
);
2348 r
= BFD_RELOC_UNUSED
;
2354 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
2361 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2363 append_insn (place
, &insn
, ep
, r
, false);
2367 * Generate a "lui" instruction.
2370 macro_build_lui (place
, counter
, ep
, regnum
)
2376 expressionS high_expr
;
2377 struct mips_cl_insn insn
;
2378 bfd_reloc_code_real_type r
;
2379 CONST
char *name
= "lui";
2380 CONST
char *fmt
= "t,u";
2388 high_expr
.X_op
= O_constant
;
2389 high_expr
.X_add_number
= ep
->X_add_number
;
2392 if (high_expr
.X_op
== O_constant
)
2394 /* we can compute the instruction now without a relocation entry */
2395 if (high_expr
.X_add_number
& 0x8000)
2396 high_expr
.X_add_number
+= 0x10000;
2397 high_expr
.X_add_number
=
2398 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
2399 r
= BFD_RELOC_UNUSED
;
2403 assert (ep
->X_op
== O_symbol
);
2404 /* _gp_disp is a special case, used from s_cpload. */
2405 assert (mips_pic
== NO_PIC
2406 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
2407 r
= BFD_RELOC_HI16_S
;
2411 * If the macro is about to expand into a second instruction,
2412 * print a warning if needed. We need to pass ip as a parameter
2413 * to generate a better warning message here...
2415 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
2416 as_warn ("Macro instruction expanded into multiple instructions");
2419 *counter
+= 1; /* bump instruction counter */
2421 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2422 assert (insn
.insn_mo
);
2423 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2424 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
2426 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
2427 if (r
== BFD_RELOC_UNUSED
)
2429 insn
.insn_opcode
|= high_expr
.X_add_number
;
2430 append_insn (place
, &insn
, NULL
, r
, false);
2433 append_insn (place
, &insn
, &high_expr
, r
, false);
2437 * Generates code to set the $at register to true (one)
2438 * if reg is less than the immediate expression.
2441 set_at (counter
, reg
, unsignedp
)
2446 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2447 macro_build ((char *) NULL
, counter
, &imm_expr
,
2448 unsignedp
? "sltiu" : "slti",
2449 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
2452 load_register (counter
, AT
, &imm_expr
, 0);
2453 macro_build ((char *) NULL
, counter
, NULL
,
2454 unsignedp
? "sltu" : "slt",
2455 "d,v,t", AT
, reg
, AT
);
2459 /* Warn if an expression is not a constant. */
2462 check_absolute_expr (ip
, ex
)
2463 struct mips_cl_insn
*ip
;
2466 if (ex
->X_op
!= O_constant
)
2467 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
2470 /* Count the leading zeroes by performing a binary chop. This is a
2471 bulky bit of source, but performance is a LOT better for the
2472 majority of values than a simple loop to count the bits:
2473 for (lcnt = 0; (lcnt < 32); lcnt++)
2474 if ((v) & (1 << (31 - lcnt)))
2476 However it is not code size friendly, and the gain will drop a bit
2477 on certain cached systems.
2479 #define COUNT_TOP_ZEROES(v) \
2480 (((v) & ~0xffff) == 0 \
2481 ? ((v) & ~0xff) == 0 \
2482 ? ((v) & ~0xf) == 0 \
2483 ? ((v) & ~0x3) == 0 \
2484 ? ((v) & ~0x1) == 0 \
2489 : ((v) & ~0x7) == 0 \
2492 : ((v) & ~0x3f) == 0 \
2493 ? ((v) & ~0x1f) == 0 \
2496 : ((v) & ~0x7f) == 0 \
2499 : ((v) & ~0xfff) == 0 \
2500 ? ((v) & ~0x3ff) == 0 \
2501 ? ((v) & ~0x1ff) == 0 \
2504 : ((v) & ~0x7ff) == 0 \
2507 : ((v) & ~0x3fff) == 0 \
2508 ? ((v) & ~0x1fff) == 0 \
2511 : ((v) & ~0x7fff) == 0 \
2514 : ((v) & ~0xffffff) == 0 \
2515 ? ((v) & ~0xfffff) == 0 \
2516 ? ((v) & ~0x3ffff) == 0 \
2517 ? ((v) & ~0x1ffff) == 0 \
2520 : ((v) & ~0x7ffff) == 0 \
2523 : ((v) & ~0x3fffff) == 0 \
2524 ? ((v) & ~0x1fffff) == 0 \
2527 : ((v) & ~0x7fffff) == 0 \
2530 : ((v) & ~0xfffffff) == 0 \
2531 ? ((v) & ~0x3ffffff) == 0 \
2532 ? ((v) & ~0x1ffffff) == 0 \
2535 : ((v) & ~0x7ffffff) == 0 \
2538 : ((v) & ~0x3fffffff) == 0 \
2539 ? ((v) & ~0x1fffffff) == 0 \
2542 : ((v) & ~0x7fffffff) == 0 \
2547 * This routine generates the least number of instructions neccessary to load
2548 * an absolute expression value into a register.
2551 load_register (counter
, reg
, ep
, dbl
)
2558 expressionS hi32
, lo32
, tmp
;
2560 if (ep
->X_op
!= O_big
)
2562 assert (ep
->X_op
== O_constant
);
2563 if (ep
->X_add_number
< 0x8000
2564 && (ep
->X_add_number
>= 0
2565 || (ep
->X_add_number
>= -0x8000
2568 || sizeof (ep
->X_add_number
) > 4))))
2570 /* We can handle 16 bit signed values with an addiu to
2571 $zero. No need to ever use daddiu here, since $zero and
2572 the result are always correct in 32 bit mode. */
2573 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2574 (int) BFD_RELOC_LO16
);
2577 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
2579 /* We can handle 16 bit unsigned values with an ori to
2581 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
2582 (int) BFD_RELOC_LO16
);
2585 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
2586 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
2587 == ~ (offsetT
) 0x7fffffff))
2590 || sizeof (ep
->X_add_number
) > 4
2591 || (ep
->X_add_number
& 0x80000000) == 0))
2592 || ((mips_isa
< 3 || !dbl
)
2593 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0))
2595 /* 32 bit values require an lui. */
2596 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2597 (int) BFD_RELOC_HI16
);
2598 if ((ep
->X_add_number
& 0xffff) != 0)
2599 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
2600 (int) BFD_RELOC_LO16
);
2605 /* The value is larger than 32 bits. */
2609 as_bad ("Number larger than 32 bits");
2610 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2611 (int) BFD_RELOC_LO16
);
2615 if (ep
->X_op
!= O_big
)
2619 hi32
.X_add_number
>>= shift
;
2620 hi32
.X_add_number
&= 0xffffffff;
2621 if ((hi32
.X_add_number
& 0x80000000) != 0)
2622 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
2624 lo32
.X_add_number
&= 0xffffffff;
2628 assert (ep
->X_add_number
> 2);
2629 if (ep
->X_add_number
== 3)
2630 generic_bignum
[3] = 0;
2631 else if (ep
->X_add_number
> 4)
2632 as_bad ("Number larger than 64 bits");
2633 lo32
.X_op
= O_constant
;
2634 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
2635 hi32
.X_op
= O_constant
;
2636 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
2639 if (hi32
.X_add_number
== 0)
2643 if (hi32
.X_add_number
== 0xffffffff)
2645 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
2647 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j", reg
, 0,
2648 (int) BFD_RELOC_LO16
);
2651 if (lo32
.X_add_number
& 0x80000000)
2653 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2654 (int) BFD_RELOC_HI16
);
2655 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, reg
,
2656 (int) BFD_RELOC_LO16
);
2661 /* Check for 16bit shifted constant: */
2663 tmp
.X_add_number
= hi32
.X_add_number
<< shift
| lo32
.X_add_number
;
2664 /* We know that hi32 is non-zero, so start the mask on the first
2665 bit of the hi32 value: */
2669 if ((tmp
.X_add_number
& ~((offsetT
)0xffff << shift
)) == 0)
2671 tmp
.X_op
= O_constant
;
2672 tmp
.X_add_number
>>= shift
;
2673 macro_build ((char *) NULL
, counter
, &tmp
, "ori", "t,r,i", reg
, 0,
2674 (int) BFD_RELOC_LO16
);
2675 macro_build ((char *) NULL
, counter
, NULL
,
2676 (shift
>= 32) ? "dsll32" : "dsll",
2677 "d,w,<", reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
2681 } while (shift
<= (64 - 16));
2685 tmp
.X_add_number
= hi32
.X_add_number
<< shift
| lo32
.X_add_number
;
2686 while ((tmp
.X_add_number
& 1) == 0)
2688 tmp
.X_add_number
>>= 1;
2691 if (((tmp
.X_add_number
+ 1) & tmp
.X_add_number
) == 0) /* (power-of-2 - 1) */
2693 shift
= COUNT_TOP_ZEROES((unsigned int)hi32
.X_add_number
);
2696 tmp
.X_op
= O_constant
;
2697 tmp
.X_add_number
= (offsetT
)-1;
2698 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j", reg
, 0,
2699 (int) BFD_RELOC_LO16
); /* set all ones */
2703 macro_build ((char *) NULL
, counter
, NULL
,
2704 (freg
>= 32) ? "dsll32" : "dsll",
2706 (freg
>= 32) ? freg
- 32 : freg
);
2708 macro_build ((char *) NULL
, counter
, NULL
, (shift
>= 32) ? "dsrl32" : "dsrl",
2709 "d,w,<", reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
2713 load_register (counter
, reg
, &hi32
, 0);
2716 if ((lo32
.X_add_number
& 0xffff0000) == 0)
2720 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
2729 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
2731 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2732 (int) BFD_RELOC_HI16
);
2733 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
2740 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
2745 mid16
.X_add_number
>>= 16;
2746 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
2747 freg
, (int) BFD_RELOC_LO16
);
2748 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
2752 if ((lo32
.X_add_number
& 0xffff) != 0)
2753 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
2754 (int) BFD_RELOC_LO16
);
2757 /* Load an address into a register. */
2760 load_address (counter
, reg
, ep
)
2767 if (ep
->X_op
!= O_constant
2768 && ep
->X_op
!= O_symbol
)
2770 as_bad ("expression too complex");
2771 ep
->X_op
= O_constant
;
2774 if (ep
->X_op
== O_constant
)
2776 load_register (counter
, reg
, ep
, 0);
2780 if (mips_pic
== NO_PIC
)
2782 /* If this is a reference to a GP relative symbol, we want
2783 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2785 lui $reg,<sym> (BFD_RELOC_HI16_S)
2786 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2787 If we have an addend, we always use the latter form. */
2788 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
2789 || nopic_need_relax (ep
->X_add_symbol
))
2794 macro_build ((char *) NULL
, counter
, ep
,
2795 mips_isa
< 3 ? "addiu" : "daddiu",
2796 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2797 p
= frag_var (rs_machine_dependent
, 8, 0,
2798 RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros
),
2799 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2801 macro_build_lui (p
, counter
, ep
, reg
);
2804 macro_build (p
, counter
, ep
,
2805 mips_isa
< 3 ? "addiu" : "daddiu",
2806 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2808 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
2812 /* If this is a reference to an external symbol, we want
2813 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2815 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2817 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2818 If there is a constant, it must be added in after. */
2819 ex
.X_add_number
= ep
->X_add_number
;
2820 ep
->X_add_number
= 0;
2822 macro_build ((char *) NULL
, counter
, ep
,
2823 mips_isa
< 3 ? "lw" : "ld",
2824 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2825 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
2826 p
= frag_var (rs_machine_dependent
, 4, 0,
2827 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
2828 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2829 macro_build (p
, counter
, ep
,
2830 mips_isa
< 3 ? "addiu" : "daddiu",
2831 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2832 if (ex
.X_add_number
!= 0)
2834 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2835 as_bad ("PIC code offset overflow (max 16 signed bits)");
2836 ex
.X_op
= O_constant
;
2837 macro_build ((char *) NULL
, counter
, &ex
,
2838 mips_isa
< 3 ? "addiu" : "daddiu",
2839 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2842 else if (mips_pic
== SVR4_PIC
)
2847 /* This is the large GOT case. If this is a reference to an
2848 external symbol, we want
2849 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
2851 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
2852 Otherwise, for a reference to a local symbol, we want
2853 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2855 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2856 If there is a constant, it must be added in after. */
2857 ex
.X_add_number
= ep
->X_add_number
;
2858 ep
->X_add_number
= 0;
2859 if (reg_needs_delay (GP
))
2864 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2865 (int) BFD_RELOC_MIPS_GOT_HI16
);
2866 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
2867 mips_isa
< 3 ? "addu" : "daddu",
2868 "d,v,t", reg
, reg
, GP
);
2869 macro_build ((char *) NULL
, counter
, ep
,
2870 mips_isa
< 3 ? "lw" : "ld",
2871 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
2872 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
2873 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
2874 mips_warn_about_macros
),
2875 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2878 /* We need a nop before loading from $gp. This special
2879 check is required because the lui which starts the main
2880 instruction stream does not refer to $gp, and so will not
2881 insert the nop which may be required. */
2882 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2885 macro_build (p
, counter
, ep
,
2886 mips_isa
< 3 ? "lw" : "ld",
2887 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2889 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2891 macro_build (p
, counter
, ep
,
2892 mips_isa
< 3 ? "addiu" : "daddiu",
2893 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2894 if (ex
.X_add_number
!= 0)
2896 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2897 as_bad ("PIC code offset overflow (max 16 signed bits)");
2898 ex
.X_op
= O_constant
;
2899 macro_build ((char *) NULL
, counter
, &ex
,
2900 mips_isa
< 3 ? "addiu" : "daddiu",
2901 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2904 else if (mips_pic
== EMBEDDED_PIC
)
2907 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2909 macro_build ((char *) NULL
, counter
, ep
,
2910 mips_isa
< 3 ? "addiu" : "daddiu",
2911 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2919 * This routine implements the seemingly endless macro or synthesized
2920 * instructions and addressing modes in the mips assembly language. Many
2921 * of these macros are simple and are similar to each other. These could
2922 * probably be handled by some kind of table or grammer aproach instead of
2923 * this verbose method. Others are not simple macros but are more like
2924 * optimizing code generation.
2925 * One interesting optimization is when several store macros appear
2926 * consecutivly that would load AT with the upper half of the same address.
2927 * The ensuing load upper instructions are ommited. This implies some kind
2928 * of global optimization. We currently only optimize within a single macro.
2929 * For many of the load and store macros if the address is specified as a
2930 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
2931 * first load register 'at' with zero and use it as the base register. The
2932 * mips assembler simply uses register $zero. Just one tiny optimization
2937 struct mips_cl_insn
*ip
;
2939 register int treg
, sreg
, dreg
, breg
;
2954 bfd_reloc_code_real_type r
;
2956 int hold_mips_optimize
;
2960 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
2961 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
2962 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
2963 mask
= ip
->insn_mo
->mask
;
2965 expr1
.X_op
= O_constant
;
2966 expr1
.X_op_symbol
= NULL
;
2967 expr1
.X_add_symbol
= NULL
;
2968 expr1
.X_add_number
= 1;
2980 mips_emit_delays (true);
2982 mips_any_noreorder
= 1;
2984 expr1
.X_add_number
= 8;
2985 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
2987 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2989 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
2990 macro_build ((char *) NULL
, &icnt
, NULL
,
2991 dbl
? "dsub" : "sub",
2992 "d,v,t", dreg
, 0, sreg
);
3015 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3017 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3018 (int) BFD_RELOC_LO16
);
3021 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3022 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3041 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3043 if (mask
!= M_NOR_I
)
3044 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3045 sreg
, (int) BFD_RELOC_LO16
);
3048 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3049 treg
, sreg
, (int) BFD_RELOC_LO16
);
3050 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
3056 load_register (&icnt
, AT
, &imm_expr
, 0);
3057 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3074 if (imm_expr
.X_add_number
== 0)
3076 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3080 load_register (&icnt
, AT
, &imm_expr
, 0);
3081 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3089 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3090 likely
? "bgezl" : "bgez",
3096 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3097 likely
? "blezl" : "blez",
3101 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3102 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3103 likely
? "beql" : "beq",
3110 /* check for > max integer */
3111 maxnum
= 0x7fffffff;
3119 if (imm_expr
.X_add_number
>= maxnum
3120 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
3123 /* result is always false */
3126 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
3127 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3131 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
3132 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3137 imm_expr
.X_add_number
++;
3141 if (mask
== M_BGEL_I
)
3143 if (imm_expr
.X_add_number
== 0)
3145 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3146 likely
? "bgezl" : "bgez",
3150 if (imm_expr
.X_add_number
== 1)
3152 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3153 likely
? "bgtzl" : "bgtz",
3157 maxnum
= 0x7fffffff;
3165 maxnum
= - maxnum
- 1;
3166 if (imm_expr
.X_add_number
<= maxnum
3167 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
3170 /* result is always true */
3171 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
3172 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3175 set_at (&icnt
, sreg
, 0);
3176 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3177 likely
? "beql" : "beq",
3188 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3189 likely
? "beql" : "beq",
3193 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3195 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3196 likely
? "beql" : "beq",
3203 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
3205 imm_expr
.X_add_number
++;
3209 if (mask
== M_BGEUL_I
)
3211 if (imm_expr
.X_add_number
== 0)
3213 if (imm_expr
.X_add_number
== 1)
3215 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3216 likely
? "bnel" : "bne",
3220 set_at (&icnt
, sreg
, 1);
3221 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3222 likely
? "beql" : "beq",
3231 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3232 likely
? "bgtzl" : "bgtz",
3238 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3239 likely
? "bltzl" : "bltz",
3243 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3244 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3245 likely
? "bnel" : "bne",
3254 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3255 likely
? "bnel" : "bne",
3261 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3263 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3264 likely
? "bnel" : "bne",
3273 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3274 likely
? "blezl" : "blez",
3280 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3281 likely
? "bgezl" : "bgez",
3285 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3286 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3287 likely
? "beql" : "beq",
3294 maxnum
= 0x7fffffff;
3302 if (imm_expr
.X_add_number
>= maxnum
3303 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
3305 imm_expr
.X_add_number
++;
3309 if (mask
== M_BLTL_I
)
3311 if (imm_expr
.X_add_number
== 0)
3313 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3314 likely
? "bltzl" : "bltz",
3318 if (imm_expr
.X_add_number
== 1)
3320 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3321 likely
? "blezl" : "blez",
3325 set_at (&icnt
, sreg
, 0);
3326 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3327 likely
? "bnel" : "bne",
3336 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3337 likely
? "beql" : "beq",
3343 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3345 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3346 likely
? "beql" : "beq",
3353 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
3355 imm_expr
.X_add_number
++;
3359 if (mask
== M_BLTUL_I
)
3361 if (imm_expr
.X_add_number
== 0)
3363 if (imm_expr
.X_add_number
== 1)
3365 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3366 likely
? "beql" : "beq",
3370 set_at (&icnt
, sreg
, 1);
3371 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3372 likely
? "bnel" : "bne",
3381 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3382 likely
? "bltzl" : "bltz",
3388 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3389 likely
? "bgtzl" : "bgtz",
3393 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3394 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3395 likely
? "bnel" : "bne",
3406 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3407 likely
? "bnel" : "bne",
3411 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3413 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3414 likely
? "bnel" : "bne",
3430 as_warn ("Divide by zero.");
3432 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3434 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3438 mips_emit_delays (true);
3440 mips_any_noreorder
= 1;
3441 macro_build ((char *) NULL
, &icnt
, NULL
,
3442 dbl
? "ddiv" : "div",
3443 "z,s,t", sreg
, treg
);
3445 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3448 expr1
.X_add_number
= 8;
3449 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3450 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3451 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3453 expr1
.X_add_number
= -1;
3454 macro_build ((char *) NULL
, &icnt
, &expr1
,
3455 dbl
? "daddiu" : "addiu",
3456 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
3457 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
3458 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
3461 expr1
.X_add_number
= 1;
3462 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
3463 (int) BFD_RELOC_LO16
);
3464 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
3469 expr1
.X_add_number
= 0x80000000;
3470 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
3471 (int) BFD_RELOC_HI16
);
3474 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
3477 expr1
.X_add_number
= 8;
3478 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
3479 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3480 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3483 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
3522 if (imm_expr
.X_add_number
== 0)
3524 as_warn ("Divide by zero.");
3526 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3528 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3531 if (imm_expr
.X_add_number
== 1)
3533 if (strcmp (s2
, "mflo") == 0)
3534 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
3537 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3540 if (imm_expr
.X_add_number
== -1
3541 && s
[strlen (s
) - 1] != 'u')
3543 if (strcmp (s2
, "mflo") == 0)
3546 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
3549 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
3553 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3557 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3558 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
3559 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
3578 mips_emit_delays (true);
3580 mips_any_noreorder
= 1;
3581 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
3583 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3586 expr1
.X_add_number
= 8;
3587 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3588 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3589 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3592 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
3598 /* Load the address of a symbol into a register. If breg is not
3599 zero, we then add a base register to it. */
3601 /* When generating embedded PIC code, we permit expressions of
3604 where bar is an address in the .text section. These are used
3605 when getting the addresses of functions. We don't permit
3606 X_add_number to be non-zero, because if the symbol is
3607 external the relaxing code needs to know that any addend is
3608 purely the offset to X_op_symbol. */
3609 if (mips_pic
== EMBEDDED_PIC
3610 && offset_expr
.X_op
== O_subtract
3611 && now_seg
== text_section
3612 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
3613 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
3614 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
3615 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
3616 ->sy_value
.X_add_symbol
)
3619 && offset_expr
.X_add_number
== 0)
3621 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3622 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
3623 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3624 mips_isa
< 3 ? "addiu" : "daddiu",
3625 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
3629 if (offset_expr
.X_op
!= O_symbol
3630 && offset_expr
.X_op
!= O_constant
)
3632 as_bad ("expression too complex");
3633 offset_expr
.X_op
= O_constant
;
3647 if (offset_expr
.X_op
== O_constant
)
3648 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
3649 else if (mips_pic
== NO_PIC
)
3651 /* If this is a reference to an GP relative symbol, we want
3652 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3654 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3655 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3656 If we have a constant, we need two instructions anyhow,
3657 so we may as well always use the latter form. */
3658 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
3659 || nopic_need_relax (offset_expr
.X_add_symbol
))
3664 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3665 mips_isa
< 3 ? "addiu" : "daddiu",
3666 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3667 p
= frag_var (rs_machine_dependent
, 8, 0,
3668 RELAX_ENCODE (4, 8, 0, 4, 0,
3669 mips_warn_about_macros
),
3670 offset_expr
.X_add_symbol
, (long) 0,
3673 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3676 macro_build (p
, &icnt
, &offset_expr
,
3677 mips_isa
< 3 ? "addiu" : "daddiu",
3678 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3680 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3682 /* If this is a reference to an external symbol, and there
3683 is no constant, we want
3684 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3685 For a local symbol, we want
3686 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3688 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3690 If we have a small constant, and this is a reference to
3691 an external symbol, we want
3692 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3694 addiu $tempreg,$tempreg,<constant>
3695 For a local symbol, we want the same instruction
3696 sequence, but we output a BFD_RELOC_LO16 reloc on the
3699 If we have a large constant, and this is a reference to
3700 an external symbol, we want
3701 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3702 lui $at,<hiconstant>
3703 addiu $at,$at,<loconstant>
3704 addu $tempreg,$tempreg,$at
3705 For a local symbol, we want the same instruction
3706 sequence, but we output a BFD_RELOC_LO16 reloc on the
3707 addiu instruction. */
3708 expr1
.X_add_number
= offset_expr
.X_add_number
;
3709 offset_expr
.X_add_number
= 0;
3711 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3713 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3714 if (expr1
.X_add_number
== 0)
3722 /* We're going to put in an addu instruction using
3723 tempreg, so we may as well insert the nop right
3725 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3729 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
3730 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
3732 ? mips_warn_about_macros
3734 offset_expr
.X_add_symbol
, (long) 0,
3738 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3741 macro_build (p
, &icnt
, &expr1
,
3742 mips_isa
< 3 ? "addiu" : "daddiu",
3743 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3744 /* FIXME: If breg == 0, and the next instruction uses
3745 $tempreg, then if this variant case is used an extra
3746 nop will be generated. */
3748 else if (expr1
.X_add_number
>= -0x8000
3749 && expr1
.X_add_number
< 0x8000)
3751 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3753 macro_build ((char *) NULL
, &icnt
, &expr1
,
3754 mips_isa
< 3 ? "addiu" : "daddiu",
3755 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3756 (void) frag_var (rs_machine_dependent
, 0, 0,
3757 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
3758 offset_expr
.X_add_symbol
, (long) 0,
3765 /* If we are going to add in a base register, and the
3766 target register and the base register are the same,
3767 then we are using AT as a temporary register. Since
3768 we want to load the constant into AT, we add our
3769 current AT (from the global offset table) and the
3770 register into the register now, and pretend we were
3771 not using a base register. */
3776 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3778 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3779 mips_isa
< 3 ? "addu" : "daddu",
3780 "d,v,t", treg
, AT
, breg
);
3786 /* Set mips_optimize around the lui instruction to avoid
3787 inserting an unnecessary nop after the lw. */
3788 hold_mips_optimize
= mips_optimize
;
3790 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
3791 mips_optimize
= hold_mips_optimize
;
3793 macro_build ((char *) NULL
, &icnt
, &expr1
,
3794 mips_isa
< 3 ? "addiu" : "daddiu",
3795 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3796 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3797 mips_isa
< 3 ? "addu" : "daddu",
3798 "d,v,t", tempreg
, tempreg
, AT
);
3799 (void) frag_var (rs_machine_dependent
, 0, 0,
3800 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
3801 offset_expr
.X_add_symbol
, (long) 0,
3806 else if (mips_pic
== SVR4_PIC
)
3810 /* This is the large GOT case. If this is a reference to an
3811 external symbol, and there is no constant, we want
3812 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3813 addu $tempreg,$tempreg,$gp
3814 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3815 For a local symbol, we want
3816 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3818 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3820 If we have a small constant, and this is a reference to
3821 an external symbol, we want
3822 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3823 addu $tempreg,$tempreg,$gp
3824 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3826 addiu $tempreg,$tempreg,<constant>
3827 For a local symbol, we want
3828 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3830 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
3832 If we have a large constant, and this is a reference to
3833 an external symbol, we want
3834 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3835 addu $tempreg,$tempreg,$gp
3836 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3837 lui $at,<hiconstant>
3838 addiu $at,$at,<loconstant>
3839 addu $tempreg,$tempreg,$at
3840 For a local symbol, we want
3841 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3842 lui $at,<hiconstant>
3843 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
3844 addu $tempreg,$tempreg,$at
3846 expr1
.X_add_number
= offset_expr
.X_add_number
;
3847 offset_expr
.X_add_number
= 0;
3849 if (reg_needs_delay (GP
))
3853 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3854 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
3855 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3856 mips_isa
< 3 ? "addu" : "daddu",
3857 "d,v,t", tempreg
, tempreg
, GP
);
3858 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3860 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
3862 if (expr1
.X_add_number
== 0)
3870 /* We're going to put in an addu instruction using
3871 tempreg, so we may as well insert the nop right
3873 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3878 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3879 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
3882 ? mips_warn_about_macros
3884 offset_expr
.X_add_symbol
, (long) 0,
3887 else if (expr1
.X_add_number
>= -0x8000
3888 && expr1
.X_add_number
< 0x8000)
3890 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3892 macro_build ((char *) NULL
, &icnt
, &expr1
,
3893 mips_isa
< 3 ? "addiu" : "daddiu",
3894 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3896 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3897 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
3899 ? mips_warn_about_macros
3901 offset_expr
.X_add_symbol
, (long) 0,
3908 /* If we are going to add in a base register, and the
3909 target register and the base register are the same,
3910 then we are using AT as a temporary register. Since
3911 we want to load the constant into AT, we add our
3912 current AT (from the global offset table) and the
3913 register into the register now, and pretend we were
3914 not using a base register. */
3922 assert (tempreg
== AT
);
3923 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3925 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3926 mips_isa
< 3 ? "addu" : "daddu",
3927 "d,v,t", treg
, AT
, breg
);
3932 /* Set mips_optimize around the lui instruction to avoid
3933 inserting an unnecessary nop after the lw. */
3934 hold_mips_optimize
= mips_optimize
;
3936 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
3937 mips_optimize
= hold_mips_optimize
;
3939 macro_build ((char *) NULL
, &icnt
, &expr1
,
3940 mips_isa
< 3 ? "addiu" : "daddiu",
3941 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3942 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3943 mips_isa
< 3 ? "addu" : "daddu",
3944 "d,v,t", dreg
, dreg
, AT
);
3946 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
3947 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
3950 ? mips_warn_about_macros
3952 offset_expr
.X_add_symbol
, (long) 0,
3960 /* This is needed because this instruction uses $gp, but
3961 the first instruction on the main stream does not. */
3962 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3965 macro_build (p
, &icnt
, &offset_expr
,
3967 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3969 if (expr1
.X_add_number
>= -0x8000
3970 && expr1
.X_add_number
< 0x8000)
3972 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3974 macro_build (p
, &icnt
, &expr1
,
3975 mips_isa
< 3 ? "addiu" : "daddiu",
3976 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3977 /* FIXME: If add_number is 0, and there was no base
3978 register, the external symbol case ended with a load,
3979 so if the symbol turns out to not be external, and
3980 the next instruction uses tempreg, an unnecessary nop
3981 will be inserted. */
3987 /* We must add in the base register now, as in the
3988 external symbol case. */
3989 assert (tempreg
== AT
);
3990 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3992 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3993 mips_isa
< 3 ? "addu" : "daddu",
3994 "d,v,t", treg
, AT
, breg
);
3997 /* We set breg to 0 because we have arranged to add
3998 it in in both cases. */
4002 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4004 macro_build (p
, &icnt
, &expr1
,
4005 mips_isa
< 3 ? "addiu" : "daddiu",
4006 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4008 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4009 mips_isa
< 3 ? "addu" : "daddu",
4010 "d,v,t", tempreg
, tempreg
, AT
);
4014 else if (mips_pic
== EMBEDDED_PIC
)
4017 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4019 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4020 mips_isa
< 3 ? "addiu" : "daddiu",
4021 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4027 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4028 mips_isa
< 3 ? "addu" : "daddu",
4029 "d,v,t", treg
, tempreg
, breg
);
4037 /* The j instruction may not be used in PIC code, since it
4038 requires an absolute address. We convert it to a b
4040 if (mips_pic
== NO_PIC
)
4041 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
4043 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4046 /* The jal instructions must be handled as macros because when
4047 generating PIC code they expand to multi-instruction
4048 sequences. Normally they are simple instructions. */
4053 if (mips_pic
== NO_PIC
4054 || mips_pic
== EMBEDDED_PIC
)
4055 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4057 else if (mips_pic
== SVR4_PIC
)
4059 if (sreg
!= PIC_CALL_REG
)
4060 as_warn ("MIPS PIC call to register other than $25");
4062 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4064 if (mips_cprestore_offset
< 0)
4065 as_warn ("No .cprestore pseudo-op used in PIC code");
4068 expr1
.X_add_number
= mips_cprestore_offset
;
4069 macro_build ((char *) NULL
, &icnt
, &expr1
,
4070 mips_isa
< 3 ? "lw" : "ld",
4071 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
4080 if (mips_pic
== NO_PIC
)
4081 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
4082 else if (mips_pic
== SVR4_PIC
)
4084 /* If this is a reference to an external symbol, and we are
4085 using a small GOT, we want
4086 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4090 lw $gp,cprestore($sp)
4091 The cprestore value is set using the .cprestore
4092 pseudo-op. If we are using a big GOT, we want
4093 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4095 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
4099 lw $gp,cprestore($sp)
4100 If the symbol is not external, we want
4101 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4103 addiu $25,$25,<sym> (BFD_RELOC_LO16)
4106 lw $gp,cprestore($sp) */
4110 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4111 mips_isa
< 3 ? "lw" : "ld",
4112 "t,o(b)", PIC_CALL_REG
,
4113 (int) BFD_RELOC_MIPS_CALL16
, GP
);
4114 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4116 p
= frag_var (rs_machine_dependent
, 4, 0,
4117 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4118 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
4124 if (reg_needs_delay (GP
))
4128 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4129 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4130 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4131 mips_isa
< 3 ? "addu" : "daddu",
4132 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4133 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4134 mips_isa
< 3 ? "lw" : "ld",
4135 "t,o(b)", PIC_CALL_REG
,
4136 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4137 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4139 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4140 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4142 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
4145 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4148 macro_build (p
, &icnt
, &offset_expr
,
4149 mips_isa
< 3 ? "lw" : "ld",
4150 "t,o(b)", PIC_CALL_REG
,
4151 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4153 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4156 macro_build (p
, &icnt
, &offset_expr
,
4157 mips_isa
< 3 ? "addiu" : "daddiu",
4158 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4159 (int) BFD_RELOC_LO16
);
4160 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4161 "jalr", "s", PIC_CALL_REG
);
4162 if (mips_cprestore_offset
< 0)
4163 as_warn ("No .cprestore pseudo-op used in PIC code");
4167 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4169 expr1
.X_add_number
= mips_cprestore_offset
;
4170 macro_build ((char *) NULL
, &icnt
, &expr1
,
4171 mips_isa
< 3 ? "lw" : "ld",
4172 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4176 else if (mips_pic
== EMBEDDED_PIC
)
4178 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4179 /* The linker may expand the call to a longer sequence which
4180 uses $at, so we must break rather than return. */
4256 if (breg
== treg
|| coproc
|| lr
)
4325 if (mask
== M_LWC1_AB
4326 || mask
== M_SWC1_AB
4327 || mask
== M_LDC1_AB
4328 || mask
== M_SDC1_AB
4337 if (offset_expr
.X_op
!= O_constant
4338 && offset_expr
.X_op
!= O_symbol
)
4340 as_bad ("expression too complex");
4341 offset_expr
.X_op
= O_constant
;
4344 /* A constant expression in PIC code can be handled just as it
4345 is in non PIC code. */
4346 if (mips_pic
== NO_PIC
4347 || offset_expr
.X_op
== O_constant
)
4349 /* If this is a reference to a GP relative symbol, and there
4350 is no base register, we want
4351 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4352 Otherwise, if there is no base register, we want
4353 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4354 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4355 If we have a constant, we need two instructions anyhow,
4356 so we always use the latter form.
4358 If we have a base register, and this is a reference to a
4359 GP relative symbol, we want
4360 addu $tempreg,$breg,$gp
4361 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4363 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4364 addu $tempreg,$tempreg,$breg
4365 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4366 With a constant we always use the latter case. */
4369 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4370 || nopic_need_relax (offset_expr
.X_add_symbol
))
4375 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4376 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4377 p
= frag_var (rs_machine_dependent
, 8, 0,
4378 RELAX_ENCODE (4, 8, 0, 4, 0,
4379 (mips_warn_about_macros
4380 || (used_at
&& mips_noat
))),
4381 offset_expr
.X_add_symbol
, (long) 0,
4385 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4388 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4389 (int) BFD_RELOC_LO16
, tempreg
);
4393 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4394 || nopic_need_relax (offset_expr
.X_add_symbol
))
4399 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4400 mips_isa
< 3 ? "addu" : "daddu",
4401 "d,v,t", tempreg
, breg
, GP
);
4402 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4403 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4404 p
= frag_var (rs_machine_dependent
, 12, 0,
4405 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
4406 offset_expr
.X_add_symbol
, (long) 0,
4409 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4412 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4413 mips_isa
< 3 ? "addu" : "daddu",
4414 "d,v,t", tempreg
, tempreg
, breg
);
4417 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4418 (int) BFD_RELOC_LO16
, tempreg
);
4421 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4423 /* If this is a reference to an external symbol, we want
4424 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4426 <op> $treg,0($tempreg)
4428 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4430 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4431 <op> $treg,0($tempreg)
4432 If there is a base register, we add it to $tempreg before
4433 the <op>. If there is a constant, we stick it in the
4434 <op> instruction. We don't handle constants larger than
4435 16 bits, because we have no way to load the upper 16 bits
4436 (actually, we could handle them for the subset of cases
4437 in which we are not using $at). */
4438 assert (offset_expr
.X_op
== O_symbol
);
4439 expr1
.X_add_number
= offset_expr
.X_add_number
;
4440 offset_expr
.X_add_number
= 0;
4441 if (expr1
.X_add_number
< -0x8000
4442 || expr1
.X_add_number
>= 0x8000)
4443 as_bad ("PIC code offset overflow (max 16 signed bits)");
4445 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4446 mips_isa
< 3 ? "lw" : "ld",
4447 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4448 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4449 p
= frag_var (rs_machine_dependent
, 4, 0,
4450 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4451 offset_expr
.X_add_symbol
, (long) 0,
4453 macro_build (p
, &icnt
, &offset_expr
,
4454 mips_isa
< 3 ? "addiu" : "daddiu",
4455 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4457 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4458 mips_isa
< 3 ? "addu" : "daddu",
4459 "d,v,t", tempreg
, tempreg
, breg
);
4460 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
4461 (int) BFD_RELOC_LO16
, tempreg
);
4463 else if (mips_pic
== SVR4_PIC
)
4467 /* If this is a reference to an external symbol, we want
4468 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4469 addu $tempreg,$tempreg,$gp
4470 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4471 <op> $treg,0($tempreg)
4473 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4475 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4476 <op> $treg,0($tempreg)
4477 If there is a base register, we add it to $tempreg before
4478 the <op>. If there is a constant, we stick it in the
4479 <op> instruction. We don't handle constants larger than
4480 16 bits, because we have no way to load the upper 16 bits
4481 (actually, we could handle them for the subset of cases
4482 in which we are not using $at). */
4483 assert (offset_expr
.X_op
== O_symbol
);
4484 expr1
.X_add_number
= offset_expr
.X_add_number
;
4485 offset_expr
.X_add_number
= 0;
4486 if (expr1
.X_add_number
< -0x8000
4487 || expr1
.X_add_number
>= 0x8000)
4488 as_bad ("PIC code offset overflow (max 16 signed bits)");
4489 if (reg_needs_delay (GP
))
4494 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4495 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4496 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4497 mips_isa
< 3 ? "addu" : "daddu",
4498 "d,v,t", tempreg
, tempreg
, GP
);
4499 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4500 mips_isa
< 3 ? "lw" : "ld",
4501 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4503 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4504 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
4505 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
4508 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4511 macro_build (p
, &icnt
, &offset_expr
,
4512 mips_isa
< 3 ? "lw" : "ld",
4513 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4515 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4517 macro_build (p
, &icnt
, &offset_expr
,
4518 mips_isa
< 3 ? "addiu" : "daddiu",
4519 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4521 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4522 mips_isa
< 3 ? "addu" : "daddu",
4523 "d,v,t", tempreg
, tempreg
, breg
);
4524 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
4525 (int) BFD_RELOC_LO16
, tempreg
);
4527 else if (mips_pic
== EMBEDDED_PIC
)
4529 /* If there is no base register, we want
4530 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4531 If there is a base register, we want
4532 addu $tempreg,$breg,$gp
4533 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4535 assert (offset_expr
.X_op
== O_symbol
);
4538 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4539 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4544 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4545 mips_isa
< 3 ? "addu" : "daddu",
4546 "d,v,t", tempreg
, breg
, GP
);
4547 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4548 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4561 load_register (&icnt
, treg
, &imm_expr
, 0);
4565 load_register (&icnt
, treg
, &imm_expr
, 1);
4569 if (imm_expr
.X_op
== O_constant
)
4571 load_register (&icnt
, AT
, &imm_expr
, 0);
4572 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4573 "mtc1", "t,G", AT
, treg
);
4578 assert (offset_expr
.X_op
== O_symbol
4579 && strcmp (segment_name (S_GET_SEGMENT
4580 (offset_expr
.X_add_symbol
)),
4582 && offset_expr
.X_add_number
== 0);
4583 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4584 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
4589 /* We know that sym is in the .rdata section. First we get the
4590 upper 16 bits of the address. */
4591 if (mips_pic
== NO_PIC
)
4593 /* FIXME: This won't work for a 64 bit address. */
4594 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
4596 else if (mips_pic
== SVR4_PIC
)
4598 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4599 mips_isa
< 3 ? "lw" : "ld",
4600 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4602 else if (mips_pic
== EMBEDDED_PIC
)
4604 /* For embedded PIC we pick up the entire address off $gp in
4605 a single instruction. */
4606 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4607 mips_isa
< 3 ? "addiu" : "daddiu",
4608 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4609 offset_expr
.X_op
= O_constant
;
4610 offset_expr
.X_add_number
= 0;
4615 /* Now we load the register(s). */
4617 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
4618 treg
, (int) BFD_RELOC_LO16
, AT
);
4621 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
4622 treg
, (int) BFD_RELOC_LO16
, AT
);
4625 /* FIXME: How in the world do we deal with the possible
4627 offset_expr
.X_add_number
+= 4;
4628 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
4629 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
4633 /* To avoid confusion in tc_gen_reloc, we must ensure that this
4634 does not become a variant frag. */
4635 frag_wane (frag_now
);
4641 assert (offset_expr
.X_op
== O_symbol
4642 && offset_expr
.X_add_number
== 0);
4643 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
4644 if (strcmp (s
, ".lit8") == 0)
4648 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
4649 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
4653 r
= BFD_RELOC_MIPS_LITERAL
;
4658 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
4659 if (mips_pic
== SVR4_PIC
)
4660 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4661 mips_isa
< 3 ? "lw" : "ld",
4662 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4665 /* FIXME: This won't work for a 64 bit address. */
4666 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
4671 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
4672 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
4674 /* To avoid confusion in tc_gen_reloc, we must ensure
4675 that this does not become a variant frag. */
4676 frag_wane (frag_now
);
4687 /* Even on a big endian machine $fn comes before $fn+1. We have
4688 to adjust when loading from memory. */
4691 assert (mips_isa
< 2);
4692 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4693 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
4695 /* FIXME: A possible overflow which I don't know how to deal
4697 offset_expr
.X_add_number
+= 4;
4698 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4699 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
4702 /* To avoid confusion in tc_gen_reloc, we must ensure that this
4703 does not become a variant frag. */
4704 frag_wane (frag_now
);
4713 * The MIPS assembler seems to check for X_add_number not
4714 * being double aligned and generating:
4717 * addiu at,at,%lo(foo+1)
4720 * But, the resulting address is the same after relocation so why
4721 * generate the extra instruction?
4768 if (offset_expr
.X_op
!= O_symbol
4769 && offset_expr
.X_op
!= O_constant
)
4771 as_bad ("expression too complex");
4772 offset_expr
.X_op
= O_constant
;
4775 /* Even on a big endian machine $fn comes before $fn+1. We have
4776 to adjust when loading from memory. We set coproc if we must
4777 load $fn+1 first. */
4778 if (byte_order
== LITTLE_ENDIAN
)
4781 if (mips_pic
== NO_PIC
4782 || offset_expr
.X_op
== O_constant
)
4784 /* If this is a reference to a GP relative symbol, we want
4785 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4786 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
4787 If we have a base register, we use this
4789 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
4790 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
4791 If this is not a GP relative symbol, we want
4792 lui $at,<sym> (BFD_RELOC_HI16_S)
4793 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4794 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4795 If there is a base register, we add it to $at after the
4796 lui instruction. If there is a constant, we always use
4798 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4799 || nopic_need_relax (offset_expr
.X_add_symbol
))
4818 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4819 mips_isa
< 3 ? "addu" : "daddu",
4820 "d,v,t", AT
, breg
, GP
);
4826 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4827 coproc
? treg
+ 1 : treg
,
4828 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4829 offset_expr
.X_add_number
+= 4;
4831 /* Set mips_optimize to 2 to avoid inserting an
4833 hold_mips_optimize
= mips_optimize
;
4835 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4836 coproc
? treg
: treg
+ 1,
4837 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4838 mips_optimize
= hold_mips_optimize
;
4840 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
4841 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
4842 used_at
&& mips_noat
),
4843 offset_expr
.X_add_symbol
, (long) 0,
4846 /* We just generated two relocs. When tc_gen_reloc
4847 handles this case, it will skip the first reloc and
4848 handle the second. The second reloc already has an
4849 extra addend of 4, which we added above. We must
4850 subtract it out, and then subtract another 4 to make
4851 the first reloc come out right. The second reloc
4852 will come out right because we are going to add 4 to
4853 offset_expr when we build its instruction below. */
4854 offset_expr
.X_add_number
-= 8;
4855 offset_expr
.X_op
= O_constant
;
4857 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
4862 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4863 mips_isa
< 3 ? "addu" : "daddu",
4864 "d,v,t", AT
, breg
, AT
);
4868 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4869 coproc
? treg
+ 1 : treg
,
4870 (int) BFD_RELOC_LO16
, AT
);
4873 /* FIXME: How do we handle overflow here? */
4874 offset_expr
.X_add_number
+= 4;
4875 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4876 coproc
? treg
: treg
+ 1,
4877 (int) BFD_RELOC_LO16
, AT
);
4879 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4883 /* If this is a reference to an external symbol, we want
4884 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4889 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4891 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4892 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4893 If there is a base register we add it to $at before the
4894 lwc1 instructions. If there is a constant we include it
4895 in the lwc1 instructions. */
4897 expr1
.X_add_number
= offset_expr
.X_add_number
;
4898 offset_expr
.X_add_number
= 0;
4899 if (expr1
.X_add_number
< -0x8000
4900 || expr1
.X_add_number
>= 0x8000 - 4)
4901 as_bad ("PIC code offset overflow (max 16 signed bits)");
4906 frag_grow (24 + off
);
4907 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4908 mips_isa
< 3 ? "lw" : "ld",
4909 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4910 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4912 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4913 mips_isa
< 3 ? "addu" : "daddu",
4914 "d,v,t", AT
, breg
, AT
);
4915 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4916 coproc
? treg
+ 1 : treg
,
4917 (int) BFD_RELOC_LO16
, AT
);
4918 expr1
.X_add_number
+= 4;
4920 /* Set mips_optimize to 2 to avoid inserting an undesired
4922 hold_mips_optimize
= mips_optimize
;
4924 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4925 coproc
? treg
: treg
+ 1,
4926 (int) BFD_RELOC_LO16
, AT
);
4927 mips_optimize
= hold_mips_optimize
;
4929 (void) frag_var (rs_machine_dependent
, 0, 0,
4930 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
4931 offset_expr
.X_add_symbol
, (long) 0,
4934 else if (mips_pic
== SVR4_PIC
)
4938 /* If this is a reference to an external symbol, we want
4939 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4941 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
4946 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4948 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4949 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4950 If there is a base register we add it to $at before the
4951 lwc1 instructions. If there is a constant we include it
4952 in the lwc1 instructions. */
4954 expr1
.X_add_number
= offset_expr
.X_add_number
;
4955 offset_expr
.X_add_number
= 0;
4956 if (expr1
.X_add_number
< -0x8000
4957 || expr1
.X_add_number
>= 0x8000 - 4)
4958 as_bad ("PIC code offset overflow (max 16 signed bits)");
4959 if (reg_needs_delay (GP
))
4968 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4969 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4970 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4971 mips_isa
< 3 ? "addu" : "daddu",
4972 "d,v,t", AT
, AT
, GP
);
4973 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4974 mips_isa
< 3 ? "lw" : "ld",
4975 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
4976 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4978 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4979 mips_isa
< 3 ? "addu" : "daddu",
4980 "d,v,t", AT
, breg
, AT
);
4981 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4982 coproc
? treg
+ 1 : treg
,
4983 (int) BFD_RELOC_LO16
, AT
);
4984 expr1
.X_add_number
+= 4;
4986 /* Set mips_optimize to 2 to avoid inserting an undesired
4988 hold_mips_optimize
= mips_optimize
;
4990 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4991 coproc
? treg
: treg
+ 1,
4992 (int) BFD_RELOC_LO16
, AT
);
4993 mips_optimize
= hold_mips_optimize
;
4994 expr1
.X_add_number
-= 4;
4996 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
4997 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
4998 8 + gpdel
+ off
, 1, 0),
4999 offset_expr
.X_add_symbol
, (long) 0,
5003 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5006 macro_build (p
, &icnt
, &offset_expr
,
5007 mips_isa
< 3 ? "lw" : "ld",
5008 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5010 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5014 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5015 mips_isa
< 3 ? "addu" : "daddu",
5016 "d,v,t", AT
, breg
, AT
);
5019 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5020 coproc
? treg
+ 1 : treg
,
5021 (int) BFD_RELOC_LO16
, AT
);
5023 expr1
.X_add_number
+= 4;
5025 /* Set mips_optimize to 2 to avoid inserting an undesired
5027 hold_mips_optimize
= mips_optimize
;
5029 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5030 coproc
? treg
: treg
+ 1,
5031 (int) BFD_RELOC_LO16
, AT
);
5032 mips_optimize
= hold_mips_optimize
;
5034 else if (mips_pic
== EMBEDDED_PIC
)
5036 /* If there is no base register, we use
5037 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5038 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5039 If we have a base register, we use
5041 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5042 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5051 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5052 mips_isa
< 3 ? "addu" : "daddu",
5053 "d,v,t", AT
, breg
, GP
);
5058 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5059 coproc
? treg
+ 1 : treg
,
5060 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5061 offset_expr
.X_add_number
+= 4;
5062 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5063 coproc
? treg
: treg
+ 1,
5064 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5080 assert (mips_isa
< 3);
5081 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5082 (int) BFD_RELOC_LO16
, breg
);
5083 offset_expr
.X_add_number
+= 4;
5084 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
5085 (int) BFD_RELOC_LO16
, breg
);
5087 #ifdef LOSING_COMPILER
5093 as_warn ("Macro used $at after \".set noat\"");
5098 struct mips_cl_insn
*ip
;
5100 register int treg
, sreg
, dreg
, breg
;
5115 bfd_reloc_code_real_type r
;
5118 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
5119 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
5120 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
5121 mask
= ip
->insn_mo
->mask
;
5123 expr1
.X_op
= O_constant
;
5124 expr1
.X_op_symbol
= NULL
;
5125 expr1
.X_add_symbol
= NULL
;
5126 expr1
.X_add_number
= 1;
5130 #endif /* LOSING_COMPILER */
5135 macro_build ((char *) NULL
, &icnt
, NULL
,
5136 dbl
? "dmultu" : "multu",
5138 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5144 /* The MIPS assembler some times generates shifts and adds. I'm
5145 not trying to be that fancy. GCC should do this for us
5147 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5148 macro_build ((char *) NULL
, &icnt
, NULL
,
5149 dbl
? "dmult" : "mult",
5151 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5157 mips_emit_delays (true);
5159 mips_any_noreorder
= 1;
5160 macro_build ((char *) NULL
, &icnt
, NULL
,
5161 dbl
? "dmult" : "mult",
5163 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5164 macro_build ((char *) NULL
, &icnt
, NULL
,
5165 dbl
? "dsra32" : "sra",
5166 "d,w,<", dreg
, dreg
, 31);
5167 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5169 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
5172 expr1
.X_add_number
= 8;
5173 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
5174 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5175 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5178 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5184 mips_emit_delays (true);
5186 mips_any_noreorder
= 1;
5187 macro_build ((char *) NULL
, &icnt
, NULL
,
5188 dbl
? "dmultu" : "multu",
5190 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5191 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5193 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
5196 expr1
.X_add_number
= 8;
5197 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
5198 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5199 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5205 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
5206 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
5207 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
5209 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5213 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
5214 (int) (imm_expr
.X_add_number
& 0x1f));
5215 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
5216 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
5217 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5221 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
5222 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
5223 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
5225 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5229 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
5230 (int) (imm_expr
.X_add_number
& 0x1f));
5231 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
5232 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
5233 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5237 assert (mips_isa
< 2);
5238 /* Even on a big endian machine $fn comes before $fn+1. We have
5239 to adjust when storing to memory. */
5240 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
5241 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
5242 (int) BFD_RELOC_LO16
, breg
);
5243 offset_expr
.X_add_number
+= 4;
5244 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
5245 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
5246 (int) BFD_RELOC_LO16
, breg
);
5251 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5252 treg
, (int) BFD_RELOC_LO16
);
5254 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5255 sreg
, (int) BFD_RELOC_LO16
);
5258 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5260 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5261 dreg
, (int) BFD_RELOC_LO16
);
5266 if (imm_expr
.X_add_number
== 0)
5268 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5269 sreg
, (int) BFD_RELOC_LO16
);
5274 as_warn ("Instruction %s: result is always false",
5276 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
5279 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
5281 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
5282 sreg
, (int) BFD_RELOC_LO16
);
5285 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
5287 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5288 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5289 mips_isa
< 3 ? "addiu" : "daddiu",
5290 "t,r,j", dreg
, sreg
,
5291 (int) BFD_RELOC_LO16
);
5296 load_register (&icnt
, AT
, &imm_expr
, 0);
5297 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5301 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
5302 (int) BFD_RELOC_LO16
);
5307 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
5313 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
5314 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5315 (int) BFD_RELOC_LO16
);
5318 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
5320 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5322 macro_build ((char *) NULL
, &icnt
, &expr1
,
5323 mask
== M_SGE_I
? "slti" : "sltiu",
5324 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5329 load_register (&icnt
, AT
, &imm_expr
, 0);
5330 macro_build ((char *) NULL
, &icnt
, NULL
,
5331 mask
== M_SGE_I
? "slt" : "sltu",
5332 "d,v,t", dreg
, sreg
, AT
);
5335 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5336 (int) BFD_RELOC_LO16
);
5341 case M_SGT
: /* sreg > treg <==> treg < sreg */
5347 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
5350 case M_SGT_I
: /* sreg > I <==> I < sreg */
5356 load_register (&icnt
, AT
, &imm_expr
, 0);
5357 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
5360 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
5366 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
5367 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5368 (int) BFD_RELOC_LO16
);
5371 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
5377 load_register (&icnt
, AT
, &imm_expr
, 0);
5378 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
5379 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5380 (int) BFD_RELOC_LO16
);
5384 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5386 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
5387 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5390 load_register (&icnt
, AT
, &imm_expr
, 0);
5391 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
5395 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5397 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
5398 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5401 load_register (&icnt
, AT
, &imm_expr
, 0);
5402 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
5408 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5411 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5415 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5417 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5423 if (imm_expr
.X_add_number
== 0)
5425 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5431 as_warn ("Instruction %s: result is always true",
5433 macro_build ((char *) NULL
, &icnt
, &expr1
,
5434 mips_isa
< 3 ? "addiu" : "daddiu",
5435 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
5438 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
5440 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
5441 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5444 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
5446 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5447 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5448 mips_isa
< 3 ? "addiu" : "daddiu",
5449 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5454 load_register (&icnt
, AT
, &imm_expr
, 0);
5455 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5459 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
5467 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
5469 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5470 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5471 dbl
? "daddi" : "addi",
5472 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5475 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5476 macro_build ((char *) NULL
, &icnt
, NULL
,
5477 dbl
? "dsub" : "sub",
5478 "d,v,t", dreg
, sreg
, AT
);
5484 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
5486 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5487 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5488 dbl
? "daddiu" : "addiu",
5489 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5492 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5493 macro_build ((char *) NULL
, &icnt
, NULL
,
5494 dbl
? "dsubu" : "subu",
5495 "d,v,t", dreg
, sreg
, AT
);
5516 load_register (&icnt
, AT
, &imm_expr
, 0);
5517 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
5522 assert (mips_isa
< 2);
5523 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
5524 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
5527 * Is the double cfc1 instruction a bug in the mips assembler;
5528 * or is there a reason for it?
5530 mips_emit_delays (true);
5532 mips_any_noreorder
= 1;
5533 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
5534 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
5535 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5536 expr1
.X_add_number
= 3;
5537 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
5538 (int) BFD_RELOC_LO16
);
5539 expr1
.X_add_number
= 2;
5540 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
5541 (int) BFD_RELOC_LO16
);
5542 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
5543 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5544 macro_build ((char *) NULL
, &icnt
, NULL
,
5545 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
5546 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
5547 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5557 if (offset_expr
.X_add_number
>= 0x7fff)
5558 as_bad ("operand overflow");
5559 /* avoid load delay */
5560 if (byte_order
== LITTLE_ENDIAN
)
5561 offset_expr
.X_add_number
+= 1;
5562 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5563 (int) BFD_RELOC_LO16
, breg
);
5564 if (byte_order
== LITTLE_ENDIAN
)
5565 offset_expr
.X_add_number
-= 1;
5567 offset_expr
.X_add_number
+= 1;
5568 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
5569 (int) BFD_RELOC_LO16
, breg
);
5570 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
5571 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
5584 if (offset_expr
.X_add_number
>= 0x8000 - off
)
5585 as_bad ("operand overflow");
5586 if (byte_order
== LITTLE_ENDIAN
)
5587 offset_expr
.X_add_number
+= off
;
5588 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5589 (int) BFD_RELOC_LO16
, breg
);
5590 if (byte_order
== LITTLE_ENDIAN
)
5591 offset_expr
.X_add_number
-= off
;
5593 offset_expr
.X_add_number
+= off
;
5594 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
5595 (int) BFD_RELOC_LO16
, breg
);
5608 load_address (&icnt
, AT
, &offset_expr
);
5610 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5611 mips_isa
< 3 ? "addu" : "daddu",
5612 "d,v,t", AT
, AT
, breg
);
5613 if (byte_order
== LITTLE_ENDIAN
)
5614 expr1
.X_add_number
= off
;
5616 expr1
.X_add_number
= 0;
5617 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
5618 (int) BFD_RELOC_LO16
, AT
);
5619 if (byte_order
== LITTLE_ENDIAN
)
5620 expr1
.X_add_number
= 0;
5622 expr1
.X_add_number
= off
;
5623 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
5624 (int) BFD_RELOC_LO16
, AT
);
5629 load_address (&icnt
, AT
, &offset_expr
);
5631 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5632 mips_isa
< 3 ? "addu" : "daddu",
5633 "d,v,t", AT
, AT
, breg
);
5634 if (byte_order
== BIG_ENDIAN
)
5635 expr1
.X_add_number
= 0;
5636 macro_build ((char *) NULL
, &icnt
, &expr1
,
5637 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
5638 (int) BFD_RELOC_LO16
, AT
);
5639 if (byte_order
== BIG_ENDIAN
)
5640 expr1
.X_add_number
= 1;
5642 expr1
.X_add_number
= 0;
5643 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
5644 (int) BFD_RELOC_LO16
, AT
);
5645 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
5647 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
5652 if (offset_expr
.X_add_number
>= 0x7fff)
5653 as_bad ("operand overflow");
5654 if (byte_order
== BIG_ENDIAN
)
5655 offset_expr
.X_add_number
+= 1;
5656 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
5657 (int) BFD_RELOC_LO16
, breg
);
5658 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
5659 if (byte_order
== BIG_ENDIAN
)
5660 offset_expr
.X_add_number
-= 1;
5662 offset_expr
.X_add_number
+= 1;
5663 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
5664 (int) BFD_RELOC_LO16
, breg
);
5677 if (offset_expr
.X_add_number
>= 0x8000 - off
)
5678 as_bad ("operand overflow");
5679 if (byte_order
== LITTLE_ENDIAN
)
5680 offset_expr
.X_add_number
+= off
;
5681 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5682 (int) BFD_RELOC_LO16
, breg
);
5683 if (byte_order
== LITTLE_ENDIAN
)
5684 offset_expr
.X_add_number
-= off
;
5686 offset_expr
.X_add_number
+= off
;
5687 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
5688 (int) BFD_RELOC_LO16
, breg
);
5701 load_address (&icnt
, AT
, &offset_expr
);
5703 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5704 mips_isa
< 3 ? "addu" : "daddu",
5705 "d,v,t", AT
, AT
, breg
);
5706 if (byte_order
== LITTLE_ENDIAN
)
5707 expr1
.X_add_number
= off
;
5709 expr1
.X_add_number
= 0;
5710 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
5711 (int) BFD_RELOC_LO16
, AT
);
5712 if (byte_order
== LITTLE_ENDIAN
)
5713 expr1
.X_add_number
= 0;
5715 expr1
.X_add_number
= off
;
5716 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
5717 (int) BFD_RELOC_LO16
, AT
);
5721 load_address (&icnt
, AT
, &offset_expr
);
5723 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5724 mips_isa
< 3 ? "addu" : "daddu",
5725 "d,v,t", AT
, AT
, breg
);
5726 if (byte_order
== LITTLE_ENDIAN
)
5727 expr1
.X_add_number
= 0;
5728 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
5729 (int) BFD_RELOC_LO16
, AT
);
5730 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
5732 if (byte_order
== LITTLE_ENDIAN
)
5733 expr1
.X_add_number
= 1;
5735 expr1
.X_add_number
= 0;
5736 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
5737 (int) BFD_RELOC_LO16
, AT
);
5738 if (byte_order
== LITTLE_ENDIAN
)
5739 expr1
.X_add_number
= 0;
5741 expr1
.X_add_number
= 1;
5742 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
5743 (int) BFD_RELOC_LO16
, AT
);
5744 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
5746 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
5751 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
5755 as_warn ("Macro used $at after \".set noat\"");
5758 /* Implement macros in mips16 mode. */
5762 struct mips_cl_insn
*ip
;
5765 int xreg
, yreg
, zreg
, tmp
;
5769 const char *s
, *s2
, *s3
;
5771 mask
= ip
->insn_mo
->mask
;
5773 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
5774 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
5775 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
5779 expr1
.X_op
= O_constant
;
5780 expr1
.X_op_symbol
= NULL
;
5781 expr1
.X_add_symbol
= NULL
;
5782 expr1
.X_add_number
= 1;
5801 mips_emit_delays (true);
5803 mips_any_noreorder
= 1;
5804 macro_build ((char *) NULL
, &icnt
, NULL
,
5805 dbl
? "ddiv" : "div",
5806 "0,x,y", xreg
, yreg
);
5807 expr1
.X_add_number
= 2;
5808 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
5809 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
5810 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
5811 since that causes an overflow. We should do that as well,
5812 but I don't see how to do the comparisons without a temporary
5815 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
5834 mips_emit_delays (true);
5836 mips_any_noreorder
= 1;
5837 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
5838 expr1
.X_add_number
= 2;
5839 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
5840 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
5842 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
5850 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5851 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5852 dbl
? "daddiu" : "addiu",
5853 "y,x,4", yreg
, xreg
);
5857 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5858 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
5863 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5864 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
5887 goto do_reverse_branch
;
5891 goto do_reverse_branch
;
5903 goto do_reverse_branch
;
5914 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
5916 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
5943 goto do_addone_branch_i
;
5948 goto do_addone_branch_i
;
5963 goto do_addone_branch_i
;
5970 ++imm_expr
.X_add_number
;
5973 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
5974 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
5979 /* This routine assembles an instruction into its binary format. As a
5980 side effect, it sets one of the global variables imm_reloc or
5981 offset_reloc to the type of relocation to do if one of the operands
5982 is an address expression. */
5987 struct mips_cl_insn
*ip
;
5992 struct mips_opcode
*insn
;
5995 unsigned int lastregno
= 0;
6000 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '6' || *s
== '.'; ++s
)
6012 as_fatal ("Unknown opcode: `%s'", str
);
6014 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
6016 insn_error
= "unrecognized opcode";
6024 assert (strcmp (insn
->name
, str
) == 0);
6026 if (insn
->pinfo
== INSN_MACRO
)
6027 insn_isa
= insn
->match
;
6028 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA2
)
6030 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA3
)
6032 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA4
)
6037 if (insn_isa
> mips_isa
6038 || ((insn
->pinfo
& INSN_ISA
) == INSN_4650
6040 || ((insn
->pinfo
& INSN_ISA
) == INSN_4010
6042 || ((insn
->pinfo
& INSN_ISA
) == INSN_4100
6045 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
6046 && strcmp (insn
->name
, insn
[1].name
) == 0)
6051 if (insn_isa
<= mips_isa
)
6052 insn_error
= "opcode not supported on this processor";
6055 static char buf
[100];
6057 sprintf (buf
, "opcode requires -mips%d or greater", insn_isa
);
6064 ip
->insn_opcode
= insn
->match
;
6065 for (args
= insn
->args
;; ++args
)
6071 case '\0': /* end of args */
6084 ip
->insn_opcode
|= lastregno
<< 21;
6089 ip
->insn_opcode
|= lastregno
<< 16;
6093 ip
->insn_opcode
|= lastregno
<< 11;
6099 /* handle optional base register.
6100 Either the base register is omitted or
6101 we must have a left paren. */
6102 /* this is dependent on the next operand specifier
6103 is a 'b' for base register */
6104 assert (args
[1] == 'b');
6108 case ')': /* these must match exactly */
6113 case '<': /* must be at least one digit */
6115 * According to the manual, if the shift amount is greater
6116 * than 31 or less than 0 the the shift amount should be
6117 * mod 32. In reality the mips assembler issues an error.
6118 * We issue a warning and mask out all but the low 5 bits.
6120 my_getExpression (&imm_expr
, s
);
6121 check_absolute_expr (ip
, &imm_expr
);
6122 if ((unsigned long) imm_expr
.X_add_number
> 31)
6124 as_warn ("Improper shift amount (%ld)",
6125 (long) imm_expr
.X_add_number
);
6126 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
6128 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
6129 imm_expr
.X_op
= O_absent
;
6133 case '>': /* shift amount minus 32 */
6134 my_getExpression (&imm_expr
, s
);
6135 check_absolute_expr (ip
, &imm_expr
);
6136 if ((unsigned long) imm_expr
.X_add_number
< 32
6137 || (unsigned long) imm_expr
.X_add_number
> 63)
6139 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
6140 imm_expr
.X_op
= O_absent
;
6144 case 'k': /* cache code */
6145 case 'h': /* prefx code */
6146 my_getExpression (&imm_expr
, s
);
6147 check_absolute_expr (ip
, &imm_expr
);
6148 if ((unsigned long) imm_expr
.X_add_number
> 31)
6150 as_warn ("Invalid value for `%s' (%lu)",
6152 (unsigned long) imm_expr
.X_add_number
);
6153 imm_expr
.X_add_number
&= 0x1f;
6156 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
6158 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
6159 imm_expr
.X_op
= O_absent
;
6163 case 'c': /* break code */
6164 my_getExpression (&imm_expr
, s
);
6165 check_absolute_expr (ip
, &imm_expr
);
6166 if ((unsigned) imm_expr
.X_add_number
> 1023)
6167 as_warn ("Illegal break code (%ld)",
6168 (long) imm_expr
.X_add_number
);
6169 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
6170 imm_expr
.X_op
= O_absent
;
6174 case 'B': /* syscall code */
6175 my_getExpression (&imm_expr
, s
);
6176 check_absolute_expr (ip
, &imm_expr
);
6177 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
6178 as_warn ("Illegal syscall code (%ld)",
6179 (long) imm_expr
.X_add_number
);
6180 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
6181 imm_expr
.X_op
= O_absent
;
6185 case 'C': /* Coprocessor code */
6186 my_getExpression (&imm_expr
, s
);
6187 check_absolute_expr (ip
, &imm_expr
);
6188 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
6190 as_warn ("Coproccesor code > 25 bits (%ld)",
6191 (long) imm_expr
.X_add_number
);
6192 imm_expr
.X_add_number
&= ((1<<25) - 1);
6194 ip
->insn_opcode
|= imm_expr
.X_add_number
;
6195 imm_expr
.X_op
= O_absent
;
6199 case 'b': /* base register */
6200 case 'd': /* destination register */
6201 case 's': /* source register */
6202 case 't': /* target register */
6203 case 'r': /* both target and source */
6204 case 'v': /* both dest and source */
6205 case 'w': /* both dest and target */
6206 case 'E': /* coprocessor target register */
6207 case 'G': /* coprocessor destination register */
6208 case 'x': /* ignore register name */
6209 case 'z': /* must be zero register */
6223 while (isdigit (*s
));
6225 as_bad ("Invalid register number (%d)", regno
);
6227 else if (*args
== 'E' || *args
== 'G')
6231 if (s
[1] == 'f' && s
[2] == 'p')
6236 else if (s
[1] == 's' && s
[2] == 'p')
6241 else if (s
[1] == 'g' && s
[2] == 'p')
6246 else if (s
[1] == 'a' && s
[2] == 't')
6251 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
6256 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
6268 as_warn ("Used $at without \".set noat\"");
6274 if (c
== 'r' || c
== 'v' || c
== 'w')
6281 /* 'z' only matches $0. */
6282 if (c
== 'z' && regno
!= 0)
6290 ip
->insn_opcode
|= regno
<< 21;
6294 ip
->insn_opcode
|= regno
<< 11;
6299 ip
->insn_opcode
|= regno
<< 16;
6302 /* This case exists because on the r3000 trunc
6303 expands into a macro which requires a gp
6304 register. On the r6000 or r4000 it is
6305 assembled into a single instruction which
6306 ignores the register. Thus the insn version
6307 is MIPS_ISA2 and uses 'x', and the macro
6308 version is MIPS_ISA1 and uses 't'. */
6311 /* This case is for the div instruction, which
6312 acts differently if the destination argument
6313 is $0. This only matches $0, and is checked
6314 outside the switch. */
6325 ip
->insn_opcode
|= lastregno
<< 21;
6328 ip
->insn_opcode
|= lastregno
<< 16;
6333 case 'D': /* floating point destination register */
6334 case 'S': /* floating point source register */
6335 case 'T': /* floating point target register */
6336 case 'R': /* floating point source register */
6340 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
6350 while (isdigit (*s
));
6353 as_bad ("Invalid float register number (%d)", regno
);
6355 if ((regno
& 1) != 0
6357 && ! (strcmp (str
, "mtc1") == 0
6358 || strcmp (str
, "mfc1") == 0
6359 || strcmp (str
, "lwc1") == 0
6360 || strcmp (str
, "swc1") == 0
6361 || strcmp (str
, "l.s") == 0
6362 || strcmp (str
, "s.s") == 0))
6363 as_warn ("Float register should be even, was %d",
6371 if (c
== 'V' || c
== 'W')
6381 ip
->insn_opcode
|= regno
<< 6;
6385 ip
->insn_opcode
|= regno
<< 11;
6389 ip
->insn_opcode
|= regno
<< 16;
6392 ip
->insn_opcode
|= regno
<< 21;
6401 ip
->insn_opcode
|= lastregno
<< 11;
6404 ip
->insn_opcode
|= lastregno
<< 16;
6410 my_getExpression (&imm_expr
, s
);
6411 if (imm_expr
.X_op
!= O_big
6412 && imm_expr
.X_op
!= O_constant
)
6413 insn_error
= "absolute expression required";
6418 my_getExpression (&offset_expr
, s
);
6419 imm_reloc
= BFD_RELOC_32
;
6431 unsigned char temp
[8];
6433 unsigned int length
;
6438 /* These only appear as the last operand in an
6439 instruction, and every instruction that accepts
6440 them in any variant accepts them in all variants.
6441 This means we don't have to worry about backing out
6442 any changes if the instruction does not match.
6444 The difference between them is the size of the
6445 floating point constant and where it goes. For 'F'
6446 and 'L' the constant is 64 bits; for 'f' and 'l' it
6447 is 32 bits. Where the constant is placed is based
6448 on how the MIPS assembler does things:
6451 f -- immediate value
6454 The .lit4 and .lit8 sections are only used if
6455 permitted by the -G argument.
6457 When generating embedded PIC code, we use the
6458 .lit8 section but not the .lit4 section (we can do
6459 .lit4 inline easily; we need to put .lit8
6460 somewhere in the data segment, and using .lit8
6461 permits the linker to eventually combine identical
6464 f64
= *args
== 'F' || *args
== 'L';
6466 save_in
= input_line_pointer
;
6467 input_line_pointer
= s
;
6468 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
6470 s
= input_line_pointer
;
6471 input_line_pointer
= save_in
;
6472 if (err
!= NULL
&& *err
!= '\0')
6474 as_bad ("Bad floating point constant: %s", err
);
6475 memset (temp
, '\0', sizeof temp
);
6476 length
= f64
? 8 : 4;
6479 assert (length
== (f64
? 8 : 4));
6483 && (! USE_GLOBAL_POINTER_OPT
6484 || mips_pic
== EMBEDDED_PIC
6485 || g_switch_value
< 4)
6488 imm_expr
.X_op
= O_constant
;
6489 if (byte_order
== LITTLE_ENDIAN
)
6490 imm_expr
.X_add_number
=
6491 (((((((int) temp
[3] << 8)
6496 imm_expr
.X_add_number
=
6497 (((((((int) temp
[0] << 8)
6504 const char *newname
;
6507 /* Switch to the right section. */
6509 subseg
= now_subseg
;
6512 default: /* unused default case avoids warnings. */
6514 newname
= RDATA_SECTION_NAME
;
6515 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
6519 newname
= RDATA_SECTION_NAME
;
6522 assert (!USE_GLOBAL_POINTER_OPT
6523 || g_switch_value
>= 4);
6527 new_seg
= subseg_new (newname
, (subsegT
) 0);
6528 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6529 bfd_set_section_flags (stdoutput
, new_seg
,
6534 frag_align (*args
== 'l' ? 2 : 3, 0);
6535 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6536 record_alignment (new_seg
, 4);
6538 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
6540 as_bad ("Can't use floating point insn in this section");
6542 /* Set the argument to the current address in the
6544 offset_expr
.X_op
= O_symbol
;
6545 offset_expr
.X_add_symbol
=
6546 symbol_new ("L0\001", now_seg
,
6547 (valueT
) frag_now_fix (), frag_now
);
6548 offset_expr
.X_add_number
= 0;
6550 /* Put the floating point number into the section. */
6551 p
= frag_more ((int) length
);
6552 memcpy (p
, temp
, length
);
6554 /* Switch back to the original section. */
6555 subseg_set (seg
, subseg
);
6560 case 'i': /* 16 bit unsigned immediate */
6561 case 'j': /* 16 bit signed immediate */
6562 imm_reloc
= BFD_RELOC_LO16
;
6563 c
= my_getSmallExpression (&imm_expr
, s
);
6568 if (imm_expr
.X_op
== O_constant
)
6569 imm_expr
.X_add_number
=
6570 (imm_expr
.X_add_number
>> 16) & 0xffff;
6573 imm_reloc
= BFD_RELOC_HI16_S
;
6574 imm_unmatched_hi
= true;
6577 imm_reloc
= BFD_RELOC_HI16
;
6582 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
6583 || ((imm_expr
.X_add_number
< 0
6584 || imm_expr
.X_add_number
>= 0x10000)
6585 && imm_expr
.X_op
== O_constant
))
6587 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
6588 !strcmp (insn
->name
, insn
[1].name
))
6590 if (imm_expr
.X_op
!= O_constant
6591 && imm_expr
.X_op
!= O_big
)
6592 insn_error
= "absolute expression required";
6594 as_bad ("16 bit expression not in range 0..65535");
6602 /* The upper bound should be 0x8000, but
6603 unfortunately the MIPS assembler accepts numbers
6604 from 0x8000 to 0xffff and sign extends them, and
6605 we want to be compatible. We only permit this
6606 extended range for an instruction which does not
6607 provide any further alternates, since those
6608 alternates may handle other cases. People should
6609 use the numbers they mean, rather than relying on
6610 a mysterious sign extension. */
6611 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
6612 strcmp (insn
->name
, insn
[1].name
) == 0);
6617 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
6618 || ((imm_expr
.X_add_number
< -0x8000
6619 || imm_expr
.X_add_number
>= max
)
6620 && imm_expr
.X_op
== O_constant
)
6622 && imm_expr
.X_add_number
< 0
6624 && imm_expr
.X_unsigned
6625 && sizeof (imm_expr
.X_add_number
) <= 4))
6629 if (imm_expr
.X_op
!= O_constant
6630 && imm_expr
.X_op
!= O_big
)
6631 insn_error
= "absolute expression required";
6633 as_bad ("16 bit expression not in range -32768..32767");
6639 case 'o': /* 16 bit offset */
6640 c
= my_getSmallExpression (&offset_expr
, s
);
6642 /* If this value won't fit into a 16 bit offset, then go
6643 find a macro that will generate the 32 bit offset
6644 code pattern. As a special hack, we accept the
6645 difference of two local symbols as a constant. This
6646 is required to suppose embedded PIC switches, which
6647 use an instruction which looks like
6648 lw $4,$L12-$LS12($4)
6649 The problem with handling this in a more general
6650 fashion is that the macro function doesn't expect to
6651 see anything which can be handled in a single
6652 constant instruction. */
6654 && (offset_expr
.X_op
!= O_constant
6655 || offset_expr
.X_add_number
>= 0x8000
6656 || offset_expr
.X_add_number
< -0x8000)
6657 && (mips_pic
!= EMBEDDED_PIC
6658 || offset_expr
.X_op
!= O_subtract
6659 || now_seg
!= text_section
6660 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
6664 offset_reloc
= BFD_RELOC_LO16
;
6665 if (c
== 'h' || c
== 'H')
6667 assert (offset_expr
.X_op
== O_constant
);
6668 offset_expr
.X_add_number
=
6669 (offset_expr
.X_add_number
>> 16) & 0xffff;
6674 case 'p': /* pc relative offset */
6675 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
6676 my_getExpression (&offset_expr
, s
);
6680 case 'u': /* upper 16 bits */
6681 c
= my_getSmallExpression (&imm_expr
, s
);
6682 if (imm_expr
.X_op
== O_constant
6683 && (imm_expr
.X_add_number
< 0
6684 || imm_expr
.X_add_number
>= 0x10000))
6685 as_bad ("lui expression not in range 0..65535");
6686 imm_reloc
= BFD_RELOC_LO16
;
6691 if (imm_expr
.X_op
== O_constant
)
6692 imm_expr
.X_add_number
=
6693 (imm_expr
.X_add_number
>> 16) & 0xffff;
6696 imm_reloc
= BFD_RELOC_HI16_S
;
6697 imm_unmatched_hi
= true;
6700 imm_reloc
= BFD_RELOC_HI16
;
6706 case 'a': /* 26 bit address */
6707 my_getExpression (&offset_expr
, s
);
6709 offset_reloc
= BFD_RELOC_MIPS_JMP
;
6712 case 'N': /* 3 bit branch condition code */
6713 case 'M': /* 3 bit compare condition code */
6714 if (strncmp (s
, "$fcc", 4) != 0)
6724 while (isdigit (*s
));
6726 as_bad ("invalid condition code register $fcc%d", regno
);
6728 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
6730 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
6734 fprintf (stderr
, "bad char = '%c'\n", *args
);
6739 /* Args don't match. */
6740 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
6741 !strcmp (insn
->name
, insn
[1].name
))
6747 insn_error
= "illegal operands";
6752 /* This routine assembles an instruction into its binary format when
6753 assembling for the mips16. As a side effect, it sets one of the
6754 global variables imm_reloc or offset_reloc to the type of
6755 relocation to do if one of the operands is an address expression.
6756 It also sets mips16_small and mips16_ext if the user explicitly
6757 requested a small or extended instruction. */
6762 struct mips_cl_insn
*ip
;
6766 struct mips_opcode
*insn
;
6769 unsigned int lastregno
= 0;
6774 mips16_small
= false;
6777 for (s
= str
; islower (*s
); ++s
)
6789 if (s
[1] == 't' && s
[2] == ' ')
6792 mips16_small
= true;
6796 else if (s
[1] == 'e' && s
[2] == ' ')
6805 insn_error
= "unknown opcode";
6809 if (! mips16_autoextend
&& ! mips16_ext
)
6810 mips16_small
= true;
6812 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
6814 insn_error
= "unrecognized opcode";
6821 assert (strcmp (insn
->name
, str
) == 0);
6824 ip
->insn_opcode
= insn
->match
;
6825 ip
->use_extend
= false;
6826 imm_expr
.X_op
= O_absent
;
6827 imm_reloc
= BFD_RELOC_UNUSED
;
6828 offset_expr
.X_op
= O_absent
;
6829 offset_reloc
= BFD_RELOC_UNUSED
;
6830 for (args
= insn
->args
; 1; ++args
)
6837 /* In this switch statement we call break if we did not find
6838 a match, continue if we did find a match, or return if we
6847 /* Stuff the immediate value in now, if we can. */
6848 if (imm_expr
.X_op
== O_constant
6849 && imm_reloc
> BFD_RELOC_UNUSED
6850 && insn
->pinfo
!= INSN_MACRO
)
6852 mips16_immed ((char *) NULL
, 0,
6853 imm_reloc
- BFD_RELOC_UNUSED
,
6854 imm_expr
.X_add_number
, true, mips16_small
,
6855 mips16_ext
, &ip
->insn_opcode
,
6856 &ip
->use_extend
, &ip
->extend
);
6857 imm_expr
.X_op
= O_absent
;
6858 imm_reloc
= BFD_RELOC_UNUSED
;
6872 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
6875 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
6891 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
6893 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
6920 while (isdigit (*s
));
6923 as_bad ("invalid register number (%d)", regno
);
6929 if (s
[1] == 'f' && s
[2] == 'p')
6934 else if (s
[1] == 's' && s
[2] == 'p')
6939 else if (s
[1] == 'g' && s
[2] == 'p')
6944 else if (s
[1] == 'a' && s
[2] == 't')
6949 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
6954 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
6967 if (c
== 'v' || c
== 'w')
6969 regno
= mips16_to_32_reg_map
[lastregno
];
6983 regno
= mips32_to_16_reg_map
[regno
];
6988 regno
= ILLEGAL_REG
;
6993 regno
= ILLEGAL_REG
;
6998 regno
= ILLEGAL_REG
;
7003 if (regno
== AT
&& ! mips_noat
)
7004 as_warn ("used $at without \".set noat\"");
7011 if (regno
== ILLEGAL_REG
)
7018 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
7022 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
7025 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
7028 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
7034 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
7037 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
7038 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
7048 if (strncmp (s
, "$pc", 3) == 0)
7071 if (s
[0] == '$' && isdigit (s
[1]))
7073 /* Looks like a register name. */
7081 /* It looks like the expression was omitted before a
7082 register indirection, which means that the
7083 expression is implicitly zero. */
7087 my_getExpression (&imm_expr
, s
);
7088 /* We need to relax this instruction. */
7089 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7098 /* We use offset_reloc rather than imm_reloc for the PC
7099 relative operands. This lets macros with both
7100 immediate and address operands work correctly. */
7101 if (s
[0] == '$' && isdigit (s
[1]))
7103 /* Looks like a register name. */
7106 my_getExpression (&offset_expr
, s
);
7107 /* We need to relax this instruction. */
7108 offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7112 case '6': /* break code */
7113 my_getExpression (&imm_expr
, s
);
7114 check_absolute_expr (ip
, &imm_expr
);
7115 if ((unsigned long) imm_expr
.X_add_number
> 63)
7117 as_warn ("Invalid value for `%s' (%lu)",
7119 (unsigned long) imm_expr
.X_add_number
);
7120 imm_expr
.X_add_number
&= 0x3f;
7122 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
7123 imm_expr
.X_op
= O_absent
;
7127 case 'a': /* 26 bit address */
7128 my_getExpression (&offset_expr
, s
);
7130 offset_reloc
= BFD_RELOC_MIPS16_JMP
;
7131 ip
->insn_opcode
<<= 16;
7134 case 'l': /* register list for entry macro */
7135 case 'L': /* register list for exit macro */
7147 while (*s
== ' ' || *s
== ',')
7151 as_bad ("can't parse register list");
7156 while (isdigit (*s
))
7173 while (isdigit (*s
))
7180 if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
7181 mask
|= (reg2
- 3) << 3;
7182 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
7183 mask
|= (reg2
- 15) << 1;
7184 else if (reg1
== 31 && reg2
== 31)
7187 as_bad ("invalid register list");
7189 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
7199 /* Args don't match. */
7200 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
7201 strcmp (insn
->name
, insn
[1].name
) == 0)
7208 insn_error
= "illegal operands";
7214 /* This structure holds information we know about a mips16 immediate
7217 struct mips16_immed_operand
7219 /* The type code used in the argument string in the opcode table. */
7221 /* The number of bits in the short form of the opcode. */
7223 /* The number of bits in the extended form of the opcode. */
7225 /* The amount by which the short form is shifted when it is used;
7226 for example, the sw instruction has a shift count of 2. */
7228 /* The amount by which the short form is shifted when it is stored
7229 into the instruction code. */
7231 /* Non-zero if the short form is unsigned. */
7233 /* Non-zero if the extended form is unsigned. */
7235 /* Non-zero if the value is PC relative. */
7239 /* The mips16 immediate operand types. */
7241 static const struct mips16_immed_operand mips16_immed_operands
[] =
7243 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
7244 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
7245 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
7246 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
7247 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
7248 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7249 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7250 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7251 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7252 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
7253 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7254 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7255 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7256 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
7257 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
7258 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
7259 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
7260 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
7261 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
7262 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
7263 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
7266 #define MIPS16_NUM_IMMED \
7267 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
7269 /* Handle a mips16 instruction with an immediate value. This or's the
7270 small immediate value into *INSN. It sets *USE_EXTEND to indicate
7271 whether an extended value is needed; if one is needed, it sets
7272 *EXTEND to the value. The argument type is TYPE. The value is VAL.
7273 If SMALL is true, an unextended opcode was explicitly requested.
7274 If EXT is true, an extended opcode was explicitly requested. If
7275 WARN is true, warn if EXT does not match reality. */
7278 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
7287 unsigned long *insn
;
7288 boolean
*use_extend
;
7289 unsigned short *extend
;
7291 register const struct mips16_immed_operand
*op
;
7292 int mintiny
, maxtiny
;
7295 op
= mips16_immed_operands
;
7296 while (op
->type
!= type
)
7299 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
7304 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
7307 maxtiny
= 1 << op
->nbits
;
7312 maxtiny
= (1 << op
->nbits
) - 1;
7317 mintiny
= - (1 << (op
->nbits
- 1));
7318 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
7321 /* Branch offsets have an implicit 0 in the lowest bit. */
7322 if (type
== 'p' || type
== 'q')
7325 if ((val
& ((1 << op
->shift
) - 1)) != 0
7326 || val
< (mintiny
<< op
->shift
)
7327 || val
> (maxtiny
<< op
->shift
))
7332 if (warn
&& ext
&& ! needext
)
7333 as_warn_where (file
, line
, "extended operand requested but not required");
7334 if (small
&& needext
)
7335 as_bad_where (file
, line
, "invalid unextended operand value");
7337 if (small
|| (! ext
&& ! needext
))
7341 *use_extend
= false;
7342 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
7343 insnval
<<= op
->op_shift
;
7348 long minext
, maxext
;
7354 maxext
= (1 << op
->extbits
) - 1;
7358 minext
= - (1 << (op
->extbits
- 1));
7359 maxext
= (1 << (op
->extbits
- 1)) - 1;
7361 if (val
< minext
|| val
> maxext
)
7362 as_bad_where (file
, line
,
7363 "operand value out of range for instruction");
7366 if (op
->extbits
== 16)
7368 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
7371 else if (op
->extbits
== 15)
7373 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
7378 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
7382 *extend
= (unsigned short) extval
;
7391 my_getSmallExpression (ep
, str
)
7402 ((str
[1] == 'h' && str
[2] == 'i')
7403 || (str
[1] == 'H' && str
[2] == 'I')
7404 || (str
[1] == 'l' && str
[2] == 'o'))
7416 * A small expression may be followed by a base register.
7417 * Scan to the end of this operand, and then back over a possible
7418 * base register. Then scan the small expression up to that
7419 * point. (Based on code in sparc.c...)
7421 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
7423 if (sp
- 4 >= str
&& sp
[-1] == RP
)
7425 if (isdigit (sp
[-2]))
7427 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
7429 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
7435 else if (sp
- 5 >= str
7438 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
7439 || (sp
[-3] == 's' && sp
[-2] == 'p')
7440 || (sp
[-3] == 'g' && sp
[-2] == 'p')
7441 || (sp
[-3] == 'a' && sp
[-2] == 't')))
7447 /* no expression means zero offset */
7450 /* %xx(reg) is an error */
7451 ep
->X_op
= O_absent
;
7456 ep
->X_op
= O_constant
;
7459 ep
->X_add_symbol
= NULL
;
7460 ep
->X_op_symbol
= NULL
;
7461 ep
->X_add_number
= 0;
7466 my_getExpression (ep
, str
);
7473 my_getExpression (ep
, str
);
7474 return c
; /* => %hi or %lo encountered */
7478 my_getExpression (ep
, str
)
7484 save_in
= input_line_pointer
;
7485 input_line_pointer
= str
;
7487 expr_end
= input_line_pointer
;
7488 input_line_pointer
= save_in
;
7491 /* Turn a string in input_line_pointer into a floating point constant
7492 of type type, and store the appropriate bytes in *litP. The number
7493 of LITTLENUMS emitted is stored in *sizeP . An error message is
7494 returned, or NULL on OK. */
7497 md_atof (type
, litP
, sizeP
)
7503 LITTLENUM_TYPE words
[4];
7519 return "bad call to md_atof";
7522 t
= atof_ieee (input_line_pointer
, type
, words
);
7524 input_line_pointer
= t
;
7528 if (byte_order
== LITTLE_ENDIAN
)
7530 for (i
= prec
- 1; i
>= 0; i
--)
7532 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
7538 for (i
= 0; i
< prec
; i
++)
7540 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
7549 md_number_to_chars (buf
, val
, n
)
7557 number_to_chars_littleendian (buf
, val
, n
);
7561 number_to_chars_bigendian (buf
, val
, n
);
7569 CONST
char *md_shortopts
= "O::g::G:";
7571 struct option md_longopts
[] = {
7572 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
7573 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
7574 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
7575 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
7576 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
7577 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
7578 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
7579 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
7580 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
7581 #define OPTION_MCPU (OPTION_MD_BASE + 5)
7582 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
7583 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
7584 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
7585 #define OPTION_TRAP (OPTION_MD_BASE + 9)
7586 {"trap", no_argument
, NULL
, OPTION_TRAP
},
7587 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
7588 #define OPTION_BREAK (OPTION_MD_BASE + 10)
7589 {"break", no_argument
, NULL
, OPTION_BREAK
},
7590 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
7591 #define OPTION_EB (OPTION_MD_BASE + 11)
7592 {"EB", no_argument
, NULL
, OPTION_EB
},
7593 #define OPTION_EL (OPTION_MD_BASE + 12)
7594 {"EL", no_argument
, NULL
, OPTION_EL
},
7595 #define OPTION_M4650 (OPTION_MD_BASE + 13)
7596 {"m4650", no_argument
, NULL
, OPTION_M4650
},
7597 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
7598 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
7599 #define OPTION_M4010 (OPTION_MD_BASE + 15)
7600 {"m4010", no_argument
, NULL
, OPTION_M4010
},
7601 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
7602 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
7603 #define OPTION_M4100 (OPTION_MD_BASE + 17)
7604 {"m4100", no_argument
, NULL
, OPTION_M4100
},
7605 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
7606 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
7607 #define OPTION_MIPS16 (OPTION_MD_BASE + 22)
7608 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
7609 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23)
7610 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
7612 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
7613 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
7614 #define OPTION_XGOT (OPTION_MD_BASE + 19)
7615 #define OPTION_32 (OPTION_MD_BASE + 20)
7616 #define OPTION_64 (OPTION_MD_BASE + 21)
7618 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
7619 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
7620 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
7621 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
7622 {"32", no_argument
, NULL
, OPTION_32
},
7623 {"64", no_argument
, NULL
, OPTION_64
},
7626 {NULL
, no_argument
, NULL
, 0}
7628 size_t md_longopts_size
= sizeof(md_longopts
);
7631 md_parse_option (c
, arg
)
7646 target_big_endian
= 1;
7650 target_big_endian
= 0;
7654 if (arg
&& arg
[1] == '0')
7664 mips_debug
= atoi (arg
);
7665 /* When the MIPS assembler sees -g or -g2, it does not do
7666 optimizations which limit full symbolic debugging. We take
7667 that to be equivalent to -O0. */
7668 if (mips_debug
== 2)
7700 /* Identify the processor type */
7702 if (strcmp (p
, "default") == 0
7703 || strcmp (p
, "DEFAULT") == 0)
7709 /* We need to cope with the various "vr" prefixes for the 4300
7711 if (*p
== 'v' || *p
== 'V')
7717 if (*p
== 'r' || *p
== 'R')
7724 if (strcmp (p
, "10000") == 0
7725 || strcmp (p
, "10k") == 0
7726 || strcmp (p
, "10K") == 0)
7731 if (strcmp (p
, "2000") == 0
7732 || strcmp (p
, "2k") == 0
7733 || strcmp (p
, "2K") == 0)
7738 if (strcmp (p
, "3000") == 0
7739 || strcmp (p
, "3k") == 0
7740 || strcmp (p
, "3K") == 0)
7745 if (strcmp (p
, "4000") == 0
7746 || strcmp (p
, "4k") == 0
7747 || strcmp (p
, "4K") == 0)
7749 else if (strcmp (p
, "4100") == 0)
7755 else if (strcmp (p
, "4300") == 0)
7757 else if (strcmp (p
, "4400") == 0)
7759 else if (strcmp (p
, "4600") == 0)
7761 else if (strcmp (p
, "4650") == 0)
7767 else if (strcmp (p
, "4010") == 0)
7776 if (strcmp (p
, "5000") == 0
7777 || strcmp (p
, "5k") == 0
7778 || strcmp (p
, "5K") == 0)
7783 if (strcmp (p
, "6000") == 0
7784 || strcmp (p
, "6k") == 0
7785 || strcmp (p
, "6K") == 0)
7790 if (strcmp (p
, "8000") == 0
7791 || strcmp (p
, "8k") == 0
7792 || strcmp (p
, "8K") == 0)
7797 if (strcmp (p
, "orion") == 0)
7802 if (sv
&& mips_cpu
!= 4300 && mips_cpu
!= 4100 && mips_cpu
!= 5000)
7804 as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg
);
7810 as_bad ("invalid architecture -mcpu=%s", arg
);
7821 case OPTION_NO_M4650
:
7829 case OPTION_NO_M4010
:
7837 case OPTION_NO_M4100
:
7843 mips_no_prev_insn ();
7846 case OPTION_NO_MIPS16
:
7848 mips_no_prev_insn ();
7851 case OPTION_MEMBEDDED_PIC
:
7852 mips_pic
= EMBEDDED_PIC
;
7853 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
7855 as_bad ("-G may not be used with embedded PIC code");
7858 g_switch_value
= 0x7fffffff;
7861 /* When generating ELF code, we permit -KPIC and -call_shared to
7862 select SVR4_PIC, and -non_shared to select no PIC. This is
7863 intended to be compatible with Irix 5. */
7864 case OPTION_CALL_SHARED
:
7865 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
7867 as_bad ("-call_shared is supported only for ELF format");
7870 mips_pic
= SVR4_PIC
;
7871 if (g_switch_seen
&& g_switch_value
!= 0)
7873 as_bad ("-G may not be used with SVR4 PIC code");
7879 case OPTION_NON_SHARED
:
7880 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
7882 as_bad ("-non_shared is supported only for ELF format");
7888 /* The -xgot option tells the assembler to use 32 offsets when
7889 accessing the got in SVR4_PIC mode. It is for Irix
7896 if (! USE_GLOBAL_POINTER_OPT
)
7898 as_bad ("-G is not supported for this configuration");
7901 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
7903 as_bad ("-G may not be used with SVR4 or embedded PIC code");
7907 g_switch_value
= atoi (arg
);
7911 /* The -32 and -64 options tell the assembler to output the 32
7912 bit or the 64 bit MIPS ELF format. */
7919 const char **list
, **l
;
7921 list
= bfd_target_list ();
7922 for (l
= list
; *l
!= NULL
; l
++)
7923 if (strcmp (*l
, "elf64-bigmips") == 0
7924 || strcmp (*l
, "elf64-littlemips") == 0)
7927 as_fatal ("No compiled in support for 64 bit object file format");
7941 md_show_usage (stream
)
7946 -membedded-pic generate embedded position independent code\n\
7947 -EB generate big endian output\n\
7948 -EL generate little endian output\n\
7949 -g, -g2 do not remove uneeded NOPs or swap branches\n\
7950 -G NUM allow referencing objects up to NUM bytes\n\
7951 implicitly with the gp register [default 8]\n");
7953 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
7954 -mips2, -mcpu=r6000 generate code for r6000\n\
7955 -mips3, -mcpu=r4000 generate code for r4000\n\
7956 -mips4, -mcpu=r8000 generate code for r8000\n\
7957 -mcpu=vr4300 generate code for vr4300\n\
7958 -mcpu=vr4100 generate code for vr4100\n\
7959 -m4650 permit R4650 instructions\n\
7960 -no-m4650 do not permit R4650 instructions\n\
7961 -m4010 permit R4010 instructions\n\
7962 -no-m4010 do not permit R4010 instructions\n\
7963 -m4100 permit VR4100 instructions\n\
7964 -no-m4100 do not permit VR4100 instructions\n");
7966 -mips16 generate mips16 instructions\n\
7967 -no-mips16 do not generate mips16 instructions\n");
7969 -O0 remove unneeded NOPs, do not swap branches\n\
7970 -O remove unneeded NOPs and swap branches\n\
7971 --trap, --no-break trap exception on div by 0 and mult overflow\n\
7972 --break, --no-trap break exception on div by 0 and mult overflow\n");
7975 -KPIC, -call_shared generate SVR4 position independent code\n\
7976 -non_shared do not generate position independent code\n\
7977 -xgot assume a 32 bit GOT\n\
7978 -32 create 32 bit object file (default)\n\
7979 -64 create 64 bit object file\n");
7984 mips_init_after_args ()
7986 if (target_big_endian
)
7987 byte_order
= BIG_ENDIAN
;
7989 byte_order
= LITTLE_ENDIAN
;
7993 md_pcrel_from (fixP
)
7996 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
7997 && fixP
->fx_addsy
!= (symbolS
*) NULL
7998 && ! S_IS_DEFINED (fixP
->fx_addsy
))
8000 /* This makes a branch to an undefined symbol be a branch to the
8001 current location. */
8005 /* return the address of the delay slot */
8006 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8009 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
8010 reloc for a cons. We could use the definition there, except that
8011 we want to handle 64 bit relocs specially. */
8014 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
8017 unsigned int nbytes
;
8021 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
8023 if (nbytes
== 8 && ! mips_64
)
8025 if (byte_order
== BIG_ENDIAN
)
8031 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
8032 as_bad ("Unsupported reloc size %d", nbytes
);
8034 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
8037 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
8040 /* Sort any unmatched HI16_S relocs so that they immediately precede
8041 the corresponding LO reloc. This is called before md_apply_fix and
8042 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
8043 explicit use of the %hi modifier. */
8048 struct mips_hi_fixup
*l
;
8050 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
8052 segment_info_type
*seginfo
;
8055 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
8057 /* Check quickly whether the next fixup happens to be a matching
8059 if (l
->fixp
->fx_next
!= NULL
8060 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
8061 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
8062 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
8065 /* Look through the fixups for this segment for a matching %lo.
8066 When we find one, move the %hi just in front of it. We do
8067 this in two passes. In the first pass, we try to find a
8068 unique %lo. In the second pass, we permit multiple %hi
8069 relocs for a single %lo (this is a GNU extension). */
8070 seginfo
= seg_info (l
->seg
);
8071 for (pass
= 0; pass
< 2; pass
++)
8076 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
8078 /* Check whether this is a %lo fixup which matches l->fixp. */
8079 if (f
->fx_r_type
== BFD_RELOC_LO16
8080 && f
->fx_addsy
== l
->fixp
->fx_addsy
8081 && f
->fx_offset
== l
->fixp
->fx_offset
8084 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
8085 || prev
->fx_addsy
!= f
->fx_addsy
8086 || prev
->fx_offset
!= f
->fx_offset
))
8090 /* Move l->fixp before f. */
8091 for (pf
= &seginfo
->fix_root
;
8093 pf
= &(*pf
)->fx_next
)
8094 assert (*pf
!= NULL
);
8096 *pf
= l
->fixp
->fx_next
;
8098 l
->fixp
->fx_next
= f
;
8100 seginfo
->fix_root
= l
->fixp
;
8102 prev
->fx_next
= l
->fixp
;
8114 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
8115 "Unmatched %%hi reloc");
8120 /* When generating embedded PIC code we need to use a special
8121 relocation to represent the difference of two symbols in the .text
8122 section (switch tables use a difference of this sort). See
8123 include/coff/mips.h for details. This macro checks whether this
8124 fixup requires the special reloc. */
8125 #define SWITCH_TABLE(fixp) \
8126 ((fixp)->fx_r_type == BFD_RELOC_32 \
8127 && (fixp)->fx_addsy != NULL \
8128 && (fixp)->fx_subsy != NULL \
8129 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
8130 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
8132 /* When generating embedded PIC code we must keep all PC relative
8133 relocations, in case the linker has to relax a call. We also need
8134 to keep relocations for switch table entries. */
8138 mips_force_relocation (fixp
)
8141 return (mips_pic
== EMBEDDED_PIC
8143 || SWITCH_TABLE (fixp
)
8144 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
8145 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
8148 /* Apply a fixup to the object file. */
8151 md_apply_fix (fixP
, valueP
)
8158 assert (fixP
->fx_size
== 4
8159 || fixP
->fx_r_type
== BFD_RELOC_16
8160 || fixP
->fx_r_type
== BFD_RELOC_64
);
8163 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
8165 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
8168 switch (fixP
->fx_r_type
)
8170 case BFD_RELOC_MIPS_JMP
:
8171 case BFD_RELOC_HI16
:
8172 case BFD_RELOC_HI16_S
:
8173 case BFD_RELOC_MIPS_GPREL
:
8174 case BFD_RELOC_MIPS_LITERAL
:
8175 case BFD_RELOC_MIPS_CALL16
:
8176 case BFD_RELOC_MIPS_GOT16
:
8177 case BFD_RELOC_MIPS_GPREL32
:
8178 case BFD_RELOC_MIPS_GOT_HI16
:
8179 case BFD_RELOC_MIPS_GOT_LO16
:
8180 case BFD_RELOC_MIPS_CALL_HI16
:
8181 case BFD_RELOC_MIPS_CALL_LO16
:
8183 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8184 "Invalid PC relative reloc");
8185 /* Nothing needed to do. The value comes from the reloc entry */
8188 case BFD_RELOC_MIPS16_JMP
:
8189 /* We currently always generate a reloc against a symbol, which
8190 means that we don't want an addend even if the symbol is
8192 fixP
->fx_addnumber
= 0;
8195 case BFD_RELOC_PCREL_HI16_S
:
8196 /* The addend for this is tricky if it is internal, so we just
8197 do everything here rather than in bfd_perform_relocation. */
8198 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
8200 /* For an external symbol adjust by the address to make it
8201 pcrel_offset. We use the address of the RELLO reloc
8202 which follows this one. */
8203 value
+= (fixP
->fx_next
->fx_frag
->fr_address
8204 + fixP
->fx_next
->fx_where
);
8209 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8210 if (byte_order
== BIG_ENDIAN
)
8212 md_number_to_chars (buf
, value
, 2);
8215 case BFD_RELOC_PCREL_LO16
:
8216 /* The addend for this is tricky if it is internal, so we just
8217 do everything here rather than in bfd_perform_relocation. */
8218 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
8219 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
8220 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8221 if (byte_order
== BIG_ENDIAN
)
8223 md_number_to_chars (buf
, value
, 2);
8227 /* This is handled like BFD_RELOC_32, but we output a sign
8228 extended value if we are only 32 bits. */
8230 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
8232 if (8 <= sizeof (valueT
))
8233 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8240 w1
= w2
= fixP
->fx_where
;
8241 if (byte_order
== BIG_ENDIAN
)
8245 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
8246 if ((value
& 0x80000000) != 0)
8250 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
8256 /* If we are deleting this reloc entry, we must fill in the
8257 value now. This can happen if we have a .word which is not
8258 resolved when it appears but is later defined. We also need
8259 to fill in the value if this is an embedded PIC switch table
8262 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
8263 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8268 /* If we are deleting this reloc entry, we must fill in the
8270 assert (fixP
->fx_size
== 2);
8272 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8276 case BFD_RELOC_LO16
:
8277 /* When handling an embedded PIC switch statement, we can wind
8278 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
8281 if (value
< -0x8000 || value
> 0x7fff)
8282 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8283 "relocation overflow");
8284 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8285 if (byte_order
== BIG_ENDIAN
)
8287 md_number_to_chars (buf
, value
, 2);
8291 case BFD_RELOC_16_PCREL_S2
:
8293 * We need to save the bits in the instruction since fixup_segment()
8294 * might be deleting the relocation entry (i.e., a branch within
8295 * the current segment).
8297 if ((value
& 0x3) != 0)
8298 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
8299 "Branch to odd address (%lx)", value
);
8302 /* update old instruction data */
8303 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
8307 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
8311 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
8319 if (value
>= -0x8000 && value
< 0x8000)
8320 insn
|= value
& 0xffff;
8323 /* The branch offset is too large. If this is an
8324 unconditional branch, and we are not generating PIC code,
8325 we can convert it to an absolute jump instruction. */
8326 if (mips_pic
== NO_PIC
8328 && fixP
->fx_frag
->fr_address
>= text_section
->vma
8329 && (fixP
->fx_frag
->fr_address
8330 < text_section
->vma
+ text_section
->_raw_size
)
8331 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
8332 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
8333 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
8335 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
8336 insn
= 0x0c000000; /* jal */
8338 insn
= 0x08000000; /* j */
8339 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
8341 fixP
->fx_addsy
= section_symbol (text_section
);
8342 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
8346 /* FIXME. It would be possible in principle to handle
8347 conditional branches which overflow. They could be
8348 transformed into a branch around a jump. This would
8349 require setting up variant frags for each different
8350 branch type. The native MIPS assembler attempts to
8351 handle these cases, but it appears to do it
8353 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8354 "Relocation overflow");
8358 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
8373 const struct mips_opcode
*p
;
8374 int treg
, sreg
, dreg
, shamt
;
8379 for (i
= 0; i
< NUMOPCODES
; ++i
)
8381 p
= &mips_opcodes
[i
];
8382 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
8384 printf ("%08lx %s\t", oc
, p
->name
);
8385 treg
= (oc
>> 16) & 0x1f;
8386 sreg
= (oc
>> 21) & 0x1f;
8387 dreg
= (oc
>> 11) & 0x1f;
8388 shamt
= (oc
>> 6) & 0x1f;
8390 for (args
= p
->args
;; ++args
)
8401 printf ("%c", *args
);
8405 assert (treg
== sreg
);
8406 printf ("$%d,$%d", treg
, sreg
);
8411 printf ("$%d", dreg
);
8416 printf ("$%d", treg
);
8420 printf ("0x%x", treg
);
8425 printf ("$%d", sreg
);
8429 printf ("0x%08lx", oc
& 0x1ffffff);
8441 printf ("$%d", shamt
);
8452 printf ("%08lx UNDEFINED\n", oc
);
8463 name
= input_line_pointer
;
8464 c
= get_symbol_end ();
8465 p
= (symbolS
*) symbol_find_or_make (name
);
8466 *input_line_pointer
= c
;
8470 /* Align the current frag to a given power of two. The MIPS assembler
8471 also automatically adjusts any preceding label. */
8474 mips_align (to
, fill
, label
)
8479 mips_emit_delays (false);
8480 frag_align (to
, fill
);
8481 record_alignment (now_seg
, to
);
8484 assert (S_GET_SEGMENT (label
) == now_seg
);
8485 label
->sy_frag
= frag_now
;
8486 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
8490 /* Align to a given power of two. .align 0 turns off the automatic
8491 alignment used by the data creating pseudo-ops. */
8498 register long temp_fill
;
8499 long max_alignment
= 15;
8503 o Note that the assembler pulls down any immediately preceeding label
8504 to the aligned address.
8505 o It's not documented but auto alignment is reinstated by
8506 a .align pseudo instruction.
8507 o Note also that after auto alignment is turned off the mips assembler
8508 issues an error on attempt to assemble an improperly aligned data item.
8513 temp
= get_absolute_expression ();
8514 if (temp
> max_alignment
)
8515 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
8518 as_warn ("Alignment negative: 0 assumed.");
8521 if (*input_line_pointer
== ',')
8523 input_line_pointer
++;
8524 temp_fill
= get_absolute_expression ();
8531 mips_align (temp
, (int) temp_fill
,
8532 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
8539 demand_empty_rest_of_line ();
8543 mips_flush_pending_output ()
8545 mips_emit_delays (false);
8546 mips_clear_insn_labels ();
8555 /* When generating embedded PIC code, we only use the .text, .lit8,
8556 .sdata and .sbss sections. We change the .data and .rdata
8557 pseudo-ops to use .sdata. */
8558 if (mips_pic
== EMBEDDED_PIC
8559 && (sec
== 'd' || sec
== 'r'))
8562 mips_emit_delays (false);
8572 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
8573 demand_empty_rest_of_line ();
8577 if (USE_GLOBAL_POINTER_OPT
)
8579 seg
= subseg_new (RDATA_SECTION_NAME
,
8580 (subsegT
) get_absolute_expression ());
8581 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8583 bfd_set_section_flags (stdoutput
, seg
,
8589 if (strcmp (TARGET_OS
, "elf") != 0)
8590 bfd_set_section_alignment (stdoutput
, seg
, 4);
8592 demand_empty_rest_of_line ();
8596 as_bad ("No read only data section in this object file format");
8597 demand_empty_rest_of_line ();
8603 if (USE_GLOBAL_POINTER_OPT
)
8605 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
8606 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8608 bfd_set_section_flags (stdoutput
, seg
,
8609 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
8611 if (strcmp (TARGET_OS
, "elf") != 0)
8612 bfd_set_section_alignment (stdoutput
, seg
, 4);
8614 demand_empty_rest_of_line ();
8619 as_bad ("Global pointers not supported; recompile -G 0");
8620 demand_empty_rest_of_line ();
8629 mips_enable_auto_align ()
8640 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
8641 mips_emit_delays (false);
8642 if (log_size
> 0 && auto_align
)
8643 mips_align (log_size
, 0, label
);
8644 mips_clear_insn_labels ();
8645 cons (1 << log_size
);
8654 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
8656 mips_emit_delays (false);
8660 mips_align (3, 0, label
);
8662 mips_align (2, 0, label
);
8664 mips_clear_insn_labels ();
8669 /* Handle .globl. We need to override it because on Irix 5 you are
8672 where foo is an undefined symbol, to mean that foo should be
8673 considered to be the address of a function. */
8684 name
= input_line_pointer
;
8685 c
= get_symbol_end ();
8686 symbolP
= symbol_find_or_make (name
);
8687 *input_line_pointer
= c
;
8690 /* On Irix 5, every global symbol that is not explicitly labelled as
8691 being a function is apparently labelled as being an object. */
8694 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
8699 secname
= input_line_pointer
;
8700 c
= get_symbol_end ();
8701 sec
= bfd_get_section_by_name (stdoutput
, secname
);
8703 as_bad ("%s: no such section", secname
);
8704 *input_line_pointer
= c
;
8706 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
8707 flag
= BSF_FUNCTION
;
8710 symbolP
->bsym
->flags
|= flag
;
8712 S_SET_EXTERNAL (symbolP
);
8713 demand_empty_rest_of_line ();
8723 opt
= input_line_pointer
;
8724 c
= get_symbol_end ();
8728 /* FIXME: What does this mean? */
8730 else if (strncmp (opt
, "pic", 3) == 0)
8738 mips_pic
= SVR4_PIC
;
8740 as_bad (".option pic%d not supported", i
);
8742 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
8744 if (g_switch_seen
&& g_switch_value
!= 0)
8745 as_warn ("-G may not be used with SVR4 PIC code");
8747 bfd_set_gp_size (stdoutput
, 0);
8751 as_warn ("Unrecognized option \"%s\"", opt
);
8753 *input_line_pointer
= c
;
8754 demand_empty_rest_of_line ();
8761 char *name
= input_line_pointer
, ch
;
8763 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
8764 input_line_pointer
++;
8765 ch
= *input_line_pointer
;
8766 *input_line_pointer
= '\0';
8768 if (strcmp (name
, "reorder") == 0)
8772 prev_insn_unreordered
= 1;
8773 prev_prev_insn_unreordered
= 1;
8777 else if (strcmp (name
, "noreorder") == 0)
8779 mips_emit_delays (true);
8781 mips_any_noreorder
= 1;
8783 else if (strcmp (name
, "at") == 0)
8787 else if (strcmp (name
, "noat") == 0)
8791 else if (strcmp (name
, "macro") == 0)
8793 mips_warn_about_macros
= 0;
8795 else if (strcmp (name
, "nomacro") == 0)
8797 if (mips_noreorder
== 0)
8798 as_bad ("`noreorder' must be set before `nomacro'");
8799 mips_warn_about_macros
= 1;
8801 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
8805 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
8809 else if (strcmp (name
, "bopt") == 0)
8813 else if (strcmp (name
, "nobopt") == 0)
8817 else if (strcmp (name
, "mips16") == 0
8818 || strcmp (name
, "MIPS-16") == 0)
8820 else if (strcmp (name
, "nomips16") == 0
8821 || strcmp (name
, "noMIPS-16") == 0)
8823 else if (strncmp (name
, "mips", 4) == 0)
8827 /* Permit the user to change the ISA on the fly. Needless to
8828 say, misuse can cause serious problems. */
8829 isa
= atoi (name
+ 4);
8831 mips_isa
= file_mips_isa
;
8832 else if (isa
< 1 || isa
> 4)
8833 as_bad ("unknown ISA level");
8837 else if (strcmp (name
, "autoextend") == 0)
8838 mips16_autoextend
= 1;
8839 else if (strcmp (name
, "noautoextend") == 0)
8840 mips16_autoextend
= 0;
8843 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
8845 *input_line_pointer
= ch
;
8846 demand_empty_rest_of_line ();
8849 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
8850 .option pic2. It means to generate SVR4 PIC calls. */
8856 mips_pic
= SVR4_PIC
;
8857 if (USE_GLOBAL_POINTER_OPT
)
8859 if (g_switch_seen
&& g_switch_value
!= 0)
8860 as_warn ("-G may not be used with SVR4 PIC code");
8863 bfd_set_gp_size (stdoutput
, 0);
8864 demand_empty_rest_of_line ();
8867 /* Handle the .cpload pseudo-op. This is used when generating SVR4
8868 PIC code. It sets the $gp register for the function based on the
8869 function address, which is in the register named in the argument.
8870 This uses a relocation against _gp_disp, which is handled specially
8871 by the linker. The result is:
8872 lui $gp,%hi(_gp_disp)
8873 addiu $gp,$gp,%lo(_gp_disp)
8874 addu $gp,$gp,.cpload argument
8875 The .cpload argument is normally $25 == $t9. */
8884 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
8885 if (mips_pic
!= SVR4_PIC
)
8891 /* .cpload should be a in .set noreorder section. */
8892 if (mips_noreorder
== 0)
8893 as_warn (".cpload not in noreorder section");
8896 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
8897 ex
.X_op_symbol
= NULL
;
8898 ex
.X_add_number
= 0;
8900 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
8901 ex
.X_add_symbol
->bsym
->flags
|= BSF_OBJECT
;
8903 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
8904 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
8905 (int) BFD_RELOC_LO16
);
8907 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
8908 GP
, GP
, tc_get_register (0));
8910 demand_empty_rest_of_line ();
8913 /* Handle the .cprestore pseudo-op. This stores $gp into a given
8914 offset from $sp. The offset is remembered, and after making a PIC
8915 call $gp is restored from that location. */
8918 s_cprestore (ignore
)
8924 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
8925 if (mips_pic
!= SVR4_PIC
)
8931 mips_cprestore_offset
= get_absolute_expression ();
8933 ex
.X_op
= O_constant
;
8934 ex
.X_add_symbol
= NULL
;
8935 ex
.X_op_symbol
= NULL
;
8936 ex
.X_add_number
= mips_cprestore_offset
;
8938 macro_build ((char *) NULL
, &icnt
, &ex
,
8939 mips_isa
< 3 ? "sw" : "sd",
8940 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
8942 demand_empty_rest_of_line ();
8945 /* Handle the .gpword pseudo-op. This is used when generating PIC
8946 code. It generates a 32 bit GP relative reloc. */
8956 /* When not generating PIC code, this is treated as .word. */
8957 if (mips_pic
!= SVR4_PIC
)
8963 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
8964 mips_emit_delays (true);
8966 mips_align (2, 0, label
);
8967 mips_clear_insn_labels ();
8971 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
8973 as_bad ("Unsupported use of .gpword");
8974 ignore_rest_of_line ();
8978 md_number_to_chars (p
, (valueT
) 0, 4);
8979 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
8980 BFD_RELOC_MIPS_GPREL32
);
8982 demand_empty_rest_of_line ();
8985 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
8986 tables in SVR4 PIC code. */
8995 /* This is ignored when not generating SVR4 PIC code. */
8996 if (mips_pic
!= SVR4_PIC
)
9002 /* Add $gp to the register named as an argument. */
9003 reg
= tc_get_register (0);
9004 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
9005 mips_isa
< 3 ? "addu" : "daddu",
9006 "d,v,t", reg
, reg
, GP
);
9008 demand_empty_rest_of_line ();
9011 /* Parse a register string into a number. Called from the ECOFF code
9012 to parse .frame. The argument is non-zero if this is the frame
9013 register, so that we can record it in mips_frame_reg. */
9016 tc_get_register (frame
)
9022 if (*input_line_pointer
++ != '$')
9024 as_warn ("expected `$'");
9027 else if (isdigit ((unsigned char) *input_line_pointer
))
9029 reg
= get_absolute_expression ();
9030 if (reg
< 0 || reg
>= 32)
9032 as_warn ("Bad register number");
9038 if (strncmp (input_line_pointer
, "fp", 2) == 0)
9040 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
9042 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
9044 else if (strncmp (input_line_pointer
, "at", 2) == 0)
9048 as_warn ("Unrecognized register name");
9051 input_line_pointer
+= 2;
9054 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
9059 md_section_align (seg
, addr
)
9063 int align
= bfd_get_section_alignment (stdoutput
, seg
);
9066 /* We don't need to align ELF sections to the full alignment.
9067 However, Irix 5 may prefer that we align them at least to a 16
9068 byte boundary. We don't bother to align the sections if we are
9069 targeted for an embedded system. */
9070 if (strcmp (TARGET_OS
, "elf") == 0)
9076 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
9079 /* Utility routine, called from above as well. If called while the
9080 input file is still being read, it's only an approximation. (For
9081 example, a symbol may later become defined which appeared to be
9082 undefined earlier.) */
9085 nopic_need_relax (sym
)
9091 if (USE_GLOBAL_POINTER_OPT
)
9093 const char *symname
;
9096 /* Find out whether this symbol can be referenced off the GP
9097 register. It can be if it is smaller than the -G size or if
9098 it is in the .sdata or .sbss section. Certain symbols can
9099 not be referenced off the GP, although it appears as though
9101 symname
= S_GET_NAME (sym
);
9102 if (symname
!= (const char *) NULL
9103 && (strcmp (symname
, "eprol") == 0
9104 || strcmp (symname
, "etext") == 0
9105 || strcmp (symname
, "_gp") == 0
9106 || strcmp (symname
, "edata") == 0
9107 || strcmp (symname
, "_fbss") == 0
9108 || strcmp (symname
, "_fdata") == 0
9109 || strcmp (symname
, "_ftext") == 0
9110 || strcmp (symname
, "end") == 0
9111 || strcmp (symname
, "_gp_disp") == 0))
9113 else if (! S_IS_DEFINED (sym
)
9115 #ifndef NO_ECOFF_DEBUGGING
9116 || (sym
->ecoff_extern_size
!= 0
9117 && sym
->ecoff_extern_size
<= g_switch_value
)
9119 || (S_GET_VALUE (sym
) != 0
9120 && S_GET_VALUE (sym
) <= g_switch_value
)))
9124 const char *segname
;
9126 segname
= segment_name (S_GET_SEGMENT (sym
));
9127 assert (strcmp (segname
, ".lit8") != 0
9128 && strcmp (segname
, ".lit4") != 0);
9129 change
= (strcmp (segname
, ".sdata") != 0
9130 && strcmp (segname
, ".sbss") != 0);
9135 /* We are not optimizing for the GP register. */
9139 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
9140 extended opcode. SEC is the section the frag is in. */
9143 mips16_extended_frag (fragp
, sec
, stretch
)
9149 register const struct mips16_immed_operand
*op
;
9151 int mintiny
, maxtiny
;
9154 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
9156 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
9159 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
9160 op
= mips16_immed_operands
;
9161 while (op
->type
!= type
)
9164 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9169 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9172 maxtiny
= 1 << op
->nbits
;
9177 maxtiny
= (1 << op
->nbits
) - 1;
9182 mintiny
= - (1 << (op
->nbits
- 1));
9183 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9186 /* We can't call S_GET_VALUE here, because we don't want to lock in
9187 a particular frag address. */
9188 if (fragp
->fr_symbol
->sy_value
.X_op
== O_constant
)
9190 val
= (fragp
->fr_symbol
->sy_value
.X_add_number
9191 + fragp
->fr_symbol
->sy_frag
->fr_address
);
9192 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
9194 else if (fragp
->fr_symbol
->sy_value
.X_op
== O_symbol
9195 && (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_op
9198 val
= (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_add_number
9199 + fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_frag
->fr_address
9200 + fragp
->fr_symbol
->sy_value
.X_add_number
9201 + fragp
->fr_symbol
->sy_frag
->fr_address
);
9202 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
->sy_value
.X_add_symbol
);
9211 /* We won't have the section when we are called from
9212 mips_relax_frag. However, we will always have been called
9213 from md_estimate_size_before_relax first. If this is a
9214 branch to a different section, we mark it as such. If SEC is
9215 NULL, and the frag is not marked, then it must be a branch to
9216 the same section. */
9219 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
9227 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9229 /* FIXME: We should support this, and let the linker
9230 catch branches and loads that are out of range. */
9231 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
9232 "unsupported PC relative reference to different section");
9238 /* In this case, we know for sure that the symbol fragment is in
9239 the same section. If the fr_address of the symbol fragment
9240 is greater then the address of this fragment we want to add
9241 in STRETCH in order to get a better estimate of the address.
9242 This particularly matters because of the shift bits. */
9244 && fragp
->fr_symbol
->sy_frag
->fr_address
>= fragp
->fr_address
)
9248 /* Adjust stretch for any alignment frag. */
9249 for (f
= fragp
; f
!= fragp
->fr_symbol
->sy_frag
; f
= f
->fr_next
)
9252 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
9255 stretch
= - ((- stretch
)
9256 & ~ ((1 << (int) f
->fr_offset
) - 1));
9258 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
9266 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
9268 /* The base address rules are complicated. The base address of
9269 a branch is the following instruction. The base address of a
9270 PC relative load or add is the instruction itself, but if it
9271 is extended add 2, and if it is in a delay slot (in which
9272 case it can not be extended) use the address of the
9273 instruction whose delay slot it is in. */
9274 if (type
== 'p' || type
== 'q')
9277 /* Ignore the low bit in the target, since it will be set
9278 for a text label. */
9282 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
9284 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
9287 /* If we are currently assuming that this frag should be
9288 extended, then the current address is two bytes higher. */
9289 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9292 val
-= addr
& ~ ((1 << op
->shift
) - 1);
9294 /* Branch offsets have an implicit 0 in the lowest bit. */
9295 if (type
== 'p' || type
== 'q')
9298 /* If any of the shifted bits are set, we must use an extended
9299 opcode. If the address depends on the size of this
9300 instruction, this can lead to a loop, so we arrange to always
9301 use an extended opcode. We only check this when we are in
9302 the main relaxation loop, when SEC is NULL. */
9303 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
9306 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9310 /* If we are about to mark a frag as extended because the value
9311 is precisely maxtiny + 1, then there is a chance of an
9312 infinite loop as in the following code:
9317 In this case when the la is extended, foo is 0x3fc bytes
9318 away, so the la can be shrunk, but then foo is 0x400 away, so
9319 the la must be extended. To avoid this loop, we mark the
9320 frag as extended if it was small, and is about to become
9321 extended with a value of maxtiny + 1. */
9322 if (val
== ((maxtiny
+ 1) << op
->shift
)
9323 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
9327 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9331 else if (symsec
!= absolute_section
&& sec
!= NULL
)
9332 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, "unsupported relocation");
9334 if ((val
& ((1 << op
->shift
) - 1)) != 0
9335 || val
< (mintiny
<< op
->shift
)
9336 || val
> (maxtiny
<< op
->shift
))
9342 /* Estimate the size of a frag before relaxing. Unless this is the
9343 mips16, we are not really relaxing here, and the final size is
9344 encoded in the subtype information. For the mips16, we have to
9345 decide whether we are using an extended opcode or not. */
9349 md_estimate_size_before_relax (fragp
, segtype
)
9355 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
9357 if (mips16_extended_frag (fragp
, segtype
, 0))
9359 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
9364 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
9369 if (mips_pic
== NO_PIC
)
9371 change
= nopic_need_relax (fragp
->fr_symbol
);
9373 else if (mips_pic
== SVR4_PIC
)
9375 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
9377 /* This must duplicate the test in adjust_reloc_syms. */
9378 change
= (symsec
!= &bfd_und_section
9379 && symsec
!= &bfd_abs_section
9380 && ! bfd_is_com_section (symsec
));
9387 /* Record the offset to the first reloc in the fr_opcode field.
9388 This lets md_convert_frag and tc_gen_reloc know that the code
9389 must be expanded. */
9390 fragp
->fr_opcode
= (fragp
->fr_literal
9392 - RELAX_OLD (fragp
->fr_subtype
)
9393 + RELAX_RELOC1 (fragp
->fr_subtype
));
9394 /* FIXME: This really needs as_warn_where. */
9395 if (RELAX_WARN (fragp
->fr_subtype
))
9396 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
9402 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
9405 /* Translate internal representation of relocation info to BFD target
9409 tc_gen_reloc (section
, fixp
)
9413 static arelent
*retval
[4];
9415 bfd_reloc_code_real_type code
;
9417 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
9420 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
9421 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9423 if (mips_pic
== EMBEDDED_PIC
9424 && SWITCH_TABLE (fixp
))
9426 /* For a switch table entry we use a special reloc. The addend
9427 is actually the difference between the reloc address and the
9429 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
9430 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
9431 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
9432 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
9434 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
9436 /* We use a special addend for an internal RELLO reloc. */
9437 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
9438 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
9440 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
9442 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
9444 assert (fixp
->fx_next
!= NULL
9445 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
9446 /* We use a special addend for an internal RELHI reloc. The
9447 reloc is relative to the RELLO; adjust the addend
9449 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
9450 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
9451 + fixp
->fx_next
->fx_where
9452 - S_GET_VALUE (fixp
->fx_subsy
));
9454 reloc
->addend
= (fixp
->fx_addnumber
9455 + fixp
->fx_next
->fx_frag
->fr_address
9456 + fixp
->fx_next
->fx_where
);
9458 else if (fixp
->fx_pcrel
== 0)
9459 reloc
->addend
= fixp
->fx_addnumber
;
9462 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
9463 /* A gruesome hack which is a result of the gruesome gas reloc
9465 reloc
->addend
= reloc
->address
;
9467 reloc
->addend
= -reloc
->address
;
9470 /* If this is a variant frag, we may need to adjust the existing
9471 reloc and generate a new one. */
9472 if (fixp
->fx_frag
->fr_opcode
!= NULL
9473 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
9474 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
9475 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
9476 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
9477 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
9478 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
9479 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
9483 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
9485 /* If this is not the last reloc in this frag, then we have two
9486 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
9487 CALL_HI16/CALL_LO16, both of which are being replaced. Let
9488 the second one handle all of them. */
9489 if (fixp
->fx_next
!= NULL
9490 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
9492 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
9493 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
9494 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
9495 && (fixp
->fx_next
->fx_r_type
9496 == BFD_RELOC_MIPS_GOT_LO16
))
9497 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
9498 && (fixp
->fx_next
->fx_r_type
9499 == BFD_RELOC_MIPS_CALL_LO16
)));
9504 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
9505 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9506 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
9508 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
9509 reloc2
->address
= (reloc
->address
9510 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
9511 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
9512 reloc2
->addend
= fixp
->fx_addnumber
;
9513 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
9514 assert (reloc2
->howto
!= NULL
);
9516 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
9520 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
9523 reloc3
->address
+= 4;
9526 if (mips_pic
== NO_PIC
)
9528 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
9529 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
9531 else if (mips_pic
== SVR4_PIC
)
9533 switch (fixp
->fx_r_type
)
9537 case BFD_RELOC_MIPS_GOT16
:
9539 case BFD_RELOC_MIPS_CALL16
:
9540 case BFD_RELOC_MIPS_GOT_LO16
:
9541 case BFD_RELOC_MIPS_CALL_LO16
:
9542 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
9550 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
9551 fixup_segment converted a non-PC relative reloc into a PC
9552 relative reloc. In such a case, we need to convert the reloc
9554 code
= fixp
->fx_r_type
;
9560 code
= BFD_RELOC_8_PCREL
;
9563 code
= BFD_RELOC_16_PCREL
;
9566 code
= BFD_RELOC_32_PCREL
;
9569 code
= BFD_RELOC_64_PCREL
;
9571 case BFD_RELOC_8_PCREL
:
9572 case BFD_RELOC_16_PCREL
:
9573 case BFD_RELOC_32_PCREL
:
9574 case BFD_RELOC_64_PCREL
:
9575 case BFD_RELOC_16_PCREL_S2
:
9576 case BFD_RELOC_PCREL_HI16_S
:
9577 case BFD_RELOC_PCREL_LO16
:
9580 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9581 "Cannot make %s relocation PC relative",
9582 bfd_get_reloc_code_name (code
));
9586 /* To support a PC relative reloc when generating embedded PIC code
9587 for ECOFF, we use a Cygnus extension. We check for that here to
9588 make sure that we don't let such a reloc escape normally. */
9589 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
9590 && code
== BFD_RELOC_16_PCREL_S2
9591 && mips_pic
!= EMBEDDED_PIC
)
9592 reloc
->howto
= NULL
;
9594 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
9596 if (reloc
->howto
== NULL
)
9598 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9599 "Can not represent %s relocation in this object file format",
9600 bfd_get_reloc_code_name (code
));
9607 /* Relax a machine dependent frag. This returns the amount by which
9608 the current size of the frag should change. */
9611 mips_relax_frag (fragp
, stretch
)
9615 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
9618 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
9620 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9622 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
9627 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9629 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
9636 /* Convert a machine dependent frag. */
9639 md_convert_frag (abfd
, asec
, fragp
)
9647 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
9650 register const struct mips16_immed_operand
*op
;
9656 unsigned short extend
;
9658 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
9659 op
= mips16_immed_operands
;
9660 while (op
->type
!= type
)
9663 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9674 resolve_symbol_value (fragp
->fr_symbol
);
9675 val
= S_GET_VALUE (fragp
->fr_symbol
);
9680 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
9682 /* The rules for the base address of a PC relative reloc are
9683 complicated; see mips16_extended_frag. */
9684 if (type
== 'p' || type
== 'q')
9687 /* Ignore the low bit in the target, since it will be
9688 set for a text label. */
9692 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
9694 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
9699 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
9702 /* Make sure the section winds up with the alignment we have
9705 record_alignment (asec
, op
->shift
);
9708 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
9715 insn
= bfd_getl16 (buf
);
9718 insn
= bfd_getb16 (buf
);
9722 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
, false, small
,
9723 ext
, &insn
, &use_extend
, &extend
);
9727 md_number_to_chars (buf
, 0xf000 | extend
, 2);
9732 md_number_to_chars (buf
, insn
, 2);
9738 if (fragp
->fr_opcode
== NULL
)
9741 old
= RELAX_OLD (fragp
->fr_subtype
);
9742 new = RELAX_NEW (fragp
->fr_subtype
);
9743 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
9746 memcpy (fixptr
- old
, fixptr
, new);
9748 fragp
->fr_fix
+= new - old
;
9754 /* This function is called after the relocs have been generated.
9755 We've been storing mips16 text labels as odd. Here we convert them
9756 back to even for the convenience of the debugger. */
9759 mips_frob_file_after_relocs ()
9762 unsigned int count
, i
;
9764 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9767 syms
= bfd_get_outsymbols (stdoutput
);
9768 count
= bfd_get_symcount (stdoutput
);
9769 for (i
= 0; i
< count
; i
++, syms
++)
9771 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
9772 && ((*syms
)->value
& 1) != 0)
9774 (*syms
)->value
&= ~1;
9775 /* If the symbol has an odd size, it was probably computed
9776 incorrectly, so adjust that as well. */
9777 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
9778 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
9785 /* This function is called whenever a label is defined. It is used
9786 when handling branch delays; if a branch has a label, we assume we
9790 mips_define_label (sym
)
9793 struct insn_label_list
*l
;
9795 if (free_insn_labels
== NULL
)
9796 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
9799 l
= free_insn_labels
;
9800 free_insn_labels
= l
->next
;
9804 l
->next
= insn_labels
;
9808 /* Decide whether a label is local. This is called by LOCAL_LABEL.
9809 In order to work with gcc when using mips-tfile, we must keep all
9810 local labels. However, in other cases, we want to discard them,
9811 since they are useless. */
9814 mips_local_label (name
)
9817 #ifndef NO_ECOFF_DEBUGGING
9820 && ! ecoff_debugging_seen
)
9822 /* We were called with -g, but we didn't see any debugging
9823 information. That may mean that gcc is smuggling debugging
9824 information through to mips-tfile, in which case we must
9825 generate all local labels. */
9830 /* Here it's OK to discard local labels. */
9832 return name
[0] == '$';
9835 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9837 /* Some special processing for a MIPS ELF file. */
9840 mips_elf_final_processing ()
9842 /* Write out the register information. */
9847 s
.ri_gprmask
= mips_gprmask
;
9848 s
.ri_cprmask
[0] = mips_cprmask
[0];
9849 s
.ri_cprmask
[1] = mips_cprmask
[1];
9850 s
.ri_cprmask
[2] = mips_cprmask
[2];
9851 s
.ri_cprmask
[3] = mips_cprmask
[3];
9852 /* The gp_value field is set by the MIPS ELF backend. */
9854 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
9855 ((Elf32_External_RegInfo
*)
9856 mips_regmask_frag
));
9860 Elf64_Internal_RegInfo s
;
9862 s
.ri_gprmask
= mips_gprmask
;
9864 s
.ri_cprmask
[0] = mips_cprmask
[0];
9865 s
.ri_cprmask
[1] = mips_cprmask
[1];
9866 s
.ri_cprmask
[2] = mips_cprmask
[2];
9867 s
.ri_cprmask
[3] = mips_cprmask
[3];
9868 /* The gp_value field is set by the MIPS ELF backend. */
9870 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
9871 ((Elf64_External_RegInfo
*)
9872 mips_regmask_frag
));
9875 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
9876 sort of BFD interface for this. */
9877 if (mips_any_noreorder
)
9878 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
9879 if (mips_pic
!= NO_PIC
)
9880 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
9883 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
9885 /* These functions should really be defined by the object file format,
9886 since they are related to debugging information. However, this
9887 code has to work for the a.out format, which does not define them,
9888 so we provide simple versions here. These don't actually generate
9889 any debugging information, but they do simple checking and someday
9890 somebody may make them useful. */
9894 struct loc
*loc_next
;
9895 unsigned long loc_fileno
;
9896 unsigned long loc_lineno
;
9897 unsigned long loc_offset
;
9898 unsigned short loc_delta
;
9899 unsigned short loc_count
;
9908 struct proc
*proc_next
;
9909 struct symbol
*proc_isym
;
9910 struct symbol
*proc_end
;
9911 unsigned long proc_reg_mask
;
9912 unsigned long proc_reg_offset
;
9913 unsigned long proc_fpreg_mask
;
9914 unsigned long proc_fpreg_offset
;
9915 unsigned long proc_frameoffset
;
9916 unsigned long proc_framereg
;
9917 unsigned long proc_pcreg
;
9919 struct file
*proc_file
;
9926 struct file
*file_next
;
9927 unsigned long file_fileno
;
9928 struct symbol
*file_symbol
;
9929 struct symbol
*file_end
;
9930 struct proc
*file_proc
;
9935 static struct obstack proc_frags
;
9936 static procS
*proc_lastP
;
9937 static procS
*proc_rootP
;
9938 static int numprocs
;
9943 obstack_begin (&proc_frags
, 0x2000);
9949 /* check for premature end, nesting errors, etc */
9950 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
9951 as_warn ("missing `.end' at end of assembly");
9960 if (*input_line_pointer
== '-')
9962 ++input_line_pointer
;
9965 if (!isdigit (*input_line_pointer
))
9966 as_bad ("Expected simple number.");
9967 if (input_line_pointer
[0] == '0')
9969 if (input_line_pointer
[1] == 'x')
9971 input_line_pointer
+= 2;
9972 while (isxdigit (*input_line_pointer
))
9975 val
|= hex_value (*input_line_pointer
++);
9977 return negative
? -val
: val
;
9981 ++input_line_pointer
;
9982 while (isdigit (*input_line_pointer
))
9985 val
|= *input_line_pointer
++ - '0';
9987 return negative
? -val
: val
;
9990 if (!isdigit (*input_line_pointer
))
9992 printf (" *input_line_pointer == '%c' 0x%02x\n",
9993 *input_line_pointer
, *input_line_pointer
);
9994 as_warn ("Invalid number");
9997 while (isdigit (*input_line_pointer
))
10000 val
+= *input_line_pointer
++ - '0';
10002 return negative
? -val
: val
;
10005 /* The .file directive; just like the usual .file directive, but there
10006 is an initial number which is the ECOFF file index. */
10014 line
= get_number ();
10019 /* The .end directive. */
10027 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
10030 demand_empty_rest_of_line ();
10034 if (now_seg
!= text_section
)
10035 as_warn (".end not in text section");
10038 as_warn (".end and no .ent seen yet.");
10044 assert (S_GET_NAME (p
));
10045 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
10046 as_warn (".end symbol does not match .ent symbol.");
10049 proc_lastP
->proc_end
= (symbolS
*) 1;
10052 /* The .aent and .ent directives. */
10062 symbolP
= get_symbol ();
10063 if (*input_line_pointer
== ',')
10064 input_line_pointer
++;
10065 SKIP_WHITESPACE ();
10066 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
10067 number
= get_number ();
10068 if (now_seg
!= text_section
)
10069 as_warn (".ent or .aent not in text section.");
10071 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
10072 as_warn ("missing `.end'");
10076 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
10077 procP
->proc_isym
= symbolP
;
10078 procP
->proc_reg_mask
= 0;
10079 procP
->proc_reg_offset
= 0;
10080 procP
->proc_fpreg_mask
= 0;
10081 procP
->proc_fpreg_offset
= 0;
10082 procP
->proc_frameoffset
= 0;
10083 procP
->proc_framereg
= 0;
10084 procP
->proc_pcreg
= 0;
10085 procP
->proc_end
= NULL
;
10086 procP
->proc_next
= NULL
;
10088 proc_lastP
->proc_next
= procP
;
10090 proc_rootP
= procP
;
10091 proc_lastP
= procP
;
10094 demand_empty_rest_of_line ();
10097 /* The .frame directive. */
10110 frame_reg
= tc_get_register (1);
10111 if (*input_line_pointer
== ',')
10112 input_line_pointer
++;
10113 frame_off
= get_absolute_expression ();
10114 if (*input_line_pointer
== ',')
10115 input_line_pointer
++;
10116 pcreg
= tc_get_register (0);
10118 /* bob third eye */
10119 assert (proc_rootP
);
10120 proc_rootP
->proc_framereg
= frame_reg
;
10121 proc_rootP
->proc_frameoffset
= frame_off
;
10122 proc_rootP
->proc_pcreg
= pcreg
;
10123 /* bob macho .frame */
10125 /* We don't have to write out a frame stab for unoptimized code. */
10126 if (!(frame_reg
== FP
&& frame_off
== 0))
10129 as_warn ("No .ent for .frame to use.");
10130 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
10131 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
10132 S_SET_TYPE (symP
, N_RMASK
);
10133 S_SET_OTHER (symP
, 0);
10134 S_SET_DESC (symP
, 0);
10135 symP
->sy_forward
= proc_lastP
->proc_isym
;
10136 /* bob perhaps I should have used pseudo set */
10138 demand_empty_rest_of_line ();
10142 /* The .fmask and .mask directives. */
10149 char str
[100], *strP
;
10155 mask
= get_number ();
10156 if (*input_line_pointer
== ',')
10157 input_line_pointer
++;
10158 off
= get_absolute_expression ();
10160 /* bob only for coff */
10161 assert (proc_rootP
);
10162 if (reg_type
== 'F')
10164 proc_rootP
->proc_fpreg_mask
= mask
;
10165 proc_rootP
->proc_fpreg_offset
= off
;
10169 proc_rootP
->proc_reg_mask
= mask
;
10170 proc_rootP
->proc_reg_offset
= off
;
10173 /* bob macho .mask + .fmask */
10175 /* We don't have to write out a mask stab if no saved regs. */
10179 as_warn ("No .ent for .mask to use.");
10181 for (i
= 0; i
< 32; i
++)
10185 sprintf (strP
, "%c%d,", reg_type
, i
);
10186 strP
+= strlen (strP
);
10190 sprintf (strP
, ";%d,", off
);
10191 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
10192 S_SET_TYPE (symP
, N_RMASK
);
10193 S_SET_OTHER (symP
, 0);
10194 S_SET_DESC (symP
, 0);
10195 symP
->sy_forward
= proc_lastP
->proc_isym
;
10196 /* bob perhaps I should have used pseudo set */
10201 /* The .loc directive. */
10212 assert (now_seg
== text_section
);
10214 lineno
= get_number ();
10215 addroff
= frag_now_fix ();
10217 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
10218 S_SET_TYPE (symbolP
, N_SLINE
);
10219 S_SET_OTHER (symbolP
, 0);
10220 S_SET_DESC (symbolP
, lineno
);
10221 symbolP
->sy_segment
= now_seg
;