1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 1995, 1996 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
28 #include "libiberty.h"
39 #include "opcode/mips.h"
42 /* Clean up namespace so we can include obj-elf.h too. */
43 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
44 #undef OBJ_PROCESS_STAB
50 #undef TARGET_SYMBOL_FIELDS
52 #undef obj_frob_symbol
54 #undef obj_sec_sym_ok_for_reloc
57 /* Fix any of them that we actually care about. */
59 #define OUTPUT_FLAVOR mips_output_flavor()
66 #ifndef ECOFF_DEBUGGING
67 #define NO_ECOFF_DEBUGGING
68 #define ECOFF_DEBUGGING 0
73 static char *mips_regmask_frag
;
76 #define PIC_CALL_REG 25
84 extern int target_big_endian
;
86 /* The default target format to use. */
90 switch (OUTPUT_FLAVOR
)
92 case bfd_target_aout_flavour
:
93 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
94 case bfd_target_ecoff_flavour
:
95 return target_big_endian
? "ecoff-bigmips" : "ecoff-littlemips";
96 case bfd_target_elf_flavour
:
97 return target_big_endian
? "elf32-bigmips" : "elf32-littlemips";
103 /* The name of the readonly data section. */
104 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
106 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
108 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
112 /* These variables are filled in with the masks of registers used.
113 The object format code reads them and puts them in the appropriate
115 unsigned long mips_gprmask
;
116 unsigned long mips_cprmask
[4];
118 /* MIPS ISA (Instruction Set Architecture) level (may be changed
119 temporarily using .set mipsN). */
120 static int mips_isa
= -1;
122 /* MIPS ISA we are using for this output file. */
123 static int file_mips_isa
;
125 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
126 static int mips_cpu
= -1;
128 /* Whether the 4650 instructions (mad/madu) are permitted. */
129 static int mips_4650
= -1;
131 /* Whether the 4010 instructions are permitted. */
132 static int mips_4010
= -1;
134 /* Whether the 4100 MADD16 and DMADD16 are permitted. */
135 static int mips_4100
= -1;
137 /* Whether the processor uses hardware interlocks, and thus does not
138 require nops to be inserted. */
139 static int interlocks
= -1;
141 /* MIPS PIC level. */
145 /* Do not generate PIC code. */
148 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
149 not sure what it is supposed to do. */
152 /* Generate PIC code as in the SVR4 MIPS ABI. */
155 /* Generate PIC code without using a global offset table: the data
156 segment has a maximum size of 64K, all data references are off
157 the $gp register, and all text references are PC relative. This
158 is used on some embedded systems. */
162 static enum mips_pic_level mips_pic
;
164 /* 1 if we should generate 32 bit offsets from the GP register in
165 SVR4_PIC mode. Currently has no meaning in other modes. */
166 static int mips_big_got
;
168 /* 1 if trap instructions should used for overflow rather than break
170 static int mips_trap
;
172 static int mips_warn_about_macros
;
173 static int mips_noreorder
;
174 static int mips_any_noreorder
;
175 static int mips_nomove
;
176 static int mips_noat
;
177 static int mips_nobopt
;
179 /* The size of the small data section. */
180 static int g_switch_value
= 8;
181 /* Whether the -G option was used. */
182 static int g_switch_seen
= 0;
187 /* If we can determine in advance that GP optimization won't be
188 possible, we can skip the relaxation stuff that tries to produce
189 GP-relative references. This makes delay slot optimization work
192 This function can only provide a guess, but it seems to work for
193 gcc output. If it guesses wrong, the only loss should be in
194 efficiency; it shouldn't introduce any bugs.
196 I don't know if a fix is needed for the SVR4_PIC mode. I've only
197 fixed it for the non-PIC mode. KR 95/04/07 */
198 static int nopic_need_relax
PARAMS ((symbolS
*));
200 /* handle of the OPCODE hash table */
201 static struct hash_control
*op_hash
= NULL
;
203 /* This array holds the chars that always start a comment. If the
204 pre-processor is disabled, these aren't very useful */
205 const char comment_chars
[] = "#";
207 /* This array holds the chars that only start a comment at the beginning of
208 a line. If the line seems to have the form '# 123 filename'
209 .line and .file directives will appear in the pre-processed output */
210 /* Note that input_file.c hand checks for '#' at the beginning of the
211 first line of the input file. This is because the compiler outputs
212 #NO_APP at the beginning of its output. */
213 /* Also note that C style comments are always supported. */
214 const char line_comment_chars
[] = "#";
216 /* This array holds machine specific line separator characters. */
217 const char line_separator_chars
[] = "";
219 /* Chars that can be used to separate mant from exp in floating point nums */
220 const char EXP_CHARS
[] = "eE";
222 /* Chars that mean this number is a floating point constant */
225 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
227 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
228 changed in read.c . Ideally it shouldn't have to know about it at all,
229 but nothing is ideal around here.
232 static char *insn_error
;
234 static int byte_order
;
236 static int auto_align
= 1;
238 /* Symbol labelling the current insn. */
239 static symbolS
*insn_label
;
241 /* When outputting SVR4 PIC code, the assembler needs to know the
242 offset in the stack frame from which to restore the $gp register.
243 This is set by the .cprestore pseudo-op, and saved in this
245 static offsetT mips_cprestore_offset
= -1;
247 /* This is the register which holds the stack frame, as set by the
248 .frame pseudo-op. This is needed to implement .cprestore. */
249 static int mips_frame_reg
= SP
;
251 /* To output NOP instructions correctly, we need to keep information
252 about the previous two instructions. */
254 /* Whether we are optimizing. The default value of 2 means to remove
255 unneeded NOPs and swap branch instructions when possible. A value
256 of 1 means to not swap branches. A value of 0 means to always
258 static int mips_optimize
= 2;
260 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
261 equivalent to seeing no -g option at all. */
262 static int mips_debug
= 0;
264 /* The previous instruction. */
265 static struct mips_cl_insn prev_insn
;
267 /* The instruction before prev_insn. */
268 static struct mips_cl_insn prev_prev_insn
;
270 /* If we don't want information for prev_insn or prev_prev_insn, we
271 point the insn_mo field at this dummy integer. */
272 static const struct mips_opcode dummy_opcode
= { 0 };
274 /* Non-zero if prev_insn is valid. */
275 static int prev_insn_valid
;
277 /* The frag for the previous instruction. */
278 static struct frag
*prev_insn_frag
;
280 /* The offset into prev_insn_frag for the previous instruction. */
281 static long prev_insn_where
;
283 /* The reloc for the previous instruction, if any. */
284 static fixS
*prev_insn_fixp
;
286 /* Non-zero if the previous instruction was in a delay slot. */
287 static int prev_insn_is_delay_slot
;
289 /* Non-zero if the previous instruction was in a .set noreorder. */
290 static int prev_insn_unreordered
;
292 /* Non-zero if the previous previous instruction was in a .set
294 static int prev_prev_insn_unreordered
;
296 /* Since the MIPS does not have multiple forms of PC relative
297 instructions, we do not have to do relaxing as is done on other
298 platforms. However, we do have to handle GP relative addressing
299 correctly, which turns out to be a similar problem.
301 Every macro that refers to a symbol can occur in (at least) two
302 forms, one with GP relative addressing and one without. For
303 example, loading a global variable into a register generally uses
304 a macro instruction like this:
306 If i can be addressed off the GP register (this is true if it is in
307 the .sbss or .sdata section, or if it is known to be smaller than
308 the -G argument) this will generate the following instruction:
310 This instruction will use a GPREL reloc. If i can not be addressed
311 off the GP register, the following instruction sequence will be used:
314 In this case the first instruction will have a HI16 reloc, and the
315 second reloc will have a LO16 reloc. Both relocs will be against
318 The issue here is that we may not know whether i is GP addressable
319 until after we see the instruction that uses it. Therefore, we
320 want to be able to choose the final instruction sequence only at
321 the end of the assembly. This is similar to the way other
322 platforms choose the size of a PC relative instruction only at the
325 When generating position independent code we do not use GP
326 addressing in quite the same way, but the issue still arises as
327 external symbols and local symbols must be handled differently.
329 We handle these issues by actually generating both possible
330 instruction sequences. The longer one is put in a frag_var with
331 type rs_machine_dependent. We encode what to do with the frag in
332 the subtype field. We encode (1) the number of existing bytes to
333 replace, (2) the number of new bytes to use, (3) the offset from
334 the start of the existing bytes to the first reloc we must generate
335 (that is, the offset is applied from the start of the existing
336 bytes after they are replaced by the new bytes, if any), (4) the
337 offset from the start of the existing bytes to the second reloc,
338 (5) whether a third reloc is needed (the third reloc is always four
339 bytes after the second reloc), and (6) whether to warn if this
340 variant is used (this is sometimes needed if .set nomacro or .set
341 noat is in effect). All these numbers are reasonably small.
343 Generating two instruction sequences must be handled carefully to
344 ensure that delay slots are handled correctly. Fortunately, there
345 are a limited number of cases. When the second instruction
346 sequence is generated, append_insn is directed to maintain the
347 existing delay slot information, so it continues to apply to any
348 code after the second instruction sequence. This means that the
349 second instruction sequence must not impose any requirements not
350 required by the first instruction sequence.
352 These variant frags are then handled in functions called by the
353 machine independent code. md_estimate_size_before_relax returns
354 the final size of the frag. md_convert_frag sets up the final form
355 of the frag. tc_gen_reloc adjust the first reloc and adds a second
357 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
361 | (((reloc1) + 64) << 9) \
362 | (((reloc2) + 64) << 2) \
363 | ((reloc3) ? (1 << 1) : 0) \
365 #define RELAX_OLD(i) (((i) >> 24) & 0xff)
366 #define RELAX_NEW(i) (((i) >> 16) & 0xff)
367 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
368 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
369 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
370 #define RELAX_WARN(i) ((i) & 1)
372 /* Prototypes for static functions. */
375 #define internalError() \
376 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
378 #define internalError() as_fatal ("MIPS internal Error");
381 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
382 unsigned int reg
, int fpr
));
383 static int reg_needs_delay
PARAMS ((int));
384 static void append_insn
PARAMS ((char *place
,
385 struct mips_cl_insn
* ip
,
387 bfd_reloc_code_real_type r
));
388 static void mips_no_prev_insn
PARAMS ((void));
389 static void mips_emit_delays
PARAMS ((void));
391 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
392 const char *name
, const char *fmt
,
395 static void macro_build ();
397 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
398 expressionS
* ep
, int regnum
));
399 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
400 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
402 static void load_register
PARAMS ((int *, int, expressionS
*, int));
403 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
404 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
405 #ifdef LOSING_COMPILER
406 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
408 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
409 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
410 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
411 static symbolS
*get_symbol
PARAMS ((void));
412 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
413 static void s_align
PARAMS ((int));
414 static void s_change_sec
PARAMS ((int));
415 static void s_cons
PARAMS ((int));
416 static void s_float_cons
PARAMS ((int));
417 static void s_mips_globl
PARAMS ((int));
418 static void s_option
PARAMS ((int));
419 static void s_mipsset
PARAMS ((int));
420 static void s_abicalls
PARAMS ((int));
421 static void s_cpload
PARAMS ((int));
422 static void s_cprestore
PARAMS ((int));
423 static void s_gpword
PARAMS ((int));
424 static void s_cpadd
PARAMS ((int));
425 static void md_obj_begin
PARAMS ((void));
426 static void md_obj_end
PARAMS ((void));
427 static long get_number
PARAMS ((void));
428 static void s_ent
PARAMS ((int));
429 static void s_mipsend
PARAMS ((int));
430 static void s_file
PARAMS ((int));
434 The following pseudo-ops from the Kane and Heinrich MIPS book
435 should be defined here, but are currently unsupported: .alias,
436 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
438 The following pseudo-ops from the Kane and Heinrich MIPS book are
439 specific to the type of debugging information being generated, and
440 should be defined by the object format: .aent, .begin, .bend,
441 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
444 The following pseudo-ops from the Kane and Heinrich MIPS book are
445 not MIPS CPU specific, but are also not specific to the object file
446 format. This file is probably the best place to define them, but
447 they are not currently supported: .asm0, .endr, .lab, .repeat,
448 .struct, .weakext. */
450 static const pseudo_typeS mips_pseudo_table
[] =
452 /* MIPS specific pseudo-ops. */
453 {"option", s_option
, 0},
454 {"set", s_mipsset
, 0},
455 {"rdata", s_change_sec
, 'r'},
456 {"sdata", s_change_sec
, 's'},
457 {"livereg", s_ignore
, 0},
458 {"abicalls", s_abicalls
, 0},
459 {"cpload", s_cpload
, 0},
460 {"cprestore", s_cprestore
, 0},
461 {"gpword", s_gpword
, 0},
462 {"cpadd", s_cpadd
, 0},
464 /* Relatively generic pseudo-ops that happen to be used on MIPS
466 {"asciiz", stringer
, 1},
467 {"bss", s_change_sec
, 'b'},
470 {"dword", s_cons
, 3},
472 /* These pseudo-ops are defined in read.c, but must be overridden
473 here for one reason or another. */
474 {"align", s_align
, 0},
476 {"data", s_change_sec
, 'd'},
477 {"double", s_float_cons
, 'd'},
478 {"float", s_float_cons
, 'f'},
479 {"globl", s_mips_globl
, 0},
480 {"global", s_mips_globl
, 0},
481 {"hword", s_cons
, 1},
486 {"short", s_cons
, 1},
487 {"single", s_float_cons
, 'f'},
488 {"text", s_change_sec
, 't'},
493 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
494 /* These pseudo-ops should be defined by the object file format.
495 However, a.out doesn't support them, so we have versions here. */
497 {"bgnb", s_ignore
, 0},
498 {"end", s_mipsend
, 0},
499 {"endb", s_ignore
, 0},
502 {"fmask", s_ignore
, 'F'},
503 {"frame", s_ignore
, 0},
504 {"loc", s_ignore
, 0},
505 {"mask", s_ignore
, 'R'},
506 {"verstamp", s_ignore
, 0},
510 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
515 pop_insert (mips_pseudo_table
);
516 if (! ECOFF_DEBUGGING
)
517 pop_insert (mips_nonecoff_pseudo_table
);
520 static char *expr_end
;
522 static expressionS imm_expr
;
523 static expressionS offset_expr
;
524 static bfd_reloc_code_real_type imm_reloc
;
525 static bfd_reloc_code_real_type offset_reloc
;
528 * This function is called once, at assembler startup time. It should
529 * set up all the tables, etc. that the MD part of the assembler will need.
535 register const char *retval
= NULL
;
536 register unsigned int i
= 0;
544 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
546 a
= xmalloc (sizeof TARGET_CPU
);
547 strcpy (a
, TARGET_CPU
);
548 a
[(sizeof TARGET_CPU
) - 3] = '\0';
552 if (strcmp (cpu
, "mips") == 0)
558 else if (strcmp (cpu
, "r6000") == 0
559 || strcmp (cpu
, "mips2") == 0)
565 else if (strcmp (cpu
, "mips64") == 0
566 || strcmp (cpu
, "r4000") == 0
567 || strcmp (cpu
, "mips3") == 0)
573 else if (strcmp (cpu
, "r4400") == 0)
579 else if (strcmp (cpu
, "mips64orion") == 0
580 || strcmp (cpu
, "r4600") == 0)
586 else if (strcmp (cpu
, "r4650") == 0)
594 else if (strcmp (cpu
, "mips64vr4300") == 0)
600 else if (strcmp (cpu
, "mips64vr4100") == 0)
608 else if (strcmp (cpu
, "r4010") == 0)
616 else if (strcmp (cpu
, "r8000") == 0
617 || strcmp (cpu
, "mips4") == 0)
623 else if (strcmp (cpu
, "r10000") == 0)
649 if (mips_4650
|| mips_4010
|| mips_4100
)
654 if (mips_isa
< 2 && mips_trap
)
655 as_bad ("trap exception not supported at ISA 1");
660 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
663 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
666 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
669 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
673 as_warn ("Could not set architecture and machine");
675 file_mips_isa
= mips_isa
;
677 op_hash
= hash_new ();
679 for (i
= 0; i
< NUMOPCODES
;)
681 const char *name
= mips_opcodes
[i
].name
;
683 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
686 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
687 mips_opcodes
[i
].name
, retval
);
688 as_fatal ("Broken assembler. No assembly attempted.");
692 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
693 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
694 != mips_opcodes
[i
].match
))
696 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
697 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
698 as_fatal ("Broken assembler. No assembly attempted.");
702 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
705 mips_no_prev_insn ();
713 /* set the default alignment for the text section (2**2) */
714 record_alignment (text_section
, 2);
716 if (USE_GLOBAL_POINTER_OPT
)
717 bfd_set_gp_size (stdoutput
, g_switch_value
);
719 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
721 /* Sections must be aligned to 16 byte boundaries. */
722 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
723 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
724 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
726 /* Create a .reginfo section for register masks and a .mdebug
727 section for debugging information. */
735 sec
= subseg_new (".reginfo", (subsegT
) 0);
737 /* The ABI says this section should be loaded so that the
738 running program can access it. */
739 (void) bfd_set_section_flags (stdoutput
, sec
,
740 (SEC_ALLOC
| SEC_LOAD
741 | SEC_READONLY
| SEC_DATA
));
742 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
745 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
750 sec
= subseg_new (".mdebug", (subsegT
) 0);
751 (void) bfd_set_section_flags (stdoutput
, sec
,
752 SEC_HAS_CONTENTS
| SEC_READONLY
);
753 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
756 subseg_set (seg
, subseg
);
760 if (! ECOFF_DEBUGGING
)
767 if (! ECOFF_DEBUGGING
)
775 struct mips_cl_insn insn
;
777 imm_expr
.X_op
= O_absent
;
778 offset_expr
.X_op
= O_absent
;
780 mips_ip (str
, &insn
);
783 as_bad ("%s `%s'", insn_error
, str
);
786 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
792 if (imm_expr
.X_op
!= O_absent
)
793 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
);
794 else if (offset_expr
.X_op
!= O_absent
)
795 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
);
797 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
);
801 /* See whether instruction IP reads register REG. If FPR is non-zero,
802 REG is a floating point register. */
805 insn_uses_reg (ip
, reg
, fpr
)
806 struct mips_cl_insn
*ip
;
810 /* Don't report on general register 0, since it never changes. */
811 if (! fpr
&& reg
== 0)
816 /* If we are called with either $f0 or $f1, we must check $f0.
817 This is not optimal, because it will introduce an unnecessary
818 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
819 need to distinguish reading both $f0 and $f1 or just one of
820 them. Note that we don't have to check the other way,
821 because there is no instruction that sets both $f0 and $f1
822 and requires a delay. */
823 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
824 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
825 == (reg
&~ (unsigned) 1)))
827 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
828 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
829 == (reg
&~ (unsigned) 1)))
834 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
835 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
837 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
838 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
845 /* This function returns true if modifying a register requires a
849 reg_needs_delay (reg
)
852 unsigned long prev_pinfo
;
854 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
857 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
859 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
861 /* A load from a coprocessor or from memory. All load
862 delays delay the use of general register rt for one
863 instruction on the r3000. The r6000 and r4000 use
865 know (prev_pinfo
& INSN_WRITE_GPR_T
);
866 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
873 /* Output an instruction. PLACE is where to put the instruction; if
874 it is NULL, this uses frag_more to get room. IP is the instruction
875 information. ADDRESS_EXPR is an operand of the instruction to be
876 used with RELOC_TYPE. */
879 append_insn (place
, ip
, address_expr
, reloc_type
)
881 struct mips_cl_insn
*ip
;
882 expressionS
*address_expr
;
883 bfd_reloc_code_real_type reloc_type
;
885 register unsigned long prev_pinfo
, pinfo
;
890 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
891 pinfo
= ip
->insn_mo
->pinfo
;
893 if (place
== NULL
&& ! mips_noreorder
)
895 /* If the previous insn required any delay slots, see if we need
896 to insert a NOP or two. There are eight kinds of possible
897 hazards, of which an instruction can have at most one type.
898 (1) a load from memory delay
899 (2) a load from a coprocessor delay
900 (3) an unconditional branch delay
901 (4) a conditional branch delay
902 (5) a move to coprocessor register delay
903 (6) a load coprocessor register from memory delay
904 (7) a coprocessor condition code delay
905 (8) a HI/LO special register delay
907 There are a lot of optimizations we could do that we don't.
908 In particular, we do not, in general, reorder instructions.
909 If you use gcc with optimization, it will reorder
910 instructions and generally do much more optimization then we
911 do here; repeating all that work in the assembler would only
912 benefit hand written assembly code, and does not seem worth
915 /* This is how a NOP is emitted. */
916 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
918 /* The previous insn might require a delay slot, depending upon
919 the contents of the current insn. */
921 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
923 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
925 /* A load from a coprocessor or from memory. All load
926 delays delay the use of general register rt for one
927 instruction on the r3000. The r6000 and r4000 use
929 know (prev_pinfo
& INSN_WRITE_GPR_T
);
930 if (mips_optimize
== 0
931 || insn_uses_reg (ip
,
932 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
937 else if (mips_isa
< 4
938 && ((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
940 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
942 /* A generic coprocessor delay. The previous instruction
943 modified a coprocessor general or control register. If
944 it modified a control register, we need to avoid any
945 coprocessor instruction (this is probably not always
946 required, but it sometimes is). If it modified a general
947 register, we avoid using that register.
949 On the r6000 and r4000 loading a coprocessor register
950 from memory is interlocked, and does not require a delay.
952 This case is not handled very well. There is no special
953 knowledge of CP0 handling, and the coprocessors other
954 than the floating point unit are not distinguished at
956 if (prev_pinfo
& INSN_WRITE_FPR_T
)
958 if (mips_optimize
== 0
959 || insn_uses_reg (ip
,
960 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
965 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
967 if (mips_optimize
== 0
968 || insn_uses_reg (ip
,
969 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
976 /* We don't know exactly what the previous instruction
977 does. If the current instruction uses a coprocessor
978 register, we must insert a NOP. If previous
979 instruction may set the condition codes, and the
980 current instruction uses them, we must insert two
982 if (mips_optimize
== 0
983 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
984 && (pinfo
& INSN_READ_COND_CODE
)))
986 else if (pinfo
& INSN_COP
)
990 else if (mips_isa
< 4
991 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
993 /* The previous instruction sets the coprocessor condition
994 codes, but does not require a general coprocessor delay
995 (this means it is a floating point comparison
996 instruction). If this instruction uses the condition
997 codes, we need to insert a single NOP. */
998 if (mips_optimize
== 0
999 || (pinfo
& INSN_READ_COND_CODE
))
1002 else if (prev_pinfo
& INSN_READ_LO
)
1004 /* The previous instruction reads the LO register; if the
1005 current instruction writes to the LO register, we must
1006 insert two NOPS. The R4650 and VR4100 have interlocks. */
1008 && (mips_optimize
== 0
1009 || (pinfo
& INSN_WRITE_LO
)))
1012 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1014 /* The previous instruction reads the HI register; if the
1015 current instruction writes to the HI register, we must
1016 insert a NOP. The R4650 and VR4100 have interlocks. */
1018 && (mips_optimize
== 0
1019 || (pinfo
& INSN_WRITE_HI
)))
1023 /* There are two cases which require two intervening
1024 instructions: 1) setting the condition codes using a move to
1025 coprocessor instruction which requires a general coprocessor
1026 delay and then reading the condition codes 2) reading the HI
1027 or LO register and then writing to it (except on the R4650,
1028 and VR4100 which have interlocks). If we are not already
1029 emitting a NOP instruction, we must check for these cases
1030 compared to the instruction previous to the previous
1034 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1035 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1036 && (pinfo
& INSN_READ_COND_CODE
))
1037 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1038 && (pinfo
& INSN_WRITE_LO
)
1040 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1041 && (pinfo
& INSN_WRITE_HI
)
1045 /* If we are being given a nop instruction, don't bother with
1046 one of the nops we would otherwise output. This will only
1047 happen when a nop instruction is used with mips_optimize set
1049 if (nops
> 0 && ip
->insn_opcode
== 0)
1052 /* Now emit the right number of NOP instructions. */
1057 for (i
= 0; i
< nops
; i
++)
1061 listing_prev_line ();
1062 /* We may be at the start of a variant frag. In case we
1063 are, make sure there is enough space for the frag
1064 after the frags created by listing_prev_line. The
1065 argument to frag_grow here must be at least as large
1066 as the argument to all other calls to frag_grow in
1067 this file. We don't have to worry about being in the
1068 middle of a variant frag, because the variants insert
1069 all needed nop instructions themselves. */
1072 if (insn_label
!= NULL
)
1074 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1075 insn_label
->sy_frag
= frag_now
;
1076 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1086 if (address_expr
!= NULL
)
1088 if (address_expr
->X_op
== O_constant
)
1093 ip
->insn_opcode
|= address_expr
->X_add_number
;
1096 case BFD_RELOC_LO16
:
1097 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1100 case BFD_RELOC_MIPS_JMP
:
1101 case BFD_RELOC_16_PCREL_S2
:
1110 assert (reloc_type
!= BFD_RELOC_UNUSED
);
1112 /* Don't generate a reloc if we are writing into a variant
1115 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1117 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1122 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1124 /* Update the register mask information. */
1125 if (pinfo
& INSN_WRITE_GPR_D
)
1126 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1127 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1128 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1129 if (pinfo
& INSN_READ_GPR_S
)
1130 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1131 if (pinfo
& INSN_WRITE_GPR_31
)
1132 mips_gprmask
|= 1 << 31;
1133 if (pinfo
& INSN_WRITE_FPR_D
)
1134 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1135 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1136 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1137 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1138 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1139 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1140 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1141 if (pinfo
& INSN_COP
)
1143 /* We don't keep enough information to sort these cases out. */
1145 /* Never set the bit for $0, which is always zero. */
1146 mips_gprmask
&=~ 1 << 0;
1148 if (place
== NULL
&& ! mips_noreorder
)
1150 /* Filling the branch delay slot is more complex. We try to
1151 switch the branch with the previous instruction, which we can
1152 do if the previous instruction does not set up a condition
1153 that the branch tests and if the branch is not itself the
1154 target of any branch. */
1155 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1156 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1158 if (mips_optimize
< 2
1159 /* If we have seen .set volatile or .set nomove, don't
1162 /* If we had to emit any NOP instructions, then we
1163 already know we can not swap. */
1165 /* If we don't even know the previous insn, we can not
1167 || ! prev_insn_valid
1168 /* If the previous insn is already in a branch delay
1169 slot, then we can not swap. */
1170 || prev_insn_is_delay_slot
1171 /* If the previous previous insn was in a .set
1172 noreorder, we can't swap. Actually, the MIPS
1173 assembler will swap in this situation. However, gcc
1174 configured -with-gnu-as will generate code like
1180 in which we can not swap the bne and INSN. If gcc is
1181 not configured -with-gnu-as, it does not output the
1182 .set pseudo-ops. We don't have to check
1183 prev_insn_unreordered, because prev_insn_valid will
1184 be 0 in that case. We don't want to use
1185 prev_prev_insn_valid, because we do want to be able
1186 to swap at the start of a function. */
1187 || prev_prev_insn_unreordered
1188 /* If the branch is itself the target of a branch, we
1189 can not swap. We cheat on this; all we check for is
1190 whether there is a label on this instruction. If
1191 there are any branches to anything other than a
1192 label, users must use .set noreorder. */
1193 || insn_label
!= NULL
1194 /* If the previous instruction is in a variant frag, we
1195 can not do the swap. */
1196 || prev_insn_frag
->fr_type
== rs_machine_dependent
1197 /* If the branch reads the condition codes, we don't
1198 even try to swap, because in the sequence
1203 we can not swap, and I don't feel like handling that
1206 && (pinfo
& INSN_READ_COND_CODE
))
1207 /* We can not swap with an instruction that requires a
1208 delay slot, becase the target of the branch might
1209 interfere with that instruction. */
1212 & (INSN_LOAD_COPROC_DELAY
1213 | INSN_COPROC_MOVE_DELAY
1214 | INSN_WRITE_COND_CODE
)))
1221 & (INSN_LOAD_MEMORY_DELAY
1222 | INSN_COPROC_MEMORY_DELAY
)))
1223 /* We can not swap with a branch instruction. */
1225 & (INSN_UNCOND_BRANCH_DELAY
1226 | INSN_COND_BRANCH_DELAY
1227 | INSN_COND_BRANCH_LIKELY
))
1228 /* We do not swap with a trap instruction, since it
1229 complicates trap handlers to have the trap
1230 instruction be in a delay slot. */
1231 || (prev_pinfo
& INSN_TRAP
)
1232 /* If the branch reads a register that the previous
1233 instruction sets, we can not swap. */
1234 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1235 && insn_uses_reg (ip
,
1236 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1239 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1240 && insn_uses_reg (ip
,
1241 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1244 /* If the branch writes a register that the previous
1245 instruction sets, we can not swap (we know that
1246 branches write only to RD or to $31). */
1247 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1248 && (((pinfo
& INSN_WRITE_GPR_D
)
1249 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1250 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1251 || ((pinfo
& INSN_WRITE_GPR_31
)
1252 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1255 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1256 && (((pinfo
& INSN_WRITE_GPR_D
)
1257 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1258 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1259 || ((pinfo
& INSN_WRITE_GPR_31
)
1260 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1263 /* If the branch writes a register that the previous
1264 instruction reads, we can not swap (we know that
1265 branches only write to RD or to $31). */
1266 || ((pinfo
& INSN_WRITE_GPR_D
)
1267 && insn_uses_reg (&prev_insn
,
1268 ((ip
->insn_opcode
>> OP_SH_RD
)
1271 || ((pinfo
& INSN_WRITE_GPR_31
)
1272 && insn_uses_reg (&prev_insn
, 31, 0))
1273 /* If we are generating embedded PIC code, the branch
1274 might be expanded into a sequence which uses $at, so
1275 we can't swap with an instruction which reads it. */
1276 || (mips_pic
== EMBEDDED_PIC
1277 && insn_uses_reg (&prev_insn
, AT
, 0))
1278 /* If the previous previous instruction has a load
1279 delay, and sets a register that the branch reads, we
1282 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1284 && (prev_prev_insn
.insn_mo
->pinfo
1285 & INSN_LOAD_MEMORY_DELAY
)))
1286 && insn_uses_reg (ip
,
1287 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1291 /* We could do even better for unconditional branches to
1292 portions of this object file; we could pick up the
1293 instruction at the destination, put it in the delay
1294 slot, and bump the destination address. */
1296 /* Update the previous insn information. */
1297 prev_prev_insn
= *ip
;
1298 prev_insn
.insn_mo
= &dummy_opcode
;
1305 /* It looks like we can actually do the swap. */
1306 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1307 memcpy (temp
, prev_f
, 4);
1308 memcpy (prev_f
, f
, 4);
1309 memcpy (f
, temp
, 4);
1312 prev_insn_fixp
->fx_frag
= frag_now
;
1313 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1317 fixp
->fx_frag
= prev_insn_frag
;
1318 fixp
->fx_where
= prev_insn_where
;
1320 /* Update the previous insn information; leave prev_insn
1322 prev_prev_insn
= *ip
;
1324 prev_insn_is_delay_slot
= 1;
1326 /* If that was an unconditional branch, forget the previous
1327 insn information. */
1328 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1330 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1331 prev_insn
.insn_mo
= &dummy_opcode
;
1334 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1336 /* We don't yet optimize a branch likely. What we should do
1337 is look at the target, copy the instruction found there
1338 into the delay slot, and increment the branch to jump to
1339 the next instruction. */
1341 /* Update the previous insn information. */
1342 prev_prev_insn
= *ip
;
1343 prev_insn
.insn_mo
= &dummy_opcode
;
1347 /* Update the previous insn information. */
1349 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1351 prev_prev_insn
= prev_insn
;
1354 /* Any time we see a branch, we always fill the delay slot
1355 immediately; since this insn is not a branch, we know it
1356 is not in a delay slot. */
1357 prev_insn_is_delay_slot
= 0;
1360 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1361 prev_insn_unreordered
= 0;
1362 prev_insn_frag
= frag_now
;
1363 prev_insn_where
= f
- frag_now
->fr_literal
;
1364 prev_insn_fixp
= fixp
;
1365 prev_insn_valid
= 1;
1368 /* We just output an insn, so the next one doesn't have a label. */
1372 /* This function forgets that there was any previous instruction or
1376 mips_no_prev_insn ()
1378 prev_insn
.insn_mo
= &dummy_opcode
;
1379 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1380 prev_insn_valid
= 0;
1381 prev_insn_is_delay_slot
= 0;
1382 prev_insn_unreordered
= 0;
1383 prev_prev_insn_unreordered
= 0;
1387 /* This function must be called whenever we turn on noreorder or emit
1388 something other than instructions. It inserts any NOPS which might
1389 be needed by the previous instruction, and clears the information
1390 kept for the previous instructions. */
1395 if (! mips_noreorder
)
1401 && (prev_insn
.insn_mo
->pinfo
1402 & (INSN_LOAD_COPROC_DELAY
1403 | INSN_COPROC_MOVE_DELAY
1404 | INSN_WRITE_COND_CODE
)))
1406 && (prev_insn
.insn_mo
->pinfo
1410 && (prev_insn
.insn_mo
->pinfo
1411 & (INSN_LOAD_MEMORY_DELAY
1412 | INSN_COPROC_MEMORY_DELAY
))))
1416 && (prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1418 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1419 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1422 else if ((mips_isa
< 4
1423 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1425 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1426 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1431 if (insn_label
!= NULL
)
1433 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1434 insn_label
->sy_frag
= frag_now
;
1435 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1440 mips_no_prev_insn ();
1443 /* Build an instruction created by a macro expansion. This is passed
1444 a pointer to the count of instructions created so far, an
1445 expression, the name of the instruction to build, an operand format
1446 string, and corresponding arguments. */
1450 macro_build (char *place
,
1458 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
1467 struct mips_cl_insn insn
;
1468 bfd_reloc_code_real_type r
;
1472 va_start (args
, fmt
);
1478 * If the macro is about to expand into a second instruction,
1479 * print a warning if needed. We need to pass ip as a parameter
1480 * to generate a better warning message here...
1482 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1483 as_warn ("Macro instruction expanded into multiple instructions");
1486 *counter
+= 1; /* bump instruction counter */
1488 r
= BFD_RELOC_UNUSED
;
1489 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1490 assert (insn
.insn_mo
);
1491 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1493 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
1494 || insn
.insn_mo
->pinfo
== INSN_MACRO
1495 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA2
1497 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA3
1499 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA4
1501 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4650
1503 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4010
1505 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4100
1509 assert (insn
.insn_mo
->name
);
1510 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1512 insn
.insn_opcode
= insn
.insn_mo
->match
;
1528 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1534 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1539 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1544 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1551 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1555 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1559 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1566 insn
.insn_opcode
|= va_arg (args
, int) << 21;
1572 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1573 assert (r
== BFD_RELOC_MIPS_GPREL
1574 || r
== BFD_RELOC_MIPS_LITERAL
1575 || r
== BFD_RELOC_LO16
1576 || r
== BFD_RELOC_MIPS_GOT16
1577 || r
== BFD_RELOC_MIPS_CALL16
1578 || r
== BFD_RELOC_MIPS_GOT_LO16
1579 || r
== BFD_RELOC_MIPS_CALL_LO16
1580 || (ep
->X_op
== O_subtract
1581 && now_seg
== text_section
1582 && r
== BFD_RELOC_PCREL_LO16
));
1586 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1588 && (ep
->X_op
== O_constant
1589 || (ep
->X_op
== O_symbol
1590 && (r
== BFD_RELOC_HI16_S
1591 || r
== BFD_RELOC_HI16
1592 || r
== BFD_RELOC_MIPS_GOT_HI16
1593 || r
== BFD_RELOC_MIPS_CALL_HI16
))
1594 || (ep
->X_op
== O_subtract
1595 && now_seg
== text_section
1596 && r
== BFD_RELOC_PCREL_HI16_S
)));
1597 if (ep
->X_op
== O_constant
)
1599 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
1601 r
= BFD_RELOC_UNUSED
;
1606 assert (ep
!= NULL
);
1608 * This allows macro() to pass an immediate expression for
1609 * creating short branches without creating a symbol.
1610 * Note that the expression still might come from the assembly
1611 * input, in which case the value is not checked for range nor
1612 * is a relocation entry generated (yuck).
1614 if (ep
->X_op
== O_constant
)
1616 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
1620 r
= BFD_RELOC_16_PCREL_S2
;
1624 assert (ep
!= NULL
);
1625 r
= BFD_RELOC_MIPS_JMP
;
1634 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1636 append_insn (place
, &insn
, ep
, r
);
1640 * Generate a "lui" instruction.
1643 macro_build_lui (place
, counter
, ep
, regnum
)
1649 expressionS high_expr
;
1650 struct mips_cl_insn insn
;
1651 bfd_reloc_code_real_type r
;
1652 CONST
char *name
= "lui";
1653 CONST
char *fmt
= "t,u";
1659 high_expr
.X_op
= O_constant
;
1660 high_expr
.X_add_number
= ep
->X_add_number
;
1663 if (high_expr
.X_op
== O_constant
)
1665 /* we can compute the instruction now without a relocation entry */
1666 if (high_expr
.X_add_number
& 0x8000)
1667 high_expr
.X_add_number
+= 0x10000;
1668 high_expr
.X_add_number
=
1669 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
1670 r
= BFD_RELOC_UNUSED
;
1674 assert (ep
->X_op
== O_symbol
);
1675 /* _gp_disp is a special case, used from s_cpload. */
1676 assert (mips_pic
== NO_PIC
1677 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
1678 r
= BFD_RELOC_HI16_S
;
1682 * If the macro is about to expand into a second instruction,
1683 * print a warning if needed. We need to pass ip as a parameter
1684 * to generate a better warning message here...
1686 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1687 as_warn ("Macro instruction expanded into multiple instructions");
1690 *counter
+= 1; /* bump instruction counter */
1692 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1693 assert (insn
.insn_mo
);
1694 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1695 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
1697 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
1698 if (r
== BFD_RELOC_UNUSED
)
1700 insn
.insn_opcode
|= high_expr
.X_add_number
;
1701 append_insn (place
, &insn
, NULL
, r
);
1704 append_insn (place
, &insn
, &high_expr
, r
);
1708 * Generates code to set the $at register to true (one)
1709 * if reg is less than the immediate expression.
1712 set_at (counter
, reg
, unsignedp
)
1717 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1718 macro_build ((char *) NULL
, counter
, &imm_expr
,
1719 unsignedp
? "sltiu" : "slti",
1720 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
1723 load_register (counter
, AT
, &imm_expr
, 0);
1724 macro_build ((char *) NULL
, counter
, NULL
,
1725 unsignedp
? "sltu" : "slt",
1726 "d,v,t", AT
, reg
, AT
);
1730 /* Warn if an expression is not a constant. */
1733 check_absolute_expr (ip
, ex
)
1734 struct mips_cl_insn
*ip
;
1737 if (ex
->X_op
!= O_constant
)
1738 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
1742 * This routine generates the least number of instructions neccessary to load
1743 * an absolute expression value into a register.
1746 load_register (counter
, reg
, ep
, dbl
)
1753 expressionS hi32
, lo32
, tmp
;
1755 if (ep
->X_op
!= O_big
)
1757 assert (ep
->X_op
== O_constant
);
1758 if (ep
->X_add_number
< 0x8000
1759 && (ep
->X_add_number
>= 0
1760 || (ep
->X_add_number
>= -0x8000
1763 || sizeof (ep
->X_add_number
) > 4))))
1765 /* We can handle 16 bit signed values with an addiu to
1766 $zero. No need to ever use daddiu here, since $zero and
1767 the result are always correct in 32 bit mode. */
1768 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1769 (int) BFD_RELOC_LO16
);
1772 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
1774 /* We can handle 16 bit unsigned values with an ori to
1776 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
1777 (int) BFD_RELOC_LO16
);
1780 else if (((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
1781 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
1782 == ~ (offsetT
) 0x7fffffff))
1785 || sizeof (ep
->X_add_number
) > 4
1786 || (ep
->X_add_number
& 0x80000000) == 0))
1788 /* 32 bit values require an lui. */
1789 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
1790 (int) BFD_RELOC_HI16
);
1791 if ((ep
->X_add_number
& 0xffff) != 0)
1792 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
1793 (int) BFD_RELOC_LO16
);
1798 /* 32 bit value with high bit set being loaded into a 64 bit
1799 register. We can't use lui, because that would
1800 incorrectly set the 32 high bits. */
1801 generic_bignum
[3] = 0;
1802 generic_bignum
[2] = 0;
1803 generic_bignum
[1] = (ep
->X_add_number
>> 16) & 0xffff;
1804 generic_bignum
[0] = ep
->X_add_number
& 0xffff;
1806 tmp
.X_add_number
= 4;
1811 /* The value is larger than 32 bits. */
1815 as_bad ("Number larger than 32 bits");
1816 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1817 (int) BFD_RELOC_LO16
);
1821 if (ep
->X_op
!= O_big
)
1825 hi32
.X_add_number
>>= shift
;
1826 hi32
.X_add_number
&= 0xffffffff;
1827 if ((hi32
.X_add_number
& 0x80000000) != 0)
1828 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
1830 lo32
.X_add_number
&= 0xffffffff;
1834 assert (ep
->X_add_number
> 2);
1835 if (ep
->X_add_number
== 3)
1836 generic_bignum
[3] = 0;
1837 else if (ep
->X_add_number
> 4)
1838 as_bad ("Number larger than 64 bits");
1839 lo32
.X_op
= O_constant
;
1840 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
1841 hi32
.X_op
= O_constant
;
1842 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
1845 if (hi32
.X_add_number
== 0)
1849 if (hi32
.X_add_number
== 0xffffffff)
1851 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
1853 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j", reg
, 0,
1854 (int) BFD_RELOC_LO16
);
1857 if (lo32
.X_add_number
& 0x80000000)
1859 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
1860 (int) BFD_RELOC_HI16
);
1861 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, reg
,
1862 (int) BFD_RELOC_LO16
);
1866 load_register (counter
, reg
, &hi32
, 0);
1869 if ((lo32
.X_add_number
& 0xffff0000) == 0)
1873 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
1882 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
1884 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
1885 (int) BFD_RELOC_HI16
);
1886 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
1893 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1898 mid16
.X_add_number
>>= 16;
1899 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
1900 freg
, (int) BFD_RELOC_LO16
);
1901 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1905 if ((lo32
.X_add_number
& 0xffff) != 0)
1906 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
1907 (int) BFD_RELOC_LO16
);
1910 /* Load an address into a register. */
1913 load_address (counter
, reg
, ep
)
1920 if (ep
->X_op
!= O_constant
1921 && ep
->X_op
!= O_symbol
)
1923 as_bad ("expression too complex");
1924 ep
->X_op
= O_constant
;
1927 if (ep
->X_op
== O_constant
)
1929 load_register (counter
, reg
, ep
, 0);
1933 if (mips_pic
== NO_PIC
)
1935 /* If this is a reference to a GP relative symbol, we want
1936 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
1938 lui $reg,<sym> (BFD_RELOC_HI16_S)
1939 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1940 If we have an addend, we always use the latter form. */
1941 if (ep
->X_add_number
!= 0 || nopic_need_relax (ep
->X_add_symbol
))
1946 macro_build ((char *) NULL
, counter
, ep
,
1947 mips_isa
< 3 ? "addiu" : "daddiu",
1948 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
1949 p
= frag_var (rs_machine_dependent
, 8, 0,
1950 RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros
),
1951 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1953 macro_build_lui (p
, counter
, ep
, reg
);
1956 macro_build (p
, counter
, ep
,
1957 mips_isa
< 3 ? "addiu" : "daddiu",
1958 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1960 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
1964 /* If this is a reference to an external symbol, we want
1965 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1967 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1969 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1970 If there is a constant, it must be added in after. */
1971 ex
.X_add_number
= ep
->X_add_number
;
1972 ep
->X_add_number
= 0;
1974 macro_build ((char *) NULL
, counter
, ep
,
1975 mips_isa
< 3 ? "lw" : "ld",
1976 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
1977 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
1978 p
= frag_var (rs_machine_dependent
, 4, 0,
1979 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
1980 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1981 macro_build (p
, counter
, ep
,
1982 mips_isa
< 3 ? "addiu" : "daddiu",
1983 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1984 if (ex
.X_add_number
!= 0)
1986 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
1987 as_bad ("PIC code offset overflow (max 16 signed bits)");
1988 ex
.X_op
= O_constant
;
1989 macro_build ((char *) NULL
, counter
, &ex
,
1990 mips_isa
< 3 ? "addiu" : "daddiu",
1991 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1994 else if (mips_pic
== SVR4_PIC
)
1999 /* This is the large GOT case. If this is a reference to an
2000 external symbol, we want
2001 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
2003 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
2004 Otherwise, for a reference to a local symbol, we want
2005 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2007 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2008 If there is a constant, it must be added in after. */
2009 ex
.X_add_number
= ep
->X_add_number
;
2010 ep
->X_add_number
= 0;
2011 if (reg_needs_delay (GP
))
2016 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2017 (int) BFD_RELOC_MIPS_GOT_HI16
);
2018 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
2019 mips_isa
< 3 ? "addu" : "daddu",
2020 "d,v,t", reg
, reg
, GP
);
2021 macro_build ((char *) NULL
, counter
, ep
,
2022 mips_isa
< 3 ? "lw" : "ld",
2023 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
2024 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
2025 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
2026 mips_warn_about_macros
),
2027 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2030 /* We need a nop before loading from $gp. This special
2031 check is required because the lui which starts the main
2032 instruction stream does not refer to $gp, and so will not
2033 insert the nop which may be required. */
2034 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2037 macro_build (p
, counter
, ep
,
2038 mips_isa
< 3 ? "lw" : "ld",
2039 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2041 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2043 macro_build (p
, counter
, ep
,
2044 mips_isa
< 3 ? "addiu" : "daddiu",
2045 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2046 if (ex
.X_add_number
!= 0)
2048 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2049 as_bad ("PIC code offset overflow (max 16 signed bits)");
2050 ex
.X_op
= O_constant
;
2051 macro_build ((char *) NULL
, counter
, &ex
,
2052 mips_isa
< 3 ? "addiu" : "daddiu",
2053 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2056 else if (mips_pic
== EMBEDDED_PIC
)
2059 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2061 macro_build ((char *) NULL
, counter
, ep
,
2062 mips_isa
< 3 ? "addiu" : "daddiu",
2063 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2071 * This routine implements the seemingly endless macro or synthesized
2072 * instructions and addressing modes in the mips assembly language. Many
2073 * of these macros are simple and are similar to each other. These could
2074 * probably be handled by some kind of table or grammer aproach instead of
2075 * this verbose method. Others are not simple macros but are more like
2076 * optimizing code generation.
2077 * One interesting optimization is when several store macros appear
2078 * consecutivly that would load AT with the upper half of the same address.
2079 * The ensuing load upper instructions are ommited. This implies some kind
2080 * of global optimization. We currently only optimize within a single macro.
2081 * For many of the load and store macros if the address is specified as a
2082 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
2083 * first load register 'at' with zero and use it as the base register. The
2084 * mips assembler simply uses register $zero. Just one tiny optimization
2089 struct mips_cl_insn
*ip
;
2091 register int treg
, sreg
, dreg
, breg
;
2106 bfd_reloc_code_real_type r
;
2108 int hold_mips_optimize
;
2110 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
2111 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
2112 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
2113 mask
= ip
->insn_mo
->mask
;
2115 expr1
.X_op
= O_constant
;
2116 expr1
.X_op_symbol
= NULL
;
2117 expr1
.X_add_symbol
= NULL
;
2118 expr1
.X_add_number
= 1;
2130 mips_emit_delays ();
2132 mips_any_noreorder
= 1;
2134 expr1
.X_add_number
= 8;
2135 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
2137 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2139 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
2140 macro_build ((char *) NULL
, &icnt
, NULL
,
2141 dbl
? "dsub" : "sub",
2142 "d,v,t", dreg
, 0, sreg
);
2165 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2167 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
2168 (int) BFD_RELOC_LO16
);
2171 load_register (&icnt
, AT
, &imm_expr
, dbl
);
2172 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
2191 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
2193 if (mask
!= M_NOR_I
)
2194 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
2195 sreg
, (int) BFD_RELOC_LO16
);
2198 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
2199 treg
, sreg
, (int) BFD_RELOC_LO16
);
2200 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
2206 load_register (&icnt
, AT
, &imm_expr
, 0);
2207 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
2224 if (imm_expr
.X_add_number
== 0)
2226 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
2230 load_register (&icnt
, AT
, &imm_expr
, 0);
2231 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
2239 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2240 likely
? "bgezl" : "bgez",
2246 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2247 likely
? "blezl" : "blez",
2251 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2252 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2253 likely
? "beql" : "beq",
2260 /* check for > max integer */
2261 maxnum
= 0x7fffffff;
2269 if (imm_expr
.X_add_number
>= maxnum
2270 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2273 /* result is always false */
2276 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
2277 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2281 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
2282 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
2287 imm_expr
.X_add_number
++;
2291 if (mask
== M_BGEL_I
)
2293 if (imm_expr
.X_add_number
== 0)
2295 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2296 likely
? "bgezl" : "bgez",
2300 if (imm_expr
.X_add_number
== 1)
2302 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2303 likely
? "bgtzl" : "bgtz",
2307 maxnum
= 0x7fffffff;
2315 maxnum
= - maxnum
- 1;
2316 if (imm_expr
.X_add_number
<= maxnum
2317 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2320 /* result is always true */
2321 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
2322 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2325 set_at (&icnt
, sreg
, 0);
2326 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2327 likely
? "beql" : "beq",
2338 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2339 likely
? "beql" : "beq",
2343 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2345 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2346 likely
? "beql" : "beq",
2353 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2355 imm_expr
.X_add_number
++;
2359 if (mask
== M_BGEUL_I
)
2361 if (imm_expr
.X_add_number
== 0)
2363 if (imm_expr
.X_add_number
== 1)
2365 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2366 likely
? "bnel" : "bne",
2370 set_at (&icnt
, sreg
, 1);
2371 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2372 likely
? "beql" : "beq",
2381 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2382 likely
? "bgtzl" : "bgtz",
2388 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2389 likely
? "bltzl" : "bltz",
2393 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2394 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2395 likely
? "bnel" : "bne",
2404 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2405 likely
? "bnel" : "bne",
2411 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2413 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2414 likely
? "bnel" : "bne",
2423 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2424 likely
? "blezl" : "blez",
2430 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2431 likely
? "bgezl" : "bgez",
2435 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2436 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2437 likely
? "beql" : "beq",
2444 maxnum
= 0x7fffffff;
2452 if (imm_expr
.X_add_number
>= maxnum
2453 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2455 imm_expr
.X_add_number
++;
2459 if (mask
== M_BLTL_I
)
2461 if (imm_expr
.X_add_number
== 0)
2463 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2464 likely
? "bltzl" : "bltz",
2468 if (imm_expr
.X_add_number
== 1)
2470 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2471 likely
? "blezl" : "blez",
2475 set_at (&icnt
, sreg
, 0);
2476 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2477 likely
? "bnel" : "bne",
2486 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2487 likely
? "beql" : "beq",
2493 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2495 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2496 likely
? "beql" : "beq",
2503 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2505 imm_expr
.X_add_number
++;
2509 if (mask
== M_BLTUL_I
)
2511 if (imm_expr
.X_add_number
== 0)
2513 if (imm_expr
.X_add_number
== 1)
2515 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2516 likely
? "beql" : "beq",
2520 set_at (&icnt
, sreg
, 1);
2521 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2522 likely
? "bnel" : "bne",
2531 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2532 likely
? "bltzl" : "bltz",
2538 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2539 likely
? "bgtzl" : "bgtz",
2543 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2544 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2545 likely
? "bnel" : "bne",
2556 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2557 likely
? "bnel" : "bne",
2561 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2563 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2564 likely
? "bnel" : "bne",
2580 as_warn ("Divide by zero.");
2582 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2584 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2588 mips_emit_delays ();
2590 mips_any_noreorder
= 1;
2591 macro_build ((char *) NULL
, &icnt
, NULL
,
2592 dbl
? "ddiv" : "div",
2593 "z,s,t", sreg
, treg
);
2595 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2598 expr1
.X_add_number
= 8;
2599 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2600 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2601 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2603 expr1
.X_add_number
= -1;
2604 macro_build ((char *) NULL
, &icnt
, &expr1
,
2605 dbl
? "daddiu" : "addiu",
2606 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
2607 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
2608 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
2611 expr1
.X_add_number
= 1;
2612 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
2613 (int) BFD_RELOC_LO16
);
2614 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
2619 expr1
.X_add_number
= 0x80000000;
2620 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
2621 (int) BFD_RELOC_HI16
);
2624 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
2627 expr1
.X_add_number
= 8;
2628 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
2629 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2630 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
2633 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
2672 if (imm_expr
.X_add_number
== 0)
2674 as_warn ("Divide by zero.");
2676 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2678 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2681 if (imm_expr
.X_add_number
== 1)
2683 if (strcmp (s2
, "mflo") == 0)
2684 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
2687 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2690 if (imm_expr
.X_add_number
== -1
2691 && s
[strlen (s
) - 1] != 'u')
2693 if (strcmp (s2
, "mflo") == 0)
2696 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
2699 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
2703 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2707 load_register (&icnt
, AT
, &imm_expr
, dbl
);
2708 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
2709 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2728 mips_emit_delays ();
2730 mips_any_noreorder
= 1;
2731 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
2733 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2736 expr1
.X_add_number
= 8;
2737 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2738 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2739 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2742 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2748 /* Load the address of a symbol into a register. If breg is not
2749 zero, we then add a base register to it. */
2751 /* When generating embedded PIC code, we permit expressions of
2754 where bar is an address in the .text section. These are used
2755 when getting the addresses of functions. We don't permit
2756 X_add_number to be non-zero, because if the symbol is
2757 external the relaxing code needs to know that any addend is
2758 purely the offset to X_op_symbol. */
2759 if (mips_pic
== EMBEDDED_PIC
2760 && offset_expr
.X_op
== O_subtract
2761 && now_seg
== text_section
2762 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
2763 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
2764 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
2765 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
2766 ->sy_value
.X_add_symbol
)
2769 && offset_expr
.X_add_number
== 0)
2771 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
2772 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
2773 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2774 mips_isa
< 3 ? "addiu" : "daddiu",
2775 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
2779 if (offset_expr
.X_op
!= O_symbol
2780 && offset_expr
.X_op
!= O_constant
)
2782 as_bad ("expression too complex");
2783 offset_expr
.X_op
= O_constant
;
2797 if (offset_expr
.X_op
== O_constant
)
2798 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
2799 else if (mips_pic
== NO_PIC
)
2801 /* If this is a reference to an GP relative symbol, we want
2802 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2804 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2805 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2806 If we have a constant, we need two instructions anyhow,
2807 so we may as well always use the latter form. */
2808 if (offset_expr
.X_add_number
!= 0
2809 || nopic_need_relax (offset_expr
.X_add_symbol
))
2814 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2815 mips_isa
< 3 ? "addiu" : "daddiu",
2816 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2817 p
= frag_var (rs_machine_dependent
, 8, 0,
2818 RELAX_ENCODE (4, 8, 0, 4, 0,
2819 mips_warn_about_macros
),
2820 offset_expr
.X_add_symbol
, (long) 0,
2823 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2826 macro_build (p
, &icnt
, &offset_expr
,
2827 mips_isa
< 3 ? "addiu" : "daddiu",
2828 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2830 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
2832 /* If this is a reference to an external symbol, and there
2833 is no constant, we want
2834 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2835 For a local symbol, we want
2836 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2838 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2840 If we have a small constant, and this is a reference to
2841 an external symbol, we want
2842 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2844 addiu $tempreg,$tempreg,<constant>
2845 For a local symbol, we want the same instruction
2846 sequence, but we output a BFD_RELOC_LO16 reloc on the
2849 If we have a large constant, and this is a reference to
2850 an external symbol, we want
2851 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2852 lui $at,<hiconstant>
2853 addiu $at,$at,<loconstant>
2854 addu $tempreg,$tempreg,$at
2855 For a local symbol, we want the same instruction
2856 sequence, but we output a BFD_RELOC_LO16 reloc on the
2857 addiu instruction. */
2858 expr1
.X_add_number
= offset_expr
.X_add_number
;
2859 offset_expr
.X_add_number
= 0;
2861 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2863 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2864 if (expr1
.X_add_number
== 0)
2872 /* We're going to put in an addu instruction using
2873 tempreg, so we may as well insert the nop right
2875 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2879 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
2880 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
2882 ? mips_warn_about_macros
2884 offset_expr
.X_add_symbol
, (long) 0,
2888 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
2891 macro_build (p
, &icnt
, &expr1
,
2892 mips_isa
< 3 ? "addiu" : "daddiu",
2893 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2894 /* FIXME: If breg == 0, and the next instruction uses
2895 $tempreg, then if this variant case is used an extra
2896 nop will be generated. */
2898 else if (expr1
.X_add_number
>= -0x8000
2899 && expr1
.X_add_number
< 0x8000)
2901 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2903 macro_build ((char *) NULL
, &icnt
, &expr1
,
2904 mips_isa
< 3 ? "addiu" : "daddiu",
2905 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2906 (void) frag_var (rs_machine_dependent
, 0, 0,
2907 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
2908 offset_expr
.X_add_symbol
, (long) 0,
2915 /* If we are going to add in a base register, and the
2916 target register and the base register are the same,
2917 then we are using AT as a temporary register. Since
2918 we want to load the constant into AT, we add our
2919 current AT (from the global offset table) and the
2920 register into the register now, and pretend we were
2921 not using a base register. */
2926 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2928 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2929 mips_isa
< 3 ? "addu" : "daddu",
2930 "d,v,t", treg
, AT
, breg
);
2936 /* Set mips_optimize around the lui instruction to avoid
2937 inserting an unnecessary nop after the lw. */
2938 hold_mips_optimize
= mips_optimize
;
2940 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
2941 mips_optimize
= hold_mips_optimize
;
2943 macro_build ((char *) NULL
, &icnt
, &expr1
,
2944 mips_isa
< 3 ? "addiu" : "daddiu",
2945 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
2946 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2947 mips_isa
< 3 ? "addu" : "daddu",
2948 "d,v,t", tempreg
, tempreg
, AT
);
2949 (void) frag_var (rs_machine_dependent
, 0, 0,
2950 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
2951 offset_expr
.X_add_symbol
, (long) 0,
2956 else if (mips_pic
== SVR4_PIC
)
2960 /* This is the large GOT case. If this is a reference to an
2961 external symbol, and there is no constant, we want
2962 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
2963 addu $tempreg,$tempreg,$gp
2964 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
2965 For a local symbol, we want
2966 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2968 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2970 If we have a small constant, and this is a reference to
2971 an external symbol, we want
2972 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
2973 addu $tempreg,$tempreg,$gp
2974 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
2976 addiu $tempreg,$tempreg,<constant>
2977 For a local symbol, we want
2978 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2980 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
2982 If we have a large constant, and this is a reference to
2983 an external symbol, we want
2984 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
2985 addu $tempreg,$tempreg,$gp
2986 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
2987 lui $at,<hiconstant>
2988 addiu $at,$at,<loconstant>
2989 addu $tempreg,$tempreg,$at
2990 For a local symbol, we want
2991 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2992 lui $at,<hiconstant>
2993 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
2994 addu $tempreg,$tempreg,$at
2996 expr1
.X_add_number
= offset_expr
.X_add_number
;
2997 offset_expr
.X_add_number
= 0;
2999 if (reg_needs_delay (GP
))
3003 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3004 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
3005 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3006 mips_isa
< 3 ? "addu" : "daddu",
3007 "d,v,t", tempreg
, tempreg
, GP
);
3008 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3010 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
3012 if (expr1
.X_add_number
== 0)
3020 /* We're going to put in an addu instruction using
3021 tempreg, so we may as well insert the nop right
3023 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3028 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3029 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
3032 ? mips_warn_about_macros
3034 offset_expr
.X_add_symbol
, (long) 0,
3037 else if (expr1
.X_add_number
>= -0x8000
3038 && expr1
.X_add_number
< 0x8000)
3040 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3042 macro_build ((char *) NULL
, &icnt
, &expr1
,
3043 mips_isa
< 3 ? "addiu" : "daddiu",
3044 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3046 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3047 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
3049 ? mips_warn_about_macros
3051 offset_expr
.X_add_symbol
, (long) 0,
3058 /* If we are going to add in a base register, and the
3059 target register and the base register are the same,
3060 then we are using AT as a temporary register. Since
3061 we want to load the constant into AT, we add our
3062 current AT (from the global offset table) and the
3063 register into the register now, and pretend we were
3064 not using a base register. */
3072 assert (tempreg
== AT
);
3073 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3075 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3076 mips_isa
< 3 ? "addu" : "daddu",
3077 "d,v,t", treg
, AT
, breg
);
3082 /* Set mips_optimize around the lui instruction to avoid
3083 inserting an unnecessary nop after the lw. */
3084 hold_mips_optimize
= mips_optimize
;
3086 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
3087 mips_optimize
= hold_mips_optimize
;
3089 macro_build ((char *) NULL
, &icnt
, &expr1
,
3090 mips_isa
< 3 ? "addiu" : "daddiu",
3091 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3092 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3093 mips_isa
< 3 ? "addu" : "daddu",
3094 "d,v,t", dreg
, dreg
, AT
);
3096 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
3097 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
3100 ? mips_warn_about_macros
3102 offset_expr
.X_add_symbol
, (long) 0,
3110 /* This is needed because this instruction uses $gp, but
3111 the first instruction on the main stream does not. */
3112 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3115 macro_build (p
, &icnt
, &offset_expr
,
3117 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3119 if (expr1
.X_add_number
>= -0x8000
3120 && expr1
.X_add_number
< 0x8000)
3122 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3124 macro_build (p
, &icnt
, &expr1
,
3125 mips_isa
< 3 ? "addiu" : "daddiu",
3126 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3127 /* FIXME: If add_number is 0, and there was no base
3128 register, the external symbol case ended with a load,
3129 so if the symbol turns out to not be external, and
3130 the next instruction uses tempreg, an unnecessary nop
3131 will be inserted. */
3137 /* We must add in the base register now, as in the
3138 external symbol case. */
3139 assert (tempreg
== AT
);
3140 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3142 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3143 mips_isa
< 3 ? "addu" : "daddu",
3144 "d,v,t", treg
, AT
, breg
);
3147 /* We set breg to 0 because we have arranged to add
3148 it in in both cases. */
3152 macro_build_lui (p
, &icnt
, &expr1
, AT
);
3154 macro_build (p
, &icnt
, &expr1
,
3155 mips_isa
< 3 ? "addiu" : "daddiu",
3156 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3158 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3159 mips_isa
< 3 ? "addu" : "daddu",
3160 "d,v,t", tempreg
, tempreg
, AT
);
3164 else if (mips_pic
== EMBEDDED_PIC
)
3167 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3169 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3170 mips_isa
< 3 ? "addiu" : "daddiu",
3171 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3177 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3178 mips_isa
< 3 ? "addu" : "daddu",
3179 "d,v,t", treg
, tempreg
, breg
);
3187 /* The j instruction may not be used in PIC code, since it
3188 requires an absolute address. We convert it to a b
3190 if (mips_pic
== NO_PIC
)
3191 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
3193 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3196 /* The jal instructions must be handled as macros because when
3197 generating PIC code they expand to multi-instruction
3198 sequences. Normally they are simple instructions. */
3203 if (mips_pic
== NO_PIC
3204 || mips_pic
== EMBEDDED_PIC
)
3205 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
3207 else if (mips_pic
== SVR4_PIC
)
3209 if (sreg
!= PIC_CALL_REG
)
3210 as_warn ("MIPS PIC call to register other than $25");
3212 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
3214 if (mips_cprestore_offset
< 0)
3215 as_warn ("No .cprestore pseudo-op used in PIC code");
3218 expr1
.X_add_number
= mips_cprestore_offset
;
3219 macro_build ((char *) NULL
, &icnt
, &expr1
,
3220 mips_isa
< 3 ? "lw" : "ld",
3221 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
3230 if (mips_pic
== NO_PIC
)
3231 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
3232 else if (mips_pic
== SVR4_PIC
)
3234 /* If this is a reference to an external symbol, and we are
3235 using a small GOT, we want
3236 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
3240 lw $gp,cprestore($sp)
3241 The cprestore value is set using the .cprestore
3242 pseudo-op. If we are using a big GOT, we want
3243 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
3245 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
3249 lw $gp,cprestore($sp)
3250 If the symbol is not external, we want
3251 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3253 addiu $25,$25,<sym> (BFD_RELOC_LO16)
3256 lw $gp,cprestore($sp) */
3260 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3261 mips_isa
< 3 ? "lw" : "ld",
3262 "t,o(b)", PIC_CALL_REG
,
3263 (int) BFD_RELOC_MIPS_CALL16
, GP
);
3264 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3266 p
= frag_var (rs_machine_dependent
, 4, 0,
3267 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
3268 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
3274 if (reg_needs_delay (GP
))
3278 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3279 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
3280 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3281 mips_isa
< 3 ? "addu" : "daddu",
3282 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
3283 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3284 mips_isa
< 3 ? "lw" : "ld",
3285 "t,o(b)", PIC_CALL_REG
,
3286 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
3287 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3289 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3290 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
3292 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
3295 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3298 macro_build (p
, &icnt
, &offset_expr
,
3299 mips_isa
< 3 ? "lw" : "ld",
3300 "t,o(b)", PIC_CALL_REG
,
3301 (int) BFD_RELOC_MIPS_GOT16
, GP
);
3303 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3306 macro_build (p
, &icnt
, &offset_expr
,
3307 mips_isa
< 3 ? "addiu" : "daddiu",
3308 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
3309 (int) BFD_RELOC_LO16
);
3310 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3311 "jalr", "s", PIC_CALL_REG
);
3312 if (mips_cprestore_offset
< 0)
3313 as_warn ("No .cprestore pseudo-op used in PIC code");
3317 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3319 expr1
.X_add_number
= mips_cprestore_offset
;
3320 macro_build ((char *) NULL
, &icnt
, &expr1
,
3321 mips_isa
< 3 ? "lw" : "ld",
3322 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
3326 else if (mips_pic
== EMBEDDED_PIC
)
3328 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
3329 /* The linker may expand the call to a longer sequence which
3330 uses $at, so we must break rather than return. */
3406 if (breg
== treg
|| coproc
|| lr
)
3475 if (mask
== M_LWC1_AB
3476 || mask
== M_SWC1_AB
3477 || mask
== M_LDC1_AB
3478 || mask
== M_SDC1_AB
3487 if (offset_expr
.X_op
!= O_constant
3488 && offset_expr
.X_op
!= O_symbol
)
3490 as_bad ("expression too complex");
3491 offset_expr
.X_op
= O_constant
;
3494 /* A constant expression in PIC code can be handled just as it
3495 is in non PIC code. */
3496 if (mips_pic
== NO_PIC
3497 || offset_expr
.X_op
== O_constant
)
3499 /* If this is a reference to a GP relative symbol, and there
3500 is no base register, we want
3501 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3502 Otherwise, if there is no base register, we want
3503 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3504 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
3505 If we have a constant, we need two instructions anyhow,
3506 so we always use the latter form.
3508 If we have a base register, and this is a reference to a
3509 GP relative symbol, we want
3510 addu $tempreg,$breg,$gp
3511 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3513 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3514 addu $tempreg,$tempreg,$breg
3515 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
3516 With a constant we always use the latter case. */
3519 if (offset_expr
.X_add_number
!= 0
3520 || nopic_need_relax (offset_expr
.X_add_symbol
))
3525 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3526 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3527 p
= frag_var (rs_machine_dependent
, 8, 0,
3528 RELAX_ENCODE (4, 8, 0, 4, 0,
3529 (mips_warn_about_macros
3530 || (used_at
&& mips_noat
))),
3531 offset_expr
.X_add_symbol
, (long) 0,
3535 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3538 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
3539 (int) BFD_RELOC_LO16
, tempreg
);
3543 if (offset_expr
.X_add_number
!= 0
3544 || nopic_need_relax (offset_expr
.X_add_symbol
))
3549 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3550 mips_isa
< 3 ? "addu" : "daddu",
3551 "d,v,t", tempreg
, breg
, GP
);
3552 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3553 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3554 p
= frag_var (rs_machine_dependent
, 12, 0,
3555 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
3556 offset_expr
.X_add_symbol
, (long) 0,
3559 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3562 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3563 mips_isa
< 3 ? "addu" : "daddu",
3564 "d,v,t", tempreg
, tempreg
, breg
);
3567 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
3568 (int) BFD_RELOC_LO16
, tempreg
);
3571 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3573 /* If this is a reference to an external symbol, we want
3574 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3576 <op> $treg,0($tempreg)
3578 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3580 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3581 <op> $treg,0($tempreg)
3582 If there is a base register, we add it to $tempreg before
3583 the <op>. If there is a constant, we stick it in the
3584 <op> instruction. We don't handle constants larger than
3585 16 bits, because we have no way to load the upper 16 bits
3586 (actually, we could handle them for the subset of cases
3587 in which we are not using $at). */
3588 assert (offset_expr
.X_op
== O_symbol
);
3589 expr1
.X_add_number
= offset_expr
.X_add_number
;
3590 offset_expr
.X_add_number
= 0;
3591 if (expr1
.X_add_number
< -0x8000
3592 || expr1
.X_add_number
>= 0x8000)
3593 as_bad ("PIC code offset overflow (max 16 signed bits)");
3595 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3596 mips_isa
< 3 ? "lw" : "ld",
3597 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3598 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3599 p
= frag_var (rs_machine_dependent
, 4, 0,
3600 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
3601 offset_expr
.X_add_symbol
, (long) 0,
3603 macro_build (p
, &icnt
, &offset_expr
,
3604 mips_isa
< 3 ? "addiu" : "daddiu",
3605 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3607 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3608 mips_isa
< 3 ? "addu" : "daddu",
3609 "d,v,t", tempreg
, tempreg
, breg
);
3610 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
3611 (int) BFD_RELOC_LO16
, tempreg
);
3613 else if (mips_pic
== SVR4_PIC
)
3617 /* If this is a reference to an external symbol, we want
3618 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3619 addu $tempreg,$tempreg,$gp
3620 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3621 <op> $treg,0($tempreg)
3623 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3625 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3626 <op> $treg,0($tempreg)
3627 If there is a base register, we add it to $tempreg before
3628 the <op>. If there is a constant, we stick it in the
3629 <op> instruction. We don't handle constants larger than
3630 16 bits, because we have no way to load the upper 16 bits
3631 (actually, we could handle them for the subset of cases
3632 in which we are not using $at). */
3633 assert (offset_expr
.X_op
== O_symbol
);
3634 expr1
.X_add_number
= offset_expr
.X_add_number
;
3635 offset_expr
.X_add_number
= 0;
3636 if (expr1
.X_add_number
< -0x8000
3637 || expr1
.X_add_number
>= 0x8000)
3638 as_bad ("PIC code offset overflow (max 16 signed bits)");
3639 if (reg_needs_delay (GP
))
3644 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3645 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
3646 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3647 mips_isa
< 3 ? "addu" : "daddu",
3648 "d,v,t", tempreg
, tempreg
, GP
);
3649 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3650 mips_isa
< 3 ? "lw" : "ld",
3651 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
);
3652 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3653 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
3654 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
3657 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3660 macro_build (p
, &icnt
, &offset_expr
,
3661 mips_isa
< 3 ? "lw" : "ld",
3662 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
);
3664 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3666 macro_build (p
, &icnt
, &offset_expr
,
3667 mips_isa
< 3 ? "addiu" : "daddiu",
3668 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3670 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3671 mips_isa
< 3 ? "addu" : "daddu",
3672 "d,v,t", tempreg
, tempreg
, breg
);
3673 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
3674 (int) BFD_RELOC_LO16
, tempreg
);
3676 else if (mips_pic
== EMBEDDED_PIC
)
3678 /* If there is no base register, we want
3679 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3680 If there is a base register, we want
3681 addu $tempreg,$breg,$gp
3682 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3684 assert (offset_expr
.X_op
== O_symbol
);
3687 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3688 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3693 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3694 mips_isa
< 3 ? "addu" : "daddu",
3695 "d,v,t", tempreg
, breg
, GP
);
3696 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3697 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3710 load_register (&icnt
, treg
, &imm_expr
, 0);
3714 load_register (&icnt
, treg
, &imm_expr
, 1);
3718 if (imm_expr
.X_op
== O_constant
)
3720 load_register (&icnt
, AT
, &imm_expr
, 0);
3721 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3722 "mtc1", "t,G", AT
, treg
);
3727 assert (offset_expr
.X_op
== O_symbol
3728 && strcmp (segment_name (S_GET_SEGMENT
3729 (offset_expr
.X_add_symbol
)),
3731 && offset_expr
.X_add_number
== 0);
3732 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3733 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3738 /* We know that sym is in the .rdata section. First we get the
3739 upper 16 bits of the address. */
3740 if (mips_pic
== NO_PIC
)
3742 /* FIXME: This won't work for a 64 bit address. */
3743 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3745 else if (mips_pic
== SVR4_PIC
)
3747 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3748 mips_isa
< 3 ? "lw" : "ld",
3749 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3751 else if (mips_pic
== EMBEDDED_PIC
)
3753 /* For embedded PIC we pick up the entire address off $gp in
3754 a single instruction. */
3755 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3756 mips_isa
< 3 ? "addiu" : "daddiu",
3757 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3758 offset_expr
.X_op
= O_constant
;
3759 offset_expr
.X_add_number
= 0;
3764 /* Now we load the register(s). */
3766 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
3767 treg
, (int) BFD_RELOC_LO16
, AT
);
3770 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3771 treg
, (int) BFD_RELOC_LO16
, AT
);
3774 /* FIXME: How in the world do we deal with the possible
3776 offset_expr
.X_add_number
+= 4;
3777 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3778 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
3782 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3783 does not become a variant frag. */
3784 frag_wane (frag_now
);
3790 assert (offset_expr
.X_op
== O_symbol
3791 && offset_expr
.X_add_number
== 0);
3792 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
3793 if (strcmp (s
, ".lit8") == 0)
3797 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3798 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3802 r
= BFD_RELOC_MIPS_LITERAL
;
3807 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
3808 if (mips_pic
== SVR4_PIC
)
3809 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3810 mips_isa
< 3 ? "lw" : "ld",
3811 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3814 /* FIXME: This won't work for a 64 bit address. */
3815 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3820 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3821 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
3823 /* To avoid confusion in tc_gen_reloc, we must ensure
3824 that this does not become a variant frag. */
3825 frag_wane (frag_now
);
3836 /* Even on a big endian machine $fn comes before $fn+1. We have
3837 to adjust when loading from memory. */
3840 assert (mips_isa
< 2);
3841 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3842 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3844 /* FIXME: A possible overflow which I don't know how to deal
3846 offset_expr
.X_add_number
+= 4;
3847 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3848 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3851 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3852 does not become a variant frag. */
3853 frag_wane (frag_now
);
3862 * The MIPS assembler seems to check for X_add_number not
3863 * being double aligned and generating:
3866 * addiu at,at,%lo(foo+1)
3869 * But, the resulting address is the same after relocation so why
3870 * generate the extra instruction?
3917 if (offset_expr
.X_op
!= O_symbol
3918 && offset_expr
.X_op
!= O_constant
)
3920 as_bad ("expression too complex");
3921 offset_expr
.X_op
= O_constant
;
3924 /* Even on a big endian machine $fn comes before $fn+1. We have
3925 to adjust when loading from memory. We set coproc if we must
3926 load $fn+1 first. */
3927 if (byte_order
== LITTLE_ENDIAN
)
3930 if (mips_pic
== NO_PIC
3931 || offset_expr
.X_op
== O_constant
)
3933 /* If this is a reference to a GP relative symbol, we want
3934 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3935 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
3936 If we have a base register, we use this
3938 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
3939 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
3940 If this is not a GP relative symbol, we want
3941 lui $at,<sym> (BFD_RELOC_HI16_S)
3942 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
3943 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
3944 If there is a base register, we add it to $at after the
3945 lui instruction. If there is a constant, we always use
3947 if (offset_expr
.X_add_number
!= 0
3948 || nopic_need_relax (offset_expr
.X_add_symbol
))
3967 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3968 mips_isa
< 3 ? "addu" : "daddu",
3969 "d,v,t", AT
, breg
, GP
);
3975 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3976 coproc
? treg
+ 1 : treg
,
3977 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3978 offset_expr
.X_add_number
+= 4;
3980 /* Set mips_optimize to 2 to avoid inserting an
3982 hold_mips_optimize
= mips_optimize
;
3984 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3985 coproc
? treg
: treg
+ 1,
3986 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3987 mips_optimize
= hold_mips_optimize
;
3989 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3990 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
3991 used_at
&& mips_noat
),
3992 offset_expr
.X_add_symbol
, (long) 0,
3995 /* We just generated two relocs. When tc_gen_reloc
3996 handles this case, it will skip the first reloc and
3997 handle the second. The second reloc already has an
3998 extra addend of 4, which we added above. We must
3999 subtract it out, and then subtract another 4 to make
4000 the first reloc come out right. The second reloc
4001 will come out right because we are going to add 4 to
4002 offset_expr when we build its instruction below. */
4003 offset_expr
.X_add_number
-= 8;
4004 offset_expr
.X_op
= O_constant
;
4006 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
4011 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4012 mips_isa
< 3 ? "addu" : "daddu",
4013 "d,v,t", AT
, breg
, AT
);
4017 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4018 coproc
? treg
+ 1 : treg
,
4019 (int) BFD_RELOC_LO16
, AT
);
4022 /* FIXME: How do we handle overflow here? */
4023 offset_expr
.X_add_number
+= 4;
4024 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4025 coproc
? treg
: treg
+ 1,
4026 (int) BFD_RELOC_LO16
, AT
);
4028 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4032 /* If this is a reference to an external symbol, we want
4033 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4038 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4040 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4041 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4042 If there is a base register we add it to $at before the
4043 lwc1 instructions. If there is a constant we include it
4044 in the lwc1 instructions. */
4046 expr1
.X_add_number
= offset_expr
.X_add_number
;
4047 offset_expr
.X_add_number
= 0;
4048 if (expr1
.X_add_number
< -0x8000
4049 || expr1
.X_add_number
>= 0x8000 - 4)
4050 as_bad ("PIC code offset overflow (max 16 signed bits)");
4055 frag_grow (24 + off
);
4056 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4057 mips_isa
< 3 ? "lw" : "ld",
4058 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4059 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4061 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4062 mips_isa
< 3 ? "addu" : "daddu",
4063 "d,v,t", AT
, breg
, AT
);
4064 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4065 coproc
? treg
+ 1 : treg
,
4066 (int) BFD_RELOC_LO16
, AT
);
4067 expr1
.X_add_number
+= 4;
4069 /* Set mips_optimize to 2 to avoid inserting an undesired
4071 hold_mips_optimize
= mips_optimize
;
4073 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4074 coproc
? treg
: treg
+ 1,
4075 (int) BFD_RELOC_LO16
, AT
);
4076 mips_optimize
= hold_mips_optimize
;
4078 (void) frag_var (rs_machine_dependent
, 0, 0,
4079 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
4080 offset_expr
.X_add_symbol
, (long) 0,
4083 else if (mips_pic
== SVR4_PIC
)
4087 /* If this is a reference to an external symbol, we want
4088 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4090 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
4095 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4097 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4098 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4099 If there is a base register we add it to $at before the
4100 lwc1 instructions. If there is a constant we include it
4101 in the lwc1 instructions. */
4103 expr1
.X_add_number
= offset_expr
.X_add_number
;
4104 offset_expr
.X_add_number
= 0;
4105 if (expr1
.X_add_number
< -0x8000
4106 || expr1
.X_add_number
>= 0x8000 - 4)
4107 as_bad ("PIC code offset overflow (max 16 signed bits)");
4108 if (reg_needs_delay (GP
))
4117 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4118 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4119 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4120 mips_isa
< 3 ? "addu" : "daddu",
4121 "d,v,t", AT
, AT
, GP
);
4122 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4123 mips_isa
< 3 ? "lw" : "ld",
4124 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
4125 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4127 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4128 mips_isa
< 3 ? "addu" : "daddu",
4129 "d,v,t", AT
, breg
, AT
);
4130 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4131 coproc
? treg
+ 1 : treg
,
4132 (int) BFD_RELOC_LO16
, AT
);
4133 expr1
.X_add_number
+= 4;
4135 /* Set mips_optimize to 2 to avoid inserting an undesired
4137 hold_mips_optimize
= mips_optimize
;
4139 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4140 coproc
? treg
: treg
+ 1,
4141 (int) BFD_RELOC_LO16
, AT
);
4142 mips_optimize
= hold_mips_optimize
;
4143 expr1
.X_add_number
-= 4;
4145 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
4146 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
4147 8 + gpdel
+ off
, 1, 0),
4148 offset_expr
.X_add_symbol
, (long) 0,
4152 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4155 macro_build (p
, &icnt
, &offset_expr
,
4156 mips_isa
< 3 ? "lw" : "ld",
4157 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4159 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4163 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4164 mips_isa
< 3 ? "addu" : "daddu",
4165 "d,v,t", AT
, breg
, AT
);
4168 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
4169 coproc
? treg
+ 1 : treg
,
4170 (int) BFD_RELOC_LO16
, AT
);
4172 expr1
.X_add_number
+= 4;
4174 /* Set mips_optimize to 2 to avoid inserting an undesired
4176 hold_mips_optimize
= mips_optimize
;
4178 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
4179 coproc
? treg
: treg
+ 1,
4180 (int) BFD_RELOC_LO16
, AT
);
4181 mips_optimize
= hold_mips_optimize
;
4183 else if (mips_pic
== EMBEDDED_PIC
)
4185 /* If there is no base register, we use
4186 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4187 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
4188 If we have a base register, we use
4190 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
4191 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
4200 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4201 mips_isa
< 3 ? "addu" : "daddu",
4202 "d,v,t", AT
, breg
, GP
);
4207 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4208 coproc
? treg
+ 1 : treg
,
4209 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4210 offset_expr
.X_add_number
+= 4;
4211 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4212 coproc
? treg
: treg
+ 1,
4213 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4229 assert (mips_isa
< 3);
4230 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4231 (int) BFD_RELOC_LO16
, breg
);
4232 offset_expr
.X_add_number
+= 4;
4233 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
4234 (int) BFD_RELOC_LO16
, breg
);
4236 #ifdef LOSING_COMPILER
4242 as_warn ("Macro used $at after \".set noat\"");
4247 struct mips_cl_insn
*ip
;
4249 register int treg
, sreg
, dreg
, breg
;
4264 bfd_reloc_code_real_type r
;
4267 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4268 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4269 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4270 mask
= ip
->insn_mo
->mask
;
4272 expr1
.X_op
= O_constant
;
4273 expr1
.X_op_symbol
= NULL
;
4274 expr1
.X_add_symbol
= NULL
;
4275 expr1
.X_add_number
= 1;
4279 #endif /* LOSING_COMPILER */
4284 macro_build ((char *) NULL
, &icnt
, NULL
,
4285 dbl
? "dmultu" : "multu",
4287 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4293 /* The MIPS assembler some times generates shifts and adds. I'm
4294 not trying to be that fancy. GCC should do this for us
4296 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4297 macro_build ((char *) NULL
, &icnt
, NULL
,
4298 dbl
? "dmult" : "mult",
4300 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4306 mips_emit_delays ();
4308 mips_any_noreorder
= 1;
4309 macro_build ((char *) NULL
, &icnt
, NULL
,
4310 dbl
? "dmult" : "mult",
4312 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4313 macro_build ((char *) NULL
, &icnt
, NULL
,
4314 dbl
? "dsra32" : "sra",
4315 "d,w,<", dreg
, dreg
, 31);
4316 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
4318 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
4321 expr1
.X_add_number
= 8;
4322 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
4323 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
4324 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4327 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4333 mips_emit_delays ();
4335 mips_any_noreorder
= 1;
4336 macro_build ((char *) NULL
, &icnt
, NULL
,
4337 dbl
? "dmultu" : "multu",
4339 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
4340 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4342 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
4345 expr1
.X_add_number
= 8;
4346 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
4347 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
4348 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4354 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
4355 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
4356 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
4358 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4362 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
4363 imm_expr
.X_add_number
& 0x1f);
4364 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
4365 (0 - imm_expr
.X_add_number
) & 0x1f);
4366 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4370 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
4371 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
4372 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
4374 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4378 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
4379 imm_expr
.X_add_number
& 0x1f);
4380 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
4381 (0 - imm_expr
.X_add_number
) & 0x1f);
4382 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4386 assert (mips_isa
< 2);
4387 /* Even on a big endian machine $fn comes before $fn+1. We have
4388 to adjust when storing to memory. */
4389 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
4390 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
4391 (int) BFD_RELOC_LO16
, breg
);
4392 offset_expr
.X_add_number
+= 4;
4393 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
4394 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
4395 (int) BFD_RELOC_LO16
, breg
);
4400 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4401 treg
, (int) BFD_RELOC_LO16
);
4403 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4404 sreg
, (int) BFD_RELOC_LO16
);
4407 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4409 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4410 dreg
, (int) BFD_RELOC_LO16
);
4415 if (imm_expr
.X_add_number
== 0)
4417 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4418 sreg
, (int) BFD_RELOC_LO16
);
4423 as_warn ("Instruction %s: result is always false",
4425 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4428 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
4430 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
4431 sreg
, (int) BFD_RELOC_LO16
);
4434 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
4436 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4437 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4438 mips_isa
< 3 ? "addiu" : "daddiu",
4439 "t,r,j", dreg
, sreg
,
4440 (int) BFD_RELOC_LO16
);
4445 load_register (&icnt
, AT
, &imm_expr
, 0);
4446 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4450 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
4451 (int) BFD_RELOC_LO16
);
4456 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
4462 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
4463 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4464 (int) BFD_RELOC_LO16
);
4467 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
4469 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
4471 macro_build ((char *) NULL
, &icnt
, &expr1
,
4472 mask
== M_SGE_I
? "slti" : "sltiu",
4473 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4478 load_register (&icnt
, AT
, &imm_expr
, 0);
4479 macro_build ((char *) NULL
, &icnt
, NULL
,
4480 mask
== M_SGE_I
? "slt" : "sltu",
4481 "d,v,t", dreg
, sreg
, AT
);
4484 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4485 (int) BFD_RELOC_LO16
);
4490 case M_SGT
: /* sreg > treg <==> treg < sreg */
4496 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
4499 case M_SGT_I
: /* sreg > I <==> I < sreg */
4505 load_register (&icnt
, AT
, &imm_expr
, 0);
4506 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
4509 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
4515 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
4516 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4517 (int) BFD_RELOC_LO16
);
4520 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
4526 load_register (&icnt
, AT
, &imm_expr
, 0);
4527 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
4528 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4529 (int) BFD_RELOC_LO16
);
4533 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
4535 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
4536 dreg
, sreg
, (int) BFD_RELOC_LO16
);
4539 load_register (&icnt
, AT
, &imm_expr
, 0);
4540 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
4544 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
4546 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
4547 dreg
, sreg
, (int) BFD_RELOC_LO16
);
4550 load_register (&icnt
, AT
, &imm_expr
, 0);
4551 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
4557 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4560 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4564 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4566 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4572 if (imm_expr
.X_add_number
== 0)
4574 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4580 as_warn ("Instruction %s: result is always true",
4582 macro_build ((char *) NULL
, &icnt
, &expr1
,
4583 mips_isa
< 3 ? "addiu" : "daddiu",
4584 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
4587 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
4589 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
4590 dreg
, sreg
, (int) BFD_RELOC_LO16
);
4593 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
4595 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4596 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4597 mips_isa
< 3 ? "addiu" : "daddiu",
4598 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4603 load_register (&icnt
, AT
, &imm_expr
, 0);
4604 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4608 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
4616 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
4618 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4619 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4620 dbl
? "daddi" : "addi",
4621 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4624 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4625 macro_build ((char *) NULL
, &icnt
, NULL
,
4626 dbl
? "dsub" : "sub",
4627 "d,v,t", dreg
, sreg
, AT
);
4633 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
4635 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4636 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4637 dbl
? "daddiu" : "addiu",
4638 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4641 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4642 macro_build ((char *) NULL
, &icnt
, NULL
,
4643 dbl
? "dsubu" : "subu",
4644 "d,v,t", dreg
, sreg
, AT
);
4665 load_register (&icnt
, AT
, &imm_expr
, 0);
4666 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
4671 assert (mips_isa
< 2);
4672 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
4673 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
4676 * Is the double cfc1 instruction a bug in the mips assembler;
4677 * or is there a reason for it?
4679 mips_emit_delays ();
4681 mips_any_noreorder
= 1;
4682 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
4683 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
4684 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4685 expr1
.X_add_number
= 3;
4686 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
4687 (int) BFD_RELOC_LO16
);
4688 expr1
.X_add_number
= 2;
4689 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
4690 (int) BFD_RELOC_LO16
);
4691 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
4692 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4693 macro_build ((char *) NULL
, &icnt
, NULL
,
4694 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
4695 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
4696 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4706 if (offset_expr
.X_add_number
>= 0x7fff)
4707 as_bad ("operand overflow");
4708 /* avoid load delay */
4709 if (byte_order
== LITTLE_ENDIAN
)
4710 offset_expr
.X_add_number
+= 1;
4711 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4712 (int) BFD_RELOC_LO16
, breg
);
4713 if (byte_order
== LITTLE_ENDIAN
)
4714 offset_expr
.X_add_number
-= 1;
4716 offset_expr
.X_add_number
+= 1;
4717 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
4718 (int) BFD_RELOC_LO16
, breg
);
4719 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
4720 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
4733 if (offset_expr
.X_add_number
>= 0x8000 - off
)
4734 as_bad ("operand overflow");
4735 if (byte_order
== LITTLE_ENDIAN
)
4736 offset_expr
.X_add_number
+= off
;
4737 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4738 (int) BFD_RELOC_LO16
, breg
);
4739 if (byte_order
== LITTLE_ENDIAN
)
4740 offset_expr
.X_add_number
-= off
;
4742 offset_expr
.X_add_number
+= off
;
4743 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
4744 (int) BFD_RELOC_LO16
, breg
);
4757 load_address (&icnt
, AT
, &offset_expr
);
4759 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4760 mips_isa
< 3 ? "addu" : "daddu",
4761 "d,v,t", AT
, AT
, breg
);
4762 if (byte_order
== LITTLE_ENDIAN
)
4763 expr1
.X_add_number
= off
;
4765 expr1
.X_add_number
= 0;
4766 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
4767 (int) BFD_RELOC_LO16
, AT
);
4768 if (byte_order
== LITTLE_ENDIAN
)
4769 expr1
.X_add_number
= 0;
4771 expr1
.X_add_number
= off
;
4772 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
4773 (int) BFD_RELOC_LO16
, AT
);
4778 load_address (&icnt
, AT
, &offset_expr
);
4780 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4781 mips_isa
< 3 ? "addu" : "daddu",
4782 "d,v,t", AT
, AT
, breg
);
4783 if (byte_order
== BIG_ENDIAN
)
4784 expr1
.X_add_number
= 0;
4785 macro_build ((char *) NULL
, &icnt
, &expr1
,
4786 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
4787 (int) BFD_RELOC_LO16
, AT
);
4788 if (byte_order
== BIG_ENDIAN
)
4789 expr1
.X_add_number
= 1;
4791 expr1
.X_add_number
= 0;
4792 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
4793 (int) BFD_RELOC_LO16
, AT
);
4794 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
4796 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
4801 if (offset_expr
.X_add_number
>= 0x7fff)
4802 as_bad ("operand overflow");
4803 if (byte_order
== BIG_ENDIAN
)
4804 offset_expr
.X_add_number
+= 1;
4805 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
4806 (int) BFD_RELOC_LO16
, breg
);
4807 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
4808 if (byte_order
== BIG_ENDIAN
)
4809 offset_expr
.X_add_number
-= 1;
4811 offset_expr
.X_add_number
+= 1;
4812 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
4813 (int) BFD_RELOC_LO16
, breg
);
4826 if (offset_expr
.X_add_number
>= 0x8000 - off
)
4827 as_bad ("operand overflow");
4828 if (byte_order
== LITTLE_ENDIAN
)
4829 offset_expr
.X_add_number
+= off
;
4830 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4831 (int) BFD_RELOC_LO16
, breg
);
4832 if (byte_order
== LITTLE_ENDIAN
)
4833 offset_expr
.X_add_number
-= off
;
4835 offset_expr
.X_add_number
+= off
;
4836 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
4837 (int) BFD_RELOC_LO16
, breg
);
4850 load_address (&icnt
, AT
, &offset_expr
);
4852 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4853 mips_isa
< 3 ? "addu" : "daddu",
4854 "d,v,t", AT
, AT
, breg
);
4855 if (byte_order
== LITTLE_ENDIAN
)
4856 expr1
.X_add_number
= off
;
4858 expr1
.X_add_number
= 0;
4859 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
4860 (int) BFD_RELOC_LO16
, AT
);
4861 if (byte_order
== LITTLE_ENDIAN
)
4862 expr1
.X_add_number
= 0;
4864 expr1
.X_add_number
= off
;
4865 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
4866 (int) BFD_RELOC_LO16
, AT
);
4870 load_address (&icnt
, AT
, &offset_expr
);
4872 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4873 mips_isa
< 3 ? "addu" : "daddu",
4874 "d,v,t", AT
, AT
, breg
);
4875 if (byte_order
== LITTLE_ENDIAN
)
4876 expr1
.X_add_number
= 0;
4877 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
4878 (int) BFD_RELOC_LO16
, AT
);
4879 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
4881 if (byte_order
== LITTLE_ENDIAN
)
4882 expr1
.X_add_number
= 1;
4884 expr1
.X_add_number
= 0;
4885 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
4886 (int) BFD_RELOC_LO16
, AT
);
4887 if (byte_order
== LITTLE_ENDIAN
)
4888 expr1
.X_add_number
= 0;
4890 expr1
.X_add_number
= 1;
4891 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
4892 (int) BFD_RELOC_LO16
, AT
);
4893 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
4895 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
4900 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
4904 as_warn ("Macro used $at after \".set noat\"");
4909 This routine assembles an instruction into its binary format. As a side
4910 effect it sets one of the global variables imm_reloc or offset_reloc to the
4911 type of relocation to do if one of the operands is an address expression.
4916 struct mips_cl_insn
*ip
;
4921 struct mips_opcode
*insn
;
4924 unsigned int lastregno
= 0;
4929 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '6' || *s
== '.'; ++s
)
4941 as_fatal ("Unknown opcode: `%s'", str
);
4943 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
4945 as_warn ("`%s' not in hash table.", str
);
4946 insn_error
= "ERROR: Unrecognized opcode";
4954 assert (strcmp (insn
->name
, str
) == 0);
4956 if (insn
->pinfo
== INSN_MACRO
)
4957 insn_isa
= insn
->match
;
4958 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA2
)
4960 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA3
)
4962 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA4
)
4967 if (insn_isa
> mips_isa
4968 || ((insn
->pinfo
& INSN_ISA
) == INSN_4650
4970 || ((insn
->pinfo
& INSN_ISA
) == INSN_4010
4972 || ((insn
->pinfo
& INSN_ISA
) == INSN_4100
4975 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
4976 && strcmp (insn
->name
, insn
[1].name
) == 0)
4981 as_warn ("Instruction not supported on this processor");
4985 ip
->insn_opcode
= insn
->match
;
4986 for (args
= insn
->args
;; ++args
)
4992 case '\0': /* end of args */
5005 ip
->insn_opcode
|= lastregno
<< 21;
5010 ip
->insn_opcode
|= lastregno
<< 16;
5014 ip
->insn_opcode
|= lastregno
<< 11;
5020 /* handle optional base register.
5021 Either the base register is omitted or
5022 we must have a left paren. */
5023 /* this is dependent on the next operand specifier
5024 is a 'b' for base register */
5025 assert (args
[1] == 'b');
5029 case ')': /* these must match exactly */
5034 case '<': /* must be at least one digit */
5036 * According to the manual, if the shift amount is greater
5037 * than 31 or less than 0 the the shift amount should be
5038 * mod 32. In reality the mips assembler issues an error.
5039 * We issue a warning and mask out all but the low 5 bits.
5041 my_getExpression (&imm_expr
, s
);
5042 check_absolute_expr (ip
, &imm_expr
);
5043 if ((unsigned long) imm_expr
.X_add_number
> 31)
5045 as_warn ("Improper shift amount (%ld)",
5046 (long) imm_expr
.X_add_number
);
5047 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
5049 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
5050 imm_expr
.X_op
= O_absent
;
5054 case '>': /* shift amount minus 32 */
5055 my_getExpression (&imm_expr
, s
);
5056 check_absolute_expr (ip
, &imm_expr
);
5057 if ((unsigned long) imm_expr
.X_add_number
< 32
5058 || (unsigned long) imm_expr
.X_add_number
> 63)
5060 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
5061 imm_expr
.X_op
= O_absent
;
5065 case 'k': /* cache code */
5066 case 'h': /* prefx code */
5067 my_getExpression (&imm_expr
, s
);
5068 check_absolute_expr (ip
, &imm_expr
);
5069 if ((unsigned long) imm_expr
.X_add_number
> 31)
5071 as_warn ("Invalid value for `%s' (%lu)",
5073 (unsigned long) imm_expr
.X_add_number
);
5074 imm_expr
.X_add_number
&= 0x1f;
5077 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
5079 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
5080 imm_expr
.X_op
= O_absent
;
5084 case 'c': /* break code */
5085 my_getExpression (&imm_expr
, s
);
5086 check_absolute_expr (ip
, &imm_expr
);
5087 if ((unsigned) imm_expr
.X_add_number
> 1023)
5088 as_warn ("Illegal break code (%ld)",
5089 (long) imm_expr
.X_add_number
);
5090 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
5091 imm_expr
.X_op
= O_absent
;
5095 case 'B': /* syscall code */
5096 my_getExpression (&imm_expr
, s
);
5097 check_absolute_expr (ip
, &imm_expr
);
5098 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
5099 as_warn ("Illegal syscall code (%ld)",
5100 (long) imm_expr
.X_add_number
);
5101 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
5102 imm_expr
.X_op
= O_absent
;
5106 case 'C': /* Coprocessor code */
5107 my_getExpression (&imm_expr
, s
);
5108 check_absolute_expr (ip
, &imm_expr
);
5109 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
5111 as_warn ("Coproccesor code > 25 bits (%ld)",
5112 (long) imm_expr
.X_add_number
);
5113 imm_expr
.X_add_number
&= ((1<<25) - 1);
5115 ip
->insn_opcode
|= imm_expr
.X_add_number
;
5116 imm_expr
.X_op
= O_absent
;
5120 case 'b': /* base register */
5121 case 'd': /* destination register */
5122 case 's': /* source register */
5123 case 't': /* target register */
5124 case 'r': /* both target and source */
5125 case 'v': /* both dest and source */
5126 case 'w': /* both dest and target */
5127 case 'E': /* coprocessor target register */
5128 case 'G': /* coprocessor destination register */
5129 case 'x': /* ignore register name */
5130 case 'z': /* must be zero register */
5144 while (isdigit (*s
));
5146 as_bad ("Invalid register number (%d)", regno
);
5148 else if (*args
== 'E' || *args
== 'G')
5152 if (s
[1] == 'f' && s
[2] == 'p')
5157 else if (s
[1] == 's' && s
[2] == 'p')
5162 else if (s
[1] == 'g' && s
[2] == 'p')
5167 else if (s
[1] == 'a' && s
[2] == 't')
5172 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
5177 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
5185 if (regno
== AT
&& ! mips_noat
)
5186 as_warn ("Used $at without \".set noat\"");
5192 if (c
== 'r' || c
== 'v' || c
== 'w')
5199 /* 'z' only matches $0. */
5200 if (c
== 'z' && regno
!= 0)
5208 ip
->insn_opcode
|= regno
<< 21;
5212 ip
->insn_opcode
|= regno
<< 11;
5217 ip
->insn_opcode
|= regno
<< 16;
5220 /* This case exists because on the r3000 trunc
5221 expands into a macro which requires a gp
5222 register. On the r6000 or r4000 it is
5223 assembled into a single instruction which
5224 ignores the register. Thus the insn version
5225 is MIPS_ISA2 and uses 'x', and the macro
5226 version is MIPS_ISA1 and uses 't'. */
5229 /* This case is for the div instruction, which
5230 acts differently if the destination argument
5231 is $0. This only matches $0, and is checked
5232 outside the switch. */
5243 ip
->insn_opcode
|= lastregno
<< 21;
5246 ip
->insn_opcode
|= lastregno
<< 16;
5251 case 'D': /* floating point destination register */
5252 case 'S': /* floating point source register */
5253 case 'T': /* floating point target register */
5254 case 'R': /* floating point source register */
5258 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
5268 while (isdigit (*s
));
5271 as_bad ("Invalid float register number (%d)", regno
);
5273 if ((regno
& 1) != 0
5275 && ! (strcmp (str
, "mtc1") == 0 ||
5276 strcmp (str
, "mfc1") == 0 ||
5277 strcmp (str
, "lwc1") == 0 ||
5278 strcmp (str
, "swc1") == 0))
5279 as_warn ("Float register should be even, was %d",
5287 if (c
== 'V' || c
== 'W')
5297 ip
->insn_opcode
|= regno
<< 6;
5301 ip
->insn_opcode
|= regno
<< 11;
5305 ip
->insn_opcode
|= regno
<< 16;
5308 ip
->insn_opcode
|= regno
<< 21;
5317 ip
->insn_opcode
|= lastregno
<< 11;
5320 ip
->insn_opcode
|= lastregno
<< 16;
5326 my_getExpression (&imm_expr
, s
);
5327 if (imm_expr
.X_op
!= O_big
)
5328 check_absolute_expr (ip
, &imm_expr
);
5333 my_getExpression (&offset_expr
, s
);
5334 imm_reloc
= BFD_RELOC_32
;
5346 unsigned char temp
[8];
5348 unsigned int length
;
5353 /* These only appear as the last operand in an
5354 instruction, and every instruction that accepts
5355 them in any variant accepts them in all variants.
5356 This means we don't have to worry about backing out
5357 any changes if the instruction does not match.
5359 The difference between them is the size of the
5360 floating point constant and where it goes. For 'F'
5361 and 'L' the constant is 64 bits; for 'f' and 'l' it
5362 is 32 bits. Where the constant is placed is based
5363 on how the MIPS assembler does things:
5366 f -- immediate value
5369 The .lit4 and .lit8 sections are only used if
5370 permitted by the -G argument.
5372 When generating embedded PIC code, we use the
5373 .lit8 section but not the .lit4 section (we can do
5374 .lit4 inline easily; we need to put .lit8
5375 somewhere in the data segment, and using .lit8
5376 permits the linker to eventually combine identical
5379 f64
= *args
== 'F' || *args
== 'L';
5381 save_in
= input_line_pointer
;
5382 input_line_pointer
= s
;
5383 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
5385 s
= input_line_pointer
;
5386 input_line_pointer
= save_in
;
5387 if (err
!= NULL
&& *err
!= '\0')
5389 as_bad ("Bad floating point constant: %s", err
);
5390 memset (temp
, '\0', sizeof temp
);
5391 length
= f64
? 8 : 4;
5394 assert (length
== (f64
? 8 : 4));
5398 && (! USE_GLOBAL_POINTER_OPT
5399 || mips_pic
== EMBEDDED_PIC
5400 || g_switch_value
< 4)
5403 imm_expr
.X_op
= O_constant
;
5404 if (byte_order
== LITTLE_ENDIAN
)
5405 imm_expr
.X_add_number
=
5406 (((((((int) temp
[3] << 8)
5411 imm_expr
.X_add_number
=
5412 (((((((int) temp
[0] << 8)
5419 const char *newname
;
5422 /* Switch to the right section. */
5424 subseg
= now_subseg
;
5427 default: /* unused default case avoids warnings. */
5429 newname
= RDATA_SECTION_NAME
;
5430 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
5434 newname
= RDATA_SECTION_NAME
;
5437 assert (!USE_GLOBAL_POINTER_OPT
5438 || g_switch_value
>= 4);
5442 new_seg
= subseg_new (newname
, (subsegT
) 0);
5443 frag_align (*args
== 'l' ? 2 : 3, 0);
5444 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
5445 record_alignment (new_seg
, 4);
5447 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
5449 as_bad ("Can't use floating point insn in this section");
5451 /* Set the argument to the current address in the
5453 offset_expr
.X_op
= O_symbol
;
5454 offset_expr
.X_add_symbol
=
5455 symbol_new ("L0\001", now_seg
,
5456 (valueT
) frag_now_fix (), frag_now
);
5457 offset_expr
.X_add_number
= 0;
5459 /* Put the floating point number into the section. */
5460 p
= frag_more ((int) length
);
5461 memcpy (p
, temp
, length
);
5463 /* Switch back to the original section. */
5464 subseg_set (seg
, subseg
);
5469 case 'i': /* 16 bit unsigned immediate */
5470 case 'j': /* 16 bit signed immediate */
5471 imm_reloc
= BFD_RELOC_LO16
;
5472 c
= my_getSmallExpression (&imm_expr
, s
);
5477 if (imm_expr
.X_op
== O_constant
)
5478 imm_expr
.X_add_number
=
5479 (imm_expr
.X_add_number
>> 16) & 0xffff;
5481 imm_reloc
= BFD_RELOC_HI16_S
;
5483 imm_reloc
= BFD_RELOC_HI16
;
5486 else if (imm_expr
.X_op
!= O_big
)
5487 check_absolute_expr (ip
, &imm_expr
);
5490 if (imm_expr
.X_op
== O_big
5491 || imm_expr
.X_add_number
< 0
5492 || imm_expr
.X_add_number
>= 0x10000)
5494 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
5495 !strcmp (insn
->name
, insn
[1].name
))
5497 as_bad ("16 bit expression not in range 0..65535");
5505 /* The upper bound should be 0x8000, but
5506 unfortunately the MIPS assembler accepts numbers
5507 from 0x8000 to 0xffff and sign extends them, and
5508 we want to be compatible. We only permit this
5509 extended range for an instruction which does not
5510 provide any further alternates, since those
5511 alternates may handle other cases. People should
5512 use the numbers they mean, rather than relying on
5513 a mysterious sign extension. */
5514 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
5515 strcmp (insn
->name
, insn
[1].name
) == 0);
5520 if (imm_expr
.X_op
== O_big
5521 || imm_expr
.X_add_number
< -0x8000
5522 || imm_expr
.X_add_number
>= max
5524 && imm_expr
.X_add_number
< 0
5526 && imm_expr
.X_unsigned
5527 && sizeof (imm_expr
.X_add_number
) <= 4))
5531 as_bad ("16 bit expression not in range -32768..32767");
5537 case 'o': /* 16 bit offset */
5538 c
= my_getSmallExpression (&offset_expr
, s
);
5540 /* If this value won't fit into a 16 bit offset, then go
5541 find a macro that will generate the 32 bit offset
5542 code pattern. As a special hack, we accept the
5543 difference of two local symbols as a constant. This
5544 is required to suppose embedded PIC switches, which
5545 use an instruction which looks like
5546 lw $4,$L12-$LS12($4)
5547 The problem with handling this in a more general
5548 fashion is that the macro function doesn't expect to
5549 see anything which can be handled in a single
5550 constant instruction. */
5552 && (offset_expr
.X_op
!= O_constant
5553 || offset_expr
.X_add_number
>= 0x8000
5554 || offset_expr
.X_add_number
< -0x8000)
5555 && (mips_pic
!= EMBEDDED_PIC
5556 || offset_expr
.X_op
!= O_subtract
5557 || now_seg
!= text_section
5558 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
5562 offset_reloc
= BFD_RELOC_LO16
;
5563 if (c
== 'h' || c
== 'H')
5565 assert (offset_expr
.X_op
== O_constant
);
5566 offset_expr
.X_add_number
=
5567 (offset_expr
.X_add_number
>> 16) & 0xffff;
5572 case 'p': /* pc relative offset */
5573 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
5574 my_getExpression (&offset_expr
, s
);
5578 case 'u': /* upper 16 bits */
5579 c
= my_getSmallExpression (&imm_expr
, s
);
5580 if (imm_expr
.X_op
== O_constant
5581 && (imm_expr
.X_add_number
< 0
5582 || imm_expr
.X_add_number
>= 0x10000))
5583 as_bad ("lui expression not in range 0..65535");
5584 imm_reloc
= BFD_RELOC_LO16
;
5589 if (imm_expr
.X_op
== O_constant
)
5590 imm_expr
.X_add_number
=
5591 (imm_expr
.X_add_number
>> 16) & 0xffff;
5593 imm_reloc
= BFD_RELOC_HI16_S
;
5595 imm_reloc
= BFD_RELOC_HI16
;
5601 case 'a': /* 26 bit address */
5602 my_getExpression (&offset_expr
, s
);
5604 offset_reloc
= BFD_RELOC_MIPS_JMP
;
5607 case 'N': /* 3 bit branch condition code */
5608 case 'M': /* 3 bit compare condition code */
5609 my_getExpression (&imm_expr
, s
);
5610 check_absolute_expr (ip
, &imm_expr
);
5611 if ((unsigned long) imm_expr
.X_add_number
> 7)
5613 as_warn ("Condition code > 7 (%ld)",
5614 (long) imm_expr
.X_add_number
);
5615 imm_expr
.X_add_number
&= 7;
5618 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_BCC
;
5620 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CCC
;
5621 imm_expr
.X_op
= O_absent
;
5626 fprintf (stderr
, "bad char = '%c'\n", *args
);
5631 /* Args don't match. */
5632 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
5633 !strcmp (insn
->name
, insn
[1].name
))
5639 insn_error
= "ERROR: Illegal operands";
5648 my_getSmallExpression (ep
, str
)
5659 ((str
[1] == 'h' && str
[2] == 'i')
5660 || (str
[1] == 'H' && str
[2] == 'I')
5661 || (str
[1] == 'l' && str
[2] == 'o'))
5673 * A small expression may be followed by a base register.
5674 * Scan to the end of this operand, and then back over a possible
5675 * base register. Then scan the small expression up to that
5676 * point. (Based on code in sparc.c...)
5678 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
5680 if (sp
- 4 >= str
&& sp
[-1] == RP
)
5682 if (isdigit (sp
[-2]))
5684 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
5686 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
5692 else if (sp
- 5 >= str
5695 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
5696 || (sp
[-3] == 's' && sp
[-2] == 'p')
5697 || (sp
[-3] == 'g' && sp
[-2] == 'p')
5698 || (sp
[-3] == 'a' && sp
[-2] == 't')))
5704 /* no expression means zero offset */
5707 /* %xx(reg) is an error */
5708 ep
->X_op
= O_absent
;
5713 ep
->X_op
= O_constant
;
5716 ep
->X_add_symbol
= NULL
;
5717 ep
->X_op_symbol
= NULL
;
5718 ep
->X_add_number
= 0;
5723 my_getExpression (ep
, str
);
5730 my_getExpression (ep
, str
);
5731 return c
; /* => %hi or %lo encountered */
5735 my_getExpression (ep
, str
)
5741 save_in
= input_line_pointer
;
5742 input_line_pointer
= str
;
5744 expr_end
= input_line_pointer
;
5745 input_line_pointer
= save_in
;
5748 /* Turn a string in input_line_pointer into a floating point constant
5749 of type type, and store the appropriate bytes in *litP. The number
5750 of LITTLENUMS emitted is stored in *sizeP . An error message is
5751 returned, or NULL on OK. */
5754 md_atof (type
, litP
, sizeP
)
5760 LITTLENUM_TYPE words
[4];
5776 return "bad call to md_atof";
5779 t
= atof_ieee (input_line_pointer
, type
, words
);
5781 input_line_pointer
= t
;
5785 if (byte_order
== LITTLE_ENDIAN
)
5787 for (i
= prec
- 1; i
>= 0; i
--)
5789 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
5795 for (i
= 0; i
< prec
; i
++)
5797 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
5806 md_number_to_chars (buf
, val
, n
)
5814 number_to_chars_littleendian (buf
, val
, n
);
5818 number_to_chars_bigendian (buf
, val
, n
);
5826 CONST
char *md_shortopts
= "O::g::G:";
5828 struct option md_longopts
[] = {
5829 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
5830 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
5831 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
5832 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
5833 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
5834 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
5835 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
5836 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
5837 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
5838 #define OPTION_MCPU (OPTION_MD_BASE + 5)
5839 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
5840 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
5841 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
5842 #define OPTION_TRAP (OPTION_MD_BASE + 9)
5843 {"trap", no_argument
, NULL
, OPTION_TRAP
},
5844 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
5845 #define OPTION_BREAK (OPTION_MD_BASE + 10)
5846 {"break", no_argument
, NULL
, OPTION_BREAK
},
5847 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
5848 #define OPTION_EB (OPTION_MD_BASE + 11)
5849 {"EB", no_argument
, NULL
, OPTION_EB
},
5850 #define OPTION_EL (OPTION_MD_BASE + 12)
5851 {"EL", no_argument
, NULL
, OPTION_EL
},
5852 #define OPTION_M4650 (OPTION_MD_BASE + 13)
5853 {"m4650", no_argument
, NULL
, OPTION_M4650
},
5854 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
5855 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
5856 #define OPTION_M4010 (OPTION_MD_BASE + 15)
5857 {"m4010", no_argument
, NULL
, OPTION_M4010
},
5858 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
5859 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
5860 #define OPTION_M4100 (OPTION_MD_BASE + 17)
5861 {"m4100", no_argument
, NULL
, OPTION_M4100
},
5862 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
5863 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
5865 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
5866 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
5867 #define OPTION_XGOT (OPTION_MD_BASE + 19)
5869 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
5870 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
5871 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
5872 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
5875 {NULL
, no_argument
, NULL
, 0}
5877 size_t md_longopts_size
= sizeof(md_longopts
);
5880 md_parse_option (c
, arg
)
5895 target_big_endian
= 1;
5899 target_big_endian
= 0;
5903 if (arg
&& arg
[1] == '0')
5913 mips_debug
= atoi (arg
);
5914 /* When the MIPS assembler sees -g or -g2, it does not do
5915 optimizations which limit full symbolic debugging. We take
5916 that to be equivalent to -O0. */
5917 if (mips_debug
== 2)
5949 /* Identify the processor type */
5951 if (strcmp (p
, "default") == 0
5952 || strcmp (p
, "DEFAULT") == 0)
5958 /* We need to cope with the various "vr" prefixes for the 4300
5960 if (*p
== 'v' || *p
== 'V')
5966 if (*p
== 'r' || *p
== 'R')
5973 if (strcmp (p
, "10000") == 0
5974 || strcmp (p
, "10k") == 0
5975 || strcmp (p
, "10K") == 0)
5980 if (strcmp (p
, "2000") == 0
5981 || strcmp (p
, "2k") == 0
5982 || strcmp (p
, "2K") == 0)
5987 if (strcmp (p
, "3000") == 0
5988 || strcmp (p
, "3k") == 0
5989 || strcmp (p
, "3K") == 0)
5994 if (strcmp (p
, "4000") == 0
5995 || strcmp (p
, "4k") == 0
5996 || strcmp (p
, "4K") == 0)
5998 else if (strcmp (p
, "4100") == 0)
6004 else if (strcmp (p
, "4300") == 0)
6006 else if (strcmp (p
, "4400") == 0)
6008 else if (strcmp (p
, "4600") == 0)
6010 else if (strcmp (p
, "4650") == 0)
6016 else if (strcmp (p
, "4010") == 0)
6025 if (strcmp (p
, "6000") == 0
6026 || strcmp (p
, "6k") == 0
6027 || strcmp (p
, "6K") == 0)
6032 if (strcmp (p
, "8000") == 0
6033 || strcmp (p
, "8k") == 0
6034 || strcmp (p
, "8K") == 0)
6039 if (strcmp (p
, "orion") == 0)
6044 if (sv
&& mips_cpu
!= 4300 && mips_cpu
!= 4100)
6046 as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg
);
6052 as_bad ("invalid architecture -mcpu=%s", arg
);
6063 case OPTION_NO_M4650
:
6071 case OPTION_NO_M4010
:
6079 case OPTION_NO_M4100
:
6083 case OPTION_MEMBEDDED_PIC
:
6084 mips_pic
= EMBEDDED_PIC
;
6085 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
6087 as_bad ("-G may not be used with embedded PIC code");
6090 g_switch_value
= 0x7fffffff;
6093 /* When generating ELF code, we permit -KPIC and -call_shared to
6094 select SVR4_PIC, and -non_shared to select no PIC. This is
6095 intended to be compatible with Irix 5. */
6096 case OPTION_CALL_SHARED
:
6097 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
6099 as_bad ("-call_shared is supported only for ELF format");
6102 mips_pic
= SVR4_PIC
;
6103 if (g_switch_seen
&& g_switch_value
!= 0)
6105 as_bad ("-G may not be used with SVR4 PIC code");
6111 case OPTION_NON_SHARED
:
6112 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
6114 as_bad ("-non_shared is supported only for ELF format");
6120 /* The -xgot option tells the assembler to use 32 offsets when
6121 accessing the got in SVR4_PIC mode. It is for Irix
6128 if (! USE_GLOBAL_POINTER_OPT
)
6130 as_bad ("-G is not supported for this configuration");
6133 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
6135 as_bad ("-G may not be used with SVR4 or embedded PIC code");
6139 g_switch_value
= atoi (arg
);
6151 md_show_usage (stream
)
6156 -membedded-pic generate embedded position independent code\n\
6157 -EB generate big endian output\n\
6158 -EL generate little endian output\n\
6159 -g, -g2 do not remove uneeded NOPs or swap branches\n\
6160 -G NUM allow referencing objects up to NUM bytes\n\
6161 implicitly with the gp register [default 8]\n");
6163 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
6164 -mips2, -mcpu=r6000 generate code for r6000\n\
6165 -mips3, -mcpu=r4000 generate code for r4000\n\
6166 -mips4, -mcpu=r8000 generate code for r8000\n\
6167 -mcpu=vr4300 generate code for vr4300\n\
6168 -mcpu=vr4100 generate code for vr4100\n\
6169 -m4650 permit R4650 instructions\n\
6170 -no-m4650 do not permit R4650 instructions\n\
6171 -m4010 permit R4010 instructions\n\
6172 -no-m4010 do not permit R4010 instructions\n\
6173 -m4100 permit VR4100 instructions\n\
6174 -no-m4100 do not permit VR4100 instructions\n");
6176 -O0 remove unneeded NOPs, do not swap branches\n\
6177 -O remove unneeded NOPs and swap branches\n\
6178 --trap, --no-break trap exception on div by 0 and mult overflow\n\
6179 --break, --no-trap break exception on div by 0 and mult overflow\n");
6182 -KPIC, -call_shared generate SVR4 position independent code\n\
6183 -non_shared do not generate position independent code\n\
6184 -xgot assume a 32 bit GOT\n");
6189 mips_init_after_args ()
6191 if (target_big_endian
)
6192 byte_order
= BIG_ENDIAN
;
6194 byte_order
= LITTLE_ENDIAN
;
6198 md_pcrel_from (fixP
)
6201 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
6202 && fixP
->fx_addsy
!= (symbolS
*) NULL
6203 && ! S_IS_DEFINED (fixP
->fx_addsy
))
6205 /* This makes a branch to an undefined symbol be a branch to the
6206 current location. */
6210 /* return the address of the delay slot */
6211 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6214 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
6215 reloc for a cons. We could use the definition there, except that
6216 we want to handle 64 bit relocs specially. */
6219 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
6222 unsigned int nbytes
;
6225 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
6227 FIXME: There is no way to select anything but 32 bit mode right
6231 if (byte_order
== BIG_ENDIAN
)
6236 if (nbytes
!= 2 && nbytes
!= 4)
6237 as_bad ("Unsupported reloc size %d", nbytes
);
6239 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
6240 nbytes
== 2 ? BFD_RELOC_16
: BFD_RELOC_32
);
6243 /* When generating embedded PIC code we need to use a special
6244 relocation to represent the difference of two symbols in the .text
6245 section (switch tables use a difference of this sort). See
6246 include/coff/mips.h for details. This macro checks whether this
6247 fixup requires the special reloc. */
6248 #define SWITCH_TABLE(fixp) \
6249 ((fixp)->fx_r_type == BFD_RELOC_32 \
6250 && (fixp)->fx_addsy != NULL \
6251 && (fixp)->fx_subsy != NULL \
6252 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
6253 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
6255 /* When generating embedded PIC code we must keep all PC relative
6256 relocations, in case the linker has to relax a call. We also need
6257 to keep relocations for switch table entries. */
6261 mips_force_relocation (fixp
)
6264 return (mips_pic
== EMBEDDED_PIC
6266 || SWITCH_TABLE (fixp
)
6267 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
6268 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
6271 /* Apply a fixup to the object file. */
6274 md_apply_fix (fixP
, valueP
)
6281 assert (fixP
->fx_size
== 4 || fixP
->fx_r_type
== BFD_RELOC_16
);
6284 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
6286 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
6289 switch (fixP
->fx_r_type
)
6291 case BFD_RELOC_MIPS_JMP
:
6292 case BFD_RELOC_HI16
:
6293 case BFD_RELOC_HI16_S
:
6294 case BFD_RELOC_MIPS_GPREL
:
6295 case BFD_RELOC_MIPS_LITERAL
:
6296 case BFD_RELOC_MIPS_CALL16
:
6297 case BFD_RELOC_MIPS_GOT16
:
6298 case BFD_RELOC_MIPS_GPREL32
:
6299 case BFD_RELOC_MIPS_GOT_HI16
:
6300 case BFD_RELOC_MIPS_GOT_LO16
:
6301 case BFD_RELOC_MIPS_CALL_HI16
:
6302 case BFD_RELOC_MIPS_CALL_LO16
:
6304 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6305 "Invalid PC relative reloc");
6306 /* Nothing needed to do. The value comes from the reloc entry */
6309 case BFD_RELOC_PCREL_HI16_S
:
6310 /* The addend for this is tricky if it is internal, so we just
6311 do everything here rather than in bfd_perform_relocation. */
6312 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
6314 /* For an external symbol adjust by the address to make it
6315 pcrel_offset. We use the address of the RELLO reloc
6316 which follows this one. */
6317 value
+= (fixP
->fx_next
->fx_frag
->fr_address
6318 + fixP
->fx_next
->fx_where
);
6323 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
6324 if (byte_order
== BIG_ENDIAN
)
6326 md_number_to_chars (buf
, value
, 2);
6329 case BFD_RELOC_PCREL_LO16
:
6330 /* The addend for this is tricky if it is internal, so we just
6331 do everything here rather than in bfd_perform_relocation. */
6332 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
6333 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
6334 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
6335 if (byte_order
== BIG_ENDIAN
)
6337 md_number_to_chars (buf
, value
, 2);
6341 /* If we are deleting this reloc entry, we must fill in the
6342 value now. This can happen if we have a .word which is not
6343 resolved when it appears but is later defined. We also need
6344 to fill in the value if this is an embedded PIC switch table
6347 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
6348 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
6353 /* If we are deleting this reloc entry, we must fill in the
6355 assert (fixP
->fx_size
== 2);
6357 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
6361 case BFD_RELOC_LO16
:
6362 /* When handling an embedded PIC switch statement, we can wind
6363 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
6366 if (value
< -0x8000 || value
> 0x7fff)
6367 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6368 "relocation overflow");
6369 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
6370 if (byte_order
== BIG_ENDIAN
)
6372 md_number_to_chars (buf
, value
, 2);
6376 case BFD_RELOC_16_PCREL_S2
:
6378 * We need to save the bits in the instruction since fixup_segment()
6379 * might be deleting the relocation entry (i.e., a branch within
6380 * the current segment).
6383 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
6384 "Branch to odd address (%lx)", value
);
6387 /* update old instruction data */
6388 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
6392 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
6396 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
6404 if (value
>= -0x8000 && value
< 0x8000)
6405 insn
|= value
& 0xffff;
6408 /* The branch offset is too large. If this is an
6409 unconditional branch, and we are not generating PIC code,
6410 we can convert it to an absolute jump instruction. */
6411 if (mips_pic
== NO_PIC
6413 && fixP
->fx_frag
->fr_address
>= text_section
->vma
6414 && (fixP
->fx_frag
->fr_address
6415 < text_section
->vma
+ text_section
->_raw_size
)
6416 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
6417 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
6418 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
6420 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
6421 insn
= 0x0c000000; /* jal */
6423 insn
= 0x08000000; /* j */
6424 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
6426 fixP
->fx_addsy
= section_symbol (text_section
);
6427 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
6431 /* FIXME. It would be possible in principle to handle
6432 conditional branches which overflow. They could be
6433 transformed into a branch around a jump. This would
6434 require setting up variant frags for each different
6435 branch type. The native MIPS assembler attempts to
6436 handle these cases, but it appears to do it
6438 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6439 "Relocation overflow");
6443 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
6458 const struct mips_opcode
*p
;
6459 int treg
, sreg
, dreg
, shamt
;
6464 for (i
= 0; i
< NUMOPCODES
; ++i
)
6466 p
= &mips_opcodes
[i
];
6467 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
6469 printf ("%08lx %s\t", oc
, p
->name
);
6470 treg
= (oc
>> 16) & 0x1f;
6471 sreg
= (oc
>> 21) & 0x1f;
6472 dreg
= (oc
>> 11) & 0x1f;
6473 shamt
= (oc
>> 6) & 0x1f;
6475 for (args
= p
->args
;; ++args
)
6486 printf ("%c", *args
);
6490 assert (treg
== sreg
);
6491 printf ("$%d,$%d", treg
, sreg
);
6496 printf ("$%d", dreg
);
6501 printf ("$%d", treg
);
6505 printf ("0x%x", treg
);
6510 printf ("$%d", sreg
);
6514 printf ("0x%08lx", oc
& 0x1ffffff);
6526 printf ("$%d", shamt
);
6537 printf ("%08lx UNDEFINED\n", oc
);
6548 name
= input_line_pointer
;
6549 c
= get_symbol_end ();
6550 p
= (symbolS
*) symbol_find_or_make (name
);
6551 *input_line_pointer
= c
;
6555 /* Align the current frag to a given power of two. The MIPS assembler
6556 also automatically adjusts any preceding label. */
6559 mips_align (to
, fill
, label
)
6564 mips_emit_delays ();
6565 frag_align (to
, fill
);
6566 record_alignment (now_seg
, to
);
6569 assert (S_GET_SEGMENT (label
) == now_seg
);
6570 label
->sy_frag
= frag_now
;
6571 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
6575 /* Align to a given power of two. .align 0 turns off the automatic
6576 alignment used by the data creating pseudo-ops. */
6583 register long temp_fill
;
6584 long max_alignment
= 15;
6588 o Note that the assembler pulls down any immediately preceeding label
6589 to the aligned address.
6590 o It's not documented but auto alignment is reinstated by
6591 a .align pseudo instruction.
6592 o Note also that after auto alignment is turned off the mips assembler
6593 issues an error on attempt to assemble an improperly aligned data item.
6598 temp
= get_absolute_expression ();
6599 if (temp
> max_alignment
)
6600 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
6603 as_warn ("Alignment negative: 0 assumed.");
6606 if (*input_line_pointer
== ',')
6608 input_line_pointer
++;
6609 temp_fill
= get_absolute_expression ();
6616 mips_align (temp
, (int) temp_fill
, insn_label
);
6623 demand_empty_rest_of_line ();
6627 mips_flush_pending_output ()
6629 mips_emit_delays ();
6639 /* When generating embedded PIC code, we only use the .text, .lit8,
6640 .sdata and .sbss sections. We change the .data and .rdata
6641 pseudo-ops to use .sdata. */
6642 if (mips_pic
== EMBEDDED_PIC
6643 && (sec
== 'd' || sec
== 'r'))
6646 mips_emit_delays ();
6656 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
6657 demand_empty_rest_of_line ();
6661 if (USE_GLOBAL_POINTER_OPT
)
6663 seg
= subseg_new (RDATA_SECTION_NAME
,
6664 (subsegT
) get_absolute_expression ());
6665 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6667 bfd_set_section_flags (stdoutput
, seg
,
6673 bfd_set_section_alignment (stdoutput
, seg
, 4);
6675 demand_empty_rest_of_line ();
6679 as_bad ("No read only data section in this object file format");
6680 demand_empty_rest_of_line ();
6686 if (USE_GLOBAL_POINTER_OPT
)
6688 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
6689 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6691 bfd_set_section_flags (stdoutput
, seg
,
6692 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
6694 bfd_set_section_alignment (stdoutput
, seg
, 4);
6696 demand_empty_rest_of_line ();
6701 as_bad ("Global pointers not supported; recompile -G 0");
6702 demand_empty_rest_of_line ();
6711 mips_enable_auto_align ()
6723 mips_emit_delays ();
6724 if (log_size
> 0 && auto_align
)
6725 mips_align (log_size
, 0, label
);
6727 cons (1 << log_size
);
6738 mips_emit_delays ();
6742 mips_align (3, 0, label
);
6744 mips_align (2, 0, label
);
6751 /* Handle .globl. We need to override it because on Irix 5 you are
6754 where foo is an undefined symbol, to mean that foo should be
6755 considered to be the address of a function. */
6766 name
= input_line_pointer
;
6767 c
= get_symbol_end ();
6768 symbolP
= symbol_find_or_make (name
);
6769 *input_line_pointer
= c
;
6772 /* On Irix 5, every global symbol that is not explicitly labelled as
6773 being a function is apparently labelled as being an object. */
6776 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6781 secname
= input_line_pointer
;
6782 c
= get_symbol_end ();
6783 sec
= bfd_get_section_by_name (stdoutput
, secname
);
6785 as_bad ("%s: no such section", secname
);
6786 *input_line_pointer
= c
;
6788 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
6789 flag
= BSF_FUNCTION
;
6792 symbolP
->bsym
->flags
|= flag
;
6794 S_SET_EXTERNAL (symbolP
);
6795 demand_empty_rest_of_line ();
6805 opt
= input_line_pointer
;
6806 c
= get_symbol_end ();
6810 /* FIXME: What does this mean? */
6812 else if (strncmp (opt
, "pic", 3) == 0)
6820 mips_pic
= SVR4_PIC
;
6822 as_bad (".option pic%d not supported", i
);
6824 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
6826 if (g_switch_seen
&& g_switch_value
!= 0)
6827 as_warn ("-G may not be used with SVR4 PIC code");
6829 bfd_set_gp_size (stdoutput
, 0);
6833 as_warn ("Unrecognized option \"%s\"", opt
);
6835 *input_line_pointer
= c
;
6836 demand_empty_rest_of_line ();
6843 char *name
= input_line_pointer
, ch
;
6845 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
6846 input_line_pointer
++;
6847 ch
= *input_line_pointer
;
6848 *input_line_pointer
= '\0';
6850 if (strcmp (name
, "reorder") == 0)
6854 prev_insn_unreordered
= 1;
6855 prev_prev_insn_unreordered
= 1;
6859 else if (strcmp (name
, "noreorder") == 0)
6861 mips_emit_delays ();
6863 mips_any_noreorder
= 1;
6865 else if (strcmp (name
, "at") == 0)
6869 else if (strcmp (name
, "noat") == 0)
6873 else if (strcmp (name
, "macro") == 0)
6875 mips_warn_about_macros
= 0;
6877 else if (strcmp (name
, "nomacro") == 0)
6879 if (mips_noreorder
== 0)
6880 as_bad ("`noreorder' must be set before `nomacro'");
6881 mips_warn_about_macros
= 1;
6883 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
6887 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
6891 else if (strcmp (name
, "bopt") == 0)
6895 else if (strcmp (name
, "nobopt") == 0)
6899 else if (strncmp (name
, "mips", 4) == 0)
6903 /* Permit the user to change the ISA on the fly. Needless to
6904 say, misuse can cause serious problems. */
6905 isa
= atoi (name
+ 4);
6907 mips_isa
= file_mips_isa
;
6908 else if (isa
< 1 || isa
> 4)
6909 as_bad ("unknown ISA level");
6915 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
6917 *input_line_pointer
= ch
;
6918 demand_empty_rest_of_line ();
6921 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
6922 .option pic2. It means to generate SVR4 PIC calls. */
6928 mips_pic
= SVR4_PIC
;
6929 if (USE_GLOBAL_POINTER_OPT
)
6931 if (g_switch_seen
&& g_switch_value
!= 0)
6932 as_warn ("-G may not be used with SVR4 PIC code");
6935 bfd_set_gp_size (stdoutput
, 0);
6936 demand_empty_rest_of_line ();
6939 /* Handle the .cpload pseudo-op. This is used when generating SVR4
6940 PIC code. It sets the $gp register for the function based on the
6941 function address, which is in the register named in the argument.
6942 This uses a relocation against _gp_disp, which is handled specially
6943 by the linker. The result is:
6944 lui $gp,%hi(_gp_disp)
6945 addiu $gp,$gp,%lo(_gp_disp)
6946 addu $gp,$gp,.cpload argument
6947 The .cpload argument is normally $25 == $t9. */
6956 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
6957 if (mips_pic
!= SVR4_PIC
)
6963 /* .cpload should be a in .set noreorder section. */
6964 if (mips_noreorder
== 0)
6965 as_warn (".cpload not in noreorder section");
6968 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
6969 ex
.X_op_symbol
= NULL
;
6970 ex
.X_add_number
= 0;
6972 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
6973 ex
.X_add_symbol
->bsym
->flags
|= BSF_OBJECT
;
6975 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
6976 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
6977 (int) BFD_RELOC_LO16
);
6979 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
6980 GP
, GP
, tc_get_register (0));
6982 demand_empty_rest_of_line ();
6985 /* Handle the .cprestore pseudo-op. This stores $gp into a given
6986 offset from $sp. The offset is remembered, and after making a PIC
6987 call $gp is restored from that location. */
6990 s_cprestore (ignore
)
6996 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
6997 if (mips_pic
!= SVR4_PIC
)
7003 mips_cprestore_offset
= get_absolute_expression ();
7005 ex
.X_op
= O_constant
;
7006 ex
.X_add_symbol
= NULL
;
7007 ex
.X_op_symbol
= NULL
;
7008 ex
.X_add_number
= mips_cprestore_offset
;
7010 macro_build ((char *) NULL
, &icnt
, &ex
,
7011 mips_isa
< 3 ? "sw" : "sd",
7012 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
7014 demand_empty_rest_of_line ();
7017 /* Handle the .gpword pseudo-op. This is used when generating PIC
7018 code. It generates a 32 bit GP relative reloc. */
7028 /* When not generating PIC code, this is treated as .word. */
7029 if (mips_pic
!= SVR4_PIC
)
7036 mips_emit_delays ();
7038 mips_align (2, 0, label
);
7043 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
7045 as_bad ("Unsupported use of .gpword");
7046 ignore_rest_of_line ();
7050 md_number_to_chars (p
, (valueT
) 0, 4);
7051 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
7052 BFD_RELOC_MIPS_GPREL32
);
7054 demand_empty_rest_of_line ();
7057 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
7058 tables in SVR4 PIC code. */
7067 /* This is ignored when not generating SVR4 PIC code. */
7068 if (mips_pic
!= SVR4_PIC
)
7074 /* Add $gp to the register named as an argument. */
7075 reg
= tc_get_register (0);
7076 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7077 mips_isa
< 3 ? "addu" : "daddu",
7078 "d,v,t", reg
, reg
, GP
);
7080 demand_empty_rest_of_line ();
7083 /* Parse a register string into a number. Called from the ECOFF code
7084 to parse .frame. The argument is non-zero if this is the frame
7085 register, so that we can record it in mips_frame_reg. */
7088 tc_get_register (frame
)
7094 if (*input_line_pointer
++ != '$')
7096 as_warn ("expected `$'");
7099 else if (isdigit ((unsigned char) *input_line_pointer
))
7101 reg
= get_absolute_expression ();
7102 if (reg
< 0 || reg
>= 32)
7104 as_warn ("Bad register number");
7110 if (strncmp (input_line_pointer
, "fp", 2) == 0)
7112 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
7114 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
7116 else if (strncmp (input_line_pointer
, "at", 2) == 0)
7120 as_warn ("Unrecognized register name");
7123 input_line_pointer
+= 2;
7126 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
7131 md_section_align (seg
, addr
)
7135 int align
= bfd_get_section_alignment (stdoutput
, seg
);
7137 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
7140 /* Utility routine, called from above as well. If called while the
7141 input file is still being read, it's only an approximation. (For
7142 example, a symbol may later become defined which appeared to be
7143 undefined earlier.) */
7146 nopic_need_relax (sym
)
7152 if (USE_GLOBAL_POINTER_OPT
)
7154 const char *symname
;
7157 /* Find out whether this symbol can be referenced off the GP
7158 register. It can be if it is smaller than the -G size or if
7159 it is in the .sdata or .sbss section. Certain symbols can
7160 not be referenced off the GP, although it appears as though
7162 symname
= S_GET_NAME (sym
);
7163 if (symname
!= (const char *) NULL
7164 && (strcmp (symname
, "eprol") == 0
7165 || strcmp (symname
, "etext") == 0
7166 || strcmp (symname
, "_gp") == 0
7167 || strcmp (symname
, "edata") == 0
7168 || strcmp (symname
, "_fbss") == 0
7169 || strcmp (symname
, "_fdata") == 0
7170 || strcmp (symname
, "_ftext") == 0
7171 || strcmp (symname
, "end") == 0
7172 || strcmp (symname
, "_gp_disp") == 0))
7174 else if (! S_IS_DEFINED (sym
)
7176 #ifndef NO_ECOFF_DEBUGGING
7177 || (sym
->ecoff_extern_size
!= 0
7178 && sym
->ecoff_extern_size
<= g_switch_value
)
7180 || (S_GET_VALUE (sym
) != 0
7181 && S_GET_VALUE (sym
) <= g_switch_value
)))
7185 const char *segname
;
7187 segname
= segment_name (S_GET_SEGMENT (sym
));
7188 assert (strcmp (segname
, ".lit8") != 0
7189 && strcmp (segname
, ".lit4") != 0);
7190 change
= (strcmp (segname
, ".sdata") != 0
7191 && strcmp (segname
, ".sbss") != 0);
7196 /* We are not optimizing for the GP register. */
7200 /* Estimate the size of a frag before relaxing. We are not really
7201 relaxing here, and the final size is encoded in the subtype
7206 md_estimate_size_before_relax (fragp
, segtype
)
7212 if (mips_pic
== NO_PIC
)
7214 change
= nopic_need_relax (fragp
->fr_symbol
);
7216 else if (mips_pic
== SVR4_PIC
)
7218 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
7220 /* This must duplicate the test in adjust_reloc_syms. */
7221 change
= (symsec
!= &bfd_und_section
7222 && symsec
!= &bfd_abs_section
7223 && ! bfd_is_com_section (symsec
));
7230 /* Record the offset to the first reloc in the fr_opcode field.
7231 This lets md_convert_frag and tc_gen_reloc know that the code
7232 must be expanded. */
7233 fragp
->fr_opcode
= (fragp
->fr_literal
7235 - RELAX_OLD (fragp
->fr_subtype
)
7236 + RELAX_RELOC1 (fragp
->fr_subtype
));
7237 /* FIXME: This really needs as_warn_where. */
7238 if (RELAX_WARN (fragp
->fr_subtype
))
7239 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
7245 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
7248 /* Translate internal representation of relocation info to BFD target
7252 tc_gen_reloc (section
, fixp
)
7256 static arelent
*retval
[4];
7259 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
7262 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
7263 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7265 if (mips_pic
== EMBEDDED_PIC
7266 && SWITCH_TABLE (fixp
))
7268 /* For a switch table entry we use a special reloc. The addend
7269 is actually the difference between the reloc address and the
7271 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
7272 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
7273 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
7274 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
7276 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
7278 /* We use a special addend for an internal RELLO reloc. */
7279 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
7280 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
7282 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
7284 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
7286 assert (fixp
->fx_next
!= NULL
7287 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
7288 /* We use a special addend for an internal RELHI reloc. The
7289 reloc is relative to the RELLO; adjust the addend
7291 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
7292 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
7293 + fixp
->fx_next
->fx_where
7294 - S_GET_VALUE (fixp
->fx_subsy
));
7296 reloc
->addend
= (fixp
->fx_addnumber
7297 + fixp
->fx_next
->fx_frag
->fr_address
7298 + fixp
->fx_next
->fx_where
);
7300 else if (fixp
->fx_pcrel
== 0)
7301 reloc
->addend
= fixp
->fx_addnumber
;
7304 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
7305 /* A gruesome hack which is a result of the gruesome gas reloc
7307 reloc
->addend
= reloc
->address
;
7309 reloc
->addend
= -reloc
->address
;
7312 /* If this is a variant frag, we may need to adjust the existing
7313 reloc and generate a new one. */
7314 if (fixp
->fx_frag
->fr_opcode
!= NULL
7315 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
7316 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
7317 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
7318 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
7319 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
7320 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
7321 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
7325 /* If this is not the last reloc in this frag, then we have two
7326 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
7327 CALL_HI16/CALL_LO16, both of which are being replaced. Let
7328 the second one handle all of them. */
7329 if (fixp
->fx_next
!= NULL
7330 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
7332 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
7333 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
7334 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
7335 && (fixp
->fx_next
->fx_r_type
7336 == BFD_RELOC_MIPS_GOT_LO16
))
7337 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
7338 && (fixp
->fx_next
->fx_r_type
7339 == BFD_RELOC_MIPS_CALL_LO16
)));
7344 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
7345 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7346 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
7348 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
7349 reloc2
->address
= (reloc
->address
7350 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
7351 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
7352 reloc2
->addend
= fixp
->fx_addnumber
;
7353 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
7354 assert (reloc2
->howto
!= NULL
);
7356 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
7360 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
7363 reloc3
->address
+= 4;
7366 if (mips_pic
== NO_PIC
)
7368 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
7369 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
7371 else if (mips_pic
== SVR4_PIC
)
7373 switch (fixp
->fx_r_type
)
7377 case BFD_RELOC_MIPS_GOT16
:
7379 case BFD_RELOC_MIPS_CALL16
:
7380 case BFD_RELOC_MIPS_GOT_LO16
:
7381 case BFD_RELOC_MIPS_CALL_LO16
:
7382 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
7390 /* To support a PC relative reloc when generating embedded PIC code
7391 for ECOFF, we use a Cygnus extension. We check for that here to
7392 make sure that we don't let such a reloc escape normally. */
7393 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
7394 && fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
7395 && mips_pic
!= EMBEDDED_PIC
)
7396 reloc
->howto
= NULL
;
7398 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
7400 if (reloc
->howto
== NULL
)
7402 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7403 "Can not represent relocation in this object file format");
7410 /* Convert a machine dependent frag. */
7413 md_convert_frag (abfd
, asec
, fragp
)
7421 if (fragp
->fr_opcode
== NULL
)
7424 old
= RELAX_OLD (fragp
->fr_subtype
);
7425 new = RELAX_NEW (fragp
->fr_subtype
);
7426 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
7429 memcpy (fixptr
- old
, fixptr
, new);
7431 fragp
->fr_fix
+= new - old
;
7434 /* This function is called whenever a label is defined. It is used
7435 when handling branch delays; if a branch has a label, we assume we
7439 mips_define_label (sym
)
7445 /* Decide whether a label is local. This is called by LOCAL_LABEL.
7446 In order to work with gcc when using mips-tfile, we must keep all
7447 local labels. However, in other cases, we want to discard them,
7448 since they are useless. */
7451 mips_local_label (name
)
7454 #ifndef NO_ECOFF_DEBUGGING
7457 && ! ecoff_debugging_seen
)
7459 /* We were called with -g, but we didn't see any debugging
7460 information. That may mean that gcc is smuggling debugging
7461 information through to mips-tfile, in which case we must
7462 generate all local labels. */
7467 /* Here it's OK to discard local labels. */
7469 return name
[0] == '$';
7472 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7474 /* Some special processing for a MIPS ELF file. */
7477 mips_elf_final_processing ()
7481 /* Write out the .reginfo section. */
7482 s
.ri_gprmask
= mips_gprmask
;
7483 s
.ri_cprmask
[0] = mips_cprmask
[0];
7484 s
.ri_cprmask
[1] = mips_cprmask
[1];
7485 s
.ri_cprmask
[2] = mips_cprmask
[2];
7486 s
.ri_cprmask
[3] = mips_cprmask
[3];
7487 /* The gp_value field is set by the MIPS ELF backend. */
7489 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
7490 ((Elf32_External_RegInfo
*)
7491 mips_regmask_frag
));
7493 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
7494 sort of BFD interface for this. */
7495 if (mips_any_noreorder
)
7496 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
7497 if (mips_pic
!= NO_PIC
)
7498 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
7501 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
7503 /* These functions should really be defined by the object file format,
7504 since they are related to debugging information. However, this
7505 code has to work for the a.out format, which does not define them,
7506 so we provide simple versions here. These don't actually generate
7507 any debugging information, but they do simple checking and someday
7508 somebody may make them useful. */
7512 struct loc
*loc_next
;
7513 unsigned long loc_fileno
;
7514 unsigned long loc_lineno
;
7515 unsigned long loc_offset
;
7516 unsigned short loc_delta
;
7517 unsigned short loc_count
;
7526 struct proc
*proc_next
;
7527 struct symbol
*proc_isym
;
7528 struct symbol
*proc_end
;
7529 unsigned long proc_reg_mask
;
7530 unsigned long proc_reg_offset
;
7531 unsigned long proc_fpreg_mask
;
7532 unsigned long proc_fpreg_offset
;
7533 unsigned long proc_frameoffset
;
7534 unsigned long proc_framereg
;
7535 unsigned long proc_pcreg
;
7537 struct file
*proc_file
;
7544 struct file
*file_next
;
7545 unsigned long file_fileno
;
7546 struct symbol
*file_symbol
;
7547 struct symbol
*file_end
;
7548 struct proc
*file_proc
;
7553 static struct obstack proc_frags
;
7554 static procS
*proc_lastP
;
7555 static procS
*proc_rootP
;
7556 static int numprocs
;
7561 obstack_begin (&proc_frags
, 0x2000);
7567 /* check for premature end, nesting errors, etc */
7568 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
7569 as_warn ("missing `.end' at end of assembly");
7578 if (*input_line_pointer
== '-')
7580 ++input_line_pointer
;
7583 if (!isdigit (*input_line_pointer
))
7584 as_bad ("Expected simple number.");
7585 if (input_line_pointer
[0] == '0')
7587 if (input_line_pointer
[1] == 'x')
7589 input_line_pointer
+= 2;
7590 while (isxdigit (*input_line_pointer
))
7593 val
|= hex_value (*input_line_pointer
++);
7595 return negative
? -val
: val
;
7599 ++input_line_pointer
;
7600 while (isdigit (*input_line_pointer
))
7603 val
|= *input_line_pointer
++ - '0';
7605 return negative
? -val
: val
;
7608 if (!isdigit (*input_line_pointer
))
7610 printf (" *input_line_pointer == '%c' 0x%02x\n",
7611 *input_line_pointer
, *input_line_pointer
);
7612 as_warn ("Invalid number");
7615 while (isdigit (*input_line_pointer
))
7618 val
+= *input_line_pointer
++ - '0';
7620 return negative
? -val
: val
;
7623 /* The .file directive; just like the usual .file directive, but there
7624 is an initial number which is the ECOFF file index. */
7632 line
= get_number ();
7637 /* The .end directive. */
7645 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
7648 demand_empty_rest_of_line ();
7652 if (now_seg
!= text_section
)
7653 as_warn (".end not in text section");
7656 as_warn (".end and no .ent seen yet.");
7662 assert (S_GET_NAME (p
));
7663 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
7664 as_warn (".end symbol does not match .ent symbol.");
7667 proc_lastP
->proc_end
= (symbolS
*) 1;
7670 /* The .aent and .ent directives. */
7680 symbolP
= get_symbol ();
7681 if (*input_line_pointer
== ',')
7682 input_line_pointer
++;
7684 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
7685 number
= get_number ();
7686 if (now_seg
!= text_section
)
7687 as_warn (".ent or .aent not in text section.");
7689 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
7690 as_warn ("missing `.end'");
7694 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
7695 procP
->proc_isym
= symbolP
;
7696 procP
->proc_reg_mask
= 0;
7697 procP
->proc_reg_offset
= 0;
7698 procP
->proc_fpreg_mask
= 0;
7699 procP
->proc_fpreg_offset
= 0;
7700 procP
->proc_frameoffset
= 0;
7701 procP
->proc_framereg
= 0;
7702 procP
->proc_pcreg
= 0;
7703 procP
->proc_end
= NULL
;
7704 procP
->proc_next
= NULL
;
7706 proc_lastP
->proc_next
= procP
;
7712 demand_empty_rest_of_line ();
7715 /* The .frame directive. */
7728 frame_reg
= tc_get_register (1);
7729 if (*input_line_pointer
== ',')
7730 input_line_pointer
++;
7731 frame_off
= get_absolute_expression ();
7732 if (*input_line_pointer
== ',')
7733 input_line_pointer
++;
7734 pcreg
= tc_get_register (0);
7737 assert (proc_rootP
);
7738 proc_rootP
->proc_framereg
= frame_reg
;
7739 proc_rootP
->proc_frameoffset
= frame_off
;
7740 proc_rootP
->proc_pcreg
= pcreg
;
7741 /* bob macho .frame */
7743 /* We don't have to write out a frame stab for unoptimized code. */
7744 if (!(frame_reg
== FP
&& frame_off
== 0))
7747 as_warn ("No .ent for .frame to use.");
7748 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
7749 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
7750 S_SET_TYPE (symP
, N_RMASK
);
7751 S_SET_OTHER (symP
, 0);
7752 S_SET_DESC (symP
, 0);
7753 symP
->sy_forward
= proc_lastP
->proc_isym
;
7754 /* bob perhaps I should have used pseudo set */
7756 demand_empty_rest_of_line ();
7760 /* The .fmask and .mask directives. */
7767 char str
[100], *strP
;
7773 mask
= get_number ();
7774 if (*input_line_pointer
== ',')
7775 input_line_pointer
++;
7776 off
= get_absolute_expression ();
7778 /* bob only for coff */
7779 assert (proc_rootP
);
7780 if (reg_type
== 'F')
7782 proc_rootP
->proc_fpreg_mask
= mask
;
7783 proc_rootP
->proc_fpreg_offset
= off
;
7787 proc_rootP
->proc_reg_mask
= mask
;
7788 proc_rootP
->proc_reg_offset
= off
;
7791 /* bob macho .mask + .fmask */
7793 /* We don't have to write out a mask stab if no saved regs. */
7797 as_warn ("No .ent for .mask to use.");
7799 for (i
= 0; i
< 32; i
++)
7803 sprintf (strP
, "%c%d,", reg_type
, i
);
7804 strP
+= strlen (strP
);
7808 sprintf (strP
, ";%d,", off
);
7809 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
7810 S_SET_TYPE (symP
, N_RMASK
);
7811 S_SET_OTHER (symP
, 0);
7812 S_SET_DESC (symP
, 0);
7813 symP
->sy_forward
= proc_lastP
->proc_isym
;
7814 /* bob perhaps I should have used pseudo set */
7819 /* The .loc directive. */
7830 assert (now_seg
== text_section
);
7832 lineno
= get_number ();
7833 addroff
= frag_now_fix ();
7835 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
7836 S_SET_TYPE (symbolP
, N_SLINE
);
7837 S_SET_OTHER (symbolP
, 0);
7838 S_SET_DESC (symbolP
, lineno
);
7839 symbolP
->sy_segment
= now_seg
;