1 /* tc-riscv.c -- RISC-V assembler
2 Copyright 2011-2016 Free Software Foundation, Inc.
4 Contributed by Andrew Waterman (andrew@sifive.com).
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
26 #include "safe-ctype.h"
29 #include "dwarf2dbg.h"
30 #include "dw2gencfi.h"
31 #include "struc-symbol.h"
33 #include "elf/riscv.h"
34 #include "opcode/riscv.h"
38 /* Information about an instruction, including its format, operands
42 /* The opcode's entry in riscv_opcodes. */
43 const struct riscv_opcode
*insn_mo
;
45 /* The encoded instruction bits. */
48 /* The frag that contains the instruction. */
51 /* The offset into FRAG of the first instruction byte. */
54 /* The relocs associated with the instruction, if any. */
59 #define DEFAULT_ARCH "riscv64"
62 static const char default_arch
[] = DEFAULT_ARCH
;
64 unsigned xlen
= 0; /* width of an x-register */
66 #define LOAD_ADDRESS_INSN (xlen == 64 ? "ld" : "lw")
67 #define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
69 static unsigned elf_flags
= 0;
71 /* This is the set of options which the .option pseudo-op may modify. */
73 struct riscv_set_options
75 int pic
; /* Generate position-independent code. */
76 int rvc
; /* Generate RVC code. */
77 int relax
; /* Emit relocs the linker is allowed to relax. */
80 static struct riscv_set_options riscv_opts
=
88 riscv_set_rvc (bfd_boolean rvc_value
)
91 elf_flags
|= EF_RISCV_RVC
;
93 riscv_opts
.rvc
= rvc_value
;
100 struct riscv_subset
*next
;
103 static struct riscv_subset
*riscv_subsets
;
106 riscv_subset_supports (const char *feature
)
108 struct riscv_subset
*s
;
110 unsigned xlen_required
= strtoul (feature
, &p
, 10);
112 if (xlen_required
&& xlen
!= xlen_required
)
115 for (s
= riscv_subsets
; s
!= NULL
; s
= s
->next
)
116 if (strcasecmp (s
->name
, p
) == 0)
123 riscv_add_subset (const char *subset
)
125 struct riscv_subset
*s
= xmalloc (sizeof *s
);
127 s
->name
= xstrdup (subset
);
128 s
->next
= riscv_subsets
;
132 /* Set which ISA and extensions are available. Formally, ISA strings must
133 begin with RV32 or RV64, but we allow the prefix to be omitted.
135 FIXME: Version numbers are not supported yet. */
137 riscv_set_arch (const char *p
)
139 const char *all_subsets
= "IMAFDC";
140 const char *extension
= NULL
;
144 if (strncasecmp (p
, "RV32", 4) == 0)
149 else if (strncasecmp (p
, "RV64", 4) == 0)
154 else if (strncasecmp (p
, "RV", 2) == 0)
167 for (i
= 0; all_subsets
[i
] != '\0'; i
++)
169 const char subset
[] = {all_subsets
[i
], '\0'};
170 riscv_add_subset (subset
);
175 as_fatal ("`I' must be the first ISA subset name specified (got %c)",
181 if (TOUPPER(*p
) == 'X')
183 char *subset
= xstrdup (p
), *q
= subset
;
185 while (*++q
!= '\0' && *q
!= '_')
190 as_fatal ("only one eXtension is supported (found %s and %s)",
193 riscv_add_subset (subset
);
194 p
+= strlen (subset
);
199 else if ((all_subsets
= strchr (all_subsets
, *p
)) != NULL
)
201 const char subset
[] = {*p
, 0};
202 riscv_add_subset (subset
);
203 if (TOUPPER(*p
) == 'C')
209 as_fatal ("unsupported ISA subset %c", *p
);
214 /* Override -m[no-]rvc setting if C was explicitly listed. */
215 riscv_set_rvc (TRUE
);
219 /* Add RVC anyway. -m[no-]rvc toggles its availability. */
220 riscv_add_subset ("C");
224 /* Handle of the OPCODE hash table. */
225 static struct hash_control
*op_hash
= NULL
;
227 /* This array holds the chars that always start a comment. If the
228 pre-processor is disabled, these aren't very useful */
229 const char comment_chars
[] = "#";
231 /* This array holds the chars that only start a comment at the beginning of
232 a line. If the line seems to have the form '# 123 filename'
233 .line and .file directives will appear in the pre-processed output */
234 /* Note that input_file.c hand checks for '#' at the beginning of the
235 first line of the input file. This is because the compiler outputs
236 #NO_APP at the beginning of its output. */
237 /* Also note that C style comments are always supported. */
238 const char line_comment_chars
[] = "#";
240 /* This array holds machine specific line separator characters. */
241 const char line_separator_chars
[] = ";";
243 /* Chars that can be used to separate mant from exp in floating point nums */
244 const char EXP_CHARS
[] = "eE";
246 /* Chars that mean this number is a floating point constant */
249 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
251 /* Macros for encoding relaxation state for RVC branches and far jumps. */
252 #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
255 | ((uncond) ? 1 : 0) \
258 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
259 #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
260 #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
261 #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
263 /* Is the given value a sign-extended 32-bit value? */
264 #define IS_SEXT_32BIT_NUM(x) \
265 (((x) &~ (offsetT) 0x7fffffff) == 0 \
266 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
268 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
269 #define IS_ZEXT_32BIT_NUM(x) \
270 (((x) &~ (offsetT) 0xffffffff) == 0 \
271 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
273 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
274 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
275 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
276 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
278 /* Determine if an instruction matches an opcode. */
279 #define OPCODE_MATCHES(OPCODE, OP) \
280 (((OPCODE) & MASK_##OP) == MATCH_##OP)
282 static char *expr_end
;
284 /* The default target format to use. */
287 riscv_target_format (void)
289 return xlen
== 64 ? "elf64-littleriscv" : "elf32-littleriscv";
292 /* Return the length of instruction INSN. */
294 static inline unsigned int
295 insn_length (const struct riscv_cl_insn
*insn
)
297 return riscv_insn_length (insn
->insn_opcode
);
300 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
303 create_insn (struct riscv_cl_insn
*insn
, const struct riscv_opcode
*mo
)
306 insn
->insn_opcode
= mo
->match
;
312 /* Install INSN at the location specified by its "frag" and "where" fields. */
315 install_insn (const struct riscv_cl_insn
*insn
)
317 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
318 md_number_to_chars (f
, insn
->insn_opcode
, insn_length (insn
));
321 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
322 and install the opcode in the new location. */
325 move_insn (struct riscv_cl_insn
*insn
, fragS
*frag
, long where
)
329 if (insn
->fixp
!= NULL
)
331 insn
->fixp
->fx_frag
= frag
;
332 insn
->fixp
->fx_where
= where
;
337 /* Add INSN to the end of the output. */
340 add_fixed_insn (struct riscv_cl_insn
*insn
)
342 char *f
= frag_more (insn_length (insn
));
343 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
347 add_relaxed_insn (struct riscv_cl_insn
*insn
, int max_chars
, int var
,
348 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
350 frag_grow (max_chars
);
351 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
352 frag_var (rs_machine_dependent
, max_chars
, var
,
353 subtype
, symbol
, offset
, NULL
);
356 /* Compute the length of a branch sequence, and adjust the stored length
357 accordingly. If FRAGP is NULL, the worst-case length is returned. */
360 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
362 int jump
, rvc
, length
= 8;
367 jump
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
);
368 rvc
= RELAX_BRANCH_RVC (fragp
->fr_subtype
);
369 length
= RELAX_BRANCH_LENGTH (fragp
->fr_subtype
);
371 /* Assume jumps are in range; the linker will catch any that aren't. */
372 length
= jump
? 4 : 8;
374 if (fragp
->fr_symbol
!= NULL
375 && S_IS_DEFINED (fragp
->fr_symbol
)
376 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
378 offsetT val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
379 bfd_vma rvc_range
= jump
? RVC_JUMP_REACH
: RVC_BRANCH_REACH
;
380 val
-= fragp
->fr_address
+ fragp
->fr_fix
;
382 if (rvc
&& (bfd_vma
)(val
+ rvc_range
/2) < rvc_range
)
384 else if ((bfd_vma
)(val
+ RISCV_BRANCH_REACH
/2) < RISCV_BRANCH_REACH
)
386 else if (!jump
&& rvc
)
391 fragp
->fr_subtype
= RELAX_BRANCH_ENCODE (jump
, rvc
, length
);
410 static struct hash_control
*reg_names_hash
= NULL
;
412 #define ENCODE_REG_HASH(cls, n) \
413 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
414 #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
415 #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
418 hash_reg_name (enum reg_class
class, const char *name
, unsigned n
)
420 void *hash
= ENCODE_REG_HASH (class, n
);
421 const char *retval
= hash_insert (reg_names_hash
, name
, hash
);
424 as_fatal (_("internal error: can't hash `%s': %s"), name
, retval
);
428 hash_reg_names (enum reg_class
class, const char * const names
[], unsigned n
)
432 for (i
= 0; i
< n
; i
++)
433 hash_reg_name (class, names
[i
], i
);
437 reg_lookup_internal (const char *s
, enum reg_class
class)
439 struct regname
*r
= (struct regname
*) hash_find (reg_names_hash
, s
);
441 if (r
== NULL
|| DECODE_REG_CLASS (r
) != class)
443 return DECODE_REG_NUM (r
);
447 reg_lookup (char **s
, enum reg_class
class, unsigned int *regnop
)
453 /* Find end of name. */
455 if (is_name_beginner (*e
))
457 while (is_part_of_name (*e
))
460 /* Terminate name. */
464 /* Look for the register. Advance to next token if one was recognized. */
465 if ((reg
= reg_lookup_internal (*s
, class)) >= 0)
475 arg_lookup (char **s
, const char *const *array
, size_t size
, unsigned *regnop
)
477 const char *p
= strchr (*s
, ',');
478 size_t i
, len
= p
? (size_t)(p
- *s
) : strlen (*s
);
480 for (i
= 0; i
< size
; i
++)
481 if (array
[i
] != NULL
&& strncmp (array
[i
], *s
, len
) == 0)
491 /* For consistency checking, verify that all bits are specified either
492 by the match/mask part of the instruction definition, or by the
495 validate_riscv_insn (const struct riscv_opcode
*opc
)
497 const char *p
= opc
->args
;
499 insn_t used_bits
= opc
->mask
;
500 int insn_width
= 8 * riscv_insn_length (opc
->match
);
501 insn_t required_bits
= ~0ULL >> (64 - insn_width
);
503 if ((used_bits
& opc
->match
) != (opc
->match
& required_bits
))
505 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
506 opc
->name
, opc
->args
);
510 #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
517 case 'a': used_bits
|= ENCODE_RVC_J_IMM (-1U); break;
518 case 'c': break; /* RS1, constrained to equal sp */
519 case 'i': used_bits
|= ENCODE_RVC_SIMM3(-1U); break;
520 case 'j': used_bits
|= ENCODE_RVC_IMM (-1U); break;
521 case 'k': used_bits
|= ENCODE_RVC_LW_IMM (-1U); break;
522 case 'l': used_bits
|= ENCODE_RVC_LD_IMM (-1U); break;
523 case 'm': used_bits
|= ENCODE_RVC_LWSP_IMM (-1U); break;
524 case 'n': used_bits
|= ENCODE_RVC_LDSP_IMM (-1U); break;
525 case 'p': used_bits
|= ENCODE_RVC_B_IMM (-1U); break;
526 case 's': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
527 case 't': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
528 case 'u': used_bits
|= ENCODE_RVC_IMM (-1U); break;
529 case 'v': used_bits
|= ENCODE_RVC_IMM (-1U); break;
530 case 'w': break; /* RS1S, constrained to equal RD */
531 case 'x': break; /* RS2S, constrained to equal RD */
532 case 'K': used_bits
|= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
533 case 'L': used_bits
|= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
534 case 'M': used_bits
|= ENCODE_RVC_SWSP_IMM (-1U); break;
535 case 'N': used_bits
|= ENCODE_RVC_SDSP_IMM (-1U); break;
536 case 'U': break; /* RS1, constrained to equal RD */
537 case 'V': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
538 case '<': used_bits
|= ENCODE_RVC_IMM (-1U); break;
539 case '>': used_bits
|= ENCODE_RVC_IMM (-1U); break;
540 case 'T': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
541 case 'D': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
543 as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"),
544 c
, opc
->name
, opc
->args
);
551 case '<': USE_BITS (OP_MASK_SHAMTW
, OP_SH_SHAMTW
); break;
552 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
554 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
555 case 'Z': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
556 case 'E': USE_BITS (OP_MASK_CSR
, OP_SH_CSR
); break;
558 case 'R': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
559 case 'S': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
560 case 'U': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); /* fallthru */
561 case 'T': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
562 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
563 case 'm': USE_BITS (OP_MASK_RM
, OP_SH_RM
); break;
564 case 's': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
565 case 't': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
566 case 'P': USE_BITS (OP_MASK_PRED
, OP_SH_PRED
); break;
567 case 'Q': USE_BITS (OP_MASK_SUCC
, OP_SH_SUCC
); break;
569 case 'j': used_bits
|= ENCODE_ITYPE_IMM (-1U); break;
570 case 'a': used_bits
|= ENCODE_UJTYPE_IMM (-1U); break;
571 case 'p': used_bits
|= ENCODE_SBTYPE_IMM (-1U); break;
572 case 'q': used_bits
|= ENCODE_STYPE_IMM (-1U); break;
573 case 'u': used_bits
|= ENCODE_UTYPE_IMM (-1U); break;
578 as_bad (_("internal: bad RISC-V opcode "
579 "(unknown operand type `%c'): %s %s"),
580 c
, opc
->name
, opc
->args
);
584 if (used_bits
!= required_bits
)
586 as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"),
587 ~(unsigned long)(used_bits
& required_bits
),
588 opc
->name
, opc
->args
);
594 struct percent_op_match
597 bfd_reloc_code_real_type reloc
;
600 /* This function is called once, at assembler startup time. It should set up
601 all the tables, etc. that the MD part of the assembler will need. */
608 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, 0))
609 as_warn (_("Could not set architecture and machine"));
611 op_hash
= hash_new ();
613 while (riscv_opcodes
[i
].name
)
615 const char *name
= riscv_opcodes
[i
].name
;
616 const char *hash_error
=
617 hash_insert (op_hash
, name
, (void *) &riscv_opcodes
[i
]);
621 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
622 riscv_opcodes
[i
].name
, hash_error
);
623 /* Probably a memory allocation problem? Give up now. */
624 as_fatal (_("Broken assembler. No assembly attempted."));
629 if (riscv_opcodes
[i
].pinfo
!= INSN_MACRO
)
631 if (!validate_riscv_insn (&riscv_opcodes
[i
]))
632 as_fatal (_("Broken assembler. No assembly attempted."));
636 while (riscv_opcodes
[i
].name
&& !strcmp (riscv_opcodes
[i
].name
, name
));
639 reg_names_hash
= hash_new ();
640 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_numeric
, NGPR
);
641 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_abi
, NGPR
);
642 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_numeric
, NFPR
);
643 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_abi
, NFPR
);
645 #define DECLARE_CSR(name, num) hash_reg_name (RCLASS_CSR, #name, num);
646 #include "opcode/riscv-opc.h"
649 /* Set the default alignment for the text section. */
650 record_alignment (text_section
, riscv_opts
.rvc
? 1 : 2);
654 riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type
, bfd_vma value
)
661 case BFD_RELOC_RISCV_HI20
:
662 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value
));
664 case BFD_RELOC_RISCV_LO12_S
:
665 return ENCODE_STYPE_IMM (value
);
667 case BFD_RELOC_RISCV_LO12_I
:
668 return ENCODE_ITYPE_IMM (value
);
675 /* Output an instruction. IP is the instruction information.
676 ADDRESS_EXPR is an operand of the instruction to be used with
680 append_insn (struct riscv_cl_insn
*ip
, expressionS
*address_expr
,
681 bfd_reloc_code_real_type reloc_type
)
683 dwarf2_emit_insn (0);
685 if (reloc_type
!= BFD_RELOC_UNUSED
)
687 reloc_howto_type
*howto
;
689 gas_assert (address_expr
);
690 if (reloc_type
== BFD_RELOC_12_PCREL
691 || reloc_type
== BFD_RELOC_RISCV_JMP
)
693 int j
= reloc_type
== BFD_RELOC_RISCV_JMP
;
694 int best_case
= riscv_insn_length (ip
->insn_opcode
);
695 unsigned worst_case
= relaxed_branch_length (NULL
, NULL
, 0);
696 add_relaxed_insn (ip
, worst_case
, best_case
,
697 RELAX_BRANCH_ENCODE (j
, best_case
== 2, worst_case
),
698 address_expr
->X_add_symbol
,
699 address_expr
->X_add_number
);
702 else if (address_expr
->X_op
== O_constant
)
703 ip
->insn_opcode
|= riscv_apply_const_reloc (reloc_type
,
704 address_expr
->X_add_number
);
707 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
);
709 as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type
);
711 ip
->fixp
= fix_new_exp (ip
->frag
, ip
->where
,
712 bfd_get_reloc_size (howto
),
713 address_expr
, FALSE
, reloc_type
);
715 ip
->fixp
->fx_tcbit
= riscv_opts
.relax
;
723 /* Build an instruction created by a macro expansion. This is passed
724 a pointer to the count of instructions created so far, an
725 expression, the name of the instruction to build, an operand format
726 string, and corresponding arguments. */
729 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
731 const struct riscv_opcode
*mo
;
732 struct riscv_cl_insn insn
;
733 bfd_reloc_code_real_type r
;
736 va_start (args
, fmt
);
738 r
= BFD_RELOC_UNUSED
;
739 mo
= (struct riscv_opcode
*) hash_find (op_hash
, name
);
742 /* Find a non-RVC variant of the instruction. append_insn will compress
744 while (riscv_insn_length (mo
->match
) < 4)
746 gas_assert (strcmp (name
, mo
->name
) == 0);
748 create_insn (&insn
, mo
);
754 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
758 INSERT_OPERAND (RS1
, insn
, va_arg (args
, int));
762 INSERT_OPERAND (RS2
, insn
, va_arg (args
, int));
766 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
772 gas_assert (ep
!= NULL
);
773 r
= va_arg (args
, int);
781 as_fatal (_("internal error: invalid macro"));
786 gas_assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
788 append_insn (&insn
, ep
, r
);
791 /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
794 normalize_constant_expr (expressionS
*ex
)
798 if ((ex
->X_op
== O_constant
|| ex
->X_op
== O_symbol
)
799 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
800 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
804 /* Fail if an expression is not a constant. */
807 check_absolute_expr (struct riscv_cl_insn
*ip
, expressionS
*ex
)
809 if (ex
->X_op
== O_big
)
810 as_bad (_("unsupported large constant"));
811 else if (ex
->X_op
!= O_constant
)
812 as_bad (_("Instruction %s requires absolute expression"),
814 normalize_constant_expr (ex
);
818 make_internal_label (void)
820 return (symbolS
*) local_symbol_make (FAKE_LABEL_NAME
, now_seg
,
821 (valueT
) frag_now_fix (), frag_now
);
824 /* Load an entry from the GOT. */
826 pcrel_access (int destreg
, int tempreg
, expressionS
*ep
,
827 const char *lo_insn
, const char *lo_pattern
,
828 bfd_reloc_code_real_type hi_reloc
,
829 bfd_reloc_code_real_type lo_reloc
)
833 ep2
.X_add_symbol
= make_internal_label ();
834 ep2
.X_add_number
= 0;
836 macro_build (ep
, "auipc", "d,u", tempreg
, hi_reloc
);
837 macro_build (&ep2
, lo_insn
, lo_pattern
, destreg
, tempreg
, lo_reloc
);
841 pcrel_load (int destreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
842 bfd_reloc_code_real_type hi_reloc
,
843 bfd_reloc_code_real_type lo_reloc
)
845 pcrel_access (destreg
, tempreg
, ep
, lo_insn
, "d,s,j", hi_reloc
, lo_reloc
);
849 pcrel_store (int srcreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
850 bfd_reloc_code_real_type hi_reloc
,
851 bfd_reloc_code_real_type lo_reloc
)
853 pcrel_access (srcreg
, tempreg
, ep
, lo_insn
, "t,s,q", hi_reloc
, lo_reloc
);
856 /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
858 riscv_call (int destreg
, int tempreg
, expressionS
*ep
,
859 bfd_reloc_code_real_type reloc
)
861 macro_build (ep
, "auipc", "d,u", tempreg
, reloc
);
862 macro_build (NULL
, "jalr", "d,s", destreg
, tempreg
);
865 /* Load an integer constant into a register. */
868 load_const (int reg
, expressionS
*ep
)
870 int shift
= RISCV_IMM_BITS
;
871 expressionS upper
= *ep
, lower
= *ep
;
872 lower
.X_add_number
= (int32_t) ep
->X_add_number
<< (32-shift
) >> (32-shift
);
873 upper
.X_add_number
-= lower
.X_add_number
;
875 if (ep
->X_op
!= O_constant
)
877 as_bad (_("unsupported large constant"));
881 if (xlen
> 32 && !IS_SEXT_32BIT_NUM (ep
->X_add_number
))
883 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
884 while (((upper
.X_add_number
>> shift
) & 1) == 0)
887 upper
.X_add_number
= (int64_t) upper
.X_add_number
>> shift
;
888 load_const (reg
, &upper
);
890 macro_build (NULL
, "slli", "d,s,>", reg
, reg
, shift
);
891 if (lower
.X_add_number
!= 0)
892 macro_build (&lower
, "addi", "d,s,j", reg
, reg
, BFD_RELOC_RISCV_LO12_I
);
896 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
899 if (upper
.X_add_number
!= 0)
901 macro_build (ep
, "lui", "d,u", reg
, BFD_RELOC_RISCV_HI20
);
905 if (lower
.X_add_number
!= 0 || hi_reg
== 0)
906 macro_build (ep
, ADD32_INSN
, "d,s,j", reg
, hi_reg
,
907 BFD_RELOC_RISCV_LO12_I
);
911 /* Expand RISC-V assembly macros into one or more instructions. */
913 macro (struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
914 bfd_reloc_code_real_type
*imm_reloc
)
916 int rd
= (ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
;
917 int rs1
= (ip
->insn_opcode
>> OP_SH_RS1
) & OP_MASK_RS1
;
918 int rs2
= (ip
->insn_opcode
>> OP_SH_RS2
) & OP_MASK_RS2
;
919 int mask
= ip
->insn_mo
->mask
;
924 load_const (rd
, imm_expr
);
929 /* Load the address of a symbol into a register. */
930 if (!IS_SEXT_32BIT_NUM (imm_expr
->X_add_number
))
931 as_bad (_("offset too large"));
933 if (imm_expr
->X_op
== O_constant
)
934 load_const (rd
, imm_expr
);
935 else if (riscv_opts
.pic
&& mask
== M_LA
) /* Global PIC symbol */
936 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
937 BFD_RELOC_RISCV_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
938 else /* Local PIC symbol, or any non-PIC symbol */
939 pcrel_load (rd
, rd
, imm_expr
, "addi",
940 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
944 pcrel_load (rd
, rd
, imm_expr
, "addi",
945 BFD_RELOC_RISCV_TLS_GD_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
949 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
950 BFD_RELOC_RISCV_TLS_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
954 pcrel_load (rd
, rd
, imm_expr
, "lb",
955 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
959 pcrel_load (rd
, rd
, imm_expr
, "lbu",
960 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
964 pcrel_load (rd
, rd
, imm_expr
, "lh",
965 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
969 pcrel_load (rd
, rd
, imm_expr
, "lhu",
970 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
974 pcrel_load (rd
, rd
, imm_expr
, "lw",
975 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
979 pcrel_load (rd
, rd
, imm_expr
, "lwu",
980 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
984 pcrel_load (rd
, rd
, imm_expr
, "ld",
985 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
989 pcrel_load (rd
, rs1
, imm_expr
, "flw",
990 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
994 pcrel_load (rd
, rs1
, imm_expr
, "fld",
995 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
999 pcrel_store (rs2
, rs1
, imm_expr
, "sb",
1000 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1004 pcrel_store (rs2
, rs1
, imm_expr
, "sh",
1005 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1009 pcrel_store (rs2
, rs1
, imm_expr
, "sw",
1010 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1014 pcrel_store (rs2
, rs1
, imm_expr
, "sd",
1015 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1019 pcrel_store (rs2
, rs1
, imm_expr
, "fsw",
1020 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1024 pcrel_store (rs2
, rs1
, imm_expr
, "fsd",
1025 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1029 riscv_call (rd
, rs1
, imm_expr
, *imm_reloc
);
1033 as_bad (_("Macro %s not implemented"), ip
->insn_mo
->name
);
1038 static const struct percent_op_match percent_op_utype
[] =
1040 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20
},
1041 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20
},
1042 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20
},
1043 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20
},
1044 {"%hi", BFD_RELOC_RISCV_HI20
},
1048 static const struct percent_op_match percent_op_itype
[] =
1050 {"%lo", BFD_RELOC_RISCV_LO12_I
},
1051 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I
},
1052 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I
},
1056 static const struct percent_op_match percent_op_stype
[] =
1058 {"%lo", BFD_RELOC_RISCV_LO12_S
},
1059 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S
},
1060 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S
},
1064 static const struct percent_op_match percent_op_rtype
[] =
1066 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD
},
1070 /* Return true if *STR points to a relocation operator. When returning true,
1071 move *STR over the operator and store its relocation code in *RELOC.
1072 Leave both *STR and *RELOC alone when returning false. */
1075 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
,
1076 const struct percent_op_match
*percent_op
)
1078 for ( ; percent_op
->str
; percent_op
++)
1079 if (strncasecmp (*str
, percent_op
->str
, strlen (percent_op
->str
)) == 0)
1081 int len
= strlen (percent_op
->str
);
1083 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
1086 *str
+= strlen (percent_op
->str
);
1087 *reloc
= percent_op
->reloc
;
1089 /* Check whether the output BFD supports this relocation.
1090 If not, issue an error and fall back on something safe. */
1091 if (*reloc
!= BFD_RELOC_UNUSED
1092 && !bfd_reloc_type_lookup (stdoutput
, *reloc
))
1094 as_bad ("relocation %s isn't supported by the current ABI",
1096 *reloc
= BFD_RELOC_UNUSED
;
1104 my_getExpression (expressionS
*ep
, char *str
)
1108 save_in
= input_line_pointer
;
1109 input_line_pointer
= str
;
1111 expr_end
= input_line_pointer
;
1112 input_line_pointer
= save_in
;
1115 /* Parse string STR as a 16-bit relocatable operand. Store the
1116 expression in *EP and the relocation, if any, in RELOC.
1117 Return the number of relocation operators used (0 or 1).
1119 On exit, EXPR_END points to the first character after the expression. */
1122 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1123 char *str
, const struct percent_op_match
*percent_op
)
1126 unsigned crux_depth
, str_depth
, regno
;
1129 /* First, check for integer registers. */
1130 if (reg_lookup (&str
, RCLASS_GPR
, ®no
))
1132 ep
->X_op
= O_register
;
1133 ep
->X_add_number
= regno
;
1137 /* Search for the start of the main expression.
1138 End the loop with CRUX pointing to the start
1139 of the main expression and with CRUX_DEPTH containing the number
1140 of open brackets at that point. */
1147 crux_depth
= str_depth
;
1149 /* Skip over whitespace and brackets, keeping count of the number
1151 while (*str
== ' ' || *str
== '\t' || *str
== '(')
1157 && parse_relocation (&str
, reloc
, percent_op
));
1159 my_getExpression (ep
, crux
);
1162 /* Match every open bracket. */
1163 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
1168 as_bad ("unclosed '('");
1175 /* This routine assembles an instruction into its binary format. As a
1176 side effect, it sets the global variable imm_reloc to the type of
1177 relocation to do if one of the operands is an address expression. */
1180 riscv_ip (char *str
, struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1181 bfd_reloc_code_real_type
*imm_reloc
)
1186 struct riscv_opcode
*insn
;
1191 const struct percent_op_match
*p
;
1192 const char *error
= "unrecognized opcode";
1194 /* Parse the name of the instruction. Terminate the string if whitespace
1195 is found so that hash_find only sees the name part of the string. */
1196 for (s
= str
; *s
!= '\0'; ++s
)
1204 insn
= (struct riscv_opcode
*) hash_find (op_hash
, str
);
1207 for ( ; insn
&& insn
->name
&& strcmp (insn
->name
, str
) == 0; insn
++)
1209 if (!riscv_subset_supports (insn
->subset
))
1212 create_insn (ip
, insn
);
1215 imm_expr
->X_op
= O_absent
;
1216 *imm_reloc
= BFD_RELOC_UNUSED
;
1217 p
= percent_op_itype
;
1219 for (args
= insn
->args
;; ++args
)
1221 s
+= strspn (s
, " \t");
1224 case '\0': /* End of args. */
1225 if (insn
->pinfo
!= INSN_MACRO
)
1227 if (!insn
->match_func (insn
, ip
->insn_opcode
))
1229 if (riscv_insn_length (insn
->match
) == 2 && !riscv_opts
.rvc
)
1234 /* Successful assembly. */
1241 case 's': /* RS1 x8-x15 */
1242 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1243 || !(regno
>= 8 && regno
<= 15))
1245 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
1247 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
1248 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1249 || EXTRACT_OPERAND (CRS1S
, ip
->insn_opcode
) + 8 != regno
)
1252 case 't': /* RS2 x8-x15 */
1253 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1254 || !(regno
>= 8 && regno
<= 15))
1256 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
1258 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
1259 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1260 || EXTRACT_OPERAND (CRS2S
, ip
->insn_opcode
) + 8 != regno
)
1263 case 'U': /* RS1, constrained to equal RD. */
1264 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1265 || EXTRACT_OPERAND (RD
, ip
->insn_opcode
) != regno
)
1269 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
))
1271 INSERT_OPERAND (CRS2
, *ip
, regno
);
1273 case 'c': /* RS1, constrained to equal sp. */
1274 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1279 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1280 || imm_expr
->X_op
!= O_constant
1281 || imm_expr
->X_add_number
<= 0
1282 || imm_expr
->X_add_number
>= 64)
1284 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1287 imm_expr
->X_op
= O_absent
;
1290 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1291 || imm_expr
->X_op
!= O_constant
1292 || !VALID_RVC_IMM (imm_expr
->X_add_number
)
1293 || imm_expr
->X_add_number
<= 0
1294 || imm_expr
->X_add_number
>= 32)
1296 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1299 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1300 || imm_expr
->X_op
!= O_constant
1301 || imm_expr
->X_add_number
== 0
1302 || !VALID_RVC_SIMM3 (imm_expr
->X_add_number
))
1304 ip
->insn_opcode
|= ENCODE_RVC_SIMM3 (imm_expr
->X_add_number
);
1307 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1308 || imm_expr
->X_op
!= O_constant
1309 || imm_expr
->X_add_number
== 0
1310 || !VALID_RVC_IMM (imm_expr
->X_add_number
))
1312 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1315 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1316 || imm_expr
->X_op
!= O_constant
1317 || !VALID_RVC_LW_IMM (imm_expr
->X_add_number
))
1319 ip
->insn_opcode
|= ENCODE_RVC_LW_IMM (imm_expr
->X_add_number
);
1322 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1323 || imm_expr
->X_op
!= O_constant
1324 || !VALID_RVC_LD_IMM (imm_expr
->X_add_number
))
1326 ip
->insn_opcode
|= ENCODE_RVC_LD_IMM (imm_expr
->X_add_number
);
1329 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1330 || imm_expr
->X_op
!= O_constant
1331 || !VALID_RVC_LWSP_IMM (imm_expr
->X_add_number
))
1334 ENCODE_RVC_LWSP_IMM (imm_expr
->X_add_number
);
1337 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1338 || imm_expr
->X_op
!= O_constant
1339 || !VALID_RVC_LDSP_IMM (imm_expr
->X_add_number
))
1342 ENCODE_RVC_LDSP_IMM (imm_expr
->X_add_number
);
1345 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1346 || imm_expr
->X_op
!= O_constant
1347 || !VALID_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
)
1348 || imm_expr
->X_add_number
== 0)
1351 ENCODE_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
);
1354 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1355 || imm_expr
->X_op
!= O_constant
1356 || !VALID_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
)
1357 || imm_expr
->X_add_number
== 0)
1360 ENCODE_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
);
1363 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1364 || imm_expr
->X_op
!= O_constant
1365 || !VALID_RVC_SWSP_IMM (imm_expr
->X_add_number
))
1368 ENCODE_RVC_SWSP_IMM (imm_expr
->X_add_number
);
1371 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1372 || imm_expr
->X_op
!= O_constant
1373 || !VALID_RVC_SDSP_IMM (imm_expr
->X_add_number
))
1376 ENCODE_RVC_SDSP_IMM (imm_expr
->X_add_number
);
1379 p
= percent_op_utype
;
1380 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
1383 if (imm_expr
->X_op
!= O_constant
1384 || imm_expr
->X_add_number
<= 0
1385 || imm_expr
->X_add_number
>= RISCV_BIGIMM_REACH
1386 || (imm_expr
->X_add_number
>= RISCV_RVC_IMM_REACH
/ 2
1387 && (imm_expr
->X_add_number
<
1388 RISCV_BIGIMM_REACH
- RISCV_RVC_IMM_REACH
/ 2)))
1390 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1393 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1394 || (imm_expr
->X_add_number
& (RISCV_IMM_REACH
- 1))
1395 || ((int32_t)imm_expr
->X_add_number
1396 != imm_expr
->X_add_number
))
1398 imm_expr
->X_add_number
=
1399 ((uint32_t) imm_expr
->X_add_number
) >> RISCV_IMM_BITS
;
1405 case 'D': /* Floating-point RS2 x8-x15. */
1406 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
1407 || !(regno
>= 8 && regno
<= 15))
1409 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
1411 case 'T': /* Floating-point RS2. */
1412 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
))
1414 INSERT_OPERAND (CRS2
, *ip
, regno
);
1417 as_bad (_("bad RVC field specifier 'C%c'\n"), *args
);
1436 case '<': /* Shift amount, 0 - 31. */
1437 my_getExpression (imm_expr
, s
);
1438 check_absolute_expr (ip
, imm_expr
);
1439 if ((unsigned long) imm_expr
->X_add_number
> 31)
1440 as_warn (_("Improper shift amount (%lu)"),
1441 (unsigned long) imm_expr
->X_add_number
);
1442 INSERT_OPERAND (SHAMTW
, *ip
, imm_expr
->X_add_number
);
1443 imm_expr
->X_op
= O_absent
;
1447 case '>': /* Shift amount, 0 - (XLEN-1). */
1448 my_getExpression (imm_expr
, s
);
1449 check_absolute_expr (ip
, imm_expr
);
1450 if ((unsigned long) imm_expr
->X_add_number
>= xlen
)
1451 as_warn (_("Improper shift amount (%lu)"),
1452 (unsigned long) imm_expr
->X_add_number
);
1453 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
->X_add_number
);
1454 imm_expr
->X_op
= O_absent
;
1458 case 'Z': /* CSRRxI immediate. */
1459 my_getExpression (imm_expr
, s
);
1460 check_absolute_expr (ip
, imm_expr
);
1461 if ((unsigned long) imm_expr
->X_add_number
> 31)
1462 as_warn (_("Improper CSRxI immediate (%lu)"),
1463 (unsigned long) imm_expr
->X_add_number
);
1464 INSERT_OPERAND (RS1
, *ip
, imm_expr
->X_add_number
);
1465 imm_expr
->X_op
= O_absent
;
1469 case 'E': /* Control register. */
1470 if (reg_lookup (&s
, RCLASS_CSR
, ®no
))
1471 INSERT_OPERAND (CSR
, *ip
, regno
);
1474 my_getExpression (imm_expr
, s
);
1475 check_absolute_expr (ip
, imm_expr
);
1476 if ((unsigned long) imm_expr
->X_add_number
> 0xfff)
1477 as_warn (_("Improper CSR address (%lu)"),
1478 (unsigned long) imm_expr
->X_add_number
);
1479 INSERT_OPERAND (CSR
, *ip
, imm_expr
->X_add_number
);
1480 imm_expr
->X_op
= O_absent
;
1485 case 'm': /* Rounding mode. */
1486 if (arg_lookup (&s
, riscv_rm
, ARRAY_SIZE (riscv_rm
), ®no
))
1488 INSERT_OPERAND (RM
, *ip
, regno
);
1494 case 'Q': /* Fence predecessor/successor. */
1495 if (arg_lookup (&s
, riscv_pred_succ
, ARRAY_SIZE (riscv_pred_succ
),
1499 INSERT_OPERAND (PRED
, *ip
, regno
);
1501 INSERT_OPERAND (SUCC
, *ip
, regno
);
1506 case 'd': /* Destination register. */
1507 case 's': /* Source register. */
1508 case 't': /* Target register. */
1509 if (reg_lookup (&s
, RCLASS_GPR
, ®no
))
1515 /* Now that we have assembled one operand, we use the args
1516 string to figure out where it goes in the instruction. */
1520 INSERT_OPERAND (RS1
, *ip
, regno
);
1523 INSERT_OPERAND (RD
, *ip
, regno
);
1526 INSERT_OPERAND (RS2
, *ip
, regno
);
1533 case 'D': /* Floating point rd. */
1534 case 'S': /* Floating point rs1. */
1535 case 'T': /* Floating point rs2. */
1536 case 'U': /* Floating point rs1 and rs2. */
1537 case 'R': /* Floating point rs3. */
1538 if (reg_lookup (&s
, RCLASS_FPR
, ®no
))
1546 INSERT_OPERAND (RD
, *ip
, regno
);
1549 INSERT_OPERAND (RS1
, *ip
, regno
);
1552 INSERT_OPERAND (RS1
, *ip
, regno
);
1555 INSERT_OPERAND (RS2
, *ip
, regno
);
1558 INSERT_OPERAND (RS3
, *ip
, regno
);
1567 my_getExpression (imm_expr
, s
);
1568 if (imm_expr
->X_op
!= O_big
1569 && imm_expr
->X_op
!= O_constant
)
1571 normalize_constant_expr (imm_expr
);
1576 my_getExpression (imm_expr
, s
);
1577 normalize_constant_expr (imm_expr
);
1578 /* The 'A' format specifier must be a symbol. */
1579 if (imm_expr
->X_op
!= O_symbol
)
1581 *imm_reloc
= BFD_RELOC_32
;
1585 case 'j': /* Sign-extended immediate. */
1586 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
1587 p
= percent_op_itype
;
1589 case 'q': /* Store displacement. */
1590 p
= percent_op_stype
;
1591 *imm_reloc
= BFD_RELOC_RISCV_LO12_S
;
1593 case 'o': /* Load displacement. */
1594 p
= percent_op_itype
;
1595 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
1597 case '0': /* AMO "displacement," which must be zero. */
1598 p
= percent_op_rtype
;
1599 *imm_reloc
= BFD_RELOC_UNUSED
;
1601 /* Check whether there is only a single bracketed expression
1602 left. If so, it must be the base register and the
1603 constant must be zero. */
1604 imm_expr
->X_op
= O_constant
;
1605 imm_expr
->X_add_number
= 0;
1606 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
1609 /* If this value won't fit into a 16 bit offset, then go
1610 find a macro that will generate the 32 bit offset
1612 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
1614 normalize_constant_expr (imm_expr
);
1615 if (imm_expr
->X_op
!= O_constant
1616 || (*args
== '0' && imm_expr
->X_add_number
!= 0)
1617 || imm_expr
->X_add_number
>= (signed)RISCV_IMM_REACH
/2
1618 || imm_expr
->X_add_number
< -(signed)RISCV_IMM_REACH
/2)
1625 case 'p': /* PC-relative offset. */
1627 *imm_reloc
= BFD_RELOC_12_PCREL
;
1628 my_getExpression (imm_expr
, s
);
1632 case 'u': /* Upper 20 bits. */
1633 p
= percent_op_utype
;
1634 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1635 && imm_expr
->X_op
== O_constant
)
1637 if (imm_expr
->X_add_number
< 0
1638 || imm_expr
->X_add_number
>= (signed)RISCV_BIGIMM_REACH
)
1639 as_bad (_("lui expression not in range 0..1048575"));
1641 *imm_reloc
= BFD_RELOC_RISCV_HI20
;
1642 imm_expr
->X_add_number
<<= RISCV_IMM_BITS
;
1647 case 'a': /* 20-bit PC-relative offset. */
1649 my_getExpression (imm_expr
, s
);
1651 *imm_reloc
= BFD_RELOC_RISCV_JMP
;
1655 my_getExpression (imm_expr
, s
);
1657 if (strcmp (s
, "@plt") == 0)
1659 *imm_reloc
= BFD_RELOC_RISCV_CALL_PLT
;
1663 *imm_reloc
= BFD_RELOC_RISCV_CALL
;
1667 as_fatal (_("internal error: bad argument type %c"), *args
);
1672 error
= _("illegal operands");
1676 /* Restore the character we might have clobbered above. */
1678 *(argsStart
- 1) = save_c
;
1684 md_assemble (char *str
)
1686 struct riscv_cl_insn insn
;
1687 expressionS imm_expr
;
1688 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
1690 const char *error
= riscv_ip (str
, &insn
, &imm_expr
, &imm_reloc
);
1694 as_bad ("%s `%s'", error
, str
);
1698 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1699 macro (&insn
, &imm_expr
, &imm_reloc
);
1701 append_insn (&insn
, &imm_expr
, imm_reloc
);
1705 md_atof (int type
, char *litP
, int *sizeP
)
1707 return ieee_md_atof (type
, litP
, sizeP
, TARGET_BYTES_BIG_ENDIAN
);
1711 md_number_to_chars (char *buf
, valueT val
, int n
)
1713 number_to_chars_littleendian (buf
, val
, n
);
1716 const char *md_shortopts
= "O::g::G:";
1720 OPTION_M32
= OPTION_MD_BASE
,
1732 struct option md_longopts
[] =
1734 {"m32", no_argument
, NULL
, OPTION_M32
},
1735 {"m64", no_argument
, NULL
, OPTION_M64
},
1736 {"march", required_argument
, NULL
, OPTION_MARCH
},
1737 {"fPIC", no_argument
, NULL
, OPTION_PIC
},
1738 {"fpic", no_argument
, NULL
, OPTION_PIC
},
1739 {"fno-pic", no_argument
, NULL
, OPTION_NO_PIC
},
1740 {"mrvc", no_argument
, NULL
, OPTION_MRVC
},
1741 {"mno-rvc", no_argument
, NULL
, OPTION_MNO_RVC
},
1742 {"msoft-float", no_argument
, NULL
, OPTION_MSOFT_FLOAT
},
1743 {"mhard-float", no_argument
, NULL
, OPTION_MHARD_FLOAT
},
1745 {NULL
, no_argument
, NULL
, 0}
1747 size_t md_longopts_size
= sizeof (md_longopts
);
1755 static enum float_mode float_mode
= FLOAT_MODE_DEFAULT
;
1758 md_parse_option (int c
, const char *arg
)
1763 riscv_set_rvc (TRUE
);
1766 case OPTION_MNO_RVC
:
1767 riscv_set_rvc (FALSE
);
1770 case OPTION_MSOFT_FLOAT
:
1771 float_mode
= FLOAT_MODE_SOFT
;
1774 case OPTION_MHARD_FLOAT
:
1775 float_mode
= FLOAT_MODE_HARD
;
1787 riscv_set_arch (arg
);
1791 riscv_opts
.pic
= FALSE
;
1795 riscv_opts
.pic
= TRUE
;
1806 riscv_after_parse_args (void)
1808 if (riscv_subsets
== NULL
)
1809 riscv_set_arch ("RVIMAFD");
1813 if (strcmp (default_arch
, "riscv32") == 0)
1815 else if (strcmp (default_arch
, "riscv64") == 0)
1818 as_bad ("unknown default architecture `%s'", default_arch
);
1823 md_pcrel_from (fixS
*fixP
)
1825 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
1828 /* Apply a fixup to the object file. */
1831 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
1833 unsigned int subtype
;
1834 bfd_byte
*buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
1835 bfd_boolean relaxable
= FALSE
;
1837 /* Remember value for tc_gen_reloc. */
1838 fixP
->fx_addnumber
= *valP
;
1840 switch (fixP
->fx_r_type
)
1842 case BFD_RELOC_RISCV_HI20
:
1843 case BFD_RELOC_RISCV_LO12_I
:
1844 case BFD_RELOC_RISCV_LO12_S
:
1845 bfd_putl32 (riscv_apply_const_reloc (fixP
->fx_r_type
, *valP
)
1846 | bfd_getl32 (buf
), buf
);
1850 case BFD_RELOC_RISCV_GOT_HI20
:
1851 case BFD_RELOC_RISCV_PCREL_HI20
:
1852 case BFD_RELOC_RISCV_ADD8
:
1853 case BFD_RELOC_RISCV_ADD16
:
1854 case BFD_RELOC_RISCV_ADD32
:
1855 case BFD_RELOC_RISCV_ADD64
:
1856 case BFD_RELOC_RISCV_SUB6
:
1857 case BFD_RELOC_RISCV_SUB8
:
1858 case BFD_RELOC_RISCV_SUB16
:
1859 case BFD_RELOC_RISCV_SUB32
:
1860 case BFD_RELOC_RISCV_SUB64
:
1861 case BFD_RELOC_RISCV_RELAX
:
1864 case BFD_RELOC_RISCV_TPREL_HI20
:
1865 case BFD_RELOC_RISCV_TPREL_LO12_I
:
1866 case BFD_RELOC_RISCV_TPREL_LO12_S
:
1867 case BFD_RELOC_RISCV_TPREL_ADD
:
1871 case BFD_RELOC_RISCV_TLS_GOT_HI20
:
1872 case BFD_RELOC_RISCV_TLS_GD_HI20
:
1873 case BFD_RELOC_RISCV_TLS_DTPREL32
:
1874 case BFD_RELOC_RISCV_TLS_DTPREL64
:
1875 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
1882 case BFD_RELOC_RISCV_CFA
:
1883 if (fixP
->fx_addsy
&& fixP
->fx_subsy
)
1885 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
1886 fixP
->fx_next
->fx_addsy
= fixP
->fx_subsy
;
1887 fixP
->fx_next
->fx_subsy
= NULL
;
1888 fixP
->fx_next
->fx_offset
= 0;
1889 fixP
->fx_subsy
= NULL
;
1891 switch (fixP
->fx_r_type
)
1894 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD64
;
1895 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB64
;
1899 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD32
;
1900 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
1904 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD16
;
1905 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
1909 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD8
;
1910 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
1913 case BFD_RELOC_RISCV_CFA
:
1914 /* Load the byte to get the subtype. */
1915 subtype
= bfd_get_8 (NULL
, &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
]);
1918 case DW_CFA_advance_loc1
:
1920 fixP
->fx_next
->fx_where
++;
1921 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET8
;
1922 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
1925 case DW_CFA_advance_loc2
:
1928 fixP
->fx_next
->fx_size
= 2;
1929 fixP
->fx_next
->fx_where
++;
1930 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET16
;
1931 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
1934 case DW_CFA_advance_loc4
:
1937 fixP
->fx_next
->fx_size
= 4;
1938 fixP
->fx_next
->fx_where
++;
1939 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET32
;
1940 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
1944 if (subtype
< 0x80 && (subtype
& 0x40))
1946 /* DW_CFA_advance_loc */
1947 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET6
;
1948 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB6
;
1951 as_fatal (_("internal error: bad CFA value #%d"), subtype
);
1957 /* This case is unreachable. */
1964 /* If we are deleting this reloc entry, we must fill in the
1965 value now. This can happen if we have a .word which is not
1966 resolved when it appears but is later defined. */
1967 if (fixP
->fx_addsy
== NULL
)
1969 gas_assert (fixP
->fx_size
<= sizeof (valueT
));
1970 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
1975 case BFD_RELOC_RISCV_JMP
:
1978 /* Fill in a tentative value to improve objdump readability. */
1979 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
1980 bfd_vma delta
= target
- md_pcrel_from (fixP
);
1981 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_UJTYPE_IMM (delta
), buf
);
1985 case BFD_RELOC_12_PCREL
:
1988 /* Fill in a tentative value to improve objdump readability. */
1989 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
1990 bfd_vma delta
= target
- md_pcrel_from (fixP
);
1991 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_SBTYPE_IMM (delta
), buf
);
1995 case BFD_RELOC_RISCV_RVC_BRANCH
:
1998 /* Fill in a tentative value to improve objdump readability. */
1999 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2000 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2001 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_B_IMM (delta
), buf
);
2005 case BFD_RELOC_RISCV_RVC_JUMP
:
2008 /* Fill in a tentative value to improve objdump readability. */
2009 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2010 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2011 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_J_IMM (delta
), buf
);
2015 case BFD_RELOC_RISCV_CALL
:
2016 case BFD_RELOC_RISCV_CALL_PLT
:
2020 case BFD_RELOC_RISCV_PCREL_LO12_S
:
2021 case BFD_RELOC_RISCV_PCREL_LO12_I
:
2022 case BFD_RELOC_RISCV_ALIGN
:
2026 /* We ignore generic BFD relocations we don't know about. */
2027 if (bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
) != NULL
)
2028 as_fatal (_("internal error: bad relocation #%d"), fixP
->fx_r_type
);
2031 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
2032 if (relaxable
&& fixP
->fx_tcbit
&& fixP
->fx_addsy
!= NULL
)
2034 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
2035 fixP
->fx_next
->fx_addsy
= fixP
->fx_next
->fx_subsy
= NULL
;
2036 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_RELAX
;
2040 /* Because the value of .cfi_remember_state may changed after relaxation,
2041 we insert a fix to relocate it again in link-time. */
2044 riscv_pre_output_hook (void)
2046 const frchainS
*frch
;
2049 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
2050 for (frch
= seg_info (s
)->frchainP
; frch
; frch
= frch
->frch_next
)
2054 for (frag
= frch
->frch_root
; frag
; frag
= frag
->fr_next
)
2056 if (frag
->fr_type
== rs_cfa
)
2058 const fragS
*loc4_frag
;
2061 symbolS
*add_symbol
= frag
->fr_symbol
->sy_value
.X_add_symbol
;
2062 symbolS
*op_symbol
= frag
->fr_symbol
->sy_value
.X_op_symbol
;
2064 exp
.X_op
= O_subtract
;
2065 exp
.X_add_symbol
= add_symbol
;
2066 exp
.X_add_number
= 0;
2067 exp
.X_op_symbol
= op_symbol
;
2069 loc4_frag
= (fragS
*) frag
->fr_opcode
;
2070 fix_new_exp (loc4_frag
, (int) frag
->fr_offset
, 1, &exp
, 0,
2071 BFD_RELOC_RISCV_CFA
);
2078 /* This structure is used to hold a stack of .option values. */
2080 struct riscv_option_stack
2082 struct riscv_option_stack
*next
;
2083 struct riscv_set_options options
;
2086 static struct riscv_option_stack
*riscv_opts_stack
;
2088 /* Handle the .option pseudo-op. */
2091 s_riscv_option (int x ATTRIBUTE_UNUSED
)
2093 char *name
= input_line_pointer
, ch
;
2095 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2096 ++input_line_pointer
;
2097 ch
= *input_line_pointer
;
2098 *input_line_pointer
= '\0';
2100 if (strcmp (name
, "rvc") == 0)
2101 riscv_set_rvc (TRUE
);
2102 else if (strcmp (name
, "norvc") == 0)
2103 riscv_set_rvc (FALSE
);
2104 else if (strcmp (name
, "pic") == 0)
2105 riscv_opts
.pic
= TRUE
;
2106 else if (strcmp (name
, "nopic") == 0)
2107 riscv_opts
.pic
= FALSE
;
2108 else if (strcmp (name
, "relax") == 0)
2109 riscv_opts
.relax
= TRUE
;
2110 else if (strcmp (name
, "norelax") == 0)
2111 riscv_opts
.relax
= FALSE
;
2112 else if (strcmp (name
, "push") == 0)
2114 struct riscv_option_stack
*s
;
2116 s
= (struct riscv_option_stack
*) xmalloc (sizeof *s
);
2117 s
->next
= riscv_opts_stack
;
2118 s
->options
= riscv_opts
;
2119 riscv_opts_stack
= s
;
2121 else if (strcmp (name
, "pop") == 0)
2123 struct riscv_option_stack
*s
;
2125 s
= riscv_opts_stack
;
2127 as_bad (_(".option pop with no .option push"));
2130 riscv_opts
= s
->options
;
2131 riscv_opts_stack
= s
->next
;
2137 as_warn (_("Unrecognized .option directive: %s\n"), name
);
2139 *input_line_pointer
= ch
;
2140 demand_empty_rest_of_line ();
2143 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
2144 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
2145 use in DWARF debug information. */
2148 s_dtprel (int bytes
)
2155 if (ex
.X_op
!= O_symbol
)
2157 as_bad (_("Unsupported use of %s"), (bytes
== 8
2160 ignore_rest_of_line ();
2163 p
= frag_more (bytes
);
2164 md_number_to_chars (p
, 0, bytes
);
2165 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
,
2167 ? BFD_RELOC_RISCV_TLS_DTPREL64
2168 : BFD_RELOC_RISCV_TLS_DTPREL32
));
2170 demand_empty_rest_of_line ();
2173 /* Handle the .bss pseudo-op. */
2176 s_bss (int ignore ATTRIBUTE_UNUSED
)
2178 subseg_set (bss_section
, 0);
2179 demand_empty_rest_of_line ();
2182 /* Align to a given power of two. */
2185 s_align (int bytes_p
)
2187 int fill_value
= 0, fill_value_specified
= 0;
2188 int min_text_alignment
= riscv_opts
.rvc
? 2 : 4;
2189 int alignment
= get_absolute_expression(), bytes
;
2194 if (bytes
< 1 || (bytes
& (bytes
-1)) != 0)
2195 as_bad (_("alignment not a power of 2: %d"), bytes
);
2196 for (alignment
= 0; bytes
> 1; bytes
>>= 1)
2200 bytes
= 1 << alignment
;
2202 if (alignment
< 0 || alignment
> 31)
2203 as_bad (_("unsatisfiable alignment: %d"), alignment
);
2205 if (*input_line_pointer
== ',')
2207 ++input_line_pointer
;
2208 fill_value
= get_absolute_expression ();
2209 fill_value_specified
= 1;
2212 if (!fill_value_specified
2213 && subseg_text_p (now_seg
)
2214 && bytes
> min_text_alignment
)
2216 /* Emit the worst-case NOP string. The linker will delete any
2217 unnecessary NOPs. This allows us to support code alignment
2218 in spite of linker relaxations. */
2219 bfd_vma i
, worst_case_bytes
= bytes
- min_text_alignment
;
2220 char *nops
= frag_more (worst_case_bytes
);
2221 for (i
= 0; i
< worst_case_bytes
- 2; i
+= 4)
2222 md_number_to_chars (nops
+ i
, RISCV_NOP
, 4);
2223 if (i
< worst_case_bytes
)
2224 md_number_to_chars (nops
+ i
, RVC_NOP
, 2);
2227 ex
.X_op
= O_constant
;
2228 ex
.X_add_number
= worst_case_bytes
;
2230 fix_new_exp (frag_now
, nops
- frag_now
->fr_literal
, 0,
2231 &ex
, FALSE
, BFD_RELOC_RISCV_ALIGN
);
2234 frag_align (alignment
, fill_value
, 0);
2236 record_alignment (now_seg
, alignment
);
2238 demand_empty_rest_of_line ();
2242 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
2244 return (fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
));
2247 /* Translate internal representation of relocation info to BFD target
2251 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
2253 arelent
*reloc
= (arelent
*) xmalloc (sizeof (arelent
));
2255 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
2256 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
2257 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
2258 reloc
->addend
= fixp
->fx_addnumber
;
2260 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
2261 if (reloc
->howto
== NULL
)
2263 if ((fixp
->fx_r_type
== BFD_RELOC_16
|| fixp
->fx_r_type
== BFD_RELOC_8
)
2264 && fixp
->fx_addsy
!= NULL
&& fixp
->fx_subsy
!= NULL
)
2266 /* We don't have R_RISCV_8/16, but for this special case,
2267 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
2271 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
2272 _("cannot represent %s relocation in object file"),
2273 bfd_get_reloc_code_name (fixp
->fx_r_type
));
2281 riscv_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
2283 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
2285 offsetT old_var
= fragp
->fr_var
;
2286 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
2287 return fragp
->fr_var
- old_var
;
2293 /* Expand far branches to multi-instruction sequences. */
2296 md_convert_frag_branch (fragS
*fragp
)
2304 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
2306 exp
.X_op
= O_symbol
;
2307 exp
.X_add_symbol
= fragp
->fr_symbol
;
2308 exp
.X_add_number
= fragp
->fr_offset
;
2310 gas_assert (fragp
->fr_var
== RELAX_BRANCH_LENGTH (fragp
->fr_subtype
));
2312 if (RELAX_BRANCH_RVC (fragp
->fr_subtype
))
2314 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
2318 /* Expand the RVC branch into a RISC-V one. */
2319 insn
= bfd_getl16 (buf
);
2320 rs1
= 8 + ((insn
>> OP_SH_CRS1S
) & OP_MASK_CRS1S
);
2321 if ((insn
& MASK_C_J
) == MATCH_C_J
)
2323 else if ((insn
& MASK_C_JAL
) == MATCH_C_JAL
)
2324 insn
= MATCH_JAL
| (X_RA
<< OP_SH_RD
);
2325 else if ((insn
& MASK_C_BEQZ
) == MATCH_C_BEQZ
)
2326 insn
= MATCH_BEQ
| (rs1
<< OP_SH_RS1
);
2327 else if ((insn
& MASK_C_BNEZ
) == MATCH_C_BNEZ
)
2328 insn
= MATCH_BNE
| (rs1
<< OP_SH_RS1
);
2331 bfd_putl32 (insn
, buf
);
2335 /* Invert the branch condition. Branch over the jump. */
2336 insn
= bfd_getl16 (buf
);
2337 insn
^= MATCH_C_BEQZ
^ MATCH_C_BNEZ
;
2338 insn
|= ENCODE_RVC_B_IMM (6);
2339 bfd_putl16 (insn
, buf
);
2344 /* Just keep the RVC branch. */
2345 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
2346 ? BFD_RELOC_RISCV_RVC_JUMP
: BFD_RELOC_RISCV_RVC_BRANCH
;
2347 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
2348 2, &exp
, FALSE
, reloc
);
2357 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
2360 gas_assert (!RELAX_BRANCH_UNCOND (fragp
->fr_subtype
));
2362 /* Invert the branch condition. Branch over the jump. */
2363 insn
= bfd_getl32 (buf
);
2364 insn
^= MATCH_BEQ
^ MATCH_BNE
;
2365 insn
|= ENCODE_SBTYPE_IMM (8);
2366 md_number_to_chars ((char *) buf
, insn
, 4);
2370 /* Jump to the target. */
2371 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
2372 4, &exp
, FALSE
, BFD_RELOC_RISCV_JMP
);
2373 md_number_to_chars ((char *) buf
, MATCH_JAL
, 4);
2378 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
2379 ? BFD_RELOC_RISCV_JMP
: BFD_RELOC_12_PCREL
;
2380 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
2381 4, &exp
, FALSE
, reloc
);
2390 fixp
->fx_file
= fragp
->fr_file
;
2391 fixp
->fx_line
= fragp
->fr_line
;
2393 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
2394 + fragp
->fr_fix
+ fragp
->fr_var
);
2396 fragp
->fr_fix
+= fragp
->fr_var
;
2399 /* Relax a machine dependent frag. This returns the amount by which
2400 the current size of the frag should change. */
2403 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec ATTRIBUTE_UNUSED
,
2406 gas_assert (RELAX_BRANCH_P (fragp
->fr_subtype
));
2407 md_convert_frag_branch (fragp
);
2411 md_show_usage (FILE *stream
)
2413 fprintf (stream
, _("\
2415 -m32 assemble RV32 code\n\
2416 -m64 assemble RV64 code (default)\n\
2417 -fpic generate position-independent code\n\
2418 -fno-pic don't generate position-independent code (default)\n\
2419 -msoft-float don't use F registers for floating-point values\n\
2420 -mhard-float use F registers for floating-point values (default)\n\
2421 -mno-rvc disable the C extension for compressed instructions (default)\n\
2422 -mrvc enable the C extension for compressed instructions\n\
2423 -march=ISA set the RISC-V architecture, RV64IMAFD by default\n\
2427 /* Standard calling conventions leave the CFA at SP on entry. */
2429 riscv_cfi_frame_initial_instructions (void)
2431 cfi_add_CFA_def_cfa_register (X_SP
);
2435 tc_riscv_regname_to_dw2regnum (char *regname
)
2439 if ((reg
= reg_lookup_internal (regname
, RCLASS_GPR
)) >= 0)
2442 if ((reg
= reg_lookup_internal (regname
, RCLASS_FPR
)) >= 0)
2445 as_bad (_("unknown register `%s'"), regname
);
2450 riscv_elf_final_processing (void)
2452 enum float_mode elf_float_mode
= float_mode
;
2454 elf_elfheader (stdoutput
)->e_flags
|= elf_flags
;
2456 if (elf_float_mode
== FLOAT_MODE_DEFAULT
)
2458 struct riscv_subset
*subset
;
2460 /* Assume soft-float unless D extension is present. */
2461 elf_float_mode
= FLOAT_MODE_SOFT
;
2463 for (subset
= riscv_subsets
; subset
!= NULL
; subset
= subset
->next
)
2464 if (strcasecmp (subset
->name
, "D") == 0)
2465 elf_float_mode
= FLOAT_MODE_HARD
;
2468 if (elf_float_mode
== FLOAT_MODE_SOFT
)
2469 elf_elfheader (stdoutput
)->e_flags
|= EF_RISCV_SOFT_FLOAT
;
2472 /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
2473 since these directives break relaxation when used with symbol deltas. */
2476 s_riscv_leb128 (int sign
)
2479 char *save_in
= input_line_pointer
;
2482 if (exp
.X_op
!= O_constant
)
2483 as_bad (_("non-constant .%cleb128 is not supported"), sign
? 's' : 'u');
2484 demand_empty_rest_of_line ();
2486 input_line_pointer
= save_in
;
2487 return s_leb128 (sign
);
2490 /* Pseudo-op table. */
2492 static const pseudo_typeS riscv_pseudo_table
[] =
2494 /* RISC-V-specific pseudo-ops. */
2495 {"option", s_riscv_option
, 0},
2499 {"dtprelword", s_dtprel
, 4},
2500 {"dtpreldword", s_dtprel
, 8},
2502 {"align", s_align
, 0},
2503 {"p2align", s_align
, 0},
2504 {"balign", s_align
, 1},
2505 {"uleb128", s_riscv_leb128
, 0},
2506 {"sleb128", s_riscv_leb128
, 1},
2512 riscv_pop_insert (void)
2514 extern void pop_insert (const pseudo_typeS
*);
2516 pop_insert (riscv_pseudo_table
);