1 /* tc-riscv.c -- RISC-V assembler
2 Copyright (C) 2011-2021 Free Software Foundation, Inc.
4 Contributed by Andrew Waterman (andrew@sifive.com).
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
26 #include "safe-ctype.h"
29 #include "dwarf2dbg.h"
30 #include "dw2gencfi.h"
32 #include "bfd/cpu-riscv.h"
33 #include "bfd/elfxx-riscv.h"
34 #include "elf/riscv.h"
35 #include "opcode/riscv.h"
39 /* Information about an instruction, including its format, operands
43 /* The opcode's entry in riscv_opcodes. */
44 const struct riscv_opcode
*insn_mo
;
46 /* The encoded instruction bits. */
49 /* The frag that contains the instruction. */
52 /* The offset into FRAG of the first instruction byte. */
55 /* The relocs associated with the instruction, if any. */
59 /* All RISC-V CSR belong to one of these classes. */
65 CSR_CLASS_I_32
, /* rv32 only */
66 CSR_CLASS_F
, /* f-ext only */
67 CSR_CLASS_DEBUG
/* debug CSR */
70 /* This structure holds all restricted conditions for a CSR. */
71 struct riscv_csr_extra
73 /* Class to which this CSR belongs. Used to decide whether or
74 not this CSR is legal in the current -march context. */
75 enum riscv_csr_class csr_class
;
77 /* CSR may have differnet numbers in the previous priv spec. */
80 /* Record the CSR is defined/valid in which versions. */
81 enum riscv_spec_class define_version
;
83 /* Record the CSR is aborted/invalid from which versions. If it isn't
84 aborted in the current version, then it should be CSR_CLASS_VDRAFT. */
85 enum riscv_spec_class abort_version
;
87 /* The CSR may have more than one setting. */
88 struct riscv_csr_extra
*next
;
91 /* All standard/Z* extensions defined in all supported ISA spec. */
92 struct riscv_ext_version
95 enum riscv_spec_class isa_spec_class
;
100 static const struct riscv_ext_version ext_version_table
[] =
102 {"e", ISA_SPEC_CLASS_20191213
, 1, 9},
103 {"e", ISA_SPEC_CLASS_20190608
, 1, 9},
104 {"e", ISA_SPEC_CLASS_2P2
, 1, 9},
106 {"i", ISA_SPEC_CLASS_20191213
, 2, 1},
107 {"i", ISA_SPEC_CLASS_20190608
, 2, 1},
108 {"i", ISA_SPEC_CLASS_2P2
, 2, 0},
110 {"m", ISA_SPEC_CLASS_20191213
, 2, 0},
111 {"m", ISA_SPEC_CLASS_20190608
, 2, 0},
112 {"m", ISA_SPEC_CLASS_2P2
, 2, 0},
114 {"a", ISA_SPEC_CLASS_20191213
, 2, 1},
115 {"a", ISA_SPEC_CLASS_20190608
, 2, 0},
116 {"a", ISA_SPEC_CLASS_2P2
, 2, 0},
118 {"f", ISA_SPEC_CLASS_20191213
, 2, 2},
119 {"f", ISA_SPEC_CLASS_20190608
, 2, 2},
120 {"f", ISA_SPEC_CLASS_2P2
, 2, 0},
122 {"d", ISA_SPEC_CLASS_20191213
, 2, 2},
123 {"d", ISA_SPEC_CLASS_20190608
, 2, 2},
124 {"d", ISA_SPEC_CLASS_2P2
, 2, 0},
126 {"q", ISA_SPEC_CLASS_20191213
, 2, 2},
127 {"q", ISA_SPEC_CLASS_20190608
, 2, 2},
128 {"q", ISA_SPEC_CLASS_2P2
, 2, 0},
130 {"c", ISA_SPEC_CLASS_20191213
, 2, 0},
131 {"c", ISA_SPEC_CLASS_20190608
, 2, 0},
132 {"c", ISA_SPEC_CLASS_2P2
, 2, 0},
134 {"zicsr", ISA_SPEC_CLASS_20191213
, 2, 0},
135 {"zicsr", ISA_SPEC_CLASS_20190608
, 2, 0},
137 {"zifencei", ISA_SPEC_CLASS_20191213
, 2, 0},
138 {"zifencei", ISA_SPEC_CLASS_20190608
, 2, 0},
140 {"zihintpause", ISA_SPEC_CLASS_DRAFT
, 1, 0},
142 {"zbb", ISA_SPEC_CLASS_DRAFT
, 0, 93},
143 {"zba", ISA_SPEC_CLASS_DRAFT
, 0, 93},
144 {"zbc", ISA_SPEC_CLASS_DRAFT
, 0, 93},
146 /* Terminate the list. */
151 #define DEFAULT_ARCH "riscv64"
154 #ifndef DEFAULT_RISCV_ATTR
155 #define DEFAULT_RISCV_ATTR 0
158 /* Let riscv_after_parse_args set the default value according to xlen. */
159 #ifndef DEFAULT_RISCV_ARCH_WITH_EXT
160 #define DEFAULT_RISCV_ARCH_WITH_EXT NULL
163 /* Need to sync the version with RISC-V compiler. */
164 #ifndef DEFAULT_RISCV_ISA_SPEC
165 #define DEFAULT_RISCV_ISA_SPEC "2.2"
168 #ifndef DEFAULT_RISCV_PRIV_SPEC
169 #define DEFAULT_RISCV_PRIV_SPEC "1.11"
172 static const char default_arch
[] = DEFAULT_ARCH
;
173 static const char *default_arch_with_ext
= DEFAULT_RISCV_ARCH_WITH_EXT
;
174 static enum riscv_spec_class default_isa_spec
= ISA_SPEC_CLASS_NONE
;
175 static enum riscv_spec_class default_priv_spec
= PRIV_SPEC_CLASS_NONE
;
177 static unsigned xlen
= 0; /* The width of an x-register. */
178 static unsigned abi_xlen
= 0; /* The width of a pointer in the ABI. */
179 static bool rve_abi
= false;
182 FLOAT_ABI_DEFAULT
= -1,
188 static enum float_abi float_abi
= FLOAT_ABI_DEFAULT
;
190 #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
191 #define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
193 static unsigned elf_flags
= 0;
195 /* Set the default_isa_spec. Return 0 if the spec isn't supported.
196 Otherwise, return 1. */
199 riscv_set_default_isa_spec (const char *s
)
201 enum riscv_spec_class
class = ISA_SPEC_CLASS_NONE
;
202 RISCV_GET_ISA_SPEC_CLASS (s
, class);
203 if (class == ISA_SPEC_CLASS_NONE
)
205 as_bad ("unknown default ISA spec `%s' set by "
206 "-misa-spec or --with-isa-spec", s
);
210 default_isa_spec
= class;
214 /* Set the default_priv_spec. Find the privileged elf attributes when
215 the input string is NULL. Return 0 if the spec isn't supported.
216 Otherwise, return 1. */
219 riscv_set_default_priv_spec (const char *s
)
221 enum riscv_spec_class
class = PRIV_SPEC_CLASS_NONE
;
222 unsigned major
, minor
, revision
;
225 RISCV_GET_PRIV_SPEC_CLASS (s
, class);
226 if (class != PRIV_SPEC_CLASS_NONE
)
228 default_priv_spec
= class;
234 as_bad (_("unknown default privileged spec `%s' set by "
235 "-mpriv-spec or --with-priv-spec"), s
);
239 /* Set the default_priv_spec by the privileged elf attributes. */
240 attr
= elf_known_obj_attributes_proc (stdoutput
);
241 major
= (unsigned) attr
[Tag_RISCV_priv_spec
].i
;
242 minor
= (unsigned) attr
[Tag_RISCV_priv_spec_minor
].i
;
243 revision
= (unsigned) attr
[Tag_RISCV_priv_spec_revision
].i
;
244 /* Version 0.0.0 is the default value and meningless. */
245 if (major
== 0 && minor
== 0 && revision
== 0)
248 riscv_get_priv_spec_class_from_numbers (major
, minor
, revision
, &class);
249 if (class != PRIV_SPEC_CLASS_NONE
)
251 default_priv_spec
= class;
255 /* Still can not find the privileged spec class. */
256 as_bad (_("unknown default privileged spec `%d.%d.%d' set by "
257 "privileged elf attributes"), major
, minor
, revision
);
261 /* This is the set of options which the .option pseudo-op may modify. */
262 struct riscv_set_options
264 int pic
; /* Generate position-independent code. */
265 int rvc
; /* Generate RVC code. */
266 int rve
; /* Generate RVE code. */
267 int relax
; /* Emit relocs the linker is allowed to relax. */
268 int arch_attr
; /* Emit architecture and privileged elf attributes. */
269 int csr_check
; /* Enable the CSR checking. */
272 static struct riscv_set_options riscv_opts
=
278 DEFAULT_RISCV_ATTR
, /* arch_attr */
283 riscv_set_rvc (bool rvc_value
)
286 elf_flags
|= EF_RISCV_RVC
;
288 riscv_opts
.rvc
= rvc_value
;
292 riscv_set_rve (bool rve_value
)
294 riscv_opts
.rve
= rve_value
;
297 static riscv_subset_list_t riscv_subsets
;
300 riscv_subset_supports (const char *feature
)
302 struct riscv_subset_t
*subset
;
304 if (riscv_opts
.rvc
&& (strcasecmp (feature
, "c") == 0))
307 return riscv_lookup_subset (&riscv_subsets
, feature
, &subset
);
311 riscv_multi_subset_supports (enum riscv_insn_class insn_class
)
315 case INSN_CLASS_I
: return riscv_subset_supports ("i");
316 case INSN_CLASS_C
: return riscv_subset_supports ("c");
317 case INSN_CLASS_A
: return riscv_subset_supports ("a");
318 case INSN_CLASS_M
: return riscv_subset_supports ("m");
319 case INSN_CLASS_F
: return riscv_subset_supports ("f");
320 case INSN_CLASS_D
: return riscv_subset_supports ("d");
321 case INSN_CLASS_Q
: return riscv_subset_supports ("q");
323 case INSN_CLASS_F_AND_C
:
324 return (riscv_subset_supports ("f")
325 && riscv_subset_supports ("c"));
326 case INSN_CLASS_D_AND_C
:
327 return (riscv_subset_supports ("d")
328 && riscv_subset_supports ("c"));
330 case INSN_CLASS_ZICSR
:
331 return riscv_subset_supports ("zicsr");
332 case INSN_CLASS_ZIFENCEI
:
333 return riscv_subset_supports ("zifencei");
334 case INSN_CLASS_ZIHINTPAUSE
:
335 return riscv_subset_supports ("zihintpause");
338 return riscv_subset_supports ("zbb");
341 return riscv_subset_supports ("zba");
344 return riscv_subset_supports ("zbc");
347 as_fatal ("internal: unreachable");
352 /* Handle of the extension with version hash table. */
353 static htab_t ext_version_hash
= NULL
;
356 init_ext_version_hash (void)
358 const struct riscv_ext_version
*table
= ext_version_table
;
359 htab_t hash
= str_htab_create ();
362 while (table
[i
].name
)
364 const char *name
= table
[i
].name
;
365 if (str_hash_insert (hash
, name
, &table
[i
], 0) != NULL
)
366 as_fatal (_("internal: duplicate %s"), name
);
370 && strcmp (table
[i
].name
, name
) == 0)
378 riscv_get_default_ext_version (const char *name
,
382 struct riscv_ext_version
*ext
;
384 if (name
== NULL
|| default_isa_spec
== ISA_SPEC_CLASS_NONE
)
387 ext
= (struct riscv_ext_version
*) str_hash_find (ext_version_hash
, name
);
390 && strcmp (ext
->name
, name
) == 0)
392 if (ext
->isa_spec_class
== ISA_SPEC_CLASS_DRAFT
393 || ext
->isa_spec_class
== default_isa_spec
)
395 *major_version
= ext
->major_version
;
396 *minor_version
= ext
->minor_version
;
403 /* Set which ISA and extensions are available. */
406 riscv_set_arch (const char *s
)
408 riscv_parse_subset_t rps
;
409 rps
.subset_list
= &riscv_subsets
;
410 rps
.error_handler
= as_bad
;
412 rps
.get_default_version
= riscv_get_default_ext_version
;
413 rps
.check_unknown_prefixed_ext
= true;
418 riscv_release_subset_list (&riscv_subsets
);
419 riscv_parse_subset (&rps
, s
);
421 /* To support .option rvc and rve. */
422 riscv_set_rvc (false);
423 if (riscv_subset_supports ("c"))
424 riscv_set_rvc (true);
425 riscv_set_rve (false);
426 if (riscv_subset_supports ("e"))
427 riscv_set_rve (true);
430 /* Indicate -mabi option is explictly set. */
431 static bool explicit_mabi
= false;
434 riscv_set_abi (unsigned new_xlen
, enum float_abi new_float_abi
, bool rve
)
437 float_abi
= new_float_abi
;
441 /* If the -mabi option isn't set, then set the abi according to the
442 ISA string. Otherwise, check if there is any conflict. */
445 riscv_set_abi_by_arch (void)
449 if (riscv_subset_supports ("q"))
450 riscv_set_abi (xlen
, FLOAT_ABI_QUAD
, false);
451 else if (riscv_subset_supports ("d"))
452 riscv_set_abi (xlen
, FLOAT_ABI_DOUBLE
, false);
453 else if (riscv_subset_supports ("e"))
454 riscv_set_abi (xlen
, FLOAT_ABI_SOFT
, true);
456 riscv_set_abi (xlen
, FLOAT_ABI_SOFT
, false);
460 gas_assert (abi_xlen
!= 0 && xlen
!= 0 && float_abi
!= FLOAT_ABI_DEFAULT
);
462 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen
, xlen
);
463 else if (abi_xlen
< xlen
)
464 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen
, xlen
);
466 if (riscv_subset_supports ("e") && !rve_abi
)
467 as_bad ("only the ilp32e ABI is supported for e extension");
469 if (float_abi
== FLOAT_ABI_SINGLE
470 && !riscv_subset_supports ("f"))
471 as_bad ("ilp32f/lp64f ABI can't be used when f extension "
473 else if (float_abi
== FLOAT_ABI_DOUBLE
474 && !riscv_subset_supports ("d"))
475 as_bad ("ilp32d/lp64d ABI can't be used when d extension "
477 else if (float_abi
== FLOAT_ABI_QUAD
478 && !riscv_subset_supports ("q"))
479 as_bad ("ilp32q/lp64q ABI can't be used when q extension "
483 /* Update the EF_RISCV_FLOAT_ABI field of elf_flags. */
484 elf_flags
&= ~EF_RISCV_FLOAT_ABI
;
485 elf_flags
|= float_abi
<< 1;
488 elf_flags
|= EF_RISCV_RVE
;
491 /* Handle of the OPCODE hash table. */
492 static htab_t op_hash
= NULL
;
494 /* Handle of the type of .insn hash table. */
495 static htab_t insn_type_hash
= NULL
;
497 /* This array holds the chars that always start a comment. If the
498 pre-processor is disabled, these aren't very useful. */
499 const char comment_chars
[] = "#";
501 /* This array holds the chars that only start a comment at the beginning of
502 a line. If the line seems to have the form '# 123 filename'
503 .line and .file directives will appear in the pre-processed output
505 Note that input_file.c hand checks for '#' at the beginning of the
506 first line of the input file. This is because the compiler outputs
507 #NO_APP at the beginning of its output.
509 Also note that C style comments are always supported. */
510 const char line_comment_chars
[] = "#";
512 /* This array holds machine specific line separator characters. */
513 const char line_separator_chars
[] = ";";
515 /* Chars that can be used to separate mant from exp in floating point nums. */
516 const char EXP_CHARS
[] = "eE";
518 /* Chars that mean this number is a floating point constant.
519 As in 0f12.456 or 0d1.2345e12. */
520 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
522 /* Indicate we are already assemble any instructions or not. */
523 static bool start_assemble
= false;
525 /* Indicate ELF attributes are explicitly set. */
526 static bool explicit_attr
= false;
528 /* Indicate CSR or priv instructions are explicitly used. */
529 static bool explicit_priv_attr
= false;
531 /* Macros for encoding relaxation state for RVC branches and far jumps. */
532 #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
535 | ((uncond) ? 1 : 0) \
538 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
539 #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
540 #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
541 #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
543 /* Is the given value a sign-extended 32-bit value? */
544 #define IS_SEXT_32BIT_NUM(x) \
545 (((x) &~ (offsetT) 0x7fffffff) == 0 \
546 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
548 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
549 #define IS_ZEXT_32BIT_NUM(x) \
550 (((x) &~ (offsetT) 0xffffffff) == 0 \
551 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
553 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
554 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
555 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
556 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
558 /* Determine if an instruction matches an opcode. */
559 #define OPCODE_MATCHES(OPCODE, OP) \
560 (((OPCODE) & MASK_##OP) == MATCH_##OP)
562 static char *expr_end
;
564 /* The default target format to use. */
567 riscv_target_format (void)
569 if (target_big_endian
)
570 return xlen
== 64 ? "elf64-bigriscv" : "elf32-bigriscv";
572 return xlen
== 64 ? "elf64-littleriscv" : "elf32-littleriscv";
575 /* Return the length of instruction INSN. */
577 static inline unsigned int
578 insn_length (const struct riscv_cl_insn
*insn
)
580 return riscv_insn_length (insn
->insn_opcode
);
583 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
586 create_insn (struct riscv_cl_insn
*insn
, const struct riscv_opcode
*mo
)
589 insn
->insn_opcode
= mo
->match
;
595 /* Install INSN at the location specified by its "frag" and "where" fields. */
598 install_insn (const struct riscv_cl_insn
*insn
)
600 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
601 number_to_chars_littleendian (f
, insn
->insn_opcode
, insn_length (insn
));
604 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
605 and install the opcode in the new location. */
608 move_insn (struct riscv_cl_insn
*insn
, fragS
*frag
, long where
)
612 if (insn
->fixp
!= NULL
)
614 insn
->fixp
->fx_frag
= frag
;
615 insn
->fixp
->fx_where
= where
;
620 /* Add INSN to the end of the output. */
623 add_fixed_insn (struct riscv_cl_insn
*insn
)
625 char *f
= frag_more (insn_length (insn
));
626 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
630 add_relaxed_insn (struct riscv_cl_insn
*insn
, int max_chars
, int var
,
631 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
633 frag_grow (max_chars
);
634 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
635 frag_var (rs_machine_dependent
, max_chars
, var
,
636 subtype
, symbol
, offset
, NULL
);
639 /* Compute the length of a branch sequence, and adjust the stored length
640 accordingly. If FRAGP is NULL, the worst-case length is returned. */
643 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
645 int jump
, rvc
, length
= 8;
650 jump
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
);
651 rvc
= RELAX_BRANCH_RVC (fragp
->fr_subtype
);
652 length
= RELAX_BRANCH_LENGTH (fragp
->fr_subtype
);
654 /* Assume jumps are in range; the linker will catch any that aren't. */
655 length
= jump
? 4 : 8;
657 if (fragp
->fr_symbol
!= NULL
658 && S_IS_DEFINED (fragp
->fr_symbol
)
659 && !S_IS_WEAK (fragp
->fr_symbol
)
660 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
662 offsetT val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
663 bfd_vma rvc_range
= jump
? RVC_JUMP_REACH
: RVC_BRANCH_REACH
;
664 val
-= fragp
->fr_address
+ fragp
->fr_fix
;
666 if (rvc
&& (bfd_vma
)(val
+ rvc_range
/2) < rvc_range
)
668 else if ((bfd_vma
)(val
+ RISCV_BRANCH_REACH
/2) < RISCV_BRANCH_REACH
)
670 else if (!jump
&& rvc
)
675 fragp
->fr_subtype
= RELAX_BRANCH_ENCODE (jump
, rvc
, length
);
680 /* Information about an opcode name, mnemonics and its value. */
687 /* List for all supported opcode name. */
688 static const struct opcode_name_t opcode_name_list
[] =
733 /* Hash table for lookup opcode name. */
734 static htab_t opcode_names_hash
= NULL
;
736 /* Initialization for hash table of opcode name. */
739 init_opcode_names_hash (void)
741 const struct opcode_name_t
*opcode
;
743 for (opcode
= &opcode_name_list
[0]; opcode
->name
!= NULL
; ++opcode
)
744 if (str_hash_insert (opcode_names_hash
, opcode
->name
, opcode
, 0) != NULL
)
745 as_fatal (_("internal: duplicate %s"), opcode
->name
);
748 /* Find `s` is a valid opcode name or not, return the opcode name info
751 static const struct opcode_name_t
*
752 opcode_name_lookup (char **s
)
756 struct opcode_name_t
*o
;
758 /* Find end of name. */
760 if (is_name_beginner (*e
))
762 while (is_part_of_name (*e
))
765 /* Terminate name. */
769 o
= (struct opcode_name_t
*) str_hash_find (opcode_names_hash
, *s
);
771 /* Advance to next token if one was recognized. */
790 static htab_t reg_names_hash
= NULL
;
791 static htab_t csr_extra_hash
= NULL
;
793 #define ENCODE_REG_HASH(cls, n) \
794 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
795 #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
796 #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
799 hash_reg_name (enum reg_class
class, const char *name
, unsigned n
)
801 void *hash
= ENCODE_REG_HASH (class, n
);
802 if (str_hash_insert (reg_names_hash
, name
, hash
, 0) != NULL
)
803 as_fatal (_("internal: duplicate %s"), name
);
807 hash_reg_names (enum reg_class
class, const char * const names
[], unsigned n
)
811 for (i
= 0; i
< n
; i
++)
812 hash_reg_name (class, names
[i
], i
);
815 /* Init hash table csr_extra_hash to handle CSR. */
818 riscv_init_csr_hash (const char *name
,
820 enum riscv_csr_class
class,
821 enum riscv_spec_class define_version
,
822 enum riscv_spec_class abort_version
)
824 struct riscv_csr_extra
*entry
, *pre_entry
;
825 bool need_enrty
= true;
828 entry
= (struct riscv_csr_extra
*) str_hash_find (csr_extra_hash
, name
);
829 while (need_enrty
&& entry
!= NULL
)
831 if (entry
->csr_class
== class
832 && entry
->address
== address
833 && entry
->define_version
== define_version
834 && entry
->abort_version
== abort_version
)
844 entry
= XNEW (struct riscv_csr_extra
);
845 entry
->csr_class
= class;
846 entry
->address
= address
;
847 entry
->define_version
= define_version
;
848 entry
->abort_version
= abort_version
;
851 if (pre_entry
== NULL
)
852 str_hash_insert (csr_extra_hash
, name
, entry
, 0);
854 pre_entry
->next
= entry
;
857 /* Return the CSR address after checking the ISA dependency and
858 the privileged spec version.
860 There are one warning and two errors for CSR,
862 Invalid CSR: the CSR was defined, but isn't allowed for the current ISA
863 or the privileged spec, report warning only if -mcsr-check is set.
864 Unknown CSR: the CSR has never been defined, report error.
865 Improper CSR: the CSR number over the range (> 0xfff), report error. */
868 riscv_csr_address (const char *csr_name
,
869 struct riscv_csr_extra
*entry
)
871 struct riscv_csr_extra
*saved_entry
= entry
;
872 enum riscv_csr_class csr_class
= entry
->csr_class
;
873 bool need_check_version
= true;
879 result
= riscv_subset_supports ("i");
882 result
= (xlen
== 32 && riscv_subset_supports ("i"));
885 result
= riscv_subset_supports ("f");
886 need_check_version
= false;
888 case CSR_CLASS_DEBUG
:
889 need_check_version
= false;
892 as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class
);
895 if (riscv_opts
.csr_check
&& !result
)
896 as_warn (_("invalid CSR `%s' for the current ISA"), csr_name
);
898 while (entry
!= NULL
)
900 if (!need_check_version
901 || (default_priv_spec
>= entry
->define_version
902 && default_priv_spec
< entry
->abort_version
))
904 /* Find the CSR according to the specific version. */
905 return entry
->address
;
910 /* Can not find the CSR address from the chosen privileged version,
911 so use the newly defined value. */
912 if (riscv_opts
.csr_check
)
914 const char *priv_name
= NULL
;
915 RISCV_GET_PRIV_SPEC_NAME (priv_name
, default_priv_spec
);
916 if (priv_name
!= NULL
)
917 as_warn (_("invalid CSR `%s' for the privileged spec `%s'"),
918 csr_name
, priv_name
);
921 return saved_entry
->address
;
924 /* Return -1 if the CSR has never been defined. Otherwise, return
928 reg_csr_lookup_internal (const char *s
)
930 struct riscv_csr_extra
*r
=
931 (struct riscv_csr_extra
*) str_hash_find (csr_extra_hash
, s
);
936 return riscv_csr_address (s
, r
);
940 reg_lookup_internal (const char *s
, enum reg_class
class)
944 if (class == RCLASS_CSR
)
945 return reg_csr_lookup_internal (s
);
947 r
= str_hash_find (reg_names_hash
, s
);
948 if (r
== NULL
|| DECODE_REG_CLASS (r
) != class)
951 if (riscv_opts
.rve
&& class == RCLASS_GPR
&& DECODE_REG_NUM (r
) > 15)
954 return DECODE_REG_NUM (r
);
958 reg_lookup (char **s
, enum reg_class
class, unsigned int *regnop
)
964 /* Find end of name. */
966 if (is_name_beginner (*e
))
968 while (is_part_of_name (*e
))
971 /* Terminate name. */
975 /* Look for the register. Advance to next token if one was recognized. */
976 if ((reg
= reg_lookup_internal (*s
, class)) >= 0)
986 arg_lookup (char **s
, const char *const *array
, size_t size
, unsigned *regnop
)
988 const char *p
= strchr (*s
, ',');
989 size_t i
, len
= p
? (size_t)(p
- *s
) : strlen (*s
);
994 for (i
= 0; i
< size
; i
++)
995 if (array
[i
] != NULL
&& strncmp (array
[i
], *s
, len
) == 0)
1005 /* For consistency checking, verify that all bits are specified either
1006 by the match/mask part of the instruction definition, or by the
1007 operand list. The `length` could be 0, 4 or 8, 0 for auto detection. */
1010 validate_riscv_insn (const struct riscv_opcode
*opc
, int length
)
1012 const char *p
= opc
->args
;
1014 insn_t used_bits
= opc
->mask
;
1016 insn_t required_bits
;
1019 insn_width
= 8 * riscv_insn_length (opc
->match
);
1021 insn_width
= 8 * length
;
1023 required_bits
= ~0ULL >> (64 - insn_width
);
1025 if ((used_bits
& opc
->match
) != (opc
->match
& required_bits
))
1027 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
1028 opc
->name
, opc
->args
);
1032 #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
1039 case 'U': break; /* CRS1, constrained to equal RD. */
1040 case 'c': break; /* CRS1, constrained to equal sp. */
1041 case 'T': /* CRS2, floating point. */
1042 case 'V': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
1043 case 'S': /* CRS1S, floating point. */
1044 case 's': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
1045 case 'w': break; /* CRS1S, constrained to equal RD. */
1046 case 'D': /* CRS2S, floating point. */
1047 case 't': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
1048 case 'x': break; /* CRS2S, constrained to equal RD. */
1049 case 'z': break; /* CRS2S, constrained to be x0. */
1050 case '>': /* CITYPE immediate, compressed shift. */
1051 case 'u': /* CITYPE immediate, compressed lui. */
1052 case 'v': /* CITYPE immediate, li to compressed lui. */
1053 case 'o': /* CITYPE immediate, allow zero. */
1054 case 'j': used_bits
|= ENCODE_CITYPE_IMM (-1U); break;
1055 case 'L': used_bits
|= ENCODE_CITYPE_ADDI16SP_IMM (-1U); break;
1056 case 'm': used_bits
|= ENCODE_CITYPE_LWSP_IMM (-1U); break;
1057 case 'n': used_bits
|= ENCODE_CITYPE_LDSP_IMM (-1U); break;
1058 case '6': used_bits
|= ENCODE_CSSTYPE_IMM (-1U); break;
1059 case 'M': used_bits
|= ENCODE_CSSTYPE_SWSP_IMM (-1U); break;
1060 case 'N': used_bits
|= ENCODE_CSSTYPE_SDSP_IMM (-1U); break;
1061 case '8': used_bits
|= ENCODE_CIWTYPE_IMM (-1U); break;
1062 case 'K': used_bits
|= ENCODE_CIWTYPE_ADDI4SPN_IMM (-1U); break;
1063 /* CLTYPE and CSTYPE have the same immediate encoding. */
1064 case '5': used_bits
|= ENCODE_CLTYPE_IMM (-1U); break;
1065 case 'k': used_bits
|= ENCODE_CLTYPE_LW_IMM (-1U); break;
1066 case 'l': used_bits
|= ENCODE_CLTYPE_LD_IMM (-1U); break;
1067 case 'p': used_bits
|= ENCODE_CBTYPE_IMM (-1U); break;
1068 case 'a': used_bits
|= ENCODE_CJTYPE_IMM (-1U); break;
1069 case 'F': /* Compressed funct for .insn directive. */
1072 case '6': USE_BITS (OP_MASK_CFUNCT6
, OP_SH_CFUNCT6
); break;
1073 case '4': USE_BITS (OP_MASK_CFUNCT4
, OP_SH_CFUNCT4
); break;
1074 case '3': USE_BITS (OP_MASK_CFUNCT3
, OP_SH_CFUNCT3
); break;
1075 case '2': USE_BITS (OP_MASK_CFUNCT2
, OP_SH_CFUNCT2
); break;
1077 as_bad (_("internal: bad RISC-V opcode "
1078 "(unknown operand type `CF%c'): %s %s"),
1079 c
, opc
->name
, opc
->args
);
1084 as_bad (_("internal: bad RISC-V opcode "
1085 "(unknown operand type `C%c'): %s %s"),
1086 c
, opc
->name
, opc
->args
);
1093 case '<': USE_BITS (OP_MASK_SHAMTW
, OP_SH_SHAMTW
); break;
1094 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
1095 case 'A': break; /* Macro operand, must be symbol. */
1096 case 'B': break; /* Macro operand, must be symbol or constant. */
1097 case 'I': break; /* Macro operand, must be constant. */
1098 case 'D': /* RD, floating point. */
1099 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
1100 case 'Z': /* RS1, CSR number. */
1101 case 'S': /* RS1, floating point. */
1102 case 's': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
1103 case 'U': /* RS1 and RS2 are the same, floating point. */
1104 USE_BITS (OP_MASK_RS1
, OP_SH_RS1
);
1106 case 'T': /* RS2, floating point. */
1107 case 't': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
1108 case 'R': /* RS3, floating point. */
1109 case 'r': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
1110 case 'm': USE_BITS (OP_MASK_RM
, OP_SH_RM
); break;
1111 case 'E': USE_BITS (OP_MASK_CSR
, OP_SH_CSR
); break;
1112 case 'P': USE_BITS (OP_MASK_PRED
, OP_SH_PRED
); break;
1113 case 'Q': USE_BITS (OP_MASK_SUCC
, OP_SH_SUCC
); break;
1114 case 'o': /* ITYPE immediate, load displacement. */
1115 case 'j': used_bits
|= ENCODE_ITYPE_IMM (-1U); break;
1116 case 'a': used_bits
|= ENCODE_JTYPE_IMM (-1U); break;
1117 case 'p': used_bits
|= ENCODE_BTYPE_IMM (-1U); break;
1118 case 'q': used_bits
|= ENCODE_STYPE_IMM (-1U); break;
1119 case 'u': used_bits
|= ENCODE_UTYPE_IMM (-1U); break;
1120 case 'z': break; /* Zero immediate. */
1121 case '[': break; /* Unused operand. */
1122 case ']': break; /* Unused operand. */
1123 case '0': break; /* AMO displacement, must to zero. */
1124 case '1': break; /* Relaxation operand. */
1125 case 'F': /* Funct for .insn directive. */
1128 case '7': USE_BITS (OP_MASK_FUNCT7
, OP_SH_FUNCT7
); break;
1129 case '3': USE_BITS (OP_MASK_FUNCT3
, OP_SH_FUNCT3
); break;
1130 case '2': USE_BITS (OP_MASK_FUNCT2
, OP_SH_FUNCT2
); break;
1132 as_bad (_("internal: bad RISC-V opcode "
1133 "(unknown operand type `F%c'): %s %s"),
1134 c
, opc
->name
, opc
->args
);
1138 case 'O': /* Opcode for .insn directive. */
1141 case '4': USE_BITS (OP_MASK_OP
, OP_SH_OP
); break;
1142 case '2': USE_BITS (OP_MASK_OP2
, OP_SH_OP2
); break;
1144 as_bad (_("internal: bad RISC-V opcode "
1145 "(unknown operand type `F%c'): %s %s"),
1146 c
, opc
->name
, opc
->args
);
1151 as_bad (_("internal: bad RISC-V opcode "
1152 "(unknown operand type `%c'): %s %s"),
1153 c
, opc
->name
, opc
->args
);
1157 if (used_bits
!= required_bits
)
1159 as_bad (_("internal: bad RISC-V opcode "
1160 "(bits 0x%lx undefined): %s %s"),
1161 ~(unsigned long)(used_bits
& required_bits
),
1162 opc
->name
, opc
->args
);
1168 struct percent_op_match
1171 bfd_reloc_code_real_type reloc
;
1174 /* Common hash table initialization function for instruction and .insn
1178 init_opcode_hash (const struct riscv_opcode
*opcodes
,
1179 bool insn_directive_p
)
1183 htab_t hash
= str_htab_create ();
1184 while (opcodes
[i
].name
)
1186 const char *name
= opcodes
[i
].name
;
1187 if (str_hash_insert (hash
, name
, &opcodes
[i
], 0) != NULL
)
1188 as_fatal (_("internal: duplicate %s"), name
);
1192 if (opcodes
[i
].pinfo
!= INSN_MACRO
)
1194 if (insn_directive_p
)
1195 length
= ((name
[0] == 'c') ? 2 : 4);
1197 length
= 0; /* Let assembler determine the length. */
1198 if (!validate_riscv_insn (&opcodes
[i
], length
))
1199 as_fatal (_("internal: broken assembler. "
1200 "No assembly attempted"));
1203 gas_assert (!insn_directive_p
);
1206 while (opcodes
[i
].name
&& !strcmp (opcodes
[i
].name
, name
));
1212 /* This function is called once, at assembler startup time. It should set up
1213 all the tables, etc. that the MD part of the assembler will need. */
1218 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
1220 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
1221 as_warn (_("could not set architecture and machine"));
1223 op_hash
= init_opcode_hash (riscv_opcodes
, false);
1224 insn_type_hash
= init_opcode_hash (riscv_insn_types
, true);
1226 reg_names_hash
= str_htab_create ();
1227 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_numeric
, NGPR
);
1228 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_abi
, NGPR
);
1229 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_numeric
, NFPR
);
1230 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_abi
, NFPR
);
1231 /* Add "fp" as an alias for "s0". */
1232 hash_reg_name (RCLASS_GPR
, "fp", 8);
1234 /* Create and insert CSR hash tables. */
1235 csr_extra_hash
= str_htab_create ();
1236 #define DECLARE_CSR(name, num, class, define_version, abort_version) \
1237 riscv_init_csr_hash (#name, num, class, define_version, abort_version);
1238 #define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
1239 DECLARE_CSR(name, num, class, define_version, abort_version);
1240 #include "opcode/riscv-opc.h"
1243 opcode_names_hash
= str_htab_create ();
1244 init_opcode_names_hash ();
1246 /* Set the default alignment for the text section. */
1247 record_alignment (text_section
, riscv_opts
.rvc
? 1 : 2);
1251 riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type
, bfd_vma value
)
1258 case BFD_RELOC_RISCV_HI20
:
1259 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value
));
1261 case BFD_RELOC_RISCV_LO12_S
:
1262 return ENCODE_STYPE_IMM (value
);
1264 case BFD_RELOC_RISCV_LO12_I
:
1265 return ENCODE_ITYPE_IMM (value
);
1272 /* Output an instruction. IP is the instruction information.
1273 ADDRESS_EXPR is an operand of the instruction to be used with
1277 append_insn (struct riscv_cl_insn
*ip
, expressionS
*address_expr
,
1278 bfd_reloc_code_real_type reloc_type
)
1280 dwarf2_emit_insn (0);
1282 if (reloc_type
!= BFD_RELOC_UNUSED
)
1284 reloc_howto_type
*howto
;
1286 gas_assert (address_expr
);
1287 if (reloc_type
== BFD_RELOC_12_PCREL
1288 || reloc_type
== BFD_RELOC_RISCV_JMP
)
1290 int j
= reloc_type
== BFD_RELOC_RISCV_JMP
;
1291 int best_case
= riscv_insn_length (ip
->insn_opcode
);
1292 unsigned worst_case
= relaxed_branch_length (NULL
, NULL
, 0);
1294 if (now_seg
== absolute_section
)
1296 as_bad (_("relaxable branches not supported in absolute section"));
1300 add_relaxed_insn (ip
, worst_case
, best_case
,
1301 RELAX_BRANCH_ENCODE (j
, best_case
== 2, worst_case
),
1302 address_expr
->X_add_symbol
,
1303 address_expr
->X_add_number
);
1308 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
);
1310 as_bad (_("internal: unsupported RISC-V relocation number %d"),
1313 ip
->fixp
= fix_new_exp (ip
->frag
, ip
->where
,
1314 bfd_get_reloc_size (howto
),
1315 address_expr
, false, reloc_type
);
1317 ip
->fixp
->fx_tcbit
= riscv_opts
.relax
;
1321 add_fixed_insn (ip
);
1324 /* We need to start a new frag after any instruction that can be
1325 optimized away or compressed by the linker during relaxation, to prevent
1326 the assembler from computing static offsets across such an instruction.
1327 This is necessary to get correct EH info. */
1328 if (reloc_type
== BFD_RELOC_RISCV_HI20
1329 || reloc_type
== BFD_RELOC_RISCV_PCREL_HI20
1330 || reloc_type
== BFD_RELOC_RISCV_TPREL_HI20
1331 || reloc_type
== BFD_RELOC_RISCV_TPREL_ADD
)
1333 frag_wane (frag_now
);
1338 /* Build an instruction created by a macro expansion. This is passed
1339 a pointer to the count of instructions created so far, an expression,
1340 the name of the instruction to build, an operand format string, and
1341 corresponding arguments. */
1344 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
1346 const struct riscv_opcode
*mo
;
1347 struct riscv_cl_insn insn
;
1348 bfd_reloc_code_real_type r
;
1351 va_start (args
, fmt
);
1353 r
= BFD_RELOC_UNUSED
;
1354 mo
= (struct riscv_opcode
*) str_hash_find (op_hash
, name
);
1357 /* Find a non-RVC variant of the instruction. append_insn will compress
1359 while (riscv_insn_length (mo
->match
) < 4)
1361 gas_assert (strcmp (name
, mo
->name
) == 0);
1363 create_insn (&insn
, mo
);
1369 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
1373 INSERT_OPERAND (RS1
, insn
, va_arg (args
, int));
1377 INSERT_OPERAND (RS2
, insn
, va_arg (args
, int));
1383 gas_assert (ep
!= NULL
);
1384 r
= va_arg (args
, int);
1392 as_fatal (_("internal: invalid macro"));
1397 gas_assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1399 append_insn (&insn
, ep
, r
);
1402 /* Build an instruction created by a macro expansion. Like md_assemble but
1403 accept a printf-style format string and arguments. */
1406 md_assemblef (const char *format
, ...)
1412 va_start (ap
, format
);
1414 r
= vasprintf (&buf
, format
, ap
);
1417 as_fatal (_("internal: vasprintf failed"));
1425 /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
1429 normalize_constant_expr (expressionS
*ex
)
1433 if ((ex
->X_op
== O_constant
|| ex
->X_op
== O_symbol
)
1434 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
1435 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
1439 /* Fail if an expression EX is not a constant. IP is the instruction using EX.
1440 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
1443 check_absolute_expr (struct riscv_cl_insn
*ip
, expressionS
*ex
,
1446 if (ex
->X_op
== O_big
)
1447 as_bad (_("unsupported large constant"));
1448 else if (maybe_csr
&& ex
->X_op
== O_symbol
)
1449 as_bad (_("unknown CSR `%s'"),
1450 S_GET_NAME (ex
->X_add_symbol
));
1451 else if (ex
->X_op
!= O_constant
)
1452 as_bad (_("instruction %s requires absolute expression"),
1454 normalize_constant_expr (ex
);
1458 make_internal_label (void)
1460 return (symbolS
*) local_symbol_make (FAKE_LABEL_NAME
, now_seg
, frag_now
,
1464 /* Load an entry from the GOT. */
1467 pcrel_access (int destreg
, int tempreg
, expressionS
*ep
,
1468 const char *lo_insn
, const char *lo_pattern
,
1469 bfd_reloc_code_real_type hi_reloc
,
1470 bfd_reloc_code_real_type lo_reloc
)
1473 ep2
.X_op
= O_symbol
;
1474 ep2
.X_add_symbol
= make_internal_label ();
1475 ep2
.X_add_number
= 0;
1477 macro_build (ep
, "auipc", "d,u", tempreg
, hi_reloc
);
1478 macro_build (&ep2
, lo_insn
, lo_pattern
, destreg
, tempreg
, lo_reloc
);
1482 pcrel_load (int destreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1483 bfd_reloc_code_real_type hi_reloc
,
1484 bfd_reloc_code_real_type lo_reloc
)
1486 pcrel_access (destreg
, tempreg
, ep
, lo_insn
, "d,s,j", hi_reloc
, lo_reloc
);
1490 pcrel_store (int srcreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1491 bfd_reloc_code_real_type hi_reloc
,
1492 bfd_reloc_code_real_type lo_reloc
)
1494 pcrel_access (srcreg
, tempreg
, ep
, lo_insn
, "t,s,q", hi_reloc
, lo_reloc
);
1497 /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
1500 riscv_call (int destreg
, int tempreg
, expressionS
*ep
,
1501 bfd_reloc_code_real_type reloc
)
1503 /* Ensure the jalr is emitted to the same frag as the auipc. */
1505 macro_build (ep
, "auipc", "d,u", tempreg
, reloc
);
1506 macro_build (NULL
, "jalr", "d,s", destreg
, tempreg
);
1507 /* See comment at end of append_insn. */
1508 frag_wane (frag_now
);
1512 /* Load an integer constant into a register. */
1515 load_const (int reg
, expressionS
*ep
)
1517 int shift
= RISCV_IMM_BITS
;
1518 bfd_vma upper_imm
, sign
= (bfd_vma
) 1 << (RISCV_IMM_BITS
- 1);
1519 expressionS upper
= *ep
, lower
= *ep
;
1520 lower
.X_add_number
= ((ep
->X_add_number
& (sign
+ sign
- 1)) ^ sign
) - sign
;
1521 upper
.X_add_number
-= lower
.X_add_number
;
1523 if (ep
->X_op
!= O_constant
)
1525 as_bad (_("unsupported large constant"));
1529 if (xlen
> 32 && !IS_SEXT_32BIT_NUM (ep
->X_add_number
))
1531 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1532 while (((upper
.X_add_number
>> shift
) & 1) == 0)
1535 upper
.X_add_number
= (int64_t) upper
.X_add_number
>> shift
;
1536 load_const (reg
, &upper
);
1538 md_assemblef ("slli x%d, x%d, 0x%x", reg
, reg
, shift
);
1539 if (lower
.X_add_number
!= 0)
1540 md_assemblef ("addi x%d, x%d, %" BFD_VMA_FMT
"d", reg
, reg
,
1541 lower
.X_add_number
);
1545 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1548 if (upper
.X_add_number
!= 0)
1550 /* Discard low part and zero-extend upper immediate. */
1551 upper_imm
= ((uint32_t)upper
.X_add_number
>> shift
);
1553 md_assemblef ("lui x%d, 0x%" BFD_VMA_FMT
"x", reg
, upper_imm
);
1557 if (lower
.X_add_number
!= 0 || hi_reg
== 0)
1558 md_assemblef ("%s x%d, x%d, %" BFD_VMA_FMT
"d", ADD32_INSN
, reg
, hi_reg
,
1559 lower
.X_add_number
);
1563 /* Zero extend and sign extend byte/half-word/word. */
1566 riscv_ext (int destreg
, int srcreg
, unsigned shift
, bool sign
)
1570 md_assemblef ("slli x%d, x%d, 0x%x", destreg
, srcreg
, shift
);
1571 md_assemblef ("srai x%d, x%d, 0x%x", destreg
, destreg
, shift
);
1575 md_assemblef ("slli x%d, x%d, 0x%x", destreg
, srcreg
, shift
);
1576 md_assemblef ("srli x%d, x%d, 0x%x", destreg
, destreg
, shift
);
1580 /* Expand RISC-V assembly macros into one or more instructions. */
1583 macro (struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1584 bfd_reloc_code_real_type
*imm_reloc
)
1586 int rd
= (ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
;
1587 int rs1
= (ip
->insn_opcode
>> OP_SH_RS1
) & OP_MASK_RS1
;
1588 int rs2
= (ip
->insn_opcode
>> OP_SH_RS2
) & OP_MASK_RS2
;
1589 int mask
= ip
->insn_mo
->mask
;
1594 load_const (rd
, imm_expr
);
1599 /* Load the address of a symbol into a register. */
1600 if (!IS_SEXT_32BIT_NUM (imm_expr
->X_add_number
))
1601 as_bad (_("offset too large"));
1603 if (imm_expr
->X_op
== O_constant
)
1604 load_const (rd
, imm_expr
);
1605 else if (riscv_opts
.pic
&& mask
== M_LA
) /* Global PIC symbol. */
1606 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1607 BFD_RELOC_RISCV_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1608 else /* Local PIC symbol, or any non-PIC symbol. */
1609 pcrel_load (rd
, rd
, imm_expr
, "addi",
1610 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1614 pcrel_load (rd
, rd
, imm_expr
, "addi",
1615 BFD_RELOC_RISCV_TLS_GD_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1619 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1620 BFD_RELOC_RISCV_TLS_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1624 pcrel_load (rd
, rd
, imm_expr
, "lb",
1625 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1629 pcrel_load (rd
, rd
, imm_expr
, "lbu",
1630 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1634 pcrel_load (rd
, rd
, imm_expr
, "lh",
1635 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1639 pcrel_load (rd
, rd
, imm_expr
, "lhu",
1640 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1644 pcrel_load (rd
, rd
, imm_expr
, "lw",
1645 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1649 pcrel_load (rd
, rd
, imm_expr
, "lwu",
1650 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1654 pcrel_load (rd
, rd
, imm_expr
, "ld",
1655 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1659 pcrel_load (rd
, rs1
, imm_expr
, "flw",
1660 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1664 pcrel_load (rd
, rs1
, imm_expr
, "fld",
1665 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1669 pcrel_store (rs2
, rs1
, imm_expr
, "sb",
1670 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1674 pcrel_store (rs2
, rs1
, imm_expr
, "sh",
1675 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1679 pcrel_store (rs2
, rs1
, imm_expr
, "sw",
1680 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1684 pcrel_store (rs2
, rs1
, imm_expr
, "sd",
1685 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1689 pcrel_store (rs2
, rs1
, imm_expr
, "fsw",
1690 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1694 pcrel_store (rs2
, rs1
, imm_expr
, "fsd",
1695 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1699 riscv_call (rd
, rs1
, imm_expr
, *imm_reloc
);
1703 riscv_ext (rd
, rs1
, xlen
- 16, false);
1707 riscv_ext (rd
, rs1
, xlen
- 32, false);
1711 riscv_ext (rd
, rs1
, xlen
- 8, true);
1715 riscv_ext (rd
, rs1
, xlen
- 16, true);
1719 as_bad (_("internal: macro %s not implemented"), ip
->insn_mo
->name
);
1724 static const struct percent_op_match percent_op_utype
[] =
1726 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20
},
1727 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20
},
1728 {"%got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20
},
1729 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20
},
1730 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20
},
1731 {"%hi", BFD_RELOC_RISCV_HI20
},
1735 static const struct percent_op_match percent_op_itype
[] =
1737 {"%lo", BFD_RELOC_RISCV_LO12_I
},
1738 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I
},
1739 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I
},
1743 static const struct percent_op_match percent_op_stype
[] =
1745 {"%lo", BFD_RELOC_RISCV_LO12_S
},
1746 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S
},
1747 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S
},
1751 static const struct percent_op_match percent_op_rtype
[] =
1753 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD
},
1757 static const struct percent_op_match percent_op_null
[] =
1762 /* Return true if *STR points to a relocation operator. When returning true,
1763 move *STR over the operator and store its relocation code in *RELOC.
1764 Leave both *STR and *RELOC alone when returning false. */
1767 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
,
1768 const struct percent_op_match
*percent_op
)
1770 for ( ; percent_op
->str
; percent_op
++)
1771 if (strncasecmp (*str
, percent_op
->str
, strlen (percent_op
->str
)) == 0)
1773 int len
= strlen (percent_op
->str
);
1775 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
1778 *str
+= strlen (percent_op
->str
);
1779 *reloc
= percent_op
->reloc
;
1781 /* Check whether the output BFD supports this relocation.
1782 If not, issue an error and fall back on something safe. */
1783 if (*reloc
!= BFD_RELOC_UNUSED
1784 && !bfd_reloc_type_lookup (stdoutput
, *reloc
))
1786 as_bad ("internal: relocation %s isn't supported by the "
1787 "current ABI", percent_op
->str
);
1788 *reloc
= BFD_RELOC_UNUSED
;
1796 my_getExpression (expressionS
*ep
, char *str
)
1800 save_in
= input_line_pointer
;
1801 input_line_pointer
= str
;
1803 expr_end
= input_line_pointer
;
1804 input_line_pointer
= save_in
;
1807 /* Parse string STR as a 16-bit relocatable operand. Store the
1808 expression in *EP and the relocation, if any, in RELOC.
1809 Return the number of relocation operators used (0 or 1).
1811 On exit, EXPR_END points to the first character after the expression. */
1814 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1815 char *str
, const struct percent_op_match
*percent_op
)
1818 unsigned crux_depth
, str_depth
, regno
;
1821 /* First, check for integer registers. No callers can accept a reg, but
1822 we need to avoid accidentally creating a useless undefined symbol below,
1823 if this is an instruction pattern that can't match. A glibc build fails
1824 if this is removed. */
1825 if (reg_lookup (&str
, RCLASS_GPR
, ®no
))
1827 ep
->X_op
= O_register
;
1828 ep
->X_add_number
= regno
;
1833 /* Search for the start of the main expression.
1835 End the loop with CRUX pointing to the start of the main expression and
1836 with CRUX_DEPTH containing the number of open brackets at that point. */
1843 crux_depth
= str_depth
;
1845 /* Skip over whitespace and brackets, keeping count of the number
1847 while (*str
== ' ' || *str
== '\t' || *str
== '(')
1853 && parse_relocation (&str
, reloc
, percent_op
));
1855 my_getExpression (ep
, crux
);
1858 /* Match every open bracket. */
1859 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
1864 as_bad ("unclosed '('");
1871 /* Parse opcode name, could be an mnemonics or number. */
1874 my_getOpcodeExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1875 char *str
, const struct percent_op_match
*percent_op
)
1877 const struct opcode_name_t
*o
= opcode_name_lookup (&str
);
1881 ep
->X_op
= O_constant
;
1882 ep
->X_add_number
= o
->val
;
1886 return my_getSmallExpression (ep
, reloc
, str
, percent_op
);
1889 /* Detect and handle implicitly zero load-store offsets. For example,
1890 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
1891 an implicit offset was detected. */
1894 riscv_handle_implicit_zero_offset (expressionS
*ep
, const char *s
)
1896 /* Check whether there is only a single bracketed expression left.
1897 If so, it must be the base register and the constant must be zero. */
1898 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
1900 ep
->X_op
= O_constant
;
1901 ep
->X_add_number
= 0;
1908 /* All RISC-V CSR instructions belong to one of these classes. */
1917 /* Return which CSR instruction is checking. */
1919 static enum csr_insn_type
1920 riscv_csr_insn_type (insn_t insn
)
1922 if (((insn
^ MATCH_CSRRW
) & MASK_CSRRW
) == 0
1923 || ((insn
^ MATCH_CSRRWI
) & MASK_CSRRWI
) == 0)
1925 else if (((insn
^ MATCH_CSRRS
) & MASK_CSRRS
) == 0
1926 || ((insn
^ MATCH_CSRRSI
) & MASK_CSRRSI
) == 0)
1928 else if (((insn
^ MATCH_CSRRC
) & MASK_CSRRC
) == 0
1929 || ((insn
^ MATCH_CSRRCI
) & MASK_CSRRCI
) == 0)
1932 return INSN_NOT_CSR
;
1935 /* CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write
1936 CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of
1937 CSR address is 0x3. */
1940 riscv_csr_read_only_check (insn_t insn
)
1942 int csr
= (insn
& (OP_MASK_CSR
<< OP_SH_CSR
)) >> OP_SH_CSR
;
1943 int rs1
= (insn
& (OP_MASK_RS1
<< OP_SH_RS1
)) >> OP_SH_RS1
;
1944 int readonly
= (((csr
& (0x3 << 10)) >> 10) == 0x3);
1945 enum csr_insn_type csr_insn
= riscv_csr_insn_type (insn
);
1948 && (((csr_insn
== INSN_CSRRS
1949 || csr_insn
== INSN_CSRRC
)
1951 || csr_insn
== INSN_CSRRW
))
1957 /* Return True if it is a privileged instruction. Otherwise, return FALSE.
1959 uret is actually a N-ext instruction. So it is better to regard it as
1960 an user instruction rather than the priv instruction.
1962 hret is used to return from traps in H-mode. H-mode is removed since
1963 the v1.10 priv spec, but probably be added in the new hypervisor spec.
1964 Therefore, hret should be controlled by the hypervisor spec rather than
1965 priv spec in the future.
1967 dret is defined in the debug spec, so it should be checked in the future,
1971 riscv_is_priv_insn (insn_t insn
)
1973 return (((insn
^ MATCH_SRET
) & MASK_SRET
) == 0
1974 || ((insn
^ MATCH_MRET
) & MASK_MRET
) == 0
1975 || ((insn
^ MATCH_SFENCE_VMA
) & MASK_SFENCE_VMA
) == 0
1976 || ((insn
^ MATCH_WFI
) & MASK_WFI
) == 0
1977 /* The sfence.vm is dropped in the v1.10 priv specs, but we still need to
1978 check it here to keep the compatible. */
1979 || ((insn
^ MATCH_SFENCE_VM
) & MASK_SFENCE_VM
) == 0);
1982 /* This routine assembles an instruction into its binary format. As a
1983 side effect, it sets the global variable imm_reloc to the type of
1984 relocation to do if one of the operands is an address expression. */
1987 riscv_ip (char *str
, struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1988 bfd_reloc_code_real_type
*imm_reloc
, htab_t hash
)
1993 struct riscv_opcode
*insn
;
1998 const struct percent_op_match
*p
;
1999 const char *error
= "unrecognized opcode";
2000 /* Indicate we are assembling instruction with CSR. */
2001 bool insn_with_csr
= false;
2003 /* Parse the name of the instruction. Terminate the string if whitespace
2004 is found so that str_hash_find only sees the name part of the string. */
2005 for (s
= str
; *s
!= '\0'; ++s
)
2013 insn
= (struct riscv_opcode
*) str_hash_find (hash
, str
);
2016 for ( ; insn
&& insn
->name
&& strcmp (insn
->name
, str
) == 0; insn
++)
2018 if ((insn
->xlen_requirement
!= 0) && (xlen
!= insn
->xlen_requirement
))
2021 if (!riscv_multi_subset_supports (insn
->insn_class
))
2024 create_insn (ip
, insn
);
2027 imm_expr
->X_op
= O_absent
;
2028 *imm_reloc
= BFD_RELOC_UNUSED
;
2029 p
= percent_op_itype
;
2031 for (args
= insn
->args
;; ++args
)
2033 s
+= strspn (s
, " \t");
2036 case '\0': /* End of args. */
2037 if (insn
->pinfo
!= INSN_MACRO
)
2039 if (!insn
->match_func (insn
, ip
->insn_opcode
))
2042 /* For .insn, insn->match and insn->mask are 0. */
2043 if (riscv_insn_length ((insn
->match
== 0 && insn
->mask
== 0)
2049 if (riscv_is_priv_insn (ip
->insn_opcode
))
2050 explicit_priv_attr
= true;
2052 /* Check if we write a read-only CSR by the CSR
2055 && riscv_opts
.csr_check
2056 && !riscv_csr_read_only_check (ip
->insn_opcode
))
2058 /* Restore the character in advance, since we want to
2059 report the detailed warning message here. */
2061 *(argsStart
- 1) = save_c
;
2062 as_warn (_("read-only CSR is written `%s'"), str
);
2063 insn_with_csr
= false;
2068 /* Successful assembly. */
2070 insn_with_csr
= false;
2076 case 's': /* RS1 x8-x15. */
2077 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
2078 || !(regno
>= 8 && regno
<= 15))
2080 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
2082 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
2083 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
2084 || EXTRACT_OPERAND (CRS1S
, ip
->insn_opcode
) + 8 != regno
)
2087 case 't': /* RS2 x8-x15. */
2088 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
2089 || !(regno
>= 8 && regno
<= 15))
2091 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
2093 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
2094 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
2095 || EXTRACT_OPERAND (CRS2S
, ip
->insn_opcode
) + 8 != regno
)
2098 case 'U': /* RS1, constrained to equal RD. */
2099 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
2100 || EXTRACT_OPERAND (RD
, ip
->insn_opcode
) != regno
)
2104 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
))
2106 INSERT_OPERAND (CRS2
, *ip
, regno
);
2108 case 'c': /* RS1, constrained to equal sp. */
2109 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
2113 case 'z': /* RS2, constrained to equal x0. */
2114 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
2118 case '>': /* Shift amount, 0 - (XLEN-1). */
2119 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2120 || imm_expr
->X_op
!= O_constant
2121 || (unsigned long) imm_expr
->X_add_number
>= xlen
)
2123 ip
->insn_opcode
|= ENCODE_CITYPE_IMM (imm_expr
->X_add_number
);
2126 imm_expr
->X_op
= O_absent
;
2129 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2130 || imm_expr
->X_op
!= O_constant
2131 || imm_expr
->X_add_number
< 0
2132 || imm_expr
->X_add_number
>= 32
2133 || !VALID_CLTYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2135 ip
->insn_opcode
|= ENCODE_CLTYPE_IMM (imm_expr
->X_add_number
);
2138 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2139 || imm_expr
->X_op
!= O_constant
2140 || imm_expr
->X_add_number
< 0
2141 || imm_expr
->X_add_number
>= 64
2142 || !VALID_CSSTYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2144 ip
->insn_opcode
|= ENCODE_CSSTYPE_IMM (imm_expr
->X_add_number
);
2147 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2148 || imm_expr
->X_op
!= O_constant
2149 || imm_expr
->X_add_number
< 0
2150 || imm_expr
->X_add_number
>= 256
2151 || !VALID_CIWTYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2153 ip
->insn_opcode
|= ENCODE_CIWTYPE_IMM (imm_expr
->X_add_number
);
2156 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2157 || imm_expr
->X_op
!= O_constant
2158 || imm_expr
->X_add_number
== 0
2159 || !VALID_CITYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2161 ip
->insn_opcode
|= ENCODE_CITYPE_IMM (imm_expr
->X_add_number
);
2164 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2166 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2167 || imm_expr
->X_op
!= O_constant
2168 || !VALID_CLTYPE_LW_IMM ((valueT
) imm_expr
->X_add_number
))
2170 ip
->insn_opcode
|= ENCODE_CLTYPE_LW_IMM (imm_expr
->X_add_number
);
2173 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2175 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2176 || imm_expr
->X_op
!= O_constant
2177 || !VALID_CLTYPE_LD_IMM ((valueT
) imm_expr
->X_add_number
))
2179 ip
->insn_opcode
|= ENCODE_CLTYPE_LD_IMM (imm_expr
->X_add_number
);
2182 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2184 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2185 || imm_expr
->X_op
!= O_constant
2186 || !VALID_CITYPE_LWSP_IMM ((valueT
) imm_expr
->X_add_number
))
2189 ENCODE_CITYPE_LWSP_IMM (imm_expr
->X_add_number
);
2192 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2194 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2195 || imm_expr
->X_op
!= O_constant
2196 || !VALID_CITYPE_LDSP_IMM ((valueT
) imm_expr
->X_add_number
))
2199 ENCODE_CITYPE_LDSP_IMM (imm_expr
->X_add_number
);
2202 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2203 || imm_expr
->X_op
!= O_constant
2204 /* C.addiw, c.li, and c.andi allow zero immediate.
2205 C.addi allows zero immediate as hint. Otherwise this
2207 || !VALID_CITYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2209 ip
->insn_opcode
|= ENCODE_CITYPE_IMM (imm_expr
->X_add_number
);
2212 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2213 || imm_expr
->X_op
!= O_constant
2214 || imm_expr
->X_add_number
== 0
2215 || !VALID_CIWTYPE_ADDI4SPN_IMM ((valueT
) imm_expr
->X_add_number
))
2218 ENCODE_CIWTYPE_ADDI4SPN_IMM (imm_expr
->X_add_number
);
2221 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2222 || imm_expr
->X_op
!= O_constant
2223 || !VALID_CITYPE_ADDI16SP_IMM ((valueT
) imm_expr
->X_add_number
))
2226 ENCODE_CITYPE_ADDI16SP_IMM (imm_expr
->X_add_number
);
2229 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2231 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2232 || imm_expr
->X_op
!= O_constant
2233 || !VALID_CSSTYPE_SWSP_IMM ((valueT
) imm_expr
->X_add_number
))
2236 ENCODE_CSSTYPE_SWSP_IMM (imm_expr
->X_add_number
);
2239 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2241 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2242 || imm_expr
->X_op
!= O_constant
2243 || !VALID_CSSTYPE_SDSP_IMM ((valueT
) imm_expr
->X_add_number
))
2246 ENCODE_CSSTYPE_SDSP_IMM (imm_expr
->X_add_number
);
2249 p
= percent_op_utype
;
2250 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2253 if (imm_expr
->X_op
!= O_constant
2254 || imm_expr
->X_add_number
<= 0
2255 || imm_expr
->X_add_number
>= RISCV_BIGIMM_REACH
2256 || (imm_expr
->X_add_number
>= RISCV_RVC_IMM_REACH
/ 2
2257 && (imm_expr
->X_add_number
<
2258 RISCV_BIGIMM_REACH
- RISCV_RVC_IMM_REACH
/ 2)))
2260 ip
->insn_opcode
|= ENCODE_CITYPE_IMM (imm_expr
->X_add_number
);
2263 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2264 || (imm_expr
->X_add_number
& (RISCV_IMM_REACH
- 1))
2265 || ((int32_t)imm_expr
->X_add_number
2266 != imm_expr
->X_add_number
))
2268 imm_expr
->X_add_number
=
2269 ((uint32_t) imm_expr
->X_add_number
) >> RISCV_IMM_BITS
;
2275 case 'S': /* Floating-point RS1 x8-x15. */
2276 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
2277 || !(regno
>= 8 && regno
<= 15))
2279 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
2281 case 'D': /* Floating-point RS2 x8-x15. */
2282 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
2283 || !(regno
>= 8 && regno
<= 15))
2285 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
2287 case 'T': /* Floating-point RS2. */
2288 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
))
2290 INSERT_OPERAND (CRS2
, *ip
, regno
);
2296 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2297 || imm_expr
->X_op
!= O_constant
2298 || imm_expr
->X_add_number
< 0
2299 || imm_expr
->X_add_number
>= 64)
2301 as_bad (_("bad value for compressed funct6 "
2302 "field, value must be 0...64"));
2305 INSERT_OPERAND (CFUNCT6
, *ip
, imm_expr
->X_add_number
);
2306 imm_expr
->X_op
= O_absent
;
2311 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2312 || imm_expr
->X_op
!= O_constant
2313 || imm_expr
->X_add_number
< 0
2314 || imm_expr
->X_add_number
>= 16)
2316 as_bad (_("bad value for compressed funct4 "
2317 "field, value must be 0...15"));
2320 INSERT_OPERAND (CFUNCT4
, *ip
, imm_expr
->X_add_number
);
2321 imm_expr
->X_op
= O_absent
;
2326 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2327 || imm_expr
->X_op
!= O_constant
2328 || imm_expr
->X_add_number
< 0
2329 || imm_expr
->X_add_number
>= 8)
2331 as_bad (_("bad value for compressed funct3 "
2332 "field, value must be 0...7"));
2335 INSERT_OPERAND (CFUNCT3
, *ip
, imm_expr
->X_add_number
);
2336 imm_expr
->X_op
= O_absent
;
2341 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2342 || imm_expr
->X_op
!= O_constant
2343 || imm_expr
->X_add_number
< 0
2344 || imm_expr
->X_add_number
>= 4)
2346 as_bad (_("bad value for compressed funct2 "
2347 "field, value must be 0...3"));
2350 INSERT_OPERAND (CFUNCT2
, *ip
, imm_expr
->X_add_number
);
2351 imm_expr
->X_op
= O_absent
;
2356 as_bad (_("internal: unknown compressed funct "
2357 "field specifier `CF%c'"), *args
);
2362 as_bad (_("internal: unknown compressed field "
2363 "specifier `C%c'"), *args
);
2382 case '<': /* Shift amount, 0 - 31. */
2383 my_getExpression (imm_expr
, s
);
2384 check_absolute_expr (ip
, imm_expr
, false);
2385 if ((unsigned long) imm_expr
->X_add_number
> 31)
2386 as_bad (_("improper shift amount (%lu)"),
2387 (unsigned long) imm_expr
->X_add_number
);
2388 INSERT_OPERAND (SHAMTW
, *ip
, imm_expr
->X_add_number
);
2389 imm_expr
->X_op
= O_absent
;
2393 case '>': /* Shift amount, 0 - (XLEN-1). */
2394 my_getExpression (imm_expr
, s
);
2395 check_absolute_expr (ip
, imm_expr
, false);
2396 if ((unsigned long) imm_expr
->X_add_number
>= xlen
)
2397 as_bad (_("improper shift amount (%lu)"),
2398 (unsigned long) imm_expr
->X_add_number
);
2399 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
->X_add_number
);
2400 imm_expr
->X_op
= O_absent
;
2404 case 'Z': /* CSRRxI immediate. */
2405 my_getExpression (imm_expr
, s
);
2406 check_absolute_expr (ip
, imm_expr
, false);
2407 if ((unsigned long) imm_expr
->X_add_number
> 31)
2408 as_bad (_("improper CSRxI immediate (%lu)"),
2409 (unsigned long) imm_expr
->X_add_number
);
2410 INSERT_OPERAND (RS1
, *ip
, imm_expr
->X_add_number
);
2411 imm_expr
->X_op
= O_absent
;
2415 case 'E': /* Control register. */
2416 insn_with_csr
= true;
2417 explicit_priv_attr
= true;
2418 if (reg_lookup (&s
, RCLASS_CSR
, ®no
))
2419 INSERT_OPERAND (CSR
, *ip
, regno
);
2422 my_getExpression (imm_expr
, s
);
2423 check_absolute_expr (ip
, imm_expr
, true);
2424 if ((unsigned long) imm_expr
->X_add_number
> 0xfff)
2425 as_bad (_("improper CSR address (%lu)"),
2426 (unsigned long) imm_expr
->X_add_number
);
2427 INSERT_OPERAND (CSR
, *ip
, imm_expr
->X_add_number
);
2428 imm_expr
->X_op
= O_absent
;
2433 case 'm': /* Rounding mode. */
2434 if (arg_lookup (&s
, riscv_rm
, ARRAY_SIZE (riscv_rm
), ®no
))
2436 INSERT_OPERAND (RM
, *ip
, regno
);
2442 case 'Q': /* Fence predecessor/successor. */
2443 if (arg_lookup (&s
, riscv_pred_succ
, ARRAY_SIZE (riscv_pred_succ
),
2447 INSERT_OPERAND (PRED
, *ip
, regno
);
2449 INSERT_OPERAND (SUCC
, *ip
, regno
);
2454 case 'd': /* Destination register. */
2455 case 's': /* Source register. */
2456 case 't': /* Target register. */
2458 if (reg_lookup (&s
, RCLASS_GPR
, ®no
))
2464 /* Now that we have assembled one operand, we use the args
2465 string to figure out where it goes in the instruction. */
2469 INSERT_OPERAND (RS1
, *ip
, regno
);
2472 INSERT_OPERAND (RD
, *ip
, regno
);
2475 INSERT_OPERAND (RS2
, *ip
, regno
);
2478 INSERT_OPERAND (RS3
, *ip
, regno
);
2485 case 'D': /* Floating point RD. */
2486 case 'S': /* Floating point RS1. */
2487 case 'T': /* Floating point RS2. */
2488 case 'U': /* Floating point RS1 and RS2. */
2489 case 'R': /* Floating point RS3. */
2490 if (reg_lookup (&s
, RCLASS_FPR
, ®no
))
2498 INSERT_OPERAND (RD
, *ip
, regno
);
2501 INSERT_OPERAND (RS1
, *ip
, regno
);
2504 INSERT_OPERAND (RS1
, *ip
, regno
);
2507 INSERT_OPERAND (RS2
, *ip
, regno
);
2510 INSERT_OPERAND (RS3
, *ip
, regno
);
2518 my_getExpression (imm_expr
, s
);
2519 if (imm_expr
->X_op
!= O_big
2520 && imm_expr
->X_op
!= O_constant
)
2522 normalize_constant_expr (imm_expr
);
2527 my_getExpression (imm_expr
, s
);
2528 normalize_constant_expr (imm_expr
);
2529 /* The 'A' format specifier must be a symbol. */
2530 if (imm_expr
->X_op
!= O_symbol
)
2532 *imm_reloc
= BFD_RELOC_32
;
2537 my_getExpression (imm_expr
, s
);
2538 normalize_constant_expr (imm_expr
);
2539 /* The 'B' format specifier must be a symbol or a constant. */
2540 if (imm_expr
->X_op
!= O_symbol
&& imm_expr
->X_op
!= O_constant
)
2542 if (imm_expr
->X_op
== O_symbol
)
2543 *imm_reloc
= BFD_RELOC_32
;
2547 case 'j': /* Sign-extended immediate. */
2548 p
= percent_op_itype
;
2549 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
2551 case 'q': /* Store displacement. */
2552 p
= percent_op_stype
;
2553 *imm_reloc
= BFD_RELOC_RISCV_LO12_S
;
2555 case 'o': /* Load displacement. */
2556 p
= percent_op_itype
;
2557 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
2560 /* This is used for TLS, where the fourth operand is
2561 %tprel_add, to get a relocation applied to an add
2562 instruction, for relaxation to use. */
2563 p
= percent_op_rtype
;
2565 case '0': /* AMO displacement, which must be zero. */
2566 p
= percent_op_null
;
2568 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2571 /* If this value won't fit into a 16 bit offset, then go
2572 find a macro that will generate the 32 bit offset
2574 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2576 normalize_constant_expr (imm_expr
);
2577 if (imm_expr
->X_op
!= O_constant
2578 || (*args
== '0' && imm_expr
->X_add_number
!= 0)
2580 || imm_expr
->X_add_number
>= (signed)RISCV_IMM_REACH
/2
2581 || imm_expr
->X_add_number
< -(signed)RISCV_IMM_REACH
/2)
2587 case 'p': /* PC-relative offset. */
2589 *imm_reloc
= BFD_RELOC_12_PCREL
;
2590 my_getExpression (imm_expr
, s
);
2594 case 'u': /* Upper 20 bits. */
2595 p
= percent_op_utype
;
2596 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2598 if (imm_expr
->X_op
!= O_constant
)
2601 if (imm_expr
->X_add_number
< 0
2602 || imm_expr
->X_add_number
>= (signed)RISCV_BIGIMM_REACH
)
2603 as_bad (_("lui expression not in range 0..1048575"));
2605 *imm_reloc
= BFD_RELOC_RISCV_HI20
;
2606 imm_expr
->X_add_number
<<= RISCV_IMM_BITS
;
2611 case 'a': /* 20-bit PC-relative offset. */
2613 my_getExpression (imm_expr
, s
);
2615 *imm_reloc
= BFD_RELOC_RISCV_JMP
;
2619 my_getExpression (imm_expr
, s
);
2621 if (strcmp (s
, "@plt") == 0)
2623 *imm_reloc
= BFD_RELOC_RISCV_CALL_PLT
;
2627 *imm_reloc
= BFD_RELOC_RISCV_CALL
;
2634 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2635 || imm_expr
->X_op
!= O_constant
2636 || imm_expr
->X_add_number
< 0
2637 || imm_expr
->X_add_number
>= 128
2638 || (imm_expr
->X_add_number
& 0x3) != 3)
2640 as_bad (_("bad value for opcode field, "
2641 "value must be 0...127 and "
2642 "lower 2 bits must be 0x3"));
2645 INSERT_OPERAND (OP
, *ip
, imm_expr
->X_add_number
);
2646 imm_expr
->X_op
= O_absent
;
2651 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2652 || imm_expr
->X_op
!= O_constant
2653 || imm_expr
->X_add_number
< 0
2654 || imm_expr
->X_add_number
>= 3)
2656 as_bad (_("bad value for opcode field, "
2657 "value must be 0...2"));
2660 INSERT_OPERAND (OP2
, *ip
, imm_expr
->X_add_number
);
2661 imm_expr
->X_op
= O_absent
;
2666 as_bad (_("internal: unknown opcode field "
2667 "specifier `O%c'"), *args
);
2675 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2676 || imm_expr
->X_op
!= O_constant
2677 || imm_expr
->X_add_number
< 0
2678 || imm_expr
->X_add_number
>= 128)
2680 as_bad (_("bad value for funct7 field, "
2681 "value must be 0...127"));
2684 INSERT_OPERAND (FUNCT7
, *ip
, imm_expr
->X_add_number
);
2685 imm_expr
->X_op
= O_absent
;
2690 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2691 || imm_expr
->X_op
!= O_constant
2692 || imm_expr
->X_add_number
< 0
2693 || imm_expr
->X_add_number
>= 8)
2695 as_bad (_("bad value for funct3 field, "
2696 "value must be 0...7"));
2699 INSERT_OPERAND (FUNCT3
, *ip
, imm_expr
->X_add_number
);
2700 imm_expr
->X_op
= O_absent
;
2705 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2706 || imm_expr
->X_op
!= O_constant
2707 || imm_expr
->X_add_number
< 0
2708 || imm_expr
->X_add_number
>= 4)
2710 as_bad (_("bad value for funct2 field, "
2711 "value must be 0...3"));
2714 INSERT_OPERAND (FUNCT2
, *ip
, imm_expr
->X_add_number
);
2715 imm_expr
->X_op
= O_absent
;
2720 as_bad (_("internal: unknown funct field "
2721 "specifier `F%c'\n"), *args
);
2726 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2727 || imm_expr
->X_op
!= O_constant
2728 || imm_expr
->X_add_number
!= 0)
2731 imm_expr
->X_op
= O_absent
;
2735 as_fatal (_("internal: unknown argument type `%c'"), *args
);
2740 error
= _("illegal operands");
2741 insn_with_csr
= false;
2745 /* Restore the character we might have clobbered above. */
2747 *(argsStart
- 1) = save_c
;
2753 md_assemble (char *str
)
2755 struct riscv_cl_insn insn
;
2756 expressionS imm_expr
;
2757 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
2759 /* The architecture and privileged elf attributes should be set
2760 before assembling. */
2761 if (!start_assemble
)
2763 start_assemble
= true;
2765 riscv_set_abi_by_arch ();
2766 if (!riscv_set_default_priv_spec (NULL
))
2770 const char *error
= riscv_ip (str
, &insn
, &imm_expr
, &imm_reloc
, op_hash
);
2774 as_bad ("%s `%s'", error
, str
);
2778 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2779 macro (&insn
, &imm_expr
, &imm_reloc
);
2781 append_insn (&insn
, &imm_expr
, imm_reloc
);
2785 md_atof (int type
, char *litP
, int *sizeP
)
2787 return ieee_md_atof (type
, litP
, sizeP
, TARGET_BYTES_BIG_ENDIAN
);
2791 md_number_to_chars (char *buf
, valueT val
, int n
)
2793 if (target_big_endian
)
2794 number_to_chars_bigendian (buf
, val
, n
);
2796 number_to_chars_littleendian (buf
, val
, n
);
2799 const char *md_shortopts
= "O::g::G:";
2803 OPTION_MARCH
= OPTION_MD_BASE
,
2810 OPTION_NO_ARCH_ATTR
,
2812 OPTION_NO_CSR_CHECK
,
2816 OPTION_LITTLE_ENDIAN
,
2820 struct option md_longopts
[] =
2822 {"march", required_argument
, NULL
, OPTION_MARCH
},
2823 {"fPIC", no_argument
, NULL
, OPTION_PIC
},
2824 {"fpic", no_argument
, NULL
, OPTION_PIC
},
2825 {"fno-pic", no_argument
, NULL
, OPTION_NO_PIC
},
2826 {"mabi", required_argument
, NULL
, OPTION_MABI
},
2827 {"mrelax", no_argument
, NULL
, OPTION_RELAX
},
2828 {"mno-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
2829 {"march-attr", no_argument
, NULL
, OPTION_ARCH_ATTR
},
2830 {"mno-arch-attr", no_argument
, NULL
, OPTION_NO_ARCH_ATTR
},
2831 {"mcsr-check", no_argument
, NULL
, OPTION_CSR_CHECK
},
2832 {"mno-csr-check", no_argument
, NULL
, OPTION_NO_CSR_CHECK
},
2833 {"misa-spec", required_argument
, NULL
, OPTION_MISA_SPEC
},
2834 {"mpriv-spec", required_argument
, NULL
, OPTION_MPRIV_SPEC
},
2835 {"mbig-endian", no_argument
, NULL
, OPTION_BIG_ENDIAN
},
2836 {"mlittle-endian", no_argument
, NULL
, OPTION_LITTLE_ENDIAN
},
2838 {NULL
, no_argument
, NULL
, 0}
2840 size_t md_longopts_size
= sizeof (md_longopts
);
2843 md_parse_option (int c
, const char *arg
)
2848 default_arch_with_ext
= arg
;
2852 riscv_opts
.pic
= false;
2856 riscv_opts
.pic
= true;
2860 if (strcmp (arg
, "ilp32") == 0)
2861 riscv_set_abi (32, FLOAT_ABI_SOFT
, false);
2862 else if (strcmp (arg
, "ilp32e") == 0)
2863 riscv_set_abi (32, FLOAT_ABI_SOFT
, true);
2864 else if (strcmp (arg
, "ilp32f") == 0)
2865 riscv_set_abi (32, FLOAT_ABI_SINGLE
, false);
2866 else if (strcmp (arg
, "ilp32d") == 0)
2867 riscv_set_abi (32, FLOAT_ABI_DOUBLE
, false);
2868 else if (strcmp (arg
, "ilp32q") == 0)
2869 riscv_set_abi (32, FLOAT_ABI_QUAD
, false);
2870 else if (strcmp (arg
, "lp64") == 0)
2871 riscv_set_abi (64, FLOAT_ABI_SOFT
, false);
2872 else if (strcmp (arg
, "lp64f") == 0)
2873 riscv_set_abi (64, FLOAT_ABI_SINGLE
, false);
2874 else if (strcmp (arg
, "lp64d") == 0)
2875 riscv_set_abi (64, FLOAT_ABI_DOUBLE
, false);
2876 else if (strcmp (arg
, "lp64q") == 0)
2877 riscv_set_abi (64, FLOAT_ABI_QUAD
, false);
2880 explicit_mabi
= true;
2884 riscv_opts
.relax
= true;
2887 case OPTION_NO_RELAX
:
2888 riscv_opts
.relax
= false;
2891 case OPTION_ARCH_ATTR
:
2892 riscv_opts
.arch_attr
= true;
2895 case OPTION_NO_ARCH_ATTR
:
2896 riscv_opts
.arch_attr
= false;
2899 case OPTION_CSR_CHECK
:
2900 riscv_opts
.csr_check
= true;
2903 case OPTION_NO_CSR_CHECK
:
2904 riscv_opts
.csr_check
= false;
2907 case OPTION_MISA_SPEC
:
2908 return riscv_set_default_isa_spec (arg
);
2910 case OPTION_MPRIV_SPEC
:
2911 return riscv_set_default_priv_spec (arg
);
2913 case OPTION_BIG_ENDIAN
:
2914 target_big_endian
= 1;
2917 case OPTION_LITTLE_ENDIAN
:
2918 target_big_endian
= 0;
2929 riscv_after_parse_args (void)
2931 /* The --with-arch is optional for now, so we still need to set the xlen
2932 according to the default_arch, which is set by the --target. */
2935 if (strcmp (default_arch
, "riscv32") == 0)
2937 else if (strcmp (default_arch
, "riscv64") == 0)
2940 as_bad ("unknown default architecture `%s'", default_arch
);
2942 if (default_arch_with_ext
== NULL
)
2943 default_arch_with_ext
= xlen
== 64 ? "rv64g" : "rv32g";
2945 /* Initialize the hash table for extensions with default version. */
2946 ext_version_hash
= init_ext_version_hash ();
2948 /* Set default specs. */
2949 if (default_isa_spec
== ISA_SPEC_CLASS_NONE
)
2950 riscv_set_default_isa_spec (DEFAULT_RISCV_ISA_SPEC
);
2951 if (default_priv_spec
== PRIV_SPEC_CLASS_NONE
)
2952 riscv_set_default_priv_spec (DEFAULT_RISCV_PRIV_SPEC
);
2954 riscv_set_arch (default_arch_with_ext
);
2956 /* If the CIE to be produced has not been overridden on the command line,
2957 then produce version 3 by default. This allows us to use the full
2958 range of registers in a .cfi_return_column directive. */
2959 if (flag_dwarf_cie_version
== -1)
2960 flag_dwarf_cie_version
= 3;
2964 md_pcrel_from (fixS
*fixP
)
2966 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2969 /* Apply a fixup to the object file. */
2972 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
2974 unsigned int subtype
;
2975 bfd_byte
*buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
2976 bool relaxable
= false;
2980 /* Remember value for tc_gen_reloc. */
2981 fixP
->fx_addnumber
= *valP
;
2983 switch (fixP
->fx_r_type
)
2985 case BFD_RELOC_RISCV_HI20
:
2986 case BFD_RELOC_RISCV_LO12_I
:
2987 case BFD_RELOC_RISCV_LO12_S
:
2988 bfd_putl32 (riscv_apply_const_reloc (fixP
->fx_r_type
, *valP
)
2989 | bfd_getl32 (buf
), buf
);
2990 if (fixP
->fx_addsy
== NULL
)
2991 fixP
->fx_done
= true;
2995 case BFD_RELOC_RISCV_GOT_HI20
:
2996 case BFD_RELOC_RISCV_ADD8
:
2997 case BFD_RELOC_RISCV_ADD16
:
2998 case BFD_RELOC_RISCV_ADD32
:
2999 case BFD_RELOC_RISCV_ADD64
:
3000 case BFD_RELOC_RISCV_SUB6
:
3001 case BFD_RELOC_RISCV_SUB8
:
3002 case BFD_RELOC_RISCV_SUB16
:
3003 case BFD_RELOC_RISCV_SUB32
:
3004 case BFD_RELOC_RISCV_SUB64
:
3005 case BFD_RELOC_RISCV_RELAX
:
3008 case BFD_RELOC_RISCV_TPREL_HI20
:
3009 case BFD_RELOC_RISCV_TPREL_LO12_I
:
3010 case BFD_RELOC_RISCV_TPREL_LO12_S
:
3011 case BFD_RELOC_RISCV_TPREL_ADD
:
3015 case BFD_RELOC_RISCV_TLS_GOT_HI20
:
3016 case BFD_RELOC_RISCV_TLS_GD_HI20
:
3017 case BFD_RELOC_RISCV_TLS_DTPREL32
:
3018 case BFD_RELOC_RISCV_TLS_DTPREL64
:
3019 if (fixP
->fx_addsy
!= NULL
)
3020 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
3022 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3023 _("TLS relocation against a constant"));
3027 /* Use pc-relative relocation for FDE initial location.
3028 The symbol address in .eh_frame may be adjusted in
3029 _bfd_elf_discard_section_eh_frame, and the content of
3030 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
3031 Therefore, we cannot insert a relocation whose addend symbol is
3032 in .eh_frame. Othrewise, the value may be adjusted twice. */
3033 if (fixP
->fx_addsy
&& fixP
->fx_subsy
3034 && (sub_segment
= S_GET_SEGMENT (fixP
->fx_subsy
))
3035 && strcmp (sub_segment
->name
, ".eh_frame") == 0
3036 && S_GET_VALUE (fixP
->fx_subsy
)
3037 == fixP
->fx_frag
->fr_address
+ fixP
->fx_where
)
3039 fixP
->fx_r_type
= BFD_RELOC_RISCV_32_PCREL
;
3040 fixP
->fx_subsy
= NULL
;
3047 case BFD_RELOC_RISCV_CFA
:
3048 if (fixP
->fx_addsy
&& fixP
->fx_subsy
)
3050 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
3051 fixP
->fx_next
->fx_addsy
= fixP
->fx_subsy
;
3052 fixP
->fx_next
->fx_subsy
= NULL
;
3053 fixP
->fx_next
->fx_offset
= 0;
3054 fixP
->fx_subsy
= NULL
;
3056 switch (fixP
->fx_r_type
)
3059 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD64
;
3060 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB64
;
3064 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD32
;
3065 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
3069 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD16
;
3070 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
3074 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD8
;
3075 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
3078 case BFD_RELOC_RISCV_CFA
:
3079 /* Load the byte to get the subtype. */
3080 subtype
= bfd_get_8 (NULL
, &((fragS
*) (fixP
->fx_frag
->fr_opcode
))->fr_literal
[fixP
->fx_where
]);
3081 loc
= fixP
->fx_frag
->fr_fix
- (subtype
& 7);
3084 case DW_CFA_advance_loc1
:
3085 fixP
->fx_where
= loc
+ 1;
3086 fixP
->fx_next
->fx_where
= loc
+ 1;
3087 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET8
;
3088 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
3091 case DW_CFA_advance_loc2
:
3093 fixP
->fx_next
->fx_size
= 2;
3094 fixP
->fx_where
= loc
+ 1;
3095 fixP
->fx_next
->fx_where
= loc
+ 1;
3096 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET16
;
3097 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
3100 case DW_CFA_advance_loc4
:
3102 fixP
->fx_next
->fx_size
= 4;
3103 fixP
->fx_where
= loc
;
3104 fixP
->fx_next
->fx_where
= loc
;
3105 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET32
;
3106 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
3110 if (subtype
< 0x80 && (subtype
& 0x40))
3112 /* DW_CFA_advance_loc */
3113 fixP
->fx_frag
= (fragS
*) fixP
->fx_frag
->fr_opcode
;
3114 fixP
->fx_next
->fx_frag
= fixP
->fx_frag
;
3115 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET6
;
3116 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB6
;
3119 as_fatal (_("internal: bad CFA value #%d"), subtype
);
3125 /* This case is unreachable. */
3132 /* If we are deleting this reloc entry, we must fill in the
3133 value now. This can happen if we have a .word which is not
3134 resolved when it appears but is later defined. */
3135 if (fixP
->fx_addsy
== NULL
)
3137 gas_assert (fixP
->fx_size
<= sizeof (valueT
));
3138 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
3143 case BFD_RELOC_RISCV_JMP
:
3146 /* Fill in a tentative value to improve objdump readability. */
3147 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3148 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3149 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_JTYPE_IMM (delta
), buf
);
3153 case BFD_RELOC_12_PCREL
:
3156 /* Fill in a tentative value to improve objdump readability. */
3157 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3158 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3159 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_BTYPE_IMM (delta
), buf
);
3163 case BFD_RELOC_RISCV_RVC_BRANCH
:
3166 /* Fill in a tentative value to improve objdump readability. */
3167 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3168 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3169 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_CBTYPE_IMM (delta
), buf
);
3173 case BFD_RELOC_RISCV_RVC_JUMP
:
3176 /* Fill in a tentative value to improve objdump readability. */
3177 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3178 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3179 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_CJTYPE_IMM (delta
), buf
);
3183 case BFD_RELOC_RISCV_CALL
:
3184 case BFD_RELOC_RISCV_CALL_PLT
:
3188 case BFD_RELOC_RISCV_PCREL_HI20
:
3189 case BFD_RELOC_RISCV_PCREL_LO12_S
:
3190 case BFD_RELOC_RISCV_PCREL_LO12_I
:
3191 relaxable
= riscv_opts
.relax
;
3194 case BFD_RELOC_RISCV_ALIGN
:
3198 /* We ignore generic BFD relocations we don't know about. */
3199 if (bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
) != NULL
)
3200 as_fatal (_("internal: bad relocation #%d"), fixP
->fx_r_type
);
3203 if (fixP
->fx_subsy
!= NULL
)
3204 as_bad_subtract (fixP
);
3206 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
3207 if (relaxable
&& fixP
->fx_tcbit
&& fixP
->fx_addsy
!= NULL
)
3209 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
3210 fixP
->fx_next
->fx_addsy
= fixP
->fx_next
->fx_subsy
= NULL
;
3211 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_RELAX
;
3212 fixP
->fx_next
->fx_size
= 0;
3216 /* Because the value of .cfi_remember_state may changed after relaxation,
3217 we insert a fix to relocate it again in link-time. */
3220 riscv_pre_output_hook (void)
3222 const frchainS
*frch
;
3225 /* Save the current segment info. */
3227 subsegT subseg
= now_subseg
;
3229 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
3230 for (frch
= seg_info (s
)->frchainP
; frch
; frch
= frch
->frch_next
)
3234 for (frag
= frch
->frch_root
; frag
; frag
= frag
->fr_next
)
3236 if (frag
->fr_type
== rs_cfa
)
3239 expressionS
*symval
;
3241 symval
= symbol_get_value_expression (frag
->fr_symbol
);
3242 exp
.X_op
= O_subtract
;
3243 exp
.X_add_symbol
= symval
->X_add_symbol
;
3244 exp
.X_add_number
= 0;
3245 exp
.X_op_symbol
= symval
->X_op_symbol
;
3247 /* We must set the segment before creating a frag after all
3248 frag chains have been chained together. */
3249 subseg_set (s
, frch
->frch_subseg
);
3251 fix_new_exp (frag
, (int) frag
->fr_offset
, 1, &exp
, 0,
3252 BFD_RELOC_RISCV_CFA
);
3257 /* Restore the original segment info. */
3258 subseg_set (seg
, subseg
);
3261 /* This structure is used to hold a stack of .option values. */
3262 struct riscv_option_stack
3264 struct riscv_option_stack
*next
;
3265 struct riscv_set_options options
;
3268 static struct riscv_option_stack
*riscv_opts_stack
;
3270 /* Handle the .option pseudo-op. */
3273 s_riscv_option (int x ATTRIBUTE_UNUSED
)
3275 char *name
= input_line_pointer
, ch
;
3277 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3278 ++input_line_pointer
;
3279 ch
= *input_line_pointer
;
3280 *input_line_pointer
= '\0';
3282 if (strcmp (name
, "rvc") == 0)
3283 riscv_set_rvc (true);
3284 else if (strcmp (name
, "norvc") == 0)
3285 riscv_set_rvc (false);
3286 else if (strcmp (name
, "pic") == 0)
3287 riscv_opts
.pic
= true;
3288 else if (strcmp (name
, "nopic") == 0)
3289 riscv_opts
.pic
= false;
3290 else if (strcmp (name
, "relax") == 0)
3291 riscv_opts
.relax
= true;
3292 else if (strcmp (name
, "norelax") == 0)
3293 riscv_opts
.relax
= false;
3294 else if (strcmp (name
, "csr-check") == 0)
3295 riscv_opts
.csr_check
= true;
3296 else if (strcmp (name
, "no-csr-check") == 0)
3297 riscv_opts
.csr_check
= false;
3298 else if (strcmp (name
, "push") == 0)
3300 struct riscv_option_stack
*s
;
3302 s
= (struct riscv_option_stack
*) xmalloc (sizeof *s
);
3303 s
->next
= riscv_opts_stack
;
3304 s
->options
= riscv_opts
;
3305 riscv_opts_stack
= s
;
3307 else if (strcmp (name
, "pop") == 0)
3309 struct riscv_option_stack
*s
;
3311 s
= riscv_opts_stack
;
3313 as_bad (_(".option pop with no .option push"));
3316 riscv_opts
= s
->options
;
3317 riscv_opts_stack
= s
->next
;
3323 as_warn (_("unrecognized .option directive: %s\n"), name
);
3325 *input_line_pointer
= ch
;
3326 demand_empty_rest_of_line ();
3329 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
3330 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
3331 use in DWARF debug information. */
3334 s_dtprel (int bytes
)
3341 if (ex
.X_op
!= O_symbol
)
3343 as_bad (_("unsupported use of %s"), (bytes
== 8
3346 ignore_rest_of_line ();
3349 p
= frag_more (bytes
);
3350 md_number_to_chars (p
, 0, bytes
);
3351 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, false,
3353 ? BFD_RELOC_RISCV_TLS_DTPREL64
3354 : BFD_RELOC_RISCV_TLS_DTPREL32
));
3356 demand_empty_rest_of_line ();
3359 /* Handle the .bss pseudo-op. */
3362 s_bss (int ignore ATTRIBUTE_UNUSED
)
3364 subseg_set (bss_section
, 0);
3365 demand_empty_rest_of_line ();
3369 riscv_make_nops (char *buf
, bfd_vma bytes
)
3373 /* RISC-V instructions cannot begin or end on odd addresses, so this case
3374 means we are not within a valid instruction sequence. It is thus safe
3375 to use a zero byte, even though that is not a valid instruction. */
3379 /* Use at most one 2-byte NOP. */
3380 if ((bytes
- i
) % 4 == 2)
3382 number_to_chars_littleendian (buf
+ i
, RVC_NOP
, 2);
3386 /* Fill the remainder with 4-byte NOPs. */
3387 for ( ; i
< bytes
; i
+= 4)
3388 number_to_chars_littleendian (buf
+ i
, RISCV_NOP
, 4);
3391 /* Called from md_do_align. Used to create an alignment frag in a
3392 code section by emitting a worst-case NOP sequence that the linker
3393 will later relax to the correct number of NOPs. We can't compute
3394 the correct alignment now because of other linker relaxations. */
3397 riscv_frag_align_code (int n
)
3399 bfd_vma bytes
= (bfd_vma
) 1 << n
;
3400 bfd_vma insn_alignment
= riscv_opts
.rvc
? 2 : 4;
3401 bfd_vma worst_case_bytes
= bytes
- insn_alignment
;
3405 /* If we are moving to a smaller alignment than the instruction size, then no
3406 alignment is required. */
3407 if (bytes
<= insn_alignment
)
3410 /* When not relaxing, riscv_handle_align handles code alignment. */
3411 if (!riscv_opts
.relax
)
3414 nops
= frag_more (worst_case_bytes
);
3416 ex
.X_op
= O_constant
;
3417 ex
.X_add_number
= worst_case_bytes
;
3419 riscv_make_nops (nops
, worst_case_bytes
);
3421 fix_new_exp (frag_now
, nops
- frag_now
->fr_literal
, 0,
3422 &ex
, false, BFD_RELOC_RISCV_ALIGN
);
3427 /* Implement HANDLE_ALIGN. */
3430 riscv_handle_align (fragS
*fragP
)
3432 switch (fragP
->fr_type
)
3435 /* When relaxing, riscv_frag_align_code handles code alignment. */
3436 if (!riscv_opts
.relax
)
3438 bfd_signed_vma bytes
= (fragP
->fr_next
->fr_address
3439 - fragP
->fr_address
- fragP
->fr_fix
);
3440 /* We have 4 byte uncompressed nops. */
3441 bfd_signed_vma size
= 4;
3442 bfd_signed_vma excess
= bytes
% size
;
3443 char *p
= fragP
->fr_literal
+ fragP
->fr_fix
;
3448 /* Insert zeros or compressed nops to get 4 byte alignment. */
3451 riscv_make_nops (p
, excess
);
3452 fragP
->fr_fix
+= excess
;
3456 /* Insert variable number of 4 byte uncompressed nops. */
3457 riscv_make_nops (p
, size
);
3458 fragP
->fr_var
= size
;
3468 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
3470 return (fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, false));
3473 /* Translate internal representation of relocation info to BFD target
3477 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
3479 arelent
*reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3481 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3482 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3483 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3484 reloc
->addend
= fixp
->fx_addnumber
;
3486 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
3487 if (reloc
->howto
== NULL
)
3489 if ((fixp
->fx_r_type
== BFD_RELOC_16
|| fixp
->fx_r_type
== BFD_RELOC_8
)
3490 && fixp
->fx_addsy
!= NULL
&& fixp
->fx_subsy
!= NULL
)
3492 /* We don't have R_RISCV_8/16, but for this special case,
3493 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
3497 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3498 _("cannot represent %s relocation in object file"),
3499 bfd_get_reloc_code_name (fixp
->fx_r_type
));
3507 riscv_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
3509 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
3511 offsetT old_var
= fragp
->fr_var
;
3512 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, true);
3513 return fragp
->fr_var
- old_var
;
3519 /* Expand far branches to multi-instruction sequences. */
3522 md_convert_frag_branch (fragS
*fragp
)
3530 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
3532 exp
.X_op
= O_symbol
;
3533 exp
.X_add_symbol
= fragp
->fr_symbol
;
3534 exp
.X_add_number
= fragp
->fr_offset
;
3536 gas_assert (fragp
->fr_var
== RELAX_BRANCH_LENGTH (fragp
->fr_subtype
));
3538 if (RELAX_BRANCH_RVC (fragp
->fr_subtype
))
3540 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
3544 /* Expand the RVC branch into a RISC-V one. */
3545 insn
= bfd_getl16 (buf
);
3546 rs1
= 8 + ((insn
>> OP_SH_CRS1S
) & OP_MASK_CRS1S
);
3547 if ((insn
& MASK_C_J
) == MATCH_C_J
)
3549 else if ((insn
& MASK_C_JAL
) == MATCH_C_JAL
)
3550 insn
= MATCH_JAL
| (X_RA
<< OP_SH_RD
);
3551 else if ((insn
& MASK_C_BEQZ
) == MATCH_C_BEQZ
)
3552 insn
= MATCH_BEQ
| (rs1
<< OP_SH_RS1
);
3553 else if ((insn
& MASK_C_BNEZ
) == MATCH_C_BNEZ
)
3554 insn
= MATCH_BNE
| (rs1
<< OP_SH_RS1
);
3557 bfd_putl32 (insn
, buf
);
3561 /* Invert the branch condition. Branch over the jump. */
3562 insn
= bfd_getl16 (buf
);
3563 insn
^= MATCH_C_BEQZ
^ MATCH_C_BNEZ
;
3564 insn
|= ENCODE_CBTYPE_IMM (6);
3565 bfd_putl16 (insn
, buf
);
3570 /* Just keep the RVC branch. */
3571 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
3572 ? BFD_RELOC_RISCV_RVC_JUMP
: BFD_RELOC_RISCV_RVC_BRANCH
;
3573 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3574 2, &exp
, false, reloc
);
3583 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
3586 gas_assert (!RELAX_BRANCH_UNCOND (fragp
->fr_subtype
));
3588 /* Invert the branch condition. Branch over the jump. */
3589 insn
= bfd_getl32 (buf
);
3590 insn
^= MATCH_BEQ
^ MATCH_BNE
;
3591 insn
|= ENCODE_BTYPE_IMM (8);
3592 bfd_putl32 (insn
, buf
);
3596 /* Jump to the target. */
3597 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3598 4, &exp
, false, BFD_RELOC_RISCV_JMP
);
3599 bfd_putl32 (MATCH_JAL
, buf
);
3604 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
3605 ? BFD_RELOC_RISCV_JMP
: BFD_RELOC_12_PCREL
;
3606 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3607 4, &exp
, false, reloc
);
3616 fixp
->fx_file
= fragp
->fr_file
;
3617 fixp
->fx_line
= fragp
->fr_line
;
3619 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
3620 + fragp
->fr_fix
+ fragp
->fr_var
);
3622 fragp
->fr_fix
+= fragp
->fr_var
;
3625 /* Relax a machine dependent frag. This returns the amount by which
3626 the current size of the frag should change. */
3629 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec ATTRIBUTE_UNUSED
,
3632 gas_assert (RELAX_BRANCH_P (fragp
->fr_subtype
));
3633 md_convert_frag_branch (fragp
);
3637 md_show_usage (FILE *stream
)
3639 fprintf (stream
, _("\
3641 -fpic generate position-independent code\n\
3642 -fno-pic don't generate position-independent code (default)\n\
3643 -march=ISA set the RISC-V architecture\n\
3644 -misa-spec=ISAspec set the RISC-V ISA spec (2.2, 20190608, 20191213)\n\
3645 -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9, 1.9.1, 1.10, 1.11)\n\
3646 -mabi=ABI set the RISC-V ABI\n\
3647 -mrelax enable relax (default)\n\
3648 -mno-relax disable relax\n\
3649 -march-attr generate RISC-V arch attribute\n\
3650 -mno-arch-attr don't generate RISC-V arch attribute\n\
3654 /* Standard calling conventions leave the CFA at SP on entry. */
3657 riscv_cfi_frame_initial_instructions (void)
3659 cfi_add_CFA_def_cfa_register (X_SP
);
3663 tc_riscv_regname_to_dw2regnum (char *regname
)
3667 if ((reg
= reg_lookup_internal (regname
, RCLASS_GPR
)) >= 0)
3670 if ((reg
= reg_lookup_internal (regname
, RCLASS_FPR
)) >= 0)
3673 /* CSRs are numbered 4096 -> 8191. */
3674 if ((reg
= reg_lookup_internal (regname
, RCLASS_CSR
)) >= 0)
3677 as_bad (_("unknown register `%s'"), regname
);
3682 riscv_elf_final_processing (void)
3684 riscv_set_abi_by_arch ();
3685 elf_elfheader (stdoutput
)->e_flags
|= elf_flags
;
3688 /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
3689 since these directives break relaxation when used with symbol deltas. */
3692 s_riscv_leb128 (int sign
)
3695 char *save_in
= input_line_pointer
;
3698 if (exp
.X_op
!= O_constant
)
3699 as_bad (_("non-constant .%cleb128 is not supported"), sign
? 's' : 'u');
3700 demand_empty_rest_of_line ();
3702 input_line_pointer
= save_in
;
3703 return s_leb128 (sign
);
3706 /* Parse the .insn directive. */
3709 s_riscv_insn (int x ATTRIBUTE_UNUSED
)
3711 char *str
= input_line_pointer
;
3712 struct riscv_cl_insn insn
;
3713 expressionS imm_expr
;
3714 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
3717 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3718 ++input_line_pointer
;
3720 save_c
= *input_line_pointer
;
3721 *input_line_pointer
= '\0';
3723 const char *error
= riscv_ip (str
, &insn
, &imm_expr
,
3724 &imm_reloc
, insn_type_hash
);
3728 as_bad ("%s `%s'", error
, str
);
3732 gas_assert (insn
.insn_mo
->pinfo
!= INSN_MACRO
);
3733 append_insn (&insn
, &imm_expr
, imm_reloc
);
3736 *input_line_pointer
= save_c
;
3737 demand_empty_rest_of_line ();
3740 /* Update architecture and privileged elf attributes. If we don't set
3741 them, then try to output the default ones. */
3744 riscv_write_out_attrs (void)
3746 const char *arch_str
, *priv_str
, *p
;
3747 /* versions[0]: major version.
3748 versions[1]: minor version.
3749 versions[2]: revision version. */
3750 unsigned versions
[3] = {0}, number
= 0;
3753 /* Re-write architecture elf attribute. */
3754 arch_str
= riscv_arch_str (xlen
, &riscv_subsets
);
3755 bfd_elf_add_proc_attr_string (stdoutput
, Tag_RISCV_arch
, arch_str
);
3756 xfree ((void *) arch_str
);
3758 /* For the file without any instruction, we don't set the default_priv_spec
3759 according to the privileged elf attributes since the md_assemble isn't
3762 && !riscv_set_default_priv_spec (NULL
))
3765 /* If we already have set privileged elf attributes, then no need to do
3766 anything. Otherwise, don't generate or update them when no CSR and
3767 privileged instructions are used. */
3768 if (!explicit_priv_attr
)
3771 RISCV_GET_PRIV_SPEC_NAME (priv_str
, default_priv_spec
);
3773 for (i
= 0; *p
; ++p
)
3775 if (*p
== '.' && i
< 3)
3777 versions
[i
++] = number
;
3780 else if (ISDIGIT (*p
))
3781 number
= (number
* 10) + (*p
- '0');
3784 as_bad (_("internal: bad RISC-V privileged spec (%s)"), priv_str
);
3788 versions
[i
] = number
;
3790 /* Re-write privileged elf attributes. */
3791 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec
, versions
[0]);
3792 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec_minor
, versions
[1]);
3793 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec_revision
, versions
[2]);
3796 /* Add the default contents for the .riscv.attributes section. */
3799 riscv_set_public_attributes (void)
3801 if (riscv_opts
.arch_attr
|| explicit_attr
)
3802 riscv_write_out_attrs ();
3805 /* Called after all assembly has been done. */
3810 riscv_set_public_attributes ();
3813 /* Given a symbolic attribute NAME, return the proper integer value.
3814 Returns -1 if the attribute is not known. */
3817 riscv_convert_symbolic_attribute (const char *name
)
3826 /* When you modify this table you should
3827 also modify the list in doc/c-riscv.texi. */
3828 #define T(tag) {#tag, Tag_RISCV_##tag}, {"Tag_RISCV_" #tag, Tag_RISCV_##tag}
3832 T(priv_spec_revision
),
3833 T(unaligned_access
),
3842 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
3843 if (strcmp (name
, attribute_table
[i
].name
) == 0)
3844 return attribute_table
[i
].tag
;
3849 /* Parse a .attribute directive. */
3852 s_riscv_attribute (int ignored ATTRIBUTE_UNUSED
)
3854 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
3856 obj_attribute
*attr
;
3858 explicit_attr
= true;
3861 case Tag_RISCV_arch
:
3863 attr
= elf_known_obj_attributes_proc (stdoutput
);
3864 if (!start_assemble
)
3865 riscv_set_arch (attr
[Tag_RISCV_arch
].s
);
3867 as_fatal (_("architecture elf attributes must set before "
3868 "any instructions"));
3870 if (old_xlen
!= xlen
)
3872 /* We must re-init bfd again if xlen is changed. */
3873 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
3874 bfd_find_target (riscv_target_format (), stdoutput
);
3876 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
3877 as_warn (_("could not set architecture and machine"));
3881 case Tag_RISCV_priv_spec
:
3882 case Tag_RISCV_priv_spec_minor
:
3883 case Tag_RISCV_priv_spec_revision
:
3885 as_fatal (_("privileged elf attributes must set before "
3886 "any instructions"));
3894 /* RISC-V pseudo-ops table. */
3895 static const pseudo_typeS riscv_pseudo_table
[] =
3897 {"option", s_riscv_option
, 0},
3901 {"dtprelword", s_dtprel
, 4},
3902 {"dtpreldword", s_dtprel
, 8},
3904 {"uleb128", s_riscv_leb128
, 0},
3905 {"sleb128", s_riscv_leb128
, 1},
3906 {"insn", s_riscv_insn
, 0},
3907 {"attribute", s_riscv_attribute
, 0},
3913 riscv_pop_insert (void)
3915 extern void pop_insert (const pseudo_typeS
*);
3917 pop_insert (riscv_pseudo_table
);