1 /* tc-riscv.c -- RISC-V assembler
2 Copyright (C) 2011-2021 Free Software Foundation, Inc.
4 Contributed by Andrew Waterman (andrew@sifive.com).
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
26 #include "safe-ctype.h"
29 #include "dwarf2dbg.h"
30 #include "dw2gencfi.h"
32 #include "bfd/cpu-riscv.h"
33 #include "bfd/elfxx-riscv.h"
34 #include "elf/riscv.h"
35 #include "opcode/riscv.h"
39 /* Information about an instruction, including its format, operands
43 /* The opcode's entry in riscv_opcodes. */
44 const struct riscv_opcode
*insn_mo
;
46 /* The encoded instruction bits. */
49 /* The frag that contains the instruction. */
52 /* The offset into FRAG of the first instruction byte. */
55 /* The relocs associated with the instruction, if any. */
59 /* All RISC-V CSR belong to one of these classes. */
65 CSR_CLASS_I_32
, /* rv32 only */
66 CSR_CLASS_F
, /* f-ext only */
67 CSR_CLASS_DEBUG
/* debug CSR */
70 /* This structure holds all restricted conditions for a CSR. */
71 struct riscv_csr_extra
73 /* Class to which this CSR belongs. Used to decide whether or
74 not this CSR is legal in the current -march context. */
75 enum riscv_csr_class csr_class
;
77 /* CSR may have differnet numbers in the previous priv spec. */
80 /* Record the CSR is defined/valid in which versions. */
81 enum riscv_spec_class define_version
;
83 /* Record the CSR is aborted/invalid from which versions. If it isn't
84 aborted in the current version, then it should be CSR_CLASS_VDRAFT. */
85 enum riscv_spec_class abort_version
;
87 /* The CSR may have more than one setting. */
88 struct riscv_csr_extra
*next
;
91 /* All standard/Z* extensions defined in all supported ISA spec. */
92 struct riscv_ext_version
95 enum riscv_spec_class isa_spec_class
;
100 static const struct riscv_ext_version ext_version_table
[] =
102 {"e", ISA_SPEC_CLASS_20191213
, 1, 9},
103 {"e", ISA_SPEC_CLASS_20190608
, 1, 9},
104 {"e", ISA_SPEC_CLASS_2P2
, 1, 9},
106 {"i", ISA_SPEC_CLASS_20191213
, 2, 1},
107 {"i", ISA_SPEC_CLASS_20190608
, 2, 1},
108 {"i", ISA_SPEC_CLASS_2P2
, 2, 0},
110 {"m", ISA_SPEC_CLASS_20191213
, 2, 0},
111 {"m", ISA_SPEC_CLASS_20190608
, 2, 0},
112 {"m", ISA_SPEC_CLASS_2P2
, 2, 0},
114 {"a", ISA_SPEC_CLASS_20191213
, 2, 1},
115 {"a", ISA_SPEC_CLASS_20190608
, 2, 0},
116 {"a", ISA_SPEC_CLASS_2P2
, 2, 0},
118 {"f", ISA_SPEC_CLASS_20191213
, 2, 2},
119 {"f", ISA_SPEC_CLASS_20190608
, 2, 2},
120 {"f", ISA_SPEC_CLASS_2P2
, 2, 0},
122 {"d", ISA_SPEC_CLASS_20191213
, 2, 2},
123 {"d", ISA_SPEC_CLASS_20190608
, 2, 2},
124 {"d", ISA_SPEC_CLASS_2P2
, 2, 0},
126 {"q", ISA_SPEC_CLASS_20191213
, 2, 2},
127 {"q", ISA_SPEC_CLASS_20190608
, 2, 2},
128 {"q", ISA_SPEC_CLASS_2P2
, 2, 0},
130 {"c", ISA_SPEC_CLASS_20191213
, 2, 0},
131 {"c", ISA_SPEC_CLASS_20190608
, 2, 0},
132 {"c", ISA_SPEC_CLASS_2P2
, 2, 0},
134 {"zicsr", ISA_SPEC_CLASS_20191213
, 2, 0},
135 {"zicsr", ISA_SPEC_CLASS_20190608
, 2, 0},
137 {"zifencei", ISA_SPEC_CLASS_20191213
, 2, 0},
138 {"zifencei", ISA_SPEC_CLASS_20190608
, 2, 0},
140 {"zihintpause", ISA_SPEC_CLASS_DRAFT
, 1, 0},
142 {"zbb", ISA_SPEC_CLASS_DRAFT
, 0, 93},
143 {"zba", ISA_SPEC_CLASS_DRAFT
, 0, 93},
144 {"zbc", ISA_SPEC_CLASS_DRAFT
, 0, 93},
146 /* Terminate the list. */
151 #define DEFAULT_ARCH "riscv64"
154 #ifndef DEFAULT_RISCV_ATTR
155 #define DEFAULT_RISCV_ATTR 0
158 /* Let riscv_after_parse_args set the default value according to xlen. */
159 #ifndef DEFAULT_RISCV_ARCH_WITH_EXT
160 #define DEFAULT_RISCV_ARCH_WITH_EXT NULL
163 /* Need to sync the version with RISC-V compiler. */
164 #ifndef DEFAULT_RISCV_ISA_SPEC
165 #define DEFAULT_RISCV_ISA_SPEC "2.2"
168 #ifndef DEFAULT_RISCV_PRIV_SPEC
169 #define DEFAULT_RISCV_PRIV_SPEC "1.11"
172 static const char default_arch
[] = DEFAULT_ARCH
;
173 static const char *default_arch_with_ext
= DEFAULT_RISCV_ARCH_WITH_EXT
;
174 static enum riscv_spec_class default_isa_spec
= ISA_SPEC_CLASS_NONE
;
175 static enum riscv_spec_class default_priv_spec
= PRIV_SPEC_CLASS_NONE
;
177 static unsigned xlen
= 0; /* The width of an x-register. */
178 static unsigned abi_xlen
= 0; /* The width of a pointer in the ABI. */
179 static bool rve_abi
= false;
182 FLOAT_ABI_DEFAULT
= -1,
188 static enum float_abi float_abi
= FLOAT_ABI_DEFAULT
;
190 #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
191 #define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
193 static unsigned elf_flags
= 0;
195 /* Set the default_isa_spec. Return 0 if the spec isn't supported.
196 Otherwise, return 1. */
199 riscv_set_default_isa_spec (const char *s
)
201 enum riscv_spec_class
class = ISA_SPEC_CLASS_NONE
;
202 RISCV_GET_ISA_SPEC_CLASS (s
, class);
203 if (class == ISA_SPEC_CLASS_NONE
)
205 as_bad ("unknown default ISA spec `%s' set by "
206 "-misa-spec or --with-isa-spec", s
);
210 default_isa_spec
= class;
214 /* Set the default_priv_spec. Find the privileged elf attributes when
215 the input string is NULL. Return 0 if the spec isn't supported.
216 Otherwise, return 1. */
219 riscv_set_default_priv_spec (const char *s
)
221 enum riscv_spec_class
class = PRIV_SPEC_CLASS_NONE
;
222 unsigned major
, minor
, revision
;
225 RISCV_GET_PRIV_SPEC_CLASS (s
, class);
226 if (class != PRIV_SPEC_CLASS_NONE
)
228 default_priv_spec
= class;
234 as_bad (_("unknown default privileged spec `%s' set by "
235 "-mpriv-spec or --with-priv-spec"), s
);
239 /* Set the default_priv_spec by the privileged elf attributes. */
240 attr
= elf_known_obj_attributes_proc (stdoutput
);
241 major
= (unsigned) attr
[Tag_RISCV_priv_spec
].i
;
242 minor
= (unsigned) attr
[Tag_RISCV_priv_spec_minor
].i
;
243 revision
= (unsigned) attr
[Tag_RISCV_priv_spec_revision
].i
;
244 /* Version 0.0.0 is the default value and meningless. */
245 if (major
== 0 && minor
== 0 && revision
== 0)
248 riscv_get_priv_spec_class_from_numbers (major
, minor
, revision
, &class);
249 if (class != PRIV_SPEC_CLASS_NONE
)
251 default_priv_spec
= class;
255 /* Still can not find the privileged spec class. */
256 as_bad (_("unknown default privileged spec `%d.%d.%d' set by "
257 "privileged elf attributes"), major
, minor
, revision
);
261 /* This is the set of options which the .option pseudo-op may modify. */
262 struct riscv_set_options
264 int pic
; /* Generate position-independent code. */
265 int rvc
; /* Generate RVC code. */
266 int rve
; /* Generate RVE code. */
267 int relax
; /* Emit relocs the linker is allowed to relax. */
268 int arch_attr
; /* Emit architecture and privileged elf attributes. */
269 int csr_check
; /* Enable the CSR checking. */
272 static struct riscv_set_options riscv_opts
=
278 DEFAULT_RISCV_ATTR
, /* arch_attr */
283 riscv_set_rvc (bool rvc_value
)
286 elf_flags
|= EF_RISCV_RVC
;
288 riscv_opts
.rvc
= rvc_value
;
292 riscv_set_rve (bool rve_value
)
294 riscv_opts
.rve
= rve_value
;
297 static riscv_subset_list_t riscv_subsets
;
300 riscv_subset_supports (const char *feature
)
302 struct riscv_subset_t
*subset
;
304 if (riscv_opts
.rvc
&& (strcasecmp (feature
, "c") == 0))
307 return riscv_lookup_subset (&riscv_subsets
, feature
, &subset
);
311 riscv_multi_subset_supports (enum riscv_insn_class insn_class
)
315 case INSN_CLASS_I
: return riscv_subset_supports ("i");
316 case INSN_CLASS_C
: return riscv_subset_supports ("c");
317 case INSN_CLASS_A
: return riscv_subset_supports ("a");
318 case INSN_CLASS_M
: return riscv_subset_supports ("m");
319 case INSN_CLASS_F
: return riscv_subset_supports ("f");
320 case INSN_CLASS_D
: return riscv_subset_supports ("d");
321 case INSN_CLASS_Q
: return riscv_subset_supports ("q");
323 case INSN_CLASS_F_AND_C
:
324 return (riscv_subset_supports ("f")
325 && riscv_subset_supports ("c"));
326 case INSN_CLASS_D_AND_C
:
327 return (riscv_subset_supports ("d")
328 && riscv_subset_supports ("c"));
330 case INSN_CLASS_ZICSR
:
331 return riscv_subset_supports ("zicsr");
332 case INSN_CLASS_ZIFENCEI
:
333 return riscv_subset_supports ("zifencei");
334 case INSN_CLASS_ZIHINTPAUSE
:
335 return riscv_subset_supports ("zihintpause");
338 return riscv_subset_supports ("zbb");
341 return riscv_subset_supports ("zba");
344 return riscv_subset_supports ("zbc");
347 as_fatal ("internal: unreachable");
352 /* Handle of the extension with version hash table. */
353 static htab_t ext_version_hash
= NULL
;
356 init_ext_version_hash (void)
358 const struct riscv_ext_version
*table
= ext_version_table
;
359 htab_t hash
= str_htab_create ();
362 while (table
[i
].name
)
364 const char *name
= table
[i
].name
;
365 if (str_hash_insert (hash
, name
, &table
[i
], 0) != NULL
)
366 as_fatal (_("internal: duplicate %s"), name
);
370 && strcmp (table
[i
].name
, name
) == 0)
378 riscv_get_default_ext_version (const char *name
,
382 struct riscv_ext_version
*ext
;
384 if (name
== NULL
|| default_isa_spec
== ISA_SPEC_CLASS_NONE
)
387 ext
= (struct riscv_ext_version
*) str_hash_find (ext_version_hash
, name
);
390 && strcmp (ext
->name
, name
) == 0)
392 if (ext
->isa_spec_class
== ISA_SPEC_CLASS_DRAFT
393 || ext
->isa_spec_class
== default_isa_spec
)
395 *major_version
= ext
->major_version
;
396 *minor_version
= ext
->minor_version
;
403 /* Set which ISA and extensions are available. */
406 riscv_set_arch (const char *s
)
408 riscv_parse_subset_t rps
;
409 rps
.subset_list
= &riscv_subsets
;
410 rps
.error_handler
= as_bad
;
412 rps
.get_default_version
= riscv_get_default_ext_version
;
417 riscv_release_subset_list (&riscv_subsets
);
418 riscv_parse_subset (&rps
, s
);
421 /* Indicate -mabi option is explictly set. */
422 static bool explicit_mabi
= false;
425 riscv_set_abi (unsigned new_xlen
, enum float_abi new_float_abi
, bool rve
)
428 float_abi
= new_float_abi
;
432 /* If the -mabi option isn't set, then set the abi according to the
433 ISA string. Otherwise, check if there is any conflict. */
436 riscv_set_abi_by_arch (void)
440 if (riscv_subset_supports ("q"))
441 riscv_set_abi (xlen
, FLOAT_ABI_QUAD
, false);
442 else if (riscv_subset_supports ("d"))
443 riscv_set_abi (xlen
, FLOAT_ABI_DOUBLE
, false);
445 riscv_set_abi (xlen
, FLOAT_ABI_SOFT
, false);
449 gas_assert (abi_xlen
!= 0 && xlen
!= 0 && float_abi
!= FLOAT_ABI_DEFAULT
);
451 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen
, xlen
);
452 else if (abi_xlen
< xlen
)
453 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen
, xlen
);
456 /* Update the EF_RISCV_FLOAT_ABI field of elf_flags. */
457 elf_flags
&= ~EF_RISCV_FLOAT_ABI
;
458 elf_flags
|= float_abi
<< 1;
461 elf_flags
|= EF_RISCV_RVE
;
464 /* Handle of the OPCODE hash table. */
465 static htab_t op_hash
= NULL
;
467 /* Handle of the type of .insn hash table. */
468 static htab_t insn_type_hash
= NULL
;
470 /* This array holds the chars that always start a comment. If the
471 pre-processor is disabled, these aren't very useful. */
472 const char comment_chars
[] = "#";
474 /* This array holds the chars that only start a comment at the beginning of
475 a line. If the line seems to have the form '# 123 filename'
476 .line and .file directives will appear in the pre-processed output
478 Note that input_file.c hand checks for '#' at the beginning of the
479 first line of the input file. This is because the compiler outputs
480 #NO_APP at the beginning of its output.
482 Also note that C style comments are always supported. */
483 const char line_comment_chars
[] = "#";
485 /* This array holds machine specific line separator characters. */
486 const char line_separator_chars
[] = ";";
488 /* Chars that can be used to separate mant from exp in floating point nums. */
489 const char EXP_CHARS
[] = "eE";
491 /* Chars that mean this number is a floating point constant.
492 As in 0f12.456 or 0d1.2345e12. */
493 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
495 /* Indicate we are already assemble any instructions or not. */
496 static bool start_assemble
= false;
498 /* Indicate ELF attributes are explicitly set. */
499 static bool explicit_attr
= false;
501 /* Indicate CSR or priv instructions are explicitly used. */
502 static bool explicit_priv_attr
= false;
504 /* Macros for encoding relaxation state for RVC branches and far jumps. */
505 #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
508 | ((uncond) ? 1 : 0) \
511 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
512 #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
513 #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
514 #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
516 /* Is the given value a sign-extended 32-bit value? */
517 #define IS_SEXT_32BIT_NUM(x) \
518 (((x) &~ (offsetT) 0x7fffffff) == 0 \
519 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
521 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
522 #define IS_ZEXT_32BIT_NUM(x) \
523 (((x) &~ (offsetT) 0xffffffff) == 0 \
524 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
526 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
527 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
528 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
529 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
531 /* Determine if an instruction matches an opcode. */
532 #define OPCODE_MATCHES(OPCODE, OP) \
533 (((OPCODE) & MASK_##OP) == MATCH_##OP)
535 static char *expr_end
;
537 /* The default target format to use. */
540 riscv_target_format (void)
542 if (target_big_endian
)
543 return xlen
== 64 ? "elf64-bigriscv" : "elf32-bigriscv";
545 return xlen
== 64 ? "elf64-littleriscv" : "elf32-littleriscv";
548 /* Return the length of instruction INSN. */
550 static inline unsigned int
551 insn_length (const struct riscv_cl_insn
*insn
)
553 return riscv_insn_length (insn
->insn_opcode
);
556 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
559 create_insn (struct riscv_cl_insn
*insn
, const struct riscv_opcode
*mo
)
562 insn
->insn_opcode
= mo
->match
;
568 /* Install INSN at the location specified by its "frag" and "where" fields. */
571 install_insn (const struct riscv_cl_insn
*insn
)
573 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
574 number_to_chars_littleendian (f
, insn
->insn_opcode
, insn_length (insn
));
577 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
578 and install the opcode in the new location. */
581 move_insn (struct riscv_cl_insn
*insn
, fragS
*frag
, long where
)
585 if (insn
->fixp
!= NULL
)
587 insn
->fixp
->fx_frag
= frag
;
588 insn
->fixp
->fx_where
= where
;
593 /* Add INSN to the end of the output. */
596 add_fixed_insn (struct riscv_cl_insn
*insn
)
598 char *f
= frag_more (insn_length (insn
));
599 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
603 add_relaxed_insn (struct riscv_cl_insn
*insn
, int max_chars
, int var
,
604 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
606 frag_grow (max_chars
);
607 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
608 frag_var (rs_machine_dependent
, max_chars
, var
,
609 subtype
, symbol
, offset
, NULL
);
612 /* Compute the length of a branch sequence, and adjust the stored length
613 accordingly. If FRAGP is NULL, the worst-case length is returned. */
616 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
618 int jump
, rvc
, length
= 8;
623 jump
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
);
624 rvc
= RELAX_BRANCH_RVC (fragp
->fr_subtype
);
625 length
= RELAX_BRANCH_LENGTH (fragp
->fr_subtype
);
627 /* Assume jumps are in range; the linker will catch any that aren't. */
628 length
= jump
? 4 : 8;
630 if (fragp
->fr_symbol
!= NULL
631 && S_IS_DEFINED (fragp
->fr_symbol
)
632 && !S_IS_WEAK (fragp
->fr_symbol
)
633 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
635 offsetT val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
636 bfd_vma rvc_range
= jump
? RVC_JUMP_REACH
: RVC_BRANCH_REACH
;
637 val
-= fragp
->fr_address
+ fragp
->fr_fix
;
639 if (rvc
&& (bfd_vma
)(val
+ rvc_range
/2) < rvc_range
)
641 else if ((bfd_vma
)(val
+ RISCV_BRANCH_REACH
/2) < RISCV_BRANCH_REACH
)
643 else if (!jump
&& rvc
)
648 fragp
->fr_subtype
= RELAX_BRANCH_ENCODE (jump
, rvc
, length
);
653 /* Information about an opcode name, mnemonics and its value. */
660 /* List for all supported opcode name. */
661 static const struct opcode_name_t opcode_name_list
[] =
706 /* Hash table for lookup opcode name. */
707 static htab_t opcode_names_hash
= NULL
;
709 /* Initialization for hash table of opcode name. */
712 init_opcode_names_hash (void)
714 const struct opcode_name_t
*opcode
;
716 for (opcode
= &opcode_name_list
[0]; opcode
->name
!= NULL
; ++opcode
)
717 if (str_hash_insert (opcode_names_hash
, opcode
->name
, opcode
, 0) != NULL
)
718 as_fatal (_("internal: duplicate %s"), opcode
->name
);
721 /* Find `s` is a valid opcode name or not, return the opcode name info
724 static const struct opcode_name_t
*
725 opcode_name_lookup (char **s
)
729 struct opcode_name_t
*o
;
731 /* Find end of name. */
733 if (is_name_beginner (*e
))
735 while (is_part_of_name (*e
))
738 /* Terminate name. */
742 o
= (struct opcode_name_t
*) str_hash_find (opcode_names_hash
, *s
);
744 /* Advance to next token if one was recognized. */
763 static htab_t reg_names_hash
= NULL
;
764 static htab_t csr_extra_hash
= NULL
;
766 #define ENCODE_REG_HASH(cls, n) \
767 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
768 #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
769 #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
772 hash_reg_name (enum reg_class
class, const char *name
, unsigned n
)
774 void *hash
= ENCODE_REG_HASH (class, n
);
775 if (str_hash_insert (reg_names_hash
, name
, hash
, 0) != NULL
)
776 as_fatal (_("internal: duplicate %s"), name
);
780 hash_reg_names (enum reg_class
class, const char * const names
[], unsigned n
)
784 for (i
= 0; i
< n
; i
++)
785 hash_reg_name (class, names
[i
], i
);
788 /* Init hash table csr_extra_hash to handle CSR. */
791 riscv_init_csr_hash (const char *name
,
793 enum riscv_csr_class
class,
794 enum riscv_spec_class define_version
,
795 enum riscv_spec_class abort_version
)
797 struct riscv_csr_extra
*entry
, *pre_entry
;
798 bool need_enrty
= true;
801 entry
= (struct riscv_csr_extra
*) str_hash_find (csr_extra_hash
, name
);
802 while (need_enrty
&& entry
!= NULL
)
804 if (entry
->csr_class
== class
805 && entry
->address
== address
806 && entry
->define_version
== define_version
807 && entry
->abort_version
== abort_version
)
817 entry
= XNEW (struct riscv_csr_extra
);
818 entry
->csr_class
= class;
819 entry
->address
= address
;
820 entry
->define_version
= define_version
;
821 entry
->abort_version
= abort_version
;
824 if (pre_entry
== NULL
)
825 str_hash_insert (csr_extra_hash
, name
, entry
, 0);
827 pre_entry
->next
= entry
;
830 /* Return the CSR address after checking the ISA dependency and
831 the privileged spec version.
833 There are one warning and two errors for CSR,
835 Invalid CSR: the CSR was defined, but isn't allowed for the current ISA
836 or the privileged spec, report warning only if -mcsr-check is set.
837 Unknown CSR: the CSR has never been defined, report error.
838 Improper CSR: the CSR number over the range (> 0xfff), report error. */
841 riscv_csr_address (const char *csr_name
,
842 struct riscv_csr_extra
*entry
)
844 struct riscv_csr_extra
*saved_entry
= entry
;
845 enum riscv_csr_class csr_class
= entry
->csr_class
;
846 bool need_check_version
= true;
852 result
= riscv_subset_supports ("i");
855 result
= (xlen
== 32 && riscv_subset_supports ("i"));
858 result
= riscv_subset_supports ("f");
859 need_check_version
= false;
861 case CSR_CLASS_DEBUG
:
862 need_check_version
= false;
865 as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class
);
868 if (riscv_opts
.csr_check
&& !result
)
869 as_warn (_("invalid CSR `%s' for the current ISA"), csr_name
);
871 while (entry
!= NULL
)
873 if (!need_check_version
874 || (default_priv_spec
>= entry
->define_version
875 && default_priv_spec
< entry
->abort_version
))
877 /* Find the CSR according to the specific version. */
878 return entry
->address
;
883 /* Can not find the CSR address from the chosen privileged version,
884 so use the newly defined value. */
885 if (riscv_opts
.csr_check
)
887 const char *priv_name
= NULL
;
888 RISCV_GET_PRIV_SPEC_NAME (priv_name
, default_priv_spec
);
889 if (priv_name
!= NULL
)
890 as_warn (_("invalid CSR `%s' for the privileged spec `%s'"),
891 csr_name
, priv_name
);
894 return saved_entry
->address
;
897 /* Return -1 if the CSR has never been defined. Otherwise, return
901 reg_csr_lookup_internal (const char *s
)
903 struct riscv_csr_extra
*r
=
904 (struct riscv_csr_extra
*) str_hash_find (csr_extra_hash
, s
);
909 return riscv_csr_address (s
, r
);
913 reg_lookup_internal (const char *s
, enum reg_class
class)
917 if (class == RCLASS_CSR
)
918 return reg_csr_lookup_internal (s
);
920 r
= str_hash_find (reg_names_hash
, s
);
921 if (r
== NULL
|| DECODE_REG_CLASS (r
) != class)
924 if (riscv_opts
.rve
&& class == RCLASS_GPR
&& DECODE_REG_NUM (r
) > 15)
927 return DECODE_REG_NUM (r
);
931 reg_lookup (char **s
, enum reg_class
class, unsigned int *regnop
)
937 /* Find end of name. */
939 if (is_name_beginner (*e
))
941 while (is_part_of_name (*e
))
944 /* Terminate name. */
948 /* Look for the register. Advance to next token if one was recognized. */
949 if ((reg
= reg_lookup_internal (*s
, class)) >= 0)
959 arg_lookup (char **s
, const char *const *array
, size_t size
, unsigned *regnop
)
961 const char *p
= strchr (*s
, ',');
962 size_t i
, len
= p
? (size_t)(p
- *s
) : strlen (*s
);
967 for (i
= 0; i
< size
; i
++)
968 if (array
[i
] != NULL
&& strncmp (array
[i
], *s
, len
) == 0)
978 /* For consistency checking, verify that all bits are specified either
979 by the match/mask part of the instruction definition, or by the
980 operand list. The `length` could be 0, 4 or 8, 0 for auto detection. */
983 validate_riscv_insn (const struct riscv_opcode
*opc
, int length
)
985 const char *p
= opc
->args
;
987 insn_t used_bits
= opc
->mask
;
989 insn_t required_bits
;
992 insn_width
= 8 * riscv_insn_length (opc
->match
);
994 insn_width
= 8 * length
;
996 required_bits
= ~0ULL >> (64 - insn_width
);
998 if ((used_bits
& opc
->match
) != (opc
->match
& required_bits
))
1000 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
1001 opc
->name
, opc
->args
);
1005 #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
1012 case 'U': break; /* CRS1, constrained to equal RD. */
1013 case 'c': break; /* CRS1, constrained to equal sp. */
1014 case 'T': /* CRS2, floating point. */
1015 case 'V': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
1016 case 'S': /* CRS1S, floating point. */
1017 case 's': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
1018 case 'w': break; /* CRS1S, constrained to equal RD. */
1019 case 'D': /* CRS2S, floating point. */
1020 case 't': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
1021 case 'x': break; /* CRS2S, constrained to equal RD. */
1022 case 'z': break; /* CRS2S, constrained to be x0. */
1023 case '>': /* CITYPE immediate, compressed shift. */
1024 case 'u': /* CITYPE immediate, compressed lui. */
1025 case 'v': /* CITYPE immediate, li to compressed lui. */
1026 case 'o': /* CITYPE immediate, allow zero. */
1027 case 'j': used_bits
|= ENCODE_CITYPE_IMM (-1U); break;
1028 case 'L': used_bits
|= ENCODE_CITYPE_ADDI16SP_IMM (-1U); break;
1029 case 'm': used_bits
|= ENCODE_CITYPE_LWSP_IMM (-1U); break;
1030 case 'n': used_bits
|= ENCODE_CITYPE_LDSP_IMM (-1U); break;
1031 case '6': used_bits
|= ENCODE_CSSTYPE_IMM (-1U); break;
1032 case 'M': used_bits
|= ENCODE_CSSTYPE_SWSP_IMM (-1U); break;
1033 case 'N': used_bits
|= ENCODE_CSSTYPE_SDSP_IMM (-1U); break;
1034 case '8': used_bits
|= ENCODE_CIWTYPE_IMM (-1U); break;
1035 case 'K': used_bits
|= ENCODE_CIWTYPE_ADDI4SPN_IMM (-1U); break;
1036 /* CLTYPE and CSTYPE have the same immediate encoding. */
1037 case '5': used_bits
|= ENCODE_CLTYPE_IMM (-1U); break;
1038 case 'k': used_bits
|= ENCODE_CLTYPE_LW_IMM (-1U); break;
1039 case 'l': used_bits
|= ENCODE_CLTYPE_LD_IMM (-1U); break;
1040 case 'p': used_bits
|= ENCODE_CBTYPE_IMM (-1U); break;
1041 case 'a': used_bits
|= ENCODE_CJTYPE_IMM (-1U); break;
1042 case 'F': /* Compressed funct for .insn directive. */
1045 case '6': USE_BITS (OP_MASK_CFUNCT6
, OP_SH_CFUNCT6
); break;
1046 case '4': USE_BITS (OP_MASK_CFUNCT4
, OP_SH_CFUNCT4
); break;
1047 case '3': USE_BITS (OP_MASK_CFUNCT3
, OP_SH_CFUNCT3
); break;
1048 case '2': USE_BITS (OP_MASK_CFUNCT2
, OP_SH_CFUNCT2
); break;
1050 as_bad (_("internal: bad RISC-V opcode "
1051 "(unknown operand type `CF%c'): %s %s"),
1052 c
, opc
->name
, opc
->args
);
1057 as_bad (_("internal: bad RISC-V opcode "
1058 "(unknown operand type `C%c'): %s %s"),
1059 c
, opc
->name
, opc
->args
);
1066 case '<': USE_BITS (OP_MASK_SHAMTW
, OP_SH_SHAMTW
); break;
1067 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
1068 case 'A': break; /* Macro operand, must be symbol. */
1069 case 'B': break; /* Macro operand, must be symbol or constant. */
1070 case 'I': break; /* Macro operand, must be constant. */
1071 case 'D': /* RD, floating point. */
1072 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
1073 case 'Z': /* RS1, CSR number. */
1074 case 'S': /* RS1, floating point. */
1075 case 's': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
1076 case 'U': /* RS1 and RS2 are the same, floating point. */
1077 USE_BITS (OP_MASK_RS1
, OP_SH_RS1
);
1079 case 'T': /* RS2, floating point. */
1080 case 't': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
1081 case 'R': /* RS3, floating point. */
1082 case 'r': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
1083 case 'm': USE_BITS (OP_MASK_RM
, OP_SH_RM
); break;
1084 case 'E': USE_BITS (OP_MASK_CSR
, OP_SH_CSR
); break;
1085 case 'P': USE_BITS (OP_MASK_PRED
, OP_SH_PRED
); break;
1086 case 'Q': USE_BITS (OP_MASK_SUCC
, OP_SH_SUCC
); break;
1087 case 'o': /* ITYPE immediate, load displacement. */
1088 case 'j': used_bits
|= ENCODE_ITYPE_IMM (-1U); break;
1089 case 'a': used_bits
|= ENCODE_JTYPE_IMM (-1U); break;
1090 case 'p': used_bits
|= ENCODE_BTYPE_IMM (-1U); break;
1091 case 'q': used_bits
|= ENCODE_STYPE_IMM (-1U); break;
1092 case 'u': used_bits
|= ENCODE_UTYPE_IMM (-1U); break;
1093 case 'z': break; /* Zero immediate. */
1094 case '[': break; /* Unused operand. */
1095 case ']': break; /* Unused operand. */
1096 case '0': break; /* AMO displacement, must to zero. */
1097 case '1': break; /* Relaxation operand. */
1098 case 'F': /* Funct for .insn directive. */
1101 case '7': USE_BITS (OP_MASK_FUNCT7
, OP_SH_FUNCT7
); break;
1102 case '3': USE_BITS (OP_MASK_FUNCT3
, OP_SH_FUNCT3
); break;
1103 case '2': USE_BITS (OP_MASK_FUNCT2
, OP_SH_FUNCT2
); break;
1105 as_bad (_("internal: bad RISC-V opcode "
1106 "(unknown operand type `F%c'): %s %s"),
1107 c
, opc
->name
, opc
->args
);
1111 case 'O': /* Opcode for .insn directive. */
1114 case '4': USE_BITS (OP_MASK_OP
, OP_SH_OP
); break;
1115 case '2': USE_BITS (OP_MASK_OP2
, OP_SH_OP2
); break;
1117 as_bad (_("internal: bad RISC-V opcode "
1118 "(unknown operand type `F%c'): %s %s"),
1119 c
, opc
->name
, opc
->args
);
1124 as_bad (_("internal: bad RISC-V opcode "
1125 "(unknown operand type `%c'): %s %s"),
1126 c
, opc
->name
, opc
->args
);
1130 if (used_bits
!= required_bits
)
1132 as_bad (_("internal: bad RISC-V opcode "
1133 "(bits 0x%lx undefined): %s %s"),
1134 ~(unsigned long)(used_bits
& required_bits
),
1135 opc
->name
, opc
->args
);
1141 struct percent_op_match
1144 bfd_reloc_code_real_type reloc
;
1147 /* Common hash table initialization function for instruction and .insn
1151 init_opcode_hash (const struct riscv_opcode
*opcodes
,
1152 bool insn_directive_p
)
1156 htab_t hash
= str_htab_create ();
1157 while (opcodes
[i
].name
)
1159 const char *name
= opcodes
[i
].name
;
1160 if (str_hash_insert (hash
, name
, &opcodes
[i
], 0) != NULL
)
1161 as_fatal (_("internal: duplicate %s"), name
);
1165 if (opcodes
[i
].pinfo
!= INSN_MACRO
)
1167 if (insn_directive_p
)
1168 length
= ((name
[0] == 'c') ? 2 : 4);
1170 length
= 0; /* Let assembler determine the length. */
1171 if (!validate_riscv_insn (&opcodes
[i
], length
))
1172 as_fatal (_("internal: broken assembler. "
1173 "No assembly attempted"));
1176 gas_assert (!insn_directive_p
);
1179 while (opcodes
[i
].name
&& !strcmp (opcodes
[i
].name
, name
));
1185 /* This function is called once, at assembler startup time. It should set up
1186 all the tables, etc. that the MD part of the assembler will need. */
1191 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
1193 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
1194 as_warn (_("could not set architecture and machine"));
1196 op_hash
= init_opcode_hash (riscv_opcodes
, false);
1197 insn_type_hash
= init_opcode_hash (riscv_insn_types
, true);
1199 reg_names_hash
= str_htab_create ();
1200 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_numeric
, NGPR
);
1201 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_abi
, NGPR
);
1202 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_numeric
, NFPR
);
1203 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_abi
, NFPR
);
1204 /* Add "fp" as an alias for "s0". */
1205 hash_reg_name (RCLASS_GPR
, "fp", 8);
1207 /* Create and insert CSR hash tables. */
1208 csr_extra_hash
= str_htab_create ();
1209 #define DECLARE_CSR(name, num, class, define_version, abort_version) \
1210 riscv_init_csr_hash (#name, num, class, define_version, abort_version);
1211 #define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
1212 DECLARE_CSR(name, num, class, define_version, abort_version);
1213 #include "opcode/riscv-opc.h"
1216 opcode_names_hash
= str_htab_create ();
1217 init_opcode_names_hash ();
1219 /* Set the default alignment for the text section. */
1220 record_alignment (text_section
, riscv_opts
.rvc
? 1 : 2);
1224 riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type
, bfd_vma value
)
1231 case BFD_RELOC_RISCV_HI20
:
1232 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value
));
1234 case BFD_RELOC_RISCV_LO12_S
:
1235 return ENCODE_STYPE_IMM (value
);
1237 case BFD_RELOC_RISCV_LO12_I
:
1238 return ENCODE_ITYPE_IMM (value
);
1245 /* Output an instruction. IP is the instruction information.
1246 ADDRESS_EXPR is an operand of the instruction to be used with
1250 append_insn (struct riscv_cl_insn
*ip
, expressionS
*address_expr
,
1251 bfd_reloc_code_real_type reloc_type
)
1253 dwarf2_emit_insn (0);
1255 if (reloc_type
!= BFD_RELOC_UNUSED
)
1257 reloc_howto_type
*howto
;
1259 gas_assert (address_expr
);
1260 if (reloc_type
== BFD_RELOC_12_PCREL
1261 || reloc_type
== BFD_RELOC_RISCV_JMP
)
1263 int j
= reloc_type
== BFD_RELOC_RISCV_JMP
;
1264 int best_case
= riscv_insn_length (ip
->insn_opcode
);
1265 unsigned worst_case
= relaxed_branch_length (NULL
, NULL
, 0);
1267 if (now_seg
== absolute_section
)
1269 as_bad (_("relaxable branches not supported in absolute section"));
1273 add_relaxed_insn (ip
, worst_case
, best_case
,
1274 RELAX_BRANCH_ENCODE (j
, best_case
== 2, worst_case
),
1275 address_expr
->X_add_symbol
,
1276 address_expr
->X_add_number
);
1281 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
);
1283 as_bad (_("internal: usupported RISC-V relocation number %d"),
1286 ip
->fixp
= fix_new_exp (ip
->frag
, ip
->where
,
1287 bfd_get_reloc_size (howto
),
1288 address_expr
, false, reloc_type
);
1290 ip
->fixp
->fx_tcbit
= riscv_opts
.relax
;
1294 add_fixed_insn (ip
);
1297 /* We need to start a new frag after any instruction that can be
1298 optimized away or compressed by the linker during relaxation, to prevent
1299 the assembler from computing static offsets across such an instruction.
1300 This is necessary to get correct EH info. */
1301 if (reloc_type
== BFD_RELOC_RISCV_HI20
1302 || reloc_type
== BFD_RELOC_RISCV_PCREL_HI20
1303 || reloc_type
== BFD_RELOC_RISCV_TPREL_HI20
1304 || reloc_type
== BFD_RELOC_RISCV_TPREL_ADD
)
1306 frag_wane (frag_now
);
1311 /* Build an instruction created by a macro expansion. This is passed
1312 a pointer to the count of instructions created so far, an expression,
1313 the name of the instruction to build, an operand format string, and
1314 corresponding arguments. */
1317 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
1319 const struct riscv_opcode
*mo
;
1320 struct riscv_cl_insn insn
;
1321 bfd_reloc_code_real_type r
;
1324 va_start (args
, fmt
);
1326 r
= BFD_RELOC_UNUSED
;
1327 mo
= (struct riscv_opcode
*) str_hash_find (op_hash
, name
);
1330 /* Find a non-RVC variant of the instruction. append_insn will compress
1332 while (riscv_insn_length (mo
->match
) < 4)
1334 gas_assert (strcmp (name
, mo
->name
) == 0);
1336 create_insn (&insn
, mo
);
1342 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
1346 INSERT_OPERAND (RS1
, insn
, va_arg (args
, int));
1350 INSERT_OPERAND (RS2
, insn
, va_arg (args
, int));
1356 gas_assert (ep
!= NULL
);
1357 r
= va_arg (args
, int);
1365 as_fatal (_("internal: invalid macro"));
1370 gas_assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1372 append_insn (&insn
, ep
, r
);
1375 /* Build an instruction created by a macro expansion. Like md_assemble but
1376 accept a printf-style format string and arguments. */
1379 md_assemblef (const char *format
, ...)
1385 va_start (ap
, format
);
1387 r
= vasprintf (&buf
, format
, ap
);
1390 as_fatal (_("internal: vasprintf failed"));
1398 /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
1402 normalize_constant_expr (expressionS
*ex
)
1406 if ((ex
->X_op
== O_constant
|| ex
->X_op
== O_symbol
)
1407 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
1408 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
1412 /* Fail if an expression EX is not a constant. IP is the instruction using EX.
1413 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
1416 check_absolute_expr (struct riscv_cl_insn
*ip
, expressionS
*ex
,
1419 if (ex
->X_op
== O_big
)
1420 as_bad (_("unsupported large constant"));
1421 else if (maybe_csr
&& ex
->X_op
== O_symbol
)
1422 as_bad (_("unknown CSR `%s'"),
1423 S_GET_NAME (ex
->X_add_symbol
));
1424 else if (ex
->X_op
!= O_constant
)
1425 as_bad (_("instruction %s requires absolute expression"),
1427 normalize_constant_expr (ex
);
1431 make_internal_label (void)
1433 return (symbolS
*) local_symbol_make (FAKE_LABEL_NAME
, now_seg
, frag_now
,
1437 /* Load an entry from the GOT. */
1440 pcrel_access (int destreg
, int tempreg
, expressionS
*ep
,
1441 const char *lo_insn
, const char *lo_pattern
,
1442 bfd_reloc_code_real_type hi_reloc
,
1443 bfd_reloc_code_real_type lo_reloc
)
1446 ep2
.X_op
= O_symbol
;
1447 ep2
.X_add_symbol
= make_internal_label ();
1448 ep2
.X_add_number
= 0;
1450 macro_build (ep
, "auipc", "d,u", tempreg
, hi_reloc
);
1451 macro_build (&ep2
, lo_insn
, lo_pattern
, destreg
, tempreg
, lo_reloc
);
1455 pcrel_load (int destreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1456 bfd_reloc_code_real_type hi_reloc
,
1457 bfd_reloc_code_real_type lo_reloc
)
1459 pcrel_access (destreg
, tempreg
, ep
, lo_insn
, "d,s,j", hi_reloc
, lo_reloc
);
1463 pcrel_store (int srcreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1464 bfd_reloc_code_real_type hi_reloc
,
1465 bfd_reloc_code_real_type lo_reloc
)
1467 pcrel_access (srcreg
, tempreg
, ep
, lo_insn
, "t,s,q", hi_reloc
, lo_reloc
);
1470 /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
1473 riscv_call (int destreg
, int tempreg
, expressionS
*ep
,
1474 bfd_reloc_code_real_type reloc
)
1476 /* Ensure the jalr is emitted to the same frag as the auipc. */
1478 macro_build (ep
, "auipc", "d,u", tempreg
, reloc
);
1479 macro_build (NULL
, "jalr", "d,s", destreg
, tempreg
);
1480 /* See comment at end of append_insn. */
1481 frag_wane (frag_now
);
1485 /* Load an integer constant into a register. */
1488 load_const (int reg
, expressionS
*ep
)
1490 int shift
= RISCV_IMM_BITS
;
1491 bfd_vma upper_imm
, sign
= (bfd_vma
) 1 << (RISCV_IMM_BITS
- 1);
1492 expressionS upper
= *ep
, lower
= *ep
;
1493 lower
.X_add_number
= ((ep
->X_add_number
& (sign
+ sign
- 1)) ^ sign
) - sign
;
1494 upper
.X_add_number
-= lower
.X_add_number
;
1496 if (ep
->X_op
!= O_constant
)
1498 as_bad (_("unsupported large constant"));
1502 if (xlen
> 32 && !IS_SEXT_32BIT_NUM (ep
->X_add_number
))
1504 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1505 while (((upper
.X_add_number
>> shift
) & 1) == 0)
1508 upper
.X_add_number
= (int64_t) upper
.X_add_number
>> shift
;
1509 load_const (reg
, &upper
);
1511 md_assemblef ("slli x%d, x%d, 0x%x", reg
, reg
, shift
);
1512 if (lower
.X_add_number
!= 0)
1513 md_assemblef ("addi x%d, x%d, %" BFD_VMA_FMT
"d", reg
, reg
,
1514 lower
.X_add_number
);
1518 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1521 if (upper
.X_add_number
!= 0)
1523 /* Discard low part and zero-extend upper immediate. */
1524 upper_imm
= ((uint32_t)upper
.X_add_number
>> shift
);
1526 md_assemblef ("lui x%d, 0x%" BFD_VMA_FMT
"x", reg
, upper_imm
);
1530 if (lower
.X_add_number
!= 0 || hi_reg
== 0)
1531 md_assemblef ("%s x%d, x%d, %" BFD_VMA_FMT
"d", ADD32_INSN
, reg
, hi_reg
,
1532 lower
.X_add_number
);
1536 /* Zero extend and sign extend byte/half-word/word. */
1539 riscv_ext (int destreg
, int srcreg
, unsigned shift
, bool sign
)
1543 md_assemblef ("slli x%d, x%d, 0x%x", destreg
, srcreg
, shift
);
1544 md_assemblef ("srai x%d, x%d, 0x%x", destreg
, destreg
, shift
);
1548 md_assemblef ("slli x%d, x%d, 0x%x", destreg
, srcreg
, shift
);
1549 md_assemblef ("srli x%d, x%d, 0x%x", destreg
, destreg
, shift
);
1553 /* Expand RISC-V assembly macros into one or more instructions. */
1556 macro (struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1557 bfd_reloc_code_real_type
*imm_reloc
)
1559 int rd
= (ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
;
1560 int rs1
= (ip
->insn_opcode
>> OP_SH_RS1
) & OP_MASK_RS1
;
1561 int rs2
= (ip
->insn_opcode
>> OP_SH_RS2
) & OP_MASK_RS2
;
1562 int mask
= ip
->insn_mo
->mask
;
1567 load_const (rd
, imm_expr
);
1572 /* Load the address of a symbol into a register. */
1573 if (!IS_SEXT_32BIT_NUM (imm_expr
->X_add_number
))
1574 as_bad (_("offset too large"));
1576 if (imm_expr
->X_op
== O_constant
)
1577 load_const (rd
, imm_expr
);
1578 else if (riscv_opts
.pic
&& mask
== M_LA
) /* Global PIC symbol. */
1579 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1580 BFD_RELOC_RISCV_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1581 else /* Local PIC symbol, or any non-PIC symbol. */
1582 pcrel_load (rd
, rd
, imm_expr
, "addi",
1583 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1587 pcrel_load (rd
, rd
, imm_expr
, "addi",
1588 BFD_RELOC_RISCV_TLS_GD_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1592 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1593 BFD_RELOC_RISCV_TLS_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1597 pcrel_load (rd
, rd
, imm_expr
, "lb",
1598 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1602 pcrel_load (rd
, rd
, imm_expr
, "lbu",
1603 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1607 pcrel_load (rd
, rd
, imm_expr
, "lh",
1608 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1612 pcrel_load (rd
, rd
, imm_expr
, "lhu",
1613 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1617 pcrel_load (rd
, rd
, imm_expr
, "lw",
1618 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1622 pcrel_load (rd
, rd
, imm_expr
, "lwu",
1623 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1627 pcrel_load (rd
, rd
, imm_expr
, "ld",
1628 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1632 pcrel_load (rd
, rs1
, imm_expr
, "flw",
1633 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1637 pcrel_load (rd
, rs1
, imm_expr
, "fld",
1638 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1642 pcrel_store (rs2
, rs1
, imm_expr
, "sb",
1643 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1647 pcrel_store (rs2
, rs1
, imm_expr
, "sh",
1648 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1652 pcrel_store (rs2
, rs1
, imm_expr
, "sw",
1653 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1657 pcrel_store (rs2
, rs1
, imm_expr
, "sd",
1658 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1662 pcrel_store (rs2
, rs1
, imm_expr
, "fsw",
1663 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1667 pcrel_store (rs2
, rs1
, imm_expr
, "fsd",
1668 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1672 riscv_call (rd
, rs1
, imm_expr
, *imm_reloc
);
1676 riscv_ext (rd
, rs1
, xlen
- 16, false);
1680 riscv_ext (rd
, rs1
, xlen
- 32, false);
1684 riscv_ext (rd
, rs1
, xlen
- 8, true);
1688 riscv_ext (rd
, rs1
, xlen
- 16, true);
1692 as_bad (_("internal: macro %s not implemented"), ip
->insn_mo
->name
);
1697 static const struct percent_op_match percent_op_utype
[] =
1699 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20
},
1700 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20
},
1701 {"%got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20
},
1702 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20
},
1703 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20
},
1704 {"%hi", BFD_RELOC_RISCV_HI20
},
1708 static const struct percent_op_match percent_op_itype
[] =
1710 {"%lo", BFD_RELOC_RISCV_LO12_I
},
1711 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I
},
1712 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I
},
1716 static const struct percent_op_match percent_op_stype
[] =
1718 {"%lo", BFD_RELOC_RISCV_LO12_S
},
1719 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S
},
1720 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S
},
1724 static const struct percent_op_match percent_op_rtype
[] =
1726 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD
},
1730 static const struct percent_op_match percent_op_null
[] =
1735 /* Return true if *STR points to a relocation operator. When returning true,
1736 move *STR over the operator and store its relocation code in *RELOC.
1737 Leave both *STR and *RELOC alone when returning false. */
1740 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
,
1741 const struct percent_op_match
*percent_op
)
1743 for ( ; percent_op
->str
; percent_op
++)
1744 if (strncasecmp (*str
, percent_op
->str
, strlen (percent_op
->str
)) == 0)
1746 int len
= strlen (percent_op
->str
);
1748 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
1751 *str
+= strlen (percent_op
->str
);
1752 *reloc
= percent_op
->reloc
;
1754 /* Check whether the output BFD supports this relocation.
1755 If not, issue an error and fall back on something safe. */
1756 if (*reloc
!= BFD_RELOC_UNUSED
1757 && !bfd_reloc_type_lookup (stdoutput
, *reloc
))
1759 as_bad ("internal: relocation %s isn't supported by the "
1760 "current ABI", percent_op
->str
);
1761 *reloc
= BFD_RELOC_UNUSED
;
1769 my_getExpression (expressionS
*ep
, char *str
)
1773 save_in
= input_line_pointer
;
1774 input_line_pointer
= str
;
1776 expr_end
= input_line_pointer
;
1777 input_line_pointer
= save_in
;
1780 /* Parse string STR as a 16-bit relocatable operand. Store the
1781 expression in *EP and the relocation, if any, in RELOC.
1782 Return the number of relocation operators used (0 or 1).
1784 On exit, EXPR_END points to the first character after the expression. */
1787 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1788 char *str
, const struct percent_op_match
*percent_op
)
1791 unsigned crux_depth
, str_depth
, regno
;
1794 /* First, check for integer registers. No callers can accept a reg, but
1795 we need to avoid accidentally creating a useless undefined symbol below,
1796 if this is an instruction pattern that can't match. A glibc build fails
1797 if this is removed. */
1798 if (reg_lookup (&str
, RCLASS_GPR
, ®no
))
1800 ep
->X_op
= O_register
;
1801 ep
->X_add_number
= regno
;
1806 /* Search for the start of the main expression.
1808 End the loop with CRUX pointing to the start of the main expression and
1809 with CRUX_DEPTH containing the number of open brackets at that point. */
1816 crux_depth
= str_depth
;
1818 /* Skip over whitespace and brackets, keeping count of the number
1820 while (*str
== ' ' || *str
== '\t' || *str
== '(')
1826 && parse_relocation (&str
, reloc
, percent_op
));
1828 my_getExpression (ep
, crux
);
1831 /* Match every open bracket. */
1832 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
1837 as_bad ("unclosed '('");
1844 /* Parse opcode name, could be an mnemonics or number. */
1847 my_getOpcodeExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1848 char *str
, const struct percent_op_match
*percent_op
)
1850 const struct opcode_name_t
*o
= opcode_name_lookup (&str
);
1854 ep
->X_op
= O_constant
;
1855 ep
->X_add_number
= o
->val
;
1859 return my_getSmallExpression (ep
, reloc
, str
, percent_op
);
1862 /* Detect and handle implicitly zero load-store offsets. For example,
1863 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
1864 an implicit offset was detected. */
1867 riscv_handle_implicit_zero_offset (expressionS
*ep
, const char *s
)
1869 /* Check whether there is only a single bracketed expression left.
1870 If so, it must be the base register and the constant must be zero. */
1871 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
1873 ep
->X_op
= O_constant
;
1874 ep
->X_add_number
= 0;
1881 /* All RISC-V CSR instructions belong to one of these classes. */
1890 /* Return which CSR instruction is checking. */
1892 static enum csr_insn_type
1893 riscv_csr_insn_type (insn_t insn
)
1895 if (((insn
^ MATCH_CSRRW
) & MASK_CSRRW
) == 0
1896 || ((insn
^ MATCH_CSRRWI
) & MASK_CSRRWI
) == 0)
1898 else if (((insn
^ MATCH_CSRRS
) & MASK_CSRRS
) == 0
1899 || ((insn
^ MATCH_CSRRSI
) & MASK_CSRRSI
) == 0)
1901 else if (((insn
^ MATCH_CSRRC
) & MASK_CSRRC
) == 0
1902 || ((insn
^ MATCH_CSRRCI
) & MASK_CSRRCI
) == 0)
1905 return INSN_NOT_CSR
;
1908 /* CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write
1909 CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of
1910 CSR address is 0x3. */
1913 riscv_csr_read_only_check (insn_t insn
)
1915 int csr
= (insn
& (OP_MASK_CSR
<< OP_SH_CSR
)) >> OP_SH_CSR
;
1916 int rs1
= (insn
& (OP_MASK_RS1
<< OP_SH_RS1
)) >> OP_SH_RS1
;
1917 int readonly
= (((csr
& (0x3 << 10)) >> 10) == 0x3);
1918 enum csr_insn_type csr_insn
= riscv_csr_insn_type (insn
);
1921 && (((csr_insn
== INSN_CSRRS
1922 || csr_insn
== INSN_CSRRC
)
1924 || csr_insn
== INSN_CSRRW
))
1930 /* Return True if it is a privileged instruction. Otherwise, return FALSE.
1932 uret is actually a N-ext instruction. So it is better to regard it as
1933 an user instruction rather than the priv instruction.
1935 hret is used to return from traps in H-mode. H-mode is removed since
1936 the v1.10 priv spec, but probably be added in the new hypervisor spec.
1937 Therefore, hret should be controlled by the hypervisor spec rather than
1938 priv spec in the future.
1940 dret is defined in the debug spec, so it should be checked in the future,
1944 riscv_is_priv_insn (insn_t insn
)
1946 return (((insn
^ MATCH_SRET
) & MASK_SRET
) == 0
1947 || ((insn
^ MATCH_MRET
) & MASK_MRET
) == 0
1948 || ((insn
^ MATCH_SFENCE_VMA
) & MASK_SFENCE_VMA
) == 0
1949 || ((insn
^ MATCH_WFI
) & MASK_WFI
) == 0
1950 /* The sfence.vm is dropped in the v1.10 priv specs, but we still need to
1951 check it here to keep the compatible. */
1952 || ((insn
^ MATCH_SFENCE_VM
) & MASK_SFENCE_VM
) == 0);
1955 /* This routine assembles an instruction into its binary format. As a
1956 side effect, it sets the global variable imm_reloc to the type of
1957 relocation to do if one of the operands is an address expression. */
1960 riscv_ip (char *str
, struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1961 bfd_reloc_code_real_type
*imm_reloc
, htab_t hash
)
1966 struct riscv_opcode
*insn
;
1971 const struct percent_op_match
*p
;
1972 const char *error
= "unrecognized opcode";
1973 /* Indicate we are assembling instruction with CSR. */
1974 bool insn_with_csr
= false;
1976 /* Parse the name of the instruction. Terminate the string if whitespace
1977 is found so that str_hash_find only sees the name part of the string. */
1978 for (s
= str
; *s
!= '\0'; ++s
)
1986 insn
= (struct riscv_opcode
*) str_hash_find (hash
, str
);
1989 for ( ; insn
&& insn
->name
&& strcmp (insn
->name
, str
) == 0; insn
++)
1991 if ((insn
->xlen_requirement
!= 0) && (xlen
!= insn
->xlen_requirement
))
1994 if (!riscv_multi_subset_supports (insn
->insn_class
))
1997 create_insn (ip
, insn
);
2000 imm_expr
->X_op
= O_absent
;
2001 *imm_reloc
= BFD_RELOC_UNUSED
;
2002 p
= percent_op_itype
;
2004 for (args
= insn
->args
;; ++args
)
2006 s
+= strspn (s
, " \t");
2009 case '\0': /* End of args. */
2010 if (insn
->pinfo
!= INSN_MACRO
)
2012 if (!insn
->match_func (insn
, ip
->insn_opcode
))
2015 /* For .insn, insn->match and insn->mask are 0. */
2016 if (riscv_insn_length ((insn
->match
== 0 && insn
->mask
== 0)
2022 if (riscv_is_priv_insn (ip
->insn_opcode
))
2023 explicit_priv_attr
= true;
2025 /* Check if we write a read-only CSR by the CSR
2028 && riscv_opts
.csr_check
2029 && !riscv_csr_read_only_check (ip
->insn_opcode
))
2031 /* Restore the character in advance, since we want to
2032 report the detailed warning message here. */
2034 *(argsStart
- 1) = save_c
;
2035 as_warn (_("read-only CSR is written `%s'"), str
);
2036 insn_with_csr
= false;
2041 /* Successful assembly. */
2043 insn_with_csr
= false;
2049 case 's': /* RS1 x8-x15. */
2050 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
2051 || !(regno
>= 8 && regno
<= 15))
2053 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
2055 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
2056 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
2057 || EXTRACT_OPERAND (CRS1S
, ip
->insn_opcode
) + 8 != regno
)
2060 case 't': /* RS2 x8-x15. */
2061 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
2062 || !(regno
>= 8 && regno
<= 15))
2064 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
2066 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
2067 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
2068 || EXTRACT_OPERAND (CRS2S
, ip
->insn_opcode
) + 8 != regno
)
2071 case 'U': /* RS1, constrained to equal RD. */
2072 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
2073 || EXTRACT_OPERAND (RD
, ip
->insn_opcode
) != regno
)
2077 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
))
2079 INSERT_OPERAND (CRS2
, *ip
, regno
);
2081 case 'c': /* RS1, constrained to equal sp. */
2082 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
2086 case 'z': /* RS2, constrained to equal x0. */
2087 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
2091 case '>': /* Shift amount, 0 - (XLEN-1). */
2092 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2093 || imm_expr
->X_op
!= O_constant
2094 || (unsigned long) imm_expr
->X_add_number
>= xlen
)
2096 ip
->insn_opcode
|= ENCODE_CITYPE_IMM (imm_expr
->X_add_number
);
2099 imm_expr
->X_op
= O_absent
;
2102 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2103 || imm_expr
->X_op
!= O_constant
2104 || imm_expr
->X_add_number
< 0
2105 || imm_expr
->X_add_number
>= 32
2106 || !VALID_CLTYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2108 ip
->insn_opcode
|= ENCODE_CLTYPE_IMM (imm_expr
->X_add_number
);
2111 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2112 || imm_expr
->X_op
!= O_constant
2113 || imm_expr
->X_add_number
< 0
2114 || imm_expr
->X_add_number
>= 64
2115 || !VALID_CSSTYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2117 ip
->insn_opcode
|= ENCODE_CSSTYPE_IMM (imm_expr
->X_add_number
);
2120 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2121 || imm_expr
->X_op
!= O_constant
2122 || imm_expr
->X_add_number
< 0
2123 || imm_expr
->X_add_number
>= 256
2124 || !VALID_CIWTYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2126 ip
->insn_opcode
|= ENCODE_CIWTYPE_IMM (imm_expr
->X_add_number
);
2129 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2130 || imm_expr
->X_op
!= O_constant
2131 || imm_expr
->X_add_number
== 0
2132 || !VALID_CITYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2134 ip
->insn_opcode
|= ENCODE_CITYPE_IMM (imm_expr
->X_add_number
);
2137 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2139 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2140 || imm_expr
->X_op
!= O_constant
2141 || !VALID_CLTYPE_LW_IMM ((valueT
) imm_expr
->X_add_number
))
2143 ip
->insn_opcode
|= ENCODE_CLTYPE_LW_IMM (imm_expr
->X_add_number
);
2146 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2148 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2149 || imm_expr
->X_op
!= O_constant
2150 || !VALID_CLTYPE_LD_IMM ((valueT
) imm_expr
->X_add_number
))
2152 ip
->insn_opcode
|= ENCODE_CLTYPE_LD_IMM (imm_expr
->X_add_number
);
2155 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2157 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2158 || imm_expr
->X_op
!= O_constant
2159 || !VALID_CITYPE_LWSP_IMM ((valueT
) imm_expr
->X_add_number
))
2162 ENCODE_CITYPE_LWSP_IMM (imm_expr
->X_add_number
);
2165 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2167 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2168 || imm_expr
->X_op
!= O_constant
2169 || !VALID_CITYPE_LDSP_IMM ((valueT
) imm_expr
->X_add_number
))
2172 ENCODE_CITYPE_LDSP_IMM (imm_expr
->X_add_number
);
2175 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2176 || imm_expr
->X_op
!= O_constant
2177 /* C.addiw, c.li, and c.andi allow zero immediate.
2178 C.addi allows zero immediate as hint. Otherwise this
2180 || !VALID_CITYPE_IMM ((valueT
) imm_expr
->X_add_number
))
2182 ip
->insn_opcode
|= ENCODE_CITYPE_IMM (imm_expr
->X_add_number
);
2185 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2186 || imm_expr
->X_op
!= O_constant
2187 || imm_expr
->X_add_number
== 0
2188 || !VALID_CIWTYPE_ADDI4SPN_IMM ((valueT
) imm_expr
->X_add_number
))
2191 ENCODE_CIWTYPE_ADDI4SPN_IMM (imm_expr
->X_add_number
);
2194 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2195 || imm_expr
->X_op
!= O_constant
2196 || !VALID_CITYPE_ADDI16SP_IMM ((valueT
) imm_expr
->X_add_number
))
2199 ENCODE_CITYPE_ADDI16SP_IMM (imm_expr
->X_add_number
);
2202 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2204 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2205 || imm_expr
->X_op
!= O_constant
2206 || !VALID_CSSTYPE_SWSP_IMM ((valueT
) imm_expr
->X_add_number
))
2209 ENCODE_CSSTYPE_SWSP_IMM (imm_expr
->X_add_number
);
2212 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2214 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2215 || imm_expr
->X_op
!= O_constant
2216 || !VALID_CSSTYPE_SDSP_IMM ((valueT
) imm_expr
->X_add_number
))
2219 ENCODE_CSSTYPE_SDSP_IMM (imm_expr
->X_add_number
);
2222 p
= percent_op_utype
;
2223 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2226 if (imm_expr
->X_op
!= O_constant
2227 || imm_expr
->X_add_number
<= 0
2228 || imm_expr
->X_add_number
>= RISCV_BIGIMM_REACH
2229 || (imm_expr
->X_add_number
>= RISCV_RVC_IMM_REACH
/ 2
2230 && (imm_expr
->X_add_number
<
2231 RISCV_BIGIMM_REACH
- RISCV_RVC_IMM_REACH
/ 2)))
2233 ip
->insn_opcode
|= ENCODE_CITYPE_IMM (imm_expr
->X_add_number
);
2236 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2237 || (imm_expr
->X_add_number
& (RISCV_IMM_REACH
- 1))
2238 || ((int32_t)imm_expr
->X_add_number
2239 != imm_expr
->X_add_number
))
2241 imm_expr
->X_add_number
=
2242 ((uint32_t) imm_expr
->X_add_number
) >> RISCV_IMM_BITS
;
2248 case 'S': /* Floating-point RS1 x8-x15. */
2249 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
2250 || !(regno
>= 8 && regno
<= 15))
2252 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
2254 case 'D': /* Floating-point RS2 x8-x15. */
2255 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
2256 || !(regno
>= 8 && regno
<= 15))
2258 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
2260 case 'T': /* Floating-point RS2. */
2261 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
))
2263 INSERT_OPERAND (CRS2
, *ip
, regno
);
2269 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2270 || imm_expr
->X_op
!= O_constant
2271 || imm_expr
->X_add_number
< 0
2272 || imm_expr
->X_add_number
>= 64)
2274 as_bad (_("bad value for compressed funct6 "
2275 "field, value must be 0...64"));
2278 INSERT_OPERAND (CFUNCT6
, *ip
, imm_expr
->X_add_number
);
2279 imm_expr
->X_op
= O_absent
;
2284 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2285 || imm_expr
->X_op
!= O_constant
2286 || imm_expr
->X_add_number
< 0
2287 || imm_expr
->X_add_number
>= 16)
2289 as_bad (_("bad value for compressed funct4 "
2290 "field, value must be 0...15"));
2293 INSERT_OPERAND (CFUNCT4
, *ip
, imm_expr
->X_add_number
);
2294 imm_expr
->X_op
= O_absent
;
2299 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2300 || imm_expr
->X_op
!= O_constant
2301 || imm_expr
->X_add_number
< 0
2302 || imm_expr
->X_add_number
>= 8)
2304 as_bad (_("bad value for compressed funct3 "
2305 "field, value must be 0...7"));
2308 INSERT_OPERAND (CFUNCT3
, *ip
, imm_expr
->X_add_number
);
2309 imm_expr
->X_op
= O_absent
;
2314 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2315 || imm_expr
->X_op
!= O_constant
2316 || imm_expr
->X_add_number
< 0
2317 || imm_expr
->X_add_number
>= 4)
2319 as_bad (_("bad value for compressed funct2 "
2320 "field, value must be 0...3"));
2323 INSERT_OPERAND (CFUNCT2
, *ip
, imm_expr
->X_add_number
);
2324 imm_expr
->X_op
= O_absent
;
2329 as_bad (_("internal: unknown compressed funct "
2330 "field specifier `CF%c'"), *args
);
2335 as_bad (_("internal: unknown compressed field "
2336 "specifier `C%c'"), *args
);
2355 case '<': /* Shift amount, 0 - 31. */
2356 my_getExpression (imm_expr
, s
);
2357 check_absolute_expr (ip
, imm_expr
, false);
2358 if ((unsigned long) imm_expr
->X_add_number
> 31)
2359 as_bad (_("improper shift amount (%lu)"),
2360 (unsigned long) imm_expr
->X_add_number
);
2361 INSERT_OPERAND (SHAMTW
, *ip
, imm_expr
->X_add_number
);
2362 imm_expr
->X_op
= O_absent
;
2366 case '>': /* Shift amount, 0 - (XLEN-1). */
2367 my_getExpression (imm_expr
, s
);
2368 check_absolute_expr (ip
, imm_expr
, false);
2369 if ((unsigned long) imm_expr
->X_add_number
>= xlen
)
2370 as_bad (_("improper shift amount (%lu)"),
2371 (unsigned long) imm_expr
->X_add_number
);
2372 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
->X_add_number
);
2373 imm_expr
->X_op
= O_absent
;
2377 case 'Z': /* CSRRxI immediate. */
2378 my_getExpression (imm_expr
, s
);
2379 check_absolute_expr (ip
, imm_expr
, false);
2380 if ((unsigned long) imm_expr
->X_add_number
> 31)
2381 as_bad (_("improper CSRxI immediate (%lu)"),
2382 (unsigned long) imm_expr
->X_add_number
);
2383 INSERT_OPERAND (RS1
, *ip
, imm_expr
->X_add_number
);
2384 imm_expr
->X_op
= O_absent
;
2388 case 'E': /* Control register. */
2389 insn_with_csr
= true;
2390 explicit_priv_attr
= true;
2391 if (reg_lookup (&s
, RCLASS_CSR
, ®no
))
2392 INSERT_OPERAND (CSR
, *ip
, regno
);
2395 my_getExpression (imm_expr
, s
);
2396 check_absolute_expr (ip
, imm_expr
, true);
2397 if ((unsigned long) imm_expr
->X_add_number
> 0xfff)
2398 as_bad (_("improper CSR address (%lu)"),
2399 (unsigned long) imm_expr
->X_add_number
);
2400 INSERT_OPERAND (CSR
, *ip
, imm_expr
->X_add_number
);
2401 imm_expr
->X_op
= O_absent
;
2406 case 'm': /* Rounding mode. */
2407 if (arg_lookup (&s
, riscv_rm
, ARRAY_SIZE (riscv_rm
), ®no
))
2409 INSERT_OPERAND (RM
, *ip
, regno
);
2415 case 'Q': /* Fence predecessor/successor. */
2416 if (arg_lookup (&s
, riscv_pred_succ
, ARRAY_SIZE (riscv_pred_succ
),
2420 INSERT_OPERAND (PRED
, *ip
, regno
);
2422 INSERT_OPERAND (SUCC
, *ip
, regno
);
2427 case 'd': /* Destination register. */
2428 case 's': /* Source register. */
2429 case 't': /* Target register. */
2431 if (reg_lookup (&s
, RCLASS_GPR
, ®no
))
2437 /* Now that we have assembled one operand, we use the args
2438 string to figure out where it goes in the instruction. */
2442 INSERT_OPERAND (RS1
, *ip
, regno
);
2445 INSERT_OPERAND (RD
, *ip
, regno
);
2448 INSERT_OPERAND (RS2
, *ip
, regno
);
2451 INSERT_OPERAND (RS3
, *ip
, regno
);
2458 case 'D': /* Floating point RD. */
2459 case 'S': /* Floating point RS1. */
2460 case 'T': /* Floating point RS2. */
2461 case 'U': /* Floating point RS1 and RS2. */
2462 case 'R': /* Floating point RS3. */
2463 if (reg_lookup (&s
, RCLASS_FPR
, ®no
))
2471 INSERT_OPERAND (RD
, *ip
, regno
);
2474 INSERT_OPERAND (RS1
, *ip
, regno
);
2477 INSERT_OPERAND (RS1
, *ip
, regno
);
2480 INSERT_OPERAND (RS2
, *ip
, regno
);
2483 INSERT_OPERAND (RS3
, *ip
, regno
);
2491 my_getExpression (imm_expr
, s
);
2492 if (imm_expr
->X_op
!= O_big
2493 && imm_expr
->X_op
!= O_constant
)
2495 normalize_constant_expr (imm_expr
);
2500 my_getExpression (imm_expr
, s
);
2501 normalize_constant_expr (imm_expr
);
2502 /* The 'A' format specifier must be a symbol. */
2503 if (imm_expr
->X_op
!= O_symbol
)
2505 *imm_reloc
= BFD_RELOC_32
;
2510 my_getExpression (imm_expr
, s
);
2511 normalize_constant_expr (imm_expr
);
2512 /* The 'B' format specifier must be a symbol or a constant. */
2513 if (imm_expr
->X_op
!= O_symbol
&& imm_expr
->X_op
!= O_constant
)
2515 if (imm_expr
->X_op
== O_symbol
)
2516 *imm_reloc
= BFD_RELOC_32
;
2520 case 'j': /* Sign-extended immediate. */
2521 p
= percent_op_itype
;
2522 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
2524 case 'q': /* Store displacement. */
2525 p
= percent_op_stype
;
2526 *imm_reloc
= BFD_RELOC_RISCV_LO12_S
;
2528 case 'o': /* Load displacement. */
2529 p
= percent_op_itype
;
2530 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
2533 /* This is used for TLS, where the fourth operand is
2534 %tprel_add, to get a relocation applied to an add
2535 instruction, for relaxation to use. */
2536 p
= percent_op_rtype
;
2538 case '0': /* AMO displacement, which must be zero. */
2539 p
= percent_op_null
;
2541 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2544 /* If this value won't fit into a 16 bit offset, then go
2545 find a macro that will generate the 32 bit offset
2547 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2549 normalize_constant_expr (imm_expr
);
2550 if (imm_expr
->X_op
!= O_constant
2551 || (*args
== '0' && imm_expr
->X_add_number
!= 0)
2553 || imm_expr
->X_add_number
>= (signed)RISCV_IMM_REACH
/2
2554 || imm_expr
->X_add_number
< -(signed)RISCV_IMM_REACH
/2)
2560 case 'p': /* PC-relative offset. */
2562 *imm_reloc
= BFD_RELOC_12_PCREL
;
2563 my_getExpression (imm_expr
, s
);
2567 case 'u': /* Upper 20 bits. */
2568 p
= percent_op_utype
;
2569 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2571 if (imm_expr
->X_op
!= O_constant
)
2574 if (imm_expr
->X_add_number
< 0
2575 || imm_expr
->X_add_number
>= (signed)RISCV_BIGIMM_REACH
)
2576 as_bad (_("lui expression not in range 0..1048575"));
2578 *imm_reloc
= BFD_RELOC_RISCV_HI20
;
2579 imm_expr
->X_add_number
<<= RISCV_IMM_BITS
;
2584 case 'a': /* 20-bit PC-relative offset. */
2586 my_getExpression (imm_expr
, s
);
2588 *imm_reloc
= BFD_RELOC_RISCV_JMP
;
2592 my_getExpression (imm_expr
, s
);
2594 if (strcmp (s
, "@plt") == 0)
2596 *imm_reloc
= BFD_RELOC_RISCV_CALL_PLT
;
2600 *imm_reloc
= BFD_RELOC_RISCV_CALL
;
2607 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2608 || imm_expr
->X_op
!= O_constant
2609 || imm_expr
->X_add_number
< 0
2610 || imm_expr
->X_add_number
>= 128
2611 || (imm_expr
->X_add_number
& 0x3) != 3)
2613 as_bad (_("bad value for opcode field, "
2614 "value must be 0...127 and "
2615 "lower 2 bits must be 0x3"));
2618 INSERT_OPERAND (OP
, *ip
, imm_expr
->X_add_number
);
2619 imm_expr
->X_op
= O_absent
;
2624 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2625 || imm_expr
->X_op
!= O_constant
2626 || imm_expr
->X_add_number
< 0
2627 || imm_expr
->X_add_number
>= 3)
2629 as_bad (_("bad value for opcode field, "
2630 "value must be 0...2"));
2633 INSERT_OPERAND (OP2
, *ip
, imm_expr
->X_add_number
);
2634 imm_expr
->X_op
= O_absent
;
2639 as_bad (_("internal: unknown opcode field "
2640 "specifier `O%c'"), *args
);
2648 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2649 || imm_expr
->X_op
!= O_constant
2650 || imm_expr
->X_add_number
< 0
2651 || imm_expr
->X_add_number
>= 128)
2653 as_bad (_("bad value for funct7 field, "
2654 "value must be 0...127"));
2657 INSERT_OPERAND (FUNCT7
, *ip
, imm_expr
->X_add_number
);
2658 imm_expr
->X_op
= O_absent
;
2663 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2664 || imm_expr
->X_op
!= O_constant
2665 || imm_expr
->X_add_number
< 0
2666 || imm_expr
->X_add_number
>= 8)
2668 as_bad (_("bad value for funct3 field, "
2669 "value must be 0...7"));
2672 INSERT_OPERAND (FUNCT3
, *ip
, imm_expr
->X_add_number
);
2673 imm_expr
->X_op
= O_absent
;
2678 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2679 || imm_expr
->X_op
!= O_constant
2680 || imm_expr
->X_add_number
< 0
2681 || imm_expr
->X_add_number
>= 4)
2683 as_bad (_("bad value for funct2 field, "
2684 "value must be 0...3"));
2687 INSERT_OPERAND (FUNCT2
, *ip
, imm_expr
->X_add_number
);
2688 imm_expr
->X_op
= O_absent
;
2693 as_bad (_("internal: unknown funct field "
2694 "specifier `F%c'\n"), *args
);
2699 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2700 || imm_expr
->X_op
!= O_constant
2701 || imm_expr
->X_add_number
!= 0)
2704 imm_expr
->X_op
= O_absent
;
2708 as_fatal (_("internal: unknown argument type `%c'"), *args
);
2713 error
= _("illegal operands");
2714 insn_with_csr
= false;
2718 /* Restore the character we might have clobbered above. */
2720 *(argsStart
- 1) = save_c
;
2726 md_assemble (char *str
)
2728 struct riscv_cl_insn insn
;
2729 expressionS imm_expr
;
2730 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
2732 /* The architecture and privileged elf attributes should be set
2733 before assembling. */
2734 if (!start_assemble
)
2736 start_assemble
= true;
2738 riscv_set_abi_by_arch ();
2739 if (!riscv_set_default_priv_spec (NULL
))
2743 const char *error
= riscv_ip (str
, &insn
, &imm_expr
, &imm_reloc
, op_hash
);
2747 as_bad ("%s `%s'", error
, str
);
2751 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2752 macro (&insn
, &imm_expr
, &imm_reloc
);
2754 append_insn (&insn
, &imm_expr
, imm_reloc
);
2758 md_atof (int type
, char *litP
, int *sizeP
)
2760 return ieee_md_atof (type
, litP
, sizeP
, TARGET_BYTES_BIG_ENDIAN
);
2764 md_number_to_chars (char *buf
, valueT val
, int n
)
2766 if (target_big_endian
)
2767 number_to_chars_bigendian (buf
, val
, n
);
2769 number_to_chars_littleendian (buf
, val
, n
);
2772 const char *md_shortopts
= "O::g::G:";
2776 OPTION_MARCH
= OPTION_MD_BASE
,
2783 OPTION_NO_ARCH_ATTR
,
2785 OPTION_NO_CSR_CHECK
,
2789 OPTION_LITTLE_ENDIAN
,
2793 struct option md_longopts
[] =
2795 {"march", required_argument
, NULL
, OPTION_MARCH
},
2796 {"fPIC", no_argument
, NULL
, OPTION_PIC
},
2797 {"fpic", no_argument
, NULL
, OPTION_PIC
},
2798 {"fno-pic", no_argument
, NULL
, OPTION_NO_PIC
},
2799 {"mabi", required_argument
, NULL
, OPTION_MABI
},
2800 {"mrelax", no_argument
, NULL
, OPTION_RELAX
},
2801 {"mno-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
2802 {"march-attr", no_argument
, NULL
, OPTION_ARCH_ATTR
},
2803 {"mno-arch-attr", no_argument
, NULL
, OPTION_NO_ARCH_ATTR
},
2804 {"mcsr-check", no_argument
, NULL
, OPTION_CSR_CHECK
},
2805 {"mno-csr-check", no_argument
, NULL
, OPTION_NO_CSR_CHECK
},
2806 {"misa-spec", required_argument
, NULL
, OPTION_MISA_SPEC
},
2807 {"mpriv-spec", required_argument
, NULL
, OPTION_MPRIV_SPEC
},
2808 {"mbig-endian", no_argument
, NULL
, OPTION_BIG_ENDIAN
},
2809 {"mlittle-endian", no_argument
, NULL
, OPTION_LITTLE_ENDIAN
},
2811 {NULL
, no_argument
, NULL
, 0}
2813 size_t md_longopts_size
= sizeof (md_longopts
);
2816 md_parse_option (int c
, const char *arg
)
2821 default_arch_with_ext
= arg
;
2825 riscv_opts
.pic
= false;
2829 riscv_opts
.pic
= true;
2833 if (strcmp (arg
, "ilp32") == 0)
2834 riscv_set_abi (32, FLOAT_ABI_SOFT
, false);
2835 else if (strcmp (arg
, "ilp32e") == 0)
2836 riscv_set_abi (32, FLOAT_ABI_SOFT
, true);
2837 else if (strcmp (arg
, "ilp32f") == 0)
2838 riscv_set_abi (32, FLOAT_ABI_SINGLE
, false);
2839 else if (strcmp (arg
, "ilp32d") == 0)
2840 riscv_set_abi (32, FLOAT_ABI_DOUBLE
, false);
2841 else if (strcmp (arg
, "ilp32q") == 0)
2842 riscv_set_abi (32, FLOAT_ABI_QUAD
, false);
2843 else if (strcmp (arg
, "lp64") == 0)
2844 riscv_set_abi (64, FLOAT_ABI_SOFT
, false);
2845 else if (strcmp (arg
, "lp64f") == 0)
2846 riscv_set_abi (64, FLOAT_ABI_SINGLE
, false);
2847 else if (strcmp (arg
, "lp64d") == 0)
2848 riscv_set_abi (64, FLOAT_ABI_DOUBLE
, false);
2849 else if (strcmp (arg
, "lp64q") == 0)
2850 riscv_set_abi (64, FLOAT_ABI_QUAD
, false);
2853 explicit_mabi
= true;
2857 riscv_opts
.relax
= true;
2860 case OPTION_NO_RELAX
:
2861 riscv_opts
.relax
= false;
2864 case OPTION_ARCH_ATTR
:
2865 riscv_opts
.arch_attr
= true;
2868 case OPTION_NO_ARCH_ATTR
:
2869 riscv_opts
.arch_attr
= false;
2872 case OPTION_CSR_CHECK
:
2873 riscv_opts
.csr_check
= true;
2876 case OPTION_NO_CSR_CHECK
:
2877 riscv_opts
.csr_check
= false;
2880 case OPTION_MISA_SPEC
:
2881 return riscv_set_default_isa_spec (arg
);
2883 case OPTION_MPRIV_SPEC
:
2884 return riscv_set_default_priv_spec (arg
);
2886 case OPTION_BIG_ENDIAN
:
2887 target_big_endian
= 1;
2890 case OPTION_LITTLE_ENDIAN
:
2891 target_big_endian
= 0;
2902 riscv_after_parse_args (void)
2904 /* The --with-arch is optional for now, so we still need to set the xlen
2905 according to the default_arch, which is set by the --target. */
2908 if (strcmp (default_arch
, "riscv32") == 0)
2910 else if (strcmp (default_arch
, "riscv64") == 0)
2913 as_bad ("unknown default architecture `%s'", default_arch
);
2915 if (default_arch_with_ext
== NULL
)
2916 default_arch_with_ext
= xlen
== 64 ? "rv64g" : "rv32g";
2918 /* Initialize the hash table for extensions with default version. */
2919 ext_version_hash
= init_ext_version_hash ();
2921 /* Set default specs. */
2922 if (default_isa_spec
== ISA_SPEC_CLASS_NONE
)
2923 riscv_set_default_isa_spec (DEFAULT_RISCV_ISA_SPEC
);
2924 if (default_priv_spec
== PRIV_SPEC_CLASS_NONE
)
2925 riscv_set_default_priv_spec (DEFAULT_RISCV_PRIV_SPEC
);
2927 riscv_set_arch (default_arch_with_ext
);
2929 /* Add the RVC extension, regardless of -march, to support .option rvc. */
2930 riscv_set_rvc (false);
2931 if (riscv_subset_supports ("c"))
2932 riscv_set_rvc (true);
2934 /* Enable RVE if specified by the -march option. */
2935 riscv_set_rve (false);
2936 if (riscv_subset_supports ("e"))
2937 riscv_set_rve (true);
2939 /* If the CIE to be produced has not been overridden on the command line,
2940 then produce version 3 by default. This allows us to use the full
2941 range of registers in a .cfi_return_column directive. */
2942 if (flag_dwarf_cie_version
== -1)
2943 flag_dwarf_cie_version
= 3;
2947 md_pcrel_from (fixS
*fixP
)
2949 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2952 /* Apply a fixup to the object file. */
2955 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
2957 unsigned int subtype
;
2958 bfd_byte
*buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
2959 bool relaxable
= false;
2963 /* Remember value for tc_gen_reloc. */
2964 fixP
->fx_addnumber
= *valP
;
2966 switch (fixP
->fx_r_type
)
2968 case BFD_RELOC_RISCV_HI20
:
2969 case BFD_RELOC_RISCV_LO12_I
:
2970 case BFD_RELOC_RISCV_LO12_S
:
2971 bfd_putl32 (riscv_apply_const_reloc (fixP
->fx_r_type
, *valP
)
2972 | bfd_getl32 (buf
), buf
);
2973 if (fixP
->fx_addsy
== NULL
)
2974 fixP
->fx_done
= true;
2978 case BFD_RELOC_RISCV_GOT_HI20
:
2979 case BFD_RELOC_RISCV_ADD8
:
2980 case BFD_RELOC_RISCV_ADD16
:
2981 case BFD_RELOC_RISCV_ADD32
:
2982 case BFD_RELOC_RISCV_ADD64
:
2983 case BFD_RELOC_RISCV_SUB6
:
2984 case BFD_RELOC_RISCV_SUB8
:
2985 case BFD_RELOC_RISCV_SUB16
:
2986 case BFD_RELOC_RISCV_SUB32
:
2987 case BFD_RELOC_RISCV_SUB64
:
2988 case BFD_RELOC_RISCV_RELAX
:
2991 case BFD_RELOC_RISCV_TPREL_HI20
:
2992 case BFD_RELOC_RISCV_TPREL_LO12_I
:
2993 case BFD_RELOC_RISCV_TPREL_LO12_S
:
2994 case BFD_RELOC_RISCV_TPREL_ADD
:
2998 case BFD_RELOC_RISCV_TLS_GOT_HI20
:
2999 case BFD_RELOC_RISCV_TLS_GD_HI20
:
3000 case BFD_RELOC_RISCV_TLS_DTPREL32
:
3001 case BFD_RELOC_RISCV_TLS_DTPREL64
:
3002 if (fixP
->fx_addsy
!= NULL
)
3003 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
3005 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3006 _("TLS relocation against a constant"));
3010 /* Use pc-relative relocation for FDE initial location.
3011 The symbol address in .eh_frame may be adjusted in
3012 _bfd_elf_discard_section_eh_frame, and the content of
3013 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
3014 Therefore, we cannot insert a relocation whose addend symbol is
3015 in .eh_frame. Othrewise, the value may be adjusted twice. */
3016 if (fixP
->fx_addsy
&& fixP
->fx_subsy
3017 && (sub_segment
= S_GET_SEGMENT (fixP
->fx_subsy
))
3018 && strcmp (sub_segment
->name
, ".eh_frame") == 0
3019 && S_GET_VALUE (fixP
->fx_subsy
)
3020 == fixP
->fx_frag
->fr_address
+ fixP
->fx_where
)
3022 fixP
->fx_r_type
= BFD_RELOC_RISCV_32_PCREL
;
3023 fixP
->fx_subsy
= NULL
;
3030 case BFD_RELOC_RISCV_CFA
:
3031 if (fixP
->fx_addsy
&& fixP
->fx_subsy
)
3033 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
3034 fixP
->fx_next
->fx_addsy
= fixP
->fx_subsy
;
3035 fixP
->fx_next
->fx_subsy
= NULL
;
3036 fixP
->fx_next
->fx_offset
= 0;
3037 fixP
->fx_subsy
= NULL
;
3039 switch (fixP
->fx_r_type
)
3042 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD64
;
3043 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB64
;
3047 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD32
;
3048 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
3052 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD16
;
3053 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
3057 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD8
;
3058 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
3061 case BFD_RELOC_RISCV_CFA
:
3062 /* Load the byte to get the subtype. */
3063 subtype
= bfd_get_8 (NULL
, &((fragS
*) (fixP
->fx_frag
->fr_opcode
))->fr_literal
[fixP
->fx_where
]);
3064 loc
= fixP
->fx_frag
->fr_fix
- (subtype
& 7);
3067 case DW_CFA_advance_loc1
:
3068 fixP
->fx_where
= loc
+ 1;
3069 fixP
->fx_next
->fx_where
= loc
+ 1;
3070 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET8
;
3071 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
3074 case DW_CFA_advance_loc2
:
3076 fixP
->fx_next
->fx_size
= 2;
3077 fixP
->fx_where
= loc
+ 1;
3078 fixP
->fx_next
->fx_where
= loc
+ 1;
3079 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET16
;
3080 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
3083 case DW_CFA_advance_loc4
:
3085 fixP
->fx_next
->fx_size
= 4;
3086 fixP
->fx_where
= loc
;
3087 fixP
->fx_next
->fx_where
= loc
;
3088 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET32
;
3089 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
3093 if (subtype
< 0x80 && (subtype
& 0x40))
3095 /* DW_CFA_advance_loc */
3096 fixP
->fx_frag
= (fragS
*) fixP
->fx_frag
->fr_opcode
;
3097 fixP
->fx_next
->fx_frag
= fixP
->fx_frag
;
3098 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET6
;
3099 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB6
;
3102 as_fatal (_("internal: bad CFA value #%d"), subtype
);
3108 /* This case is unreachable. */
3115 /* If we are deleting this reloc entry, we must fill in the
3116 value now. This can happen if we have a .word which is not
3117 resolved when it appears but is later defined. */
3118 if (fixP
->fx_addsy
== NULL
)
3120 gas_assert (fixP
->fx_size
<= sizeof (valueT
));
3121 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
3126 case BFD_RELOC_RISCV_JMP
:
3129 /* Fill in a tentative value to improve objdump readability. */
3130 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3131 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3132 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_JTYPE_IMM (delta
), buf
);
3136 case BFD_RELOC_12_PCREL
:
3139 /* Fill in a tentative value to improve objdump readability. */
3140 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3141 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3142 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_BTYPE_IMM (delta
), buf
);
3146 case BFD_RELOC_RISCV_RVC_BRANCH
:
3149 /* Fill in a tentative value to improve objdump readability. */
3150 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3151 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3152 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_CBTYPE_IMM (delta
), buf
);
3156 case BFD_RELOC_RISCV_RVC_JUMP
:
3159 /* Fill in a tentative value to improve objdump readability. */
3160 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3161 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3162 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_CJTYPE_IMM (delta
), buf
);
3166 case BFD_RELOC_RISCV_CALL
:
3167 case BFD_RELOC_RISCV_CALL_PLT
:
3171 case BFD_RELOC_RISCV_PCREL_HI20
:
3172 case BFD_RELOC_RISCV_PCREL_LO12_S
:
3173 case BFD_RELOC_RISCV_PCREL_LO12_I
:
3174 relaxable
= riscv_opts
.relax
;
3177 case BFD_RELOC_RISCV_ALIGN
:
3181 /* We ignore generic BFD relocations we don't know about. */
3182 if (bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
) != NULL
)
3183 as_fatal (_("internal: bad relocation #%d"), fixP
->fx_r_type
);
3186 if (fixP
->fx_subsy
!= NULL
)
3187 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3188 _("unsupported symbol subtraction"));
3190 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
3191 if (relaxable
&& fixP
->fx_tcbit
&& fixP
->fx_addsy
!= NULL
)
3193 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
3194 fixP
->fx_next
->fx_addsy
= fixP
->fx_next
->fx_subsy
= NULL
;
3195 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_RELAX
;
3196 fixP
->fx_next
->fx_size
= 0;
3200 /* Because the value of .cfi_remember_state may changed after relaxation,
3201 we insert a fix to relocate it again in link-time. */
3204 riscv_pre_output_hook (void)
3206 const frchainS
*frch
;
3209 /* Save the current segment info. */
3211 subsegT subseg
= now_subseg
;
3213 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
3214 for (frch
= seg_info (s
)->frchainP
; frch
; frch
= frch
->frch_next
)
3218 for (frag
= frch
->frch_root
; frag
; frag
= frag
->fr_next
)
3220 if (frag
->fr_type
== rs_cfa
)
3223 expressionS
*symval
;
3225 symval
= symbol_get_value_expression (frag
->fr_symbol
);
3226 exp
.X_op
= O_subtract
;
3227 exp
.X_add_symbol
= symval
->X_add_symbol
;
3228 exp
.X_add_number
= 0;
3229 exp
.X_op_symbol
= symval
->X_op_symbol
;
3231 /* We must set the segment before creating a frag after all
3232 frag chains have been chained together. */
3233 subseg_set (s
, frch
->frch_subseg
);
3235 fix_new_exp (frag
, (int) frag
->fr_offset
, 1, &exp
, 0,
3236 BFD_RELOC_RISCV_CFA
);
3241 /* Restore the original segment info. */
3242 subseg_set (seg
, subseg
);
3245 /* This structure is used to hold a stack of .option values. */
3246 struct riscv_option_stack
3248 struct riscv_option_stack
*next
;
3249 struct riscv_set_options options
;
3252 static struct riscv_option_stack
*riscv_opts_stack
;
3254 /* Handle the .option pseudo-op. */
3257 s_riscv_option (int x ATTRIBUTE_UNUSED
)
3259 char *name
= input_line_pointer
, ch
;
3261 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3262 ++input_line_pointer
;
3263 ch
= *input_line_pointer
;
3264 *input_line_pointer
= '\0';
3266 if (strcmp (name
, "rvc") == 0)
3267 riscv_set_rvc (true);
3268 else if (strcmp (name
, "norvc") == 0)
3269 riscv_set_rvc (false);
3270 else if (strcmp (name
, "pic") == 0)
3271 riscv_opts
.pic
= true;
3272 else if (strcmp (name
, "nopic") == 0)
3273 riscv_opts
.pic
= false;
3274 else if (strcmp (name
, "relax") == 0)
3275 riscv_opts
.relax
= true;
3276 else if (strcmp (name
, "norelax") == 0)
3277 riscv_opts
.relax
= false;
3278 else if (strcmp (name
, "csr-check") == 0)
3279 riscv_opts
.csr_check
= true;
3280 else if (strcmp (name
, "no-csr-check") == 0)
3281 riscv_opts
.csr_check
= false;
3282 else if (strcmp (name
, "push") == 0)
3284 struct riscv_option_stack
*s
;
3286 s
= (struct riscv_option_stack
*) xmalloc (sizeof *s
);
3287 s
->next
= riscv_opts_stack
;
3288 s
->options
= riscv_opts
;
3289 riscv_opts_stack
= s
;
3291 else if (strcmp (name
, "pop") == 0)
3293 struct riscv_option_stack
*s
;
3295 s
= riscv_opts_stack
;
3297 as_bad (_(".option pop with no .option push"));
3300 riscv_opts
= s
->options
;
3301 riscv_opts_stack
= s
->next
;
3307 as_warn (_("unrecognized .option directive: %s\n"), name
);
3309 *input_line_pointer
= ch
;
3310 demand_empty_rest_of_line ();
3313 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
3314 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
3315 use in DWARF debug information. */
3318 s_dtprel (int bytes
)
3325 if (ex
.X_op
!= O_symbol
)
3327 as_bad (_("unsupported use of %s"), (bytes
== 8
3330 ignore_rest_of_line ();
3333 p
= frag_more (bytes
);
3334 md_number_to_chars (p
, 0, bytes
);
3335 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, false,
3337 ? BFD_RELOC_RISCV_TLS_DTPREL64
3338 : BFD_RELOC_RISCV_TLS_DTPREL32
));
3340 demand_empty_rest_of_line ();
3343 /* Handle the .bss pseudo-op. */
3346 s_bss (int ignore ATTRIBUTE_UNUSED
)
3348 subseg_set (bss_section
, 0);
3349 demand_empty_rest_of_line ();
3353 riscv_make_nops (char *buf
, bfd_vma bytes
)
3357 /* RISC-V instructions cannot begin or end on odd addresses, so this case
3358 means we are not within a valid instruction sequence. It is thus safe
3359 to use a zero byte, even though that is not a valid instruction. */
3363 /* Use at most one 2-byte NOP. */
3364 if ((bytes
- i
) % 4 == 2)
3366 number_to_chars_littleendian (buf
+ i
, RVC_NOP
, 2);
3370 /* Fill the remainder with 4-byte NOPs. */
3371 for ( ; i
< bytes
; i
+= 4)
3372 number_to_chars_littleendian (buf
+ i
, RISCV_NOP
, 4);
3375 /* Called from md_do_align. Used to create an alignment frag in a
3376 code section by emitting a worst-case NOP sequence that the linker
3377 will later relax to the correct number of NOPs. We can't compute
3378 the correct alignment now because of other linker relaxations. */
3381 riscv_frag_align_code (int n
)
3383 bfd_vma bytes
= (bfd_vma
) 1 << n
;
3384 bfd_vma insn_alignment
= riscv_opts
.rvc
? 2 : 4;
3385 bfd_vma worst_case_bytes
= bytes
- insn_alignment
;
3389 /* If we are moving to a smaller alignment than the instruction size, then no
3390 alignment is required. */
3391 if (bytes
<= insn_alignment
)
3394 /* When not relaxing, riscv_handle_align handles code alignment. */
3395 if (!riscv_opts
.relax
)
3398 nops
= frag_more (worst_case_bytes
);
3400 ex
.X_op
= O_constant
;
3401 ex
.X_add_number
= worst_case_bytes
;
3403 riscv_make_nops (nops
, worst_case_bytes
);
3405 fix_new_exp (frag_now
, nops
- frag_now
->fr_literal
, 0,
3406 &ex
, false, BFD_RELOC_RISCV_ALIGN
);
3411 /* Implement HANDLE_ALIGN. */
3414 riscv_handle_align (fragS
*fragP
)
3416 switch (fragP
->fr_type
)
3419 /* When relaxing, riscv_frag_align_code handles code alignment. */
3420 if (!riscv_opts
.relax
)
3422 bfd_signed_vma bytes
= (fragP
->fr_next
->fr_address
3423 - fragP
->fr_address
- fragP
->fr_fix
);
3424 /* We have 4 byte uncompressed nops. */
3425 bfd_signed_vma size
= 4;
3426 bfd_signed_vma excess
= bytes
% size
;
3427 char *p
= fragP
->fr_literal
+ fragP
->fr_fix
;
3432 /* Insert zeros or compressed nops to get 4 byte alignment. */
3435 riscv_make_nops (p
, excess
);
3436 fragP
->fr_fix
+= excess
;
3440 /* Insert variable number of 4 byte uncompressed nops. */
3441 riscv_make_nops (p
, size
);
3442 fragP
->fr_var
= size
;
3452 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
3454 return (fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, false));
3457 /* Translate internal representation of relocation info to BFD target
3461 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
3463 arelent
*reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3465 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3466 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3467 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3468 reloc
->addend
= fixp
->fx_addnumber
;
3470 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
3471 if (reloc
->howto
== NULL
)
3473 if ((fixp
->fx_r_type
== BFD_RELOC_16
|| fixp
->fx_r_type
== BFD_RELOC_8
)
3474 && fixp
->fx_addsy
!= NULL
&& fixp
->fx_subsy
!= NULL
)
3476 /* We don't have R_RISCV_8/16, but for this special case,
3477 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
3481 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3482 _("cannot represent %s relocation in object file"),
3483 bfd_get_reloc_code_name (fixp
->fx_r_type
));
3491 riscv_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
3493 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
3495 offsetT old_var
= fragp
->fr_var
;
3496 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, true);
3497 return fragp
->fr_var
- old_var
;
3503 /* Expand far branches to multi-instruction sequences. */
3506 md_convert_frag_branch (fragS
*fragp
)
3514 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
3516 exp
.X_op
= O_symbol
;
3517 exp
.X_add_symbol
= fragp
->fr_symbol
;
3518 exp
.X_add_number
= fragp
->fr_offset
;
3520 gas_assert (fragp
->fr_var
== RELAX_BRANCH_LENGTH (fragp
->fr_subtype
));
3522 if (RELAX_BRANCH_RVC (fragp
->fr_subtype
))
3524 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
3528 /* Expand the RVC branch into a RISC-V one. */
3529 insn
= bfd_getl16 (buf
);
3530 rs1
= 8 + ((insn
>> OP_SH_CRS1S
) & OP_MASK_CRS1S
);
3531 if ((insn
& MASK_C_J
) == MATCH_C_J
)
3533 else if ((insn
& MASK_C_JAL
) == MATCH_C_JAL
)
3534 insn
= MATCH_JAL
| (X_RA
<< OP_SH_RD
);
3535 else if ((insn
& MASK_C_BEQZ
) == MATCH_C_BEQZ
)
3536 insn
= MATCH_BEQ
| (rs1
<< OP_SH_RS1
);
3537 else if ((insn
& MASK_C_BNEZ
) == MATCH_C_BNEZ
)
3538 insn
= MATCH_BNE
| (rs1
<< OP_SH_RS1
);
3541 bfd_putl32 (insn
, buf
);
3545 /* Invert the branch condition. Branch over the jump. */
3546 insn
= bfd_getl16 (buf
);
3547 insn
^= MATCH_C_BEQZ
^ MATCH_C_BNEZ
;
3548 insn
|= ENCODE_CBTYPE_IMM (6);
3549 bfd_putl16 (insn
, buf
);
3554 /* Just keep the RVC branch. */
3555 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
3556 ? BFD_RELOC_RISCV_RVC_JUMP
: BFD_RELOC_RISCV_RVC_BRANCH
;
3557 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3558 2, &exp
, false, reloc
);
3567 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
3570 gas_assert (!RELAX_BRANCH_UNCOND (fragp
->fr_subtype
));
3572 /* Invert the branch condition. Branch over the jump. */
3573 insn
= bfd_getl32 (buf
);
3574 insn
^= MATCH_BEQ
^ MATCH_BNE
;
3575 insn
|= ENCODE_BTYPE_IMM (8);
3576 bfd_putl32 (insn
, buf
);
3580 /* Jump to the target. */
3581 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3582 4, &exp
, false, BFD_RELOC_RISCV_JMP
);
3583 bfd_putl32 (MATCH_JAL
, buf
);
3588 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
3589 ? BFD_RELOC_RISCV_JMP
: BFD_RELOC_12_PCREL
;
3590 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3591 4, &exp
, false, reloc
);
3600 fixp
->fx_file
= fragp
->fr_file
;
3601 fixp
->fx_line
= fragp
->fr_line
;
3603 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
3604 + fragp
->fr_fix
+ fragp
->fr_var
);
3606 fragp
->fr_fix
+= fragp
->fr_var
;
3609 /* Relax a machine dependent frag. This returns the amount by which
3610 the current size of the frag should change. */
3613 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec ATTRIBUTE_UNUSED
,
3616 gas_assert (RELAX_BRANCH_P (fragp
->fr_subtype
));
3617 md_convert_frag_branch (fragp
);
3621 md_show_usage (FILE *stream
)
3623 fprintf (stream
, _("\
3625 -fpic generate position-independent code\n\
3626 -fno-pic don't generate position-independent code (default)\n\
3627 -march=ISA set the RISC-V architecture\n\
3628 -misa-spec=ISAspec set the RISC-V ISA spec (2.2, 20190608, 20191213)\n\
3629 -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9, 1.9.1, 1.10, 1.11)\n\
3630 -mabi=ABI set the RISC-V ABI\n\
3631 -mrelax enable relax (default)\n\
3632 -mno-relax disable relax\n\
3633 -march-attr generate RISC-V arch attribute\n\
3634 -mno-arch-attr don't generate RISC-V arch attribute\n\
3638 /* Standard calling conventions leave the CFA at SP on entry. */
3641 riscv_cfi_frame_initial_instructions (void)
3643 cfi_add_CFA_def_cfa_register (X_SP
);
3647 tc_riscv_regname_to_dw2regnum (char *regname
)
3651 if ((reg
= reg_lookup_internal (regname
, RCLASS_GPR
)) >= 0)
3654 if ((reg
= reg_lookup_internal (regname
, RCLASS_FPR
)) >= 0)
3657 /* CSRs are numbered 4096 -> 8191. */
3658 if ((reg
= reg_lookup_internal (regname
, RCLASS_CSR
)) >= 0)
3661 as_bad (_("unknown register `%s'"), regname
);
3666 riscv_elf_final_processing (void)
3668 riscv_set_abi_by_arch ();
3669 elf_elfheader (stdoutput
)->e_flags
|= elf_flags
;
3672 /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
3673 since these directives break relaxation when used with symbol deltas. */
3676 s_riscv_leb128 (int sign
)
3679 char *save_in
= input_line_pointer
;
3682 if (exp
.X_op
!= O_constant
)
3683 as_bad (_("non-constant .%cleb128 is not supported"), sign
? 's' : 'u');
3684 demand_empty_rest_of_line ();
3686 input_line_pointer
= save_in
;
3687 return s_leb128 (sign
);
3690 /* Parse the .insn directive. */
3693 s_riscv_insn (int x ATTRIBUTE_UNUSED
)
3695 char *str
= input_line_pointer
;
3696 struct riscv_cl_insn insn
;
3697 expressionS imm_expr
;
3698 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
3701 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3702 ++input_line_pointer
;
3704 save_c
= *input_line_pointer
;
3705 *input_line_pointer
= '\0';
3707 const char *error
= riscv_ip (str
, &insn
, &imm_expr
,
3708 &imm_reloc
, insn_type_hash
);
3712 as_bad ("%s `%s'", error
, str
);
3716 gas_assert (insn
.insn_mo
->pinfo
!= INSN_MACRO
);
3717 append_insn (&insn
, &imm_expr
, imm_reloc
);
3720 *input_line_pointer
= save_c
;
3721 demand_empty_rest_of_line ();
3724 /* Update architecture and privileged elf attributes. If we don't set
3725 them, then try to output the default ones. */
3728 riscv_write_out_attrs (void)
3730 const char *arch_str
, *priv_str
, *p
;
3731 /* versions[0]: major version.
3732 versions[1]: minor version.
3733 versions[2]: revision version. */
3734 unsigned versions
[3] = {0}, number
= 0;
3737 /* Re-write architecture elf attribute. */
3738 arch_str
= riscv_arch_str (xlen
, &riscv_subsets
);
3739 bfd_elf_add_proc_attr_string (stdoutput
, Tag_RISCV_arch
, arch_str
);
3740 xfree ((void *) arch_str
);
3742 /* For the file without any instruction, we don't set the default_priv_spec
3743 according to the privileged elf attributes since the md_assemble isn't
3746 && !riscv_set_default_priv_spec (NULL
))
3749 /* If we already have set privileged elf attributes, then no need to do
3750 anything. Otherwise, don't generate or update them when no CSR and
3751 privileged instructions are used. */
3752 if (!explicit_priv_attr
)
3755 RISCV_GET_PRIV_SPEC_NAME (priv_str
, default_priv_spec
);
3757 for (i
= 0; *p
; ++p
)
3759 if (*p
== '.' && i
< 3)
3761 versions
[i
++] = number
;
3764 else if (ISDIGIT (*p
))
3765 number
= (number
* 10) + (*p
- '0');
3768 as_bad (_("internal: bad RISC-V privileged spec (%s)"), priv_str
);
3772 versions
[i
] = number
;
3774 /* Re-write privileged elf attributes. */
3775 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec
, versions
[0]);
3776 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec_minor
, versions
[1]);
3777 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec_revision
, versions
[2]);
3780 /* Add the default contents for the .riscv.attributes section. */
3783 riscv_set_public_attributes (void)
3785 if (riscv_opts
.arch_attr
|| explicit_attr
)
3786 riscv_write_out_attrs ();
3789 /* Called after all assembly has been done. */
3794 riscv_set_public_attributes ();
3797 /* Given a symbolic attribute NAME, return the proper integer value.
3798 Returns -1 if the attribute is not known. */
3801 riscv_convert_symbolic_attribute (const char *name
)
3810 /* When you modify this table you should
3811 also modify the list in doc/c-riscv.texi. */
3812 #define T(tag) {#tag, Tag_RISCV_##tag}, {"Tag_RISCV_" #tag, Tag_RISCV_##tag}
3816 T(priv_spec_revision
),
3817 T(unaligned_access
),
3826 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
3827 if (strcmp (name
, attribute_table
[i
].name
) == 0)
3828 return attribute_table
[i
].tag
;
3833 /* Parse a .attribute directive. */
3836 s_riscv_attribute (int ignored ATTRIBUTE_UNUSED
)
3838 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
3840 obj_attribute
*attr
;
3842 explicit_attr
= true;
3845 case Tag_RISCV_arch
:
3847 attr
= elf_known_obj_attributes_proc (stdoutput
);
3848 if (!start_assemble
)
3849 riscv_set_arch (attr
[Tag_RISCV_arch
].s
);
3851 as_fatal (_("architecture elf attributes must set before "
3852 "any instructions"));
3854 if (old_xlen
!= xlen
)
3856 /* We must re-init bfd again if xlen is changed. */
3857 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
3858 bfd_find_target (riscv_target_format (), stdoutput
);
3860 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
3861 as_warn (_("could not set architecture and machine"));
3865 case Tag_RISCV_priv_spec
:
3866 case Tag_RISCV_priv_spec_minor
:
3867 case Tag_RISCV_priv_spec_revision
:
3869 as_fatal (_("privileged elf attributes must set before "
3870 "any instructions"));
3878 /* RISC-V pseudo-ops table. */
3879 static const pseudo_typeS riscv_pseudo_table
[] =
3881 {"option", s_riscv_option
, 0},
3885 {"dtprelword", s_dtprel
, 4},
3886 {"dtpreldword", s_dtprel
, 8},
3888 {"uleb128", s_riscv_leb128
, 0},
3889 {"sleb128", s_riscv_leb128
, 1},
3890 {"insn", s_riscv_insn
, 0},
3891 {"attribute", s_riscv_attribute
, 0},
3897 riscv_pop_insert (void)
3899 extern void pop_insert (const pseudo_typeS
*);
3901 pop_insert (riscv_pseudo_table
);