1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright (C) 1989-2016 Free Software Foundation, Inc.
3 This file is part of GAS, the GNU Assembler.
5 GAS is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 3, or (at your option)
10 GAS is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public
16 License along with GAS; see the file COPYING. If not, write
17 to the Free Software Foundation, 51 Franklin Street - Fifth Floor,
18 Boston, MA 02110-1301, USA. */
21 #include "safe-ctype.h"
24 #include "opcode/sparc.h"
25 #include "dw2gencfi.h"
28 #include "elf/sparc.h"
29 #include "dwarf2dbg.h"
32 /* Some ancient Sun C compilers would not take such hex constants as
33 unsigned, and would end up sign-extending them to form an offsetT,
34 so use these constants instead. */
35 #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1)
36 #define U0x80000000 ((((unsigned long) 1 << 16) << 15))
38 static int sparc_ip (char *, const struct sparc_opcode
**);
39 static int parse_keyword_arg (int (*) (const char *), char **, int *);
40 static int parse_const_expr_arg (char **, int *);
41 static int get_expression (char *);
43 /* Default architecture. */
44 /* ??? The default value should be V8, but sparclite support was added
45 by making it the default. GCC now passes -Asparclite, so maybe sometime in
46 the future we can set this to V8. */
48 #define DEFAULT_ARCH "sparclite"
50 static const char *default_arch
= DEFAULT_ARCH
;
52 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
54 static int default_init_p
;
56 /* Current architecture. We don't bump up unless necessary. */
57 static enum sparc_opcode_arch_val current_architecture
= SPARC_OPCODE_ARCH_V6
;
59 /* The maximum architecture level we can bump up to.
60 In a 32 bit environment, don't allow bumping up to v9 by default.
61 The native assembler works this way. The user is required to pass
62 an explicit argument before we'll create v9 object files. However, if
63 we don't see any v9 insns, a v8plus object file is not created. */
64 static enum sparc_opcode_arch_val max_architecture
;
66 /* Either 32 or 64, selects file format. */
67 static int sparc_arch_size
;
68 /* Initial (default) value, recorded separately in case a user option
69 changes the value before md_show_usage is called. */
70 static int default_arch_size
;
73 /* The currently selected v9 memory model. Currently only used for
75 static enum { MM_TSO
, MM_PSO
, MM_RMO
} sparc_memory_model
= MM_RMO
;
78 /* Bitmask of instruction types seen so far, used to populate the
79 GNU attributes section with hwcap information. */
80 static bfd_uint64_t hwcap_seen
;
84 static bfd_uint64_t hwcap_allowed
;
86 static int architecture_requested
;
87 static int warn_on_bump
;
89 /* If warn_on_bump and the needed architecture is higher than this
90 architecture, issue a warning. */
91 static enum sparc_opcode_arch_val warn_after_architecture
;
93 /* Non-zero if as should generate error if an undeclared g[23] register
94 has been used in -64. */
95 static int no_undeclared_regs
;
97 /* Non-zero if we should try to relax jumps and calls. */
98 static int sparc_relax
;
100 /* Non-zero if we are generating PIC code. */
103 /* Non-zero if we should give an error when misaligned data is seen. */
104 static int enforce_aligned_data
;
106 extern int target_big_endian
;
108 static int target_little_endian_data
;
110 /* Symbols for global registers on v9. */
111 static symbolS
*globals
[8];
113 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
114 int sparc_cie_data_alignment
;
116 /* V9 and 86x have big and little endian data, but instructions are always big
117 endian. The sparclet has bi-endian support but both data and insns have
118 the same endianness. Global `target_big_endian' is used for data.
119 The following macro is used for instructions. */
120 #ifndef INSN_BIG_ENDIAN
121 #define INSN_BIG_ENDIAN (target_big_endian \
122 || default_arch_type == sparc86x \
123 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
126 /* Handle of the OPCODE hash table. */
127 static struct hash_control
*op_hash
;
129 static void s_data1 (void);
130 static void s_seg (int);
131 static void s_proc (int);
132 static void s_reserve (int);
133 static void s_common (int);
134 static void s_empty (int);
135 static void s_uacons (int);
136 static void s_ncons (int);
138 static void s_register (int);
141 const pseudo_typeS md_pseudo_table
[] =
143 {"align", s_align_bytes
, 0}, /* Defaulting is invalid (0). */
144 {"common", s_common
, 0},
145 {"empty", s_empty
, 0},
146 {"global", s_globl
, 0},
148 {"nword", s_ncons
, 0},
149 {"optim", s_ignore
, 0},
151 {"reserve", s_reserve
, 0},
153 {"skip", s_space
, 0},
156 {"uahalf", s_uacons
, 2},
157 {"uaword", s_uacons
, 4},
158 {"uaxword", s_uacons
, 8},
160 /* These are specific to sparc/svr4. */
161 {"2byte", s_uacons
, 2},
162 {"4byte", s_uacons
, 4},
163 {"8byte", s_uacons
, 8},
164 {"register", s_register
, 0},
169 /* This array holds the chars that always start a comment. If the
170 pre-processor is disabled, these aren't very useful. */
171 const char comment_chars
[] = "!"; /* JF removed '|' from
174 /* This array holds the chars that only start a comment at the beginning of
175 a line. If the line seems to have the form '# 123 filename'
176 .line and .file directives will appear in the pre-processed output. */
177 /* Note that input_file.c hand checks for '#' at the beginning of the
178 first line of the input file. This is because the compiler outputs
179 #NO_APP at the beginning of its output. */
180 /* Also note that comments started like this one will always
181 work if '/' isn't otherwise defined. */
182 const char line_comment_chars
[] = "#";
184 const char line_separator_chars
[] = ";";
186 /* Chars that can be used to separate mant from exp in floating point
188 const char EXP_CHARS
[] = "eE";
190 /* Chars that mean this number is a floating point constant.
193 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
195 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
196 changed in read.c. Ideally it shouldn't have to know about it at all,
197 but nothing is ideal around here. */
199 #define isoctal(c) ((unsigned) ((c) - '0') < 8)
204 unsigned long opcode
;
205 struct nlist
*nlistp
;
209 bfd_reloc_code_real_type reloc
;
212 struct sparc_it the_insn
, set_insn
;
214 static void output_insn (const struct sparc_opcode
*, struct sparc_it
*);
216 /* Table of arguments to -A.
217 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
218 for this use. That table is for opcodes only. This table is for opcodes
221 enum sparc_arch_types
{v6
, v7
, v8
, leon
, sparclet
, sparclite
, sparc86x
, v8plus
,
222 v8plusa
, v9
, v9a
, v9b
, v9_64
};
224 /* Hardware capability sets, used to keep sparc_arch_table easy to
226 #define HWS_V8 HWCAP_MUL32 | HWCAP_DIV32 | HWCAP_FSMULD
227 #define HWS_V9 HWS_V8 | HWCAP_POPC
228 #define HWS_VA HWS_V9 | HWCAP_VIS
229 #define HWS_VB HWS_VA | HWCAP_VIS2
230 #define HWS_VC HWS_VB | HWCAP_ASI_BLK_INIT
231 #define HWS_VD HWS_VC | HWCAP_FMAF | HWCAP_VIS3 | HWCAP_HPC
232 #define HWS_VE HWS_VD \
233 | HWCAP_AES | HWCAP_DES | HWCAP_KASUMI | HWCAP_CAMELLIA \
234 | HWCAP_MD5 | HWCAP_SHA1 | HWCAP_SHA256 |HWCAP_SHA512 | HWCAP_MPMUL \
235 | HWCAP_MONT | HWCAP_CRC32C | HWCAP_CBCOND | HWCAP_PAUSE
236 #define HWS_VV HWS_VE | HWCAP_FJFMAU | HWCAP_IMA
237 #define HWS_VM HWS_VV
240 HWCAP2_VIS3B | HWCAP2_ADP | HWCAP2_SPARC5 | HWCAP2_MWAIT \
241 | HWCAP2_XMPMUL | HWCAP2_XMONT
243 static struct sparc_arch
{
245 const char *opcode_arch
;
246 enum sparc_arch_types arch_type
;
247 /* Default word size, as specified during configuration.
248 A value of zero means can't be used to specify default architecture. */
249 int default_arch_size
;
250 /* Allowable arg to -A? */
254 } sparc_arch_table
[] = {
255 { "v6", "v6", v6
, 0, 1, 0, 0 },
256 { "v7", "v7", v7
, 0, 1, 0, 0 },
257 { "v8", "v8", v8
, 32, 1, HWS_V8
, 0 },
258 { "v8a", "v8", v8
, 32, 1, HWS_V8
, 0 },
259 { "sparc", "v9", v9
, 0, 1, HWCAP_V8PLUS
|HWS_V9
, 0 },
260 { "sparcvis", "v9a", v9
, 0, 1, HWS_VA
, 0 },
261 { "sparcvis2", "v9b", v9
, 0, 1, HWS_VB
, 0 },
262 { "sparcfmaf", "v9b", v9
, 0, 1, HWS_VB
|HWCAP_FMAF
, 0 },
263 { "sparcima", "v9b", v9
, 0, 1, HWS_VB
|HWCAP_FMAF
|HWCAP_IMA
, 0 },
264 { "sparcvis3", "v9b", v9
, 0, 1, HWS_VB
|HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
, 0 },
265 { "sparcvis3r", "v9b", v9
, 0, 1, HWS_VB
|HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
|HWCAP_FJFMAU
, 0 },
267 { "sparc4", "v9v", v9
, 0, 1, HWS_VV
, 0 },
268 { "sparc5", "v9m", v9
, 0, 1, HWS_VM
, HWS2_VM
},
270 { "leon", "leon", leon
, 32, 1, HWS_V8
, 0 },
271 { "sparclet", "sparclet", sparclet
, 32, 1, HWS_V8
, 0 },
272 { "sparclite", "sparclite", sparclite
, 32, 1, HWS_V8
, 0 },
273 { "sparc86x", "sparclite", sparc86x
, 32, 1, HWS_V8
, 0 },
275 { "v8plus", "v9", v9
, 0, 1, HWCAP_V8PLUS
|HWS_V9
, 0 },
276 { "v8plusa", "v9a", v9
, 0, 1, HWCAP_V8PLUS
|HWS_VA
, 0 },
277 { "v8plusb", "v9b", v9
, 0, 1, HWCAP_V8PLUS
|HWS_VB
, 0 },
278 { "v8plusc", "v9c", v9
, 0, 1, HWCAP_V8PLUS
|HWS_VC
, 0 },
279 { "v8plusd", "v9d", v9
, 0, 1, HWCAP_V8PLUS
|HWS_VD
, 0 },
280 { "v8pluse", "v9e", v9
, 0, 1, HWCAP_V8PLUS
|HWS_VE
, 0 },
281 { "v8plusv", "v9v", v9
, 0, 1, HWCAP_V8PLUS
|HWS_VV
, 0 },
282 { "v8plusm", "v9m", v9
, 0, 1, HWCAP_V8PLUS
|HWS_VM
, 0 },
284 { "v9", "v9", v9
, 0, 1, HWS_V9
, 0 },
285 { "v9a", "v9a", v9
, 0, 1, HWS_VA
, 0 },
286 { "v9b", "v9b", v9
, 0, 1, HWS_VB
, 0 },
287 { "v9c", "v9c", v9
, 0, 1, HWS_VC
, 0 },
288 { "v9d", "v9d", v9
, 0, 1, HWS_VD
, 0 },
289 { "v9e", "v9e", v9
, 0, 1, HWS_VE
, 0 },
290 { "v9v", "v9v", v9
, 0, 1, HWS_VV
, 0 },
291 { "v9m", "v9m", v9
, 0, 1, HWS_VM
, HWS2_VM
},
293 /* This exists to allow configure.tgt to pass one
294 value to specify both the default machine and default word size. */
295 { "v9-64", "v9", v9
, 64, 0, HWS_V9
, 0 },
296 { NULL
, NULL
, v8
, 0, 0, 0, 0 }
299 /* Variant of default_arch */
300 static enum sparc_arch_types default_arch_type
;
302 static struct sparc_arch
*
303 lookup_arch (const char *name
)
305 struct sparc_arch
*sa
;
307 for (sa
= &sparc_arch_table
[0]; sa
->name
!= NULL
; sa
++)
308 if (strcmp (sa
->name
, name
) == 0)
310 if (sa
->name
== NULL
)
315 /* Initialize the default opcode arch and word size from the default
316 architecture name. */
319 init_default_arch (void)
321 struct sparc_arch
*sa
= lookup_arch (default_arch
);
324 || sa
->default_arch_size
== 0)
325 as_fatal (_("Invalid default architecture, broken assembler."));
327 max_architecture
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
328 if (max_architecture
== SPARC_OPCODE_ARCH_BAD
)
329 as_fatal (_("Bad opcode table, broken assembler."));
330 default_arch_size
= sparc_arch_size
= sa
->default_arch_size
;
332 default_arch_type
= sa
->arch_type
;
335 /* Called by TARGET_FORMAT. */
338 sparc_target_format (void)
340 /* We don't get a chance to initialize anything before we're called,
341 so handle that now. */
342 if (! default_init_p
)
343 init_default_arch ();
347 return "a.out-sparc-netbsd";
350 if (target_big_endian
)
351 return "a.out-sunos-big";
352 else if (default_arch_type
== sparc86x
&& target_little_endian_data
)
353 return "a.out-sunos-big";
355 return "a.out-sparc-little";
357 return "a.out-sunos-big";
368 return "coff-sparc-lynx";
375 return "elf32-sparc-vxworks";
379 return sparc_arch_size
== 64 ? ELF64_TARGET_FORMAT
: ELF_TARGET_FORMAT
;
386 * Invocation line includes a switch not recognized by the base assembler.
387 * See if it's a processor-specific option. These are:
390 * Warn on architecture bumps. See also -A.
392 * -Av6, -Av7, -Av8, -Aleon, -Asparclite, -Asparclet
393 * Standard 32 bit architectures.
395 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
396 * This used to only mean 64 bits, but properly specifying it
397 * complicated gcc's ASM_SPECs, so now opcode selection is
398 * specified orthogonally to word size (except when specifying
399 * the default, but that is an internal implementation detail).
400 * -Av8plus, -Av8plusa, -Av8plusb
401 * Same as -Av9{,a,b}.
402 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
403 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's
405 * -xarch=v9, -xarch=v9a, -xarch=v9b
406 * Same as -Av9{,a,b} -64, for compatibility with Sun's
409 * Select the architecture and possibly the file format.
410 * Instructions or features not supported by the selected
411 * architecture cause fatal errors.
413 * The default is to start at v6, and bump the architecture up
414 * whenever an instruction is seen at a higher level. In 32 bit
415 * environments, v9 is not bumped up to, the user must pass
418 * If -bump is specified, a warning is printing when bumping to
421 * If an architecture is specified, all instructions must match
422 * that architecture. Any higher level instructions are flagged
423 * as errors. Note that in the 32 bit environment specifying
424 * -Av8plus does not automatically create a v8plus object file, a
425 * v9 insn must be seen.
427 * If both an architecture and -bump are specified, the
428 * architecture starts at the specified level, but bumps are
429 * warnings. Note that we can't set `current_architecture' to
430 * the requested level in this case: in the 32 bit environment,
431 * we still must avoid creating v8plus object files unless v9
435 * Bumping between incompatible architectures is always an
436 * error. For example, from sparclite to v9.
440 const char *md_shortopts
= "A:K:VQ:sq";
443 const char *md_shortopts
= "A:k";
445 const char *md_shortopts
= "A:";
448 struct option md_longopts
[] = {
449 #define OPTION_BUMP (OPTION_MD_BASE)
450 {"bump", no_argument
, NULL
, OPTION_BUMP
},
451 #define OPTION_SPARC (OPTION_MD_BASE + 1)
452 {"sparc", no_argument
, NULL
, OPTION_SPARC
},
453 #define OPTION_XARCH (OPTION_MD_BASE + 2)
454 {"xarch", required_argument
, NULL
, OPTION_XARCH
},
456 #define OPTION_32 (OPTION_MD_BASE + 3)
457 {"32", no_argument
, NULL
, OPTION_32
},
458 #define OPTION_64 (OPTION_MD_BASE + 4)
459 {"64", no_argument
, NULL
, OPTION_64
},
460 #define OPTION_TSO (OPTION_MD_BASE + 5)
461 {"TSO", no_argument
, NULL
, OPTION_TSO
},
462 #define OPTION_PSO (OPTION_MD_BASE + 6)
463 {"PSO", no_argument
, NULL
, OPTION_PSO
},
464 #define OPTION_RMO (OPTION_MD_BASE + 7)
465 {"RMO", no_argument
, NULL
, OPTION_RMO
},
467 #ifdef SPARC_BIENDIAN
468 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
469 {"EL", no_argument
, NULL
, OPTION_LITTLE_ENDIAN
},
470 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
471 {"EB", no_argument
, NULL
, OPTION_BIG_ENDIAN
},
473 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
474 {"enforce-aligned-data", no_argument
, NULL
, OPTION_ENFORCE_ALIGNED_DATA
},
475 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
476 {"little-endian-data", no_argument
, NULL
, OPTION_LITTLE_ENDIAN_DATA
},
478 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
479 {"no-undeclared-regs", no_argument
, NULL
, OPTION_NO_UNDECLARED_REGS
},
480 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
481 {"undeclared-regs", no_argument
, NULL
, OPTION_UNDECLARED_REGS
},
483 #define OPTION_RELAX (OPTION_MD_BASE + 14)
484 {"relax", no_argument
, NULL
, OPTION_RELAX
},
485 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
486 {"no-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
487 {NULL
, no_argument
, NULL
, 0}
490 size_t md_longopts_size
= sizeof (md_longopts
);
493 md_parse_option (int c
, const char *arg
)
495 /* We don't get a chance to initialize anything before we're called,
496 so handle that now. */
497 if (! default_init_p
)
498 init_default_arch ();
504 warn_after_architecture
= SPARC_OPCODE_ARCH_V6
;
509 if (!strncmp (arg
, "v9", 2))
510 md_parse_option (OPTION_64
, NULL
);
513 if (!strncmp (arg
, "v8", 2)
514 || !strncmp (arg
, "v7", 2)
515 || !strncmp (arg
, "v6", 2)
516 || !strcmp (arg
, "sparclet")
517 || !strcmp (arg
, "sparclite")
518 || !strcmp (arg
, "sparc86x"))
519 md_parse_option (OPTION_32
, NULL
);
526 struct sparc_arch
*sa
;
527 enum sparc_opcode_arch_val opcode_arch
;
529 sa
= lookup_arch (arg
);
531 || ! sa
->user_option_p
)
533 if (c
== OPTION_XARCH
)
534 as_bad (_("invalid architecture -xarch=%s"), arg
);
536 as_bad (_("invalid architecture -A%s"), arg
);
540 opcode_arch
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
541 if (opcode_arch
== SPARC_OPCODE_ARCH_BAD
)
542 as_fatal (_("Bad opcode table, broken assembler."));
544 if (!architecture_requested
545 || opcode_arch
> max_architecture
)
546 max_architecture
= opcode_arch
;
548 |= (((bfd_uint64_t
) sa
->hwcap2_allowed
) << 32) | sa
->hwcap_allowed
;
549 architecture_requested
= 1;
554 /* Ignore -sparc, used by SunOS make default .s.o rule. */
557 case OPTION_ENFORCE_ALIGNED_DATA
:
558 enforce_aligned_data
= 1;
561 #ifdef SPARC_BIENDIAN
562 case OPTION_LITTLE_ENDIAN
:
563 target_big_endian
= 0;
564 if (default_arch_type
!= sparclet
)
565 as_fatal ("This target does not support -EL");
567 case OPTION_LITTLE_ENDIAN_DATA
:
568 target_little_endian_data
= 1;
569 target_big_endian
= 0;
570 if (default_arch_type
!= sparc86x
571 && default_arch_type
!= v9
)
572 as_fatal ("This target does not support --little-endian-data");
574 case OPTION_BIG_ENDIAN
:
575 target_big_endian
= 1;
589 const char **list
, **l
;
591 sparc_arch_size
= c
== OPTION_32
? 32 : 64;
592 list
= bfd_target_list ();
593 for (l
= list
; *l
!= NULL
; l
++)
595 if (sparc_arch_size
== 32)
597 if (CONST_STRNEQ (*l
, "elf32-sparc"))
602 if (CONST_STRNEQ (*l
, "elf64-sparc"))
607 as_fatal (_("No compiled in support for %d bit object file format"),
611 if (sparc_arch_size
== 64
612 && max_architecture
< SPARC_OPCODE_ARCH_V9
)
613 max_architecture
= SPARC_OPCODE_ARCH_V9
;
618 sparc_memory_model
= MM_TSO
;
622 sparc_memory_model
= MM_PSO
;
626 sparc_memory_model
= MM_RMO
;
634 /* Qy - do emit .comment
635 Qn - do not emit .comment. */
639 /* Use .stab instead of .stab.excl. */
643 /* quick -- Native assembler does fewer checks. */
647 if (strcmp (arg
, "PIC") != 0)
648 as_warn (_("Unrecognized option following -K"));
653 case OPTION_NO_UNDECLARED_REGS
:
654 no_undeclared_regs
= 1;
657 case OPTION_UNDECLARED_REGS
:
658 no_undeclared_regs
= 0;
666 case OPTION_NO_RELAX
:
678 md_show_usage (FILE *stream
)
680 const struct sparc_arch
*arch
;
683 /* We don't get a chance to initialize anything before we're called,
684 so handle that now. */
685 if (! default_init_p
)
686 init_default_arch ();
688 fprintf (stream
, _("SPARC options:\n"));
690 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
692 if (!arch
->user_option_p
)
694 if (arch
!= &sparc_arch_table
[0])
695 fprintf (stream
, " | ");
696 if (column
+ strlen (arch
->name
) > 70)
699 fputc ('\n', stream
);
701 column
+= 5 + 2 + strlen (arch
->name
);
702 fprintf (stream
, "-A%s", arch
->name
);
704 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
706 if (!arch
->user_option_p
)
708 fprintf (stream
, " | ");
709 if (column
+ strlen (arch
->name
) > 65)
712 fputc ('\n', stream
);
714 column
+= 5 + 7 + strlen (arch
->name
);
715 fprintf (stream
, "-xarch=%s", arch
->name
);
717 fprintf (stream
, _("\n\
718 specify variant of SPARC architecture\n\
719 -bump warn when assembler switches architectures\n\
721 --enforce-aligned-data force .long, etc., to be aligned correctly\n\
722 -relax relax jumps and branches (default)\n\
723 -no-relax avoid changing any jumps and branches\n"));
725 fprintf (stream
, _("\
726 -k generate PIC\n"));
729 fprintf (stream
, _("\
730 -32 create 32 bit object file\n\
731 -64 create 64 bit object file\n"));
732 fprintf (stream
, _("\
733 [default is %d]\n"), default_arch_size
);
734 fprintf (stream
, _("\
735 -TSO use Total Store Ordering\n\
736 -PSO use Partial Store Ordering\n\
737 -RMO use Relaxed Memory Ordering\n"));
738 fprintf (stream
, _("\
739 [default is %s]\n"), (default_arch_size
== 64) ? "RMO" : "TSO");
740 fprintf (stream
, _("\
741 -KPIC generate PIC\n\
742 -V print assembler version number\n\
743 -undeclared-regs ignore application global register usage without\n\
744 appropriate .register directive (default)\n\
745 -no-undeclared-regs force error on application global register usage\n\
746 without appropriate .register directive\n\
751 #ifdef SPARC_BIENDIAN
752 fprintf (stream
, _("\
753 -EL generate code for a little endian machine\n\
754 -EB generate code for a big endian machine\n\
755 --little-endian-data generate code for a machine having big endian\n\
756 instructions and little endian data.\n"));
760 /* Native operand size opcode translation. */
766 } native_op_table
[] =
768 {"ldn", "ld", "ldx"},
769 {"ldna", "lda", "ldxa"},
770 {"stn", "st", "stx"},
771 {"stna", "sta", "stxa"},
772 {"slln", "sll", "sllx"},
773 {"srln", "srl", "srlx"},
774 {"sran", "sra", "srax"},
775 {"casn", "cas", "casx"},
776 {"casna", "casa", "casxa"},
777 {"clrn", "clr", "clrx"},
781 /* sparc64 privileged and hyperprivileged registers. */
783 struct priv_reg_entry
789 struct priv_reg_entry priv_reg_table
[] =
810 {NULL
, -1}, /* End marker. */
813 struct priv_reg_entry hpriv_reg_table
[] =
823 {"hstick_offset", 28},
824 {"hstick_enable", 29},
826 {NULL
, -1}, /* End marker. */
829 /* v9a or later specific ancillary state registers. */
831 struct priv_reg_entry v9a_asr_table
[] =
834 {"sys_tick_cmpr", 25},
838 {"softint_clear", 21},
849 {"clear_softint", 21},
850 {NULL
, -1}, /* End marker. */
854 cmp_reg_entry (const void *parg
, const void *qarg
)
856 const struct priv_reg_entry
*p
= (const struct priv_reg_entry
*) parg
;
857 const struct priv_reg_entry
*q
= (const struct priv_reg_entry
*) qarg
;
859 if (p
->name
== q
->name
)
861 else if (p
->name
== NULL
)
863 else if (q
->name
== NULL
)
866 return strcmp (q
->name
, p
->name
);
869 /* sparc %-pseudo-operations. */
872 #define F_POP_V9 0x1 /* The pseudo-op is for v9 only. */
873 #define F_POP_PCREL 0x2 /* The pseudo-op can be used in pc-relative
875 #define F_POP_TLS_CALL 0x4 /* The pseudo-op marks a tls call. */
876 #define F_POP_POSTFIX 0x8 /* The pseudo-op should appear after the
878 instruction. (Generally they can appear
879 anywhere an immediate operand is
883 /* The name as it appears in assembler. */
885 /* The reloc this pseudo-op translates to. */
887 /* Flags. See F_POP_* above. */
891 struct pop_entry pop_table
[] =
893 { "hix", BFD_RELOC_SPARC_HIX22
, F_POP_V9
},
894 { "lox", BFD_RELOC_SPARC_LOX10
, F_POP_V9
},
895 { "hi", BFD_RELOC_HI22
, F_POP_PCREL
},
896 { "lo", BFD_RELOC_LO10
, F_POP_PCREL
},
897 { "pc22", BFD_RELOC_SPARC_PC22
, F_POP_PCREL
},
898 { "pc10", BFD_RELOC_SPARC_PC10
, F_POP_PCREL
},
899 { "hh", BFD_RELOC_SPARC_HH22
, F_POP_V9
|F_POP_PCREL
},
900 { "hm", BFD_RELOC_SPARC_HM10
, F_POP_V9
|F_POP_PCREL
},
901 { "lm", BFD_RELOC_SPARC_LM22
, F_POP_V9
|F_POP_PCREL
},
902 { "h34", BFD_RELOC_SPARC_H34
, F_POP_V9
},
903 { "l34", BFD_RELOC_SPARC_L44
, F_POP_V9
},
904 { "h44", BFD_RELOC_SPARC_H44
, F_POP_V9
},
905 { "m44", BFD_RELOC_SPARC_M44
, F_POP_V9
},
906 { "l44", BFD_RELOC_SPARC_L44
, F_POP_V9
},
907 { "uhi", BFD_RELOC_SPARC_HH22
, F_POP_V9
},
908 { "ulo", BFD_RELOC_SPARC_HM10
, F_POP_V9
},
909 { "tgd_hi22", BFD_RELOC_SPARC_TLS_GD_HI22
, 0 },
910 { "tgd_lo10", BFD_RELOC_SPARC_TLS_GD_LO10
, 0 },
911 { "tldm_hi22", BFD_RELOC_SPARC_TLS_LDM_HI22
, 0 },
912 { "tldm_lo10", BFD_RELOC_SPARC_TLS_LDM_LO10
, 0 },
913 { "tldo_hix22", BFD_RELOC_SPARC_TLS_LDO_HIX22
, 0 },
914 { "tldo_lox10", BFD_RELOC_SPARC_TLS_LDO_LOX10
, 0 },
915 { "tie_hi22", BFD_RELOC_SPARC_TLS_IE_HI22
, 0 },
916 { "tie_lo10", BFD_RELOC_SPARC_TLS_IE_LO10
, 0 },
917 { "tle_hix22", BFD_RELOC_SPARC_TLS_LE_HIX22
, 0 },
918 { "tle_lox10", BFD_RELOC_SPARC_TLS_LE_LOX10
, 0 },
919 { "gdop_hix22", BFD_RELOC_SPARC_GOTDATA_OP_HIX22
, 0 },
920 { "gdop_lox10", BFD_RELOC_SPARC_GOTDATA_OP_LOX10
, 0 },
921 { "tgd_add", BFD_RELOC_SPARC_TLS_GD_ADD
, F_POP_POSTFIX
},
922 { "tgd_call", BFD_RELOC_SPARC_TLS_GD_CALL
, F_POP_POSTFIX
|F_POP_TLS_CALL
},
923 { "tldm_add", BFD_RELOC_SPARC_TLS_LDM_ADD
, F_POP_POSTFIX
},
924 { "tldm_call", BFD_RELOC_SPARC_TLS_LDM_CALL
, F_POP_POSTFIX
|F_POP_TLS_CALL
},
925 { "tldo_add", BFD_RELOC_SPARC_TLS_LDO_ADD
, F_POP_POSTFIX
},
926 { "tie_ldx", BFD_RELOC_SPARC_TLS_IE_LDX
, F_POP_POSTFIX
},
927 { "tie_ld", BFD_RELOC_SPARC_TLS_IE_LD
, F_POP_POSTFIX
},
928 { "tie_add", BFD_RELOC_SPARC_TLS_IE_ADD
, F_POP_POSTFIX
},
929 { "gdop", BFD_RELOC_SPARC_GOTDATA_OP
, F_POP_POSTFIX
},
933 /* Table of %-names that can appear in a sparc assembly program. This
934 table is initialized in md_begin and contains entries for each
935 privileged/hyperprivileged/alternate register and %-pseudo-op. */
948 enum perc_entry_type type
;
949 /* Name of the %-entity. */
953 /* Value. Either a pop or a reg depending on type.*/
956 struct pop_entry
*pop
;
957 struct priv_reg_entry
*reg
;
961 #define NUM_PERC_ENTRIES \
962 (((sizeof (priv_reg_table) / sizeof (priv_reg_table[0])) - 1) \
963 + ((sizeof (hpriv_reg_table) / sizeof (hpriv_reg_table[0])) - 1) \
964 + ((sizeof (v9a_asr_table) / sizeof (v9a_asr_table[0])) - 1) \
965 + ((sizeof (pop_table) / sizeof (pop_table[0])) - 1) \
968 struct perc_entry perc_table
[NUM_PERC_ENTRIES
];
971 cmp_perc_entry (const void *parg
, const void *qarg
)
973 const struct perc_entry
*p
= (const struct perc_entry
*) parg
;
974 const struct perc_entry
*q
= (const struct perc_entry
*) qarg
;
976 if (p
->name
== q
->name
)
978 else if (p
->name
== NULL
)
980 else if (q
->name
== NULL
)
983 return strcmp (q
->name
, p
->name
);
986 /* This function is called once, at assembler startup time. It should
987 set up all the tables, etc. that the MD part of the assembler will
993 const char *retval
= NULL
;
997 /* We don't get a chance to initialize anything before md_parse_option
998 is called, and it may not be called, so handle default initialization
999 now if not already done. */
1000 if (! default_init_p
)
1001 init_default_arch ();
1003 sparc_cie_data_alignment
= sparc_arch_size
== 64 ? -8 : -4;
1004 op_hash
= hash_new ();
1006 while (i
< (unsigned int) sparc_num_opcodes
)
1008 const char *name
= sparc_opcodes
[i
].name
;
1009 retval
= hash_insert (op_hash
, name
, (void *) &sparc_opcodes
[i
]);
1012 as_bad (_("Internal error: can't hash `%s': %s\n"),
1013 sparc_opcodes
[i
].name
, retval
);
1018 if (sparc_opcodes
[i
].match
& sparc_opcodes
[i
].lose
)
1020 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
1021 sparc_opcodes
[i
].name
, sparc_opcodes
[i
].args
);
1026 while (i
< (unsigned int) sparc_num_opcodes
1027 && !strcmp (sparc_opcodes
[i
].name
, name
));
1030 for (i
= 0; native_op_table
[i
].name
; i
++)
1032 const struct sparc_opcode
*insn
;
1033 const char *name
= ((sparc_arch_size
== 32)
1034 ? native_op_table
[i
].name32
1035 : native_op_table
[i
].name64
);
1036 insn
= (struct sparc_opcode
*) hash_find (op_hash
, name
);
1039 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
1040 name
, native_op_table
[i
].name
);
1045 retval
= hash_insert (op_hash
, native_op_table
[i
].name
,
1049 as_bad (_("Internal error: can't hash `%s': %s\n"),
1050 sparc_opcodes
[i
].name
, retval
);
1057 as_fatal (_("Broken assembler. No assembly attempted."));
1059 qsort (priv_reg_table
, sizeof (priv_reg_table
) / sizeof (priv_reg_table
[0]),
1060 sizeof (priv_reg_table
[0]), cmp_reg_entry
);
1061 qsort (hpriv_reg_table
, sizeof (hpriv_reg_table
) / sizeof (hpriv_reg_table
[0]),
1062 sizeof (hpriv_reg_table
[0]), cmp_reg_entry
);
1063 qsort (v9a_asr_table
, sizeof (v9a_asr_table
) / sizeof (v9a_asr_table
[0]),
1064 sizeof (v9a_asr_table
[0]), cmp_reg_entry
);
1066 /* If -bump, record the architecture level at which we start issuing
1067 warnings. The behaviour is different depending upon whether an
1068 architecture was explicitly specified. If it wasn't, we issue warnings
1069 for all upwards bumps. If it was, we don't start issuing warnings until
1070 we need to bump beyond the requested architecture or when we bump between
1071 conflicting architectures. */
1074 && architecture_requested
)
1076 /* `max_architecture' records the requested architecture.
1077 Issue warnings if we go above it. */
1078 warn_after_architecture
= max_architecture
;
1081 /* Find the highest architecture level that doesn't conflict with
1082 the requested one. */
1085 || !architecture_requested
)
1087 enum sparc_opcode_arch_val current_max_architecture
1090 for (max_architecture
= SPARC_OPCODE_ARCH_MAX
;
1091 max_architecture
> warn_after_architecture
;
1093 if (! SPARC_OPCODE_CONFLICT_P (max_architecture
,
1094 current_max_architecture
))
1098 /* Prepare the tables of %-pseudo-ops. */
1100 struct priv_reg_entry
*reg_tables
[]
1101 = {priv_reg_table
, hpriv_reg_table
, v9a_asr_table
, NULL
};
1102 struct priv_reg_entry
**reg_table
;
1105 /* Add registers. */
1106 for (reg_table
= reg_tables
; reg_table
[0]; reg_table
++)
1108 struct priv_reg_entry
*reg
;
1109 for (reg
= *reg_table
; reg
->name
; reg
++)
1111 struct perc_entry
*p
= &perc_table
[entry
++];
1112 p
->type
= perc_entry_reg
;
1113 p
->name
= reg
->name
;
1114 p
->len
= strlen (reg
->name
);
1119 /* Add %-pseudo-ops. */
1121 struct pop_entry
*pop
;
1123 for (pop
= pop_table
; pop
->name
; pop
++)
1125 struct perc_entry
*p
= &perc_table
[entry
++];
1126 p
->type
= (pop
->flags
& F_POP_POSTFIX
1127 ? perc_entry_post_pop
: perc_entry_imm_pop
);
1128 p
->name
= pop
->name
;
1129 p
->len
= strlen (pop
->name
);
1134 /* Last entry is the centinel. */
1135 perc_table
[entry
].type
= perc_entry_none
;
1137 qsort (perc_table
, sizeof (perc_table
) / sizeof (perc_table
[0]),
1138 sizeof (perc_table
[0]), cmp_perc_entry
);
1143 /* Called after all assembly has been done. */
1148 unsigned long mach
= bfd_mach_sparc
;
1149 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
1150 int hwcaps
, hwcaps2
;
1153 if (sparc_arch_size
== 64)
1154 switch (current_architecture
)
1156 case SPARC_OPCODE_ARCH_V9A
: mach
= bfd_mach_sparc_v9a
; break;
1157 case SPARC_OPCODE_ARCH_V9B
: mach
= bfd_mach_sparc_v9b
; break;
1158 case SPARC_OPCODE_ARCH_V9C
: mach
= bfd_mach_sparc_v9c
; break;
1159 case SPARC_OPCODE_ARCH_V9D
: mach
= bfd_mach_sparc_v9d
; break;
1160 case SPARC_OPCODE_ARCH_V9E
: mach
= bfd_mach_sparc_v9e
; break;
1161 case SPARC_OPCODE_ARCH_V9V
: mach
= bfd_mach_sparc_v9v
; break;
1162 case SPARC_OPCODE_ARCH_V9M
: mach
= bfd_mach_sparc_v9m
; break;
1163 default: mach
= bfd_mach_sparc_v9
; break;
1166 switch (current_architecture
)
1168 case SPARC_OPCODE_ARCH_SPARCLET
: mach
= bfd_mach_sparc_sparclet
; break;
1169 case SPARC_OPCODE_ARCH_V9
: mach
= bfd_mach_sparc_v8plus
; break;
1170 case SPARC_OPCODE_ARCH_V9A
: mach
= bfd_mach_sparc_v8plusa
; break;
1171 case SPARC_OPCODE_ARCH_V9B
: mach
= bfd_mach_sparc_v8plusb
; break;
1172 case SPARC_OPCODE_ARCH_V9C
: mach
= bfd_mach_sparc_v8plusc
; break;
1173 case SPARC_OPCODE_ARCH_V9D
: mach
= bfd_mach_sparc_v8plusd
; break;
1174 case SPARC_OPCODE_ARCH_V9E
: mach
= bfd_mach_sparc_v8pluse
; break;
1175 case SPARC_OPCODE_ARCH_V9V
: mach
= bfd_mach_sparc_v8plusv
; break;
1176 case SPARC_OPCODE_ARCH_V9M
: mach
= bfd_mach_sparc_v8plusm
; break;
1177 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
1178 be but for now it is (since that's the way it's always been
1182 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, mach
);
1184 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
1185 hwcaps
= hwcap_seen
& U0xffffffff
;
1186 hwcaps2
= hwcap_seen
>> 32;
1189 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
, Tag_GNU_Sparc_HWCAPS
, hwcaps
);
1191 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
, Tag_GNU_Sparc_HWCAPS2
, hwcaps2
);
1195 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
1198 in_signed_range (bfd_signed_vma val
, bfd_signed_vma max
)
1202 /* Sign-extend the value from the architecture word size, so that
1203 0xffffffff is always considered -1 on sparc32. */
1204 if (sparc_arch_size
== 32)
1206 bfd_signed_vma sign
= (bfd_signed_vma
) 1 << 31;
1207 val
= ((val
& U0xffffffff
) ^ sign
) - sign
;
1216 /* Return non-zero if VAL is in the range 0 to MAX. */
1219 in_unsigned_range (bfd_vma val
, bfd_vma max
)
1226 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
1227 (e.g. -15 to +31). */
1230 in_bitfield_range (bfd_signed_vma val
, bfd_signed_vma max
)
1236 if (val
< ~(max
>> 1))
1242 sparc_ffs (unsigned int mask
)
1249 for (i
= 0; (mask
& 1) == 0; ++i
)
1254 /* Implement big shift right. */
1256 BSR (bfd_vma val
, int amount
)
1258 if (sizeof (bfd_vma
) <= 4 && amount
>= 32)
1259 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
1260 return val
>> amount
;
1263 /* For communication between sparc_ip and get_expression. */
1264 static char *expr_end
;
1266 /* Values for `special_case'.
1267 Instructions that require wierd handling because they're longer than
1269 #define SPECIAL_CASE_NONE 0
1270 #define SPECIAL_CASE_SET 1
1271 #define SPECIAL_CASE_SETSW 2
1272 #define SPECIAL_CASE_SETX 3
1273 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
1274 #define SPECIAL_CASE_FDIV 4
1276 /* Bit masks of various insns. */
1277 #define NOP_INSN 0x01000000
1278 #define OR_INSN 0x80100000
1279 #define XOR_INSN 0x80180000
1280 #define FMOVS_INSN 0x81A00020
1281 #define SETHI_INSN 0x01000000
1282 #define SLLX_INSN 0x81281000
1283 #define SRA_INSN 0x81380000
1285 /* The last instruction to be assembled. */
1286 static const struct sparc_opcode
*last_insn
;
1287 /* The assembled opcode of `last_insn'. */
1288 static unsigned long last_opcode
;
1290 /* Handle the set and setuw synthetic instructions. */
1293 synthetize_setuw (const struct sparc_opcode
*insn
)
1295 int need_hi22_p
= 0;
1296 int rd
= (the_insn
.opcode
& RD (~0)) >> 25;
1298 if (the_insn
.exp
.X_op
== O_constant
)
1300 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1302 if (sizeof (offsetT
) > 4
1303 && (the_insn
.exp
.X_add_number
< 0
1304 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1305 as_warn (_("set: number not in 0..4294967295 range"));
1309 if (sizeof (offsetT
) > 4
1310 && (the_insn
.exp
.X_add_number
< -(offsetT
) U0x80000000
1311 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1312 as_warn (_("set: number not in -2147483648..4294967295 range"));
1313 the_insn
.exp
.X_add_number
= (int) the_insn
.exp
.X_add_number
;
1317 /* See if operand is absolute and small; skip sethi if so. */
1318 if (the_insn
.exp
.X_op
!= O_constant
1319 || the_insn
.exp
.X_add_number
>= (1 << 12)
1320 || the_insn
.exp
.X_add_number
< -(1 << 12))
1322 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
1323 | ((the_insn
.exp
.X_add_number
>> 10)
1324 & (the_insn
.exp
.X_op
== O_constant
1326 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1327 ? BFD_RELOC_HI22
: BFD_RELOC_NONE
);
1328 output_insn (insn
, &the_insn
);
1332 /* See if operand has no low-order bits; skip OR if so. */
1333 if (the_insn
.exp
.X_op
!= O_constant
1334 || (need_hi22_p
&& (the_insn
.exp
.X_add_number
& 0x3FF) != 0)
1337 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (rd
) : 0)
1339 | (the_insn
.exp
.X_add_number
1340 & (the_insn
.exp
.X_op
!= O_constant
1341 ? 0 : need_hi22_p
? 0x3ff : 0x1fff)));
1342 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1343 ? BFD_RELOC_LO10
: BFD_RELOC_NONE
);
1344 output_insn (insn
, &the_insn
);
1348 /* Handle the setsw synthetic instruction. */
1351 synthetize_setsw (const struct sparc_opcode
*insn
)
1355 rd
= (the_insn
.opcode
& RD (~0)) >> 25;
1357 if (the_insn
.exp
.X_op
!= O_constant
)
1359 synthetize_setuw (insn
);
1361 /* Need to sign extend it. */
1362 the_insn
.opcode
= (SRA_INSN
| RS1 (rd
) | RD (rd
));
1363 the_insn
.reloc
= BFD_RELOC_NONE
;
1364 output_insn (insn
, &the_insn
);
1368 if (sizeof (offsetT
) > 4
1369 && (the_insn
.exp
.X_add_number
< -(offsetT
) U0x80000000
1370 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1371 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1373 low32
= the_insn
.exp
.X_add_number
;
1377 synthetize_setuw (insn
);
1383 the_insn
.reloc
= BFD_RELOC_NONE
;
1384 /* See if operand is absolute and small; skip sethi if so. */
1385 if (low32
< -(1 << 12))
1387 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
1388 | (((~the_insn
.exp
.X_add_number
) >> 10) & 0x3fffff));
1389 output_insn (insn
, &the_insn
);
1390 low32
= 0x1c00 | (low32
& 0x3ff);
1391 opc
= RS1 (rd
) | XOR_INSN
;
1394 the_insn
.opcode
= (opc
| RD (rd
) | IMMED
1395 | (low32
& 0x1fff));
1396 output_insn (insn
, &the_insn
);
1399 /* Handle the setx synthetic instruction. */
1402 synthetize_setx (const struct sparc_opcode
*insn
)
1404 int upper32
, lower32
;
1405 int tmpreg
= (the_insn
.opcode
& RS1 (~0)) >> 14;
1406 int dstreg
= (the_insn
.opcode
& RD (~0)) >> 25;
1408 int need_hh22_p
= 0, need_hm10_p
= 0, need_hi22_p
= 0, need_lo10_p
= 0;
1409 int need_xor10_p
= 0;
1411 #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000)
1412 lower32
= SIGNEXT32 (the_insn
.exp
.X_add_number
);
1413 upper32
= SIGNEXT32 (BSR (the_insn
.exp
.X_add_number
, 32));
1416 upper_dstreg
= tmpreg
;
1417 /* The tmp reg should not be the dst reg. */
1418 if (tmpreg
== dstreg
)
1419 as_warn (_("setx: temporary register same as destination register"));
1421 /* ??? Obviously there are other optimizations we can do
1422 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1423 doing some of these. Later. If you do change things, try to
1424 change all of this to be table driven as well. */
1425 /* What to output depends on the number if it's constant.
1426 Compute that first, then output what we've decided upon. */
1427 if (the_insn
.exp
.X_op
!= O_constant
)
1429 if (sparc_arch_size
== 32)
1431 /* When arch size is 32, we want setx to be equivalent
1432 to setuw for anything but constants. */
1433 the_insn
.exp
.X_add_number
&= 0xffffffff;
1434 synthetize_setuw (insn
);
1437 need_hh22_p
= need_hm10_p
= need_hi22_p
= need_lo10_p
= 1;
1443 /* Reset X_add_number, we've extracted it as upper32/lower32.
1444 Otherwise fixup_segment will complain about not being able to
1445 write an 8 byte number in a 4 byte field. */
1446 the_insn
.exp
.X_add_number
= 0;
1448 /* Only need hh22 if `or' insn can't handle constant. */
1449 if (upper32
< -(1 << 12) || upper32
>= (1 << 12))
1452 /* Does bottom part (after sethi) have bits? */
1453 if ((need_hh22_p
&& (upper32
& 0x3ff) != 0)
1454 /* No hh22, but does upper32 still have bits we can't set
1456 || (! need_hh22_p
&& upper32
!= 0 && upper32
!= -1))
1459 /* If the lower half is all zero, we build the upper half directly
1460 into the dst reg. */
1462 /* Need lower half if number is zero or 0xffffffff00000000. */
1463 || (! need_hh22_p
&& ! need_hm10_p
))
1465 /* No need for sethi if `or' insn can handle constant. */
1466 if (lower32
< -(1 << 12) || lower32
>= (1 << 12)
1467 /* Note that we can't use a negative constant in the `or'
1468 insn unless the upper 32 bits are all ones. */
1469 || (lower32
< 0 && upper32
!= -1)
1470 || (lower32
>= 0 && upper32
== -1))
1473 if (need_hi22_p
&& upper32
== -1)
1476 /* Does bottom part (after sethi) have bits? */
1477 else if ((need_hi22_p
&& (lower32
& 0x3ff) != 0)
1479 || (! need_hi22_p
&& (lower32
& 0x1fff) != 0)
1480 /* Need `or' if we didn't set anything else. */
1481 || (! need_hi22_p
&& ! need_hh22_p
&& ! need_hm10_p
))
1485 /* Output directly to dst reg if lower 32 bits are all zero. */
1486 upper_dstreg
= dstreg
;
1489 if (!upper_dstreg
&& dstreg
)
1490 as_warn (_("setx: illegal temporary register g0"));
1494 the_insn
.opcode
= (SETHI_INSN
| RD (upper_dstreg
)
1495 | ((upper32
>> 10) & 0x3fffff));
1496 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1497 ? BFD_RELOC_SPARC_HH22
: BFD_RELOC_NONE
);
1498 output_insn (insn
, &the_insn
);
1503 the_insn
.opcode
= (SETHI_INSN
| RD (dstreg
)
1504 | (((need_xor10_p
? ~lower32
: lower32
)
1505 >> 10) & 0x3fffff));
1506 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1507 ? BFD_RELOC_SPARC_LM22
: BFD_RELOC_NONE
);
1508 output_insn (insn
, &the_insn
);
1513 the_insn
.opcode
= (OR_INSN
1514 | (need_hh22_p
? RS1 (upper_dstreg
) : 0)
1517 | (upper32
& (need_hh22_p
? 0x3ff : 0x1fff)));
1518 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1519 ? BFD_RELOC_SPARC_HM10
: BFD_RELOC_NONE
);
1520 output_insn (insn
, &the_insn
);
1525 /* FIXME: One nice optimization to do here is to OR the low part
1526 with the highpart if hi22 isn't needed and the low part is
1528 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (dstreg
) : 0)
1531 | (lower32
& (need_hi22_p
? 0x3ff : 0x1fff)));
1532 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1533 ? BFD_RELOC_LO10
: BFD_RELOC_NONE
);
1534 output_insn (insn
, &the_insn
);
1537 /* If we needed to build the upper part, shift it into place. */
1538 if (need_hh22_p
|| need_hm10_p
)
1540 the_insn
.opcode
= (SLLX_INSN
| RS1 (upper_dstreg
) | RD (upper_dstreg
)
1542 the_insn
.reloc
= BFD_RELOC_NONE
;
1543 output_insn (insn
, &the_insn
);
1546 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1549 the_insn
.opcode
= (XOR_INSN
| RS1 (dstreg
) | RD (dstreg
) | IMMED
1550 | 0x1c00 | (lower32
& 0x3ff));
1551 the_insn
.reloc
= BFD_RELOC_NONE
;
1552 output_insn (insn
, &the_insn
);
1555 /* If we needed to build both upper and lower parts, OR them together. */
1556 else if ((need_hh22_p
|| need_hm10_p
) && (need_hi22_p
|| need_lo10_p
))
1558 the_insn
.opcode
= (OR_INSN
| RS1 (dstreg
) | RS2 (upper_dstreg
)
1560 the_insn
.reloc
= BFD_RELOC_NONE
;
1561 output_insn (insn
, &the_insn
);
1565 /* Main entry point to assemble one instruction. */
1568 md_assemble (char *str
)
1570 const struct sparc_opcode
*insn
;
1574 special_case
= sparc_ip (str
, &insn
);
1578 /* We warn about attempts to put a floating point branch in a delay slot,
1579 unless the delay slot has been annulled. */
1580 if (last_insn
!= NULL
1581 && (insn
->flags
& F_FBR
) != 0
1582 && (last_insn
->flags
& F_DELAYED
) != 0
1583 /* ??? This test isn't completely accurate. We assume anything with
1584 F_{UNBR,CONDBR,FBR} set is annullable. */
1585 && ((last_insn
->flags
& (F_UNBR
| F_CONDBR
| F_FBR
)) == 0
1586 || (last_opcode
& ANNUL
) == 0))
1587 as_warn (_("FP branch in delay slot"));
1589 /* SPARC before v9 requires a nop instruction between a floating
1590 point instruction and a floating point branch. We insert one
1591 automatically, with a warning. */
1592 if (max_architecture
< SPARC_OPCODE_ARCH_V9
1593 && last_insn
!= NULL
1594 && (insn
->flags
& F_FBR
) != 0
1595 && (last_insn
->flags
& F_FLOAT
) != 0)
1597 struct sparc_it nop_insn
;
1599 nop_insn
.opcode
= NOP_INSN
;
1600 nop_insn
.reloc
= BFD_RELOC_NONE
;
1601 output_insn (insn
, &nop_insn
);
1602 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1605 switch (special_case
)
1607 case SPECIAL_CASE_NONE
:
1609 output_insn (insn
, &the_insn
);
1612 case SPECIAL_CASE_SETSW
:
1613 synthetize_setsw (insn
);
1616 case SPECIAL_CASE_SET
:
1617 synthetize_setuw (insn
);
1620 case SPECIAL_CASE_SETX
:
1621 synthetize_setx (insn
);
1624 case SPECIAL_CASE_FDIV
:
1626 int rd
= (the_insn
.opcode
>> 25) & 0x1f;
1628 output_insn (insn
, &the_insn
);
1630 /* According to information leaked from Sun, the "fdiv" instructions
1631 on early SPARC machines would produce incorrect results sometimes.
1632 The workaround is to add an fmovs of the destination register to
1633 itself just after the instruction. This was true on machines
1634 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1635 gas_assert (the_insn
.reloc
== BFD_RELOC_NONE
);
1636 the_insn
.opcode
= FMOVS_INSN
| rd
| RD (rd
);
1637 output_insn (insn
, &the_insn
);
1642 as_fatal (_("failed special case insn sanity check"));
1647 get_hwcap_name (bfd_uint64_t mask
)
1649 if (mask
& HWCAP_MUL32
)
1651 if (mask
& HWCAP_DIV32
)
1653 if (mask
& HWCAP_FSMULD
)
1655 if (mask
& HWCAP_V8PLUS
)
1657 if (mask
& HWCAP_POPC
)
1659 if (mask
& HWCAP_VIS
)
1661 if (mask
& HWCAP_VIS2
)
1663 if (mask
& HWCAP_ASI_BLK_INIT
)
1664 return "ASIBlkInit";
1665 if (mask
& HWCAP_FMAF
)
1667 if (mask
& HWCAP_VIS3
)
1669 if (mask
& HWCAP_HPC
)
1671 if (mask
& HWCAP_RANDOM
)
1673 if (mask
& HWCAP_TRANS
)
1675 if (mask
& HWCAP_FJFMAU
)
1677 if (mask
& HWCAP_IMA
)
1679 if (mask
& HWCAP_ASI_CACHE_SPARING
)
1681 if (mask
& HWCAP_AES
)
1683 if (mask
& HWCAP_DES
)
1685 if (mask
& HWCAP_KASUMI
)
1687 if (mask
& HWCAP_CAMELLIA
)
1689 if (mask
& HWCAP_MD5
)
1691 if (mask
& HWCAP_SHA1
)
1693 if (mask
& HWCAP_SHA256
)
1695 if (mask
& HWCAP_SHA512
)
1697 if (mask
& HWCAP_MPMUL
)
1699 if (mask
& HWCAP_MONT
)
1701 if (mask
& HWCAP_PAUSE
)
1703 if (mask
& HWCAP_CBCOND
)
1705 if (mask
& HWCAP_CRC32C
)
1709 if (mask
& HWCAP2_FJATHPLUS
)
1711 if (mask
& HWCAP2_VIS3B
)
1713 if (mask
& HWCAP2_ADP
)
1715 if (mask
& HWCAP2_SPARC5
)
1717 if (mask
& HWCAP2_MWAIT
)
1719 if (mask
& HWCAP2_XMPMUL
)
1721 if (mask
& HWCAP2_XMONT
)
1723 if (mask
& HWCAP2_NSEC
)
1729 /* Subroutine of md_assemble to do the actual parsing. */
1732 sparc_ip (char *str
, const struct sparc_opcode
**pinsn
)
1734 const char *error_message
= "";
1738 const struct sparc_opcode
*insn
;
1740 unsigned long opcode
;
1741 unsigned int mask
= 0;
1745 int special_case
= SPECIAL_CASE_NONE
;
1752 while (ISLOWER (*s
) || ISDIGIT (*s
) || *s
== '_');
1769 as_bad (_("Unknown opcode: `%s'"), str
);
1771 return special_case
;
1773 insn
= (struct sparc_opcode
*) hash_find (op_hash
, str
);
1777 as_bad (_("Unknown opcode: `%s'"), str
);
1778 return special_case
;
1788 opcode
= insn
->match
;
1789 memset (&the_insn
, '\0', sizeof (the_insn
));
1790 the_insn
.reloc
= BFD_RELOC_NONE
;
1793 /* Build the opcode, checking as we go to make sure that the
1795 for (args
= insn
->args
;; ++args
)
1803 /* Parse a series of masks. */
1810 if (! parse_keyword_arg (sparc_encode_membar
, &s
,
1813 error_message
= _(": invalid membar mask name");
1819 if (*s
== '|' || *s
== '+')
1827 if (! parse_const_expr_arg (&s
, &kmask
))
1829 error_message
= _(": invalid membar mask expression");
1832 if (kmask
< 0 || kmask
> 127)
1834 error_message
= _(": invalid membar mask number");
1839 opcode
|= MEMBAR (kmask
);
1847 if (! parse_const_expr_arg (&s
, &smask
))
1849 error_message
= _(": invalid siam mode expression");
1852 if (smask
< 0 || smask
> 7)
1854 error_message
= _(": invalid siam mode number");
1865 /* Parse a prefetch function. */
1868 if (! parse_keyword_arg (sparc_encode_prefetch
, &s
, &fcn
))
1870 error_message
= _(": invalid prefetch function name");
1876 if (! parse_const_expr_arg (&s
, &fcn
))
1878 error_message
= _(": invalid prefetch function expression");
1881 if (fcn
< 0 || fcn
> 31)
1883 error_message
= _(": invalid prefetch function number");
1893 /* Parse a sparc64 privileged register. */
1896 struct priv_reg_entry
*p
;
1897 unsigned int len
= 9999999; /* Init to make gcc happy. */
1900 for (p
= priv_reg_table
; p
->name
; p
++)
1901 if (p
->name
[0] == s
[0])
1903 len
= strlen (p
->name
);
1904 if (strncmp (p
->name
, s
, len
) == 0)
1910 error_message
= _(": unrecognizable privileged register");
1914 if (((opcode
>> (*args
== '?' ? 14 : 25)) & 0x1f) != (unsigned) p
->regnum
)
1916 error_message
= _(": unrecognizable privileged register");
1925 error_message
= _(": unrecognizable privileged register");
1931 /* Parse a sparc64 hyperprivileged register. */
1934 struct priv_reg_entry
*p
;
1935 unsigned int len
= 9999999; /* Init to make gcc happy. */
1938 for (p
= hpriv_reg_table
; p
->name
; p
++)
1939 if (p
->name
[0] == s
[0])
1941 len
= strlen (p
->name
);
1942 if (strncmp (p
->name
, s
, len
) == 0)
1948 error_message
= _(": unrecognizable hyperprivileged register");
1952 if (((opcode
>> (*args
== '$' ? 14 : 25)) & 0x1f) != (unsigned) p
->regnum
)
1954 error_message
= _(": unrecognizable hyperprivileged register");
1963 error_message
= _(": unrecognizable hyperprivileged register");
1969 /* Parse a v9a or later ancillary state register. */
1972 struct priv_reg_entry
*p
;
1973 unsigned int len
= 9999999; /* Init to make gcc happy. */
1976 for (p
= v9a_asr_table
; p
->name
; p
++)
1977 if (p
->name
[0] == s
[0])
1979 len
= strlen (p
->name
);
1980 if (strncmp (p
->name
, s
, len
) == 0)
1986 error_message
= _(": unrecognizable ancillary state register");
1990 if (((opcode
>> (*args
== '/' ? 14 : 25)) & 0x1f) != (unsigned) p
->regnum
)
1992 error_message
= _(": unrecognizable ancillary state register");
2001 error_message
= _(": unrecognizable ancillary state register");
2007 if (strncmp (s
, "%asr", 4) == 0)
2015 while (ISDIGIT (*s
))
2017 num
= num
* 10 + *s
- '0';
2021 /* We used to check here for the asr number to
2022 be between 16 and 31 in V9 and later, as
2023 mandated by the section C.1.1 "Register
2024 Names" in the SPARC spec. However, we
2025 decided to remove this restriction as a) it
2026 introduces problems when new V9 asr registers
2027 are introduced, b) the Solaris assembler
2028 doesn't implement this restriction and c) the
2029 restriction will go away in future revisions
2030 of the Oracle SPARC Architecture. */
2032 if (num
< 0 || 31 < num
)
2034 error_message
= _(": asr number must be between 0 and 31");
2038 opcode
|= (*args
== 'M' ? RS1 (num
) : RD (num
));
2043 error_message
= _(": expecting %asrN");
2050 the_insn
.reloc
= BFD_RELOC_SPARC_11
;
2054 the_insn
.reloc
= BFD_RELOC_SPARC_10
;
2060 if ((s
[0] == '0' && s
[1] == 'x' && ISXDIGIT (s
[2]))
2065 if (s
[0] == '0' && s
[1] == 'x')
2068 while (ISXDIGIT (*s
))
2071 num
|= hex_value (*s
);
2077 while (ISDIGIT (*s
))
2079 num
= num
* 10 + *s
- '0';
2083 if (num
< 0 || num
> 31)
2085 error_message
= _(": crypto immediate must be between 0 and 31");
2089 opcode
|= RS3 (num
);
2094 error_message
= _(": expecting crypto immediate");
2099 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
2100 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2101 the_insn
.reloc
= BFD_RELOC_SPARC_5
;
2103 the_insn
.reloc
= BFD_RELOC_SPARC13
;
2104 /* These fields are unsigned, but for upward compatibility,
2105 allow negative values as well. */
2109 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
2110 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2111 the_insn
.reloc
= BFD_RELOC_SPARC_6
;
2113 the_insn
.reloc
= BFD_RELOC_SPARC13
;
2114 /* These fields are unsigned, but for upward compatibility,
2115 allow negative values as well. */
2119 the_insn
.reloc
= /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16
;
2124 the_insn
.reloc
= /* RELOC_WDISP2_8 */ BFD_RELOC_SPARC_WDISP10
;
2129 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP19
;
2134 if (*s
== 'p' && s
[1] == 'n')
2142 if (*s
== 'p' && s
[1] == 't')
2154 if ((strncmp (s
, "%icc", 4) == 0)
2155 || (sparc_arch_size
== 32 && strncmp (s
, "%ncc", 4) == 0))
2167 if ((strncmp (s
, "%xcc", 4) == 0)
2168 || (sparc_arch_size
== 64 && strncmp (s
, "%ncc", 4) == 0))
2180 if (strncmp (s
, "%fcc0", 5) == 0)
2192 if (strncmp (s
, "%fcc1", 5) == 0)
2204 if (strncmp (s
, "%fcc2", 5) == 0)
2216 if (strncmp (s
, "%fcc3", 5) == 0)
2224 if (strncmp (s
, "%pc", 3) == 0)
2232 if (strncmp (s
, "%tick", 5) == 0)
2239 case '\0': /* End of args. */
2240 if (s
[0] == ',' && s
[1] == '%')
2244 const struct perc_entry
*p
;
2246 for (p
= perc_table
; p
->type
!= perc_entry_none
; p
++)
2247 if ((p
->type
== perc_entry_post_pop
|| p
->type
== perc_entry_reg
)
2248 && strncmp (s
+ 2, p
->name
, p
->len
) == 0)
2250 if (p
->type
== perc_entry_none
|| p
->type
== perc_entry_reg
)
2253 if (s
[p
->len
+ 2] != '(')
2255 as_bad (_("Illegal operands: %%%s requires arguments in ()"), p
->name
);
2256 return special_case
;
2259 if (! (p
->pop
->flags
& F_POP_TLS_CALL
)
2260 && the_insn
.reloc
!= BFD_RELOC_NONE
)
2262 as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"),
2264 return special_case
;
2267 if ((p
->pop
->flags
& F_POP_TLS_CALL
)
2268 && (the_insn
.reloc
!= BFD_RELOC_32_PCREL_S2
2269 || the_insn
.exp
.X_add_number
!= 0
2270 || the_insn
.exp
.X_add_symbol
2271 != symbol_find_or_make ("__tls_get_addr")))
2273 as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"),
2275 return special_case
;
2278 the_insn
.reloc
= p
->pop
->reloc
;
2279 memset (&the_insn
.exp
, 0, sizeof (the_insn
.exp
));
2282 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2285 else if (*s1
== ')')
2294 as_bad (_("Illegal operands: %%%s requires arguments in ()"), p
->name
);
2295 return special_case
;
2299 (void) get_expression (s
);
2319 case '[': /* These must match exactly. */
2327 case '#': /* Must be at least one digit. */
2330 while (ISDIGIT (*s
))
2338 case 'C': /* Coprocessor state register. */
2339 if (strncmp (s
, "%csr", 4) == 0)
2346 case 'b': /* Next operand is a coprocessor register. */
2349 if (*s
++ == '%' && *s
++ == 'c' && ISDIGIT (*s
))
2354 mask
= 10 * (mask
- '0') + (*s
++ - '0');
2368 opcode
|= mask
<< 14;
2376 opcode
|= mask
<< 25;
2382 case 'r': /* next operand must be a register */
2392 case 'f': /* frame pointer */
2400 case 'g': /* global register */
2409 case 'i': /* in register */
2413 mask
= c
- '0' + 24;
2418 case 'l': /* local register */
2422 mask
= (c
- '0' + 16);
2427 case 'o': /* out register */
2431 mask
= (c
- '0' + 8);
2436 case 's': /* stack pointer */
2444 case 'r': /* any register */
2445 if (!ISDIGIT ((c
= *s
++)))
2462 if ((c
= 10 * (c
- '0') + (*s
++ - '0')) >= 32)
2478 if ((mask
& ~1) == 2 && sparc_arch_size
== 64
2479 && no_undeclared_regs
&& ! globals
[mask
])
2480 as_bad (_("detected global register use not covered by .register pseudo-op"));
2482 /* Got the register, now figure out where
2483 it goes in the opcode. */
2487 opcode
|= mask
<< 14;
2495 opcode
|= mask
<< 25;
2499 opcode
|= (mask
<< 25) | (mask
<< 14);
2503 opcode
|= (mask
<< 25) | (mask
<< 0);
2509 case 'e': /* next operand is a floating point register */
2528 && ((format
= *s
) == 'f'
2533 for (mask
= 0; ISDIGIT (*s
); ++s
)
2535 mask
= 10 * mask
+ (*s
- '0');
2536 } /* read the number */
2545 /* register must be even numbered */
2555 /* register must be multiple of 4 */
2561 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2562 error_message
= _(": There are only 64 f registers; [0-63]");
2564 error_message
= _(": There are only 32 f registers; [0-31]");
2567 else if (mask
>= 32)
2569 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2571 if (*args
== 'e' || *args
== 'f' || *args
== 'g')
2574 = _(": There are only 32 single precision f registers; [0-31]");
2578 mask
-= 31; /* wrap high bit */
2582 error_message
= _(": There are only 32 f registers; [0-31]");
2590 } /* if not an 'f' register. */
2592 if (*args
== '}' && mask
!= RS2 (opcode
))
2595 = _(": Instruction requires frs2 and frsd must be the same register");
2604 opcode
|= RS1 (mask
);
2610 opcode
|= RS2 (mask
);
2615 opcode
|= RS3 (mask
);
2622 opcode
|= RD (mask
);
2631 if (strncmp (s
, "%fsr", 4) == 0)
2639 if (strncmp (s
, "%efsr", 5) == 0)
2646 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2647 the_insn
.reloc
= BFD_RELOC_NONE
; /* reloc handled elsewhere */
2650 case 'l': /* 22 bit PC relative immediate */
2651 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP22
;
2655 case 'L': /* 30 bit immediate */
2656 the_insn
.reloc
= BFD_RELOC_32_PCREL_S2
;
2661 case 'n': /* 22 bit immediate */
2662 the_insn
.reloc
= BFD_RELOC_SPARC22
;
2665 case 'i': /* 13 bit immediate */
2666 the_insn
.reloc
= BFD_RELOC_SPARC13
;
2676 const char *op_arg
= NULL
;
2677 static expressionS op_exp
;
2678 bfd_reloc_code_real_type old_reloc
= the_insn
.reloc
;
2680 /* Check for %hi, etc. */
2683 const struct perc_entry
*p
;
2685 for (p
= perc_table
; p
->type
!= perc_entry_none
; p
++)
2686 if ((p
->type
== perc_entry_imm_pop
|| p
->type
== perc_entry_reg
)
2687 && strncmp (s
+ 1, p
->name
, p
->len
) == 0)
2689 if (p
->type
== perc_entry_none
|| p
->type
== perc_entry_reg
)
2692 if (s
[p
->len
+ 1] != '(')
2694 as_bad (_("Illegal operands: %%%s requires arguments in ()"), p
->name
);
2695 return special_case
;
2699 the_insn
.reloc
= p
->pop
->reloc
;
2701 v9_arg_p
= p
->pop
->flags
& F_POP_V9
;
2704 /* Note that if the get_expression() fails, we will still
2705 have created U entries in the symbol table for the
2706 'symbols' in the input string. Try not to create U
2707 symbols for registers, etc. */
2709 /* This stuff checks to see if the expression ends in
2710 +%reg. If it does, it removes the register from
2711 the expression, and re-sets 's' to point to the
2718 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2721 else if (*s1
== ')')
2730 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg
);
2731 return special_case
;
2735 (void) get_expression (s
);
2739 as_bad (_("Expression inside %%%s could not be parsed"), op_arg
);
2740 return special_case
;
2743 if (*s
== ',' || *s
== ']' || !*s
)
2745 if (*s
!= '+' && *s
!= '-')
2747 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg
);
2748 return special_case
;
2752 op_exp
= the_insn
.exp
;
2753 memset (&the_insn
.exp
, 0, sizeof (the_insn
.exp
));
2756 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2759 if (s1
!= s
&& ISDIGIT (s1
[-1]))
2761 if (s1
[-2] == '%' && s1
[-3] == '+')
2763 else if (strchr ("golir0123456789", s1
[-2]) && s1
[-3] == '%' && s1
[-4] == '+')
2765 else if (s1
[-3] == 'r' && s1
[-4] == '%' && s1
[-5] == '+')
2772 if (op_arg
&& s1
== s
+ 1)
2773 the_insn
.exp
.X_op
= O_absent
;
2775 (void) get_expression (s
);
2787 (void) get_expression (s
);
2795 the_insn
.exp2
= the_insn
.exp
;
2796 the_insn
.exp
= op_exp
;
2797 if (the_insn
.exp2
.X_op
== O_absent
)
2798 the_insn
.exp2
.X_op
= O_illegal
;
2799 else if (the_insn
.exp
.X_op
== O_absent
)
2801 the_insn
.exp
= the_insn
.exp2
;
2802 the_insn
.exp2
.X_op
= O_illegal
;
2804 else if (the_insn
.exp
.X_op
== O_constant
)
2806 valueT val
= the_insn
.exp
.X_add_number
;
2807 switch (the_insn
.reloc
)
2812 case BFD_RELOC_SPARC_HH22
:
2813 val
= BSR (val
, 32);
2816 case BFD_RELOC_SPARC_LM22
:
2817 case BFD_RELOC_HI22
:
2818 val
= (val
>> 10) & 0x3fffff;
2821 case BFD_RELOC_SPARC_HM10
:
2822 val
= BSR (val
, 32);
2825 case BFD_RELOC_LO10
:
2829 case BFD_RELOC_SPARC_H34
:
2834 case BFD_RELOC_SPARC_H44
:
2839 case BFD_RELOC_SPARC_M44
:
2844 case BFD_RELOC_SPARC_L44
:
2848 case BFD_RELOC_SPARC_HIX22
:
2850 val
= (val
>> 10) & 0x3fffff;
2853 case BFD_RELOC_SPARC_LOX10
:
2854 val
= (val
& 0x3ff) | 0x1c00;
2857 the_insn
.exp
= the_insn
.exp2
;
2858 the_insn
.exp
.X_add_number
+= val
;
2859 the_insn
.exp2
.X_op
= O_illegal
;
2860 the_insn
.reloc
= old_reloc
;
2862 else if (the_insn
.exp2
.X_op
!= O_constant
)
2864 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg
);
2865 return special_case
;
2869 if (old_reloc
!= BFD_RELOC_SPARC13
2870 || the_insn
.reloc
!= BFD_RELOC_LO10
2871 || sparc_arch_size
!= 64
2874 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg
);
2875 return special_case
;
2877 the_insn
.reloc
= BFD_RELOC_SPARC_OLO10
;
2881 /* Check for constants that don't require emitting a reloc. */
2882 if (the_insn
.exp
.X_op
== O_constant
2883 && the_insn
.exp
.X_add_symbol
== 0
2884 && the_insn
.exp
.X_op_symbol
== 0)
2886 /* For pc-relative call instructions, we reject
2887 constants to get better code. */
2889 && the_insn
.reloc
== BFD_RELOC_32_PCREL_S2
2890 && in_signed_range (the_insn
.exp
.X_add_number
, 0x3fff))
2892 error_message
= _(": PC-relative operand can't be a constant");
2896 if (the_insn
.reloc
>= BFD_RELOC_SPARC_TLS_GD_HI22
2897 && the_insn
.reloc
<= BFD_RELOC_SPARC_TLS_TPOFF64
)
2899 error_message
= _(": TLS operand can't be a constant");
2903 /* Constants that won't fit are checked in md_apply_fix
2904 and bfd_install_relocation.
2905 ??? It would be preferable to install the constants
2906 into the insn here and save having to create a fixS
2907 for each one. There already exists code to handle
2908 all the various cases (e.g. in md_apply_fix and
2909 bfd_install_relocation) so duplicating all that code
2910 here isn't right. */
2912 /* This is a special case to handle cbcond instructions
2913 properly, which can need two relocations. The first
2914 one is for the 5-bit immediate field and the latter
2915 is going to be for the WDISP10 branch part. We
2916 handle the R_SPARC_5 immediate directly here so that
2917 we don't need to add support for multiple relocations
2918 in one instruction just yet. */
2919 if (the_insn
.reloc
== BFD_RELOC_SPARC_5
)
2921 valueT val
= the_insn
.exp
.X_add_number
;
2923 if (! in_bitfield_range (val
, 0x1f))
2925 error_message
= _(": Immediate value in cbcond is out of range.");
2928 opcode
|= val
& 0x1f;
2929 the_insn
.reloc
= BFD_RELOC_NONE
;
2950 if (! parse_keyword_arg (sparc_encode_asi
, &s
, &asi
))
2952 error_message
= _(": invalid ASI name");
2958 if (! parse_const_expr_arg (&s
, &asi
))
2960 error_message
= _(": invalid ASI expression");
2963 if (asi
< 0 || asi
> 255)
2965 error_message
= _(": invalid ASI number");
2969 opcode
|= ASI (asi
);
2971 } /* Alternate space. */
2974 if (strncmp (s
, "%psr", 4) == 0)
2981 case 'q': /* Floating point queue. */
2982 if (strncmp (s
, "%fq", 3) == 0)
2989 case 'Q': /* Coprocessor queue. */
2990 if (strncmp (s
, "%cq", 3) == 0)
2998 if (strcmp (str
, "set") == 0
2999 || strcmp (str
, "setuw") == 0)
3001 special_case
= SPECIAL_CASE_SET
;
3004 else if (strcmp (str
, "setsw") == 0)
3006 special_case
= SPECIAL_CASE_SETSW
;
3009 else if (strcmp (str
, "setx") == 0)
3011 special_case
= SPECIAL_CASE_SETX
;
3014 else if (strncmp (str
, "fdiv", 4) == 0)
3016 special_case
= SPECIAL_CASE_FDIV
;
3022 if (strncmp (s
, "%asi", 4) != 0)
3028 if (strncmp (s
, "%fprs", 5) != 0)
3034 if (strncmp (s
, "%mcdper",7) != 0)
3040 if (strncmp (s
, "%ccr", 4) != 0)
3046 if (strncmp (s
, "%tbr", 4) != 0)
3052 if (strncmp (s
, "%wim", 4) != 0)
3059 char *push
= input_line_pointer
;
3062 input_line_pointer
= s
;
3064 if (e
.X_op
== O_constant
)
3066 int n
= e
.X_add_number
;
3067 if (n
!= e
.X_add_number
|| (n
& ~0x1ff) != 0)
3068 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
3070 opcode
|= e
.X_add_number
<< 5;
3073 as_bad (_("non-immediate OPF operand, ignored"));
3074 s
= input_line_pointer
;
3075 input_line_pointer
= push
;
3080 if (strncmp (s
, "%y", 2) != 0)
3088 /* Parse a sparclet cpreg. */
3090 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg
, &s
, &cpreg
))
3092 error_message
= _(": invalid cpreg name");
3095 opcode
|= (*args
== 'U' ? RS1 (cpreg
) : RD (cpreg
));
3100 as_fatal (_("failed sanity check."));
3101 } /* switch on arg code. */
3103 /* Break out of for() loop. */
3105 } /* For each arg that we expect. */
3110 /* Args don't match. */
3111 if (&insn
[1] - sparc_opcodes
< sparc_num_opcodes
3112 && (insn
->name
== insn
[1].name
3113 || !strcmp (insn
->name
, insn
[1].name
)))
3121 as_bad (_("Illegal operands%s"), error_message
);
3122 return special_case
;
3127 /* We have a match. Now see if the architecture is OK. */
3128 int needed_arch_mask
= insn
->architecture
;
3130 = (((bfd_uint64_t
) insn
->hwcaps2
) << 32) | insn
->hwcaps
;
3132 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
3134 hwcap_seen
|= hwcaps
;
3139 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9
) - 1);
3140 if (! needed_arch_mask
)
3142 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9
);
3145 if (needed_arch_mask
3146 & SPARC_OPCODE_SUPPORTED (current_architecture
))
3149 /* Can we bump up the architecture? */
3150 else if (needed_arch_mask
3151 & SPARC_OPCODE_SUPPORTED (max_architecture
))
3153 enum sparc_opcode_arch_val needed_architecture
=
3154 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture
)
3155 & needed_arch_mask
);
3157 gas_assert (needed_architecture
<= SPARC_OPCODE_ARCH_MAX
);
3159 && needed_architecture
> warn_after_architecture
)
3161 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
3162 sparc_opcode_archs
[current_architecture
].name
,
3163 sparc_opcode_archs
[needed_architecture
].name
,
3165 warn_after_architecture
= needed_architecture
;
3167 current_architecture
= needed_architecture
;
3168 hwcap_allowed
|= hwcaps
;
3171 /* ??? This seems to be a bit fragile. What if the next entry in
3172 the opcode table is the one we want and it is supported?
3173 It is possible to arrange the table today so that this can't
3174 happen but what about tomorrow? */
3177 int arch
, printed_one_p
= 0;
3179 char required_archs
[SPARC_OPCODE_ARCH_MAX
* 16];
3181 /* Create a list of the architectures that support the insn. */
3182 needed_arch_mask
&= ~SPARC_OPCODE_SUPPORTED (max_architecture
);
3184 arch
= sparc_ffs (needed_arch_mask
);
3185 while ((1 << arch
) <= needed_arch_mask
)
3187 if ((1 << arch
) & needed_arch_mask
)
3191 strcpy (p
, sparc_opcode_archs
[arch
].name
);
3198 as_bad (_("Architecture mismatch on \"%s\"."), str
);
3199 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
3201 sparc_opcode_archs
[max_architecture
].name
);
3202 return special_case
;
3205 /* Make sure the hwcaps used by the instruction are
3206 currently enabled. */
3207 if (hwcaps
& ~hwcap_allowed
)
3209 const char *hwcap_name
= get_hwcap_name(hwcaps
& ~hwcap_allowed
);
3211 as_bad (_("Hardware capability \"%s\" not enabled for \"%s\"."),
3213 return special_case
;
3215 } /* If no match. */
3218 } /* Forever looking for a match. */
3220 the_insn
.opcode
= opcode
;
3221 return special_case
;
3224 /* Parse an argument that can be expressed as a keyword.
3225 (eg: #StoreStore or %ccfr).
3226 The result is a boolean indicating success.
3227 If successful, INPUT_POINTER is updated. */
3230 parse_keyword_arg (int (*lookup_fn
) (const char *),
3231 char **input_pointerP
,
3237 p
= *input_pointerP
;
3238 for (q
= p
+ (*p
== '#' || *p
== '%');
3239 ISALNUM (*q
) || *q
== '_';
3244 value
= (*lookup_fn
) (p
);
3249 *input_pointerP
= q
;
3253 /* Parse an argument that is a constant expression.
3254 The result is a boolean indicating success. */
3257 parse_const_expr_arg (char **input_pointerP
, int *valueP
)
3259 char *save
= input_line_pointer
;
3262 input_line_pointer
= *input_pointerP
;
3263 /* The next expression may be something other than a constant
3264 (say if we're not processing the right variant of the insn).
3265 Don't call expression unless we're sure it will succeed as it will
3266 signal an error (which we want to defer until later). */
3267 /* FIXME: It might be better to define md_operand and have it recognize
3268 things like %asi, etc. but continuing that route through to the end
3269 is a lot of work. */
3270 if (*input_line_pointer
== '%')
3272 input_line_pointer
= save
;
3276 *input_pointerP
= input_line_pointer
;
3277 input_line_pointer
= save
;
3278 if (exp
.X_op
!= O_constant
)
3280 *valueP
= exp
.X_add_number
;
3284 /* Subroutine of sparc_ip to parse an expression. */
3287 get_expression (char *str
)
3292 save_in
= input_line_pointer
;
3293 input_line_pointer
= str
;
3294 seg
= expression (&the_insn
.exp
);
3295 if (seg
!= absolute_section
3296 && seg
!= text_section
3297 && seg
!= data_section
3298 && seg
!= bss_section
3299 && seg
!= undefined_section
)
3301 the_insn
.error
= _("bad segment");
3302 expr_end
= input_line_pointer
;
3303 input_line_pointer
= save_in
;
3306 expr_end
= input_line_pointer
;
3307 input_line_pointer
= save_in
;
3311 /* Subroutine of md_assemble to output one insn. */
3314 output_insn (const struct sparc_opcode
*insn
, struct sparc_it
*theinsn
)
3316 char *toP
= frag_more (4);
3318 /* Put out the opcode. */
3319 if (INSN_BIG_ENDIAN
)
3320 number_to_chars_bigendian (toP
, (valueT
) theinsn
->opcode
, 4);
3322 number_to_chars_littleendian (toP
, (valueT
) theinsn
->opcode
, 4);
3324 /* Put out the symbol-dependent stuff. */
3325 if (theinsn
->reloc
!= BFD_RELOC_NONE
)
3327 fixS
*fixP
= fix_new_exp (frag_now
, /* Which frag. */
3328 (toP
- frag_now
->fr_literal
), /* Where. */
3333 /* Turn off overflow checking in fixup_segment. We'll do our
3334 own overflow checking in md_apply_fix. This is necessary because
3335 the insn size is 4 and fixup_segment will signal an overflow for
3336 large 8 byte quantities. */
3337 fixP
->fx_no_overflow
= 1;
3338 if (theinsn
->reloc
== BFD_RELOC_SPARC_OLO10
)
3339 fixP
->tc_fix_data
= theinsn
->exp2
.X_add_number
;
3343 last_opcode
= theinsn
->opcode
;
3346 dwarf2_emit_insn (4);
3351 md_atof (int type
, char *litP
, int *sizeP
)
3353 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
3356 /* Write a value out to the object file, using the appropriate
3360 md_number_to_chars (char *buf
, valueT val
, int n
)
3362 if (target_big_endian
)
3363 number_to_chars_bigendian (buf
, val
, n
);
3364 else if (target_little_endian_data
3365 && ((n
== 4 || n
== 2) && ~now_seg
->flags
& SEC_ALLOC
))
3366 /* Output debug words, which are not in allocated sections, as big
3368 number_to_chars_bigendian (buf
, val
, n
);
3369 else if (target_little_endian_data
|| ! target_big_endian
)
3370 number_to_chars_littleendian (buf
, val
, n
);
3373 /* Apply a fixS to the frags, now that we know the value it ought to
3377 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT segment ATTRIBUTE_UNUSED
)
3379 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
3380 offsetT val
= * (offsetT
*) valP
;
3383 gas_assert (fixP
->fx_r_type
< BFD_RELOC_UNUSED
);
3385 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc. */
3388 /* SPARC ELF relocations don't use an addend in the data field. */
3389 if (fixP
->fx_addsy
!= NULL
)
3391 switch (fixP
->fx_r_type
)
3393 case BFD_RELOC_SPARC_TLS_GD_HI22
:
3394 case BFD_RELOC_SPARC_TLS_GD_LO10
:
3395 case BFD_RELOC_SPARC_TLS_GD_ADD
:
3396 case BFD_RELOC_SPARC_TLS_GD_CALL
:
3397 case BFD_RELOC_SPARC_TLS_LDM_HI22
:
3398 case BFD_RELOC_SPARC_TLS_LDM_LO10
:
3399 case BFD_RELOC_SPARC_TLS_LDM_ADD
:
3400 case BFD_RELOC_SPARC_TLS_LDM_CALL
:
3401 case BFD_RELOC_SPARC_TLS_LDO_HIX22
:
3402 case BFD_RELOC_SPARC_TLS_LDO_LOX10
:
3403 case BFD_RELOC_SPARC_TLS_LDO_ADD
:
3404 case BFD_RELOC_SPARC_TLS_IE_HI22
:
3405 case BFD_RELOC_SPARC_TLS_IE_LO10
:
3406 case BFD_RELOC_SPARC_TLS_IE_LD
:
3407 case BFD_RELOC_SPARC_TLS_IE_LDX
:
3408 case BFD_RELOC_SPARC_TLS_IE_ADD
:
3409 case BFD_RELOC_SPARC_TLS_LE_HIX22
:
3410 case BFD_RELOC_SPARC_TLS_LE_LOX10
:
3411 case BFD_RELOC_SPARC_TLS_DTPMOD32
:
3412 case BFD_RELOC_SPARC_TLS_DTPMOD64
:
3413 case BFD_RELOC_SPARC_TLS_DTPOFF32
:
3414 case BFD_RELOC_SPARC_TLS_DTPOFF64
:
3415 case BFD_RELOC_SPARC_TLS_TPOFF32
:
3416 case BFD_RELOC_SPARC_TLS_TPOFF64
:
3417 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
3427 /* This is a hack. There should be a better way to
3428 handle this. Probably in terms of howto fields, once
3429 we can look at these fixups in terms of howtos. */
3430 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
&& fixP
->fx_addsy
)
3431 val
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3434 /* FIXME: More ridiculous gas reloc hacking. If we are going to
3435 generate a reloc, then we just want to let the reloc addend set
3436 the value. We do not want to also stuff the addend into the
3437 object file. Including the addend in the object file works when
3438 doing a static link, because the linker will ignore the object
3439 file contents. However, the dynamic linker does not ignore the
3440 object file contents. */
3441 if (fixP
->fx_addsy
!= NULL
3442 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
)
3445 /* When generating PIC code, we do not want an addend for a reloc
3446 against a local symbol. We adjust fx_addnumber to cancel out the
3447 value already included in val, and to also cancel out the
3448 adjustment which bfd_install_relocation will create. */
3450 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
3451 && fixP
->fx_addsy
!= NULL
3452 && ! S_IS_COMMON (fixP
->fx_addsy
)
3453 && symbol_section_p (fixP
->fx_addsy
))
3454 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
3456 /* When generating PIC code, we need to fiddle to get
3457 bfd_install_relocation to do the right thing for a PC relative
3458 reloc against a local symbol which we are going to keep. */
3460 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
3461 && fixP
->fx_addsy
!= NULL
3462 && (S_IS_EXTERNAL (fixP
->fx_addsy
)
3463 || S_IS_WEAK (fixP
->fx_addsy
))
3464 && S_IS_DEFINED (fixP
->fx_addsy
)
3465 && ! S_IS_COMMON (fixP
->fx_addsy
))
3468 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
3472 /* If this is a data relocation, just output VAL. */
3474 if (fixP
->fx_r_type
== BFD_RELOC_8
)
3476 md_number_to_chars (buf
, val
, 1);
3478 else if (fixP
->fx_r_type
== BFD_RELOC_16
3479 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA16
)
3481 md_number_to_chars (buf
, val
, 2);
3483 else if (fixP
->fx_r_type
== BFD_RELOC_32
3484 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA32
3485 || fixP
->fx_r_type
== BFD_RELOC_SPARC_REV32
)
3487 md_number_to_chars (buf
, val
, 4);
3489 else if (fixP
->fx_r_type
== BFD_RELOC_64
3490 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA64
)
3492 md_number_to_chars (buf
, val
, 8);
3494 else if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3495 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3502 /* It's a relocation against an instruction. */
3504 if (INSN_BIG_ENDIAN
)
3505 insn
= bfd_getb32 ((unsigned char *) buf
);
3507 insn
= bfd_getl32 ((unsigned char *) buf
);
3509 switch (fixP
->fx_r_type
)
3511 case BFD_RELOC_32_PCREL_S2
:
3513 /* FIXME: This increment-by-one deserves a comment of why it's
3515 if (! sparc_pic_code
3516 || fixP
->fx_addsy
== NULL
3517 || symbol_section_p (fixP
->fx_addsy
))
3520 insn
|= val
& 0x3fffffff;
3522 /* See if we have a delay slot. */
3523 if (sparc_relax
&& fixP
->fx_where
+ 8 <= fixP
->fx_frag
->fr_fix
)
3527 #define XCC (2 << 20)
3528 #define COND(x) (((x)&0xf)<<25)
3529 #define CONDA COND(0x8)
3530 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
3531 #define INSN_BA (F2(0,2) | CONDA)
3532 #define INSN_OR F3(2, 0x2, 0)
3533 #define INSN_NOP F2(0,4)
3537 /* If the instruction is a call with either:
3539 arithmetic instruction with rd == %o7
3540 where rs1 != %o7 and rs2 if it is register != %o7
3541 then we can optimize if the call destination is near
3542 by changing the call into a branch always. */
3543 if (INSN_BIG_ENDIAN
)
3544 delay
= bfd_getb32 ((unsigned char *) buf
+ 4);
3546 delay
= bfd_getl32 ((unsigned char *) buf
+ 4);
3547 if ((insn
& OP (~0)) != OP (1) || (delay
& OP (~0)) != OP (2))
3549 if ((delay
& OP3 (~0)) != OP3 (0x3d) /* Restore. */
3550 && ((delay
& OP3 (0x28)) != 0 /* Arithmetic. */
3551 || ((delay
& RD (~0)) != RD (O7
))))
3553 if ((delay
& RS1 (~0)) == RS1 (O7
)
3554 || ((delay
& F3I (~0)) == 0
3555 && (delay
& RS2 (~0)) == RS2 (O7
)))
3557 /* Ensure the branch will fit into simm22. */
3558 if ((val
& 0x3fe00000)
3559 && (val
& 0x3fe00000) != 0x3fe00000)
3561 /* Check if the arch is v9 and branch will fit
3563 if (((val
& 0x3c0000) == 0
3564 || (val
& 0x3c0000) == 0x3c0000)
3565 && (sparc_arch_size
== 64
3566 || current_architecture
>= SPARC_OPCODE_ARCH_V9
))
3568 insn
= INSN_BPA
| (val
& 0x7ffff);
3571 insn
= INSN_BA
| (val
& 0x3fffff);
3572 if (fixP
->fx_where
>= 4
3573 && ((delay
& (0xffffffff ^ RS1 (~0)))
3574 == (INSN_OR
| RD (O7
) | RS2 (G0
))))
3579 if (INSN_BIG_ENDIAN
)
3580 setter
= bfd_getb32 ((unsigned char *) buf
- 4);
3582 setter
= bfd_getl32 ((unsigned char *) buf
- 4);
3583 if ((setter
& (0xffffffff ^ RD (~0)))
3584 != (INSN_OR
| RS1 (O7
) | RS2 (G0
)))
3591 If call foo was replaced with ba, replace
3592 or %rN, %g0, %o7 with nop. */
3593 reg
= (delay
& RS1 (~0)) >> 14;
3594 if (reg
!= ((setter
& RD (~0)) >> 25)
3595 || reg
== G0
|| reg
== O7
)
3598 if (INSN_BIG_ENDIAN
)
3599 bfd_putb32 (INSN_NOP
, (unsigned char *) buf
+ 4);
3601 bfd_putl32 (INSN_NOP
, (unsigned char *) buf
+ 4);
3606 case BFD_RELOC_SPARC_11
:
3607 if (! in_signed_range (val
, 0x7ff))
3608 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3609 _("relocation overflow"));
3610 insn
|= val
& 0x7ff;
3613 case BFD_RELOC_SPARC_10
:
3614 if (! in_signed_range (val
, 0x3ff))
3615 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3616 _("relocation overflow"));
3617 insn
|= val
& 0x3ff;
3620 case BFD_RELOC_SPARC_7
:
3621 if (! in_bitfield_range (val
, 0x7f))
3622 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3623 _("relocation overflow"));
3627 case BFD_RELOC_SPARC_6
:
3628 if (! in_bitfield_range (val
, 0x3f))
3629 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3630 _("relocation overflow"));
3634 case BFD_RELOC_SPARC_5
:
3635 if (! in_bitfield_range (val
, 0x1f))
3636 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3637 _("relocation overflow"));
3641 case BFD_RELOC_SPARC_WDISP10
:
3644 || val
<= -(offsetT
) 0x808)
3645 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3646 _("relocation overflow"));
3647 /* FIXME: The +1 deserves a comment. */
3648 val
= (val
>> 2) + 1;
3649 insn
|= ((val
& 0x300) << 11)
3650 | ((val
& 0xff) << 5);
3653 case BFD_RELOC_SPARC_WDISP16
:
3656 || val
<= -(offsetT
) 0x20008)
3657 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3658 _("relocation overflow"));
3659 /* FIXME: The +1 deserves a comment. */
3660 val
= (val
>> 2) + 1;
3661 insn
|= ((val
& 0xc000) << 6) | (val
& 0x3fff);
3664 case BFD_RELOC_SPARC_WDISP19
:
3667 || val
<= -(offsetT
) 0x100008)
3668 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3669 _("relocation overflow"));
3670 /* FIXME: The +1 deserves a comment. */
3671 val
= (val
>> 2) + 1;
3672 insn
|= val
& 0x7ffff;
3675 case BFD_RELOC_SPARC_HH22
:
3676 val
= BSR (val
, 32);
3679 case BFD_RELOC_SPARC_LM22
:
3680 case BFD_RELOC_HI22
:
3681 if (!fixP
->fx_addsy
)
3682 insn
|= (val
>> 10) & 0x3fffff;
3684 /* FIXME: Need comment explaining why we do this. */
3688 case BFD_RELOC_SPARC22
:
3689 if (val
& ~0x003fffff)
3690 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3691 _("relocation overflow"));
3692 insn
|= (val
& 0x3fffff);
3695 case BFD_RELOC_SPARC_HM10
:
3696 val
= BSR (val
, 32);
3699 case BFD_RELOC_LO10
:
3700 if (!fixP
->fx_addsy
)
3701 insn
|= val
& 0x3ff;
3703 /* FIXME: Need comment explaining why we do this. */
3707 case BFD_RELOC_SPARC_OLO10
:
3709 val
+= fixP
->tc_fix_data
;
3712 case BFD_RELOC_SPARC13
:
3713 if (! in_signed_range (val
, 0x1fff))
3714 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3715 _("relocation overflow"));
3716 insn
|= val
& 0x1fff;
3719 case BFD_RELOC_SPARC_WDISP22
:
3720 val
= (val
>> 2) + 1;
3722 case BFD_RELOC_SPARC_BASE22
:
3723 insn
|= val
& 0x3fffff;
3726 case BFD_RELOC_SPARC_H34
:
3727 if (!fixP
->fx_addsy
)
3731 insn
|= tval
& 0x3fffff;
3735 case BFD_RELOC_SPARC_H44
:
3736 if (!fixP
->fx_addsy
)
3740 insn
|= tval
& 0x3fffff;
3744 case BFD_RELOC_SPARC_M44
:
3745 if (!fixP
->fx_addsy
)
3746 insn
|= (val
>> 12) & 0x3ff;
3749 case BFD_RELOC_SPARC_L44
:
3750 if (!fixP
->fx_addsy
)
3751 insn
|= val
& 0xfff;
3754 case BFD_RELOC_SPARC_HIX22
:
3755 if (!fixP
->fx_addsy
)
3757 val
^= ~(offsetT
) 0;
3758 insn
|= (val
>> 10) & 0x3fffff;
3762 case BFD_RELOC_SPARC_LOX10
:
3763 if (!fixP
->fx_addsy
)
3764 insn
|= 0x1c00 | (val
& 0x3ff);
3767 case BFD_RELOC_NONE
:
3769 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3770 _("bad or unhandled relocation type: 0x%02x"),
3775 if (INSN_BIG_ENDIAN
)
3776 bfd_putb32 (insn
, (unsigned char *) buf
);
3778 bfd_putl32 (insn
, (unsigned char *) buf
);
3781 /* Are we finished with this relocation now? */
3782 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
3786 /* Translate internal representation of relocation info to BFD target
3790 tc_gen_reloc (asection
*section
, fixS
*fixp
)
3792 static arelent
*relocs
[3];
3794 bfd_reloc_code_real_type code
;
3796 relocs
[0] = reloc
= XNEW (arelent
);
3799 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
3800 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3801 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3803 switch (fixp
->fx_r_type
)
3807 case BFD_RELOC_HI22
:
3808 case BFD_RELOC_LO10
:
3809 case BFD_RELOC_32_PCREL_S2
:
3810 case BFD_RELOC_SPARC13
:
3811 case BFD_RELOC_SPARC22
:
3812 case BFD_RELOC_SPARC_PC22
:
3813 case BFD_RELOC_SPARC_PC10
:
3814 case BFD_RELOC_SPARC_BASE13
:
3815 case BFD_RELOC_SPARC_WDISP10
:
3816 case BFD_RELOC_SPARC_WDISP16
:
3817 case BFD_RELOC_SPARC_WDISP19
:
3818 case BFD_RELOC_SPARC_WDISP22
:
3820 case BFD_RELOC_SPARC_5
:
3821 case BFD_RELOC_SPARC_6
:
3822 case BFD_RELOC_SPARC_7
:
3823 case BFD_RELOC_SPARC_10
:
3824 case BFD_RELOC_SPARC_11
:
3825 case BFD_RELOC_SPARC_HH22
:
3826 case BFD_RELOC_SPARC_HM10
:
3827 case BFD_RELOC_SPARC_LM22
:
3828 case BFD_RELOC_SPARC_PC_HH22
:
3829 case BFD_RELOC_SPARC_PC_HM10
:
3830 case BFD_RELOC_SPARC_PC_LM22
:
3831 case BFD_RELOC_SPARC_H34
:
3832 case BFD_RELOC_SPARC_H44
:
3833 case BFD_RELOC_SPARC_M44
:
3834 case BFD_RELOC_SPARC_L44
:
3835 case BFD_RELOC_SPARC_HIX22
:
3836 case BFD_RELOC_SPARC_LOX10
:
3837 case BFD_RELOC_SPARC_REV32
:
3838 case BFD_RELOC_SPARC_OLO10
:
3839 case BFD_RELOC_SPARC_UA16
:
3840 case BFD_RELOC_SPARC_UA32
:
3841 case BFD_RELOC_SPARC_UA64
:
3842 case BFD_RELOC_8_PCREL
:
3843 case BFD_RELOC_16_PCREL
:
3844 case BFD_RELOC_32_PCREL
:
3845 case BFD_RELOC_64_PCREL
:
3846 case BFD_RELOC_SPARC_PLT32
:
3847 case BFD_RELOC_SPARC_PLT64
:
3848 case BFD_RELOC_VTABLE_ENTRY
:
3849 case BFD_RELOC_VTABLE_INHERIT
:
3850 case BFD_RELOC_SPARC_TLS_GD_HI22
:
3851 case BFD_RELOC_SPARC_TLS_GD_LO10
:
3852 case BFD_RELOC_SPARC_TLS_GD_ADD
:
3853 case BFD_RELOC_SPARC_TLS_GD_CALL
:
3854 case BFD_RELOC_SPARC_TLS_LDM_HI22
:
3855 case BFD_RELOC_SPARC_TLS_LDM_LO10
:
3856 case BFD_RELOC_SPARC_TLS_LDM_ADD
:
3857 case BFD_RELOC_SPARC_TLS_LDM_CALL
:
3858 case BFD_RELOC_SPARC_TLS_LDO_HIX22
:
3859 case BFD_RELOC_SPARC_TLS_LDO_LOX10
:
3860 case BFD_RELOC_SPARC_TLS_LDO_ADD
:
3861 case BFD_RELOC_SPARC_TLS_IE_HI22
:
3862 case BFD_RELOC_SPARC_TLS_IE_LO10
:
3863 case BFD_RELOC_SPARC_TLS_IE_LD
:
3864 case BFD_RELOC_SPARC_TLS_IE_LDX
:
3865 case BFD_RELOC_SPARC_TLS_IE_ADD
:
3866 case BFD_RELOC_SPARC_TLS_LE_HIX22
:
3867 case BFD_RELOC_SPARC_TLS_LE_LOX10
:
3868 case BFD_RELOC_SPARC_TLS_DTPOFF32
:
3869 case BFD_RELOC_SPARC_TLS_DTPOFF64
:
3870 case BFD_RELOC_SPARC_GOTDATA_OP_HIX22
:
3871 case BFD_RELOC_SPARC_GOTDATA_OP_LOX10
:
3872 case BFD_RELOC_SPARC_GOTDATA_OP
:
3873 code
= fixp
->fx_r_type
;
3880 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
3881 /* If we are generating PIC code, we need to generate a different
3885 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3887 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
3890 #define GOTT_BASE "__GOTT_BASE__"
3891 #define GOTT_INDEX "__GOTT_INDEX__"
3894 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */
3900 case BFD_RELOC_32_PCREL_S2
:
3901 if (generic_force_reloc (fixp
))
3902 code
= BFD_RELOC_SPARC_WPLT30
;
3904 case BFD_RELOC_HI22
:
3905 code
= BFD_RELOC_SPARC_GOT22
;
3906 if (fixp
->fx_addsy
!= NULL
)
3908 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
3909 code
= BFD_RELOC_SPARC_PC22
;
3911 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_BASE
) == 0
3912 || strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_INDEX
) == 0)
3913 code
= BFD_RELOC_HI22
; /* Unchanged. */
3917 case BFD_RELOC_LO10
:
3918 code
= BFD_RELOC_SPARC_GOT10
;
3919 if (fixp
->fx_addsy
!= NULL
)
3921 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
3922 code
= BFD_RELOC_SPARC_PC10
;
3924 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_BASE
) == 0
3925 || strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_INDEX
) == 0)
3926 code
= BFD_RELOC_LO10
; /* Unchanged. */
3930 case BFD_RELOC_SPARC13
:
3931 code
= BFD_RELOC_SPARC_GOT13
;
3937 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
3939 /* Nothing is aligned in DWARF debugging sections. */
3940 if (bfd_get_section_flags (stdoutput
, section
) & SEC_DEBUGGING
)
3943 case BFD_RELOC_16
: code
= BFD_RELOC_SPARC_UA16
; break;
3944 case BFD_RELOC_32
: code
= BFD_RELOC_SPARC_UA32
; break;
3945 case BFD_RELOC_64
: code
= BFD_RELOC_SPARC_UA64
; break;
3949 if (code
== BFD_RELOC_SPARC_OLO10
)
3950 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO10
);
3952 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
3953 if (reloc
->howto
== 0)
3955 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3956 _("internal error: can't export reloc type %d (`%s')"),
3957 fixp
->fx_r_type
, bfd_get_reloc_code_name (code
));
3963 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
3966 if (reloc
->howto
->pc_relative
== 0
3967 || code
== BFD_RELOC_SPARC_PC10
3968 || code
== BFD_RELOC_SPARC_PC22
)
3969 reloc
->addend
= fixp
->fx_addnumber
;
3970 else if (sparc_pic_code
3971 && fixp
->fx_r_type
== BFD_RELOC_32_PCREL_S2
3972 && fixp
->fx_addsy
!= NULL
3973 && (S_IS_EXTERNAL (fixp
->fx_addsy
)
3974 || S_IS_WEAK (fixp
->fx_addsy
))
3975 && S_IS_DEFINED (fixp
->fx_addsy
)
3976 && ! S_IS_COMMON (fixp
->fx_addsy
))
3977 reloc
->addend
= fixp
->fx_addnumber
;
3979 reloc
->addend
= fixp
->fx_offset
- reloc
->address
;
3981 #else /* elf or coff */
3983 if (code
!= BFD_RELOC_32_PCREL_S2
3984 && code
!= BFD_RELOC_SPARC_WDISP22
3985 && code
!= BFD_RELOC_SPARC_WDISP16
3986 && code
!= BFD_RELOC_SPARC_WDISP19
3987 && code
!= BFD_RELOC_SPARC_WDISP10
3988 && code
!= BFD_RELOC_SPARC_WPLT30
3989 && code
!= BFD_RELOC_SPARC_TLS_GD_CALL
3990 && code
!= BFD_RELOC_SPARC_TLS_LDM_CALL
)
3991 reloc
->addend
= fixp
->fx_addnumber
;
3992 else if (symbol_section_p (fixp
->fx_addsy
))
3993 reloc
->addend
= (section
->vma
3994 + fixp
->fx_addnumber
3995 + md_pcrel_from (fixp
));
3997 reloc
->addend
= fixp
->fx_offset
;
4000 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
4001 on the same location. */
4002 if (code
== BFD_RELOC_SPARC_OLO10
)
4004 relocs
[1] = reloc
= XNEW (arelent
);
4007 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
4009 = symbol_get_bfdsym (section_symbol (absolute_section
));
4010 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4011 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_SPARC13
);
4012 reloc
->addend
= fixp
->tc_fix_data
;
4018 /* We have no need to default values of symbols. */
4021 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
4026 /* Round up a section size to the appropriate boundary. */
4029 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
4032 /* This is not right for ELF; a.out wants it, and COFF will force
4033 the alignment anyways. */
4034 valueT align
= ((valueT
) 1
4035 << (valueT
) bfd_get_section_alignment (stdoutput
, segment
));
4038 /* Turn alignment value into a mask. */
4040 newsize
= (size
+ align
) & ~align
;
4047 /* Exactly what point is a PC-relative offset relative TO?
4048 On the sparc, they're relative to the address of the offset, plus
4049 its size. This gets us to the following instruction.
4050 (??? Is this right? FIXME-SOON) */
4052 md_pcrel_from (fixS
*fixP
)
4056 ret
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4057 if (! sparc_pic_code
4058 || fixP
->fx_addsy
== NULL
4059 || symbol_section_p (fixP
->fx_addsy
))
4060 ret
+= fixP
->fx_size
;
4064 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
4075 for (shift
= 0; (value
& 1) == 0; value
>>= 1)
4078 return (value
== 1) ? shift
: -1;
4081 /* Sort of like s_lcomm. */
4084 static int max_alignment
= 15;
4088 s_reserve (int ignore ATTRIBUTE_UNUSED
)
4098 c
= get_symbol_name (&name
);
4099 p
= input_line_pointer
;
4101 SKIP_WHITESPACE_AFTER_NAME ();
4103 if (*input_line_pointer
!= ',')
4105 as_bad (_("Expected comma after name"));
4106 ignore_rest_of_line ();
4110 ++input_line_pointer
;
4112 if ((size
= get_absolute_expression ()) < 0)
4114 as_bad (_("BSS length (%d.) <0! Ignored."), size
);
4115 ignore_rest_of_line ();
4120 symbolP
= symbol_find_or_make (name
);
4123 if (strncmp (input_line_pointer
, ",\"bss\"", 6) != 0
4124 && strncmp (input_line_pointer
, ",\".bss\"", 7) != 0)
4126 as_bad (_("bad .reserve segment -- expected BSS segment"));
4130 if (input_line_pointer
[2] == '.')
4131 input_line_pointer
+= 7;
4133 input_line_pointer
+= 6;
4136 if (*input_line_pointer
== ',')
4138 ++input_line_pointer
;
4141 if (*input_line_pointer
== '\n')
4143 as_bad (_("missing alignment"));
4144 ignore_rest_of_line ();
4148 align
= (int) get_absolute_expression ();
4151 if (align
> max_alignment
)
4153 align
= max_alignment
;
4154 as_warn (_("alignment too large; assuming %d"), align
);
4160 as_bad (_("negative alignment"));
4161 ignore_rest_of_line ();
4167 temp
= mylog2 (align
);
4170 as_bad (_("alignment not a power of 2"));
4171 ignore_rest_of_line ();
4178 record_alignment (bss_section
, align
);
4183 if (!S_IS_DEFINED (symbolP
)
4185 && S_GET_OTHER (symbolP
) == 0
4186 && S_GET_DESC (symbolP
) == 0
4193 segT current_seg
= now_seg
;
4194 subsegT current_subseg
= now_subseg
;
4196 /* Switch to bss. */
4197 subseg_set (bss_section
, 1);
4201 frag_align (align
, 0, 0);
4203 /* Detach from old frag. */
4204 if (S_GET_SEGMENT (symbolP
) == bss_section
)
4205 symbol_get_frag (symbolP
)->fr_symbol
= NULL
;
4207 symbol_set_frag (symbolP
, frag_now
);
4208 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
4209 (offsetT
) size
, (char *) 0);
4212 S_SET_SEGMENT (symbolP
, bss_section
);
4214 subseg_set (current_seg
, current_subseg
);
4217 S_SET_SIZE (symbolP
, size
);
4223 as_warn (_("Ignoring attempt to re-define symbol %s"),
4224 S_GET_NAME (symbolP
));
4227 demand_empty_rest_of_line ();
4231 s_common (int ignore ATTRIBUTE_UNUSED
)
4239 c
= get_symbol_name (&name
);
4240 /* Just after name is now '\0'. */
4241 p
= input_line_pointer
;
4243 SKIP_WHITESPACE_AFTER_NAME ();
4244 if (*input_line_pointer
!= ',')
4246 as_bad (_("Expected comma after symbol-name"));
4247 ignore_rest_of_line ();
4252 input_line_pointer
++;
4254 if ((temp
= get_absolute_expression ()) < 0)
4256 as_bad (_(".COMMon length (%lu) out of range ignored"),
4257 (unsigned long) temp
);
4258 ignore_rest_of_line ();
4263 symbolP
= symbol_find_or_make (name
);
4265 if (S_IS_DEFINED (symbolP
) && ! S_IS_COMMON (symbolP
))
4267 as_bad (_("Ignoring attempt to re-define symbol"));
4268 ignore_rest_of_line ();
4271 if (S_GET_VALUE (symbolP
) != 0)
4273 if (S_GET_VALUE (symbolP
) != (valueT
) size
)
4275 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."),
4276 S_GET_NAME (symbolP
), (long) S_GET_VALUE (symbolP
), (long) size
);
4282 S_SET_VALUE (symbolP
, (valueT
) size
);
4283 S_SET_EXTERNAL (symbolP
);
4286 know (symbol_get_frag (symbolP
) == &zero_address_frag
);
4287 if (*input_line_pointer
!= ',')
4289 as_bad (_("Expected comma after common length"));
4290 ignore_rest_of_line ();
4293 input_line_pointer
++;
4295 if (*input_line_pointer
!= '"')
4297 temp
= get_absolute_expression ();
4300 if (temp
> max_alignment
)
4302 temp
= max_alignment
;
4303 as_warn (_("alignment too large; assuming %ld"), (long) temp
);
4309 as_bad (_("negative alignment"));
4310 ignore_rest_of_line ();
4315 if (symbol_get_obj (symbolP
)->local
)
4322 old_subsec
= now_subseg
;
4327 align
= mylog2 (temp
);
4331 as_bad (_("alignment not a power of 2"));
4332 ignore_rest_of_line ();
4336 record_alignment (bss_section
, align
);
4337 subseg_set (bss_section
, 0);
4339 frag_align (align
, 0, 0);
4340 if (S_GET_SEGMENT (symbolP
) == bss_section
)
4341 symbol_get_frag (symbolP
)->fr_symbol
= 0;
4342 symbol_set_frag (symbolP
, frag_now
);
4343 p
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
4344 (offsetT
) size
, (char *) 0);
4346 S_SET_SEGMENT (symbolP
, bss_section
);
4347 S_CLEAR_EXTERNAL (symbolP
);
4348 S_SET_SIZE (symbolP
, size
);
4349 subseg_set (old_sec
, old_subsec
);
4352 #endif /* OBJ_ELF */
4355 S_SET_VALUE (symbolP
, (valueT
) size
);
4357 S_SET_ALIGN (symbolP
, temp
);
4358 S_SET_SIZE (symbolP
, size
);
4360 S_SET_EXTERNAL (symbolP
);
4361 S_SET_SEGMENT (symbolP
, bfd_com_section_ptr
);
4366 input_line_pointer
++;
4367 /* @@ Some use the dot, some don't. Can we get some consistency?? */
4368 if (*input_line_pointer
== '.')
4369 input_line_pointer
++;
4370 /* @@ Some say data, some say bss. */
4371 if (strncmp (input_line_pointer
, "bss\"", 4)
4372 && strncmp (input_line_pointer
, "data\"", 5))
4374 while (*--input_line_pointer
!= '"')
4376 input_line_pointer
--;
4377 goto bad_common_segment
;
4379 while (*input_line_pointer
++ != '"')
4381 goto allocate_common
;
4384 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
4386 demand_empty_rest_of_line ();
4391 p
= input_line_pointer
;
4392 while (*p
&& *p
!= '\n')
4396 as_bad (_("bad .common segment %s"), input_line_pointer
+ 1);
4398 input_line_pointer
= p
;
4399 ignore_rest_of_line ();
4404 /* Handle the .empty pseudo-op. This suppresses the warnings about
4405 invalid delay slot usage. */
4408 s_empty (int ignore ATTRIBUTE_UNUSED
)
4410 /* The easy way to implement is to just forget about the last
4416 s_seg (int ignore ATTRIBUTE_UNUSED
)
4419 if (strncmp (input_line_pointer
, "\"text\"", 6) == 0)
4421 input_line_pointer
+= 6;
4425 if (strncmp (input_line_pointer
, "\"data\"", 6) == 0)
4427 input_line_pointer
+= 6;
4431 if (strncmp (input_line_pointer
, "\"data1\"", 7) == 0)
4433 input_line_pointer
+= 7;
4437 if (strncmp (input_line_pointer
, "\"bss\"", 5) == 0)
4439 input_line_pointer
+= 5;
4440 /* We only support 2 segments -- text and data -- for now, so
4441 things in the "bss segment" will have to go into data for now.
4442 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
4443 subseg_set (data_section
, 255); /* FIXME-SOMEDAY. */
4446 as_bad (_("Unknown segment type"));
4447 demand_empty_rest_of_line ();
4453 subseg_set (data_section
, 1);
4454 demand_empty_rest_of_line ();
4458 s_proc (int ignore ATTRIBUTE_UNUSED
)
4460 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
4462 ++input_line_pointer
;
4464 ++input_line_pointer
;
4467 /* This static variable is set by s_uacons to tell sparc_cons_align
4468 that the expression does not need to be aligned. */
4470 static int sparc_no_align_cons
= 0;
4472 /* This handles the unaligned space allocation pseudo-ops, such as
4473 .uaword. .uaword is just like .word, but the value does not need
4477 s_uacons (int bytes
)
4479 /* Tell sparc_cons_align not to align this value. */
4480 sparc_no_align_cons
= 1;
4482 sparc_no_align_cons
= 0;
4485 /* This handles the native word allocation pseudo-op .nword.
4486 For sparc_arch_size 32 it is equivalent to .word, for
4487 sparc_arch_size 64 it is equivalent to .xword. */
4490 s_ncons (int bytes ATTRIBUTE_UNUSED
)
4492 cons (sparc_arch_size
== 32 ? 4 : 8);
4496 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
4500 .register %g[2367],{#scratch|symbolname|#ignore}
4504 s_register (int ignore ATTRIBUTE_UNUSED
)
4511 if (input_line_pointer
[0] != '%'
4512 || input_line_pointer
[1] != 'g'
4513 || ((input_line_pointer
[2] & ~1) != '2'
4514 && (input_line_pointer
[2] & ~1) != '6')
4515 || input_line_pointer
[3] != ',')
4516 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4517 reg
= input_line_pointer
[2] - '0';
4518 input_line_pointer
+= 4;
4520 if (*input_line_pointer
== '#')
4522 ++input_line_pointer
;
4523 c
= get_symbol_name (®name
);
4524 if (strcmp (regname
, "scratch") && strcmp (regname
, "ignore"))
4525 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4526 if (regname
[0] == 'i')
4529 regname
= (char *) "";
4533 c
= get_symbol_name (®name
);
4536 if (sparc_arch_size
== 64)
4540 if ((regname
&& globals
[reg
] != (symbolS
*) 1
4541 && strcmp (S_GET_NAME (globals
[reg
]), regname
))
4542 || ((regname
!= NULL
) ^ (globals
[reg
] != (symbolS
*) 1)))
4543 as_bad (_("redefinition of global register"));
4547 if (regname
== NULL
)
4548 globals
[reg
] = (symbolS
*) 1;
4553 if (symbol_find (regname
))
4554 as_bad (_("Register symbol %s already defined."),
4557 globals
[reg
] = symbol_make (regname
);
4558 flags
= symbol_get_bfdsym (globals
[reg
])->flags
;
4560 flags
= flags
& ~(BSF_GLOBAL
|BSF_LOCAL
|BSF_WEAK
);
4561 if (! (flags
& (BSF_GLOBAL
|BSF_LOCAL
|BSF_WEAK
)))
4562 flags
|= BSF_GLOBAL
;
4563 symbol_get_bfdsym (globals
[reg
])->flags
= flags
;
4564 S_SET_VALUE (globals
[reg
], (valueT
) reg
);
4565 S_SET_ALIGN (globals
[reg
], reg
);
4566 S_SET_SIZE (globals
[reg
], 0);
4567 /* Although we actually want undefined_section here,
4568 we have to use absolute_section, because otherwise
4569 generic as code will make it a COM section.
4570 We fix this up in sparc_adjust_symtab. */
4571 S_SET_SEGMENT (globals
[reg
], absolute_section
);
4572 S_SET_OTHER (globals
[reg
], 0);
4573 elf_symbol (symbol_get_bfdsym (globals
[reg
]))
4574 ->internal_elf_sym
.st_info
=
4575 ELF_ST_INFO(STB_GLOBAL
, STT_REGISTER
);
4576 elf_symbol (symbol_get_bfdsym (globals
[reg
]))
4577 ->internal_elf_sym
.st_shndx
= SHN_UNDEF
;
4582 (void) restore_line_pointer (c
);
4584 demand_empty_rest_of_line ();
4587 /* Adjust the symbol table. We set undefined sections for STT_REGISTER
4588 symbols which need it. */
4591 sparc_adjust_symtab (void)
4595 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
4597 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym
))
4598 ->internal_elf_sym
.st_info
) != STT_REGISTER
)
4601 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym
))
4602 ->internal_elf_sym
.st_shndx
!= SHN_UNDEF
))
4605 S_SET_SEGMENT (sym
, undefined_section
);
4610 /* If the --enforce-aligned-data option is used, we require .word,
4611 et. al., to be aligned correctly. We do it by setting up an
4612 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
4613 no unexpected alignment was introduced.
4615 The SunOS and Solaris native assemblers enforce aligned data by
4616 default. We don't want to do that, because gcc can deliberately
4617 generate misaligned data if the packed attribute is used. Instead,
4618 we permit misaligned data by default, and permit the user to set an
4619 option to check for it. */
4622 sparc_cons_align (int nbytes
)
4626 /* Only do this if we are enforcing aligned data. */
4627 if (! enforce_aligned_data
)
4630 /* Don't align if this is an unaligned pseudo-op. */
4631 if (sparc_no_align_cons
)
4634 nalign
= mylog2 (nbytes
);
4638 gas_assert (nalign
> 0);
4640 if (now_seg
== absolute_section
)
4642 if ((abs_section_offset
& ((1 << nalign
) - 1)) != 0)
4643 as_bad (_("misaligned data"));
4647 frag_var (rs_align_test
, 1, 1, (relax_substateT
) 0,
4648 (symbolS
*) NULL
, (offsetT
) nalign
, (char *) NULL
);
4650 record_alignment (now_seg
, nalign
);
4653 /* This is called from HANDLE_ALIGN in tc-sparc.h. */
4656 sparc_handle_align (fragS
*fragp
)
4661 count
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
4663 switch (fragp
->fr_type
)
4667 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("misaligned data"));
4671 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
4682 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
) && count
> 8)
4684 unsigned wval
= (0x30680000 | count
>> 2); /* ba,a,pt %xcc, 1f */
4685 if (INSN_BIG_ENDIAN
)
4686 number_to_chars_bigendian (p
, wval
, 4);
4688 number_to_chars_littleendian (p
, wval
, 4);
4694 if (INSN_BIG_ENDIAN
)
4695 number_to_chars_bigendian (p
, 0x01000000, 4);
4697 number_to_chars_littleendian (p
, 0x01000000, 4);
4699 fragp
->fr_fix
+= fix
;
4709 /* Some special processing for a Sparc ELF file. */
4712 sparc_elf_final_processing (void)
4714 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4715 sort of BFD interface for this. */
4716 if (sparc_arch_size
== 64)
4718 switch (sparc_memory_model
)
4721 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_RMO
;
4724 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_PSO
;
4730 else if (current_architecture
>= SPARC_OPCODE_ARCH_V9
)
4731 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_32PLUS
;
4732 if (current_architecture
== SPARC_OPCODE_ARCH_V9A
)
4733 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_SUN_US1
;
4734 else if (current_architecture
== SPARC_OPCODE_ARCH_V9B
)
4735 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_SUN_US1
|EF_SPARC_SUN_US3
;
4739 sparc_cons (expressionS
*exp
, int size
)
4742 const char *sparc_cons_special_reloc
= NULL
;
4745 save
= input_line_pointer
;
4746 if (input_line_pointer
[0] == '%'
4747 && input_line_pointer
[1] == 'r'
4748 && input_line_pointer
[2] == '_')
4750 if (strncmp (input_line_pointer
+ 3, "disp", 4) == 0)
4752 input_line_pointer
+= 7;
4753 sparc_cons_special_reloc
= "disp";
4755 else if (strncmp (input_line_pointer
+ 3, "plt", 3) == 0)
4757 if (size
!= 4 && size
!= 8)
4758 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size
);
4761 input_line_pointer
+= 6;
4762 sparc_cons_special_reloc
= "plt";
4765 else if (strncmp (input_line_pointer
+ 3, "tls_dtpoff", 10) == 0)
4767 if (size
!= 4 && size
!= 8)
4768 as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size
);
4771 input_line_pointer
+= 13;
4772 sparc_cons_special_reloc
= "tls_dtpoff";
4775 if (sparc_cons_special_reloc
)
4782 if (*input_line_pointer
!= '8')
4784 input_line_pointer
--;
4787 if (input_line_pointer
[0] != '1' || input_line_pointer
[1] != '6')
4791 if (input_line_pointer
[0] != '3' || input_line_pointer
[1] != '2')
4795 if (input_line_pointer
[0] != '6' || input_line_pointer
[1] != '4')
4805 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"),
4806 sparc_cons_special_reloc
, size
* 8, size
);
4810 input_line_pointer
+= 2;
4811 if (*input_line_pointer
!= '(')
4813 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4814 sparc_cons_special_reloc
, size
* 8);
4821 input_line_pointer
= save
;
4822 sparc_cons_special_reloc
= NULL
;
4827 char *end
= ++input_line_pointer
;
4830 while (! is_end_of_line
[(c
= *end
)])
4844 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4845 sparc_cons_special_reloc
, size
* 8);
4851 if (input_line_pointer
!= end
)
4853 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4854 sparc_cons_special_reloc
, size
* 8);
4858 input_line_pointer
++;
4860 c
= *input_line_pointer
;
4861 if (! is_end_of_line
[c
] && c
!= ',')
4862 as_bad (_("Illegal operands: garbage after %%r_%s%d()"),
4863 sparc_cons_special_reloc
, size
* 8);
4869 if (sparc_cons_special_reloc
== NULL
)
4871 return sparc_cons_special_reloc
;
4876 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4877 reloc for a cons. We could use the definition there, except that
4878 we want to handle little endian relocs specially. */
4881 cons_fix_new_sparc (fragS
*frag
,
4883 unsigned int nbytes
,
4885 const char *sparc_cons_special_reloc
)
4887 bfd_reloc_code_real_type r
;
4889 r
= (nbytes
== 1 ? BFD_RELOC_8
:
4890 (nbytes
== 2 ? BFD_RELOC_16
:
4891 (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
4893 if (target_little_endian_data
4895 && now_seg
->flags
& SEC_ALLOC
)
4896 r
= BFD_RELOC_SPARC_REV32
;
4898 if (sparc_cons_special_reloc
)
4900 if (*sparc_cons_special_reloc
== 'd')
4903 case 1: r
= BFD_RELOC_8_PCREL
; break;
4904 case 2: r
= BFD_RELOC_16_PCREL
; break;
4905 case 4: r
= BFD_RELOC_32_PCREL
; break;
4906 case 8: r
= BFD_RELOC_64_PCREL
; break;
4909 else if (*sparc_cons_special_reloc
== 'p')
4912 case 4: r
= BFD_RELOC_SPARC_PLT32
; break;
4913 case 8: r
= BFD_RELOC_SPARC_PLT64
; break;
4918 case 4: r
= BFD_RELOC_SPARC_TLS_DTPOFF32
; break;
4919 case 8: r
= BFD_RELOC_SPARC_TLS_DTPOFF64
; break;
4922 else if (sparc_no_align_cons
)
4926 case 2: r
= BFD_RELOC_SPARC_UA16
; break;
4927 case 4: r
= BFD_RELOC_SPARC_UA32
; break;
4928 case 8: r
= BFD_RELOC_SPARC_UA64
; break;
4933 fix_new_exp (frag
, where
, (int) nbytes
, exp
, 0, r
);
4937 sparc_cfi_frame_initial_instructions (void)
4939 cfi_add_CFA_def_cfa (14, sparc_arch_size
== 64 ? 0x7ff : 0);
4943 sparc_regname_to_dw2regnum (char *regname
)
4953 case 'g': i
= 0; break;
4954 case 'o': i
= 1; break;
4955 case 'l': i
= 2; break;
4956 case 'i': i
= 3; break;
4957 default: i
= -1; break;
4961 if (regname
[1] < '0' || regname
[1] > '8' || regname
[2])
4963 return i
* 8 + regname
[1] - '0';
4965 if (regname
[0] == 's' && regname
[1] == 'p' && !regname
[2])
4967 if (regname
[0] == 'f' && regname
[1] == 'p' && !regname
[2])
4969 if (regname
[0] == 'f' || regname
[0] == 'r')
4971 unsigned int regnum
;
4973 regnum
= strtoul (regname
+ 1, &q
, 10);
4974 if (q
== NULL
|| *q
)
4976 if (regnum
>= ((regname
[0] == 'f'
4977 && SPARC_OPCODE_ARCH_V9_P (max_architecture
))
4980 if (regname
[0] == 'f')
4983 if (regnum
>= 64 && (regnum
& 1))
4992 sparc_cfi_emit_pcrel_expr (expressionS
*exp
, unsigned int nbytes
)
4994 sparc_no_align_cons
= 1;
4995 emit_expr_with_reloc (exp
, nbytes
, "disp");
4996 sparc_no_align_cons
= 0;