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[binutils-gdb.git] / gas / config / tc-sparc.c
1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright (C) 1989, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000
3 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public
17 License along with GAS; see the file COPYING. If not, write
18 to the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
20
21 #include <stdio.h>
22 #include <ctype.h>
23
24 #include "as.h"
25 #include "subsegs.h"
26
27 #include "opcode/sparc.h"
28
29 #ifdef OBJ_ELF
30 #include "elf/sparc.h"
31 #endif
32
33 static struct sparc_arch *lookup_arch PARAMS ((char *));
34 static void init_default_arch PARAMS ((void));
35 static int sparc_ip PARAMS ((char *, const struct sparc_opcode **));
36 static int in_signed_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
37 static int in_unsigned_range PARAMS ((bfd_vma, bfd_vma));
38 static int in_bitfield_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
39 static int sparc_ffs PARAMS ((unsigned int));
40 static void synthetize_setuw PARAMS ((const struct sparc_opcode *));
41 static void synthetize_setsw PARAMS ((const struct sparc_opcode *));
42 static void synthetize_setx PARAMS ((const struct sparc_opcode *));
43 static bfd_vma BSR PARAMS ((bfd_vma, int));
44 static int cmp_reg_entry PARAMS ((const PTR, const PTR));
45 static int parse_keyword_arg PARAMS ((int (*) (const char *), char **, int *));
46 static int parse_const_expr_arg PARAMS ((char **, int *));
47 static int get_expression PARAMS ((char *str));
48
49 /* Default architecture. */
50 /* ??? The default value should be V8, but sparclite support was added
51 by making it the default. GCC now passes -Asparclite, so maybe sometime in
52 the future we can set this to V8. */
53 #ifndef DEFAULT_ARCH
54 #define DEFAULT_ARCH "sparclite"
55 #endif
56 static char *default_arch = DEFAULT_ARCH;
57
58 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
59 have been set. */
60 static int default_init_p;
61
62 /* Current architecture. We don't bump up unless necessary. */
63 static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6;
64
65 /* The maximum architecture level we can bump up to.
66 In a 32 bit environment, don't allow bumping up to v9 by default.
67 The native assembler works this way. The user is required to pass
68 an explicit argument before we'll create v9 object files. However, if
69 we don't see any v9 insns, a v8plus object file is not created. */
70 static enum sparc_opcode_arch_val max_architecture;
71
72 /* Either 32 or 64, selects file format. */
73 static int sparc_arch_size;
74 /* Initial (default) value, recorded separately in case a user option
75 changes the value before md_show_usage is called. */
76 static int default_arch_size;
77
78 #ifdef OBJ_ELF
79 /* The currently selected v9 memory model. Currently only used for
80 ELF. */
81 static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO;
82 #endif
83
84 static int architecture_requested;
85 static int warn_on_bump;
86
87 /* If warn_on_bump and the needed architecture is higher than this
88 architecture, issue a warning. */
89 static enum sparc_opcode_arch_val warn_after_architecture;
90
91 /* Non-zero if as should generate error if an undeclared g[23] register
92 has been used in -64. */
93 static int no_undeclared_regs;
94
95 /* Non-zero if we should try to relax jumps and calls. */
96 static int sparc_relax;
97
98 /* Non-zero if we are generating PIC code. */
99 int sparc_pic_code;
100
101 /* Non-zero if we should give an error when misaligned data is seen. */
102 static int enforce_aligned_data;
103
104 extern int target_big_endian;
105
106 static int target_little_endian_data;
107
108 /* Symbols for global registers on v9. */
109 static symbolS *globals[8];
110
111 /* V9 and 86x have big and little endian data, but instructions are always big
112 endian. The sparclet has bi-endian support but both data and insns have
113 the same endianness. Global `target_big_endian' is used for data.
114 The following macro is used for instructions. */
115 #ifndef INSN_BIG_ENDIAN
116 #define INSN_BIG_ENDIAN (target_big_endian \
117 || default_arch_type == sparc86x \
118 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
119 #endif
120
121 /* Handle of the OPCODE hash table. */
122 static struct hash_control *op_hash;
123
124 static int log2 PARAMS ((int));
125 static void s_data1 PARAMS ((void));
126 static void s_seg PARAMS ((int));
127 static void s_proc PARAMS ((int));
128 static void s_reserve PARAMS ((int));
129 static void s_common PARAMS ((int));
130 static void s_empty PARAMS ((int));
131 static void s_uacons PARAMS ((int));
132 static void s_ncons PARAMS ((int));
133 static void s_register PARAMS ((int));
134
135 const pseudo_typeS md_pseudo_table[] =
136 {
137 {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */
138 {"common", s_common, 0},
139 {"empty", s_empty, 0},
140 {"global", s_globl, 0},
141 {"half", cons, 2},
142 {"nword", s_ncons, 0},
143 {"optim", s_ignore, 0},
144 {"proc", s_proc, 0},
145 {"reserve", s_reserve, 0},
146 {"seg", s_seg, 0},
147 {"skip", s_space, 0},
148 {"word", cons, 4},
149 {"xword", cons, 8},
150 {"uahalf", s_uacons, 2},
151 {"uaword", s_uacons, 4},
152 {"uaxword", s_uacons, 8},
153 #ifdef OBJ_ELF
154 /* These are specific to sparc/svr4. */
155 {"2byte", s_uacons, 2},
156 {"4byte", s_uacons, 4},
157 {"8byte", s_uacons, 8},
158 {"register", s_register, 0},
159 #endif
160 {NULL, 0, 0},
161 };
162
163 /* Size of relocation record. */
164 const int md_reloc_size = 12;
165
166 /* This array holds the chars that always start a comment. If the
167 pre-processor is disabled, these aren't very useful. */
168 const char comment_chars[] = "!"; /* JF removed '|' from
169 comment_chars. */
170
171 /* This array holds the chars that only start a comment at the beginning of
172 a line. If the line seems to have the form '# 123 filename'
173 .line and .file directives will appear in the pre-processed output. */
174 /* Note that input_file.c hand checks for '#' at the beginning of the
175 first line of the input file. This is because the compiler outputs
176 #NO_APP at the beginning of its output. */
177 /* Also note that comments started like this one will always
178 work if '/' isn't otherwise defined. */
179 const char line_comment_chars[] = "#";
180
181 const char line_separator_chars[] = ";";
182
183 /* Chars that can be used to separate mant from exp in floating point
184 nums. */
185 const char EXP_CHARS[] = "eE";
186
187 /* Chars that mean this number is a floating point constant.
188 As in 0f12.456
189 or 0d1.2345e12 */
190 const char FLT_CHARS[] = "rRsSfFdDxXpP";
191
192 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
193 changed in read.c. Ideally it shouldn't have to know about it at all,
194 but nothing is ideal around here. */
195
196 #define isoctal(c) ((unsigned)((c) - '0') < '8')
197
198 struct sparc_it
199 {
200 char *error;
201 unsigned long opcode;
202 struct nlist *nlistp;
203 expressionS exp;
204 expressionS exp2;
205 int pcrel;
206 bfd_reloc_code_real_type reloc;
207 };
208
209 struct sparc_it the_insn, set_insn;
210
211 static void output_insn
212 PARAMS ((const struct sparc_opcode *, struct sparc_it *));
213 \f
214 /* Table of arguments to -A.
215 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
216 for this use. That table is for opcodes only. This table is for opcodes
217 and file formats. */
218
219 enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus,
220 v8plusa, v9, v9a, v9b, v9_64};
221
222 static struct sparc_arch {
223 char *name;
224 char *opcode_arch;
225 enum sparc_arch_types arch_type;
226 /* Default word size, as specified during configuration.
227 A value of zero means can't be used to specify default architecture. */
228 int default_arch_size;
229 /* Allowable arg to -A? */
230 int user_option_p;
231 } sparc_arch_table[] = {
232 { "v6", "v6", v6, 0, 1 },
233 { "v7", "v7", v7, 0, 1 },
234 { "v8", "v8", v8, 32, 1 },
235 { "sparclet", "sparclet", sparclet, 32, 1 },
236 { "sparclite", "sparclite", sparclite, 32, 1 },
237 { "sparc86x", "sparclite", sparc86x, 32, 1 },
238 { "v8plus", "v9", v9, 0, 1 },
239 { "v8plusa", "v9a", v9, 0, 1 },
240 { "v8plusb", "v9b", v9, 0, 1 },
241 { "v9", "v9", v9, 0, 1 },
242 { "v9a", "v9a", v9, 0, 1 },
243 { "v9b", "v9b", v9, 0, 1 },
244 /* This exists to allow configure.in/Makefile.in to pass one
245 value to specify both the default machine and default word size. */
246 { "v9-64", "v9", v9, 64, 0 },
247 { NULL, NULL, v8, 0, 0 }
248 };
249
250 /* Variant of default_arch */
251 static enum sparc_arch_types default_arch_type;
252
253 static struct sparc_arch *
254 lookup_arch (name)
255 char *name;
256 {
257 struct sparc_arch *sa;
258
259 for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++)
260 if (strcmp (sa->name, name) == 0)
261 break;
262 if (sa->name == NULL)
263 return NULL;
264 return sa;
265 }
266
267 /* Initialize the default opcode arch and word size from the default
268 architecture name. */
269
270 static void
271 init_default_arch ()
272 {
273 struct sparc_arch *sa = lookup_arch (default_arch);
274
275 if (sa == NULL
276 || sa->default_arch_size == 0)
277 as_fatal (_("Invalid default architecture, broken assembler."));
278
279 max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch);
280 if (max_architecture == SPARC_OPCODE_ARCH_BAD)
281 as_fatal (_("Bad opcode table, broken assembler."));
282 default_arch_size = sparc_arch_size = sa->default_arch_size;
283 default_init_p = 1;
284 default_arch_type = sa->arch_type;
285 }
286
287 /* Called by TARGET_FORMAT. */
288
289 const char *
290 sparc_target_format ()
291 {
292 /* We don't get a chance to initialize anything before we're called,
293 so handle that now. */
294 if (! default_init_p)
295 init_default_arch ();
296
297 #ifdef OBJ_AOUT
298 #ifdef TE_NetBSD
299 return "a.out-sparc-netbsd";
300 #else
301 #ifdef TE_SPARCAOUT
302 if (target_big_endian)
303 return "a.out-sunos-big";
304 else if (default_arch_type == sparc86x && target_little_endian_data)
305 return "a.out-sunos-big";
306 else
307 return "a.out-sparc-little";
308 #else
309 return "a.out-sunos-big";
310 #endif
311 #endif
312 #endif
313
314 #ifdef OBJ_BOUT
315 return "b.out.big";
316 #endif
317
318 #ifdef OBJ_COFF
319 #ifdef TE_LYNX
320 return "coff-sparc-lynx";
321 #else
322 return "coff-sparc";
323 #endif
324 #endif
325
326 #ifdef OBJ_ELF
327 return sparc_arch_size == 64 ? "elf64-sparc" : "elf32-sparc";
328 #endif
329
330 abort ();
331 }
332 \f
333 /* md_parse_option
334 * Invocation line includes a switch not recognized by the base assembler.
335 * See if it's a processor-specific option. These are:
336 *
337 * -bump
338 * Warn on architecture bumps. See also -A.
339 *
340 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet
341 * Standard 32 bit architectures.
342 * -Av9, -Av9a, -Av9b
343 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
344 * This used to only mean 64 bits, but properly specifying it
345 * complicated gcc's ASM_SPECs, so now opcode selection is
346 * specified orthogonally to word size (except when specifying
347 * the default, but that is an internal implementation detail).
348 * -Av8plus, -Av8plusa, -Av8plusb
349 * Same as -Av9{,a,b}.
350 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
351 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's
352 * assembler.
353 * -xarch=v9, -xarch=v9a, -xarch=v9b
354 * Same as -Av9{,a,b} -64, for compatibility with Sun's
355 * assembler.
356 *
357 * Select the architecture and possibly the file format.
358 * Instructions or features not supported by the selected
359 * architecture cause fatal errors.
360 *
361 * The default is to start at v6, and bump the architecture up
362 * whenever an instruction is seen at a higher level. In 32 bit
363 * environments, v9 is not bumped up to, the user must pass
364 * -Av8plus{,a,b}.
365 *
366 * If -bump is specified, a warning is printing when bumping to
367 * higher levels.
368 *
369 * If an architecture is specified, all instructions must match
370 * that architecture. Any higher level instructions are flagged
371 * as errors. Note that in the 32 bit environment specifying
372 * -Av8plus does not automatically create a v8plus object file, a
373 * v9 insn must be seen.
374 *
375 * If both an architecture and -bump are specified, the
376 * architecture starts at the specified level, but bumps are
377 * warnings. Note that we can't set `current_architecture' to
378 * the requested level in this case: in the 32 bit environment,
379 * we still must avoid creating v8plus object files unless v9
380 * insns are seen.
381 *
382 * Note:
383 * Bumping between incompatible architectures is always an
384 * error. For example, from sparclite to v9.
385 */
386
387 #ifdef OBJ_ELF
388 CONST char *md_shortopts = "A:K:VQ:sq";
389 #else
390 #ifdef OBJ_AOUT
391 CONST char *md_shortopts = "A:k";
392 #else
393 CONST char *md_shortopts = "A:";
394 #endif
395 #endif
396 struct option md_longopts[] = {
397 #define OPTION_BUMP (OPTION_MD_BASE)
398 {"bump", no_argument, NULL, OPTION_BUMP},
399 #define OPTION_SPARC (OPTION_MD_BASE + 1)
400 {"sparc", no_argument, NULL, OPTION_SPARC},
401 #define OPTION_XARCH (OPTION_MD_BASE + 2)
402 {"xarch", required_argument, NULL, OPTION_XARCH},
403 #ifdef OBJ_ELF
404 #define OPTION_32 (OPTION_MD_BASE + 3)
405 {"32", no_argument, NULL, OPTION_32},
406 #define OPTION_64 (OPTION_MD_BASE + 4)
407 {"64", no_argument, NULL, OPTION_64},
408 #define OPTION_TSO (OPTION_MD_BASE + 5)
409 {"TSO", no_argument, NULL, OPTION_TSO},
410 #define OPTION_PSO (OPTION_MD_BASE + 6)
411 {"PSO", no_argument, NULL, OPTION_PSO},
412 #define OPTION_RMO (OPTION_MD_BASE + 7)
413 {"RMO", no_argument, NULL, OPTION_RMO},
414 #endif
415 #ifdef SPARC_BIENDIAN
416 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
417 {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN},
418 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
419 {"EB", no_argument, NULL, OPTION_BIG_ENDIAN},
420 #endif
421 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
422 {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA},
423 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
424 {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA},
425 #ifdef OBJ_ELF
426 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
427 {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS},
428 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
429 {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS},
430 #endif
431 #define OPTION_RELAX (OPTION_MD_BASE + 14)
432 {"relax", no_argument, NULL, OPTION_RELAX},
433 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
434 {"no-relax", no_argument, NULL, OPTION_NO_RELAX},
435 {NULL, no_argument, NULL, 0}
436 };
437
438 size_t md_longopts_size = sizeof (md_longopts);
439
440 int
441 md_parse_option (c, arg)
442 int c;
443 char *arg;
444 {
445 /* We don't get a chance to initialize anything before we're called,
446 so handle that now. */
447 if (! default_init_p)
448 init_default_arch ();
449
450 switch (c)
451 {
452 case OPTION_BUMP:
453 warn_on_bump = 1;
454 warn_after_architecture = SPARC_OPCODE_ARCH_V6;
455 break;
456
457 case OPTION_XARCH:
458 #ifdef OBJ_ELF
459 if (strncmp (arg, "v9", 2) != 0)
460 md_parse_option (OPTION_32, NULL);
461 else
462 md_parse_option (OPTION_64, NULL);
463 #endif
464 /* Fall through. */
465
466 case 'A':
467 {
468 struct sparc_arch *sa;
469 enum sparc_opcode_arch_val opcode_arch;
470
471 sa = lookup_arch (arg);
472 if (sa == NULL
473 || ! sa->user_option_p)
474 {
475 if (c == OPTION_XARCH)
476 as_bad (_("invalid architecture -xarch=%s"), arg);
477 else
478 as_bad (_("invalid architecture -A%s"), arg);
479 return 0;
480 }
481
482 opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch);
483 if (opcode_arch == SPARC_OPCODE_ARCH_BAD)
484 as_fatal (_("Bad opcode table, broken assembler."));
485
486 max_architecture = opcode_arch;
487 architecture_requested = 1;
488 }
489 break;
490
491 case OPTION_SPARC:
492 /* Ignore -sparc, used by SunOS make default .s.o rule. */
493 break;
494
495 case OPTION_ENFORCE_ALIGNED_DATA:
496 enforce_aligned_data = 1;
497 break;
498
499 #ifdef SPARC_BIENDIAN
500 case OPTION_LITTLE_ENDIAN:
501 target_big_endian = 0;
502 if (default_arch_type != sparclet)
503 as_fatal ("This target does not support -EL");
504 break;
505 case OPTION_LITTLE_ENDIAN_DATA:
506 target_little_endian_data = 1;
507 target_big_endian = 0;
508 if (default_arch_type != sparc86x
509 && default_arch_type != v9)
510 as_fatal ("This target does not support --little-endian-data");
511 break;
512 case OPTION_BIG_ENDIAN:
513 target_big_endian = 1;
514 break;
515 #endif
516
517 #ifdef OBJ_AOUT
518 case 'k':
519 sparc_pic_code = 1;
520 break;
521 #endif
522
523 #ifdef OBJ_ELF
524 case OPTION_32:
525 case OPTION_64:
526 {
527 const char **list, **l;
528
529 sparc_arch_size = c == OPTION_32 ? 32 : 64;
530 list = bfd_target_list ();
531 for (l = list; *l != NULL; l++)
532 {
533 if (sparc_arch_size == 32)
534 {
535 if (strcmp (*l, "elf32-sparc") == 0)
536 break;
537 }
538 else
539 {
540 if (strcmp (*l, "elf64-sparc") == 0)
541 break;
542 }
543 }
544 if (*l == NULL)
545 as_fatal (_("No compiled in support for %d bit object file format"),
546 sparc_arch_size);
547 free (list);
548 }
549 break;
550
551 case OPTION_TSO:
552 sparc_memory_model = MM_TSO;
553 break;
554
555 case OPTION_PSO:
556 sparc_memory_model = MM_PSO;
557 break;
558
559 case OPTION_RMO:
560 sparc_memory_model = MM_RMO;
561 break;
562
563 case 'V':
564 print_version_id ();
565 break;
566
567 case 'Q':
568 /* Qy - do emit .comment
569 Qn - do not emit .comment. */
570 break;
571
572 case 's':
573 /* Use .stab instead of .stab.excl. */
574 break;
575
576 case 'q':
577 /* quick -- Native assembler does fewer checks. */
578 break;
579
580 case 'K':
581 if (strcmp (arg, "PIC") != 0)
582 as_warn (_("Unrecognized option following -K"));
583 else
584 sparc_pic_code = 1;
585 break;
586
587 case OPTION_NO_UNDECLARED_REGS:
588 no_undeclared_regs = 1;
589 break;
590
591 case OPTION_UNDECLARED_REGS:
592 no_undeclared_regs = 0;
593 break;
594 #endif
595
596 case OPTION_RELAX:
597 sparc_relax = 1;
598 break;
599
600 case OPTION_NO_RELAX:
601 sparc_relax = 0;
602 break;
603
604 default:
605 return 0;
606 }
607
608 return 1;
609 }
610
611 void
612 md_show_usage (stream)
613 FILE *stream;
614 {
615 const struct sparc_arch *arch;
616 int column;
617
618 /* We don't get a chance to initialize anything before we're called,
619 so handle that now. */
620 if (! default_init_p)
621 init_default_arch ();
622
623 fprintf (stream, _("SPARC options:\n"));
624 column = 0;
625 for (arch = &sparc_arch_table[0]; arch->name; arch++)
626 {
627 if (!arch->user_option_p)
628 continue;
629 if (arch != &sparc_arch_table[0])
630 fprintf (stream, " | ");
631 if (column + strlen(arch->name) > 70)
632 {
633 column = 0;
634 fputc ('\n', stream);
635 }
636 column += 5 + 2 + strlen(arch->name);
637 fprintf (stream, "-A%s", arch->name);
638 }
639 for (arch = &sparc_arch_table[0]; arch->name; arch++)
640 {
641 if (!arch->user_option_p)
642 continue;
643 fprintf (stream, " | ");
644 if (column + strlen(arch->name) > 65)
645 {
646 column = 0;
647 fputc ('\n', stream);
648 }
649 column += 5 + 7 + strlen(arch->name);
650 fprintf (stream, "-xarch=%s", arch->name);
651 }
652 fprintf (stream, _("\n\
653 specify variant of SPARC architecture\n\
654 -bump warn when assembler switches architectures\n\
655 -sparc ignored\n\
656 --enforce-aligned-data force .long, etc., to be aligned correctly\n\
657 -relax relax jumps and branches (default)\n\
658 -no-relax avoid changing any jumps and branches\n"));
659 #ifdef OBJ_AOUT
660 fprintf (stream, _("\
661 -k generate PIC\n"));
662 #endif
663 #ifdef OBJ_ELF
664 fprintf (stream, _("\
665 -32 create 32 bit object file\n\
666 -64 create 64 bit object file\n"));
667 fprintf (stream, _("\
668 [default is %d]\n"), default_arch_size);
669 fprintf (stream, _("\
670 -TSO use Total Store Ordering\n\
671 -PSO use Partial Store Ordering\n\
672 -RMO use Relaxed Memory Ordering\n"));
673 fprintf (stream, _("\
674 [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO");
675 fprintf (stream, _("\
676 -KPIC generate PIC\n\
677 -V print assembler version number\n\
678 -undeclared-regs ignore application global register usage without\n\
679 appropriate .register directive (default)\n\
680 -no-undeclared-regs force error on application global register usage\n\
681 without appropriate .register directive\n\
682 -q ignored\n\
683 -Qy, -Qn ignored\n\
684 -s ignored\n"));
685 #endif
686 #ifdef SPARC_BIENDIAN
687 fprintf (stream, _("\
688 -EL generate code for a little endian machine\n\
689 -EB generate code for a big endian machine\n\
690 --little-endian-data generate code for a machine having big endian\n\
691 instructions and little endian data.\n"));
692 #endif
693 }
694 \f
695 /* Native operand size opcode translation. */
696 struct
697 {
698 char *name;
699 char *name32;
700 char *name64;
701 } native_op_table[] =
702 {
703 {"ldn", "ld", "ldx"},
704 {"ldna", "lda", "ldxa"},
705 {"stn", "st", "stx"},
706 {"stna", "sta", "stxa"},
707 {"slln", "sll", "sllx"},
708 {"srln", "srl", "srlx"},
709 {"sran", "sra", "srax"},
710 {"casn", "cas", "casx"},
711 {"casna", "casa", "casxa"},
712 {"clrn", "clr", "clrx"},
713 {NULL, NULL, NULL},
714 };
715 \f
716 /* sparc64 priviledged registers. */
717
718 struct priv_reg_entry
719 {
720 char *name;
721 int regnum;
722 };
723
724 struct priv_reg_entry priv_reg_table[] =
725 {
726 {"tpc", 0},
727 {"tnpc", 1},
728 {"tstate", 2},
729 {"tt", 3},
730 {"tick", 4},
731 {"tba", 5},
732 {"pstate", 6},
733 {"tl", 7},
734 {"pil", 8},
735 {"cwp", 9},
736 {"cansave", 10},
737 {"canrestore", 11},
738 {"cleanwin", 12},
739 {"otherwin", 13},
740 {"wstate", 14},
741 {"fq", 15},
742 {"ver", 31},
743 {"", -1}, /* End marker. */
744 };
745
746 /* v9a specific asrs. */
747
748 struct priv_reg_entry v9a_asr_table[] =
749 {
750 {"tick_cmpr", 23},
751 {"sys_tick_cmpr", 25},
752 {"sys_tick", 24},
753 {"softint", 22},
754 {"set_softint", 20},
755 {"pic", 17},
756 {"pcr", 16},
757 {"gsr", 19},
758 {"dcr", 18},
759 {"clear_softint", 21},
760 {"", -1}, /* End marker. */
761 };
762
763 static int
764 cmp_reg_entry (parg, qarg)
765 const PTR parg;
766 const PTR qarg;
767 {
768 const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg;
769 const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg;
770
771 return strcmp (q->name, p->name);
772 }
773 \f
774 /* This function is called once, at assembler startup time. It should
775 set up all the tables, etc. that the MD part of the assembler will
776 need. */
777
778 void
779 md_begin ()
780 {
781 register const char *retval = NULL;
782 int lose = 0;
783 register unsigned int i = 0;
784
785 /* We don't get a chance to initialize anything before md_parse_option
786 is called, and it may not be called, so handle default initialization
787 now if not already done. */
788 if (! default_init_p)
789 init_default_arch ();
790
791 op_hash = hash_new ();
792
793 while (i < (unsigned int) sparc_num_opcodes)
794 {
795 const char *name = sparc_opcodes[i].name;
796 retval = hash_insert (op_hash, name, (PTR) &sparc_opcodes[i]);
797 if (retval != NULL)
798 {
799 as_bad (_("Internal error: can't hash `%s': %s\n"),
800 sparc_opcodes[i].name, retval);
801 lose = 1;
802 }
803 do
804 {
805 if (sparc_opcodes[i].match & sparc_opcodes[i].lose)
806 {
807 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
808 sparc_opcodes[i].name, sparc_opcodes[i].args);
809 lose = 1;
810 }
811 ++i;
812 }
813 while (i < (unsigned int) sparc_num_opcodes
814 && !strcmp (sparc_opcodes[i].name, name));
815 }
816
817 for (i = 0; native_op_table[i].name; i++)
818 {
819 const struct sparc_opcode *insn;
820 char *name = ((sparc_arch_size == 32)
821 ? native_op_table[i].name32
822 : native_op_table[i].name64);
823 insn = (struct sparc_opcode *) hash_find (op_hash, name);
824 if (insn == NULL)
825 {
826 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
827 name, native_op_table[i].name);
828 lose = 1;
829 }
830 else
831 {
832 retval = hash_insert (op_hash, native_op_table[i].name, (PTR) insn);
833 if (retval != NULL)
834 {
835 as_bad (_("Internal error: can't hash `%s': %s\n"),
836 sparc_opcodes[i].name, retval);
837 lose = 1;
838 }
839 }
840 }
841
842 if (lose)
843 as_fatal (_("Broken assembler. No assembly attempted."));
844
845 qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]),
846 sizeof (priv_reg_table[0]), cmp_reg_entry);
847
848 /* If -bump, record the architecture level at which we start issuing
849 warnings. The behaviour is different depending upon whether an
850 architecture was explicitly specified. If it wasn't, we issue warnings
851 for all upwards bumps. If it was, we don't start issuing warnings until
852 we need to bump beyond the requested architecture or when we bump between
853 conflicting architectures. */
854
855 if (warn_on_bump
856 && architecture_requested)
857 {
858 /* `max_architecture' records the requested architecture.
859 Issue warnings if we go above it. */
860 warn_after_architecture = max_architecture;
861
862 /* Find the highest architecture level that doesn't conflict with
863 the requested one. */
864 for (max_architecture = SPARC_OPCODE_ARCH_MAX;
865 max_architecture > warn_after_architecture;
866 --max_architecture)
867 if (! SPARC_OPCODE_CONFLICT_P (max_architecture,
868 warn_after_architecture))
869 break;
870 }
871 }
872
873 /* Called after all assembly has been done. */
874
875 void
876 sparc_md_end ()
877 {
878 unsigned long mach = bfd_mach_sparc;
879
880 if (sparc_arch_size == 64)
881 switch (current_architecture)
882 {
883 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break;
884 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break;
885 default: mach = bfd_mach_sparc_v9; break;
886 }
887 else
888 switch (current_architecture)
889 {
890 case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break;
891 case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break;
892 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break;
893 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break;
894 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
895 be but for now it is (since that's the way it's always been
896 treated). */
897 default: break;
898 }
899 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach);
900 }
901 \f
902 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
903
904 static INLINE int
905 in_signed_range (val, max)
906 bfd_signed_vma val, max;
907 {
908 if (max <= 0)
909 abort ();
910 /* Sign-extend the value from the architecture word size, so that
911 0xffffffff is always considered -1 on sparc32. */
912 if (sparc_arch_size == 32)
913 {
914 bfd_signed_vma sign = (bfd_signed_vma) 1 << 31;
915 val = ((val & 0xffffffff) ^ sign) - sign;
916 }
917 if (val > max)
918 return 0;
919 if (val < ~max)
920 return 0;
921 return 1;
922 }
923
924 /* Return non-zero if VAL is in the range 0 to MAX. */
925
926 static INLINE int
927 in_unsigned_range (val, max)
928 bfd_vma val, max;
929 {
930 if (val > max)
931 return 0;
932 return 1;
933 }
934
935 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
936 (e.g. -15 to +31). */
937
938 static INLINE int
939 in_bitfield_range (val, max)
940 bfd_signed_vma val, max;
941 {
942 if (max <= 0)
943 abort ();
944 if (val > max)
945 return 0;
946 if (val < ~(max >> 1))
947 return 0;
948 return 1;
949 }
950
951 static int
952 sparc_ffs (mask)
953 unsigned int mask;
954 {
955 int i;
956
957 if (mask == 0)
958 return -1;
959
960 for (i = 0; (mask & 1) == 0; ++i)
961 mask >>= 1;
962 return i;
963 }
964
965 /* Implement big shift right. */
966 static bfd_vma
967 BSR (val, amount)
968 bfd_vma val;
969 int amount;
970 {
971 if (sizeof (bfd_vma) <= 4 && amount >= 32)
972 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
973 return val >> amount;
974 }
975 \f
976 /* For communication between sparc_ip and get_expression. */
977 static char *expr_end;
978
979 /* Values for `special_case'.
980 Instructions that require wierd handling because they're longer than
981 4 bytes. */
982 #define SPECIAL_CASE_NONE 0
983 #define SPECIAL_CASE_SET 1
984 #define SPECIAL_CASE_SETSW 2
985 #define SPECIAL_CASE_SETX 3
986 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
987 #define SPECIAL_CASE_FDIV 4
988
989 /* Bit masks of various insns. */
990 #define NOP_INSN 0x01000000
991 #define OR_INSN 0x80100000
992 #define XOR_INSN 0x80180000
993 #define FMOVS_INSN 0x81A00020
994 #define SETHI_INSN 0x01000000
995 #define SLLX_INSN 0x81281000
996 #define SRA_INSN 0x81380000
997
998 /* The last instruction to be assembled. */
999 static const struct sparc_opcode *last_insn;
1000 /* The assembled opcode of `last_insn'. */
1001 static unsigned long last_opcode;
1002 \f
1003 /* Handle the set and setuw synthetic instructions. */
1004
1005 static void
1006 synthetize_setuw (insn)
1007 const struct sparc_opcode *insn;
1008 {
1009 int need_hi22_p = 0;
1010 int rd = (the_insn.opcode & RD (~0)) >> 25;
1011
1012 if (the_insn.exp.X_op == O_constant)
1013 {
1014 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1015 {
1016 if (sizeof (offsetT) > 4
1017 && (the_insn.exp.X_add_number < 0
1018 || the_insn.exp.X_add_number > (offsetT) 0xffffffff))
1019 as_warn (_("set: number not in 0..4294967295 range"));
1020 }
1021 else
1022 {
1023 if (sizeof (offsetT) > 4
1024 && (the_insn.exp.X_add_number < -(offsetT) 0x80000000
1025 || the_insn.exp.X_add_number > (offsetT) 0xffffffff))
1026 as_warn (_("set: number not in -2147483648..4294967295 range"));
1027 the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number;
1028 }
1029 }
1030
1031 /* See if operand is absolute and small; skip sethi if so. */
1032 if (the_insn.exp.X_op != O_constant
1033 || the_insn.exp.X_add_number >= (1 << 12)
1034 || the_insn.exp.X_add_number < -(1 << 12))
1035 {
1036 the_insn.opcode = (SETHI_INSN | RD (rd)
1037 | ((the_insn.exp.X_add_number >> 10)
1038 & (the_insn.exp.X_op == O_constant
1039 ? 0x3fffff : 0)));
1040 the_insn.reloc = (the_insn.exp.X_op != O_constant
1041 ? BFD_RELOC_HI22 : BFD_RELOC_NONE);
1042 output_insn (insn, &the_insn);
1043 need_hi22_p = 1;
1044 }
1045
1046 /* See if operand has no low-order bits; skip OR if so. */
1047 if (the_insn.exp.X_op != O_constant
1048 || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0)
1049 || ! need_hi22_p)
1050 {
1051 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0)
1052 | RD (rd) | IMMED
1053 | (the_insn.exp.X_add_number
1054 & (the_insn.exp.X_op != O_constant
1055 ? 0 : need_hi22_p ? 0x3ff : 0x1fff)));
1056 the_insn.reloc = (the_insn.exp.X_op != O_constant
1057 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1058 output_insn (insn, &the_insn);
1059 }
1060 }
1061
1062 /* Handle the setsw synthetic instruction. */
1063
1064 static void
1065 synthetize_setsw (insn)
1066 const struct sparc_opcode *insn;
1067 {
1068 int low32, rd, opc;
1069
1070 rd = (the_insn.opcode & RD (~0)) >> 25;
1071
1072 if (the_insn.exp.X_op != O_constant)
1073 {
1074 synthetize_setuw (insn);
1075
1076 /* Need to sign extend it. */
1077 the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd));
1078 the_insn.reloc = BFD_RELOC_NONE;
1079 output_insn (insn, &the_insn);
1080 return;
1081 }
1082
1083 if (sizeof (offsetT) > 4
1084 && (the_insn.exp.X_add_number < -(offsetT) 0x80000000
1085 || the_insn.exp.X_add_number > (offsetT) 0xffffffff))
1086 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1087
1088 low32 = the_insn.exp.X_add_number;
1089
1090 if (low32 >= 0)
1091 {
1092 synthetize_setuw (insn);
1093 return;
1094 }
1095
1096 opc = OR_INSN;
1097
1098 the_insn.reloc = BFD_RELOC_NONE;
1099 /* See if operand is absolute and small; skip sethi if so. */
1100 if (low32 < -(1 << 12))
1101 {
1102 the_insn.opcode = (SETHI_INSN | RD (rd)
1103 | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff));
1104 output_insn (insn, &the_insn);
1105 low32 = 0x1c00 | (low32 & 0x3ff);
1106 opc = RS1 (rd) | XOR_INSN;
1107 }
1108
1109 the_insn.opcode = (opc | RD (rd) | IMMED
1110 | (low32 & 0x1fff));
1111 output_insn (insn, &the_insn);
1112 }
1113
1114 /* Handle the setsw synthetic instruction. */
1115
1116 static void
1117 synthetize_setx (insn)
1118 const struct sparc_opcode *insn;
1119 {
1120 int upper32, lower32;
1121 int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14;
1122 int dstreg = (the_insn.opcode & RD (~0)) >> 25;
1123 int upper_dstreg;
1124 int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0;
1125 int need_xor10_p = 0;
1126
1127 #define SIGNEXT32(x) ((((x) & 0xffffffff) ^ 0x80000000) - 0x80000000)
1128 lower32 = SIGNEXT32 (the_insn.exp.X_add_number);
1129 upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32));
1130 #undef SIGNEXT32
1131
1132 upper_dstreg = tmpreg;
1133 /* The tmp reg should not be the dst reg. */
1134 if (tmpreg == dstreg)
1135 as_warn (_("setx: temporary register same as destination register"));
1136
1137 /* ??? Obviously there are other optimizations we can do
1138 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1139 doing some of these. Later. If you do change things, try to
1140 change all of this to be table driven as well. */
1141 /* What to output depends on the number if it's constant.
1142 Compute that first, then output what we've decided upon. */
1143 if (the_insn.exp.X_op != O_constant)
1144 {
1145 if (sparc_arch_size == 32)
1146 {
1147 /* When arch size is 32, we want setx to be equivalent
1148 to setuw for anything but constants. */
1149 the_insn.exp.X_add_number &= 0xffffffff;
1150 synthetize_setuw (insn);
1151 return;
1152 }
1153 need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1;
1154 lower32 = 0;
1155 upper32 = 0;
1156 }
1157 else
1158 {
1159 /* Reset X_add_number, we've extracted it as upper32/lower32.
1160 Otherwise fixup_segment will complain about not being able to
1161 write an 8 byte number in a 4 byte field. */
1162 the_insn.exp.X_add_number = 0;
1163
1164 /* Only need hh22 if `or' insn can't handle constant. */
1165 if (upper32 < -(1 << 12) || upper32 >= (1 << 12))
1166 need_hh22_p = 1;
1167
1168 /* Does bottom part (after sethi) have bits? */
1169 if ((need_hh22_p && (upper32 & 0x3ff) != 0)
1170 /* No hh22, but does upper32 still have bits we can't set
1171 from lower32? */
1172 || (! need_hh22_p && upper32 != 0 && upper32 != -1))
1173 need_hm10_p = 1;
1174
1175 /* If the lower half is all zero, we build the upper half directly
1176 into the dst reg. */
1177 if (lower32 != 0
1178 /* Need lower half if number is zero or 0xffffffff00000000. */
1179 || (! need_hh22_p && ! need_hm10_p))
1180 {
1181 /* No need for sethi if `or' insn can handle constant. */
1182 if (lower32 < -(1 << 12) || lower32 >= (1 << 12)
1183 /* Note that we can't use a negative constant in the `or'
1184 insn unless the upper 32 bits are all ones. */
1185 || (lower32 < 0 && upper32 != -1)
1186 || (lower32 >= 0 && upper32 == -1))
1187 need_hi22_p = 1;
1188
1189 if (need_hi22_p && upper32 == -1)
1190 need_xor10_p = 1;
1191
1192 /* Does bottom part (after sethi) have bits? */
1193 else if ((need_hi22_p && (lower32 & 0x3ff) != 0)
1194 /* No sethi. */
1195 || (! need_hi22_p && (lower32 & 0x1fff) != 0)
1196 /* Need `or' if we didn't set anything else. */
1197 || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p))
1198 need_lo10_p = 1;
1199 }
1200 else
1201 /* Output directly to dst reg if lower 32 bits are all zero. */
1202 upper_dstreg = dstreg;
1203 }
1204
1205 if (!upper_dstreg && dstreg)
1206 as_warn (_("setx: illegal temporary register g0"));
1207
1208 if (need_hh22_p)
1209 {
1210 the_insn.opcode = (SETHI_INSN | RD (upper_dstreg)
1211 | ((upper32 >> 10) & 0x3fffff));
1212 the_insn.reloc = (the_insn.exp.X_op != O_constant
1213 ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE);
1214 output_insn (insn, &the_insn);
1215 }
1216
1217 if (need_hi22_p)
1218 {
1219 the_insn.opcode = (SETHI_INSN | RD (dstreg)
1220 | (((need_xor10_p ? ~lower32 : lower32)
1221 >> 10) & 0x3fffff));
1222 the_insn.reloc = (the_insn.exp.X_op != O_constant
1223 ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE);
1224 output_insn (insn, &the_insn);
1225 }
1226
1227 if (need_hm10_p)
1228 {
1229 the_insn.opcode = (OR_INSN
1230 | (need_hh22_p ? RS1 (upper_dstreg) : 0)
1231 | RD (upper_dstreg)
1232 | IMMED
1233 | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff)));
1234 the_insn.reloc = (the_insn.exp.X_op != O_constant
1235 ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE);
1236 output_insn (insn, &the_insn);
1237 }
1238
1239 if (need_lo10_p)
1240 {
1241 /* FIXME: One nice optimization to do here is to OR the low part
1242 with the highpart if hi22 isn't needed and the low part is
1243 positive. */
1244 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0)
1245 | RD (dstreg)
1246 | IMMED
1247 | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff)));
1248 the_insn.reloc = (the_insn.exp.X_op != O_constant
1249 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1250 output_insn (insn, &the_insn);
1251 }
1252
1253 /* If we needed to build the upper part, shift it into place. */
1254 if (need_hh22_p || need_hm10_p)
1255 {
1256 the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg)
1257 | IMMED | 32);
1258 the_insn.reloc = BFD_RELOC_NONE;
1259 output_insn (insn, &the_insn);
1260 }
1261
1262 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1263 if (need_xor10_p)
1264 {
1265 the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED
1266 | 0x1c00 | (lower32 & 0x3ff));
1267 the_insn.reloc = BFD_RELOC_NONE;
1268 output_insn (insn, &the_insn);
1269 }
1270
1271 /* If we needed to build both upper and lower parts, OR them together. */
1272 else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p))
1273 {
1274 the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg)
1275 | RD (dstreg));
1276 the_insn.reloc = BFD_RELOC_NONE;
1277 output_insn (insn, &the_insn);
1278 }
1279 }
1280 \f
1281 /* Main entry point to assemble one instruction. */
1282
1283 void
1284 md_assemble (str)
1285 char *str;
1286 {
1287 const struct sparc_opcode *insn;
1288 int special_case;
1289
1290 know (str);
1291 special_case = sparc_ip (str, &insn);
1292
1293 /* We warn about attempts to put a floating point branch in a delay slot,
1294 unless the delay slot has been annulled. */
1295 if (insn != NULL
1296 && last_insn != NULL
1297 && (insn->flags & F_FBR) != 0
1298 && (last_insn->flags & F_DELAYED) != 0
1299 /* ??? This test isn't completely accurate. We assume anything with
1300 F_{UNBR,CONDBR,FBR} set is annullable. */
1301 && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0
1302 || (last_opcode & ANNUL) == 0))
1303 as_warn (_("FP branch in delay slot"));
1304
1305 /* SPARC before v9 requires a nop instruction between a floating
1306 point instruction and a floating point branch. We insert one
1307 automatically, with a warning. */
1308 if (max_architecture < SPARC_OPCODE_ARCH_V9
1309 && insn != NULL
1310 && last_insn != NULL
1311 && (insn->flags & F_FBR) != 0
1312 && (last_insn->flags & F_FLOAT) != 0)
1313 {
1314 struct sparc_it nop_insn;
1315
1316 nop_insn.opcode = NOP_INSN;
1317 nop_insn.reloc = BFD_RELOC_NONE;
1318 output_insn (insn, &nop_insn);
1319 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1320 }
1321
1322 switch (special_case)
1323 {
1324 case SPECIAL_CASE_NONE:
1325 /* Normal insn. */
1326 output_insn (insn, &the_insn);
1327 break;
1328
1329 case SPECIAL_CASE_SETSW:
1330 synthetize_setsw (insn);
1331 break;
1332
1333 case SPECIAL_CASE_SET:
1334 synthetize_setuw (insn);
1335 break;
1336
1337 case SPECIAL_CASE_SETX:
1338 synthetize_setx (insn);
1339 break;
1340
1341 case SPECIAL_CASE_FDIV:
1342 {
1343 int rd = (the_insn.opcode >> 25) & 0x1f;
1344
1345 output_insn (insn, &the_insn);
1346
1347 /* According to information leaked from Sun, the "fdiv" instructions
1348 on early SPARC machines would produce incorrect results sometimes.
1349 The workaround is to add an fmovs of the destination register to
1350 itself just after the instruction. This was true on machines
1351 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1352 assert (the_insn.reloc == BFD_RELOC_NONE);
1353 the_insn.opcode = FMOVS_INSN | rd | RD (rd);
1354 output_insn (insn, &the_insn);
1355 return;
1356 }
1357
1358 default:
1359 as_fatal (_("failed special case insn sanity check"));
1360 }
1361 }
1362
1363 /* Subroutine of md_assemble to do the actual parsing. */
1364
1365 static int
1366 sparc_ip (str, pinsn)
1367 char *str;
1368 const struct sparc_opcode **pinsn;
1369 {
1370 char *error_message = "";
1371 char *s;
1372 const char *args;
1373 char c;
1374 const struct sparc_opcode *insn;
1375 char *argsStart;
1376 unsigned long opcode;
1377 unsigned int mask = 0;
1378 int match = 0;
1379 int comma = 0;
1380 int v9_arg_p;
1381 int special_case = SPECIAL_CASE_NONE;
1382
1383 s = str;
1384 if (islower ((unsigned char) *s))
1385 {
1386 do
1387 ++s;
1388 while (islower ((unsigned char) *s) || isdigit ((unsigned char) *s));
1389 }
1390
1391 switch (*s)
1392 {
1393 case '\0':
1394 break;
1395
1396 case ',':
1397 comma = 1;
1398 /* Fall through. */
1399
1400 case ' ':
1401 *s++ = '\0';
1402 break;
1403
1404 default:
1405 as_fatal (_("Unknown opcode: `%s'"), str);
1406 }
1407 insn = (struct sparc_opcode *) hash_find (op_hash, str);
1408 *pinsn = insn;
1409 if (insn == NULL)
1410 {
1411 as_bad (_("Unknown opcode: `%s'"), str);
1412 return special_case;
1413 }
1414 if (comma)
1415 {
1416 *--s = ',';
1417 }
1418
1419 argsStart = s;
1420 for (;;)
1421 {
1422 opcode = insn->match;
1423 memset (&the_insn, '\0', sizeof (the_insn));
1424 the_insn.reloc = BFD_RELOC_NONE;
1425 v9_arg_p = 0;
1426
1427 /* Build the opcode, checking as we go to make sure that the
1428 operands match. */
1429 for (args = insn->args;; ++args)
1430 {
1431 switch (*args)
1432 {
1433 case 'K':
1434 {
1435 int kmask = 0;
1436
1437 /* Parse a series of masks. */
1438 if (*s == '#')
1439 {
1440 while (*s == '#')
1441 {
1442 int mask;
1443
1444 if (! parse_keyword_arg (sparc_encode_membar, &s,
1445 &mask))
1446 {
1447 error_message = _(": invalid membar mask name");
1448 goto error;
1449 }
1450 kmask |= mask;
1451 while (*s == ' ')
1452 ++s;
1453 if (*s == '|' || *s == '+')
1454 ++s;
1455 while (*s == ' ')
1456 ++s;
1457 }
1458 }
1459 else
1460 {
1461 if (! parse_const_expr_arg (&s, &kmask))
1462 {
1463 error_message = _(": invalid membar mask expression");
1464 goto error;
1465 }
1466 if (kmask < 0 || kmask > 127)
1467 {
1468 error_message = _(": invalid membar mask number");
1469 goto error;
1470 }
1471 }
1472
1473 opcode |= MEMBAR (kmask);
1474 continue;
1475 }
1476
1477 case '3':
1478 {
1479 int smask = 0;
1480
1481 if (! parse_const_expr_arg (&s, &smask))
1482 {
1483 error_message = _(": invalid siam mode expression");
1484 goto error;
1485 }
1486 if (smask < 0 || smask > 7)
1487 {
1488 error_message = _(": invalid siam mode number");
1489 goto error;
1490 }
1491 opcode |= smask;
1492 continue;
1493 }
1494
1495 case '*':
1496 {
1497 int fcn = 0;
1498
1499 /* Parse a prefetch function. */
1500 if (*s == '#')
1501 {
1502 if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn))
1503 {
1504 error_message = _(": invalid prefetch function name");
1505 goto error;
1506 }
1507 }
1508 else
1509 {
1510 if (! parse_const_expr_arg (&s, &fcn))
1511 {
1512 error_message = _(": invalid prefetch function expression");
1513 goto error;
1514 }
1515 if (fcn < 0 || fcn > 31)
1516 {
1517 error_message = _(": invalid prefetch function number");
1518 goto error;
1519 }
1520 }
1521 opcode |= RD (fcn);
1522 continue;
1523 }
1524
1525 case '!':
1526 case '?':
1527 /* Parse a sparc64 privileged register. */
1528 if (*s == '%')
1529 {
1530 struct priv_reg_entry *p = priv_reg_table;
1531 unsigned int len = 9999999; /* Init to make gcc happy. */
1532
1533 s += 1;
1534 while (p->name[0] > s[0])
1535 p++;
1536 while (p->name[0] == s[0])
1537 {
1538 len = strlen (p->name);
1539 if (strncmp (p->name, s, len) == 0)
1540 break;
1541 p++;
1542 }
1543 if (p->name[0] != s[0])
1544 {
1545 error_message = _(": unrecognizable privileged register");
1546 goto error;
1547 }
1548 if (*args == '?')
1549 opcode |= (p->regnum << 14);
1550 else
1551 opcode |= (p->regnum << 25);
1552 s += len;
1553 continue;
1554 }
1555 else
1556 {
1557 error_message = _(": unrecognizable privileged register");
1558 goto error;
1559 }
1560
1561 case '_':
1562 case '/':
1563 /* Parse a v9a/v9b ancillary state register. */
1564 if (*s == '%')
1565 {
1566 struct priv_reg_entry *p = v9a_asr_table;
1567 unsigned int len = 9999999; /* Init to make gcc happy. */
1568
1569 s += 1;
1570 while (p->name[0] > s[0])
1571 p++;
1572 while (p->name[0] == s[0])
1573 {
1574 len = strlen (p->name);
1575 if (strncmp (p->name, s, len) == 0)
1576 break;
1577 p++;
1578 }
1579 if (p->name[0] != s[0])
1580 {
1581 error_message = _(": unrecognizable v9a or v9b ancillary state register");
1582 goto error;
1583 }
1584 if (*args == '/' && (p->regnum == 20 || p->regnum == 21))
1585 {
1586 error_message = _(": rd on write only ancillary state register");
1587 goto error;
1588 }
1589 if (p->regnum >= 24
1590 && (insn->architecture
1591 & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)))
1592 {
1593 /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */
1594 error_message = _(": unrecognizable v9a ancillary state register");
1595 goto error;
1596 }
1597 if (*args == '/')
1598 opcode |= (p->regnum << 14);
1599 else
1600 opcode |= (p->regnum << 25);
1601 s += len;
1602 continue;
1603 }
1604 else
1605 {
1606 error_message = _(": unrecognizable v9a or v9b ancillary state register");
1607 goto error;
1608 }
1609
1610 case 'M':
1611 case 'm':
1612 if (strncmp (s, "%asr", 4) == 0)
1613 {
1614 s += 4;
1615
1616 if (isdigit ((unsigned char) *s))
1617 {
1618 long num = 0;
1619
1620 while (isdigit ((unsigned char) *s))
1621 {
1622 num = num * 10 + *s - '0';
1623 ++s;
1624 }
1625
1626 if (current_architecture >= SPARC_OPCODE_ARCH_V9)
1627 {
1628 if (num < 16 || 31 < num)
1629 {
1630 error_message = _(": asr number must be between 16 and 31");
1631 goto error;
1632 }
1633 }
1634 else
1635 {
1636 if (num < 0 || 31 < num)
1637 {
1638 error_message = _(": asr number must be between 0 and 31");
1639 goto error;
1640 }
1641 }
1642
1643 opcode |= (*args == 'M' ? RS1 (num) : RD (num));
1644 continue;
1645 }
1646 else
1647 {
1648 error_message = _(": expecting %asrN");
1649 goto error;
1650 }
1651 } /* if %asr */
1652 break;
1653
1654 case 'I':
1655 the_insn.reloc = BFD_RELOC_SPARC_11;
1656 goto immediate;
1657
1658 case 'j':
1659 the_insn.reloc = BFD_RELOC_SPARC_10;
1660 goto immediate;
1661
1662 case 'X':
1663 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1664 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1665 the_insn.reloc = BFD_RELOC_SPARC_5;
1666 else
1667 the_insn.reloc = BFD_RELOC_SPARC13;
1668 /* These fields are unsigned, but for upward compatibility,
1669 allow negative values as well. */
1670 goto immediate;
1671
1672 case 'Y':
1673 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1674 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1675 the_insn.reloc = BFD_RELOC_SPARC_6;
1676 else
1677 the_insn.reloc = BFD_RELOC_SPARC13;
1678 /* These fields are unsigned, but for upward compatibility,
1679 allow negative values as well. */
1680 goto immediate;
1681
1682 case 'k':
1683 the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16;
1684 the_insn.pcrel = 1;
1685 goto immediate;
1686
1687 case 'G':
1688 the_insn.reloc = BFD_RELOC_SPARC_WDISP19;
1689 the_insn.pcrel = 1;
1690 goto immediate;
1691
1692 case 'N':
1693 if (*s == 'p' && s[1] == 'n')
1694 {
1695 s += 2;
1696 continue;
1697 }
1698 break;
1699
1700 case 'T':
1701 if (*s == 'p' && s[1] == 't')
1702 {
1703 s += 2;
1704 continue;
1705 }
1706 break;
1707
1708 case 'z':
1709 if (*s == ' ')
1710 {
1711 ++s;
1712 }
1713 if (strncmp (s, "%icc", 4) == 0)
1714 {
1715 s += 4;
1716 continue;
1717 }
1718 break;
1719
1720 case 'Z':
1721 if (*s == ' ')
1722 {
1723 ++s;
1724 }
1725 if (strncmp (s, "%xcc", 4) == 0)
1726 {
1727 s += 4;
1728 continue;
1729 }
1730 break;
1731
1732 case '6':
1733 if (*s == ' ')
1734 {
1735 ++s;
1736 }
1737 if (strncmp (s, "%fcc0", 5) == 0)
1738 {
1739 s += 5;
1740 continue;
1741 }
1742 break;
1743
1744 case '7':
1745 if (*s == ' ')
1746 {
1747 ++s;
1748 }
1749 if (strncmp (s, "%fcc1", 5) == 0)
1750 {
1751 s += 5;
1752 continue;
1753 }
1754 break;
1755
1756 case '8':
1757 if (*s == ' ')
1758 {
1759 ++s;
1760 }
1761 if (strncmp (s, "%fcc2", 5) == 0)
1762 {
1763 s += 5;
1764 continue;
1765 }
1766 break;
1767
1768 case '9':
1769 if (*s == ' ')
1770 {
1771 ++s;
1772 }
1773 if (strncmp (s, "%fcc3", 5) == 0)
1774 {
1775 s += 5;
1776 continue;
1777 }
1778 break;
1779
1780 case 'P':
1781 if (strncmp (s, "%pc", 3) == 0)
1782 {
1783 s += 3;
1784 continue;
1785 }
1786 break;
1787
1788 case 'W':
1789 if (strncmp (s, "%tick", 5) == 0)
1790 {
1791 s += 5;
1792 continue;
1793 }
1794 break;
1795
1796 case '\0': /* End of args. */
1797 if (*s == '\0')
1798 {
1799 match = 1;
1800 }
1801 break;
1802
1803 case '+':
1804 if (*s == '+')
1805 {
1806 ++s;
1807 continue;
1808 }
1809 if (*s == '-')
1810 {
1811 continue;
1812 }
1813 break;
1814
1815 case '[': /* These must match exactly. */
1816 case ']':
1817 case ',':
1818 case ' ':
1819 if (*s++ == *args)
1820 continue;
1821 break;
1822
1823 case '#': /* Must be at least one digit. */
1824 if (isdigit ((unsigned char) *s++))
1825 {
1826 while (isdigit ((unsigned char) *s))
1827 {
1828 ++s;
1829 }
1830 continue;
1831 }
1832 break;
1833
1834 case 'C': /* Coprocessor state register. */
1835 if (strncmp (s, "%csr", 4) == 0)
1836 {
1837 s += 4;
1838 continue;
1839 }
1840 break;
1841
1842 case 'b': /* Next operand is a coprocessor register. */
1843 case 'c':
1844 case 'D':
1845 if (*s++ == '%' && *s++ == 'c' && isdigit ((unsigned char) *s))
1846 {
1847 mask = *s++;
1848 if (isdigit ((unsigned char) *s))
1849 {
1850 mask = 10 * (mask - '0') + (*s++ - '0');
1851 if (mask >= 32)
1852 {
1853 break;
1854 }
1855 }
1856 else
1857 {
1858 mask -= '0';
1859 }
1860 switch (*args)
1861 {
1862
1863 case 'b':
1864 opcode |= mask << 14;
1865 continue;
1866
1867 case 'c':
1868 opcode |= mask;
1869 continue;
1870
1871 case 'D':
1872 opcode |= mask << 25;
1873 continue;
1874 }
1875 }
1876 break;
1877
1878 case 'r': /* next operand must be a register */
1879 case 'O':
1880 case '1':
1881 case '2':
1882 case 'd':
1883 if (*s++ == '%')
1884 {
1885 switch (c = *s++)
1886 {
1887
1888 case 'f': /* frame pointer */
1889 if (*s++ == 'p')
1890 {
1891 mask = 0x1e;
1892 break;
1893 }
1894 goto error;
1895
1896 case 'g': /* global register */
1897 c = *s++;
1898 if (isoctal (c))
1899 {
1900 mask = c - '0';
1901 break;
1902 }
1903 goto error;
1904
1905 case 'i': /* in register */
1906 c = *s++;
1907 if (isoctal (c))
1908 {
1909 mask = c - '0' + 24;
1910 break;
1911 }
1912 goto error;
1913
1914 case 'l': /* local register */
1915 c = *s++;
1916 if (isoctal (c))
1917 {
1918 mask = (c - '0' + 16);
1919 break;
1920 }
1921 goto error;
1922
1923 case 'o': /* out register */
1924 c = *s++;
1925 if (isoctal (c))
1926 {
1927 mask = (c - '0' + 8);
1928 break;
1929 }
1930 goto error;
1931
1932 case 's': /* stack pointer */
1933 if (*s++ == 'p')
1934 {
1935 mask = 0xe;
1936 break;
1937 }
1938 goto error;
1939
1940 case 'r': /* any register */
1941 if (!isdigit ((unsigned char) (c = *s++)))
1942 {
1943 goto error;
1944 }
1945 /* FALLTHROUGH */
1946 case '0':
1947 case '1':
1948 case '2':
1949 case '3':
1950 case '4':
1951 case '5':
1952 case '6':
1953 case '7':
1954 case '8':
1955 case '9':
1956 if (isdigit ((unsigned char) *s))
1957 {
1958 if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32)
1959 {
1960 goto error;
1961 }
1962 }
1963 else
1964 {
1965 c -= '0';
1966 }
1967 mask = c;
1968 break;
1969
1970 default:
1971 goto error;
1972 }
1973
1974 if ((mask & ~1) == 2 && sparc_arch_size == 64
1975 && no_undeclared_regs && ! globals[mask])
1976 as_bad (_("detected global register use not covered by .register pseudo-op"));
1977
1978 /* Got the register, now figure out where
1979 it goes in the opcode. */
1980 switch (*args)
1981 {
1982 case '1':
1983 opcode |= mask << 14;
1984 continue;
1985
1986 case '2':
1987 opcode |= mask;
1988 continue;
1989
1990 case 'd':
1991 opcode |= mask << 25;
1992 continue;
1993
1994 case 'r':
1995 opcode |= (mask << 25) | (mask << 14);
1996 continue;
1997
1998 case 'O':
1999 opcode |= (mask << 25) | (mask << 0);
2000 continue;
2001 }
2002 }
2003 break;
2004
2005 case 'e': /* next operand is a floating point register */
2006 case 'v':
2007 case 'V':
2008
2009 case 'f':
2010 case 'B':
2011 case 'R':
2012
2013 case 'g':
2014 case 'H':
2015 case 'J':
2016 {
2017 char format;
2018
2019 if (*s++ == '%'
2020 && ((format = *s) == 'f')
2021 && isdigit ((unsigned char) *++s))
2022 {
2023 for (mask = 0; isdigit ((unsigned char) *s); ++s)
2024 {
2025 mask = 10 * mask + (*s - '0');
2026 } /* read the number */
2027
2028 if ((*args == 'v'
2029 || *args == 'B'
2030 || *args == 'H')
2031 && (mask & 1))
2032 {
2033 break;
2034 } /* register must be even numbered */
2035
2036 if ((*args == 'V'
2037 || *args == 'R'
2038 || *args == 'J')
2039 && (mask & 3))
2040 {
2041 break;
2042 } /* register must be multiple of 4 */
2043
2044 if (mask >= 64)
2045 {
2046 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2047 error_message = _(": There are only 64 f registers; [0-63]");
2048 else
2049 error_message = _(": There are only 32 f registers; [0-31]");
2050 goto error;
2051 } /* on error */
2052 else if (mask >= 32)
2053 {
2054 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2055 {
2056 v9_arg_p = 1;
2057 mask -= 31; /* wrap high bit */
2058 }
2059 else
2060 {
2061 error_message = _(": There are only 32 f registers; [0-31]");
2062 goto error;
2063 }
2064 }
2065 }
2066 else
2067 {
2068 break;
2069 } /* if not an 'f' register. */
2070
2071 switch (*args)
2072 {
2073 case 'v':
2074 case 'V':
2075 case 'e':
2076 opcode |= RS1 (mask);
2077 continue;
2078
2079 case 'f':
2080 case 'B':
2081 case 'R':
2082 opcode |= RS2 (mask);
2083 continue;
2084
2085 case 'g':
2086 case 'H':
2087 case 'J':
2088 opcode |= RD (mask);
2089 continue;
2090 } /* Pack it in. */
2091
2092 know (0);
2093 break;
2094 } /* float arg */
2095
2096 case 'F':
2097 if (strncmp (s, "%fsr", 4) == 0)
2098 {
2099 s += 4;
2100 continue;
2101 }
2102 break;
2103
2104 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2105 the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */
2106 goto immediate;
2107
2108 case 'l': /* 22 bit PC relative immediate */
2109 the_insn.reloc = BFD_RELOC_SPARC_WDISP22;
2110 the_insn.pcrel = 1;
2111 goto immediate;
2112
2113 case 'L': /* 30 bit immediate */
2114 the_insn.reloc = BFD_RELOC_32_PCREL_S2;
2115 the_insn.pcrel = 1;
2116 goto immediate;
2117
2118 case 'h':
2119 case 'n': /* 22 bit immediate */
2120 the_insn.reloc = BFD_RELOC_SPARC22;
2121 goto immediate;
2122
2123 case 'i': /* 13 bit immediate */
2124 the_insn.reloc = BFD_RELOC_SPARC13;
2125
2126 /* fallthrough */
2127
2128 immediate:
2129 if (*s == ' ')
2130 s++;
2131
2132 {
2133 char *s1;
2134 char *op_arg = NULL;
2135 expressionS op_exp;
2136 bfd_reloc_code_real_type old_reloc = the_insn.reloc;
2137
2138 /* Check for %hi, etc. */
2139 if (*s == '%')
2140 {
2141 static const struct ops {
2142 /* The name as it appears in assembler. */
2143 char *name;
2144 /* strlen (name), precomputed for speed */
2145 int len;
2146 /* The reloc this pseudo-op translates to. */
2147 int reloc;
2148 /* Non-zero if for v9 only. */
2149 int v9_p;
2150 /* Non-zero if can be used in pc-relative contexts. */
2151 int pcrel_p;/*FIXME:wip*/
2152 } ops[] = {
2153 /* hix/lox must appear before hi/lo so %hix won't be
2154 mistaken for %hi. */
2155 { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 },
2156 { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 },
2157 { "hi", 2, BFD_RELOC_HI22, 0, 1 },
2158 { "lo", 2, BFD_RELOC_LO10, 0, 1 },
2159 { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 },
2160 { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 },
2161 { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 },
2162 { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 },
2163 { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 },
2164 { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 },
2165 { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 },
2166 { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 },
2167 { NULL, 0, 0, 0, 0 }
2168 };
2169 const struct ops *o;
2170
2171 for (o = ops; o->name; o++)
2172 if (strncmp (s + 1, o->name, o->len) == 0)
2173 break;
2174 if (o->name == NULL)
2175 break;
2176
2177 if (s[o->len + 1] != '(')
2178 {
2179 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
2180 return special_case;
2181 }
2182
2183 op_arg = o->name;
2184 the_insn.reloc = o->reloc;
2185 s += o->len + 2;
2186 v9_arg_p = o->v9_p;
2187 }
2188
2189 /* Note that if the get_expression() fails, we will still
2190 have created U entries in the symbol table for the
2191 'symbols' in the input string. Try not to create U
2192 symbols for registers, etc. */
2193
2194 /* This stuff checks to see if the expression ends in
2195 +%reg. If it does, it removes the register from
2196 the expression, and re-sets 's' to point to the
2197 right place. */
2198
2199 if (op_arg)
2200 {
2201 int npar = 0;
2202
2203 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2204 if (*s1 == '(')
2205 npar++;
2206 else if (*s1 == ')')
2207 {
2208 if (!npar)
2209 break;
2210 npar--;
2211 }
2212
2213 if (*s1 != ')')
2214 {
2215 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg);
2216 return special_case;
2217 }
2218
2219 *s1 = '\0';
2220 (void) get_expression (s);
2221 *s1 = ')';
2222 s = s1 + 1;
2223 if (*s == ',' || *s == ']' || !*s)
2224 continue;
2225 if (*s != '+' && *s != '-')
2226 {
2227 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg);
2228 return special_case;
2229 }
2230 *s1 = '0';
2231 s = s1;
2232 op_exp = the_insn.exp;
2233 memset (&the_insn.exp, 0, sizeof (the_insn.exp));
2234 }
2235
2236 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2237 ;
2238
2239 if (s1 != s && isdigit ((unsigned char) s1[-1]))
2240 {
2241 if (s1[-2] == '%' && s1[-3] == '+')
2242 s1 -= 3;
2243 else if (strchr ("goli0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+')
2244 s1 -= 4;
2245 else
2246 s1 = NULL;
2247 if (s1)
2248 {
2249 *s1 = '\0';
2250 if (op_arg && s1 == s + 1)
2251 the_insn.exp.X_op = O_absent;
2252 else
2253 (void) get_expression (s);
2254 *s1 = '+';
2255 if (op_arg)
2256 *s = ')';
2257 s = s1;
2258 }
2259 }
2260 else
2261 s1 = NULL;
2262
2263 if (!s1)
2264 {
2265 (void) get_expression (s);
2266 if (op_arg)
2267 *s = ')';
2268 s = expr_end;
2269 }
2270
2271 if (op_arg)
2272 {
2273 the_insn.exp2 = the_insn.exp;
2274 the_insn.exp = op_exp;
2275 if (the_insn.exp2.X_op == O_absent)
2276 the_insn.exp2.X_op = O_illegal;
2277 else if (the_insn.exp.X_op == O_absent)
2278 {
2279 the_insn.exp = the_insn.exp2;
2280 the_insn.exp2.X_op = O_illegal;
2281 }
2282 else if (the_insn.exp.X_op == O_constant)
2283 {
2284 valueT val = the_insn.exp.X_add_number;
2285 switch (the_insn.reloc)
2286 {
2287 default:
2288 break;
2289
2290 case BFD_RELOC_SPARC_HH22:
2291 val = BSR (val, 32);
2292 /* Fall through. */
2293
2294 case BFD_RELOC_SPARC_LM22:
2295 case BFD_RELOC_HI22:
2296 val = (val >> 10) & 0x3fffff;
2297 break;
2298
2299 case BFD_RELOC_SPARC_HM10:
2300 val = BSR (val, 32);
2301 /* Fall through. */
2302
2303 case BFD_RELOC_LO10:
2304 val &= 0x3ff;
2305 break;
2306
2307 case BFD_RELOC_SPARC_H44:
2308 val >>= 22;
2309 val &= 0x3fffff;
2310 break;
2311
2312 case BFD_RELOC_SPARC_M44:
2313 val >>= 12;
2314 val &= 0x3ff;
2315 break;
2316
2317 case BFD_RELOC_SPARC_L44:
2318 val &= 0xfff;
2319 break;
2320
2321 case BFD_RELOC_SPARC_HIX22:
2322 val = ~val;
2323 val = (val >> 10) & 0x3fffff;
2324 break;
2325
2326 case BFD_RELOC_SPARC_LOX10:
2327 val = (val & 0x3ff) | 0x1c00;
2328 break;
2329 }
2330 the_insn.exp = the_insn.exp2;
2331 the_insn.exp.X_add_number += val;
2332 the_insn.exp2.X_op = O_illegal;
2333 the_insn.reloc = old_reloc;
2334 }
2335 else if (the_insn.exp2.X_op != O_constant)
2336 {
2337 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg);
2338 return special_case;
2339 }
2340 else
2341 {
2342 if (old_reloc != BFD_RELOC_SPARC13
2343 || the_insn.reloc != BFD_RELOC_LO10
2344 || sparc_arch_size != 64
2345 || sparc_pic_code)
2346 {
2347 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg);
2348 return special_case;
2349 }
2350 the_insn.reloc = BFD_RELOC_SPARC_OLO10;
2351 }
2352 }
2353 }
2354 /* Check for constants that don't require emitting a reloc. */
2355 if (the_insn.exp.X_op == O_constant
2356 && the_insn.exp.X_add_symbol == 0
2357 && the_insn.exp.X_op_symbol == 0)
2358 {
2359 /* For pc-relative call instructions, we reject
2360 constants to get better code. */
2361 if (the_insn.pcrel
2362 && the_insn.reloc == BFD_RELOC_32_PCREL_S2
2363 && in_signed_range (the_insn.exp.X_add_number, 0x3fff))
2364 {
2365 error_message = _(": PC-relative operand can't be a constant");
2366 goto error;
2367 }
2368
2369 /* Constants that won't fit are checked in md_apply_fix3
2370 and bfd_install_relocation.
2371 ??? It would be preferable to install the constants
2372 into the insn here and save having to create a fixS
2373 for each one. There already exists code to handle
2374 all the various cases (e.g. in md_apply_fix3 and
2375 bfd_install_relocation) so duplicating all that code
2376 here isn't right. */
2377 }
2378
2379 continue;
2380
2381 case 'a':
2382 if (*s++ == 'a')
2383 {
2384 opcode |= ANNUL;
2385 continue;
2386 }
2387 break;
2388
2389 case 'A':
2390 {
2391 int asi = 0;
2392
2393 /* Parse an asi. */
2394 if (*s == '#')
2395 {
2396 if (! parse_keyword_arg (sparc_encode_asi, &s, &asi))
2397 {
2398 error_message = _(": invalid ASI name");
2399 goto error;
2400 }
2401 }
2402 else
2403 {
2404 if (! parse_const_expr_arg (&s, &asi))
2405 {
2406 error_message = _(": invalid ASI expression");
2407 goto error;
2408 }
2409 if (asi < 0 || asi > 255)
2410 {
2411 error_message = _(": invalid ASI number");
2412 goto error;
2413 }
2414 }
2415 opcode |= ASI (asi);
2416 continue;
2417 } /* Alternate space. */
2418
2419 case 'p':
2420 if (strncmp (s, "%psr", 4) == 0)
2421 {
2422 s += 4;
2423 continue;
2424 }
2425 break;
2426
2427 case 'q': /* Floating point queue. */
2428 if (strncmp (s, "%fq", 3) == 0)
2429 {
2430 s += 3;
2431 continue;
2432 }
2433 break;
2434
2435 case 'Q': /* Coprocessor queue. */
2436 if (strncmp (s, "%cq", 3) == 0)
2437 {
2438 s += 3;
2439 continue;
2440 }
2441 break;
2442
2443 case 'S':
2444 if (strcmp (str, "set") == 0
2445 || strcmp (str, "setuw") == 0)
2446 {
2447 special_case = SPECIAL_CASE_SET;
2448 continue;
2449 }
2450 else if (strcmp (str, "setsw") == 0)
2451 {
2452 special_case = SPECIAL_CASE_SETSW;
2453 continue;
2454 }
2455 else if (strcmp (str, "setx") == 0)
2456 {
2457 special_case = SPECIAL_CASE_SETX;
2458 continue;
2459 }
2460 else if (strncmp (str, "fdiv", 4) == 0)
2461 {
2462 special_case = SPECIAL_CASE_FDIV;
2463 continue;
2464 }
2465 break;
2466
2467 case 'o':
2468 if (strncmp (s, "%asi", 4) != 0)
2469 break;
2470 s += 4;
2471 continue;
2472
2473 case 's':
2474 if (strncmp (s, "%fprs", 5) != 0)
2475 break;
2476 s += 5;
2477 continue;
2478
2479 case 'E':
2480 if (strncmp (s, "%ccr", 4) != 0)
2481 break;
2482 s += 4;
2483 continue;
2484
2485 case 't':
2486 if (strncmp (s, "%tbr", 4) != 0)
2487 break;
2488 s += 4;
2489 continue;
2490
2491 case 'w':
2492 if (strncmp (s, "%wim", 4) != 0)
2493 break;
2494 s += 4;
2495 continue;
2496
2497 case 'x':
2498 {
2499 char *push = input_line_pointer;
2500 expressionS e;
2501
2502 input_line_pointer = s;
2503 expression (&e);
2504 if (e.X_op == O_constant)
2505 {
2506 int n = e.X_add_number;
2507 if (n != e.X_add_number || (n & ~0x1ff) != 0)
2508 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
2509 else
2510 opcode |= e.X_add_number << 5;
2511 }
2512 else
2513 as_bad (_("non-immediate OPF operand, ignored"));
2514 s = input_line_pointer;
2515 input_line_pointer = push;
2516 continue;
2517 }
2518
2519 case 'y':
2520 if (strncmp (s, "%y", 2) != 0)
2521 break;
2522 s += 2;
2523 continue;
2524
2525 case 'u':
2526 case 'U':
2527 {
2528 /* Parse a sparclet cpreg. */
2529 int cpreg;
2530 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg))
2531 {
2532 error_message = _(": invalid cpreg name");
2533 goto error;
2534 }
2535 opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg));
2536 continue;
2537 }
2538
2539 default:
2540 as_fatal (_("failed sanity check."));
2541 } /* switch on arg code. */
2542
2543 /* Break out of for() loop. */
2544 break;
2545 } /* For each arg that we expect. */
2546
2547 error:
2548 if (match == 0)
2549 {
2550 /* Args don't match. */
2551 if (&insn[1] - sparc_opcodes < sparc_num_opcodes
2552 && (insn->name == insn[1].name
2553 || !strcmp (insn->name, insn[1].name)))
2554 {
2555 ++insn;
2556 s = argsStart;
2557 continue;
2558 }
2559 else
2560 {
2561 as_bad (_("Illegal operands%s"), error_message);
2562 return special_case;
2563 }
2564 }
2565 else
2566 {
2567 /* We have a match. Now see if the architecture is OK. */
2568 int needed_arch_mask = insn->architecture;
2569
2570 if (v9_arg_p)
2571 {
2572 needed_arch_mask &=
2573 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1);
2574 if (! needed_arch_mask)
2575 needed_arch_mask =
2576 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
2577 }
2578
2579 if (needed_arch_mask
2580 & SPARC_OPCODE_SUPPORTED (current_architecture))
2581 /* OK. */
2582 ;
2583 /* Can we bump up the architecture? */
2584 else if (needed_arch_mask
2585 & SPARC_OPCODE_SUPPORTED (max_architecture))
2586 {
2587 enum sparc_opcode_arch_val needed_architecture =
2588 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture)
2589 & needed_arch_mask);
2590
2591 assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX);
2592 if (warn_on_bump
2593 && needed_architecture > warn_after_architecture)
2594 {
2595 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
2596 sparc_opcode_archs[current_architecture].name,
2597 sparc_opcode_archs[needed_architecture].name,
2598 str);
2599 warn_after_architecture = needed_architecture;
2600 }
2601 current_architecture = needed_architecture;
2602 }
2603 /* Conflict. */
2604 /* ??? This seems to be a bit fragile. What if the next entry in
2605 the opcode table is the one we want and it is supported?
2606 It is possible to arrange the table today so that this can't
2607 happen but what about tomorrow? */
2608 else
2609 {
2610 int arch, printed_one_p = 0;
2611 char *p;
2612 char required_archs[SPARC_OPCODE_ARCH_MAX * 16];
2613
2614 /* Create a list of the architectures that support the insn. */
2615 needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture);
2616 p = required_archs;
2617 arch = sparc_ffs (needed_arch_mask);
2618 while ((1 << arch) <= needed_arch_mask)
2619 {
2620 if ((1 << arch) & needed_arch_mask)
2621 {
2622 if (printed_one_p)
2623 *p++ = '|';
2624 strcpy (p, sparc_opcode_archs[arch].name);
2625 p += strlen (p);
2626 printed_one_p = 1;
2627 }
2628 ++arch;
2629 }
2630
2631 as_bad (_("Architecture mismatch on \"%s\"."), str);
2632 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
2633 required_archs,
2634 sparc_opcode_archs[max_architecture].name);
2635 return special_case;
2636 }
2637 } /* If no match. */
2638
2639 break;
2640 } /* Forever looking for a match. */
2641
2642 the_insn.opcode = opcode;
2643 return special_case;
2644 }
2645
2646 /* Parse an argument that can be expressed as a keyword.
2647 (eg: #StoreStore or %ccfr).
2648 The result is a boolean indicating success.
2649 If successful, INPUT_POINTER is updated. */
2650
2651 static int
2652 parse_keyword_arg (lookup_fn, input_pointerP, valueP)
2653 int (*lookup_fn) PARAMS ((const char *));
2654 char **input_pointerP;
2655 int *valueP;
2656 {
2657 int value;
2658 char c, *p, *q;
2659
2660 p = *input_pointerP;
2661 for (q = p + (*p == '#' || *p == '%');
2662 isalnum ((unsigned char) *q) || *q == '_';
2663 ++q)
2664 continue;
2665 c = *q;
2666 *q = 0;
2667 value = (*lookup_fn) (p);
2668 *q = c;
2669 if (value == -1)
2670 return 0;
2671 *valueP = value;
2672 *input_pointerP = q;
2673 return 1;
2674 }
2675
2676 /* Parse an argument that is a constant expression.
2677 The result is a boolean indicating success. */
2678
2679 static int
2680 parse_const_expr_arg (input_pointerP, valueP)
2681 char **input_pointerP;
2682 int *valueP;
2683 {
2684 char *save = input_line_pointer;
2685 expressionS exp;
2686
2687 input_line_pointer = *input_pointerP;
2688 /* The next expression may be something other than a constant
2689 (say if we're not processing the right variant of the insn).
2690 Don't call expression unless we're sure it will succeed as it will
2691 signal an error (which we want to defer until later). */
2692 /* FIXME: It might be better to define md_operand and have it recognize
2693 things like %asi, etc. but continuing that route through to the end
2694 is a lot of work. */
2695 if (*input_line_pointer == '%')
2696 {
2697 input_line_pointer = save;
2698 return 0;
2699 }
2700 expression (&exp);
2701 *input_pointerP = input_line_pointer;
2702 input_line_pointer = save;
2703 if (exp.X_op != O_constant)
2704 return 0;
2705 *valueP = exp.X_add_number;
2706 return 1;
2707 }
2708
2709 /* Subroutine of sparc_ip to parse an expression. */
2710
2711 static int
2712 get_expression (str)
2713 char *str;
2714 {
2715 char *save_in;
2716 segT seg;
2717
2718 save_in = input_line_pointer;
2719 input_line_pointer = str;
2720 seg = expression (&the_insn.exp);
2721 if (seg != absolute_section
2722 && seg != text_section
2723 && seg != data_section
2724 && seg != bss_section
2725 && seg != undefined_section)
2726 {
2727 the_insn.error = _("bad segment");
2728 expr_end = input_line_pointer;
2729 input_line_pointer = save_in;
2730 return 1;
2731 }
2732 expr_end = input_line_pointer;
2733 input_line_pointer = save_in;
2734 return 0;
2735 }
2736
2737 /* Subroutine of md_assemble to output one insn. */
2738
2739 static void
2740 output_insn (insn, the_insn)
2741 const struct sparc_opcode *insn;
2742 struct sparc_it *the_insn;
2743 {
2744 char *toP = frag_more (4);
2745
2746 /* Put out the opcode. */
2747 if (INSN_BIG_ENDIAN)
2748 number_to_chars_bigendian (toP, (valueT) the_insn->opcode, 4);
2749 else
2750 number_to_chars_littleendian (toP, (valueT) the_insn->opcode, 4);
2751
2752 /* Put out the symbol-dependent stuff. */
2753 if (the_insn->reloc != BFD_RELOC_NONE)
2754 {
2755 fixS *fixP = fix_new_exp (frag_now, /* Which frag. */
2756 (toP - frag_now->fr_literal), /* Where. */
2757 4, /* Size. */
2758 &the_insn->exp,
2759 the_insn->pcrel,
2760 the_insn->reloc);
2761 /* Turn off overflow checking in fixup_segment. We'll do our
2762 own overflow checking in md_apply_fix3. This is necessary because
2763 the insn size is 4 and fixup_segment will signal an overflow for
2764 large 8 byte quantities. */
2765 fixP->fx_no_overflow = 1;
2766 if (the_insn->reloc == BFD_RELOC_SPARC_OLO10)
2767 fixP->tc_fix_data = the_insn->exp2.X_add_number;
2768 }
2769
2770 last_insn = insn;
2771 last_opcode = the_insn->opcode;
2772 }
2773 \f
2774 /* This is identical to the md_atof in m68k.c. I think this is right,
2775 but I'm not sure.
2776
2777 Turn a string in input_line_pointer into a floating point constant
2778 of type TYPE, and store the appropriate bytes in *LITP. The number
2779 of LITTLENUMS emitted is stored in *SIZEP. An error message is
2780 returned, or NULL on OK. */
2781
2782 /* Equal to MAX_PRECISION in atof-ieee.c. */
2783 #define MAX_LITTLENUMS 6
2784
2785 char *
2786 md_atof (type, litP, sizeP)
2787 char type;
2788 char *litP;
2789 int *sizeP;
2790 {
2791 int i, prec;
2792 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2793 char *t;
2794
2795 switch (type)
2796 {
2797 case 'f':
2798 case 'F':
2799 case 's':
2800 case 'S':
2801 prec = 2;
2802 break;
2803
2804 case 'd':
2805 case 'D':
2806 case 'r':
2807 case 'R':
2808 prec = 4;
2809 break;
2810
2811 case 'x':
2812 case 'X':
2813 prec = 6;
2814 break;
2815
2816 case 'p':
2817 case 'P':
2818 prec = 6;
2819 break;
2820
2821 default:
2822 *sizeP = 0;
2823 return _("Bad call to MD_ATOF()");
2824 }
2825
2826 t = atof_ieee (input_line_pointer, type, words);
2827 if (t)
2828 input_line_pointer = t;
2829 *sizeP = prec * sizeof (LITTLENUM_TYPE);
2830
2831 if (target_big_endian)
2832 {
2833 for (i = 0; i < prec; i++)
2834 {
2835 md_number_to_chars (litP, (valueT) words[i],
2836 sizeof (LITTLENUM_TYPE));
2837 litP += sizeof (LITTLENUM_TYPE);
2838 }
2839 }
2840 else
2841 {
2842 for (i = prec - 1; i >= 0; i--)
2843 {
2844 md_number_to_chars (litP, (valueT) words[i],
2845 sizeof (LITTLENUM_TYPE));
2846 litP += sizeof (LITTLENUM_TYPE);
2847 }
2848 }
2849
2850 return 0;
2851 }
2852
2853 /* Write a value out to the object file, using the appropriate
2854 endianness. */
2855
2856 void
2857 md_number_to_chars (buf, val, n)
2858 char *buf;
2859 valueT val;
2860 int n;
2861 {
2862 if (target_big_endian)
2863 number_to_chars_bigendian (buf, val, n);
2864 else if (target_little_endian_data
2865 && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC))
2866 /* Output debug words, which are not in allocated sections, as big
2867 endian. */
2868 number_to_chars_bigendian (buf, val, n);
2869 else if (target_little_endian_data || ! target_big_endian)
2870 number_to_chars_littleendian (buf, val, n);
2871 }
2872 \f
2873 /* Apply a fixS to the frags, now that we know the value it ought to
2874 hold. */
2875
2876 int
2877 md_apply_fix3 (fixP, value, segment)
2878 fixS *fixP;
2879 valueT *value;
2880 segT segment;
2881 {
2882 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
2883 offsetT val;
2884 long insn;
2885
2886 val = *value;
2887
2888 assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
2889
2890 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
2891
2892 #ifdef OBJ_ELF
2893 /* FIXME: SPARC ELF relocations don't use an addend in the data
2894 field itself. This whole approach should be somehow combined
2895 with the calls to bfd_install_relocation. Also, the value passed
2896 in by fixup_segment includes the value of a defined symbol. We
2897 don't want to include the value of an externally visible symbol. */
2898 if (fixP->fx_addsy != NULL)
2899 {
2900 if (symbol_used_in_reloc_p (fixP->fx_addsy)
2901 && (S_IS_EXTERNAL (fixP->fx_addsy)
2902 || S_IS_WEAK (fixP->fx_addsy)
2903 || (sparc_pic_code && ! fixP->fx_pcrel)
2904 || (S_GET_SEGMENT (fixP->fx_addsy) != segment
2905 && ((bfd_get_section_flags (stdoutput,
2906 S_GET_SEGMENT (fixP->fx_addsy))
2907 & SEC_LINK_ONCE) != 0
2908 || strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)),
2909 ".gnu.linkonce",
2910 sizeof ".gnu.linkonce" - 1) == 0)))
2911 && S_GET_SEGMENT (fixP->fx_addsy) != absolute_section
2912 && S_GET_SEGMENT (fixP->fx_addsy) != undefined_section
2913 && ! bfd_is_com_section (S_GET_SEGMENT (fixP->fx_addsy)))
2914 fixP->fx_addnumber -= S_GET_VALUE (fixP->fx_addsy);
2915 return 1;
2916 }
2917 #endif
2918
2919 /* This is a hack. There should be a better way to
2920 handle this. Probably in terms of howto fields, once
2921 we can look at these fixups in terms of howtos. */
2922 if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy)
2923 val += fixP->fx_where + fixP->fx_frag->fr_address;
2924
2925 #ifdef OBJ_AOUT
2926 /* FIXME: More ridiculous gas reloc hacking. If we are going to
2927 generate a reloc, then we just want to let the reloc addend set
2928 the value. We do not want to also stuff the addend into the
2929 object file. Including the addend in the object file works when
2930 doing a static link, because the linker will ignore the object
2931 file contents. However, the dynamic linker does not ignore the
2932 object file contents. */
2933 if (fixP->fx_addsy != NULL
2934 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2)
2935 val = 0;
2936
2937 /* When generating PIC code, we do not want an addend for a reloc
2938 against a local symbol. We adjust fx_addnumber to cancel out the
2939 value already included in val, and to also cancel out the
2940 adjustment which bfd_install_relocation will create. */
2941 if (sparc_pic_code
2942 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2
2943 && fixP->fx_addsy != NULL
2944 && ! S_IS_COMMON (fixP->fx_addsy)
2945 && symbol_section_p (fixP->fx_addsy))
2946 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
2947
2948 /* When generating PIC code, we need to fiddle to get
2949 bfd_install_relocation to do the right thing for a PC relative
2950 reloc against a local symbol which we are going to keep. */
2951 if (sparc_pic_code
2952 && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2
2953 && fixP->fx_addsy != NULL
2954 && (S_IS_EXTERNAL (fixP->fx_addsy)
2955 || S_IS_WEAK (fixP->fx_addsy))
2956 && S_IS_DEFINED (fixP->fx_addsy)
2957 && ! S_IS_COMMON (fixP->fx_addsy))
2958 {
2959 val = 0;
2960 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
2961 }
2962 #endif
2963
2964 /* If this is a data relocation, just output VAL. */
2965
2966 if (fixP->fx_r_type == BFD_RELOC_16)
2967 {
2968 md_number_to_chars (buf, val, 2);
2969 }
2970 else if (fixP->fx_r_type == BFD_RELOC_32
2971 || fixP->fx_r_type == BFD_RELOC_SPARC_REV32)
2972 {
2973 md_number_to_chars (buf, val, 4);
2974 }
2975 else if (fixP->fx_r_type == BFD_RELOC_64)
2976 {
2977 md_number_to_chars (buf, val, 8);
2978 }
2979 else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2980 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2981 {
2982 fixP->fx_done = 0;
2983 return 1;
2984 }
2985 else
2986 {
2987 /* It's a relocation against an instruction. */
2988
2989 if (INSN_BIG_ENDIAN)
2990 insn = bfd_getb32 ((unsigned char *) buf);
2991 else
2992 insn = bfd_getl32 ((unsigned char *) buf);
2993
2994 switch (fixP->fx_r_type)
2995 {
2996 case BFD_RELOC_32_PCREL_S2:
2997 val = val >> 2;
2998 /* FIXME: This increment-by-one deserves a comment of why it's
2999 being done! */
3000 if (! sparc_pic_code
3001 || fixP->fx_addsy == NULL
3002 || symbol_section_p (fixP->fx_addsy))
3003 ++val;
3004
3005 insn |= val & 0x3fffffff;
3006
3007 /* See if we have a delay slot. */
3008 if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix)
3009 {
3010 #define G0 0
3011 #define O7 15
3012 #define XCC (2 << 20)
3013 #define COND(x) (((x)&0xf)<<25)
3014 #define CONDA COND(0x8)
3015 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
3016 #define INSN_BA (F2(0,2) | CONDA)
3017 #define INSN_OR F3(2, 0x2, 0)
3018 #define INSN_NOP F2(0,4)
3019
3020 long delay;
3021
3022 /* If the instruction is a call with either:
3023 restore
3024 arithmetic instruction with rd == %o7
3025 where rs1 != %o7 and rs2 if it is register != %o7
3026 then we can optimize if the call destination is near
3027 by changing the call into a branch always. */
3028 if (INSN_BIG_ENDIAN)
3029 delay = bfd_getb32 ((unsigned char *) buf + 4);
3030 else
3031 delay = bfd_getl32 ((unsigned char *) buf + 4);
3032 if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2))
3033 break;
3034 if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */
3035 && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */
3036 || ((delay & RD (~0)) != RD (O7))))
3037 break;
3038 if ((delay & RS1 (~0)) == RS1 (O7)
3039 || ((delay & F3I (~0)) == 0
3040 && (delay & RS2 (~0)) == RS2 (O7)))
3041 break;
3042 /* Ensure the branch will fit into simm22. */
3043 if ((val & 0x3fe00000)
3044 && (val & 0x3fe00000) != 0x3fe00000)
3045 break;
3046 /* Check if the arch is v9 and branch will fit
3047 into simm19. */
3048 if (((val & 0x3c0000) == 0
3049 || (val & 0x3c0000) == 0x3c0000)
3050 && (sparc_arch_size == 64
3051 || current_architecture >= SPARC_OPCODE_ARCH_V9))
3052 /* ba,pt %xcc */
3053 insn = INSN_BPA | (val & 0x7ffff);
3054 else
3055 /* ba */
3056 insn = INSN_BA | (val & 0x3fffff);
3057 if (fixP->fx_where >= 4
3058 && ((delay & (0xffffffff ^ RS1 (~0)))
3059 == (INSN_OR | RD (O7) | RS2 (G0))))
3060 {
3061 long setter;
3062 int reg;
3063
3064 if (INSN_BIG_ENDIAN)
3065 setter = bfd_getb32 ((unsigned char *) buf - 4);
3066 else
3067 setter = bfd_getl32 ((unsigned char *) buf - 4);
3068 if ((setter & (0xffffffff ^ RD (~0)))
3069 != (INSN_OR | RS1 (O7) | RS2 (G0)))
3070 break;
3071 /* The sequence was
3072 or %o7, %g0, %rN
3073 call foo
3074 or %rN, %g0, %o7
3075
3076 If call foo was replaced with ba, replace
3077 or %rN, %g0, %o7 with nop. */
3078 reg = (delay & RS1 (~0)) >> 14;
3079 if (reg != ((setter & RD (~0)) >> 25)
3080 || reg == G0 || reg == O7)
3081 break;
3082
3083 if (INSN_BIG_ENDIAN)
3084 bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4);
3085 else
3086 bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4);
3087 }
3088 }
3089 break;
3090
3091 case BFD_RELOC_SPARC_11:
3092 if (! in_signed_range (val, 0x7ff))
3093 as_bad_where (fixP->fx_file, fixP->fx_line,
3094 _("relocation overflow"));
3095 insn |= val & 0x7ff;
3096 break;
3097
3098 case BFD_RELOC_SPARC_10:
3099 if (! in_signed_range (val, 0x3ff))
3100 as_bad_where (fixP->fx_file, fixP->fx_line,
3101 _("relocation overflow"));
3102 insn |= val & 0x3ff;
3103 break;
3104
3105 case BFD_RELOC_SPARC_7:
3106 if (! in_bitfield_range (val, 0x7f))
3107 as_bad_where (fixP->fx_file, fixP->fx_line,
3108 _("relocation overflow"));
3109 insn |= val & 0x7f;
3110 break;
3111
3112 case BFD_RELOC_SPARC_6:
3113 if (! in_bitfield_range (val, 0x3f))
3114 as_bad_where (fixP->fx_file, fixP->fx_line,
3115 _("relocation overflow"));
3116 insn |= val & 0x3f;
3117 break;
3118
3119 case BFD_RELOC_SPARC_5:
3120 if (! in_bitfield_range (val, 0x1f))
3121 as_bad_where (fixP->fx_file, fixP->fx_line,
3122 _("relocation overflow"));
3123 insn |= val & 0x1f;
3124 break;
3125
3126 case BFD_RELOC_SPARC_WDISP16:
3127 /* FIXME: simplify. */
3128 if (((val > 0) && (val & ~0x3fffc))
3129 || ((val < 0) && (~(val - 1) & ~0x3fffc)))
3130 as_bad_where (fixP->fx_file, fixP->fx_line,
3131 _("relocation overflow"));
3132 /* FIXME: The +1 deserves a comment. */
3133 val = (val >> 2) + 1;
3134 insn |= ((val & 0xc000) << 6) | (val & 0x3fff);
3135 break;
3136
3137 case BFD_RELOC_SPARC_WDISP19:
3138 /* FIXME: simplify. */
3139 if (((val > 0) && (val & ~0x1ffffc))
3140 || ((val < 0) && (~(val - 1) & ~0x1ffffc)))
3141 as_bad_where (fixP->fx_file, fixP->fx_line,
3142 _("relocation overflow"));
3143 /* FIXME: The +1 deserves a comment. */
3144 val = (val >> 2) + 1;
3145 insn |= val & 0x7ffff;
3146 break;
3147
3148 case BFD_RELOC_SPARC_HH22:
3149 val = BSR (val, 32);
3150 /* Fall through. */
3151
3152 case BFD_RELOC_SPARC_LM22:
3153 case BFD_RELOC_HI22:
3154 if (!fixP->fx_addsy)
3155 {
3156 insn |= (val >> 10) & 0x3fffff;
3157 }
3158 else
3159 {
3160 /* FIXME: Need comment explaining why we do this. */
3161 insn &= ~0xffff;
3162 }
3163 break;
3164
3165 case BFD_RELOC_SPARC22:
3166 if (val & ~0x003fffff)
3167 as_bad_where (fixP->fx_file, fixP->fx_line,
3168 _("relocation overflow"));
3169 insn |= (val & 0x3fffff);
3170 break;
3171
3172 case BFD_RELOC_SPARC_HM10:
3173 val = BSR (val, 32);
3174 /* Fall through. */
3175
3176 case BFD_RELOC_LO10:
3177 if (!fixP->fx_addsy)
3178 {
3179 insn |= val & 0x3ff;
3180 }
3181 else
3182 {
3183 /* FIXME: Need comment explaining why we do this. */
3184 insn &= ~0xff;
3185 }
3186 break;
3187
3188 case BFD_RELOC_SPARC_OLO10:
3189 val &= 0x3ff;
3190 val += fixP->tc_fix_data;
3191 /* Fall through. */
3192
3193 case BFD_RELOC_SPARC13:
3194 if (! in_signed_range (val, 0x1fff))
3195 as_bad_where (fixP->fx_file, fixP->fx_line,
3196 _("relocation overflow"));
3197 insn |= val & 0x1fff;
3198 break;
3199
3200 case BFD_RELOC_SPARC_WDISP22:
3201 val = (val >> 2) + 1;
3202 /* Fall through. */
3203 case BFD_RELOC_SPARC_BASE22:
3204 insn |= val & 0x3fffff;
3205 break;
3206
3207 case BFD_RELOC_SPARC_H44:
3208 if (!fixP->fx_addsy)
3209 {
3210 bfd_vma tval = val;
3211 tval >>= 22;
3212 insn |= tval & 0x3fffff;
3213 }
3214 break;
3215
3216 case BFD_RELOC_SPARC_M44:
3217 if (!fixP->fx_addsy)
3218 insn |= (val >> 12) & 0x3ff;
3219 break;
3220
3221 case BFD_RELOC_SPARC_L44:
3222 if (!fixP->fx_addsy)
3223 insn |= val & 0xfff;
3224 break;
3225
3226 case BFD_RELOC_SPARC_HIX22:
3227 if (!fixP->fx_addsy)
3228 {
3229 val ^= ~(offsetT) 0;
3230 insn |= (val >> 10) & 0x3fffff;
3231 }
3232 break;
3233
3234 case BFD_RELOC_SPARC_LOX10:
3235 if (!fixP->fx_addsy)
3236 insn |= 0x1c00 | (val & 0x3ff);
3237 break;
3238
3239 case BFD_RELOC_NONE:
3240 default:
3241 as_bad_where (fixP->fx_file, fixP->fx_line,
3242 _("bad or unhandled relocation type: 0x%02x"),
3243 fixP->fx_r_type);
3244 break;
3245 }
3246
3247 if (INSN_BIG_ENDIAN)
3248 bfd_putb32 (insn, (unsigned char *) buf);
3249 else
3250 bfd_putl32 (insn, (unsigned char *) buf);
3251 }
3252
3253 /* Are we finished with this relocation now? */
3254 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
3255 fixP->fx_done = 1;
3256
3257 return 1;
3258 }
3259
3260 /* Translate internal representation of relocation info to BFD target
3261 format. */
3262
3263 arelent **
3264 tc_gen_reloc (section, fixp)
3265 asection *section;
3266 fixS *fixp;
3267 {
3268 static arelent *relocs[3];
3269 arelent *reloc;
3270 bfd_reloc_code_real_type code;
3271
3272 relocs[0] = reloc = (arelent *) xmalloc (sizeof (arelent));
3273 relocs[1] = NULL;
3274
3275 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3276 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
3277 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3278
3279 switch (fixp->fx_r_type)
3280 {
3281 case BFD_RELOC_16:
3282 case BFD_RELOC_32:
3283 case BFD_RELOC_HI22:
3284 case BFD_RELOC_LO10:
3285 case BFD_RELOC_32_PCREL_S2:
3286 case BFD_RELOC_SPARC13:
3287 case BFD_RELOC_SPARC22:
3288 case BFD_RELOC_SPARC_BASE13:
3289 case BFD_RELOC_SPARC_WDISP16:
3290 case BFD_RELOC_SPARC_WDISP19:
3291 case BFD_RELOC_SPARC_WDISP22:
3292 case BFD_RELOC_64:
3293 case BFD_RELOC_SPARC_5:
3294 case BFD_RELOC_SPARC_6:
3295 case BFD_RELOC_SPARC_7:
3296 case BFD_RELOC_SPARC_10:
3297 case BFD_RELOC_SPARC_11:
3298 case BFD_RELOC_SPARC_HH22:
3299 case BFD_RELOC_SPARC_HM10:
3300 case BFD_RELOC_SPARC_LM22:
3301 case BFD_RELOC_SPARC_PC_HH22:
3302 case BFD_RELOC_SPARC_PC_HM10:
3303 case BFD_RELOC_SPARC_PC_LM22:
3304 case BFD_RELOC_SPARC_H44:
3305 case BFD_RELOC_SPARC_M44:
3306 case BFD_RELOC_SPARC_L44:
3307 case BFD_RELOC_SPARC_HIX22:
3308 case BFD_RELOC_SPARC_LOX10:
3309 case BFD_RELOC_SPARC_REV32:
3310 case BFD_RELOC_SPARC_OLO10:
3311 case BFD_RELOC_VTABLE_ENTRY:
3312 case BFD_RELOC_VTABLE_INHERIT:
3313 code = fixp->fx_r_type;
3314 break;
3315 default:
3316 abort ();
3317 return NULL;
3318 }
3319
3320 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
3321 /* If we are generating PIC code, we need to generate a different
3322 set of relocs. */
3323
3324 #ifdef OBJ_ELF
3325 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3326 #else
3327 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
3328 #endif
3329
3330 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */
3331
3332 if (sparc_pic_code)
3333 {
3334 switch (code)
3335 {
3336 case BFD_RELOC_32_PCREL_S2:
3337 if (! S_IS_DEFINED (fixp->fx_addsy)
3338 || S_IS_COMMON (fixp->fx_addsy)
3339 || S_IS_EXTERNAL (fixp->fx_addsy)
3340 || S_IS_WEAK (fixp->fx_addsy))
3341 code = BFD_RELOC_SPARC_WPLT30;
3342 break;
3343 case BFD_RELOC_HI22:
3344 if (fixp->fx_addsy != NULL
3345 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3346 code = BFD_RELOC_SPARC_PC22;
3347 else
3348 code = BFD_RELOC_SPARC_GOT22;
3349 break;
3350 case BFD_RELOC_LO10:
3351 if (fixp->fx_addsy != NULL
3352 && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3353 code = BFD_RELOC_SPARC_PC10;
3354 else
3355 code = BFD_RELOC_SPARC_GOT10;
3356 break;
3357 case BFD_RELOC_SPARC13:
3358 code = BFD_RELOC_SPARC_GOT13;
3359 break;
3360 default:
3361 break;
3362 }
3363 }
3364 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
3365
3366 if (code == BFD_RELOC_SPARC_OLO10)
3367 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10);
3368 else
3369 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
3370 if (reloc->howto == 0)
3371 {
3372 as_bad_where (fixp->fx_file, fixp->fx_line,
3373 _("internal error: can't export reloc type %d (`%s')"),
3374 fixp->fx_r_type, bfd_get_reloc_code_name (code));
3375 xfree (reloc);
3376 relocs[0] = NULL;
3377 return relocs;
3378 }
3379
3380 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
3381 #ifdef OBJ_AOUT
3382
3383 if (reloc->howto->pc_relative == 0
3384 || code == BFD_RELOC_SPARC_PC10
3385 || code == BFD_RELOC_SPARC_PC22)
3386 reloc->addend = fixp->fx_addnumber;
3387 else if (sparc_pic_code
3388 && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2
3389 && fixp->fx_addsy != NULL
3390 && (S_IS_EXTERNAL (fixp->fx_addsy)
3391 || S_IS_WEAK (fixp->fx_addsy))
3392 && S_IS_DEFINED (fixp->fx_addsy)
3393 && ! S_IS_COMMON (fixp->fx_addsy))
3394 reloc->addend = fixp->fx_addnumber;
3395 else
3396 reloc->addend = fixp->fx_offset - reloc->address;
3397
3398 #else /* elf or coff */
3399
3400 if (reloc->howto->pc_relative == 0
3401 || code == BFD_RELOC_SPARC_PC10
3402 || code == BFD_RELOC_SPARC_PC22)
3403 reloc->addend = fixp->fx_addnumber;
3404 else if (symbol_section_p (fixp->fx_addsy))
3405 reloc->addend = (section->vma
3406 + fixp->fx_addnumber
3407 + md_pcrel_from (fixp));
3408 else
3409 reloc->addend = fixp->fx_offset;
3410 #endif
3411
3412 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
3413 on the same location. */
3414 if (code == BFD_RELOC_SPARC_OLO10)
3415 {
3416 relocs[1] = reloc = (arelent *) xmalloc (sizeof (arelent));
3417 relocs[2] = NULL;
3418
3419 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3420 *reloc->sym_ptr_ptr
3421 = symbol_get_bfdsym (section_symbol (absolute_section));
3422 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3423 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13);
3424 reloc->addend = fixp->tc_fix_data;
3425 }
3426
3427 return relocs;
3428 }
3429 \f
3430 /* We have no need to default values of symbols. */
3431
3432 symbolS *
3433 md_undefined_symbol (name)
3434 char *name ATTRIBUTE_UNUSED;
3435 {
3436 return 0;
3437 }
3438
3439 /* Round up a section size to the appropriate boundary. */
3440
3441 valueT
3442 md_section_align (segment, size)
3443 segT segment ATTRIBUTE_UNUSED;
3444 valueT size;
3445 {
3446 #ifndef OBJ_ELF
3447 /* This is not right for ELF; a.out wants it, and COFF will force
3448 the alignment anyways. */
3449 valueT align = ((valueT) 1
3450 << (valueT) bfd_get_section_alignment (stdoutput, segment));
3451 valueT newsize;
3452
3453 /* Turn alignment value into a mask. */
3454 align--;
3455 newsize = (size + align) & ~align;
3456 return newsize;
3457 #else
3458 return size;
3459 #endif
3460 }
3461
3462 /* Exactly what point is a PC-relative offset relative TO?
3463 On the sparc, they're relative to the address of the offset, plus
3464 its size. This gets us to the following instruction.
3465 (??? Is this right? FIXME-SOON) */
3466 long
3467 md_pcrel_from (fixP)
3468 fixS *fixP;
3469 {
3470 long ret;
3471
3472 ret = fixP->fx_where + fixP->fx_frag->fr_address;
3473 if (! sparc_pic_code
3474 || fixP->fx_addsy == NULL
3475 || symbol_section_p (fixP->fx_addsy))
3476 ret += fixP->fx_size;
3477 return ret;
3478 }
3479 \f
3480 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
3481 of two. */
3482
3483 static int
3484 log2 (value)
3485 int value;
3486 {
3487 int shift;
3488
3489 if (value <= 0)
3490 return -1;
3491
3492 for (shift = 0; (value & 1) == 0; value >>= 1)
3493 ++shift;
3494
3495 return (value == 1) ? shift : -1;
3496 }
3497
3498 /* Sort of like s_lcomm. */
3499
3500 #ifndef OBJ_ELF
3501 static int max_alignment = 15;
3502 #endif
3503
3504 static void
3505 s_reserve (ignore)
3506 int ignore ATTRIBUTE_UNUSED;
3507 {
3508 char *name;
3509 char *p;
3510 char c;
3511 int align;
3512 int size;
3513 int temp;
3514 symbolS *symbolP;
3515
3516 name = input_line_pointer;
3517 c = get_symbol_end ();
3518 p = input_line_pointer;
3519 *p = c;
3520 SKIP_WHITESPACE ();
3521
3522 if (*input_line_pointer != ',')
3523 {
3524 as_bad (_("Expected comma after name"));
3525 ignore_rest_of_line ();
3526 return;
3527 }
3528
3529 ++input_line_pointer;
3530
3531 if ((size = get_absolute_expression ()) < 0)
3532 {
3533 as_bad (_("BSS length (%d.) <0! Ignored."), size);
3534 ignore_rest_of_line ();
3535 return;
3536 } /* Bad length. */
3537
3538 *p = 0;
3539 symbolP = symbol_find_or_make (name);
3540 *p = c;
3541
3542 if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0
3543 && strncmp (input_line_pointer, ",\".bss\"", 7) != 0)
3544 {
3545 as_bad (_("bad .reserve segment -- expected BSS segment"));
3546 return;
3547 }
3548
3549 if (input_line_pointer[2] == '.')
3550 input_line_pointer += 7;
3551 else
3552 input_line_pointer += 6;
3553 SKIP_WHITESPACE ();
3554
3555 if (*input_line_pointer == ',')
3556 {
3557 ++input_line_pointer;
3558
3559 SKIP_WHITESPACE ();
3560 if (*input_line_pointer == '\n')
3561 {
3562 as_bad (_("missing alignment"));
3563 ignore_rest_of_line ();
3564 return;
3565 }
3566
3567 align = (int) get_absolute_expression ();
3568
3569 #ifndef OBJ_ELF
3570 if (align > max_alignment)
3571 {
3572 align = max_alignment;
3573 as_warn (_("alignment too large; assuming %d"), align);
3574 }
3575 #endif
3576
3577 if (align < 0)
3578 {
3579 as_bad (_("negative alignment"));
3580 ignore_rest_of_line ();
3581 return;
3582 }
3583
3584 if (align != 0)
3585 {
3586 temp = log2 (align);
3587 if (temp < 0)
3588 {
3589 as_bad (_("alignment not a power of 2"));
3590 ignore_rest_of_line ();
3591 return;
3592 }
3593
3594 align = temp;
3595 }
3596
3597 record_alignment (bss_section, align);
3598 }
3599 else
3600 align = 0;
3601
3602 if (!S_IS_DEFINED (symbolP)
3603 #ifdef OBJ_AOUT
3604 && S_GET_OTHER (symbolP) == 0
3605 && S_GET_DESC (symbolP) == 0
3606 #endif
3607 )
3608 {
3609 if (! need_pass_2)
3610 {
3611 char *pfrag;
3612 segT current_seg = now_seg;
3613 subsegT current_subseg = now_subseg;
3614
3615 /* Switch to bss. */
3616 subseg_set (bss_section, 1);
3617
3618 if (align)
3619 /* Do alignment. */
3620 frag_align (align, 0, 0);
3621
3622 /* Detach from old frag. */
3623 if (S_GET_SEGMENT (symbolP) == bss_section)
3624 symbol_get_frag (symbolP)->fr_symbol = NULL;
3625
3626 symbol_set_frag (symbolP, frag_now);
3627 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3628 (offsetT) size, (char *) 0);
3629 *pfrag = 0;
3630
3631 S_SET_SEGMENT (symbolP, bss_section);
3632
3633 subseg_set (current_seg, current_subseg);
3634
3635 #ifdef OBJ_ELF
3636 S_SET_SIZE (symbolP, size);
3637 #endif
3638 }
3639 }
3640 else
3641 {
3642 as_warn ("Ignoring attempt to re-define symbol %s",
3643 S_GET_NAME (symbolP));
3644 } /* if not redefining. */
3645
3646 demand_empty_rest_of_line ();
3647 }
3648
3649 static void
3650 s_common (ignore)
3651 int ignore ATTRIBUTE_UNUSED;
3652 {
3653 char *name;
3654 char c;
3655 char *p;
3656 int temp, size;
3657 symbolS *symbolP;
3658
3659 name = input_line_pointer;
3660 c = get_symbol_end ();
3661 /* Just after name is now '\0'. */
3662 p = input_line_pointer;
3663 *p = c;
3664 SKIP_WHITESPACE ();
3665 if (*input_line_pointer != ',')
3666 {
3667 as_bad (_("Expected comma after symbol-name"));
3668 ignore_rest_of_line ();
3669 return;
3670 }
3671
3672 /* Skip ','. */
3673 input_line_pointer++;
3674
3675 if ((temp = get_absolute_expression ()) < 0)
3676 {
3677 as_bad (_(".COMMon length (%d.) <0! Ignored."), temp);
3678 ignore_rest_of_line ();
3679 return;
3680 }
3681 size = temp;
3682 *p = 0;
3683 symbolP = symbol_find_or_make (name);
3684 *p = c;
3685 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
3686 {
3687 as_bad (_("Ignoring attempt to re-define symbol"));
3688 ignore_rest_of_line ();
3689 return;
3690 }
3691 if (S_GET_VALUE (symbolP) != 0)
3692 {
3693 if (S_GET_VALUE (symbolP) != (valueT) size)
3694 {
3695 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %d."),
3696 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), size);
3697 }
3698 }
3699 else
3700 {
3701 #ifndef OBJ_ELF
3702 S_SET_VALUE (symbolP, (valueT) size);
3703 S_SET_EXTERNAL (symbolP);
3704 #endif
3705 }
3706 know (symbol_get_frag (symbolP) == &zero_address_frag);
3707 if (*input_line_pointer != ',')
3708 {
3709 as_bad (_("Expected comma after common length"));
3710 ignore_rest_of_line ();
3711 return;
3712 }
3713 input_line_pointer++;
3714 SKIP_WHITESPACE ();
3715 if (*input_line_pointer != '"')
3716 {
3717 temp = get_absolute_expression ();
3718
3719 #ifndef OBJ_ELF
3720 if (temp > max_alignment)
3721 {
3722 temp = max_alignment;
3723 as_warn (_("alignment too large; assuming %d"), temp);
3724 }
3725 #endif
3726
3727 if (temp < 0)
3728 {
3729 as_bad (_("negative alignment"));
3730 ignore_rest_of_line ();
3731 return;
3732 }
3733
3734 #ifdef OBJ_ELF
3735 if (symbol_get_obj (symbolP)->local)
3736 {
3737 segT old_sec;
3738 int old_subsec;
3739 char *p;
3740 int align;
3741
3742 old_sec = now_seg;
3743 old_subsec = now_subseg;
3744
3745 if (temp == 0)
3746 align = 0;
3747 else
3748 align = log2 (temp);
3749
3750 if (align < 0)
3751 {
3752 as_bad (_("alignment not a power of 2"));
3753 ignore_rest_of_line ();
3754 return;
3755 }
3756
3757 record_alignment (bss_section, align);
3758 subseg_set (bss_section, 0);
3759 if (align)
3760 frag_align (align, 0, 0);
3761 if (S_GET_SEGMENT (symbolP) == bss_section)
3762 symbol_get_frag (symbolP)->fr_symbol = 0;
3763 symbol_set_frag (symbolP, frag_now);
3764 p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3765 (offsetT) size, (char *) 0);
3766 *p = 0;
3767 S_SET_SEGMENT (symbolP, bss_section);
3768 S_CLEAR_EXTERNAL (symbolP);
3769 S_SET_SIZE (symbolP, size);
3770 subseg_set (old_sec, old_subsec);
3771 }
3772 else
3773 #endif /* OBJ_ELF */
3774 {
3775 allocate_common:
3776 S_SET_VALUE (symbolP, (valueT) size);
3777 #ifdef OBJ_ELF
3778 S_SET_ALIGN (symbolP, temp);
3779 S_SET_SIZE (symbolP, size);
3780 #endif
3781 S_SET_EXTERNAL (symbolP);
3782 S_SET_SEGMENT (symbolP, bfd_com_section_ptr);
3783 }
3784 }
3785 else
3786 {
3787 input_line_pointer++;
3788 /* @@ Some use the dot, some don't. Can we get some consistency?? */
3789 if (*input_line_pointer == '.')
3790 input_line_pointer++;
3791 /* @@ Some say data, some say bss. */
3792 if (strncmp (input_line_pointer, "bss\"", 4)
3793 && strncmp (input_line_pointer, "data\"", 5))
3794 {
3795 while (*--input_line_pointer != '"')
3796 ;
3797 input_line_pointer--;
3798 goto bad_common_segment;
3799 }
3800 while (*input_line_pointer++ != '"')
3801 ;
3802 goto allocate_common;
3803 }
3804
3805 #ifdef BFD_ASSEMBLER
3806 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
3807 #endif
3808
3809 demand_empty_rest_of_line ();
3810 return;
3811
3812 {
3813 bad_common_segment:
3814 p = input_line_pointer;
3815 while (*p && *p != '\n')
3816 p++;
3817 c = *p;
3818 *p = '\0';
3819 as_bad (_("bad .common segment %s"), input_line_pointer + 1);
3820 *p = c;
3821 input_line_pointer = p;
3822 ignore_rest_of_line ();
3823 return;
3824 }
3825 }
3826
3827 /* Handle the .empty pseudo-op. This supresses the warnings about
3828 invalid delay slot usage. */
3829
3830 static void
3831 s_empty (ignore)
3832 int ignore ATTRIBUTE_UNUSED;
3833 {
3834 /* The easy way to implement is to just forget about the last
3835 instruction. */
3836 last_insn = NULL;
3837 }
3838
3839 static void
3840 s_seg (ignore)
3841 int ignore ATTRIBUTE_UNUSED;
3842 {
3843
3844 if (strncmp (input_line_pointer, "\"text\"", 6) == 0)
3845 {
3846 input_line_pointer += 6;
3847 s_text (0);
3848 return;
3849 }
3850 if (strncmp (input_line_pointer, "\"data\"", 6) == 0)
3851 {
3852 input_line_pointer += 6;
3853 s_data (0);
3854 return;
3855 }
3856 if (strncmp (input_line_pointer, "\"data1\"", 7) == 0)
3857 {
3858 input_line_pointer += 7;
3859 s_data1 ();
3860 return;
3861 }
3862 if (strncmp (input_line_pointer, "\"bss\"", 5) == 0)
3863 {
3864 input_line_pointer += 5;
3865 /* We only support 2 segments -- text and data -- for now, so
3866 things in the "bss segment" will have to go into data for now.
3867 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
3868 subseg_set (data_section, 255); /* FIXME-SOMEDAY. */
3869 return;
3870 }
3871 as_bad (_("Unknown segment type"));
3872 demand_empty_rest_of_line ();
3873 }
3874
3875 static void
3876 s_data1 ()
3877 {
3878 subseg_set (data_section, 1);
3879 demand_empty_rest_of_line ();
3880 }
3881
3882 static void
3883 s_proc (ignore)
3884 int ignore ATTRIBUTE_UNUSED;
3885 {
3886 while (!is_end_of_line[(unsigned char) *input_line_pointer])
3887 {
3888 ++input_line_pointer;
3889 }
3890 ++input_line_pointer;
3891 }
3892
3893 /* This static variable is set by s_uacons to tell sparc_cons_align
3894 that the expession does not need to be aligned. */
3895
3896 static int sparc_no_align_cons = 0;
3897
3898 /* This handles the unaligned space allocation pseudo-ops, such as
3899 .uaword. .uaword is just like .word, but the value does not need
3900 to be aligned. */
3901
3902 static void
3903 s_uacons (bytes)
3904 int bytes;
3905 {
3906 /* Tell sparc_cons_align not to align this value. */
3907 sparc_no_align_cons = 1;
3908 cons (bytes);
3909 }
3910
3911 /* This handles the native word allocation pseudo-op .nword.
3912 For sparc_arch_size 32 it is equivalent to .word, for
3913 sparc_arch_size 64 it is equivalent to .xword. */
3914
3915 static void
3916 s_ncons (bytes)
3917 int bytes ATTRIBUTE_UNUSED;
3918 {
3919 cons (sparc_arch_size == 32 ? 4 : 8);
3920 }
3921
3922 #ifdef OBJ_ELF
3923 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
3924 global register.
3925 The syntax is:
3926
3927 .register %g[2367],{#scratch|symbolname|#ignore}
3928 */
3929
3930 static void
3931 s_register (ignore)
3932 int ignore ATTRIBUTE_UNUSED;
3933 {
3934 char c;
3935 int reg;
3936 int flags;
3937 const char *regname;
3938
3939 if (input_line_pointer[0] != '%'
3940 || input_line_pointer[1] != 'g'
3941 || ((input_line_pointer[2] & ~1) != '2'
3942 && (input_line_pointer[2] & ~1) != '6')
3943 || input_line_pointer[3] != ',')
3944 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
3945 reg = input_line_pointer[2] - '0';
3946 input_line_pointer += 4;
3947
3948 if (*input_line_pointer == '#')
3949 {
3950 ++input_line_pointer;
3951 regname = input_line_pointer;
3952 c = get_symbol_end ();
3953 if (strcmp (regname, "scratch") && strcmp (regname, "ignore"))
3954 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
3955 if (regname[0] == 'i')
3956 regname = NULL;
3957 else
3958 regname = "";
3959 }
3960 else
3961 {
3962 regname = input_line_pointer;
3963 c = get_symbol_end ();
3964 }
3965 if (sparc_arch_size == 64)
3966 {
3967 if (globals[reg])
3968 {
3969 if ((regname && globals[reg] != (symbolS *) 1
3970 && strcmp (S_GET_NAME (globals[reg]), regname))
3971 || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1)))
3972 as_bad (_("redefinition of global register"));
3973 }
3974 else
3975 {
3976 if (regname == NULL)
3977 globals[reg] = (symbolS *) 1;
3978 else
3979 {
3980 if (*regname)
3981 {
3982 if (symbol_find (regname))
3983 as_bad (_("Register symbol %s already defined."),
3984 regname);
3985 }
3986 globals[reg] = symbol_make (regname);
3987 flags = symbol_get_bfdsym (globals[reg])->flags;
3988 if (! *regname)
3989 flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK);
3990 if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK)))
3991 flags |= BSF_GLOBAL;
3992 symbol_get_bfdsym (globals[reg])->flags = flags;
3993 S_SET_VALUE (globals[reg], (valueT) reg);
3994 S_SET_ALIGN (globals[reg], reg);
3995 S_SET_SIZE (globals[reg], 0);
3996 /* Although we actually want undefined_section here,
3997 we have to use absolute_section, because otherwise
3998 generic as code will make it a COM section.
3999 We fix this up in sparc_adjust_symtab. */
4000 S_SET_SEGMENT (globals[reg], absolute_section);
4001 S_SET_OTHER (globals[reg], 0);
4002 elf_symbol (symbol_get_bfdsym (globals[reg]))
4003 ->internal_elf_sym.st_info =
4004 ELF_ST_INFO(STB_GLOBAL, STT_REGISTER);
4005 elf_symbol (symbol_get_bfdsym (globals[reg]))
4006 ->internal_elf_sym.st_shndx = SHN_UNDEF;
4007 }
4008 }
4009 }
4010
4011 *input_line_pointer = c;
4012
4013 demand_empty_rest_of_line ();
4014 }
4015
4016 /* Adjust the symbol table. We set undefined sections for STT_REGISTER
4017 symbols which need it. */
4018
4019 void
4020 sparc_adjust_symtab ()
4021 {
4022 symbolS *sym;
4023
4024 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
4025 {
4026 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4027 ->internal_elf_sym.st_info) != STT_REGISTER)
4028 continue;
4029
4030 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4031 ->internal_elf_sym.st_shndx != SHN_UNDEF))
4032 continue;
4033
4034 S_SET_SEGMENT (sym, undefined_section);
4035 }
4036 }
4037 #endif
4038
4039 /* If the --enforce-aligned-data option is used, we require .word,
4040 et. al., to be aligned correctly. We do it by setting up an
4041 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
4042 no unexpected alignment was introduced.
4043
4044 The SunOS and Solaris native assemblers enforce aligned data by
4045 default. We don't want to do that, because gcc can deliberately
4046 generate misaligned data if the packed attribute is used. Instead,
4047 we permit misaligned data by default, and permit the user to set an
4048 option to check for it. */
4049
4050 void
4051 sparc_cons_align (nbytes)
4052 int nbytes;
4053 {
4054 int nalign;
4055 char *p;
4056
4057 /* Only do this if we are enforcing aligned data. */
4058 if (! enforce_aligned_data)
4059 return;
4060
4061 if (sparc_no_align_cons)
4062 {
4063 /* This is an unaligned pseudo-op. */
4064 sparc_no_align_cons = 0;
4065 return;
4066 }
4067
4068 nalign = log2 (nbytes);
4069 if (nalign == 0)
4070 return;
4071
4072 assert (nalign > 0);
4073
4074 if (now_seg == absolute_section)
4075 {
4076 if ((abs_section_offset & ((1 << nalign) - 1)) != 0)
4077 as_bad (_("misaligned data"));
4078 return;
4079 }
4080
4081 p = frag_var (rs_align_code, 1, 1, (relax_substateT) 0,
4082 (symbolS *) NULL, (offsetT) nalign, (char *) NULL);
4083
4084 record_alignment (now_seg, nalign);
4085 }
4086
4087 /* This is where we do the unexpected alignment check.
4088 This is called from HANDLE_ALIGN in tc-sparc.h. */
4089
4090 void
4091 sparc_handle_align (fragp)
4092 fragS *fragp;
4093 {
4094 if (fragp->fr_type == rs_align_code && !fragp->fr_subtype
4095 && fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix != 0)
4096 as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data"));
4097 if (fragp->fr_type == rs_align_code && fragp->fr_subtype == 1024)
4098 {
4099 int count =
4100 fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
4101
4102 if (count >= 4
4103 && !(count & 3)
4104 && count <= 1024
4105 && !((long) (fragp->fr_literal + fragp->fr_fix) & 3))
4106 {
4107 unsigned *p = (unsigned *) (fragp->fr_literal + fragp->fr_fix);
4108 int i;
4109
4110 for (i = 0; i < count; i += 4, p++)
4111 if (INSN_BIG_ENDIAN)
4112 /* Emit nops. */
4113 number_to_chars_bigendian ((char *) p, 0x01000000, 4);
4114 else
4115 number_to_chars_littleendian ((char *) p, 0x10000000, 4);
4116
4117 if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8)
4118 {
4119 char *waddr = &fragp->fr_literal[fragp->fr_fix];
4120 unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */
4121 if (INSN_BIG_ENDIAN)
4122 number_to_chars_bigendian (waddr, wval, 4);
4123 else
4124 number_to_chars_littleendian (waddr, wval, 4);
4125 }
4126 fragp->fr_var = count;
4127 }
4128 }
4129 }
4130
4131 #ifdef OBJ_ELF
4132 /* Some special processing for a Sparc ELF file. */
4133
4134 void
4135 sparc_elf_final_processing ()
4136 {
4137 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4138 sort of BFD interface for this. */
4139 if (sparc_arch_size == 64)
4140 {
4141 switch (sparc_memory_model)
4142 {
4143 case MM_RMO:
4144 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO;
4145 break;
4146 case MM_PSO:
4147 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO;
4148 break;
4149 default:
4150 break;
4151 }
4152 }
4153 else if (current_architecture >= SPARC_OPCODE_ARCH_V9)
4154 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS;
4155 if (current_architecture == SPARC_OPCODE_ARCH_V9A)
4156 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1;
4157 else if (current_architecture == SPARC_OPCODE_ARCH_V9B)
4158 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3;
4159 }
4160 #endif
4161
4162 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4163 reloc for a cons. We could use the definition there, except that
4164 we want to handle little endian relocs specially. */
4165
4166 void
4167 cons_fix_new_sparc (frag, where, nbytes, exp)
4168 fragS *frag;
4169 int where;
4170 unsigned int nbytes;
4171 expressionS *exp;
4172 {
4173 bfd_reloc_code_real_type r;
4174
4175 r = (nbytes == 1 ? BFD_RELOC_8 :
4176 (nbytes == 2 ? BFD_RELOC_16 :
4177 (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64)));
4178
4179 if (target_little_endian_data && nbytes == 4
4180 && now_seg->flags & SEC_ALLOC)
4181 r = BFD_RELOC_SPARC_REV32;
4182 fix_new_exp (frag, where, (int) nbytes, exp, 0, r);
4183 }
4184
4185 #ifdef OBJ_ELF
4186 int
4187 elf32_sparc_force_relocation (fixp)
4188 struct fix *fixp;
4189 {
4190 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4191 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4192 return 1;
4193
4194 return 0;
4195 }
4196 #endif