1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright (C) 1989, 90-96, 1997 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public
17 License along with GAS; see the file COPYING. If not, write
18 to the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
27 /* careful, this file includes data *declarations* */
28 #include "opcode/sparc.h"
30 static void sparc_ip
PARAMS ((char *, const struct sparc_opcode
**));
31 static int in_signed_range
PARAMS ((bfd_signed_vma
, bfd_signed_vma
));
32 static int in_bitfield_range
PARAMS ((bfd_signed_vma
, bfd_signed_vma
));
33 static int sparc_ffs
PARAMS ((unsigned int));
34 static bfd_vma BSR
PARAMS ((bfd_vma
, int));
35 static int cmp_reg_entry
PARAMS ((const PTR
, const PTR
));
36 static int parse_keyword_arg
PARAMS ((int (*) (const char *), char **, int *));
37 static int parse_const_expr_arg
PARAMS ((char **, int *));
38 static int get_expression
PARAMS ((char *str
));
40 /* Current architecture. We don't bump up unless necessary. */
41 static enum sparc_opcode_arch_val current_architecture
= SPARC_OPCODE_ARCH_V6
;
43 /* The maximum architecture level we can bump up to.
44 In a 32 bit environment, don't allow bumping up to v9 by default.
45 The native assembler works this way. The user is required to pass
46 an explicit argument before we'll create v9 object files. However, if
47 we don't see any v9 insns, a v9 object file is not created. */
49 static enum sparc_opcode_arch_val max_architecture
= SPARC_OPCODE_ARCH_V9
;
51 /* ??? This should be V8, but sparclite support was added by making it the
52 default. GCC now passes -Asparclite, so maybe sometime in the future
53 we can set this to V8. */
54 static enum sparc_opcode_arch_val max_architecture
= SPARC_OPCODE_ARCH_SPARCLITE
;
57 static int architecture_requested
;
58 static int warn_on_bump
;
60 /* If warn_on_bump and the needed architecture is higher than this
61 architecture, issue a warning. */
62 static enum sparc_opcode_arch_val warn_after_architecture
;
64 /* Non-zero if we are generating PIC code. */
67 /* Non-zero if we should give an error when misaligned data is seen. */
68 static int enforce_aligned_data
;
70 extern int target_big_endian
;
72 /* V9 has big and little endian data, but instructions are always big endian.
73 The sparclet has bi-endian support but both data and insns have the same
74 endianness. Global `target_big_endian' is used for data. The following
75 macro is used for instructions. */
76 #define INSN_BIG_ENDIAN (target_big_endian \
77 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
79 /* handle of the OPCODE hash table */
80 static struct hash_control
*op_hash
;
82 static void s_data1
PARAMS ((void));
83 static void s_seg
PARAMS ((int));
84 static void s_proc
PARAMS ((int));
85 static void s_reserve
PARAMS ((int));
86 static void s_common
PARAMS ((int));
87 static void s_empty
PARAMS ((int));
88 static void s_uacons
PARAMS ((int));
90 const pseudo_typeS md_pseudo_table
[] =
92 {"align", s_align_bytes
, 0}, /* Defaulting is invalid (0) */
93 {"common", s_common
, 0},
94 {"empty", s_empty
, 0},
95 {"global", s_globl
, 0},
97 {"optim", s_ignore
, 0},
99 {"reserve", s_reserve
, 0},
101 {"skip", s_space
, 0},
104 {"uahalf", s_uacons
, 2},
105 {"uaword", s_uacons
, 4},
106 {"uaxword", s_uacons
, 8},
108 /* these are specific to sparc/svr4 */
109 {"pushsection", obj_elf_section
, 0},
110 {"popsection", obj_elf_previous
, 0},
111 {"2byte", s_uacons
, 2},
112 {"4byte", s_uacons
, 4},
113 {"8byte", s_uacons
, 8},
118 const int md_reloc_size
= 12; /* Size of relocation record */
120 /* This array holds the chars that always start a comment. If the
121 pre-processor is disabled, these aren't very useful */
122 const char comment_chars
[] = "!"; /* JF removed '|' from comment_chars */
124 /* This array holds the chars that only start a comment at the beginning of
125 a line. If the line seems to have the form '# 123 filename'
126 .line and .file directives will appear in the pre-processed output */
127 /* Note that input_file.c hand checks for '#' at the beginning of the
128 first line of the input file. This is because the compiler outputs
129 #NO_APP at the beginning of its output. */
130 /* Also note that comments started like this one will always
131 work if '/' isn't otherwise defined. */
132 const char line_comment_chars
[] = "#";
134 const char line_separator_chars
[] = "";
136 /* Chars that can be used to separate mant from exp in floating point nums */
137 const char EXP_CHARS
[] = "eE";
139 /* Chars that mean this number is a floating point constant */
142 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
144 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
145 changed in read.c. Ideally it shouldn't have to know about it at all,
146 but nothing is ideal around here. */
148 static unsigned char octal
[256];
149 #define isoctal(c) octal[(unsigned char) (c)]
150 static unsigned char toHex
[256];
155 unsigned long opcode
;
156 struct nlist
*nlistp
;
159 bfd_reloc_code_real_type reloc
;
162 struct sparc_it the_insn
, set_insn
;
164 static void output_insn
165 PARAMS ((const struct sparc_opcode
*, struct sparc_it
*));
169 * Invocation line includes a switch not recognized by the base assembler.
170 * See if it's a processor-specific option. These are:
173 * Warn on architecture bumps. See also -A.
175 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet
176 * Standard 32 bit architectures.
177 * -Av8plus, -Av8plusa
178 * Sparc64 in a 32 bit world.
180 * Sparc64 in a 64 bit world.
181 * -xarch=v8plus, -xarch=v8plusa
182 * Same as -Av8plus{,a}, for compatibility with Sun's assembler.
184 * Select the architecture and possibly the file format.
185 * Instructions or features not supported by the selected
186 * architecture cause fatal errors.
188 * The default is to start at v6, and bump the architecture up
189 * whenever an instruction is seen at a higher level. If 32 bit
190 * environments, v9 is not bumped up to, the user must pass -Av9.
192 * -xarch=v8plus{,a} is for compatibility with the Sun assembler.
194 * If -bump is specified, a warning is printing when bumping to
197 * If an architecture is specified, all instructions must match
198 * that architecture. Any higher level instructions are flagged
199 * as errors. Note that in the 32 bit environment specifying
200 * -Av9 does not automatically create a v9 object file, a v9
203 * If both an architecture and -bump are specified, the
204 * architecture starts at the specified level, but bumps are
205 * warnings. Note that we can't set `current_architecture' to
206 * the requested level in this case: in the 32 bit environment,
207 * we still must avoid creating v9 object files unless v9 insns
211 * Bumping between incompatible architectures is always an
212 * error. For example, from sparclite to v9.
216 CONST
char *md_shortopts
= "A:K:VQ:sq";
219 CONST
char *md_shortopts
= "A:k";
221 CONST
char *md_shortopts
= "A:";
224 struct option md_longopts
[] = {
225 #define OPTION_BUMP (OPTION_MD_BASE)
226 {"bump", no_argument
, NULL
, OPTION_BUMP
},
227 #define OPTION_SPARC (OPTION_MD_BASE + 1)
228 {"sparc", no_argument
, NULL
, OPTION_SPARC
},
229 #define OPTION_XARCH (OPTION_MD_BASE + 2)
230 {"xarch", required_argument
, NULL
, OPTION_XARCH
},
231 #ifdef SPARC_BIENDIAN
232 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 3)
233 {"EL", no_argument
, NULL
, OPTION_LITTLE_ENDIAN
},
234 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 4)
235 {"EB", no_argument
, NULL
, OPTION_BIG_ENDIAN
},
237 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 5)
238 {"enforce-aligned-data", no_argument
, NULL
, OPTION_ENFORCE_ALIGNED_DATA
},
239 {NULL
, no_argument
, NULL
, 0}
241 size_t md_longopts_size
= sizeof(md_longopts
);
244 md_parse_option (c
, arg
)
252 warn_after_architecture
= SPARC_OPCODE_ARCH_V6
;
256 /* This is for compatibility with Sun's assembler.
257 We could add v8plus and v8plusa to sparc_opcode_archs,
258 but that table is used to describe architectures whereas here we
259 want the argument to describe *both* the architecture and the file
261 if (strcmp (arg
, "v8plus") == 0)
263 else if (strcmp (arg
, "v8plusa") == 0)
267 as_bad ("invalid architecture -xarch=%s", arg
);
275 enum sparc_opcode_arch_val new_arch
= sparc_opcode_lookup_arch (arg
);
277 if (new_arch
== SPARC_OPCODE_ARCH_BAD
)
279 as_bad ("invalid architecture -A%s", arg
);
283 max_architecture
= new_arch
;
284 architecture_requested
= 1;
289 /* Ignore -sparc, used by SunOS make default .s.o rule. */
292 case OPTION_ENFORCE_ALIGNED_DATA
:
293 enforce_aligned_data
= 1;
296 #ifdef SPARC_BIENDIAN
297 case OPTION_LITTLE_ENDIAN
:
298 target_big_endian
= 0;
300 case OPTION_BIG_ENDIAN
:
301 target_big_endian
= 1;
317 /* Qy - do emit .comment
318 Qn - do not emit .comment */
322 /* use .stab instead of .stab.excl */
326 /* quick -- native assembler does fewer checks */
330 if (strcmp (arg
, "PIC") != 0)
331 as_warn ("Unrecognized option following -K");
345 md_show_usage (stream
)
348 const struct sparc_opcode_arch
*arch
;
350 fprintf(stream
, "SPARC options:\n");
351 for (arch
= &sparc_opcode_archs
[0]; arch
->name
; arch
++)
353 if (arch
!= &sparc_opcode_archs
[0])
354 fprintf (stream
, " | ");
355 fprintf (stream
, "-A%s", arch
->name
);
357 fprintf (stream
, "\n-xarch=v8plus | -xarch=v8plusa\n");
359 specify variant of SPARC architecture\n\
360 -bump warn when assembler switches architectures\n\
362 --enforce-aligned-data force .long, etc., to be aligned correctly\n");
369 -KPIC generate PIC\n\
370 -V print assembler version number\n\
375 #ifdef SPARC_BIENDIAN
377 -EL generate code for a little endian machine\n\
378 -EB generate code for a big endian machine\n");
382 /* sparc64 priviledged registers */
384 struct priv_reg_entry
390 struct priv_reg_entry priv_reg_table
[] =
409 {"", -1}, /* end marker */
413 cmp_reg_entry (parg
, qarg
)
417 const struct priv_reg_entry
*p
= (const struct priv_reg_entry
*) parg
;
418 const struct priv_reg_entry
*q
= (const struct priv_reg_entry
*) qarg
;
420 return strcmp (q
->name
, p
->name
);
423 /* This function is called once, at assembler startup time. It should
424 set up all the tables, etc. that the MD part of the assembler will need. */
429 register const char *retval
= NULL
;
431 register unsigned int i
= 0;
433 op_hash
= hash_new ();
435 while (i
< sparc_num_opcodes
)
437 const char *name
= sparc_opcodes
[i
].name
;
438 retval
= hash_insert (op_hash
, name
, (PTR
) &sparc_opcodes
[i
]);
441 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
442 sparc_opcodes
[i
].name
, retval
);
447 if (sparc_opcodes
[i
].match
& sparc_opcodes
[i
].lose
)
449 fprintf (stderr
, "internal error: losing opcode: `%s' \"%s\"\n",
450 sparc_opcodes
[i
].name
, sparc_opcodes
[i
].args
);
455 while (i
< sparc_num_opcodes
456 && !strcmp (sparc_opcodes
[i
].name
, name
));
460 as_fatal ("Broken assembler. No assembly attempted.");
462 for (i
= '0'; i
< '8'; ++i
)
464 for (i
= '0'; i
<= '9'; ++i
)
466 for (i
= 'a'; i
<= 'f'; ++i
)
467 toHex
[i
] = i
+ 10 - 'a';
468 for (i
= 'A'; i
<= 'F'; ++i
)
469 toHex
[i
] = i
+ 10 - 'A';
471 qsort (priv_reg_table
, sizeof (priv_reg_table
) / sizeof (priv_reg_table
[0]),
472 sizeof (priv_reg_table
[0]), cmp_reg_entry
);
474 /* If -bump, record the architecture level at which we start issuing
475 warnings. The behaviour is different depending upon whether an
476 architecture was explicitly specified. If it wasn't, we issue warnings
477 for all upwards bumps. If it was, we don't start issuing warnings until
478 we need to bump beyond the requested architecture or when we bump between
479 conflicting architectures. */
482 && architecture_requested
)
484 /* `max_architecture' records the requested architecture.
485 Issue warnings if we go above it. */
486 warn_after_architecture
= max_architecture
;
488 /* Find the highest architecture level that doesn't conflict with
489 the requested one. */
490 for (max_architecture
= SPARC_OPCODE_ARCH_MAX
;
491 max_architecture
> warn_after_architecture
;
493 if (! SPARC_OPCODE_CONFLICT_P (max_architecture
,
494 warn_after_architecture
))
499 /* Called after all assembly has been done. */
505 if (current_architecture
== SPARC_OPCODE_ARCH_V9A
)
506 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_v9a
);
508 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_v9
);
510 if (current_architecture
== SPARC_OPCODE_ARCH_V9
)
511 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_v8plus
);
512 else if (current_architecture
== SPARC_OPCODE_ARCH_V9A
)
513 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_v8plusa
);
514 else if (current_architecture
== SPARC_OPCODE_ARCH_SPARCLET
)
515 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_sparclet
);
518 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
519 be but for now it is (since that's the way it's always been
521 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc
);
526 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
529 in_signed_range (val
, max
)
530 bfd_signed_vma val
, max
;
541 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
542 (e.g. -15 to +31). */
545 in_bitfield_range (val
, max
)
546 bfd_signed_vma val
, max
;
552 if (val
< ~(max
>> 1))
566 for (i
= 0; (mask
& 1) == 0; ++i
)
571 /* Implement big shift right. */
577 if (sizeof (bfd_vma
) <= 4 && amount
>= 32)
578 as_fatal ("Support for 64-bit arithmetic not compiled in.");
579 return val
>> amount
;
582 /* For communication between sparc_ip and get_expression. */
583 static char *expr_end
;
585 /* For communication between md_assemble and sparc_ip. */
586 static int special_case
;
588 /* Values for `special_case'.
589 Instructions that require wierd handling because they're longer than
591 #define SPECIAL_CASE_NONE 0
592 #define SPECIAL_CASE_SET 1
593 #define SPECIAL_CASE_SETSW 2
594 #define SPECIAL_CASE_SETX 3
595 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
596 #define SPECIAL_CASE_FDIV 4
598 /* Bit masks of various insns. */
599 #define NOP_INSN 0x01000000
600 #define OR_INSN 0x80100000
601 #define FMOVS_INSN 0x81A00020
602 #define SETHI_INSN 0x01000000
603 #define SLLX_INSN 0x81281000
604 #define SRA_INSN 0x81380000
606 /* The last instruction to be assembled. */
607 static const struct sparc_opcode
*last_insn
;
608 /* The assembled opcode of `last_insn'. */
609 static unsigned long last_opcode
;
611 /* Main entry point to assemble one instruction. */
617 const struct sparc_opcode
*insn
;
620 special_case
= SPECIAL_CASE_NONE
;
621 sparc_ip (str
, &insn
);
623 /* We warn about attempts to put a floating point branch in a delay slot,
624 unless the delay slot has been annulled. */
627 && (insn
->flags
& F_FBR
) != 0
628 && (last_insn
->flags
& F_DELAYED
) != 0
629 /* ??? This test isn't completely accurate. We assume anything with
630 F_{UNBR,CONDBR,FBR} set is annullable. */
631 && ((last_insn
->flags
& (F_UNBR
| F_CONDBR
| F_FBR
)) == 0
632 || (last_opcode
& ANNUL
) == 0))
633 as_warn ("FP branch in delay slot");
635 /* SPARC before v9 requires a nop instruction between a floating
636 point instruction and a floating point branch. We insert one
637 automatically, with a warning. */
638 if (max_architecture
< SPARC_OPCODE_ARCH_V9
641 && (insn
->flags
& F_FBR
) != 0
642 && (last_insn
->flags
& F_FLOAT
) != 0)
644 struct sparc_it nop_insn
;
646 nop_insn
.opcode
= NOP_INSN
;
647 nop_insn
.reloc
= BFD_RELOC_NONE
;
648 output_insn (insn
, &nop_insn
);
649 as_warn ("FP branch preceded by FP instruction; NOP inserted");
652 switch (special_case
)
654 case SPECIAL_CASE_NONE
:
656 output_insn (insn
, &the_insn
);
659 case SPECIAL_CASE_SET
:
663 /* "set" is not defined for negative numbers in v9: it doesn't yield
664 what you expect it to. */
665 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
)
666 && the_insn
.exp
.X_op
== O_constant
)
668 if (the_insn
.exp
.X_add_number
< 0)
669 as_warn ("set: used with negative number");
670 else if (the_insn
.exp
.X_add_number
> 0xffffffff)
671 as_warn ("set: number larger than 4294967295");
674 /* See if operand is absolute and small; skip sethi if so. */
675 if (the_insn
.exp
.X_op
!= O_constant
676 || the_insn
.exp
.X_add_number
>= (1 << 12)
677 || the_insn
.exp
.X_add_number
< -(1 << 12))
679 output_insn (insn
, &the_insn
);
682 /* See if operand has no low-order bits; skip OR if so. */
683 if (the_insn
.exp
.X_op
!= O_constant
684 || (need_hi22_p
&& (the_insn
.exp
.X_add_number
& 0x3FF) != 0)
687 int rd
= (the_insn
.opcode
& RD (~0)) >> 25;
688 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (rd
) : 0)
691 | (the_insn
.exp
.X_add_number
692 & (need_hi22_p
? 0x3ff : 0x1fff)));
693 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
696 output_insn (insn
, &the_insn
);
701 case SPECIAL_CASE_SETSW
:
703 /* FIXME: Not finished. */
707 case SPECIAL_CASE_SETX
:
709 #define SIGNEXT32(x) ((((x) & 0xffffffff) ^ 0x80000000) - 0x80000000)
710 int upper32
= SIGNEXT32 (BSR (the_insn
.exp
.X_add_number
, 32));
711 int lower32
= SIGNEXT32 (the_insn
.exp
.X_add_number
);
713 int tmpreg
= (the_insn
.opcode
& RS1 (~0)) >> 14;
714 int dstreg
= (the_insn
.opcode
& RD (~0)) >> 25;
715 /* Output directly to dst reg if lower 32 bits are all zero. */
716 int upper_dstreg
= (the_insn
.exp
.X_op
== O_constant
717 && lower32
== 0) ? dstreg
: tmpreg
;
718 int need_hh22_p
= 0, need_hm10_p
= 0, need_hi22_p
= 0, need_lo10_p
= 0;
720 /* The tmp reg should not be the dst reg. */
721 if (tmpreg
== dstreg
)
722 as_warn ("setx: temporary register same as destination register");
724 /* Reset X_add_number, we've extracted it as upper32/lower32.
725 Otherwise fixup_segment will complain about not being able to
726 write an 8 byte number in a 4 byte field. */
727 the_insn
.exp
.X_add_number
= 0;
729 /* ??? Obviously there are other optimizations we can do
730 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
731 doing some of these. Later. If you do change things, try to
732 change all of this to be table driven as well. */
734 /* What to output depends on the number if it's constant.
735 Compute that first, then output what we've decided upon. */
736 if (the_insn
.exp
.X_op
!= O_constant
)
737 need_hh22_p
= need_hm10_p
= need_hi22_p
= need_lo10_p
= 1;
740 /* Only need hh22 if `or' insn can't handle constant. */
741 if (upper32
< -(1 << 12) || upper32
>= (1 << 12))
744 /* Does bottom part (after sethi) have bits? */
745 if ((need_hh22_p
&& (upper32
& 0x3ff) != 0)
746 /* No hh22, but does upper32 still have bits we can't set
750 && (upper32
!= -1 || lower32
>= 0)))
753 /* If the lower half is all zero, we build the upper half directly
756 /* Need lower half if number is zero. */
757 || (! need_hh22_p
&& ! need_hm10_p
))
759 /* No need for sethi if `or' insn can handle constant. */
760 if (lower32
< -(1 << 12) || lower32
>= (1 << 12)
761 /* Note that we can't use a negative constant in the `or'
762 insn unless the upper 32 bits are all ones. */
763 || (lower32
< 0 && upper32
!= -1))
766 /* Does bottom part (after sethi) have bits? */
767 if ((need_hi22_p
&& (lower32
& 0x3ff) != 0)
769 || (! need_hi22_p
&& (lower32
& 0x1fff) != 0)
770 /* Need `or' if we didn't set anything else. */
771 || (! need_hi22_p
&& ! need_hh22_p
&& ! need_hm10_p
))
778 the_insn
.opcode
= (SETHI_INSN
| RD (upper_dstreg
)
779 | ((upper32
>> 10) & 0x3fffff));
780 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
781 ? BFD_RELOC_SPARC_HH22
: BFD_RELOC_NONE
);
782 output_insn (insn
, &the_insn
);
787 the_insn
.opcode
= (OR_INSN
788 | (need_hh22_p
? RS1 (upper_dstreg
) : 0)
792 & (need_hh22_p
? 0x3ff : 0x1fff)));
793 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
794 ? BFD_RELOC_SPARC_HM10
: BFD_RELOC_NONE
);
795 output_insn (insn
, &the_insn
);
800 the_insn
.opcode
= (SETHI_INSN
| RD (dstreg
)
801 | ((lower32
>> 10) & 0x3fffff));
802 the_insn
.reloc
= BFD_RELOC_HI22
;
803 output_insn (insn
, &the_insn
);
808 /* FIXME: One nice optimization to do here is to OR the low part
809 with the highpart if hi22 isn't needed and the low part is
811 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (dstreg
) : 0)
815 & (need_hi22_p
? 0x3ff : 0x1fff)));
816 the_insn
.reloc
= BFD_RELOC_LO10
;
817 output_insn (insn
, &the_insn
);
820 /* If we needed to build the upper part, shift it into place. */
821 if (need_hh22_p
|| need_hm10_p
)
823 the_insn
.opcode
= (SLLX_INSN
| RS1 (upper_dstreg
) | RD (upper_dstreg
)
825 the_insn
.reloc
= BFD_RELOC_NONE
;
826 output_insn (insn
, &the_insn
);
829 /* If we needed to build both upper and lower parts, OR them together. */
830 if ((need_hh22_p
|| need_hm10_p
)
831 && (need_hi22_p
|| need_lo10_p
))
833 the_insn
.opcode
= (OR_INSN
| RS1 (dstreg
) | RS2 (upper_dstreg
)
835 the_insn
.reloc
= BFD_RELOC_NONE
;
836 output_insn (insn
, &the_insn
);
838 /* We didn't need both regs, but we may have to sign extend lower32. */
839 else if (need_hi22_p
&& upper32
== -1)
841 the_insn
.opcode
= (SRA_INSN
| RS1 (dstreg
) | RD (dstreg
)
843 the_insn
.reloc
= BFD_RELOC_NONE
;
844 output_insn (insn
, &the_insn
);
849 case SPECIAL_CASE_FDIV
:
851 int rd
= (the_insn
.opcode
>> 25) & 0x1f;
853 output_insn (insn
, &the_insn
);
855 /* According to information leaked from Sun, the "fdiv" instructions
856 on early SPARC machines would produce incorrect results sometimes.
857 The workaround is to add an fmovs of the destination register to
858 itself just after the instruction. This was true on machines
859 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
860 assert (the_insn
.reloc
== BFD_RELOC_NONE
);
861 the_insn
.opcode
= FMOVS_INSN
| rd
| RD (rd
);
862 output_insn (insn
, &the_insn
);
867 as_fatal ("failed special case insn sanity check");
871 /* Subroutine of md_assemble to do the actual parsing. */
874 sparc_ip (str
, pinsn
)
876 const struct sparc_opcode
**pinsn
;
878 char *error_message
= "";
882 const struct sparc_opcode
*insn
;
884 unsigned long opcode
;
885 unsigned int mask
= 0;
888 long immediate_max
= 0;
891 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3'); ++s
)
909 as_fatal ("Unknown opcode: `%s'", str
);
911 insn
= (struct sparc_opcode
*) hash_find (op_hash
, str
);
915 as_bad ("Unknown opcode: `%s'", str
);
926 opcode
= insn
->match
;
927 memset (&the_insn
, '\0', sizeof (the_insn
));
928 the_insn
.reloc
= BFD_RELOC_NONE
;
932 * Build the opcode, checking as we go to make
933 * sure that the operands match
935 for (args
= insn
->args
;; ++args
)
943 /* Parse a series of masks. */
950 if (! parse_keyword_arg (sparc_encode_membar
, &s
,
953 error_message
= ": invalid membar mask name";
957 while (*s
== ' ') { ++s
; continue; }
958 if (*s
== '|' || *s
== '+')
960 while (*s
== ' ') { ++s
; continue; }
965 if (! parse_const_expr_arg (&s
, &kmask
))
967 error_message
= ": invalid membar mask expression";
970 if (kmask
< 0 || kmask
> 127)
972 error_message
= ": invalid membar mask number";
977 opcode
|= MEMBAR (kmask
);
985 /* Parse a prefetch function. */
988 if (! parse_keyword_arg (sparc_encode_prefetch
, &s
, &fcn
))
990 error_message
= ": invalid prefetch function name";
996 if (! parse_const_expr_arg (&s
, &fcn
))
998 error_message
= ": invalid prefetch function expression";
1001 if (fcn
< 0 || fcn
> 31)
1003 error_message
= ": invalid prefetch function number";
1013 /* Parse a sparc64 privileged register. */
1016 struct priv_reg_entry
*p
= priv_reg_table
;
1017 unsigned int len
= 9999999; /* init to make gcc happy */
1020 while (p
->name
[0] > s
[0])
1022 while (p
->name
[0] == s
[0])
1024 len
= strlen (p
->name
);
1025 if (strncmp (p
->name
, s
, len
) == 0)
1029 if (p
->name
[0] != s
[0])
1031 error_message
= ": unrecognizable privileged register";
1035 opcode
|= (p
->regnum
<< 14);
1037 opcode
|= (p
->regnum
<< 25);
1043 error_message
= ": unrecognizable privileged register";
1049 if (strncmp (s
, "%asr", 4) == 0)
1057 while (isdigit (*s
))
1059 num
= num
* 10 + *s
- '0';
1063 if (current_architecture
>= SPARC_OPCODE_ARCH_V9
)
1065 if (num
< 16 || 31 < num
)
1067 error_message
= ": asr number must be between 16 and 31";
1073 if (num
< 0 || 31 < num
)
1075 error_message
= ": asr number must be between 0 and 31";
1080 opcode
|= (*args
== 'M' ? RS1 (num
) : RD (num
));
1085 error_message
= ": expecting %asrN";
1092 the_insn
.reloc
= BFD_RELOC_SPARC_11
;
1093 immediate_max
= 0x03FF;
1097 the_insn
.reloc
= BFD_RELOC_SPARC_10
;
1098 immediate_max
= 0x01FF;
1102 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1103 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1104 the_insn
.reloc
= BFD_RELOC_SPARC_5
;
1106 the_insn
.reloc
= BFD_RELOC_SPARC13
;
1107 /* These fields are unsigned, but for upward compatibility,
1108 allow negative values as well. */
1109 immediate_max
= 0x1f;
1113 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1114 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1115 the_insn
.reloc
= BFD_RELOC_SPARC_6
;
1117 the_insn
.reloc
= BFD_RELOC_SPARC13
;
1118 /* These fields are unsigned, but for upward compatibility,
1119 allow negative values as well. */
1120 immediate_max
= 0x3f;
1124 the_insn
.reloc
= /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16
;
1129 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP19
;
1134 if (*s
== 'p' && s
[1] == 'n')
1142 if (*s
== 'p' && s
[1] == 't')
1154 if (strncmp (s
, "%icc", 4) == 0)
1166 if (strncmp (s
, "%xcc", 4) == 0)
1178 if (strncmp (s
, "%fcc0", 5) == 0)
1190 if (strncmp (s
, "%fcc1", 5) == 0)
1202 if (strncmp (s
, "%fcc2", 5) == 0)
1214 if (strncmp (s
, "%fcc3", 5) == 0)
1222 if (strncmp (s
, "%pc", 3) == 0)
1230 if (strncmp (s
, "%tick", 5) == 0)
1237 case '\0': /* end of args */
1256 case '[': /* these must match exactly */
1264 case '#': /* must be at least one digit */
1267 while (isdigit (*s
))
1275 case 'C': /* coprocessor state register */
1276 if (strncmp (s
, "%csr", 4) == 0)
1283 case 'b': /* next operand is a coprocessor register */
1286 if (*s
++ == '%' && *s
++ == 'c' && isdigit (*s
))
1291 mask
= 10 * (mask
- '0') + (*s
++ - '0');
1305 opcode
|= mask
<< 14;
1313 opcode
|= mask
<< 25;
1319 case 'r': /* next operand must be a register */
1329 case 'f': /* frame pointer */
1337 case 'g': /* global register */
1338 if (isoctal (c
= *s
++))
1345 case 'i': /* in register */
1346 if (isoctal (c
= *s
++))
1348 mask
= c
- '0' + 24;
1353 case 'l': /* local register */
1354 if (isoctal (c
= *s
++))
1356 mask
= (c
- '0' + 16);
1361 case 'o': /* out register */
1362 if (isoctal (c
= *s
++))
1364 mask
= (c
- '0' + 8);
1369 case 's': /* stack pointer */
1377 case 'r': /* any register */
1378 if (!isdigit (c
= *s
++))
1395 if ((c
= 10 * (c
- '0') + (*s
++ - '0')) >= 32)
1411 /* Got the register, now figure out where
1412 it goes in the opcode. */
1416 opcode
|= mask
<< 14;
1424 opcode
|= mask
<< 25;
1428 opcode
|= (mask
<< 25) | (mask
<< 14);
1432 opcode
|= (mask
<< 25) | (mask
<< 0);
1438 case 'e': /* next operand is a floating point register */
1453 && ((format
= *s
) == 'f')
1456 for (mask
= 0; isdigit (*s
); ++s
)
1458 mask
= 10 * mask
+ (*s
- '0');
1459 } /* read the number */
1467 } /* register must be even numbered */
1475 } /* register must be multiple of 4 */
1479 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1480 error_message
= ": There are only 64 f registers; [0-63]";
1482 error_message
= ": There are only 32 f registers; [0-31]";
1485 else if (mask
>= 32)
1487 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1490 mask
-= 31; /* wrap high bit */
1494 error_message
= ": There are only 32 f registers; [0-31]";
1502 } /* if not an 'f' register. */
1509 opcode
|= RS1 (mask
);
1516 opcode
|= RS2 (mask
);
1522 opcode
|= RD (mask
);
1531 if (strncmp (s
, "%fsr", 4) == 0)
1538 case '0': /* 64 bit immediate (setx insn) */
1539 the_insn
.reloc
= BFD_RELOC_NONE
; /* reloc handled elsewhere */
1542 case 'h': /* high 22 bits */
1543 the_insn
.reloc
= BFD_RELOC_HI22
;
1546 case 'l': /* 22 bit PC relative immediate */
1547 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP22
;
1551 case 'L': /* 30 bit immediate */
1552 the_insn
.reloc
= BFD_RELOC_32_PCREL_S2
;
1556 case 'n': /* 22 bit immediate */
1557 the_insn
.reloc
= BFD_RELOC_SPARC22
;
1560 case 'i': /* 13 bit immediate */
1561 the_insn
.reloc
= BFD_RELOC_SPARC13
;
1562 immediate_max
= 0x0FFF;
1571 if ((c
= s
[1]) == 'h' && s
[2] == 'i')
1573 the_insn
.reloc
= BFD_RELOC_HI22
;
1576 else if (c
== 'l' && s
[2] == 'o')
1578 the_insn
.reloc
= BFD_RELOC_LO10
;
1585 the_insn
.reloc
= BFD_RELOC_SPARC_HH22
;
1593 the_insn
.reloc
= BFD_RELOC_SPARC_HM10
;
1600 /* Note that if the get_expression() fails, we will still
1601 have created U entries in the symbol table for the
1602 'symbols' in the input string. Try not to create U
1603 symbols for registers, etc. */
1605 /* This stuff checks to see if the expression ends in
1606 +%reg. If it does, it removes the register from
1607 the expression, and re-sets 's' to point to the
1612 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++) ;
1614 if (s1
!= s
&& isdigit (s1
[-1]))
1616 if (s1
[-2] == '%' && s1
[-3] == '+')
1620 (void) get_expression (s
);
1625 else if (strchr ("goli0123456789", s1
[-2]) && s1
[-3] == '%' && s1
[-4] == '+')
1629 (void) get_expression (s
);
1636 (void) get_expression (s
);
1639 if (the_insn
.exp
.X_op
== O_constant
1640 && the_insn
.exp
.X_add_symbol
== 0
1641 && the_insn
.exp
.X_op_symbol
== 0)
1643 /* Handle %uhi/%ulo by moving the upper word to the lower
1644 one and pretending it's %hi/%lo. We also need to watch
1645 for %hi/%lo: the top word needs to be zeroed otherwise
1646 fixup_segment will complain the value is too big. */
1647 switch (the_insn
.reloc
)
1649 case BFD_RELOC_SPARC_HH22
:
1650 the_insn
.reloc
= BFD_RELOC_HI22
;
1651 the_insn
.exp
.X_add_number
= BSR (the_insn
.exp
.X_add_number
, 32);
1653 case BFD_RELOC_SPARC_HM10
:
1654 the_insn
.reloc
= BFD_RELOC_LO10
;
1655 the_insn
.exp
.X_add_number
= BSR (the_insn
.exp
.X_add_number
, 32);
1657 case BFD_RELOC_HI22
:
1658 case BFD_RELOC_LO10
:
1659 the_insn
.exp
.X_add_number
&= 0xffffffff;
1665 /* For pc-relative call instructions, we reject
1666 constants to get better code. */
1668 && the_insn
.reloc
== BFD_RELOC_32_PCREL_S2
1669 && in_signed_range (the_insn
.exp
.X_add_number
, 0x3fff)
1672 error_message
= ": PC-relative operand can't be a constant";
1675 /* Check for invalid constant values. Don't warn if
1676 constant was inside %hi or %lo, since these
1677 truncate the constant to fit. */
1678 if (immediate_max
!= 0
1679 && the_insn
.reloc
!= BFD_RELOC_LO10
1680 && the_insn
.reloc
!= BFD_RELOC_HI22
1681 && !in_signed_range (the_insn
.exp
.X_add_number
,
1686 /* Who knows? After relocation, we may be within
1687 range. Let the linker figure it out. */
1689 the_insn
.exp
.X_op
= O_symbol
;
1690 the_insn
.exp
.X_add_symbol
= section_symbol (absolute_section
);
1693 /* Immediate value is non-pcrel, and out of
1695 as_bad ("constant value %ld out of range (%ld .. %ld)",
1696 the_insn
.exp
.X_add_number
,
1697 ~immediate_max
, immediate_max
);
1701 /* Reset to prevent extraneous range check. */
1721 if (! parse_keyword_arg (sparc_encode_asi
, &s
, &asi
))
1723 error_message
= ": invalid ASI name";
1729 if (! parse_const_expr_arg (&s
, &asi
))
1731 error_message
= ": invalid ASI expression";
1734 if (asi
< 0 || asi
> 255)
1736 error_message
= ": invalid ASI number";
1740 opcode
|= ASI (asi
);
1742 } /* alternate space */
1745 if (strncmp (s
, "%psr", 4) == 0)
1752 case 'q': /* floating point queue */
1753 if (strncmp (s
, "%fq", 3) == 0)
1760 case 'Q': /* coprocessor queue */
1761 if (strncmp (s
, "%cq", 3) == 0)
1769 if (strcmp (str
, "set") == 0
1770 || strcmp (str
, "setuw") == 0)
1772 special_case
= SPECIAL_CASE_SET
;
1775 else if (strcmp (str
, "setsw") == 0)
1777 special_case
= SPECIAL_CASE_SETSW
;
1780 else if (strcmp (str
, "setx") == 0)
1782 special_case
= SPECIAL_CASE_SETX
;
1785 else if (strncmp (str
, "fdiv", 4) == 0)
1787 special_case
= SPECIAL_CASE_FDIV
;
1793 if (strncmp (s
, "%asi", 4) != 0)
1799 if (strncmp (s
, "%fprs", 5) != 0)
1805 if (strncmp (s
, "%ccr", 4) != 0)
1811 if (strncmp (s
, "%tbr", 4) != 0)
1817 if (strncmp (s
, "%wim", 4) != 0)
1824 char *push
= input_line_pointer
;
1827 input_line_pointer
= s
;
1829 if (e
.X_op
== O_constant
)
1831 int n
= e
.X_add_number
;
1832 if (n
!= e
.X_add_number
|| (n
& ~0x1ff) != 0)
1833 as_bad ("OPF immediate operand out of range (0-0x1ff)");
1835 opcode
|= e
.X_add_number
<< 5;
1838 as_bad ("non-immediate OPF operand, ignored");
1839 s
= input_line_pointer
;
1840 input_line_pointer
= push
;
1845 if (strncmp (s
, "%y", 2) != 0)
1853 /* Parse a sparclet cpreg. */
1855 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg
, &s
, &cpreg
))
1857 error_message
= ": invalid cpreg name";
1860 opcode
|= (*args
== 'U' ? RS1 (cpreg
) : RD (cpreg
));
1865 as_fatal ("failed sanity check.");
1866 } /* switch on arg code */
1868 /* Break out of for() loop. */
1870 } /* for each arg that we expect */
1875 /* Args don't match. */
1876 if (((unsigned) (&insn
[1] - sparc_opcodes
)) < sparc_num_opcodes
1877 && (insn
->name
== insn
[1].name
1878 || !strcmp (insn
->name
, insn
[1].name
)))
1886 as_bad ("Illegal operands%s", error_message
);
1892 /* We have a match. Now see if the architecture is ok. */
1893 int needed_arch_mask
= insn
->architecture
;
1897 needed_arch_mask
&= ~ ((1 << SPARC_OPCODE_ARCH_V9
)
1898 | (1 << SPARC_OPCODE_ARCH_V9A
));
1899 needed_arch_mask
|= (1 << SPARC_OPCODE_ARCH_V9
);
1902 if (needed_arch_mask
& SPARC_OPCODE_SUPPORTED (current_architecture
))
1904 /* Can we bump up the architecture? */
1905 else if (needed_arch_mask
& SPARC_OPCODE_SUPPORTED (max_architecture
))
1907 enum sparc_opcode_arch_val needed_architecture
=
1908 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture
)
1909 & needed_arch_mask
);
1911 assert (needed_architecture
<= SPARC_OPCODE_ARCH_MAX
);
1913 && needed_architecture
> warn_after_architecture
)
1915 as_warn ("architecture bumped from \"%s\" to \"%s\" on \"%s\"",
1916 sparc_opcode_archs
[current_architecture
].name
,
1917 sparc_opcode_archs
[needed_architecture
].name
,
1919 warn_after_architecture
= needed_architecture
;
1921 current_architecture
= needed_architecture
;
1924 /* ??? This seems to be a bit fragile. What if the next entry in
1925 the opcode table is the one we want and it is supported?
1926 It is possible to arrange the table today so that this can't
1927 happen but what about tomorrow? */
1930 int arch
,printed_one_p
= 0;
1932 char required_archs
[SPARC_OPCODE_ARCH_MAX
* 16];
1934 /* Create a list of the architectures that support the insn. */
1935 needed_arch_mask
&= ~ SPARC_OPCODE_SUPPORTED (max_architecture
);
1937 arch
= sparc_ffs (needed_arch_mask
);
1938 while ((1 << arch
) <= needed_arch_mask
)
1940 if ((1 << arch
) & needed_arch_mask
)
1944 strcpy (p
, sparc_opcode_archs
[arch
].name
);
1951 as_bad ("Architecture mismatch on \"%s\".", str
);
1952 as_tsktsk (" (Requires %s; requested architecture is %s.)",
1954 sparc_opcode_archs
[max_architecture
].name
);
1960 } /* forever looking for a match */
1962 the_insn
.opcode
= opcode
;
1965 /* Parse an argument that can be expressed as a keyword.
1966 (eg: #StoreStore or %ccfr).
1967 The result is a boolean indicating success.
1968 If successful, INPUT_POINTER is updated. */
1971 parse_keyword_arg (lookup_fn
, input_pointerP
, valueP
)
1972 int (*lookup_fn
) PARAMS ((const char *));
1973 char **input_pointerP
;
1979 p
= *input_pointerP
;
1980 for (q
= p
+ (*p
== '#' || *p
== '%'); isalnum (*q
) || *q
== '_'; ++q
)
1984 value
= (*lookup_fn
) (p
);
1989 *input_pointerP
= q
;
1993 /* Parse an argument that is a constant expression.
1994 The result is a boolean indicating success. */
1997 parse_const_expr_arg (input_pointerP
, valueP
)
1998 char **input_pointerP
;
2001 char *save
= input_line_pointer
;
2004 input_line_pointer
= *input_pointerP
;
2005 /* The next expression may be something other than a constant
2006 (say if we're not processing the right variant of the insn).
2007 Don't call expression unless we're sure it will succeed as it will
2008 signal an error (which we want to defer until later). */
2009 /* FIXME: It might be better to define md_operand and have it recognize
2010 things like %asi, etc. but continuing that route through to the end
2011 is a lot of work. */
2012 if (*input_line_pointer
== '%')
2014 input_line_pointer
= save
;
2018 *input_pointerP
= input_line_pointer
;
2019 input_line_pointer
= save
;
2020 if (exp
.X_op
!= O_constant
)
2022 *valueP
= exp
.X_add_number
;
2026 /* Subroutine of sparc_ip to parse an expression. */
2029 get_expression (str
)
2035 save_in
= input_line_pointer
;
2036 input_line_pointer
= str
;
2037 seg
= expression (&the_insn
.exp
);
2038 if (seg
!= absolute_section
2039 && seg
!= text_section
2040 && seg
!= data_section
2041 && seg
!= bss_section
2042 && seg
!= undefined_section
)
2044 the_insn
.error
= "bad segment";
2045 expr_end
= input_line_pointer
;
2046 input_line_pointer
= save_in
;
2049 expr_end
= input_line_pointer
;
2050 input_line_pointer
= save_in
;
2054 /* Subroutine of md_assemble to output one insn. */
2057 output_insn (insn
, the_insn
)
2058 const struct sparc_opcode
*insn
;
2059 struct sparc_it
*the_insn
;
2061 char *toP
= frag_more (4);
2063 /* put out the opcode */
2064 if (INSN_BIG_ENDIAN
)
2065 number_to_chars_bigendian (toP
, (valueT
) the_insn
->opcode
, 4);
2067 number_to_chars_littleendian (toP
, (valueT
) the_insn
->opcode
, 4);
2069 /* put out the symbol-dependent stuff */
2070 if (the_insn
->reloc
!= BFD_RELOC_NONE
)
2072 fix_new_exp (frag_now
, /* which frag */
2073 (toP
- frag_now
->fr_literal
), /* where */
2081 last_opcode
= the_insn
->opcode
;
2085 This is identical to the md_atof in m68k.c. I think this is right,
2088 Turn a string in input_line_pointer into a floating point constant of type
2089 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
2090 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
2093 /* Equal to MAX_PRECISION in atof-ieee.c */
2094 #define MAX_LITTLENUMS 6
2097 md_atof (type
, litP
, sizeP
)
2103 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2134 return "Bad call to MD_ATOF()";
2137 t
= atof_ieee (input_line_pointer
, type
, words
);
2139 input_line_pointer
= t
;
2140 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
2142 if (target_big_endian
)
2144 for (i
= 0; i
< prec
; i
++)
2146 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
2147 litP
+= sizeof (LITTLENUM_TYPE
);
2152 for (i
= prec
- 1; i
>= 0; i
--)
2154 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
2155 litP
+= sizeof (LITTLENUM_TYPE
);
2162 /* Write a value out to the object file, using the appropriate
2166 md_number_to_chars (buf
, val
, n
)
2171 if (target_big_endian
)
2172 number_to_chars_bigendian (buf
, val
, n
);
2174 number_to_chars_littleendian (buf
, val
, n
);
2177 /* Apply a fixS to the frags, now that we know the value it ought to
2181 md_apply_fix3 (fixP
, value
, segment
)
2186 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
2192 assert (fixP
->fx_r_type
< BFD_RELOC_UNUSED
);
2194 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc */
2197 /* FIXME: SPARC ELF relocations don't use an addend in the data
2198 field itself. This whole approach should be somehow combined
2199 with the calls to bfd_install_relocation. Also, the value passed
2200 in by fixup_segment includes the value of a defined symbol. We
2201 don't want to include the value of an externally visible symbol. */
2202 if (fixP
->fx_addsy
!= NULL
)
2204 if (fixP
->fx_addsy
->sy_used_in_reloc
2205 && (S_IS_EXTERNAL (fixP
->fx_addsy
)
2206 || S_IS_WEAK (fixP
->fx_addsy
)
2207 || (sparc_pic_code
&& ! fixP
->fx_pcrel
)
2208 || (S_GET_SEGMENT (fixP
->fx_addsy
) != segment
2209 && ((bfd_get_section_flags (stdoutput
,
2210 S_GET_SEGMENT (fixP
->fx_addsy
))
2211 & SEC_LINK_ONCE
) != 0
2212 || strncmp (segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)),
2214 sizeof ".gnu.linkonce" - 1) == 0)))
2215 && S_GET_SEGMENT (fixP
->fx_addsy
) != absolute_section
2216 && S_GET_SEGMENT (fixP
->fx_addsy
) != undefined_section
2217 && ! bfd_is_com_section (S_GET_SEGMENT (fixP
->fx_addsy
)))
2218 fixP
->fx_addnumber
-= S_GET_VALUE (fixP
->fx_addsy
);
2223 /* This is a hack. There should be a better way to
2224 handle this. Probably in terms of howto fields, once
2225 we can look at these fixups in terms of howtos. */
2226 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
&& fixP
->fx_addsy
)
2227 val
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2230 /* FIXME: More ridiculous gas reloc hacking. If we are going to
2231 generate a reloc, then we just want to let the reloc addend set
2232 the value. We do not want to also stuff the addend into the
2233 object file. Including the addend in the object file works when
2234 doing a static link, because the linker will ignore the object
2235 file contents. However, the dynamic linker does not ignore the
2236 object file contents. */
2237 if (fixP
->fx_addsy
!= NULL
2238 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
)
2241 /* When generating PIC code, we do not want an addend for a reloc
2242 against a local symbol. We adjust fx_addnumber to cancel out the
2243 value already included in val, and to also cancel out the
2244 adjustment which bfd_install_relocation will create. */
2246 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
2247 && fixP
->fx_addsy
!= NULL
2248 && ! S_IS_COMMON (fixP
->fx_addsy
)
2249 && (fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
2250 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
2253 /* If this is a data relocation, just output VAL. */
2255 if (fixP
->fx_r_type
== BFD_RELOC_16
)
2257 md_number_to_chars (buf
, val
, 2);
2259 else if (fixP
->fx_r_type
== BFD_RELOC_32
)
2261 md_number_to_chars (buf
, val
, 4);
2263 else if (fixP
->fx_r_type
== BFD_RELOC_64
)
2265 md_number_to_chars (buf
, val
, 8);
2269 /* It's a relocation against an instruction. */
2271 if (INSN_BIG_ENDIAN
)
2272 insn
= bfd_getb32 ((unsigned char *) buf
);
2274 insn
= bfd_getl32 ((unsigned char *) buf
);
2276 switch (fixP
->fx_r_type
)
2278 case BFD_RELOC_32_PCREL_S2
:
2280 /* FIXME: This increment-by-one deserves a comment of why it's
2282 if (! sparc_pic_code
2283 || fixP
->fx_addsy
== NULL
2284 || (fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) != 0)
2286 insn
|= val
& 0x3fffffff;
2289 case BFD_RELOC_SPARC_11
:
2290 if (! in_signed_range (val
, 0x7ff))
2291 as_bad ("relocation overflow.");
2292 insn
|= val
& 0x7ff;
2295 case BFD_RELOC_SPARC_10
:
2296 if (! in_signed_range (val
, 0x3ff))
2297 as_bad ("relocation overflow.");
2298 insn
|= val
& 0x3ff;
2301 case BFD_RELOC_SPARC_6
:
2302 if (! in_bitfield_range (val
, 0x3f))
2303 as_bad ("relocation overflow.");
2307 case BFD_RELOC_SPARC_5
:
2308 if (! in_bitfield_range (val
, 0x1f))
2309 as_bad ("relocation overflow.");
2313 case BFD_RELOC_SPARC_WDISP16
:
2314 /* FIXME: simplify */
2315 if (((val
> 0) && (val
& ~0x3fffc))
2316 || ((val
< 0) && (~(val
- 1) & ~0x3fffc)))
2317 as_bad ("relocation overflow.");
2318 /* FIXME: The +1 deserves a comment. */
2319 val
= (val
>> 2) + 1;
2320 insn
|= ((val
& 0xc000) << 6) | (val
& 0x3fff);
2323 case BFD_RELOC_SPARC_WDISP19
:
2324 /* FIXME: simplify */
2325 if (((val
> 0) && (val
& ~0x1ffffc))
2326 || ((val
< 0) && (~(val
- 1) & ~0x1ffffc)))
2327 as_bad ("relocation overflow.");
2328 /* FIXME: The +1 deserves a comment. */
2329 val
= (val
>> 2) + 1;
2330 insn
|= val
& 0x7ffff;
2333 case BFD_RELOC_SPARC_HH22
:
2334 val
= BSR (val
, 32);
2335 /* intentional fallthrough */
2337 case BFD_RELOC_SPARC_LM22
:
2338 case BFD_RELOC_HI22
:
2339 if (!fixP
->fx_addsy
)
2341 insn
|= (val
>> 10) & 0x3fffff;
2345 /* FIXME: Need comment explaining why we do this. */
2350 case BFD_RELOC_SPARC22
:
2351 if (val
& ~0x003fffff)
2352 as_bad ("relocation overflow");
2353 insn
|= (val
& 0x3fffff);
2356 case BFD_RELOC_SPARC_HM10
:
2357 val
= BSR (val
, 32);
2358 /* intentional fallthrough */
2360 case BFD_RELOC_LO10
:
2361 if (!fixP
->fx_addsy
)
2363 insn
|= val
& 0x3ff;
2367 /* FIXME: Need comment explaining why we do this. */
2372 case BFD_RELOC_SPARC13
:
2373 if (! in_signed_range (val
, 0x1fff))
2374 as_bad ("relocation overflow");
2375 insn
|= val
& 0x1fff;
2378 case BFD_RELOC_SPARC_WDISP22
:
2379 val
= (val
>> 2) + 1;
2381 case BFD_RELOC_SPARC_BASE22
:
2382 insn
|= val
& 0x3fffff;
2385 case BFD_RELOC_NONE
:
2387 as_bad ("bad or unhandled relocation type: 0x%02x", fixP
->fx_r_type
);
2391 if (INSN_BIG_ENDIAN
)
2392 bfd_putb32 (insn
, (unsigned char *) buf
);
2394 bfd_putl32 (insn
, (unsigned char *) buf
);
2397 /* Are we finished with this relocation now? */
2398 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
2404 /* Translate internal representation of relocation info to BFD target
2407 tc_gen_reloc (section
, fixp
)
2412 bfd_reloc_code_real_type code
;
2414 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
2416 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
2417 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
2419 switch (fixp
->fx_r_type
)
2423 case BFD_RELOC_HI22
:
2424 case BFD_RELOC_LO10
:
2425 case BFD_RELOC_32_PCREL_S2
:
2426 case BFD_RELOC_SPARC13
:
2427 case BFD_RELOC_SPARC_BASE13
:
2428 case BFD_RELOC_SPARC_WDISP16
:
2429 case BFD_RELOC_SPARC_WDISP19
:
2430 case BFD_RELOC_SPARC_WDISP22
:
2432 case BFD_RELOC_SPARC_5
:
2433 case BFD_RELOC_SPARC_6
:
2434 case BFD_RELOC_SPARC_10
:
2435 case BFD_RELOC_SPARC_11
:
2436 case BFD_RELOC_SPARC_HH22
:
2437 case BFD_RELOC_SPARC_HM10
:
2438 case BFD_RELOC_SPARC_LM22
:
2439 case BFD_RELOC_SPARC_PC_HH22
:
2440 case BFD_RELOC_SPARC_PC_HM10
:
2441 case BFD_RELOC_SPARC_PC_LM22
:
2442 code
= fixp
->fx_r_type
;
2448 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
2449 /* If we are generating PIC code, we need to generate a different
2453 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
2455 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
2462 case BFD_RELOC_32_PCREL_S2
:
2463 if (! S_IS_DEFINED (fixp
->fx_addsy
)
2464 || S_IS_COMMON (fixp
->fx_addsy
)
2465 || S_IS_EXTERNAL (fixp
->fx_addsy
)
2466 || S_IS_WEAK (fixp
->fx_addsy
))
2467 code
= BFD_RELOC_SPARC_WPLT30
;
2469 case BFD_RELOC_HI22
:
2470 if (fixp
->fx_addsy
!= NULL
2471 && strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
2472 code
= BFD_RELOC_SPARC_PC22
;
2474 code
= BFD_RELOC_SPARC_GOT22
;
2476 case BFD_RELOC_LO10
:
2477 if (fixp
->fx_addsy
!= NULL
2478 && strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
2479 code
= BFD_RELOC_SPARC_PC10
;
2481 code
= BFD_RELOC_SPARC_GOT10
;
2483 case BFD_RELOC_SPARC13
:
2484 code
= BFD_RELOC_SPARC_GOT13
;
2490 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
2492 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
2493 if (reloc
->howto
== 0)
2495 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
2496 "internal error: can't export reloc type %d (`%s')",
2497 fixp
->fx_r_type
, bfd_get_reloc_code_name (code
));
2501 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
2504 if (reloc
->howto
->pc_relative
== 0
2505 || code
== BFD_RELOC_SPARC_PC10
2506 || code
== BFD_RELOC_SPARC_PC22
)
2507 reloc
->addend
= fixp
->fx_addnumber
;
2509 reloc
->addend
= fixp
->fx_offset
- reloc
->address
;
2511 #else /* elf or coff */
2513 if (reloc
->howto
->pc_relative
== 0
2514 || code
== BFD_RELOC_SPARC_PC10
2515 || code
== BFD_RELOC_SPARC_PC22
)
2516 reloc
->addend
= fixp
->fx_addnumber
;
2517 else if ((fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) != 0)
2518 reloc
->addend
= (section
->vma
2519 + fixp
->fx_addnumber
2520 + md_pcrel_from (fixp
));
2522 reloc
->addend
= fixp
->fx_offset
;
2528 /* We have no need to default values of symbols. */
2532 md_undefined_symbol (name
)
2536 } /* md_undefined_symbol() */
2538 /* Round up a section size to the appropriate boundary. */
2540 md_section_align (segment
, size
)
2545 /* This is not right for ELF; a.out wants it, and COFF will force
2546 the alignment anyways. */
2547 valueT align
= ((valueT
) 1
2548 << (valueT
) bfd_get_section_alignment (stdoutput
, segment
));
2550 /* turn alignment value into a mask */
2552 newsize
= (size
+ align
) & ~align
;
2559 /* Exactly what point is a PC-relative offset relative TO?
2560 On the sparc, they're relative to the address of the offset, plus
2561 its size. This gets us to the following instruction.
2562 (??? Is this right? FIXME-SOON) */
2564 md_pcrel_from (fixP
)
2569 ret
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2570 if (! sparc_pic_code
2571 || fixP
->fx_addsy
== NULL
2572 || (fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) != 0)
2573 ret
+= fixP
->fx_size
;
2578 * sort of like s_lcomm
2582 static int max_alignment
= 15;
2597 name
= input_line_pointer
;
2598 c
= get_symbol_end ();
2599 p
= input_line_pointer
;
2603 if (*input_line_pointer
!= ',')
2605 as_bad ("Expected comma after name");
2606 ignore_rest_of_line ();
2610 ++input_line_pointer
;
2612 if ((size
= get_absolute_expression ()) < 0)
2614 as_bad ("BSS length (%d.) <0! Ignored.", size
);
2615 ignore_rest_of_line ();
2620 symbolP
= symbol_find_or_make (name
);
2623 if (strncmp (input_line_pointer
, ",\"bss\"", 6) != 0
2624 && strncmp (input_line_pointer
, ",\".bss\"", 7) != 0)
2626 as_bad ("bad .reserve segment -- expected BSS segment");
2630 if (input_line_pointer
[2] == '.')
2631 input_line_pointer
+= 7;
2633 input_line_pointer
+= 6;
2636 if (*input_line_pointer
== ',')
2638 ++input_line_pointer
;
2641 if (*input_line_pointer
== '\n')
2643 as_bad ("Missing alignment");
2647 align
= get_absolute_expression ();
2649 if (align
> max_alignment
)
2651 align
= max_alignment
;
2652 as_warn ("Alignment too large: %d. assumed.", align
);
2658 as_warn ("Alignment negative. 0 assumed.");
2661 record_alignment (bss_section
, align
);
2663 /* convert to a power of 2 alignment */
2664 for (temp
= 0; (align
& 1) == 0; align
>>= 1, ++temp
);;
2668 as_bad ("Alignment not a power of 2");
2669 ignore_rest_of_line ();
2671 } /* not a power of two */
2674 } /* if has optional alignment */
2678 if (!S_IS_DEFINED (symbolP
)
2680 && S_GET_OTHER (symbolP
) == 0
2681 && S_GET_DESC (symbolP
) == 0
2688 segT current_seg
= now_seg
;
2689 subsegT current_subseg
= now_subseg
;
2691 subseg_set (bss_section
, 1); /* switch to bss */
2694 frag_align (align
, 0, 0); /* do alignment */
2696 /* detach from old frag */
2697 if (S_GET_SEGMENT(symbolP
) == bss_section
)
2698 symbolP
->sy_frag
->fr_symbol
= NULL
;
2700 symbolP
->sy_frag
= frag_now
;
2701 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
)0, symbolP
,
2702 (offsetT
) size
, (char *)0);
2705 S_SET_SEGMENT (symbolP
, bss_section
);
2707 subseg_set (current_seg
, current_subseg
);
2712 as_warn("Ignoring attempt to re-define symbol %s",
2713 S_GET_NAME (symbolP
));
2714 } /* if not redefining */
2716 demand_empty_rest_of_line ();
2729 name
= input_line_pointer
;
2730 c
= get_symbol_end ();
2731 /* just after name is now '\0' */
2732 p
= input_line_pointer
;
2735 if (*input_line_pointer
!= ',')
2737 as_bad ("Expected comma after symbol-name");
2738 ignore_rest_of_line ();
2741 input_line_pointer
++; /* skip ',' */
2742 if ((temp
= get_absolute_expression ()) < 0)
2744 as_bad (".COMMon length (%d.) <0! Ignored.", temp
);
2745 ignore_rest_of_line ();
2750 symbolP
= symbol_find_or_make (name
);
2752 if (S_IS_DEFINED (symbolP
) && ! S_IS_COMMON (symbolP
))
2754 as_bad ("Ignoring attempt to re-define symbol");
2755 ignore_rest_of_line ();
2758 if (S_GET_VALUE (symbolP
) != 0)
2760 if (S_GET_VALUE (symbolP
) != size
)
2762 as_warn ("Length of .comm \"%s\" is already %ld. Not changed to %d.",
2763 S_GET_NAME (symbolP
), (long) S_GET_VALUE (symbolP
), size
);
2769 S_SET_VALUE (symbolP
, (valueT
) size
);
2770 S_SET_EXTERNAL (symbolP
);
2773 know (symbolP
->sy_frag
== &zero_address_frag
);
2774 if (*input_line_pointer
!= ',')
2776 as_bad ("Expected comma after common length");
2777 ignore_rest_of_line ();
2780 input_line_pointer
++;
2782 if (*input_line_pointer
!= '"')
2784 temp
= get_absolute_expression ();
2786 if (temp
> max_alignment
)
2788 temp
= max_alignment
;
2789 as_warn ("Common alignment too large: %d. assumed", temp
);
2795 as_warn ("Common alignment negative; 0 assumed");
2806 old_subsec
= now_subseg
;
2808 record_alignment (bss_section
, align
);
2809 subseg_set (bss_section
, 0);
2811 frag_align (align
, 0, 0);
2812 if (S_GET_SEGMENT (symbolP
) == bss_section
)
2813 symbolP
->sy_frag
->fr_symbol
= 0;
2814 symbolP
->sy_frag
= frag_now
;
2815 p
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
2816 (offsetT
) size
, (char *) 0);
2818 S_SET_SEGMENT (symbolP
, bss_section
);
2819 S_CLEAR_EXTERNAL (symbolP
);
2820 subseg_set (old_sec
, old_subsec
);
2826 S_SET_VALUE (symbolP
, (valueT
) size
);
2828 S_SET_ALIGN (symbolP
, temp
);
2830 S_SET_EXTERNAL (symbolP
);
2831 S_SET_SEGMENT (symbolP
, bfd_com_section_ptr
);
2836 input_line_pointer
++;
2837 /* @@ Some use the dot, some don't. Can we get some consistency?? */
2838 if (*input_line_pointer
== '.')
2839 input_line_pointer
++;
2840 /* @@ Some say data, some say bss. */
2841 if (strncmp (input_line_pointer
, "bss\"", 4)
2842 && strncmp (input_line_pointer
, "data\"", 5))
2844 while (*--input_line_pointer
!= '"')
2846 input_line_pointer
--;
2847 goto bad_common_segment
;
2849 while (*input_line_pointer
++ != '"')
2851 goto allocate_common
;
2854 #ifdef BFD_ASSEMBLER
2855 symbolP
->bsym
->flags
|= BSF_OBJECT
;
2858 demand_empty_rest_of_line ();
2863 p
= input_line_pointer
;
2864 while (*p
&& *p
!= '\n')
2868 as_bad ("bad .common segment %s", input_line_pointer
+ 1);
2870 input_line_pointer
= p
;
2871 ignore_rest_of_line ();
2876 /* Handle the .empty pseudo-op. This supresses the warnings about
2877 invalid delay slot usage. */
2883 /* The easy way to implement is to just forget about the last
2893 if (strncmp (input_line_pointer
, "\"text\"", 6) == 0)
2895 input_line_pointer
+= 6;
2899 if (strncmp (input_line_pointer
, "\"data\"", 6) == 0)
2901 input_line_pointer
+= 6;
2905 if (strncmp (input_line_pointer
, "\"data1\"", 7) == 0)
2907 input_line_pointer
+= 7;
2911 if (strncmp (input_line_pointer
, "\"bss\"", 5) == 0)
2913 input_line_pointer
+= 5;
2914 /* We only support 2 segments -- text and data -- for now, so
2915 things in the "bss segment" will have to go into data for now.
2916 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
2917 subseg_set (data_section
, 255); /* FIXME-SOMEDAY */
2920 as_bad ("Unknown segment type");
2921 demand_empty_rest_of_line ();
2927 subseg_set (data_section
, 1);
2928 demand_empty_rest_of_line ();
2935 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2937 ++input_line_pointer
;
2939 ++input_line_pointer
;
2942 /* This static variable is set by s_uacons to tell sparc_cons_align
2943 that the expession does not need to be aligned. */
2945 static int sparc_no_align_cons
= 0;
2947 /* This handles the unaligned space allocation pseudo-ops, such as
2948 .uaword. .uaword is just like .word, but the value does not need
2955 /* Tell sparc_cons_align not to align this value. */
2956 sparc_no_align_cons
= 1;
2960 /* If the --enforce-aligned-data option is used, we require .word,
2961 et. al., to be aligned correctly. We do it by setting up an
2962 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
2963 no unexpected alignment was introduced.
2965 The SunOS and Solaris native assemblers enforce aligned data by
2966 default. We don't want to do that, because gcc can deliberately
2967 generate misaligned data if the packed attribute is used. Instead,
2968 we permit misaligned data by default, and permit the user to set an
2969 option to check for it. */
2972 sparc_cons_align (nbytes
)
2978 /* Only do this if we are enforcing aligned data. */
2979 if (! enforce_aligned_data
)
2982 if (sparc_no_align_cons
)
2984 /* This is an unaligned pseudo-op. */
2985 sparc_no_align_cons
= 0;
2990 while ((nbytes
& 1) == 0)
2999 if (now_seg
== absolute_section
)
3001 if ((abs_section_offset
& ((1 << nalign
) - 1)) != 0)
3002 as_bad ("misaligned data");
3006 p
= frag_var (rs_align_code
, 1, 1, (relax_substateT
) 0,
3007 (symbolS
*) NULL
, (offsetT
) nalign
, (char *) NULL
);
3009 record_alignment (now_seg
, nalign
);
3012 /* This is where we do the unexpected alignment check.
3013 This is called from HANDLE_ALIGN in tc-sparc.h. */
3016 sparc_handle_align (fragp
)
3019 if (fragp
->fr_type
== rs_align_code
3020 && fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
!= 0)
3021 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, "misaligned data");