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gas TC_PARSE_CONS_EXPRESSION communication with TC_CONS_FIX_NEW
[binutils-gdb.git] / gas / config / tc-v850.c
1 /* tc-v850.c -- Assembler code for the NEC V850
2 Copyright (C) 1996-2014 Free Software Foundation, Inc.
3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor,
19 Boston, MA 02110-1301, USA. */
20
21 #include "as.h"
22 #include "safe-ctype.h"
23 #include "subsegs.h"
24 #include "opcode/v850.h"
25 #include "dwarf2dbg.h"
26
27 /* Sign-extend a 16-bit number. */
28 #define SEXT16(x) ((((x) & 0xffff) ^ (~0x7fff)) + 0x8000)
29
30 /* Set to TRUE if we want to be pedantic about signed overflows. */
31 static bfd_boolean warn_signed_overflows = FALSE;
32 static bfd_boolean warn_unsigned_overflows = FALSE;
33
34 /* Indicates the target BFD machine number. */
35 static int machine = -1;
36
37
38 /* Indiciates the target BFD architecture. */
39 int v850_target_arch = bfd_arch_v850_rh850;
40 const char * v850_target_format = "elf32-v850-rh850";
41 static flagword v850_e_flags = 0;
42
43 /* Indicates the target processor(s) for the assemble. */
44 static int processor_mask = 0;
45 \f
46 /* Structure to hold information about predefined registers. */
47 struct reg_name
48 {
49 const char *name;
50 int value;
51 unsigned int processors;
52 };
53
54 /* Generic assembler global variables which must be defined by all
55 targets. */
56
57 /* Characters which always start a comment. */
58 const char comment_chars[] = "#";
59
60 /* Characters which start a comment at the beginning of a line. */
61 const char line_comment_chars[] = ";#";
62
63 /* Characters which may be used to separate multiple commands on a
64 single line. */
65 const char line_separator_chars[] = ";";
66
67 /* Characters which are used to indicate an exponent in a floating
68 point number. */
69 const char EXP_CHARS[] = "eE";
70
71 /* Characters which mean that a number is a floating point constant,
72 as in 0d1.0. */
73 const char FLT_CHARS[] = "dD";
74 \f
75 const relax_typeS md_relax_table[] =
76 {
77 /* Conditional branches.(V850/V850E, max 22bit) */
78 #define SUBYPTE_COND_9_22 0
79 {0xfe, -0x100, 2, SUBYPTE_COND_9_22 + 1},
80 {0x1ffffe + 2, -0x200000 + 2, 6, 0},
81 /* Conditional branches.(V850/V850E, max 22bit) */
82 #define SUBYPTE_SA_9_22 2
83 {0xfe, -0x100, 2, SUBYPTE_SA_9_22 + 1},
84 {0x1ffffe + 4, -0x200000 + 4, 8, 0},
85 /* Unconditional branches.(V850/V850E, max 22bit) */
86 #define SUBYPTE_UNCOND_9_22 4
87 {0xfe, -0x100, 2, SUBYPTE_UNCOND_9_22 + 1},
88 {0x1ffffe, -0x200000, 4, 0},
89 /* Conditional branches.(V850E2, max 32bit) */
90 #define SUBYPTE_COND_9_22_32 6
91 {0xfe, -0x100, 2, SUBYPTE_COND_9_22_32 + 1},
92 {0x1fffff + 2, -0x200000 + 2, 6, SUBYPTE_COND_9_22_32 + 2},
93 {0x7ffffffe, -0x80000000, 8, 0},
94 /* Conditional branches.(V850E2, max 32bit) */
95 #define SUBYPTE_SA_9_22_32 9
96 {0xfe, -0x100, 2, SUBYPTE_SA_9_22_32 + 1},
97 {0x1ffffe + 4, -0x200000 + 4, 8, SUBYPTE_SA_9_22_32 + 2},
98 {0x7ffffffe, -0x80000000, 10, 0},
99 /* Unconditional branches.(V850E2, max 32bit) */
100 #define SUBYPTE_UNCOND_9_22_32 12
101 {0xfe, -0x100, 2, SUBYPTE_UNCOND_9_22_32 + 1},
102 {0x1ffffe, -0x200000, 4, SUBYPTE_UNCOND_9_22_32 + 2},
103 {0x7ffffffe, -0x80000000, 6, 0},
104 /* Conditional branches.(V850E2R max 22bit) */
105 #define SUBYPTE_COND_9_17_22 15
106 {0xfe, -0x100, 2, SUBYPTE_COND_9_17_22 + 1},
107 {0xfffe, -0x10000, 4, SUBYPTE_COND_9_17_22 + 2},
108 {0x1ffffe + 2, -0x200000 + 2, 6, 0},
109 /* Conditional branches.(V850E2R max 22bit) */
110 #define SUBYPTE_SA_9_17_22 18
111 {0xfe, -0x100, 2, SUBYPTE_SA_9_17_22 + 1},
112 {0xfffe, -0x10000, 4, SUBYPTE_SA_9_17_22 + 2},
113 {0x1ffffe + 4, -0x200000 + 4, 8, 0},
114 /* Conditional branches.(V850E2R max 32bit) */
115 #define SUBYPTE_COND_9_17_22_32 21
116 {0xfe, -0x100, 2, SUBYPTE_COND_9_17_22_32 + 1},
117 {0xfffe, -0x10000, 4, SUBYPTE_COND_9_17_22_32 + 2},
118 {0x1ffffe + 2, -0x200000 + 2, 6, SUBYPTE_COND_9_17_22_32 + 3},
119 {0x7ffffffe, -0x80000000, 8, 0},
120 /* Conditional branches.(V850E2R max 32bit) */
121 #define SUBYPTE_SA_9_17_22_32 25
122 {0xfe, -0x100, 2, SUBYPTE_SA_9_17_22_32 + 1},
123 {0xfffe, -0x10000, 4, SUBYPTE_SA_9_17_22_32 + 2},
124 {0x1ffffe + 4, -0x200000 + 4, 8, SUBYPTE_SA_9_17_22_32 + 3},
125 {0x7ffffffe, -0x80000000, 10, 0},
126 /* Loop. (V850E2V4_UP, max 22-bit). */
127 #define SUBYPTE_LOOP_16_22 29
128 {0x0, -0x0fffe, 4, SUBYPTE_LOOP_16_22 + 1},
129 {0x1ffffe + 2, -0x200000 + 2, 6, 0},
130 };
131
132 static int v850_relax = 0;
133
134 /* Default branch disp size 22 or 32. */
135 static int default_disp_size = 22;
136
137 /* Default no using bcond17. */
138 static int no_bcond17 = 0;
139
140 /* Default no using ld/st 23bit offset. */
141 static int no_stld23 = 0;
142
143 /* Fixups. */
144 #define MAX_INSN_FIXUPS 5
145
146 struct v850_fixup
147 {
148 expressionS exp;
149 int opindex;
150 bfd_reloc_code_real_type reloc;
151 };
152
153 struct v850_fixup fixups[MAX_INSN_FIXUPS];
154 static int fc;
155
156 struct v850_seg_entry
157 {
158 segT s;
159 const char *name;
160 flagword flags;
161 };
162
163 struct v850_seg_entry v850_seg_table[] =
164 {
165 { NULL, ".sdata",
166 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS
167 | SEC_SMALL_DATA },
168 { NULL, ".tdata",
169 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS },
170 { NULL, ".zdata",
171 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS },
172 { NULL, ".sbss",
173 SEC_ALLOC | SEC_SMALL_DATA },
174 { NULL, ".tbss",
175 SEC_ALLOC },
176 { NULL, ".zbss",
177 SEC_ALLOC},
178 { NULL, ".rosdata",
179 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_READONLY | SEC_DATA
180 | SEC_HAS_CONTENTS | SEC_SMALL_DATA },
181 { NULL, ".rozdata",
182 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_READONLY | SEC_DATA
183 | SEC_HAS_CONTENTS },
184 { NULL, ".scommon",
185 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS
186 | SEC_SMALL_DATA | SEC_IS_COMMON },
187 { NULL, ".tcommon",
188 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS
189 | SEC_IS_COMMON },
190 { NULL, ".zcommon",
191 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS
192 | SEC_IS_COMMON },
193 { NULL, ".call_table_data",
194 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS },
195 { NULL, ".call_table_text",
196 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_READONLY | SEC_CODE
197 | SEC_HAS_CONTENTS},
198 { NULL, ".bss",
199 SEC_ALLOC }
200 };
201
202 #define SDATA_SECTION 0
203 #define TDATA_SECTION 1
204 #define ZDATA_SECTION 2
205 #define SBSS_SECTION 3
206 #define TBSS_SECTION 4
207 #define ZBSS_SECTION 5
208 #define ROSDATA_SECTION 6
209 #define ROZDATA_SECTION 7
210 #define SCOMMON_SECTION 8
211 #define TCOMMON_SECTION 9
212 #define ZCOMMON_SECTION 10
213 #define CALL_TABLE_DATA_SECTION 11
214 #define CALL_TABLE_TEXT_SECTION 12
215 #define BSS_SECTION 13
216
217 static void
218 do_v850_seg (int i, subsegT sub)
219 {
220 struct v850_seg_entry *seg = v850_seg_table + i;
221
222 obj_elf_section_change_hook ();
223
224 if (seg->s != NULL)
225 subseg_set (seg->s, sub);
226 else
227 {
228 seg->s = subseg_new (seg->name, sub);
229 bfd_set_section_flags (stdoutput, seg->s, seg->flags);
230 if ((seg->flags & SEC_LOAD) == 0)
231 seg_info (seg->s)->bss = 1;
232 }
233 }
234
235 static void
236 v850_seg (int i)
237 {
238 subsegT sub = get_absolute_expression ();
239
240 do_v850_seg (i, sub);
241 demand_empty_rest_of_line ();
242 }
243
244 static void
245 v850_offset (int ignore ATTRIBUTE_UNUSED)
246 {
247 char *pfrag;
248 int temp = get_absolute_expression ();
249
250 pfrag = frag_var (rs_org, 1, 1, (relax_substateT)0, (symbolS *)0,
251 (offsetT) temp, (char *) 0);
252 *pfrag = 0;
253
254 demand_empty_rest_of_line ();
255 }
256
257 /* Copied from obj_elf_common() in gas/config/obj-elf.c. */
258
259 static void
260 v850_comm (int area)
261 {
262 char *name;
263 char c;
264 char *p;
265 int temp;
266 unsigned int size;
267 symbolS *symbolP;
268 int have_align;
269
270 name = input_line_pointer;
271 c = get_symbol_end ();
272
273 /* Just after name is now '\0'. */
274 p = input_line_pointer;
275 *p = c;
276
277 SKIP_WHITESPACE ();
278
279 if (*input_line_pointer != ',')
280 {
281 as_bad (_("Expected comma after symbol-name"));
282 ignore_rest_of_line ();
283 return;
284 }
285
286 /* Skip ','. */
287 input_line_pointer++;
288
289 if ((temp = get_absolute_expression ()) < 0)
290 {
291 /* xgettext:c-format */
292 as_bad (_(".COMMon length (%d.) < 0! Ignored."), temp);
293 ignore_rest_of_line ();
294 return;
295 }
296
297 size = temp;
298 *p = 0;
299 symbolP = symbol_find_or_make (name);
300 *p = c;
301
302 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
303 {
304 as_bad (_("Ignoring attempt to re-define symbol"));
305 ignore_rest_of_line ();
306 return;
307 }
308
309 if (S_GET_VALUE (symbolP) != 0)
310 {
311 if (S_GET_VALUE (symbolP) != size)
312 /* xgettext:c-format */
313 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %d."),
314 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), size);
315 }
316
317 know (symbol_get_frag (symbolP) == &zero_address_frag);
318
319 if (*input_line_pointer != ',')
320 have_align = 0;
321 else
322 {
323 have_align = 1;
324 input_line_pointer++;
325 SKIP_WHITESPACE ();
326 }
327
328 if (! have_align || *input_line_pointer != '"')
329 {
330 if (! have_align)
331 temp = 0;
332 else
333 {
334 temp = get_absolute_expression ();
335
336 if (temp < 0)
337 {
338 temp = 0;
339 as_warn (_("Common alignment negative; 0 assumed"));
340 }
341 }
342
343 if (symbol_get_obj (symbolP)->local)
344 {
345 segT old_sec;
346 int old_subsec;
347 char *pfrag;
348 int align;
349 flagword applicable;
350
351 old_sec = now_seg;
352 old_subsec = now_subseg;
353
354 applicable = bfd_applicable_section_flags (stdoutput);
355
356 applicable &= SEC_ALLOC;
357
358 switch (area)
359 {
360 case SCOMMON_SECTION:
361 do_v850_seg (SBSS_SECTION, 0);
362 break;
363
364 case ZCOMMON_SECTION:
365 do_v850_seg (ZBSS_SECTION, 0);
366 break;
367
368 case TCOMMON_SECTION:
369 do_v850_seg (TBSS_SECTION, 0);
370 break;
371 }
372
373 if (temp)
374 {
375 /* Convert to a power of 2 alignment. */
376 for (align = 0; (temp & 1) == 0; temp >>= 1, ++align)
377 ;
378
379 if (temp != 1)
380 {
381 as_bad (_("Common alignment not a power of 2"));
382 ignore_rest_of_line ();
383 return;
384 }
385 }
386 else
387 align = 0;
388
389 record_alignment (now_seg, align);
390
391 if (align)
392 frag_align (align, 0, 0);
393
394 switch (area)
395 {
396 case SCOMMON_SECTION:
397 if (S_GET_SEGMENT (symbolP) == v850_seg_table[SBSS_SECTION].s)
398 symbol_get_frag (symbolP)->fr_symbol = 0;
399 break;
400
401 case ZCOMMON_SECTION:
402 if (S_GET_SEGMENT (symbolP) == v850_seg_table[ZBSS_SECTION].s)
403 symbol_get_frag (symbolP)->fr_symbol = 0;
404 break;
405
406 case TCOMMON_SECTION:
407 if (S_GET_SEGMENT (symbolP) == v850_seg_table[TBSS_SECTION].s)
408 symbol_get_frag (symbolP)->fr_symbol = 0;
409 break;
410
411 default:
412 abort ();
413 }
414
415 symbol_set_frag (symbolP, frag_now);
416 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
417 (offsetT) size, (char *) 0);
418 *pfrag = 0;
419 S_SET_SIZE (symbolP, size);
420
421 switch (area)
422 {
423 case SCOMMON_SECTION:
424 S_SET_SEGMENT (symbolP, v850_seg_table[SBSS_SECTION].s);
425 break;
426
427 case ZCOMMON_SECTION:
428 S_SET_SEGMENT (symbolP, v850_seg_table[ZBSS_SECTION].s);
429 break;
430
431 case TCOMMON_SECTION:
432 S_SET_SEGMENT (symbolP, v850_seg_table[TBSS_SECTION].s);
433 break;
434
435 default:
436 abort ();
437 }
438
439 S_CLEAR_EXTERNAL (symbolP);
440 obj_elf_section_change_hook ();
441 subseg_set (old_sec, old_subsec);
442 }
443 else
444 {
445 segT old_sec;
446 int old_subsec;
447
448 allocate_common:
449 old_sec = now_seg;
450 old_subsec = now_subseg;
451
452 S_SET_VALUE (symbolP, (valueT) size);
453 S_SET_ALIGN (symbolP, temp);
454 S_SET_EXTERNAL (symbolP);
455
456 switch (area)
457 {
458 case SCOMMON_SECTION:
459 case ZCOMMON_SECTION:
460 case TCOMMON_SECTION:
461 do_v850_seg (area, 0);
462 S_SET_SEGMENT (symbolP, v850_seg_table[area].s);
463 break;
464
465 default:
466 abort ();
467 }
468
469 obj_elf_section_change_hook ();
470 subseg_set (old_sec, old_subsec);
471 }
472 }
473 else
474 {
475 input_line_pointer++;
476
477 /* @@ Some use the dot, some don't. Can we get some consistency?? */
478 if (*input_line_pointer == '.')
479 input_line_pointer++;
480
481 /* @@ Some say data, some say bss. */
482 if (strncmp (input_line_pointer, "bss\"", 4)
483 && strncmp (input_line_pointer, "data\"", 5))
484 {
485 while (*--input_line_pointer != '"')
486 ;
487 input_line_pointer--;
488 goto bad_common_segment;
489 }
490
491 while (*input_line_pointer++ != '"')
492 ;
493
494 goto allocate_common;
495 }
496
497 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
498
499 demand_empty_rest_of_line ();
500 return;
501
502 {
503 bad_common_segment:
504 p = input_line_pointer;
505 while (*p && *p != '\n')
506 p++;
507 c = *p;
508 *p = '\0';
509 as_bad (_("bad .common segment %s"), input_line_pointer + 1);
510 *p = c;
511 input_line_pointer = p;
512 ignore_rest_of_line ();
513 return;
514 }
515 }
516
517 static void
518 set_machine (int number)
519 {
520 machine = number;
521 bfd_set_arch_mach (stdoutput, v850_target_arch, machine);
522
523 switch (machine)
524 {
525 case 0: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850); break;
526 case bfd_mach_v850: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850); break;
527 case bfd_mach_v850e: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E); break;
528 case bfd_mach_v850e1: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E); break;
529 case bfd_mach_v850e2: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2); break;
530 case bfd_mach_v850e2v3:SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2V3); break;
531 case bfd_mach_v850e3v5: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5); break;
532 }
533 }
534
535 static void
536 v850_longcode (int type)
537 {
538 expressionS ex;
539
540 if (! v850_relax)
541 {
542 if (type == 1)
543 as_warn (_(".longcall pseudo-op seen when not relaxing"));
544 else
545 as_warn (_(".longjump pseudo-op seen when not relaxing"));
546 }
547
548 expression (&ex);
549
550 if (ex.X_op != O_symbol || ex.X_add_number != 0)
551 {
552 as_bad (_("bad .longcall format"));
553 ignore_rest_of_line ();
554
555 return;
556 }
557
558 if (type == 1)
559 fix_new_exp (frag_now, frag_now_fix (), 4, & ex, 1,
560 BFD_RELOC_V850_LONGCALL);
561 else
562 fix_new_exp (frag_now, frag_now_fix (), 4, & ex, 1,
563 BFD_RELOC_V850_LONGJUMP);
564
565 demand_empty_rest_of_line ();
566 }
567
568 /* The target specific pseudo-ops which we support. */
569 const pseudo_typeS md_pseudo_table[] =
570 {
571 { "sdata", v850_seg, SDATA_SECTION },
572 { "tdata", v850_seg, TDATA_SECTION },
573 { "zdata", v850_seg, ZDATA_SECTION },
574 { "sbss", v850_seg, SBSS_SECTION },
575 { "tbss", v850_seg, TBSS_SECTION },
576 { "zbss", v850_seg, ZBSS_SECTION },
577 { "rosdata", v850_seg, ROSDATA_SECTION },
578 { "rozdata", v850_seg, ROZDATA_SECTION },
579 { "bss", v850_seg, BSS_SECTION },
580 { "offset", v850_offset, 0 },
581 { "word", cons, 4 },
582 { "zcomm", v850_comm, ZCOMMON_SECTION },
583 { "scomm", v850_comm, SCOMMON_SECTION },
584 { "tcomm", v850_comm, TCOMMON_SECTION },
585 { "v850", set_machine, 0 },
586 { "call_table_data", v850_seg, CALL_TABLE_DATA_SECTION },
587 { "call_table_text", v850_seg, CALL_TABLE_TEXT_SECTION },
588 { "v850e", set_machine, bfd_mach_v850e },
589 { "v850e1", set_machine, bfd_mach_v850e1 },
590 { "v850e2", set_machine, bfd_mach_v850e2 },
591 { "v850e2v3", set_machine, bfd_mach_v850e2v3 },
592 { "v850e2v4", set_machine, bfd_mach_v850e3v5 },
593 { "v850e3v5", set_machine, bfd_mach_v850e3v5 },
594 { "longcall", v850_longcode, 1 },
595 { "longjump", v850_longcode, 2 },
596 { NULL, NULL, 0 }
597 };
598
599 /* Opcode hash table. */
600 static struct hash_control *v850_hash;
601
602 /* This table is sorted. Suitable for searching by a binary search. */
603 static const struct reg_name pre_defined_registers[] =
604 {
605 { "ep", 30, PROCESSOR_ALL }, /* ep - element ptr. */
606 { "gp", 4, PROCESSOR_ALL }, /* gp - global ptr. */
607 { "hp", 2, PROCESSOR_ALL }, /* hp - handler stack ptr. */
608 { "lp", 31, PROCESSOR_ALL }, /* lp - link ptr. */
609 { "r0", 0, PROCESSOR_ALL },
610 { "r1", 1, PROCESSOR_ALL },
611 { "r10", 10, PROCESSOR_ALL },
612 { "r11", 11, PROCESSOR_ALL },
613 { "r12", 12, PROCESSOR_ALL },
614 { "r13", 13, PROCESSOR_ALL },
615 { "r14", 14, PROCESSOR_ALL },
616 { "r15", 15, PROCESSOR_ALL },
617 { "r16", 16, PROCESSOR_ALL },
618 { "r17", 17, PROCESSOR_ALL },
619 { "r18", 18, PROCESSOR_ALL },
620 { "r19", 19, PROCESSOR_ALL },
621 { "r2", 2, PROCESSOR_ALL },
622 { "r20", 20, PROCESSOR_ALL },
623 { "r21", 21, PROCESSOR_ALL },
624 { "r22", 22, PROCESSOR_ALL },
625 { "r23", 23, PROCESSOR_ALL },
626 { "r24", 24, PROCESSOR_ALL },
627 { "r25", 25, PROCESSOR_ALL },
628 { "r26", 26, PROCESSOR_ALL },
629 { "r27", 27, PROCESSOR_ALL },
630 { "r28", 28, PROCESSOR_ALL },
631 { "r29", 29, PROCESSOR_ALL },
632 { "r3", 3, PROCESSOR_ALL },
633 { "r30", 30, PROCESSOR_ALL },
634 { "r31", 31, PROCESSOR_ALL },
635 { "r4", 4, PROCESSOR_ALL },
636 { "r5", 5, PROCESSOR_ALL },
637 { "r6", 6, PROCESSOR_ALL },
638 { "r7", 7, PROCESSOR_ALL },
639 { "r8", 8, PROCESSOR_ALL },
640 { "r9", 9, PROCESSOR_ALL },
641 { "sp", 3, PROCESSOR_ALL }, /* sp - stack ptr. */
642 { "tp", 5, PROCESSOR_ALL }, /* tp - text ptr. */
643 { "zero", 0, PROCESSOR_ALL },
644 };
645
646 #define REG_NAME_CNT \
647 (sizeof (pre_defined_registers) / sizeof (struct reg_name))
648
649 static const struct reg_name system_registers[] =
650 {
651 { "asid", 23, PROCESSOR_NOT_V850 },
652 { "bpam", 25, PROCESSOR_NOT_V850 },
653 { "bpav", 24, PROCESSOR_NOT_V850 },
654 { "bpc", 22, PROCESSOR_NOT_V850 },
655 { "bpdm", 27, PROCESSOR_NOT_V850 },
656 { "bpdv", 26, PROCESSOR_NOT_V850 },
657 { "bsel", 31, PROCESSOR_V850E2_UP },
658 { "cfg", 7, PROCESSOR_V850E2V3_UP },
659 { "ctbp", 20, PROCESSOR_NOT_V850 },
660 { "ctpc", 16, PROCESSOR_NOT_V850 },
661 { "ctpsw", 17, PROCESSOR_NOT_V850 },
662 { "dbic", 15, PROCESSOR_V850E2_UP },
663 { "dbpc", 18, PROCESSOR_NOT_V850 },
664 { "dbpsw", 19, PROCESSOR_NOT_V850 },
665 { "dbwr", 30, PROCESSOR_V850E2_UP },
666 { "dir", 21, PROCESSOR_NOT_V850 },
667 { "dpa0l", 16, PROCESSOR_V850E2V3_UP },
668 { "dpa0u", 17, PROCESSOR_V850E2V3_UP },
669 { "dpa1l", 18, PROCESSOR_V850E2V3_UP },
670 { "dpa1u", 19, PROCESSOR_V850E2V3_UP },
671 { "dpa2l", 20, PROCESSOR_V850E2V3_UP },
672 { "dpa2u", 21, PROCESSOR_V850E2V3_UP },
673 { "dpa3l", 22, PROCESSOR_V850E2V3_UP },
674 { "dpa3u", 23, PROCESSOR_V850E2V3_UP },
675 { "dpa4l", 24, PROCESSOR_V850E2V3_UP },
676 { "dpa4u", 25, PROCESSOR_V850E2V3_UP },
677 { "dpa5l", 26, PROCESSOR_V850E2V3_UP },
678 { "dpa5u", 27, PROCESSOR_V850E2V3_UP },
679 { "ecr", 4, PROCESSOR_ALL },
680 { "eh_base", 3, PROCESSOR_V850E2V3_UP },
681 { "eh_cfg", 1, PROCESSOR_V850E2V3_UP },
682 { "eh_reset", 2, PROCESSOR_V850E2V3_UP },
683 { "eiic", 13, PROCESSOR_V850E2_UP },
684 { "eipc", 0, PROCESSOR_ALL },
685 { "eipsw", 1, PROCESSOR_ALL },
686 { "eiwr", 28, PROCESSOR_V850E2_UP },
687 { "feic", 14, PROCESSOR_V850E2_UP },
688 { "fepc", 2, PROCESSOR_ALL },
689 { "fepsw", 3, PROCESSOR_ALL },
690 { "fewr", 29, PROCESSOR_V850E2_UP },
691 { "fpcc", 9, PROCESSOR_V850E2V3_UP },
692 { "fpcfg", 10, PROCESSOR_V850E2V3_UP },
693 { "fpec", 11, PROCESSOR_V850E2V3_UP },
694 { "fpepc", 7, PROCESSOR_V850E2V3_UP },
695 { "fpspc", 27, PROCESSOR_V850E2V3_UP },
696 { "fpsr", 6, PROCESSOR_V850E2V3_UP },
697 { "fpst", 8, PROCESSOR_V850E2V3_UP },
698 { "ipa0l", 6, PROCESSOR_V850E2V3_UP },
699 { "ipa0u", 7, PROCESSOR_V850E2V3_UP },
700 { "ipa1l", 8, PROCESSOR_V850E2V3_UP },
701 { "ipa1u", 9, PROCESSOR_V850E2V3_UP },
702 { "ipa2l", 10, PROCESSOR_V850E2V3_UP },
703 { "ipa2u", 11, PROCESSOR_V850E2V3_UP },
704 { "ipa3l", 12, PROCESSOR_V850E2V3_UP },
705 { "ipa3u", 13, PROCESSOR_V850E2V3_UP },
706 { "ipa4l", 14, PROCESSOR_V850E2V3_UP },
707 { "ipa4u", 15, PROCESSOR_V850E2V3_UP },
708 { "mca", 24, PROCESSOR_V850E2V3_UP },
709 { "mcc", 26, PROCESSOR_V850E2V3_UP },
710 { "mcr", 27, PROCESSOR_V850E2V3_UP },
711 { "mcs", 25, PROCESSOR_V850E2V3_UP },
712 { "mpc", 1, PROCESSOR_V850E2V3_UP },
713 { "mpm", 0, PROCESSOR_V850E2V3_UP },
714 { "mpu10_dpa0l", 16, PROCESSOR_V850E2V3_UP },
715 { "mpu10_dpa0u", 17, PROCESSOR_V850E2V3_UP },
716 { "mpu10_dpa1l", 18, PROCESSOR_V850E2V3_UP },
717 { "mpu10_dpa1u", 19, PROCESSOR_V850E2V3_UP },
718 { "mpu10_dpa2l", 20, PROCESSOR_V850E2V3_UP },
719 { "mpu10_dpa2u", 21, PROCESSOR_V850E2V3_UP },
720 { "mpu10_dpa3l", 22, PROCESSOR_V850E2V3_UP },
721 { "mpu10_dpa3u", 23, PROCESSOR_V850E2V3_UP },
722 { "mpu10_dpa4l", 24, PROCESSOR_V850E2V3_UP },
723 { "mpu10_dpa4u", 25, PROCESSOR_V850E2V3_UP },
724 { "mpu10_dpa5l", 26, PROCESSOR_V850E2V3_UP },
725 { "mpu10_dpa5u", 27, PROCESSOR_V850E2V3_UP },
726 { "mpu10_ipa0l", 6, PROCESSOR_V850E2V3_UP },
727 { "mpu10_ipa0u", 7, PROCESSOR_V850E2V3_UP },
728 { "mpu10_ipa1l", 8, PROCESSOR_V850E2V3_UP },
729 { "mpu10_ipa1u", 9, PROCESSOR_V850E2V3_UP },
730 { "mpu10_ipa2l", 10, PROCESSOR_V850E2V3_UP },
731 { "mpu10_ipa2u", 11, PROCESSOR_V850E2V3_UP },
732 { "mpu10_ipa3l", 12, PROCESSOR_V850E2V3_UP },
733 { "mpu10_ipa3u", 13, PROCESSOR_V850E2V3_UP },
734 { "mpu10_ipa4l", 14, PROCESSOR_V850E2V3_UP },
735 { "mpu10_ipa4u", 15, PROCESSOR_V850E2V3_UP },
736 { "mpu10_mpc", 1, PROCESSOR_V850E2V3_UP },
737 { "mpu10_mpm", 0, PROCESSOR_V850E2V3_UP },
738 { "mpu10_tid", 2, PROCESSOR_V850E2V3_UP },
739 { "mpu10_vmadr", 5, PROCESSOR_V850E2V3_UP },
740 { "mpu10_vmecr", 3, PROCESSOR_V850E2V3_UP },
741 { "mpu10_vmtid", 4, PROCESSOR_V850E2V3_UP },
742 { "pid", 6, PROCESSOR_V850E2V3_UP },
743 { "pmcr0", 4, PROCESSOR_V850E2V3_UP },
744 { "pmis2", 14, PROCESSOR_V850E2V3_UP },
745 { "psw", 5, PROCESSOR_ALL },
746 { "scbp", 12, PROCESSOR_V850E2V3_UP },
747 { "sccfg", 11, PROCESSOR_V850E2V3_UP },
748 { "sr0", 0, PROCESSOR_ALL },
749 { "sr1", 1, PROCESSOR_ALL },
750 { "sr10", 10, PROCESSOR_ALL },
751 { "sr11", 11, PROCESSOR_ALL },
752 { "sr12", 12, PROCESSOR_ALL },
753 { "sr13", 13, PROCESSOR_ALL },
754 { "sr14", 14, PROCESSOR_ALL },
755 { "sr15", 15, PROCESSOR_ALL },
756 { "sr16", 16, PROCESSOR_ALL },
757 { "sr17", 17, PROCESSOR_ALL },
758 { "sr18", 18, PROCESSOR_ALL },
759 { "sr19", 19, PROCESSOR_ALL },
760 { "sr2", 2, PROCESSOR_ALL },
761 { "sr20", 20, PROCESSOR_ALL },
762 { "sr21", 21, PROCESSOR_ALL },
763 { "sr22", 22, PROCESSOR_ALL },
764 { "sr23", 23, PROCESSOR_ALL },
765 { "sr24", 24, PROCESSOR_ALL },
766 { "sr25", 25, PROCESSOR_ALL },
767 { "sr26", 26, PROCESSOR_ALL },
768 { "sr27", 27, PROCESSOR_ALL },
769 { "sr28", 28, PROCESSOR_ALL },
770 { "sr29", 29, PROCESSOR_ALL },
771 { "sr3", 3, PROCESSOR_ALL },
772 { "sr30", 30, PROCESSOR_ALL },
773 { "sr31", 31, PROCESSOR_ALL },
774 { "sr4", 4, PROCESSOR_ALL },
775 { "sr5", 5, PROCESSOR_ALL },
776 { "sr6", 6, PROCESSOR_ALL },
777 { "sr7", 7, PROCESSOR_ALL },
778 { "sr8", 8, PROCESSOR_ALL },
779 { "sr9", 9, PROCESSOR_ALL },
780 { "sw_base", 3, PROCESSOR_V850E2V3_UP },
781 { "sw_cfg", 1, PROCESSOR_V850E2V3_UP },
782 { "sw_ctl", 0, PROCESSOR_V850E2V3_UP },
783 { "tid", 2, PROCESSOR_V850E2V3_UP },
784 { "vmadr", 6, PROCESSOR_V850E2V3_UP },
785 { "vmecr", 4, PROCESSOR_V850E2V3_UP },
786 { "vmtid", 5, PROCESSOR_V850E2V3_UP },
787 { "vsadr", 2, PROCESSOR_V850E2V3_UP },
788 { "vsecr", 0, PROCESSOR_V850E2V3_UP },
789 { "vstid", 1, PROCESSOR_V850E2V3_UP },
790 };
791
792 #define SYSREG_NAME_CNT \
793 (sizeof (system_registers) / sizeof (struct reg_name))
794
795
796 static const struct reg_name cc_names[] =
797 {
798 { "c", 0x1, PROCESSOR_ALL },
799 { "e", 0x2, PROCESSOR_ALL },
800 { "ge", 0xe, PROCESSOR_ALL },
801 { "gt", 0xf, PROCESSOR_ALL },
802 { "h", 0xb, PROCESSOR_ALL },
803 { "l", 0x1, PROCESSOR_ALL },
804 { "le", 0x7, PROCESSOR_ALL },
805 { "lt", 0x6, PROCESSOR_ALL },
806 { "n", 0x4, PROCESSOR_ALL },
807 { "nc", 0x9, PROCESSOR_ALL },
808 { "ne", 0xa, PROCESSOR_ALL },
809 { "nh", 0x3, PROCESSOR_ALL },
810 { "nl", 0x9, PROCESSOR_ALL },
811 { "ns", 0xc, PROCESSOR_ALL },
812 { "nv", 0x8, PROCESSOR_ALL },
813 { "nz", 0xa, PROCESSOR_ALL },
814 { "p", 0xc, PROCESSOR_ALL },
815 { "s", 0x4, PROCESSOR_ALL },
816 #define COND_SA_NUM 0xd
817 { "sa", COND_SA_NUM, PROCESSOR_ALL },
818 { "t", 0x5, PROCESSOR_ALL },
819 { "v", 0x0, PROCESSOR_ALL },
820 { "z", 0x2, PROCESSOR_ALL },
821 };
822
823 #define CC_NAME_CNT \
824 (sizeof (cc_names) / sizeof (struct reg_name))
825
826 static const struct reg_name float_cc_names[] =
827 {
828 { "eq", 0x2, PROCESSOR_V850E2V3_UP }, /* true. */
829 { "f", 0x0, PROCESSOR_V850E2V3_UP }, /* true. */
830 { "ge", 0xd, PROCESSOR_V850E2V3_UP }, /* false. */
831 { "gl", 0xb, PROCESSOR_V850E2V3_UP }, /* false. */
832 { "gle", 0x9, PROCESSOR_V850E2V3_UP }, /* false. */
833 { "gt", 0xf, PROCESSOR_V850E2V3_UP }, /* false. */
834 { "le", 0xe, PROCESSOR_V850E2V3_UP }, /* true. */
835 { "lt", 0xc, PROCESSOR_V850E2V3_UP }, /* true. */
836 { "neq", 0x2, PROCESSOR_V850E2V3_UP }, /* false. */
837 { "nge", 0xd, PROCESSOR_V850E2V3_UP }, /* true. */
838 { "ngl", 0xb, PROCESSOR_V850E2V3_UP }, /* true. */
839 { "ngle",0x9, PROCESSOR_V850E2V3_UP }, /* true. */
840 { "ngt", 0xf, PROCESSOR_V850E2V3_UP }, /* true. */
841 { "nle", 0xe, PROCESSOR_V850E2V3_UP }, /* false. */
842 { "nlt", 0xc, PROCESSOR_V850E2V3_UP }, /* false. */
843 { "oge", 0x5, PROCESSOR_V850E2V3_UP }, /* false. */
844 { "ogl", 0x3, PROCESSOR_V850E2V3_UP }, /* false. */
845 { "ogt", 0x7, PROCESSOR_V850E2V3_UP }, /* false. */
846 { "ole", 0x6, PROCESSOR_V850E2V3_UP }, /* true. */
847 { "olt", 0x4, PROCESSOR_V850E2V3_UP }, /* true. */
848 { "or", 0x1, PROCESSOR_V850E2V3_UP }, /* false. */
849 { "seq", 0xa, PROCESSOR_V850E2V3_UP }, /* true. */
850 { "sf", 0x8, PROCESSOR_V850E2V3_UP }, /* true. */
851 { "sne", 0xa, PROCESSOR_V850E2V3_UP }, /* false. */
852 { "st", 0x8, PROCESSOR_V850E2V3_UP }, /* false. */
853 { "t", 0x0, PROCESSOR_V850E2V3_UP }, /* false. */
854 { "ueq", 0x3, PROCESSOR_V850E2V3_UP }, /* true. */
855 { "uge", 0x4, PROCESSOR_V850E2V3_UP }, /* false. */
856 { "ugt", 0x6, PROCESSOR_V850E2V3_UP }, /* false. */
857 { "ule", 0x7, PROCESSOR_V850E2V3_UP }, /* true. */
858 { "ult", 0x5, PROCESSOR_V850E2V3_UP }, /* true. */
859 { "un", 0x1, PROCESSOR_V850E2V3_UP }, /* true. */
860 };
861
862 #define FLOAT_CC_NAME_CNT \
863 (sizeof (float_cc_names) / sizeof (struct reg_name))
864
865
866 static const struct reg_name cacheop_names[] =
867 {
868 { "cfald", 0x44, PROCESSOR_V850E3V5_UP },
869 { "cfali", 0x40, PROCESSOR_V850E3V5_UP },
870 { "chbid", 0x04, PROCESSOR_V850E3V5_UP },
871 { "chbii", 0x00, PROCESSOR_V850E3V5_UP },
872 { "chbiwbd", 0x06, PROCESSOR_V850E3V5_UP },
873 { "chbwbd", 0x07, PROCESSOR_V850E3V5_UP },
874 { "cibid", 0x24, PROCESSOR_V850E3V5_UP },
875 { "cibii", 0x20, PROCESSOR_V850E3V5_UP },
876 { "cibiwbd", 0x26, PROCESSOR_V850E3V5_UP },
877 { "cibwbd", 0x27, PROCESSOR_V850E3V5_UP },
878 { "cildd", 0x65, PROCESSOR_V850E3V5_UP },
879 { "cildi", 0x61, PROCESSOR_V850E3V5_UP },
880 { "cistd", 0x64, PROCESSOR_V850E3V5_UP },
881 { "cisti", 0x60, PROCESSOR_V850E3V5_UP },
882 };
883
884 #define CACHEOP_NAME_CNT \
885 (sizeof (cacheop_names) / sizeof (struct reg_name))
886
887 static const struct reg_name prefop_names[] =
888 {
889 { "prefd", 0x04, PROCESSOR_V850E3V5_UP },
890 { "prefi", 0x00, PROCESSOR_V850E3V5_UP },
891 };
892
893 #define PREFOP_NAME_CNT \
894 (sizeof (prefop_names) / sizeof (struct reg_name))
895
896 static const struct reg_name vector_registers[] =
897 {
898 { "vr0", 0, PROCESSOR_V850E3V5_UP },
899 { "vr1", 1, PROCESSOR_V850E3V5_UP },
900 { "vr10", 10, PROCESSOR_V850E3V5_UP },
901 { "vr11", 11, PROCESSOR_V850E3V5_UP },
902 { "vr12", 12, PROCESSOR_V850E3V5_UP },
903 { "vr13", 13, PROCESSOR_V850E3V5_UP },
904 { "vr14", 14, PROCESSOR_V850E3V5_UP },
905 { "vr15", 15, PROCESSOR_V850E3V5_UP },
906 { "vr16", 16, PROCESSOR_V850E3V5_UP },
907 { "vr17", 17, PROCESSOR_V850E3V5_UP },
908 { "vr18", 18, PROCESSOR_V850E3V5_UP },
909 { "vr19", 19, PROCESSOR_V850E3V5_UP },
910 { "vr2", 2, PROCESSOR_V850E3V5_UP },
911 { "vr20", 20, PROCESSOR_V850E3V5_UP },
912 { "vr21", 21, PROCESSOR_V850E3V5_UP },
913 { "vr22", 22, PROCESSOR_V850E3V5_UP },
914 { "vr23", 23, PROCESSOR_V850E3V5_UP },
915 { "vr24", 24, PROCESSOR_V850E3V5_UP },
916 { "vr25", 25, PROCESSOR_V850E3V5_UP },
917 { "vr26", 26, PROCESSOR_V850E3V5_UP },
918 { "vr27", 27, PROCESSOR_V850E3V5_UP },
919 { "vr28", 28, PROCESSOR_V850E3V5_UP },
920 { "vr29", 29, PROCESSOR_V850E3V5_UP },
921 { "vr3", 3, PROCESSOR_V850E3V5_UP },
922 { "vr30", 30, PROCESSOR_V850E3V5_UP },
923 { "vr31", 31, PROCESSOR_V850E3V5_UP },
924 { "vr4", 4, PROCESSOR_V850E3V5_UP },
925 { "vr5", 5, PROCESSOR_V850E3V5_UP },
926 { "vr6", 6, PROCESSOR_V850E3V5_UP },
927 { "vr7", 7, PROCESSOR_V850E3V5_UP },
928 { "vr8", 8, PROCESSOR_V850E3V5_UP },
929 { "vr9", 9, PROCESSOR_V850E3V5_UP },
930 };
931
932 #define VREG_NAME_CNT \
933 (sizeof (vector_registers) / sizeof (struct reg_name))
934
935 /* Do a binary search of the given register table to see if NAME is a
936 valid regiter name. Return the register number from the array on
937 success, or -1 on failure. */
938
939 static int
940 reg_name_search (const struct reg_name *regs,
941 int regcount,
942 const char *name,
943 bfd_boolean accept_numbers)
944 {
945 int middle, low, high;
946 int cmp;
947 symbolS *symbolP;
948
949 /* If the register name is a symbol, then evaluate it. */
950 if ((symbolP = symbol_find (name)) != NULL)
951 {
952 /* If the symbol is an alias for another name then use that.
953 If the symbol is an alias for a number, then return the number. */
954 if (symbol_equated_p (symbolP))
955 name
956 = S_GET_NAME (symbol_get_value_expression (symbolP)->X_add_symbol);
957 else if (accept_numbers)
958 {
959 int reg = S_GET_VALUE (symbolP);
960 return reg;
961 }
962
963 /* Otherwise drop through and try parsing name normally. */
964 }
965
966 low = 0;
967 high = regcount - 1;
968
969 do
970 {
971 middle = (low + high) / 2;
972 cmp = strcasecmp (name, regs[middle].name);
973 if (cmp < 0)
974 high = middle - 1;
975 else if (cmp > 0)
976 low = middle + 1;
977 else
978 return ((regs[middle].processors & processor_mask)
979 ? regs[middle].value
980 : -1);
981 }
982 while (low <= high);
983 return -1;
984 }
985
986 /* Summary of register_name().
987
988 in: Input_line_pointer points to 1st char of operand.
989
990 out: An expressionS.
991 The operand may have been a register: in this case, X_op == O_register,
992 X_add_number is set to the register number, and truth is returned.
993 Input_line_pointer->(next non-blank) char after operand, or is in
994 its original state. */
995
996 static bfd_boolean
997 register_name (expressionS *expressionP)
998 {
999 int reg_number;
1000 char *name;
1001 char *start;
1002 char c;
1003
1004 /* Find the spelling of the operand. */
1005 start = name = input_line_pointer;
1006
1007 c = get_symbol_end ();
1008
1009 reg_number = reg_name_search (pre_defined_registers, REG_NAME_CNT,
1010 name, FALSE);
1011
1012 /* Put back the delimiting char. */
1013 *input_line_pointer = c;
1014
1015 expressionP->X_add_symbol = NULL;
1016 expressionP->X_op_symbol = NULL;
1017
1018 /* Look to see if it's in the register table. */
1019 if (reg_number >= 0)
1020 {
1021 expressionP->X_op = O_register;
1022 expressionP->X_add_number = reg_number;
1023
1024 return TRUE;
1025 }
1026
1027 /* Reset the line as if we had not done anything. */
1028 input_line_pointer = start;
1029
1030 expressionP->X_op = O_illegal;
1031
1032 return FALSE;
1033 }
1034
1035 /* Summary of system_register_name().
1036
1037 in: INPUT_LINE_POINTER points to 1st char of operand.
1038 EXPRESSIONP points to an expression structure to be filled in.
1039 ACCEPT_NUMBERS is true iff numerical register names may be used.
1040
1041 out: An expressionS structure in expressionP.
1042 The operand may have been a register: in this case, X_op == O_register,
1043 X_add_number is set to the register number, and truth is returned.
1044 Input_line_pointer->(next non-blank) char after operand, or is in
1045 its original state. */
1046
1047 static bfd_boolean
1048 system_register_name (expressionS *expressionP,
1049 bfd_boolean accept_numbers)
1050 {
1051 int reg_number;
1052 char *name;
1053 char *start;
1054 char c;
1055
1056 /* Find the spelling of the operand. */
1057 start = name = input_line_pointer;
1058
1059 c = get_symbol_end ();
1060 reg_number = reg_name_search (system_registers, SYSREG_NAME_CNT, name,
1061 accept_numbers);
1062
1063 /* Put back the delimiting char. */
1064 *input_line_pointer = c;
1065
1066 if (reg_number < 0
1067 && accept_numbers)
1068 {
1069 /* Reset input_line pointer. */
1070 input_line_pointer = start;
1071
1072 if (ISDIGIT (*input_line_pointer))
1073 {
1074 reg_number = strtol (input_line_pointer, &input_line_pointer, 0);
1075 }
1076 }
1077
1078 expressionP->X_add_symbol = NULL;
1079 expressionP->X_op_symbol = NULL;
1080
1081 /* Look to see if it's in the register table. */
1082 if (reg_number >= 0)
1083 {
1084 expressionP->X_op = O_register;
1085 expressionP->X_add_number = reg_number;
1086
1087 return TRUE;
1088 }
1089
1090 /* Reset the line as if we had not done anything. */
1091 input_line_pointer = start;
1092
1093 expressionP->X_op = O_illegal;
1094
1095 return FALSE;
1096 }
1097
1098 /* Summary of cc_name().
1099
1100 in: INPUT_LINE_POINTER points to 1st char of operand.
1101
1102 out: An expressionS.
1103 The operand may have been a register: in this case, X_op == O_register,
1104 X_add_number is set to the register number, and truth is returned.
1105 Input_line_pointer->(next non-blank) char after operand, or is in
1106 its original state. */
1107
1108 static bfd_boolean
1109 cc_name (expressionS *expressionP,
1110 bfd_boolean accept_numbers)
1111 {
1112 int reg_number;
1113 char *name;
1114 char *start;
1115 char c;
1116
1117 /* Find the spelling of the operand. */
1118 start = name = input_line_pointer;
1119
1120 c = get_symbol_end ();
1121 reg_number = reg_name_search (cc_names, CC_NAME_CNT, name, accept_numbers);
1122
1123 /* Put back the delimiting char. */
1124 *input_line_pointer = c;
1125
1126 if (reg_number < 0
1127 && accept_numbers)
1128 {
1129 /* Reset input_line pointer. */
1130 input_line_pointer = start;
1131
1132 if (ISDIGIT (*input_line_pointer))
1133 {
1134 reg_number = strtol (input_line_pointer, &input_line_pointer, 0);
1135 }
1136 }
1137
1138 expressionP->X_add_symbol = NULL;
1139 expressionP->X_op_symbol = NULL;
1140
1141 /* Look to see if it's in the register table. */
1142 if (reg_number >= 0)
1143 {
1144 expressionP->X_op = O_constant;
1145 expressionP->X_add_number = reg_number;
1146
1147 return TRUE;
1148 }
1149
1150 /* Reset the line as if we had not done anything. */
1151 input_line_pointer = start;
1152
1153 expressionP->X_op = O_illegal;
1154 expressionP->X_add_number = 0;
1155
1156 return FALSE;
1157 }
1158
1159 static bfd_boolean
1160 float_cc_name (expressionS *expressionP,
1161 bfd_boolean accept_numbers)
1162 {
1163 int reg_number;
1164 char *name;
1165 char *start;
1166 char c;
1167
1168 /* Find the spelling of the operand. */
1169 start = name = input_line_pointer;
1170
1171 c = get_symbol_end ();
1172 reg_number = reg_name_search (float_cc_names, FLOAT_CC_NAME_CNT, name, accept_numbers);
1173
1174 /* Put back the delimiting char. */
1175 *input_line_pointer = c;
1176
1177 if (reg_number < 0
1178 && accept_numbers)
1179 {
1180 /* Reset input_line pointer. */
1181 input_line_pointer = start;
1182
1183 if (ISDIGIT (*input_line_pointer))
1184 {
1185 reg_number = strtol (input_line_pointer, &input_line_pointer, 0);
1186 }
1187 }
1188
1189 expressionP->X_add_symbol = NULL;
1190 expressionP->X_op_symbol = NULL;
1191
1192 /* Look to see if it's in the register table. */
1193 if (reg_number >= 0)
1194 {
1195 expressionP->X_op = O_constant;
1196 expressionP->X_add_number = reg_number;
1197
1198 return TRUE;
1199 }
1200
1201 /* Reset the line as if we had not done anything. */
1202 input_line_pointer = start;
1203
1204 expressionP->X_op = O_illegal;
1205 expressionP->X_add_number = 0;
1206
1207 return FALSE;
1208 }
1209
1210 static bfd_boolean
1211 cacheop_name (expressionS * expressionP,
1212 bfd_boolean accept_numbers)
1213 {
1214 int reg_number;
1215 char *name;
1216 char *start;
1217 char c;
1218
1219 /* Find the spelling of the operand. */
1220 start = name = input_line_pointer;
1221
1222 c = get_symbol_end ();
1223 reg_number = reg_name_search (cacheop_names, CACHEOP_NAME_CNT, name, accept_numbers);
1224
1225 /* Put back the delimiting char. */
1226 *input_line_pointer = c;
1227
1228 if (reg_number < 0
1229 && accept_numbers)
1230 {
1231 /* Reset input_line pointer. */
1232 input_line_pointer = start;
1233
1234 if (ISDIGIT (*input_line_pointer))
1235 reg_number = strtol (input_line_pointer, &input_line_pointer, 0);
1236 }
1237
1238 expressionP->X_add_symbol = NULL;
1239 expressionP->X_op_symbol = NULL;
1240
1241 /* Look to see if it's in the register table. */
1242 if (reg_number >= 0)
1243 {
1244 expressionP->X_op = O_constant;
1245 expressionP->X_add_number = reg_number;
1246
1247 return TRUE;
1248 }
1249
1250 /* Reset the line as if we had not done anything. */
1251 input_line_pointer = start;
1252
1253 expressionP->X_op = O_illegal;
1254 expressionP->X_add_number = 0;
1255
1256 return FALSE;
1257 }
1258
1259 static bfd_boolean
1260 prefop_name (expressionS * expressionP,
1261 bfd_boolean accept_numbers)
1262 {
1263 int reg_number;
1264 char *name;
1265 char *start;
1266 char c;
1267
1268 /* Find the spelling of the operand. */
1269 start = name = input_line_pointer;
1270
1271 c = get_symbol_end ();
1272 reg_number = reg_name_search (prefop_names, PREFOP_NAME_CNT, name, accept_numbers);
1273
1274 /* Put back the delimiting char. */
1275 *input_line_pointer = c;
1276
1277 if (reg_number < 0
1278 && accept_numbers)
1279 {
1280 /* Reset input_line pointer. */
1281 input_line_pointer = start;
1282
1283 if (ISDIGIT (*input_line_pointer))
1284 reg_number = strtol (input_line_pointer, &input_line_pointer, 0);
1285 }
1286
1287 expressionP->X_add_symbol = NULL;
1288 expressionP->X_op_symbol = NULL;
1289
1290 /* Look to see if it's in the register table. */
1291 if (reg_number >= 0)
1292 {
1293 expressionP->X_op = O_constant;
1294 expressionP->X_add_number = reg_number;
1295
1296 return TRUE;
1297 }
1298
1299 /* Reset the line as if we had not done anything. */
1300 input_line_pointer = start;
1301
1302 expressionP->X_op = O_illegal;
1303 expressionP->X_add_number = 0;
1304
1305 return FALSE;
1306 }
1307
1308 static bfd_boolean
1309 vector_register_name (expressionS *expressionP)
1310 {
1311 int reg_number;
1312 char *name;
1313 char *start;
1314 char c;
1315
1316 /* Find the spelling of the operand. */
1317 start = name = input_line_pointer;
1318
1319 c = get_symbol_end ();
1320
1321 reg_number = reg_name_search (vector_registers, VREG_NAME_CNT,
1322 name, FALSE);
1323
1324 /* Put back the delimiting char. */
1325 *input_line_pointer = c;
1326
1327 expressionP->X_add_symbol = NULL;
1328 expressionP->X_op_symbol = NULL;
1329
1330 /* Look to see if it's in the register table. */
1331 if (reg_number >= 0)
1332 {
1333 expressionP->X_op = O_register;
1334 expressionP->X_add_number = reg_number;
1335
1336 return TRUE;
1337 }
1338
1339 /* Reset the line as if we had not done anything. */
1340 input_line_pointer = start;
1341
1342 expressionP->X_op = O_illegal;
1343
1344 return FALSE;
1345 }
1346
1347 static void
1348 skip_white_space (void)
1349 {
1350 while (*input_line_pointer == ' '
1351 || *input_line_pointer == '\t')
1352 ++input_line_pointer;
1353 }
1354
1355 /* Summary of parse_register_list ().
1356
1357 in: INPUT_LINE_POINTER points to 1st char of a list of registers.
1358 INSN is the partially constructed instruction.
1359 OPERAND is the operand being inserted.
1360
1361 out: NULL if the parse completed successfully, otherwise a
1362 pointer to an error message is returned. If the parse
1363 completes the correct bit fields in the instruction
1364 will be filled in.
1365
1366 Parses register lists with the syntax:
1367
1368 { rX }
1369 { rX, rY }
1370 { rX - rY }
1371 { rX - rY, rZ }
1372 etc
1373
1374 and also parses constant expressions whoes bits indicate the
1375 registers in the lists. The LSB in the expression refers to
1376 the lowest numbered permissible register in the register list,
1377 and so on upwards. System registers are considered to be very
1378 high numbers. */
1379
1380 static char *
1381 parse_register_list (unsigned long *insn,
1382 const struct v850_operand *operand)
1383 {
1384 static int type1_regs[32] =
1385 {
1386 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1387 0, 0, 0, 0, 0, 31, 29, 28, 23, 22, 21, 20, 27, 26, 25, 24
1388 };
1389
1390 int *regs;
1391 expressionS exp;
1392
1393 /* Select a register array to parse. */
1394 switch (operand->shift)
1395 {
1396 case 0xffe00001: regs = type1_regs; break;
1397 default:
1398 as_bad (_("unknown operand shift: %x\n"), operand->shift);
1399 return _("internal failure in parse_register_list");
1400 }
1401
1402 skip_white_space ();
1403
1404 /* If the expression starts with a curly brace it is a register list.
1405 Otherwise it is a constant expression, whoes bits indicate which
1406 registers are to be included in the list. */
1407 if (*input_line_pointer != '{')
1408 {
1409 int reg;
1410 int i;
1411
1412 expression (&exp);
1413
1414 if (exp.X_op != O_constant)
1415 return _("constant expression or register list expected");
1416
1417 if (regs == type1_regs)
1418 {
1419 if (exp.X_add_number & 0xFFFFF000)
1420 return _("high bits set in register list expression");
1421
1422 for (reg = 20; reg < 32; reg++)
1423 if (exp.X_add_number & (1 << (reg - 20)))
1424 {
1425 for (i = 0; i < 32; i++)
1426 if (regs[i] == reg)
1427 *insn |= (1 << i);
1428 }
1429 }
1430
1431 return NULL;
1432 }
1433
1434 input_line_pointer++;
1435
1436 /* Parse the register list until a terminator (closing curly brace or
1437 new-line) is found. */
1438 for (;;)
1439 {
1440 skip_white_space ();
1441
1442 if (register_name (&exp))
1443 {
1444 int i;
1445
1446 /* Locate the given register in the list, and if it is there,
1447 insert the corresponding bit into the instruction. */
1448 for (i = 0; i < 32; i++)
1449 {
1450 if (regs[i] == exp.X_add_number)
1451 {
1452 *insn |= (1 << i);
1453 break;
1454 }
1455 }
1456
1457 if (i == 32)
1458 return _("illegal register included in list");
1459 }
1460 else if (system_register_name (&exp, TRUE))
1461 {
1462 if (regs == type1_regs)
1463 {
1464 return _("system registers cannot be included in list");
1465 }
1466 }
1467
1468 if (*input_line_pointer == '}')
1469 {
1470 input_line_pointer++;
1471 break;
1472 }
1473 else if (*input_line_pointer == ',')
1474 {
1475 input_line_pointer++;
1476 continue;
1477 }
1478 else if (*input_line_pointer == '-')
1479 {
1480 /* We have encountered a range of registers: rX - rY. */
1481 int j;
1482 expressionS exp2;
1483
1484 /* Skip the dash. */
1485 ++input_line_pointer;
1486
1487 /* Get the second register in the range. */
1488 if (! register_name (&exp2))
1489 {
1490 return _("second register should follow dash in register list");
1491 }
1492
1493 if (exp.X_add_number > exp2.X_add_number)
1494 {
1495 return _("second register should be greater than first register");
1496 }
1497
1498 /* Add the rest of the registers in the range. */
1499 for (j = exp.X_add_number + 1; j <= exp2.X_add_number; j++)
1500 {
1501 int i;
1502
1503 /* Locate the given register in the list, and if it is there,
1504 insert the corresponding bit into the instruction. */
1505 for (i = 0; i < 32; i++)
1506 {
1507 if (regs[i] == j)
1508 {
1509 *insn |= (1 << i);
1510 break;
1511 }
1512 }
1513
1514 if (i == 32)
1515 return _("illegal register included in list");
1516 }
1517
1518 exp = exp2;
1519 }
1520 else
1521 break;
1522 }
1523
1524 return NULL;
1525 }
1526
1527 const char *md_shortopts = "m:";
1528
1529 struct option md_longopts[] =
1530 {
1531 #define OPTION_DISP_SIZE_DEFAULT_22 (OPTION_MD_BASE)
1532 {"disp-size-default-22", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_22},
1533 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 1)
1534 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
1535 {NULL, no_argument, NULL, 0}
1536 };
1537
1538 size_t md_longopts_size = sizeof (md_longopts);
1539
1540 void
1541 md_show_usage (FILE *stream)
1542 {
1543 fprintf (stream, _(" V850 options:\n"));
1544 fprintf (stream, _(" -mwarn-signed-overflow Warn if signed immediate values overflow\n"));
1545 fprintf (stream, _(" -mwarn-unsigned-overflow Warn if unsigned immediate values overflow\n"));
1546 fprintf (stream, _(" -mv850 The code is targeted at the v850\n"));
1547 fprintf (stream, _(" -mv850e The code is targeted at the v850e\n"));
1548 fprintf (stream, _(" -mv850e1 The code is targeted at the v850e1\n"));
1549 fprintf (stream, _(" -mv850e2 The code is targeted at the v850e2\n"));
1550 fprintf (stream, _(" -mv850e2v3 The code is targeted at the v850e2v3\n"));
1551 fprintf (stream, _(" -mv850e2v4 Alias for -mv850e3v5\n"));
1552 fprintf (stream, _(" -mv850e3v5 The code is targeted at the v850e3v5\n"));
1553 fprintf (stream, _(" -mrelax Enable relaxation\n"));
1554 fprintf (stream, _(" --disp-size-default-22 branch displacement with unknown size is 22 bits (default)\n"));
1555 fprintf (stream, _(" --disp-size-default-32 branch displacement with unknown size is 32 bits\n"));
1556 fprintf (stream, _(" -mextension enable extension opcode support\n"));
1557 fprintf (stream, _(" -mno-bcond17 disable b<cond> disp17 instruction\n"));
1558 fprintf (stream, _(" -mno-stld23 disable st/ld offset23 instruction\n"));
1559 fprintf (stream, _(" -mgcc-abi Mark the binary as using the old GCC ABI\n"));
1560 fprintf (stream, _(" -mrh850-abi Mark the binary as using the RH850 ABI (default)\n"));
1561 fprintf (stream, _(" -m8byte-align Mark the binary as using 64-bit alignment\n"));
1562 fprintf (stream, _(" -m4byte-align Mark the binary as using 32-bit alignment (default)\n"));
1563 }
1564
1565 int
1566 md_parse_option (int c, char *arg)
1567 {
1568 if (c != 'm')
1569 {
1570 switch (c)
1571 {
1572 case OPTION_DISP_SIZE_DEFAULT_22:
1573 default_disp_size = 22;
1574 return 1;
1575
1576 case OPTION_DISP_SIZE_DEFAULT_32:
1577 default_disp_size = 32;
1578 return 1;
1579 }
1580 return 0;
1581 }
1582
1583 if (strcmp (arg, "warn-signed-overflow") == 0)
1584 warn_signed_overflows = TRUE;
1585
1586 else if (strcmp (arg, "warn-unsigned-overflow") == 0)
1587 warn_unsigned_overflows = TRUE;
1588
1589 else if (strcmp (arg, "v850") == 0)
1590 {
1591 machine = 0;
1592 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850);
1593 }
1594 else if (strcmp (arg, "v850e") == 0)
1595 {
1596 machine = bfd_mach_v850e;
1597 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E);
1598 }
1599 else if (strcmp (arg, "v850e1") == 0)
1600 {
1601 machine = bfd_mach_v850e1;
1602 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E1);
1603 }
1604 else if (strcmp (arg, "v850e2") == 0)
1605 {
1606 machine = bfd_mach_v850e2;
1607 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2);
1608 }
1609 else if (strcmp (arg, "v850e2v3") == 0)
1610 {
1611 machine = bfd_mach_v850e2v3;
1612 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2V3);
1613 }
1614 else if (strcmp (arg, "v850e2v4") == 0)
1615 {
1616 machine = bfd_mach_v850e3v5;
1617 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5);
1618 }
1619 else if (strcmp (arg, "v850e3v5") == 0)
1620 {
1621 machine = bfd_mach_v850e3v5;
1622 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5);
1623 }
1624 else if (strcmp (arg, "extension") == 0)
1625 {
1626 processor_mask |= PROCESSOR_OPTION_EXTENSION | PROCESSOR_OPTION_ALIAS;
1627 }
1628 else if (strcmp (arg, "no-bcond17") == 0)
1629 {
1630 no_bcond17 = 1;
1631 }
1632 else if (strcmp (arg, "no-stld23") == 0)
1633 {
1634 no_stld23 = 1;
1635 }
1636 else if (strcmp (arg, "relax") == 0)
1637 v850_relax = 1;
1638 else if (strcmp (arg, "gcc-abi") == 0)
1639 {
1640 v850_target_arch = bfd_arch_v850;
1641 v850_target_format = "elf32-v850";
1642 }
1643 else if (strcmp (arg, "rh850-abi") == 0)
1644 {
1645 v850_target_arch = bfd_arch_v850_rh850;
1646 v850_target_format = "elf32-v850-rh850";
1647 }
1648 else if (strcmp (arg, "8byte-align") == 0)
1649 v850_e_flags |= EF_RH850_DATA_ALIGN8;
1650 else if (strcmp (arg, "4byte-align") == 0)
1651 v850_e_flags &= ~ EF_RH850_DATA_ALIGN8;
1652 else
1653 return 0;
1654
1655 return 1;
1656 }
1657
1658 symbolS *
1659 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
1660 {
1661 return 0;
1662 }
1663
1664 char *
1665 md_atof (int type, char *litp, int *sizep)
1666 {
1667 return ieee_md_atof (type, litp, sizep, FALSE);
1668 }
1669
1670 /* Very gross. */
1671
1672 void
1673 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
1674 asection *sec,
1675 fragS *fragP)
1676 {
1677 union u
1678 {
1679 bfd_reloc_code_real_type fx_r_type;
1680 char * fr_opcode;
1681 }
1682 opcode_converter;
1683 subseg_change (sec, 0);
1684
1685 opcode_converter.fr_opcode = fragP->fr_opcode;
1686
1687 subseg_change (sec, 0);
1688
1689 if (fragP->fr_subtype == SUBYPTE_LOOP_16_22)
1690 {
1691 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
1692 fragP->fr_offset, 1,
1693 BFD_RELOC_UNUSED + opcode_converter.fx_r_type);
1694 fragP->fr_fix += 4;
1695 }
1696 else if (fragP->fr_subtype == SUBYPTE_LOOP_16_22 + 1)
1697 {
1698 unsigned char * buffer =
1699 (unsigned char *) (fragP->fr_fix + fragP->fr_literal);
1700 int loop_reg = (buffer[0] & 0x1f);
1701
1702 /* Add -1.reg. */
1703 md_number_to_chars ((char *) buffer, 0x025f | (loop_reg << 11), 2);
1704 /* Now create the conditional branch + fixup to the final target. */
1705 /* 0x000107ea = bne LBL(disp17). */
1706 md_number_to_chars ((char *) buffer + 2, 0x000107ea, 4);
1707 fix_new (fragP, fragP->fr_fix+2, 4, fragP->fr_symbol,
1708 fragP->fr_offset, 1,
1709 BFD_RELOC_V850_17_PCREL);
1710 fragP->fr_fix += 6;
1711 }
1712 /* In range conditional or unconditional branch. */
1713 else if (fragP->fr_subtype == SUBYPTE_COND_9_22
1714 || fragP->fr_subtype == SUBYPTE_UNCOND_9_22
1715 || fragP->fr_subtype == SUBYPTE_COND_9_22_32
1716 || fragP->fr_subtype == SUBYPTE_UNCOND_9_22_32
1717 || fragP->fr_subtype == SUBYPTE_COND_9_17_22
1718 || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32
1719 || fragP->fr_subtype == SUBYPTE_SA_9_22
1720 || fragP->fr_subtype == SUBYPTE_SA_9_22_32
1721 || fragP->fr_subtype == SUBYPTE_SA_9_17_22
1722 || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32)
1723
1724 {
1725 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
1726 fragP->fr_offset, 1,
1727 BFD_RELOC_UNUSED + opcode_converter.fx_r_type);
1728 fragP->fr_fix += 2;
1729 }
1730 /* V850e2r-v3 17bit conditional branch. */
1731 else if (fragP->fr_subtype == SUBYPTE_COND_9_17_22 + 1
1732 || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32 + 1
1733 || fragP->fr_subtype == SUBYPTE_SA_9_17_22 + 1
1734 || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32 + 1)
1735 {
1736 unsigned char *buffer =
1737 (unsigned char *) (fragP->fr_fix + fragP->fr_literal);
1738
1739 buffer[0] &= 0x0f; /* Use condition. */
1740 buffer[0] |= 0xe0;
1741 buffer[1] = 0x07;
1742
1743 /* Now create the unconditional branch + fixup to the final
1744 target. */
1745 md_number_to_chars ((char *) buffer + 2, 0x0001, 2);
1746 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
1747 fragP->fr_offset, 1, BFD_RELOC_V850_17_PCREL);
1748 fragP->fr_fix += 4;
1749 }
1750 /* Out of range conditional branch. Emit a branch around a 22bit jump. */
1751 else if (fragP->fr_subtype == SUBYPTE_COND_9_22 + 1
1752 || fragP->fr_subtype == SUBYPTE_COND_9_22_32 + 1
1753 || fragP->fr_subtype == SUBYPTE_COND_9_17_22 + 2
1754 || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32 + 2)
1755 {
1756 unsigned char *buffer =
1757 (unsigned char *) (fragP->fr_fix + fragP->fr_literal);
1758
1759 /* Reverse the condition of the first branch. */
1760 buffer[0] ^= 0x08;
1761 /* Mask off all the displacement bits. */
1762 buffer[0] &= 0x8f;
1763 buffer[1] &= 0x07;
1764 /* Now set the displacement bits so that we branch
1765 around the unconditional branch. */
1766 buffer[0] |= 0x30;
1767
1768 /* Now create the unconditional branch + fixup to the final
1769 target. */
1770 md_number_to_chars ((char *) buffer + 2, 0x00000780, 4);
1771 fix_new (fragP, fragP->fr_fix + 2, 4, fragP->fr_symbol,
1772 fragP->fr_offset, 1, BFD_RELOC_V850_22_PCREL);
1773 fragP->fr_fix += 6;
1774 }
1775 /* Out of range conditional branch. Emit a branch around a 32bit jump. */
1776 else if (fragP->fr_subtype == SUBYPTE_COND_9_22_32 + 2
1777 || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32 + 3)
1778 {
1779 unsigned char *buffer =
1780 (unsigned char *) (fragP->fr_fix + fragP->fr_literal);
1781
1782 /* Reverse the condition of the first branch. */
1783 buffer[0] ^= 0x08;
1784 /* Mask off all the displacement bits. */
1785 buffer[0] &= 0x8f;
1786 buffer[1] &= 0x07;
1787 /* Now set the displacement bits so that we branch
1788 around the unconditional branch. */
1789 buffer[0] |= 0x40;
1790
1791 /* Now create the unconditional branch + fixup to the final
1792 target. */
1793 md_number_to_chars ((char *) buffer + 2, 0x02e0, 2);
1794 fix_new (fragP, fragP->fr_fix + 4, 4, fragP->fr_symbol,
1795 fragP->fr_offset + 2, 1, BFD_RELOC_V850_32_PCREL);
1796 fragP->fr_fix += 8;
1797 }
1798 /* Out of range unconditional branch. Emit a 22bit jump. */
1799 else if (fragP->fr_subtype == SUBYPTE_UNCOND_9_22 + 1
1800 || fragP->fr_subtype == SUBYPTE_UNCOND_9_22_32 + 1)
1801 {
1802 md_number_to_chars (fragP->fr_fix + fragP->fr_literal, 0x00000780, 4);
1803 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
1804 fragP->fr_offset, 1, BFD_RELOC_V850_22_PCREL);
1805 fragP->fr_fix += 4;
1806 }
1807 /* Out of range unconditional branch. Emit a 32bit jump. */
1808 else if (fragP->fr_subtype == SUBYPTE_UNCOND_9_22_32 + 2)
1809 {
1810 md_number_to_chars (fragP->fr_fix + fragP->fr_literal, 0x02e0, 2);
1811 fix_new (fragP, fragP->fr_fix + 4, 4, fragP->fr_symbol,
1812 fragP->fr_offset + 2, 1, BFD_RELOC_V850_32_PCREL);
1813 fragP->fr_fix += 6;
1814 }
1815 /* Out of range SA conditional branch. Emit a branch to a 22bit jump. */
1816 else if (fragP->fr_subtype == SUBYPTE_SA_9_22 + 1
1817 || fragP->fr_subtype == SUBYPTE_SA_9_22_32 + 1
1818 || fragP->fr_subtype == SUBYPTE_SA_9_17_22 + 2
1819 || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32 + 2)
1820 {
1821 unsigned char *buffer =
1822 (unsigned char *) (fragP->fr_fix + fragP->fr_literal);
1823
1824 /* bsa .+4 */
1825 buffer[0] &= 0x8f;
1826 buffer[0] |= 0x20;
1827 buffer[1] &= 0x07;
1828
1829 /* br .+6 */
1830 md_number_to_chars ((char *) buffer + 2, 0x05b5, 2);
1831
1832 /* Now create the unconditional branch + fixup to the final
1833 target. */
1834 /* jr SYM */
1835 md_number_to_chars ((char *) buffer + 4, 0x00000780, 4);
1836 fix_new (fragP, fragP->fr_fix + 4, 4, fragP->fr_symbol,
1837 fragP->fr_offset, 1,
1838 BFD_RELOC_V850_22_PCREL);
1839 fragP->fr_fix += 8;
1840 }
1841 /* Out of range SA conditional branch. Emit a branch around a 32bit jump. */
1842 else if (fragP->fr_subtype == SUBYPTE_SA_9_22_32 + 2
1843 || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32 + 3)
1844 {
1845 unsigned char *buffer =
1846 (unsigned char *) (fragP->fr_fix + fragP->fr_literal);
1847
1848 /* bsa .+2 */
1849 buffer[0] &= 0x8f;
1850 buffer[0] |= 0x20;
1851 buffer[1] &= 0x07;
1852
1853 /* br .+8 */
1854 md_number_to_chars ((char *) buffer + 2, 0x05c5, 2);
1855
1856 /* Now create the unconditional branch + fixup to the final
1857 target. */
1858 /* jr SYM */
1859 md_number_to_chars ((char *) buffer + 4, 0x02e0, 2);
1860 fix_new (fragP, fragP->fr_fix + 6, 4, fragP->fr_symbol,
1861 fragP->fr_offset + 2, 1, BFD_RELOC_V850_32_PCREL);
1862
1863 fragP->fr_fix += 10;
1864 }
1865 else
1866 abort ();
1867 }
1868
1869 valueT
1870 md_section_align (asection *seg, valueT addr)
1871 {
1872 int align = bfd_get_section_alignment (stdoutput, seg);
1873 return ((addr + (1 << align) - 1) & (-1 << align));
1874 }
1875
1876 void
1877 md_begin (void)
1878 {
1879 char *prev_name = "";
1880 const struct v850_opcode *op;
1881
1882 if (strncmp (TARGET_CPU, "v850e3v5", 8) == 0)
1883 {
1884 if (machine == -1)
1885 machine = bfd_mach_v850e3v5;
1886
1887 if (!processor_mask)
1888 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5);
1889 }
1890 else if (strncmp (TARGET_CPU, "v850e2v4", 8) == 0)
1891 {
1892 if (machine == -1)
1893 machine = bfd_mach_v850e3v5;
1894
1895 if (!processor_mask)
1896 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5);
1897 }
1898 else if (strncmp (TARGET_CPU, "v850e2v3", 8) == 0)
1899 {
1900 if (machine == -1)
1901 machine = bfd_mach_v850e2v3;
1902
1903 if (!processor_mask)
1904 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2V3);
1905 }
1906 else if (strncmp (TARGET_CPU, "v850e2", 6) == 0)
1907 {
1908 if (machine == -1)
1909 machine = bfd_mach_v850e2;
1910
1911 if (!processor_mask)
1912 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2);
1913 }
1914 else if (strncmp (TARGET_CPU, "v850e1", 6) == 0)
1915 {
1916 if (machine == -1)
1917 machine = bfd_mach_v850e1;
1918
1919 if (!processor_mask)
1920 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E1);
1921 }
1922 else if (strncmp (TARGET_CPU, "v850e", 5) == 0)
1923 {
1924 if (machine == -1)
1925 machine = bfd_mach_v850e;
1926
1927 if (!processor_mask)
1928 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E);
1929 }
1930 else if (strncmp (TARGET_CPU, "v850", 4) == 0)
1931 {
1932 if (machine == -1)
1933 machine = 0;
1934
1935 if (!processor_mask)
1936 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850);
1937 }
1938 else
1939 /* xgettext:c-format */
1940 as_bad (_("Unable to determine default target processor from string: %s"),
1941 TARGET_CPU);
1942
1943 v850_hash = hash_new ();
1944
1945 /* Insert unique names into hash table. The V850 instruction set
1946 has many identical opcode names that have different opcodes based
1947 on the operands. This hash table then provides a quick index to
1948 the first opcode with a particular name in the opcode table. */
1949 op = v850_opcodes;
1950 while (op->name)
1951 {
1952 if (strcmp (prev_name, op->name))
1953 {
1954 prev_name = (char *) op->name;
1955 hash_insert (v850_hash, op->name, (char *) op);
1956 }
1957 op++;
1958 }
1959
1960 v850_seg_table[BSS_SECTION].s = bss_section;
1961 bfd_set_arch_mach (stdoutput, v850_target_arch, machine);
1962 bfd_set_private_flags (stdoutput, v850_e_flags);
1963 }
1964
1965
1966 static bfd_reloc_code_real_type
1967 handle_hi016 (const struct v850_operand *operand, const char **errmsg)
1968 {
1969 if (operand == NULL)
1970 return BFD_RELOC_HI16;
1971
1972 if (operand->default_reloc == BFD_RELOC_HI16)
1973 return BFD_RELOC_HI16;
1974
1975 if (operand->default_reloc == BFD_RELOC_HI16_S)
1976 return BFD_RELOC_HI16;
1977
1978 if (operand->default_reloc == BFD_RELOC_16)
1979 return BFD_RELOC_HI16;
1980
1981 *errmsg = _("hi0() relocation used on an instruction which does "
1982 "not support it");
1983 return BFD_RELOC_64; /* Used to indicate an error condition. */
1984 }
1985
1986 static bfd_reloc_code_real_type
1987 handle_hi16 (const struct v850_operand *operand, const char **errmsg)
1988 {
1989 if (operand == NULL)
1990 return BFD_RELOC_HI16_S;
1991
1992 if (operand->default_reloc == BFD_RELOC_HI16_S)
1993 return BFD_RELOC_HI16_S;
1994
1995 if (operand->default_reloc == BFD_RELOC_HI16)
1996 return BFD_RELOC_HI16_S;
1997
1998 if (operand->default_reloc == BFD_RELOC_16)
1999 return BFD_RELOC_HI16_S;
2000
2001 *errmsg = _("hi() relocation used on an instruction which does "
2002 "not support it");
2003 return BFD_RELOC_64; /* Used to indicate an error condition. */
2004 }
2005
2006 static bfd_reloc_code_real_type
2007 handle_lo16 (const struct v850_operand *operand, const char **errmsg)
2008 {
2009 if (operand == NULL)
2010 return BFD_RELOC_LO16;
2011
2012 if (operand->default_reloc == BFD_RELOC_LO16)
2013 return BFD_RELOC_LO16;
2014
2015 if (operand->default_reloc == BFD_RELOC_V850_16_SPLIT_OFFSET)
2016 return BFD_RELOC_V850_LO16_SPLIT_OFFSET;
2017
2018 if (operand->default_reloc == BFD_RELOC_V850_16_S1)
2019 return BFD_RELOC_V850_LO16_S1;
2020
2021 if (operand->default_reloc == BFD_RELOC_16)
2022 return BFD_RELOC_LO16;
2023
2024 *errmsg = _("lo() relocation used on an instruction which does "
2025 "not support it");
2026 return BFD_RELOC_64; /* Used to indicate an error condition. */
2027 }
2028
2029 static bfd_reloc_code_real_type
2030 handle_ctoff (const struct v850_operand *operand, const char **errmsg)
2031 {
2032 if (operand == NULL)
2033 return BFD_RELOC_V850_CALLT_16_16_OFFSET;
2034
2035 if (operand->default_reloc == BFD_RELOC_V850_CALLT_6_7_OFFSET)
2036 return operand->default_reloc;
2037
2038 if (operand->default_reloc == BFD_RELOC_V850_16_S1)
2039 return BFD_RELOC_V850_CALLT_15_16_OFFSET;
2040
2041 if (operand->default_reloc == BFD_RELOC_16)
2042 return BFD_RELOC_V850_CALLT_16_16_OFFSET;
2043
2044 *errmsg = _("ctoff() relocation used on an instruction which does not support it");
2045 return BFD_RELOC_64; /* Used to indicate an error condition. */
2046 }
2047
2048 static bfd_reloc_code_real_type
2049 handle_sdaoff (const struct v850_operand *operand, const char **errmsg)
2050 {
2051 if (operand == NULL)
2052 return BFD_RELOC_V850_SDA_16_16_OFFSET;
2053
2054 if (operand->default_reloc == BFD_RELOC_V850_16_SPLIT_OFFSET)
2055 return BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET;
2056
2057 if (operand->default_reloc == BFD_RELOC_16)
2058 return BFD_RELOC_V850_SDA_16_16_OFFSET;
2059
2060 if (operand->default_reloc == BFD_RELOC_V850_16_S1)
2061 return BFD_RELOC_V850_SDA_15_16_OFFSET;
2062
2063 *errmsg = _("sdaoff() relocation used on an instruction which does not support it");
2064 return BFD_RELOC_64; /* Used to indicate an error condition. */
2065 }
2066
2067 static bfd_reloc_code_real_type
2068 handle_zdaoff (const struct v850_operand *operand, const char **errmsg)
2069 {
2070 if (operand == NULL)
2071 return BFD_RELOC_V850_ZDA_16_16_OFFSET;
2072
2073 if (operand->default_reloc == BFD_RELOC_V850_16_SPLIT_OFFSET)
2074 return BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET;
2075
2076 if (operand->default_reloc == BFD_RELOC_16)
2077 return BFD_RELOC_V850_ZDA_16_16_OFFSET;
2078
2079 if (operand->default_reloc == BFD_RELOC_V850_16_S1)
2080 return BFD_RELOC_V850_ZDA_15_16_OFFSET;
2081
2082 *errmsg = _("zdaoff() relocation used on an instruction which does not support it");
2083 return BFD_RELOC_64; /* Used to indicate an error condition. */
2084 }
2085
2086 static bfd_reloc_code_real_type
2087 handle_tdaoff (const struct v850_operand *operand, const char **errmsg)
2088 {
2089 if (operand == NULL)
2090 /* Data item, not an instruction. */
2091 return BFD_RELOC_V850_TDA_16_16_OFFSET;
2092
2093 switch (operand->default_reloc)
2094 {
2095 /* sld.hu, operand: D5-4. */
2096 case BFD_RELOC_V850_TDA_4_5_OFFSET:
2097 /* sld.bu, operand: D4. */
2098 case BFD_RELOC_V850_TDA_4_4_OFFSET:
2099 /* sld.w/sst.w, operand: D8_6. */
2100 case BFD_RELOC_V850_TDA_6_8_OFFSET:
2101 /* sld.h/sst.h, operand: D8_7. */
2102 case BFD_RELOC_V850_TDA_7_8_OFFSET:
2103 /* sld.b/sst.b, operand: D7. */
2104 case BFD_RELOC_V850_TDA_7_7_OFFSET:
2105 return operand->default_reloc;
2106 default:
2107 break;
2108 }
2109
2110 if (operand->default_reloc == BFD_RELOC_16 && operand->shift == 16)
2111 /* set1 & chums, operands: D16. */
2112 return BFD_RELOC_V850_TDA_16_16_OFFSET;
2113
2114 *errmsg = _("tdaoff() relocation used on an instruction which does not support it");
2115 /* Used to indicate an error condition. */
2116 return BFD_RELOC_64;
2117 }
2118
2119 /* Warning: The code in this function relies upon the definitions
2120 in the v850_operands[] array (defined in opcodes/v850-opc.c)
2121 matching the hard coded values contained herein. */
2122
2123 static bfd_reloc_code_real_type
2124 v850_reloc_prefix (const struct v850_operand *operand, const char **errmsg)
2125 {
2126 bfd_boolean paren_skipped = FALSE;
2127
2128 /* Skip leading opening parenthesis. */
2129 if (*input_line_pointer == '(')
2130 {
2131 ++input_line_pointer;
2132 paren_skipped = TRUE;
2133 }
2134
2135 #define CHECK_(name, reloc) \
2136 if (strncmp (input_line_pointer, name "(", strlen (name) + 1) == 0) \
2137 { \
2138 input_line_pointer += strlen (name); \
2139 return reloc; \
2140 }
2141
2142 CHECK_ ("hi0", handle_hi016(operand, errmsg) );
2143 CHECK_ ("hi", handle_hi16(operand, errmsg) );
2144 CHECK_ ("lo", handle_lo16 (operand, errmsg) );
2145 CHECK_ ("sdaoff", handle_sdaoff (operand, errmsg));
2146 CHECK_ ("zdaoff", handle_zdaoff (operand, errmsg));
2147 CHECK_ ("tdaoff", handle_tdaoff (operand, errmsg));
2148 CHECK_ ("hilo", BFD_RELOC_32);
2149 CHECK_ ("lo23", BFD_RELOC_V850_23);
2150 CHECK_ ("ctoff", handle_ctoff (operand, errmsg) );
2151
2152 /* Restore skipped parenthesis. */
2153 if (paren_skipped)
2154 --input_line_pointer;
2155
2156 return BFD_RELOC_NONE;
2157 }
2158
2159 /* Insert an operand value into an instruction. */
2160
2161 static unsigned long
2162 v850_insert_operand (unsigned long insn,
2163 const struct v850_operand *operand,
2164 offsetT val,
2165 const char **errmsg)
2166 {
2167 if (operand->insert)
2168 {
2169 const char *message = NULL;
2170
2171 insn = operand->insert (insn, val, &message);
2172 if (message != NULL)
2173 {
2174 if ((operand->flags & V850_OPERAND_SIGNED)
2175 && ! warn_signed_overflows
2176 && v850_msg_is_out_of_range (message))
2177 {
2178 /* Skip warning... */
2179 }
2180 else if ((operand->flags & V850_OPERAND_SIGNED) == 0
2181 && ! warn_unsigned_overflows
2182 && v850_msg_is_out_of_range (message))
2183 {
2184 /* Skip warning... */
2185 }
2186 else
2187 {
2188 if (errmsg != NULL)
2189 *errmsg = message;
2190 }
2191 }
2192 }
2193 else if (operand->bits == -1
2194 || operand->flags & V850E_IMMEDIATE16
2195 || operand->flags & V850E_IMMEDIATE23
2196 || operand->flags & V850E_IMMEDIATE32)
2197 {
2198 abort ();
2199 }
2200 else
2201 {
2202 if (operand->bits < 32)
2203 {
2204 long min, max;
2205
2206 if ((operand->flags & V850_OPERAND_SIGNED) != 0)
2207 {
2208 if (! warn_signed_overflows)
2209 max = (1 << operand->bits) - 1;
2210 else
2211 max = (1 << (operand->bits - 1)) - 1;
2212
2213 min = -(1 << (operand->bits - 1));
2214 }
2215 else
2216 {
2217 max = (1 << operand->bits) - 1;
2218
2219 if (! warn_unsigned_overflows)
2220 min = -(1 << (operand->bits - 1));
2221 else
2222 min = 0;
2223 }
2224
2225 /* Some people write constants with the sign extension done by
2226 hand but only up to 32 bits. This shouldn't really be valid,
2227 but, to permit this code to assemble on a 64-bit host, we
2228 sign extend the 32-bit value to 64 bits if so doing makes the
2229 value valid. */
2230 if (val > max
2231 && (offsetT) (val - 0x80000000 - 0x80000000) >= min
2232 && (offsetT) (val - 0x80000000 - 0x80000000) <= max)
2233 val = val - 0x80000000 - 0x80000000;
2234
2235 /* Similarly, people write expressions like ~(1<<15), and expect
2236 this to be OK for a 32-bit unsigned value. */
2237 else if (val < min
2238 && (offsetT) (val + 0x80000000 + 0x80000000) >= min
2239 && (offsetT) (val + 0x80000000 + 0x80000000) <= max)
2240 val = val + 0x80000000 + 0x80000000;
2241
2242 else if (val < (offsetT) min || val > (offsetT) max)
2243 {
2244 static char buf [128];
2245
2246 /* Restore min and mix to expected values for decimal ranges. */
2247 if ((operand->flags & V850_OPERAND_SIGNED)
2248 && ! warn_signed_overflows)
2249 max = (1 << (operand->bits - 1)) - 1;
2250
2251 if (! (operand->flags & V850_OPERAND_SIGNED)
2252 && ! warn_unsigned_overflows)
2253 min = 0;
2254
2255 sprintf (buf, _("operand out of range (%d is not between %d and %d)"),
2256 (int) val, (int) min, (int) max);
2257 *errmsg = buf;
2258 }
2259
2260 insn |= (((long) val & ((1 << operand->bits) - 1)) << operand->shift);
2261 }
2262 else
2263 {
2264 insn |= (((long) val) << operand->shift);
2265 }
2266 }
2267
2268 return insn;
2269 }
2270 \f
2271 static char copy_of_instruction[128];
2272
2273 void
2274 md_assemble (char *str)
2275 {
2276 char *s;
2277 char *start_of_operands;
2278 struct v850_opcode *opcode;
2279 struct v850_opcode *next_opcode;
2280 const unsigned char *opindex_ptr;
2281 int next_opindex;
2282 int relaxable = 0;
2283 unsigned long insn;
2284 unsigned long insn_size;
2285 char *f = NULL;
2286 int i;
2287 int match;
2288 bfd_boolean extra_data_after_insn = FALSE;
2289 unsigned extra_data_len = 0;
2290 unsigned long extra_data = 0;
2291 char *saved_input_line_pointer;
2292 char most_match_errmsg[1024];
2293 int most_match_count = -1;
2294
2295 strncpy (copy_of_instruction, str, sizeof (copy_of_instruction) - 1);
2296 most_match_errmsg[0] = 0;
2297
2298 /* Get the opcode. */
2299 for (s = str; *s != '\0' && ! ISSPACE (*s); s++)
2300 continue;
2301
2302 if (*s != '\0')
2303 *s++ = '\0';
2304
2305 /* Find the first opcode with the proper name. */
2306 opcode = (struct v850_opcode *) hash_find (v850_hash, str);
2307 if (opcode == NULL)
2308 {
2309 /* xgettext:c-format */
2310 as_bad (_("Unrecognized opcode: `%s'"), str);
2311 ignore_rest_of_line ();
2312 return;
2313 }
2314
2315 str = s;
2316 while (ISSPACE (*str))
2317 ++str;
2318
2319 start_of_operands = str;
2320
2321 saved_input_line_pointer = input_line_pointer;
2322
2323 for (;;)
2324 {
2325 const char *errmsg = NULL;
2326 const char *warningmsg = NULL;
2327
2328 match = 0;
2329 opindex_ptr = opcode->operands;
2330
2331 if (no_stld23)
2332 {
2333 if ((strncmp (opcode->name, "st.", 3) == 0
2334 && v850_operands[opcode->operands[1]].bits == 23)
2335 || (strncmp (opcode->name, "ld.", 3) == 0
2336 && v850_operands[opcode->operands[0]].bits == 23))
2337 {
2338 errmsg = _("st/ld offset 23 instruction was disabled .");
2339 goto error;
2340 }
2341 }
2342
2343 if ((opcode->processors & processor_mask & PROCESSOR_MASK) == 0
2344 || (((opcode->processors & ~PROCESSOR_MASK) != 0)
2345 && ((opcode->processors & processor_mask & ~PROCESSOR_MASK) == 0)))
2346 {
2347 errmsg = _("Target processor does not support this instruction.");
2348 goto error;
2349 }
2350
2351 relaxable = 0;
2352 fc = 0;
2353 next_opindex = 0;
2354 insn = opcode->opcode;
2355 extra_data_len = 0;
2356 extra_data_after_insn = FALSE;
2357
2358 input_line_pointer = str = start_of_operands;
2359
2360 for (opindex_ptr = opcode->operands; *opindex_ptr != 0; opindex_ptr++)
2361 {
2362 const struct v850_operand *operand;
2363 char *hold;
2364 expressionS ex;
2365 bfd_reloc_code_real_type reloc;
2366
2367 if (next_opindex == 0)
2368 operand = &v850_operands[*opindex_ptr];
2369 else
2370 {
2371 operand = &v850_operands[next_opindex];
2372 next_opindex = 0;
2373 }
2374
2375 errmsg = NULL;
2376
2377 while (*str == ' ')
2378 ++str;
2379
2380 if (operand->flags & V850_OPERAND_BANG
2381 && *str == '!')
2382 ++str;
2383 else if (operand->flags & V850_OPERAND_PERCENT
2384 && *str == '%')
2385 ++str;
2386
2387 if (*str == ',' || *str == '[' || *str == ']')
2388 ++str;
2389
2390 while (*str == ' ')
2391 ++str;
2392
2393 if ( (strcmp (opcode->name, "pushsp") == 0
2394 || strcmp (opcode->name, "popsp") == 0
2395 || strcmp (opcode->name, "dbpush") == 0)
2396 && (*str == '-'))
2397 ++str;
2398
2399 if (operand->flags & V850_OPERAND_RELAX)
2400 relaxable = 1;
2401
2402 /* Gather the operand. */
2403 hold = input_line_pointer;
2404 input_line_pointer = str;
2405
2406 /* lo(), hi(), hi0(), etc... */
2407 if ((reloc = v850_reloc_prefix (operand, &errmsg)) != BFD_RELOC_NONE)
2408 {
2409 /* This is a fake reloc, used to indicate an error condition. */
2410 if (reloc == BFD_RELOC_64)
2411 {
2412 /* match = 1; */
2413 goto error;
2414 }
2415
2416 expression (&ex);
2417
2418 if (ex.X_op == O_constant)
2419 {
2420 switch (reloc)
2421 {
2422 case BFD_RELOC_V850_ZDA_16_16_OFFSET:
2423 case BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET:
2424 case BFD_RELOC_V850_ZDA_15_16_OFFSET:
2425 /* To cope with "not1 7, zdaoff(0xfffff006)[r0]"
2426 and the like. */
2427 /* Fall through. */
2428
2429 case BFD_RELOC_LO16:
2430 case BFD_RELOC_V850_LO16_S1:
2431 case BFD_RELOC_V850_LO16_SPLIT_OFFSET:
2432 {
2433 /* Truncate, then sign extend the value. */
2434 ex.X_add_number = SEXT16 (ex.X_add_number);
2435 break;
2436 }
2437
2438 case BFD_RELOC_HI16:
2439 {
2440 /* Truncate, then sign extend the value. */
2441 ex.X_add_number = SEXT16 (ex.X_add_number >> 16);
2442 break;
2443 }
2444
2445 case BFD_RELOC_HI16_S:
2446 {
2447 /* Truncate, then sign extend the value. */
2448 int temp = (ex.X_add_number >> 16) & 0xffff;
2449
2450 temp += (ex.X_add_number >> 15) & 1;
2451
2452 ex.X_add_number = SEXT16 (temp);
2453 break;
2454 }
2455
2456 case BFD_RELOC_V850_23:
2457 if ((operand->flags & V850E_IMMEDIATE23) == 0)
2458 {
2459 errmsg = _("immediate operand is too large");
2460 goto error;
2461 }
2462 break;
2463
2464 case BFD_RELOC_32:
2465 case BFD_RELOC_V850_32_ABS:
2466 case BFD_RELOC_V850_32_PCREL:
2467 if ((operand->flags & V850E_IMMEDIATE32) == 0)
2468 {
2469 errmsg = _("immediate operand is too large");
2470 goto error;
2471 }
2472
2473 break;
2474
2475 default:
2476 as_bad (_("AAARG -> unhandled constant reloc: %d"), reloc);
2477 break;
2478 }
2479
2480 if (operand->flags & V850E_IMMEDIATE32)
2481 {
2482 extra_data_after_insn = TRUE;
2483 extra_data_len = 4;
2484 extra_data = 0;
2485 }
2486 else if (operand->flags & V850E_IMMEDIATE23)
2487 {
2488 if (reloc != BFD_RELOC_V850_23)
2489 {
2490 errmsg = _("immediate operand is too large");
2491 goto error;
2492 }
2493 extra_data_after_insn = TRUE;
2494 extra_data_len = 2;
2495 extra_data = 0;
2496 }
2497 else if ((operand->flags & V850E_IMMEDIATE16)
2498 || (operand->flags & V850E_IMMEDIATE16HI))
2499 {
2500 if (operand->flags & V850E_IMMEDIATE16HI
2501 && reloc != BFD_RELOC_HI16
2502 && reloc != BFD_RELOC_HI16_S)
2503 {
2504 errmsg = _("immediate operand is too large");
2505 goto error;
2506 }
2507 else if (operand->flags & V850E_IMMEDIATE16
2508 && reloc != BFD_RELOC_LO16)
2509 {
2510 errmsg = _("immediate operand is too large");
2511 goto error;
2512 }
2513
2514 extra_data_after_insn = TRUE;
2515 extra_data_len = 2;
2516 extra_data = 0;
2517 }
2518
2519 if (fc > MAX_INSN_FIXUPS)
2520 as_fatal (_("too many fixups"));
2521
2522 fixups[fc].exp = ex;
2523 fixups[fc].opindex = *opindex_ptr;
2524 fixups[fc].reloc = reloc;
2525 fc++;
2526 }
2527 else /* ex.X_op != O_constant. */
2528 {
2529 if ((reloc == BFD_RELOC_32
2530 || reloc == BFD_RELOC_V850_32_ABS
2531 || reloc == BFD_RELOC_V850_32_PCREL)
2532 && operand->bits < 32)
2533 {
2534 errmsg = _("immediate operand is too large");
2535 goto error;
2536 }
2537 else if (reloc == BFD_RELOC_V850_23
2538 && (operand->flags & V850E_IMMEDIATE23) == 0)
2539 {
2540 errmsg = _("immediate operand is too large");
2541 goto error;
2542 }
2543 else if ((reloc == BFD_RELOC_HI16
2544 || reloc == BFD_RELOC_HI16_S)
2545 && operand->bits < 16)
2546 {
2547 errmsg = _("immediate operand is too large");
2548 goto error;
2549 }
2550
2551 if (operand->flags & V850E_IMMEDIATE32)
2552 {
2553 extra_data_after_insn = TRUE;
2554 extra_data_len = 4;
2555 extra_data = 0;
2556 }
2557 else if (operand->flags & V850E_IMMEDIATE23)
2558 {
2559 if (reloc != BFD_RELOC_V850_23)
2560 {
2561 errmsg = _("immediate operand is too large");
2562 goto error;
2563 }
2564 extra_data_after_insn = TRUE;
2565 extra_data_len = 2;
2566 extra_data = 0;
2567 }
2568 else if ((operand->flags & V850E_IMMEDIATE16)
2569 || (operand->flags & V850E_IMMEDIATE16HI))
2570 {
2571 if (operand->flags & V850E_IMMEDIATE16HI
2572 && reloc != BFD_RELOC_HI16
2573 && reloc != BFD_RELOC_HI16_S)
2574 {
2575 errmsg = _("immediate operand is too large");
2576 goto error;
2577 }
2578 else if (operand->flags & V850E_IMMEDIATE16
2579 && reloc != BFD_RELOC_LO16)
2580 {
2581 errmsg = _("immediate operand is too large");
2582 goto error;
2583 }
2584
2585 extra_data_after_insn = TRUE;
2586 extra_data_len = 2;
2587 extra_data = 0;
2588 }
2589
2590 if (fc > MAX_INSN_FIXUPS)
2591 as_fatal (_("too many fixups"));
2592
2593 fixups[fc].exp = ex;
2594 fixups[fc].opindex = *opindex_ptr;
2595 fixups[fc].reloc = reloc;
2596 fc++;
2597 }
2598 }
2599 else if (operand->flags & V850E_IMMEDIATE16
2600 || operand->flags & V850E_IMMEDIATE16HI)
2601 {
2602 expression (&ex);
2603
2604 switch (ex.X_op)
2605 {
2606 case O_constant:
2607 if (operand->flags & V850E_IMMEDIATE16HI)
2608 {
2609 if (ex.X_add_number & 0xffff)
2610 {
2611 errmsg = _("constant too big to fit into instruction");
2612 goto error;
2613 }
2614
2615 ex.X_add_number >>= 16;
2616 }
2617 if (operand->flags & V850E_IMMEDIATE16)
2618 {
2619 if ((ex.X_add_number & 0xffff8000)
2620 && ((ex.X_add_number & 0xffff8000) != 0xffff8000))
2621 {
2622 errmsg = _("constant too big to fit into instruction");
2623 goto error;
2624 }
2625 }
2626 break;
2627
2628 case O_illegal:
2629 errmsg = _("illegal operand");
2630 goto error;
2631
2632 case O_absent:
2633 errmsg = _("missing operand");
2634 goto error;
2635
2636 default:
2637 if (fc >= MAX_INSN_FIXUPS)
2638 as_fatal (_("too many fixups"));
2639
2640 fixups[fc].exp = ex;
2641 fixups[fc].opindex = *opindex_ptr;
2642 fixups[fc].reloc = operand->default_reloc;
2643 ++fc;
2644
2645 ex.X_add_number = 0;
2646 break;
2647 }
2648
2649 extra_data_after_insn = TRUE;
2650 extra_data_len = 2;
2651 extra_data = ex.X_add_number;
2652 }
2653 else if (operand->flags & V850E_IMMEDIATE23)
2654 {
2655 expression (&ex);
2656
2657 switch (ex.X_op)
2658 {
2659 case O_constant:
2660 break;
2661
2662 case O_illegal:
2663 errmsg = _("illegal operand");
2664 goto error;
2665
2666 case O_absent:
2667 errmsg = _("missing operand");
2668 goto error;
2669
2670 default:
2671 break;
2672 }
2673
2674 if (fc >= MAX_INSN_FIXUPS)
2675 as_fatal (_("too many fixups"));
2676
2677 fixups[fc].exp = ex;
2678 fixups[fc].opindex = *opindex_ptr;
2679 fixups[fc].reloc = operand->default_reloc;
2680 ++fc;
2681
2682 extra_data_after_insn = TRUE;
2683 extra_data_len = 2;
2684 extra_data = 0;
2685 }
2686 else if (operand->flags & V850E_IMMEDIATE32)
2687 {
2688 expression (&ex);
2689
2690 switch (ex.X_op)
2691 {
2692 case O_constant:
2693 if ((operand->default_reloc == BFD_RELOC_V850_32_ABS
2694 || operand->default_reloc == BFD_RELOC_V850_32_PCREL)
2695 && (ex.X_add_number & 1))
2696 {
2697 errmsg = _("odd number cannot be used here");
2698 goto error;
2699 }
2700 break;
2701
2702 case O_illegal:
2703 errmsg = _("illegal operand");
2704 goto error;
2705
2706 case O_absent:
2707 errmsg = _("missing operand");
2708 goto error;
2709
2710 default:
2711 if (fc >= MAX_INSN_FIXUPS)
2712 as_fatal (_("too many fixups"));
2713
2714 fixups[fc].exp = ex;
2715 fixups[fc].opindex = *opindex_ptr;
2716 fixups[fc].reloc = operand->default_reloc;
2717 ++fc;
2718
2719 ex.X_add_number = 0;
2720 break;
2721 }
2722
2723 extra_data_after_insn = TRUE;
2724 extra_data_len = 4;
2725 extra_data = ex.X_add_number;
2726 }
2727 else if (operand->flags & V850E_OPERAND_REG_LIST)
2728 {
2729 errmsg = parse_register_list (&insn, operand);
2730
2731 if (errmsg)
2732 goto error;
2733 }
2734 else
2735 {
2736 errmsg = NULL;
2737
2738 if ((operand->flags & V850_OPERAND_REG) != 0)
2739 {
2740 if (!register_name (&ex))
2741 {
2742 errmsg = _("invalid register name");
2743 }
2744
2745 if ((operand->flags & V850_NOT_R0)
2746 && ex.X_add_number == 0)
2747 {
2748 errmsg = _("register r0 cannot be used here");
2749 }
2750
2751 if (operand->flags & V850_REG_EVEN)
2752 {
2753 if (ex.X_add_number % 2)
2754 errmsg = _("odd register cannot be used here");
2755 ex.X_add_number = ex.X_add_number / 2;
2756 }
2757
2758 }
2759 else if ((operand->flags & V850_OPERAND_SRG) != 0)
2760 {
2761 if (!system_register_name (&ex, TRUE))
2762 {
2763 errmsg = _("invalid system register name");
2764 }
2765 }
2766 else if ((operand->flags & V850_OPERAND_EP) != 0)
2767 {
2768 char *start = input_line_pointer;
2769 char c = get_symbol_end ();
2770
2771 if (strcmp (start, "ep") != 0 && strcmp (start, "r30") != 0)
2772 {
2773 /* Put things back the way we found them. */
2774 *input_line_pointer = c;
2775 input_line_pointer = start;
2776 errmsg = _("expected EP register");
2777 goto error;
2778 }
2779
2780 *input_line_pointer = c;
2781 str = input_line_pointer;
2782 input_line_pointer = hold;
2783
2784 while (*str == ' ' || *str == ','
2785 || *str == '[' || *str == ']')
2786 ++str;
2787 continue;
2788 }
2789 else if ((operand->flags & V850_OPERAND_CC) != 0)
2790 {
2791 if (!cc_name (&ex, TRUE))
2792 {
2793 errmsg = _("invalid condition code name");
2794 }
2795
2796 if ((operand->flags & V850_NOT_SA)
2797 && ex.X_add_number == COND_SA_NUM)
2798 {
2799 errmsg = _("condition sa cannot be used here");
2800 }
2801 }
2802 else if ((operand->flags & V850_OPERAND_FLOAT_CC) != 0)
2803 {
2804 if (!float_cc_name (&ex, TRUE))
2805 {
2806 errmsg = _("invalid condition code name");
2807 }
2808 }
2809 else if ((operand->flags & V850_OPERAND_CACHEOP) != 0)
2810 {
2811 if (!cacheop_name (&ex, TRUE))
2812 errmsg = _("invalid cache oparation name");
2813 }
2814 else if ((operand->flags & V850_OPERAND_PREFOP) != 0)
2815 {
2816 if (!prefop_name (&ex, TRUE))
2817 errmsg = _("invalid pref oparation name");
2818 }
2819 else if ((operand->flags & V850_OPERAND_VREG) != 0)
2820 {
2821 if (!vector_register_name (&ex))
2822 errmsg = _("invalid vector register name");
2823 }
2824 else if ((register_name (&ex)
2825 && (operand->flags & V850_OPERAND_REG) == 0))
2826 {
2827 char c;
2828 int exists = 0;
2829
2830 /* It is possible that an alias has been defined that
2831 matches a register name. For example the code may
2832 include a ".set ZERO, 0" directive, which matches
2833 the register name "zero". Attempt to reparse the
2834 field as an expression, and only complain if we
2835 cannot generate a constant. */
2836
2837 input_line_pointer = str;
2838
2839 c = get_symbol_end ();
2840
2841 if (symbol_find (str) != NULL)
2842 exists = 1;
2843
2844 *input_line_pointer = c;
2845 input_line_pointer = str;
2846
2847 expression (&ex);
2848
2849 if (ex.X_op != O_constant)
2850 {
2851 /* If this register is actually occurring too early on
2852 the parsing of the instruction, (because another
2853 field is missing) then report this. */
2854 if (opindex_ptr[1] != 0
2855 && ((v850_operands[opindex_ptr[1]].flags
2856 & V850_OPERAND_REG)
2857 ||(v850_operands[opindex_ptr[1]].flags
2858 & V850_OPERAND_VREG)))
2859 errmsg = _("syntax error: value is missing before the register name");
2860 else
2861 errmsg = _("syntax error: register not expected");
2862
2863 /* If we created a symbol in the process of this
2864 test then delete it now, so that it will not
2865 be output with the real symbols... */
2866 if (exists == 0
2867 && ex.X_op == O_symbol)
2868 symbol_remove (ex.X_add_symbol,
2869 &symbol_rootP, &symbol_lastP);
2870 }
2871 }
2872 else if (system_register_name (&ex, FALSE)
2873 && (operand->flags & V850_OPERAND_SRG) == 0)
2874 {
2875 errmsg = _("syntax error: system register not expected");
2876 }
2877 else if (cc_name (&ex, FALSE)
2878 && (operand->flags & V850_OPERAND_CC) == 0)
2879 {
2880 errmsg = _("syntax error: condition code not expected");
2881 }
2882 else if (float_cc_name (&ex, FALSE)
2883 && (operand->flags & V850_OPERAND_FLOAT_CC) == 0)
2884 {
2885 errmsg = _("syntax error: condition code not expected");
2886 }
2887 else if (vector_register_name (&ex)
2888 && (operand->flags & V850_OPERAND_VREG) == 0)
2889 {
2890 errmsg = _("syntax error: vector register not expected");
2891 }
2892 else
2893 {
2894 expression (&ex);
2895
2896 if ((operand->flags & V850_NOT_IMM0)
2897 && ex.X_op == O_constant
2898 && ex.X_add_number == 0)
2899 {
2900 errmsg = _("immediate 0 cannot be used here");
2901 }
2902
2903 /* Special case:
2904 If we are assembling a MOV/JARL/JR instruction and the immediate
2905 value does not fit into the bits available then create a
2906 fake error so that the next MOV/JARL/JR instruction will be
2907 selected. This one has a 32 bit immediate field. */
2908
2909 if ((strcmp (opcode->name, "mov") == 0
2910 || strcmp (opcode->name, "jarl") == 0
2911 || strcmp (opcode->name, "jr") == 0)
2912 && ex.X_op == O_constant
2913 && (ex.X_add_number < (-(1 << (operand->bits - 1)))
2914 || ex.X_add_number > ((1 << (operand->bits - 1)) - 1)))
2915 {
2916 errmsg = _("immediate operand is too large");
2917 }
2918
2919 if ((strcmp (opcode->name, "jarl") == 0
2920 || strcmp (opcode->name, "jr") == 0)
2921 && ex.X_op != O_constant
2922 && operand->bits != default_disp_size)
2923 {
2924 errmsg = _("immediate operand is not match");
2925 }
2926
2927 /* Special case2 :
2928 If we are assembling a ld/st instruction and the immediate
2929 value does not fit into the bits available then create a
2930 fake error so that the next ld/st instruction will be
2931 selected. */
2932 if ( ( (strncmp (opcode->name, "st.", 3) == 0)
2933 || (strncmp (opcode->name, "ld.", 3) == 0))
2934 && ex.X_op == O_constant
2935 && (ex.X_add_number < (-(1 << (operand->bits - 1)))
2936 || ex.X_add_number > ((1 << (operand->bits - 1)) - 1)))
2937 errmsg = _("displacement is too large");
2938 }
2939
2940 if (errmsg)
2941 goto error;
2942
2943 switch (ex.X_op)
2944 {
2945 case O_illegal:
2946 errmsg = _("illegal operand");
2947 goto error;
2948 case O_absent:
2949 errmsg = _("missing operand");
2950 goto error;
2951 case O_register:
2952 if ((operand->flags
2953 & (V850_OPERAND_REG | V850_OPERAND_SRG | V850_OPERAND_VREG)) == 0)
2954 {
2955 errmsg = _("invalid operand");
2956 goto error;
2957 }
2958
2959 insn = v850_insert_operand (insn, operand,
2960 ex.X_add_number,
2961 &warningmsg);
2962
2963 break;
2964
2965 case O_constant:
2966 insn = v850_insert_operand (insn, operand, ex.X_add_number,
2967 &warningmsg);
2968 break;
2969
2970 default:
2971 /* We need to generate a fixup for this expression. */
2972 if (fc >= MAX_INSN_FIXUPS)
2973 as_fatal (_("too many fixups"));
2974
2975 fixups[fc].exp = ex;
2976 fixups[fc].opindex = *opindex_ptr;
2977 fixups[fc].reloc = BFD_RELOC_NONE;
2978 ++fc;
2979 break;
2980 }
2981 }
2982
2983 str = input_line_pointer;
2984 input_line_pointer = hold;
2985
2986 while (*str == ' ' || *str == ',' || *str == '[' || *str == ']'
2987 || *str == ')')
2988 ++str;
2989 }
2990
2991 while (ISSPACE (*str))
2992 ++str;
2993
2994 if (*str == '\0')
2995 match = 1;
2996
2997 error:
2998 if (match == 0)
2999 {
3000 if ((opindex_ptr - opcode->operands) >= most_match_count)
3001 {
3002 most_match_count = opindex_ptr - opcode->operands;
3003 if (errmsg != NULL)
3004 strncpy (most_match_errmsg, errmsg, sizeof (most_match_errmsg)-1);
3005 }
3006
3007 next_opcode = opcode + 1;
3008 if (next_opcode->name != NULL
3009 && strcmp (next_opcode->name, opcode->name) == 0)
3010 {
3011 opcode = next_opcode;
3012
3013 /* Skip versions that are not supported by the target
3014 processor. */
3015 if ((opcode->processors & processor_mask) == 0)
3016 goto error;
3017
3018 continue;
3019 }
3020
3021 if (most_match_errmsg[0] == 0)
3022 /* xgettext:c-format. */
3023 as_bad (_("junk at end of line: `%s'"), str);
3024 else
3025 as_bad ("%s: %s", copy_of_instruction, most_match_errmsg);
3026
3027 if (*input_line_pointer == ']')
3028 ++input_line_pointer;
3029
3030 ignore_rest_of_line ();
3031 input_line_pointer = saved_input_line_pointer;
3032 return;
3033 }
3034
3035 if (warningmsg != NULL)
3036 as_warn ("%s", warningmsg);
3037 break;
3038 }
3039
3040 input_line_pointer = str;
3041
3042 /* Tie dwarf2 debug info to the address at the start of the insn.
3043 We can't do this after the insn has been output as the current
3044 frag may have been closed off. eg. by frag_var. */
3045 dwarf2_emit_insn (0);
3046
3047 /* Write out the instruction. */
3048
3049 if (relaxable && fc > 0)
3050 {
3051 insn_size = 2;
3052 fc = 0;
3053
3054 if (strcmp (opcode->name, "loop") == 0)
3055 {
3056 if (((processor_mask & PROCESSOR_V850E3V5_UP) == 0) || default_disp_size == 22)
3057 {
3058 insn_size = 4;
3059 f = frag_var (rs_machine_dependent, 6, 2, SUBYPTE_LOOP_16_22,
3060 fixups[0].exp.X_add_symbol,
3061 fixups[0].exp.X_add_number,
3062 (char *)(size_t) fixups[0].opindex);
3063 md_number_to_chars (f, insn, insn_size);
3064 md_number_to_chars (f+4, 0, 4);
3065 }
3066 else
3067 {
3068 as_bad (_("loop: 32-bit displacement not supported"));
3069 }
3070 }
3071 else if (strcmp (opcode->name, "br") == 0
3072 || strcmp (opcode->name, "jbr") == 0)
3073 {
3074 if ((processor_mask & PROCESSOR_V850E2_UP) == 0 || default_disp_size == 22)
3075 {
3076 f = frag_var (rs_machine_dependent, 4, 2, SUBYPTE_UNCOND_9_22,
3077 fixups[0].exp.X_add_symbol,
3078 fixups[0].exp.X_add_number,
3079 (char *)(size_t) fixups[0].opindex);
3080 md_number_to_chars (f, insn, insn_size);
3081 md_number_to_chars (f + 2, 0, 2);
3082 }
3083 else
3084 {
3085 f = frag_var (rs_machine_dependent, 6, 4, SUBYPTE_UNCOND_9_22_32,
3086 fixups[0].exp.X_add_symbol,
3087 fixups[0].exp.X_add_number,
3088 (char *)(size_t) fixups[0].opindex);
3089 md_number_to_chars (f, insn, insn_size);
3090 md_number_to_chars (f + 2, 0, 4);
3091 }
3092 }
3093 else /* b<cond>, j<cond>. */
3094 {
3095 if (default_disp_size == 22
3096 || (processor_mask & PROCESSOR_V850E2_UP) == 0)
3097 {
3098 if (processor_mask & PROCESSOR_V850E2V3_UP && !no_bcond17)
3099 {
3100 if (strcmp (opcode->name, "bsa") == 0)
3101 {
3102 f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_SA_9_17_22,
3103 fixups[0].exp.X_add_symbol,
3104 fixups[0].exp.X_add_number,
3105 (char *)(size_t) fixups[0].opindex);
3106 md_number_to_chars (f, insn, insn_size);
3107 md_number_to_chars (f + 2, 0, 6);
3108 }
3109 else
3110 {
3111 f = frag_var (rs_machine_dependent, 6, 4, SUBYPTE_COND_9_17_22,
3112 fixups[0].exp.X_add_symbol,
3113 fixups[0].exp.X_add_number,
3114 (char *)(size_t) fixups[0].opindex);
3115 md_number_to_chars (f, insn, insn_size);
3116 md_number_to_chars (f + 2, 0, 4);
3117 }
3118 }
3119 else
3120 {
3121 if (strcmp (opcode->name, "bsa") == 0)
3122 {
3123 f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_SA_9_22,
3124 fixups[0].exp.X_add_symbol,
3125 fixups[0].exp.X_add_number,
3126 (char *)(size_t) fixups[0].opindex);
3127 md_number_to_chars (f, insn, insn_size);
3128 md_number_to_chars (f + 2, 0, 6);
3129 }
3130 else
3131 {
3132 f = frag_var (rs_machine_dependent, 6, 4, SUBYPTE_COND_9_22,
3133 fixups[0].exp.X_add_symbol,
3134 fixups[0].exp.X_add_number,
3135 (char *)(size_t) fixups[0].opindex);
3136 md_number_to_chars (f, insn, insn_size);
3137 md_number_to_chars (f + 2, 0, 4);
3138 }
3139 }
3140 }
3141 else
3142 {
3143 if (processor_mask & PROCESSOR_V850E2V3_UP && !no_bcond17)
3144 {
3145 if (strcmp (opcode->name, "bsa") == 0)
3146 {
3147 f = frag_var (rs_machine_dependent, 10, 8, SUBYPTE_SA_9_17_22_32,
3148 fixups[0].exp.X_add_symbol,
3149 fixups[0].exp.X_add_number,
3150 (char *)(size_t) fixups[0].opindex);
3151 md_number_to_chars (f, insn, insn_size);
3152 md_number_to_chars (f + 2, 0, 8);
3153 }
3154 else
3155 {
3156 f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_COND_9_17_22_32,
3157 fixups[0].exp.X_add_symbol,
3158 fixups[0].exp.X_add_number,
3159 (char *)(size_t) fixups[0].opindex);
3160 md_number_to_chars (f, insn, insn_size);
3161 md_number_to_chars (f + 2, 0, 6);
3162 }
3163 }
3164 else
3165 {
3166 if (strcmp (opcode->name, "bsa") == 0)
3167 {
3168 f = frag_var (rs_machine_dependent, 10, 8, SUBYPTE_SA_9_22_32,
3169 fixups[0].exp.X_add_symbol,
3170 fixups[0].exp.X_add_number,
3171 (char *)(size_t) fixups[0].opindex);
3172 md_number_to_chars (f, insn, insn_size);
3173 md_number_to_chars (f + 2, 0, 8);
3174 }
3175 else
3176 {
3177 f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_COND_9_22_32,
3178 fixups[0].exp.X_add_symbol,
3179 fixups[0].exp.X_add_number,
3180 (char *)(size_t) fixups[0].opindex);
3181 md_number_to_chars (f, insn, insn_size);
3182 md_number_to_chars (f + 2, 0, 6);
3183 }
3184 }
3185 }
3186 }
3187 }
3188 else
3189 {
3190 /* Four byte insns have an opcode with the two high bits on. */
3191 if ((insn & 0x0600) == 0x0600)
3192 insn_size = 4;
3193 else
3194 insn_size = 2;
3195
3196 /* Special case: 32 bit MOV. */
3197 if ((insn & 0xffe0) == 0x0620)
3198 insn_size = 2;
3199
3200 /* Special case: 32 bit JARL,JMP,JR. */
3201 if ((insn & 0x1ffe0) == 0x2e0 /* JARL. */
3202 || (insn & 0x1ffe0) == 0x6e0 /* JMP. */
3203 || (insn & 0x1ffff) == 0x2e0) /* JR. */
3204 insn_size = 2;
3205
3206 if (obstack_room (& frchain_now->frch_obstack) < (insn_size + extra_data_len))
3207 {
3208 frag_wane (frag_now);
3209 frag_new (0);
3210 }
3211
3212 f = frag_more (insn_size);
3213 md_number_to_chars (f, insn, insn_size);
3214
3215 if (extra_data_after_insn)
3216 {
3217 f = frag_more (extra_data_len);
3218 md_number_to_chars (f, extra_data, extra_data_len);
3219
3220 extra_data_after_insn = FALSE;
3221 }
3222 }
3223
3224 /* Create any fixups. At this point we do not use a
3225 bfd_reloc_code_real_type, but instead just use the
3226 BFD_RELOC_UNUSED plus the operand index. This lets us easily
3227 handle fixups for any operand type, although that is admittedly
3228 not a very exciting feature. We pick a BFD reloc type in
3229 md_apply_fix. */
3230 for (i = 0; i < fc; i++)
3231 {
3232 const struct v850_operand *operand;
3233 bfd_reloc_code_real_type reloc;
3234
3235 operand = &v850_operands[fixups[i].opindex];
3236
3237 reloc = fixups[i].reloc;
3238
3239 if (reloc != BFD_RELOC_NONE)
3240 {
3241 reloc_howto_type *reloc_howto =
3242 bfd_reloc_type_lookup (stdoutput, reloc);
3243 int size;
3244 int address;
3245 fixS *fixP;
3246
3247 if (!reloc_howto)
3248 abort ();
3249
3250 size = bfd_get_reloc_size (reloc_howto);
3251
3252 /* XXX This will abort on an R_V850_8 reloc -
3253 is this reloc actually used? */
3254 if (size != 2 && size != 4)
3255 abort ();
3256
3257 if (extra_data_len == 0)
3258 {
3259 address = (f - frag_now->fr_literal) + insn_size - size;
3260 }
3261 else
3262 {
3263 address = (f - frag_now->fr_literal) + extra_data_len - size;
3264 }
3265
3266 if ((operand->flags & V850E_IMMEDIATE32) && (operand->flags & V850_PCREL))
3267 {
3268 fixups[i].exp.X_add_number += 2;
3269 }
3270 else if (operand->default_reloc == BFD_RELOC_V850_16_PCREL)
3271 {
3272 fixups[i].exp.X_add_number += 2;
3273 address += 2;
3274 }
3275
3276 /* fprintf (stderr, "0x%x %d %ld\n", address, size, fixups[i].exp.X_add_number); */
3277 fixP = fix_new_exp (frag_now, address, size,
3278 &fixups[i].exp,
3279 reloc_howto->pc_relative,
3280 reloc);
3281
3282 fixP->tc_fix_data = (void *) operand;
3283
3284 switch (reloc)
3285 {
3286 case BFD_RELOC_LO16:
3287 case BFD_RELOC_V850_LO16_S1:
3288 case BFD_RELOC_V850_LO16_SPLIT_OFFSET:
3289 case BFD_RELOC_HI16:
3290 case BFD_RELOC_HI16_S:
3291 fixP->fx_no_overflow = 1;
3292 break;
3293 default:
3294 break;
3295 }
3296 }
3297 else
3298 {
3299 gas_assert (f != NULL);
3300 fix_new_exp (frag_now,
3301 f - frag_now->fr_literal, 4,
3302 & fixups[i].exp,
3303 (operand->flags & V850_PCREL) != 0,
3304 (bfd_reloc_code_real_type) (fixups[i].opindex
3305 + (int) BFD_RELOC_UNUSED));
3306 }
3307 }
3308
3309 input_line_pointer = saved_input_line_pointer;
3310 }
3311
3312 /* If while processing a fixup, a reloc really needs to be created
3313 then it is done here. */
3314
3315 arelent *
3316 tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp)
3317 {
3318 arelent *reloc;
3319
3320 reloc = xmalloc (sizeof (arelent));
3321 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
3322 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
3323 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3324
3325 if ( fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY
3326 || fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3327 || fixp->fx_r_type == BFD_RELOC_V850_LONGCALL
3328 || fixp->fx_r_type == BFD_RELOC_V850_LONGJUMP
3329 || fixp->fx_r_type == BFD_RELOC_V850_ALIGN)
3330 reloc->addend = fixp->fx_offset;
3331 else
3332 {
3333 #if 0
3334 if (fixp->fx_r_type == BFD_RELOC_32
3335 && fixp->fx_pcrel)
3336 fixp->fx_r_type = BFD_RELOC_32_PCREL;
3337 #endif
3338
3339 reloc->addend = fixp->fx_addnumber;
3340 }
3341
3342 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
3343
3344 if (reloc->howto == NULL)
3345 {
3346 as_bad_where (fixp->fx_file, fixp->fx_line,
3347 /* xgettext:c-format */
3348 _("reloc %d not supported by object file format"),
3349 (int) fixp->fx_r_type);
3350
3351 xfree (reloc);
3352
3353 return NULL;
3354 }
3355
3356 return reloc;
3357 }
3358
3359 void
3360 v850_handle_align (fragS * frag)
3361 {
3362 if (v850_relax
3363 && frag->fr_type == rs_align
3364 && frag->fr_address + frag->fr_fix > 0
3365 && frag->fr_offset > 1
3366 && now_seg != bss_section
3367 && now_seg != v850_seg_table[SBSS_SECTION].s
3368 && now_seg != v850_seg_table[TBSS_SECTION].s
3369 && now_seg != v850_seg_table[ZBSS_SECTION].s)
3370 fix_new (frag, frag->fr_fix, 2, & abs_symbol, frag->fr_offset, 0,
3371 BFD_RELOC_V850_ALIGN);
3372 }
3373
3374 /* Return current size of variable part of frag. */
3375
3376 int
3377 md_estimate_size_before_relax (fragS *fragp, asection *seg ATTRIBUTE_UNUSED)
3378 {
3379 if (fragp->fr_subtype >= sizeof (md_relax_table) / sizeof (md_relax_table[0]))
3380 abort ();
3381
3382 return md_relax_table[fragp->fr_subtype].rlx_length;
3383 }
3384
3385 long
3386 v850_pcrel_from_section (fixS *fixp, segT section)
3387 {
3388 /* If the symbol is undefined, or in a section other than our own,
3389 or it is weak (in which case it may well be in another section,
3390 then let the linker figure it out. */
3391 if (fixp->fx_addsy != (symbolS *) NULL
3392 && (! S_IS_DEFINED (fixp->fx_addsy)
3393 || S_IS_WEAK (fixp->fx_addsy)
3394 || (S_GET_SEGMENT (fixp->fx_addsy) != section)))
3395 return 0;
3396
3397 return fixp->fx_frag->fr_address + fixp->fx_where;
3398 }
3399
3400 void
3401 md_apply_fix (fixS *fixP, valueT *valueP, segT seg ATTRIBUTE_UNUSED)
3402 {
3403 valueT value = * valueP;
3404 char *where;
3405
3406 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3407 || fixP->fx_r_type == BFD_RELOC_V850_LONGCALL
3408 || fixP->fx_r_type == BFD_RELOC_V850_LONGJUMP
3409 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3410 {
3411 fixP->fx_done = 0;
3412 return;
3413 }
3414
3415 if (fixP->fx_addsy == (symbolS *) NULL)
3416 fixP->fx_addnumber = value,
3417 fixP->fx_done = 1;
3418
3419 else if (fixP->fx_pcrel)
3420 fixP->fx_addnumber = fixP->fx_offset;
3421
3422 else
3423 {
3424 value = fixP->fx_offset;
3425 if (fixP->fx_subsy != (symbolS *) NULL)
3426 {
3427 if (S_GET_SEGMENT (fixP->fx_subsy) == absolute_section)
3428 value -= S_GET_VALUE (fixP->fx_subsy);
3429 else
3430 /* We don't actually support subtracting a symbol. */
3431 as_bad_where (fixP->fx_file, fixP->fx_line,
3432 _("expression too complex"));
3433 }
3434 fixP->fx_addnumber = value;
3435 }
3436
3437 if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED)
3438 {
3439 int opindex;
3440 const struct v850_operand *operand;
3441 unsigned long insn;
3442 const char *errmsg = NULL;
3443
3444 opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED;
3445 operand = &v850_operands[opindex];
3446
3447 /* Fetch the instruction, insert the fully resolved operand
3448 value, and stuff the instruction back again.
3449
3450 Note the instruction has been stored in little endian
3451 format! */
3452 where = fixP->fx_frag->fr_literal + fixP->fx_where;
3453
3454 if (fixP->fx_size > 2)
3455 insn = bfd_getl32 ((unsigned char *) where);
3456 else
3457 insn = bfd_getl16 ((unsigned char *) where);
3458
3459 /* When inserting loop offets a backwards displacement
3460 is encoded as a positive value. */
3461 if (operand->flags & V850_INVERSE_PCREL)
3462 value = - value;
3463
3464 insn = v850_insert_operand (insn, operand, (offsetT) value,
3465 &errmsg);
3466 if (errmsg)
3467 as_warn_where (fixP->fx_file, fixP->fx_line, "%s", errmsg);
3468
3469 if (fixP->fx_size > 2)
3470 bfd_putl32 ((bfd_vma) insn, (unsigned char *) where);
3471 else
3472 bfd_putl16 ((bfd_vma) insn, (unsigned char *) where);
3473
3474 if (fixP->fx_done)
3475 /* Nothing else to do here. */
3476 return;
3477
3478 /* Determine a BFD reloc value based on the operand information.
3479 We are only prepared to turn a few of the operands into relocs. */
3480
3481 if (operand->default_reloc == BFD_RELOC_NONE)
3482 {
3483 as_bad_where (fixP->fx_file, fixP->fx_line,
3484 _("unresolved expression that must be resolved"));
3485 fixP->fx_done = 1;
3486 return;
3487 }
3488
3489 {
3490 fixP->fx_r_type = operand->default_reloc;
3491 if (operand->default_reloc == BFD_RELOC_V850_16_PCREL)
3492 {
3493 fixP->fx_where += 2;
3494 fixP->fx_size = 2;
3495 fixP->fx_addnumber += 2;
3496 }
3497 }
3498 }
3499 else if (fixP->fx_done)
3500 {
3501 /* We still have to insert the value into memory! */
3502 where = fixP->fx_frag->fr_literal + fixP->fx_where;
3503
3504 if (fixP->tc_fix_data != NULL
3505 && ((struct v850_operand *) fixP->tc_fix_data)->insert != NULL)
3506 {
3507 const char * message = NULL;
3508 struct v850_operand * operand = (struct v850_operand *) fixP->tc_fix_data;
3509 unsigned long insn;
3510
3511 /* The variable "where" currently points at the exact point inside
3512 the insn where we need to insert the value. But we need to
3513 extract the entire insn so we probably need to move "where"
3514 back a few bytes. */
3515
3516 if (fixP->fx_size == 2)
3517 where -= 2;
3518 else if (fixP->fx_size == 1)
3519 where -= 3;
3520
3521 insn = bfd_getl32 ((unsigned char *) where);
3522
3523 /* Use the operand's insertion procedure, if present, in order to
3524 make sure that the value is correctly stored in the insn. */
3525 insn = operand->insert (insn, (offsetT) value, & message);
3526 /* Ignore message even if it is set. */
3527
3528 bfd_putl32 ((bfd_vma) insn, (unsigned char *) where);
3529 }
3530 else
3531 {
3532 switch (fixP->fx_r_type)
3533 {
3534 case BFD_RELOC_V850_32_ABS:
3535 case BFD_RELOC_V850_32_PCREL:
3536 bfd_putl32 (value & 0xfffffffe, (unsigned char *) where);
3537 break;
3538
3539 case BFD_RELOC_32:
3540 bfd_putl32 (value, (unsigned char *) where);
3541 break;
3542
3543 case BFD_RELOC_V850_23:
3544 bfd_putl32 (((value & 0x7f) << 4) | ((value & 0x7fff80) << (16-7))
3545 | (bfd_getl32 (where) & ~((0x7f << 4) | (0xffff << 16))),
3546 (unsigned char *) where);
3547 break;
3548
3549 case BFD_RELOC_16:
3550 case BFD_RELOC_HI16:
3551 case BFD_RELOC_HI16_S:
3552 case BFD_RELOC_LO16:
3553 case BFD_RELOC_V850_ZDA_16_16_OFFSET:
3554 case BFD_RELOC_V850_SDA_16_16_OFFSET:
3555 case BFD_RELOC_V850_TDA_16_16_OFFSET:
3556 case BFD_RELOC_V850_CALLT_16_16_OFFSET:
3557 bfd_putl16 (value & 0xffff, (unsigned char *) where);
3558 break;
3559
3560 case BFD_RELOC_8:
3561 *where = value & 0xff;
3562 break;
3563
3564 case BFD_RELOC_V850_9_PCREL:
3565 bfd_putl16 (((value & 0x1f0) << 7) | ((value & 0x0e) << 3)
3566 | (bfd_getl16 (where) & ~((0x1f0 << 7) | (0x0e << 3))), where);
3567 break;
3568
3569 case BFD_RELOC_V850_17_PCREL:
3570 bfd_putl32 (((value & 0x10000) >> (16 - 4)) | ((value & 0xfffe) << 16)
3571 | (bfd_getl32 (where) & ~((0x10000 >> (16 - 4)) | (0xfffe << 16))), where);
3572 break;
3573
3574 case BFD_RELOC_V850_16_PCREL:
3575 bfd_putl16 ((-value & 0xfffe) | (bfd_getl16 (where + 2) & 0x0001),
3576 (unsigned char *) (where + 2));
3577 break;
3578
3579 case BFD_RELOC_V850_22_PCREL:
3580 bfd_putl32 (((value & 0xfffe) << 16) | ((value & 0x3f0000) >> 16)
3581 | (bfd_getl32 (where) & ~((0xfffe << 16) | (0x3f0000 >> 16))), where);
3582 break;
3583
3584 case BFD_RELOC_V850_16_S1:
3585 case BFD_RELOC_V850_LO16_S1:
3586 case BFD_RELOC_V850_ZDA_15_16_OFFSET:
3587 case BFD_RELOC_V850_SDA_15_16_OFFSET:
3588 bfd_putl16 (value & 0xfffe, (unsigned char *) where);
3589 break;
3590
3591 case BFD_RELOC_V850_16_SPLIT_OFFSET:
3592 case BFD_RELOC_V850_LO16_SPLIT_OFFSET:
3593 case BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET:
3594 case BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET:
3595 bfd_putl32 (((value << 16) & 0xfffe0000)
3596 | ((value << 5) & 0x20)
3597 | (bfd_getl32 (where) & ~0xfffe0020), where);
3598 break;
3599
3600 case BFD_RELOC_V850_TDA_6_8_OFFSET:
3601 *where = (*where & ~0x7e) | ((value >> 1) & 0x7e);
3602 break;
3603
3604 case BFD_RELOC_V850_TDA_7_8_OFFSET:
3605 *where = (*where & ~0x7f) | ((value >> 1) & 0x7f);
3606 break;
3607
3608 case BFD_RELOC_V850_TDA_7_7_OFFSET:
3609 *where = (*where & ~0x7f) | (value & 0x7f);
3610 break;
3611
3612 case BFD_RELOC_V850_TDA_4_5_OFFSET:
3613 *where = (*where & ~0xf) | ((value >> 1) & 0xf);
3614 break;
3615
3616 case BFD_RELOC_V850_TDA_4_4_OFFSET:
3617 *where = (*where & ~0xf) | (value & 0xf);
3618 break;
3619
3620 case BFD_RELOC_V850_CALLT_6_7_OFFSET:
3621 *where = (*where & ~0x3f) | (value & 0x3f);
3622 break;
3623
3624 default:
3625 abort ();
3626 }
3627 }
3628 }
3629 }
3630
3631 /* Parse a cons expression. We have to handle hi(), lo(), etc
3632 on the v850. */
3633
3634 bfd_reloc_code_real_type
3635 parse_cons_expression_v850 (expressionS *exp)
3636 {
3637 const char *errmsg;
3638 bfd_reloc_code_real_type r;
3639
3640 /* See if there's a reloc prefix like hi() we have to handle. */
3641 r = v850_reloc_prefix (NULL, &errmsg);
3642
3643 /* Do normal expression parsing. */
3644 expression (exp);
3645 return r;
3646 }
3647
3648 /* Create a fixup for a cons expression. If parse_cons_expression_v850
3649 found a reloc prefix, then we use that reloc, else we choose an
3650 appropriate one based on the size of the expression. */
3651
3652 void
3653 cons_fix_new_v850 (fragS *frag,
3654 int where,
3655 int size,
3656 expressionS *exp,
3657 bfd_reloc_code_real_type r)
3658 {
3659 if (r == BFD_RELOC_NONE)
3660 {
3661 if (size == 4)
3662 r = BFD_RELOC_32;
3663 if (size == 2)
3664 r = BFD_RELOC_16;
3665 if (size == 1)
3666 r = BFD_RELOC_8;
3667 }
3668
3669 if (exp != NULL)
3670 fix_new_exp (frag, where, size, exp, 0, r);
3671 else
3672 fix_new (frag, where, size, NULL, 0, 0, r);
3673 }
3674
3675 bfd_boolean
3676 v850_fix_adjustable (fixS *fixP)
3677 {
3678 if (fixP->fx_addsy == NULL)
3679 return 1;
3680
3681 /* Don't adjust function names. */
3682 if (S_IS_FUNCTION (fixP->fx_addsy))
3683 return 0;
3684
3685 /* We need the symbol name for the VTABLE entries. */
3686 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3687 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3688 return 0;
3689
3690 return 1;
3691 }
3692
3693 int
3694 v850_force_relocation (struct fix *fixP)
3695 {
3696 if (fixP->fx_r_type == BFD_RELOC_V850_LONGCALL
3697 || fixP->fx_r_type == BFD_RELOC_V850_LONGJUMP)
3698 return 1;
3699
3700 if (v850_relax
3701 && (fixP->fx_pcrel
3702 || fixP->fx_r_type == BFD_RELOC_V850_ALIGN
3703 || fixP->fx_r_type == BFD_RELOC_V850_9_PCREL
3704 || fixP->fx_r_type == BFD_RELOC_V850_16_PCREL
3705 || fixP->fx_r_type == BFD_RELOC_V850_17_PCREL
3706 || fixP->fx_r_type == BFD_RELOC_V850_22_PCREL
3707 || fixP->fx_r_type == BFD_RELOC_V850_32_PCREL
3708 || fixP->fx_r_type >= BFD_RELOC_UNUSED))
3709 return 1;
3710
3711 return generic_force_reloc (fixP);
3712 }