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* config/tc-v850.c (md_assemble): Allow signed values for
[binutils-gdb.git] / gas / config / tc-v850.c
1 /* tc-v850.c -- Assembler code for the NEC V850
2 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
3 2006, 2007, 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 51 Franklin Street - Fifth Floor,
20 Boston, MA 02110-1301, USA. */
21
22 #include "as.h"
23 #include "safe-ctype.h"
24 #include "subsegs.h"
25 #include "opcode/v850.h"
26 #include "dwarf2dbg.h"
27
28 /* Sign-extend a 16-bit number. */
29 #define SEXT16(x) ((((x) & 0xffff) ^ (~0x7fff)) + 0x8000)
30
31 /* Temporarily holds the reloc in a cons expression. */
32 static bfd_reloc_code_real_type hold_cons_reloc = BFD_RELOC_UNUSED;
33
34 /* Set to TRUE if we want to be pedantic about signed overflows. */
35 static bfd_boolean warn_signed_overflows = FALSE;
36 static bfd_boolean warn_unsigned_overflows = FALSE;
37
38 /* Indicates the target BFD machine number. */
39 static int machine = -1;
40
41
42 /* Indiciates the target BFD architecture. */
43 int v850_target_arch = bfd_arch_v850_rh850;
44 const char * v850_target_format = "elf32-v850-rh850";
45 static flagword v850_e_flags = 0;
46
47 /* Indicates the target processor(s) for the assemble. */
48 static int processor_mask = 0;
49 \f
50 /* Structure to hold information about predefined registers. */
51 struct reg_name
52 {
53 const char *name;
54 int value;
55 unsigned int processors;
56 };
57
58 /* Generic assembler global variables which must be defined by all
59 targets. */
60
61 /* Characters which always start a comment. */
62 const char comment_chars[] = "#";
63
64 /* Characters which start a comment at the beginning of a line. */
65 const char line_comment_chars[] = ";#";
66
67 /* Characters which may be used to separate multiple commands on a
68 single line. */
69 const char line_separator_chars[] = ";";
70
71 /* Characters which are used to indicate an exponent in a floating
72 point number. */
73 const char EXP_CHARS[] = "eE";
74
75 /* Characters which mean that a number is a floating point constant,
76 as in 0d1.0. */
77 const char FLT_CHARS[] = "dD";
78 \f
79 const relax_typeS md_relax_table[] =
80 {
81 /* Conditional branches.(V850/V850E, max 22bit) */
82 #define SUBYPTE_COND_9_22 0
83 {0xfe, -0x100, 2, SUBYPTE_COND_9_22 + 1},
84 {0x1ffffe + 2, -0x200000 + 2, 6, 0},
85 /* Conditional branches.(V850/V850E, max 22bit) */
86 #define SUBYPTE_SA_9_22 2
87 {0xfe, -0x100, 2, SUBYPTE_SA_9_22 + 1},
88 {0x1ffffe + 4, -0x200000 + 4, 8, 0},
89 /* Unconditional branches.(V850/V850E, max 22bit) */
90 #define SUBYPTE_UNCOND_9_22 4
91 {0xfe, -0x100, 2, SUBYPTE_UNCOND_9_22 + 1},
92 {0x1ffffe, -0x200000, 4, 0},
93 /* Conditional branches.(V850E2, max 32bit) */
94 #define SUBYPTE_COND_9_22_32 6
95 {0xfe, -0x100, 2, SUBYPTE_COND_9_22_32 + 1},
96 {0x1fffff + 2, -0x200000 + 2, 6, SUBYPTE_COND_9_22_32 + 2},
97 {0x7ffffffe, -0x80000000, 8, 0},
98 /* Conditional branches.(V850E2, max 32bit) */
99 #define SUBYPTE_SA_9_22_32 9
100 {0xfe, -0x100, 2, SUBYPTE_SA_9_22_32 + 1},
101 {0x1ffffe + 4, -0x200000 + 4, 8, SUBYPTE_SA_9_22_32 + 2},
102 {0x7ffffffe, -0x80000000, 10, 0},
103 /* Unconditional branches.(V850E2, max 32bit) */
104 #define SUBYPTE_UNCOND_9_22_32 12
105 {0xfe, -0x100, 2, SUBYPTE_UNCOND_9_22_32 + 1},
106 {0x1ffffe, -0x200000, 4, SUBYPTE_UNCOND_9_22_32 + 2},
107 {0x7ffffffe, -0x80000000, 6, 0},
108 /* Conditional branches.(V850E2R max 22bit) */
109 #define SUBYPTE_COND_9_17_22 15
110 {0xfe, -0x100, 2, SUBYPTE_COND_9_17_22 + 1},
111 {0xfffe, -0x10000, 4, SUBYPTE_COND_9_17_22 + 2},
112 {0x1ffffe + 2, -0x200000 + 2, 6, 0},
113 /* Conditional branches.(V850E2R max 22bit) */
114 #define SUBYPTE_SA_9_17_22 18
115 {0xfe, -0x100, 2, SUBYPTE_SA_9_17_22 + 1},
116 {0xfffe, -0x10000, 4, SUBYPTE_SA_9_17_22 + 2},
117 {0x1ffffe + 4, -0x200000 + 4, 8, 0},
118 /* Conditional branches.(V850E2R max 32bit) */
119 #define SUBYPTE_COND_9_17_22_32 21
120 {0xfe, -0x100, 2, SUBYPTE_COND_9_17_22_32 + 1},
121 {0xfffe, -0x10000, 4, SUBYPTE_COND_9_17_22_32 + 2},
122 {0x1ffffe + 2, -0x200000 + 2, 6, SUBYPTE_COND_9_17_22_32 + 3},
123 {0x7ffffffe, -0x80000000, 8, 0},
124 /* Conditional branches.(V850E2R max 32bit) */
125 #define SUBYPTE_SA_9_17_22_32 25
126 {0xfe, -0x100, 2, SUBYPTE_SA_9_17_22_32 + 1},
127 {0xfffe, -0x10000, 4, SUBYPTE_SA_9_17_22_32 + 2},
128 {0x1ffffe + 4, -0x200000 + 4, 8, SUBYPTE_SA_9_17_22_32 + 3},
129 {0x7ffffffe, -0x80000000, 10, 0},
130 };
131
132 static int v850_relax = 0;
133
134 /* Default branch disp size 22 or 32. */
135 static int default_disp_size = 22;
136
137 /* Default no using bcond17. */
138 static int no_bcond17 = 0;
139
140 /* Default no using ld/st 23bit offset. */
141 static int no_stld23 = 0;
142
143 /* Fixups. */
144 #define MAX_INSN_FIXUPS 5
145
146 struct v850_fixup
147 {
148 expressionS exp;
149 int opindex;
150 bfd_reloc_code_real_type reloc;
151 };
152
153 struct v850_fixup fixups[MAX_INSN_FIXUPS];
154 static int fc;
155
156 struct v850_seg_entry
157 {
158 segT s;
159 const char *name;
160 flagword flags;
161 };
162
163 struct v850_seg_entry v850_seg_table[] =
164 {
165 { NULL, ".sdata",
166 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS
167 | SEC_SMALL_DATA },
168 { NULL, ".tdata",
169 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS },
170 { NULL, ".zdata",
171 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS },
172 { NULL, ".sbss",
173 SEC_ALLOC | SEC_SMALL_DATA },
174 { NULL, ".tbss",
175 SEC_ALLOC },
176 { NULL, ".zbss",
177 SEC_ALLOC},
178 { NULL, ".rosdata",
179 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_READONLY | SEC_DATA
180 | SEC_HAS_CONTENTS | SEC_SMALL_DATA },
181 { NULL, ".rozdata",
182 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_READONLY | SEC_DATA
183 | SEC_HAS_CONTENTS },
184 { NULL, ".scommon",
185 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS
186 | SEC_SMALL_DATA | SEC_IS_COMMON },
187 { NULL, ".tcommon",
188 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS
189 | SEC_IS_COMMON },
190 { NULL, ".zcommon",
191 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS
192 | SEC_IS_COMMON },
193 { NULL, ".call_table_data",
194 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS },
195 { NULL, ".call_table_text",
196 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_READONLY | SEC_CODE
197 | SEC_HAS_CONTENTS},
198 { NULL, ".bss",
199 SEC_ALLOC }
200 };
201
202 #define SDATA_SECTION 0
203 #define TDATA_SECTION 1
204 #define ZDATA_SECTION 2
205 #define SBSS_SECTION 3
206 #define TBSS_SECTION 4
207 #define ZBSS_SECTION 5
208 #define ROSDATA_SECTION 6
209 #define ROZDATA_SECTION 7
210 #define SCOMMON_SECTION 8
211 #define TCOMMON_SECTION 9
212 #define ZCOMMON_SECTION 10
213 #define CALL_TABLE_DATA_SECTION 11
214 #define CALL_TABLE_TEXT_SECTION 12
215 #define BSS_SECTION 13
216
217 static void
218 do_v850_seg (int i, subsegT sub)
219 {
220 struct v850_seg_entry *seg = v850_seg_table + i;
221
222 obj_elf_section_change_hook ();
223
224 if (seg->s != NULL)
225 subseg_set (seg->s, sub);
226 else
227 {
228 seg->s = subseg_new (seg->name, sub);
229 bfd_set_section_flags (stdoutput, seg->s, seg->flags);
230 if ((seg->flags & SEC_LOAD) == 0)
231 seg_info (seg->s)->bss = 1;
232 }
233 }
234
235 static void
236 v850_seg (int i)
237 {
238 subsegT sub = get_absolute_expression ();
239
240 do_v850_seg (i, sub);
241 demand_empty_rest_of_line ();
242 }
243
244 static void
245 v850_offset (int ignore ATTRIBUTE_UNUSED)
246 {
247 char *pfrag;
248 int temp = get_absolute_expression ();
249
250 pfrag = frag_var (rs_org, 1, 1, (relax_substateT)0, (symbolS *)0,
251 (offsetT) temp, (char *) 0);
252 *pfrag = 0;
253
254 demand_empty_rest_of_line ();
255 }
256
257 /* Copied from obj_elf_common() in gas/config/obj-elf.c. */
258
259 static void
260 v850_comm (int area)
261 {
262 char *name;
263 char c;
264 char *p;
265 int temp;
266 unsigned int size;
267 symbolS *symbolP;
268 int have_align;
269
270 name = input_line_pointer;
271 c = get_symbol_end ();
272
273 /* Just after name is now '\0'. */
274 p = input_line_pointer;
275 *p = c;
276
277 SKIP_WHITESPACE ();
278
279 if (*input_line_pointer != ',')
280 {
281 as_bad (_("Expected comma after symbol-name"));
282 ignore_rest_of_line ();
283 return;
284 }
285
286 /* Skip ','. */
287 input_line_pointer++;
288
289 if ((temp = get_absolute_expression ()) < 0)
290 {
291 /* xgettext:c-format */
292 as_bad (_(".COMMon length (%d.) < 0! Ignored."), temp);
293 ignore_rest_of_line ();
294 return;
295 }
296
297 size = temp;
298 *p = 0;
299 symbolP = symbol_find_or_make (name);
300 *p = c;
301
302 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
303 {
304 as_bad (_("Ignoring attempt to re-define symbol"));
305 ignore_rest_of_line ();
306 return;
307 }
308
309 if (S_GET_VALUE (symbolP) != 0)
310 {
311 if (S_GET_VALUE (symbolP) != size)
312 /* xgettext:c-format */
313 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %d."),
314 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), size);
315 }
316
317 know (symbol_get_frag (symbolP) == &zero_address_frag);
318
319 if (*input_line_pointer != ',')
320 have_align = 0;
321 else
322 {
323 have_align = 1;
324 input_line_pointer++;
325 SKIP_WHITESPACE ();
326 }
327
328 if (! have_align || *input_line_pointer != '"')
329 {
330 if (! have_align)
331 temp = 0;
332 else
333 {
334 temp = get_absolute_expression ();
335
336 if (temp < 0)
337 {
338 temp = 0;
339 as_warn (_("Common alignment negative; 0 assumed"));
340 }
341 }
342
343 if (symbol_get_obj (symbolP)->local)
344 {
345 segT old_sec;
346 int old_subsec;
347 char *pfrag;
348 int align;
349 flagword applicable;
350
351 old_sec = now_seg;
352 old_subsec = now_subseg;
353
354 applicable = bfd_applicable_section_flags (stdoutput);
355
356 applicable &= SEC_ALLOC;
357
358 switch (area)
359 {
360 case SCOMMON_SECTION:
361 do_v850_seg (SBSS_SECTION, 0);
362 break;
363
364 case ZCOMMON_SECTION:
365 do_v850_seg (ZBSS_SECTION, 0);
366 break;
367
368 case TCOMMON_SECTION:
369 do_v850_seg (TBSS_SECTION, 0);
370 break;
371 }
372
373 if (temp)
374 {
375 /* Convert to a power of 2 alignment. */
376 for (align = 0; (temp & 1) == 0; temp >>= 1, ++align)
377 ;
378
379 if (temp != 1)
380 {
381 as_bad (_("Common alignment not a power of 2"));
382 ignore_rest_of_line ();
383 return;
384 }
385 }
386 else
387 align = 0;
388
389 record_alignment (now_seg, align);
390
391 if (align)
392 frag_align (align, 0, 0);
393
394 switch (area)
395 {
396 case SCOMMON_SECTION:
397 if (S_GET_SEGMENT (symbolP) == v850_seg_table[SBSS_SECTION].s)
398 symbol_get_frag (symbolP)->fr_symbol = 0;
399 break;
400
401 case ZCOMMON_SECTION:
402 if (S_GET_SEGMENT (symbolP) == v850_seg_table[ZBSS_SECTION].s)
403 symbol_get_frag (symbolP)->fr_symbol = 0;
404 break;
405
406 case TCOMMON_SECTION:
407 if (S_GET_SEGMENT (symbolP) == v850_seg_table[TBSS_SECTION].s)
408 symbol_get_frag (symbolP)->fr_symbol = 0;
409 break;
410
411 default:
412 abort ();
413 }
414
415 symbol_set_frag (symbolP, frag_now);
416 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
417 (offsetT) size, (char *) 0);
418 *pfrag = 0;
419 S_SET_SIZE (symbolP, size);
420
421 switch (area)
422 {
423 case SCOMMON_SECTION:
424 S_SET_SEGMENT (symbolP, v850_seg_table[SBSS_SECTION].s);
425 break;
426
427 case ZCOMMON_SECTION:
428 S_SET_SEGMENT (symbolP, v850_seg_table[ZBSS_SECTION].s);
429 break;
430
431 case TCOMMON_SECTION:
432 S_SET_SEGMENT (symbolP, v850_seg_table[TBSS_SECTION].s);
433 break;
434
435 default:
436 abort ();
437 }
438
439 S_CLEAR_EXTERNAL (symbolP);
440 obj_elf_section_change_hook ();
441 subseg_set (old_sec, old_subsec);
442 }
443 else
444 {
445 segT old_sec;
446 int old_subsec;
447
448 allocate_common:
449 old_sec = now_seg;
450 old_subsec = now_subseg;
451
452 S_SET_VALUE (symbolP, (valueT) size);
453 S_SET_ALIGN (symbolP, temp);
454 S_SET_EXTERNAL (symbolP);
455
456 switch (area)
457 {
458 case SCOMMON_SECTION:
459 case ZCOMMON_SECTION:
460 case TCOMMON_SECTION:
461 do_v850_seg (area, 0);
462 S_SET_SEGMENT (symbolP, v850_seg_table[area].s);
463 break;
464
465 default:
466 abort ();
467 }
468
469 obj_elf_section_change_hook ();
470 subseg_set (old_sec, old_subsec);
471 }
472 }
473 else
474 {
475 input_line_pointer++;
476
477 /* @@ Some use the dot, some don't. Can we get some consistency?? */
478 if (*input_line_pointer == '.')
479 input_line_pointer++;
480
481 /* @@ Some say data, some say bss. */
482 if (strncmp (input_line_pointer, "bss\"", 4)
483 && strncmp (input_line_pointer, "data\"", 5))
484 {
485 while (*--input_line_pointer != '"')
486 ;
487 input_line_pointer--;
488 goto bad_common_segment;
489 }
490
491 while (*input_line_pointer++ != '"')
492 ;
493
494 goto allocate_common;
495 }
496
497 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
498
499 demand_empty_rest_of_line ();
500 return;
501
502 {
503 bad_common_segment:
504 p = input_line_pointer;
505 while (*p && *p != '\n')
506 p++;
507 c = *p;
508 *p = '\0';
509 as_bad (_("bad .common segment %s"), input_line_pointer + 1);
510 *p = c;
511 input_line_pointer = p;
512 ignore_rest_of_line ();
513 return;
514 }
515 }
516
517 static void
518 set_machine (int number)
519 {
520 machine = number;
521 bfd_set_arch_mach (stdoutput, v850_target_arch, machine);
522
523 switch (machine)
524 {
525 case 0: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850); break;
526 case bfd_mach_v850: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850); break;
527 case bfd_mach_v850e: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E); break;
528 case bfd_mach_v850e1: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E); break;
529 case bfd_mach_v850e2: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2); break;
530 case bfd_mach_v850e2v3:SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2V3); break;
531 }
532 }
533
534 static void
535 v850_longcode (int type)
536 {
537 expressionS ex;
538
539 if (! v850_relax)
540 {
541 if (type == 1)
542 as_warn (_(".longcall pseudo-op seen when not relaxing"));
543 else
544 as_warn (_(".longjump pseudo-op seen when not relaxing"));
545 }
546
547 expression (&ex);
548
549 if (ex.X_op != O_symbol || ex.X_add_number != 0)
550 {
551 as_bad (_("bad .longcall format"));
552 ignore_rest_of_line ();
553
554 return;
555 }
556
557 if (type == 1)
558 fix_new_exp (frag_now, frag_now_fix (), 4, & ex, 1,
559 BFD_RELOC_V850_LONGCALL);
560 else
561 fix_new_exp (frag_now, frag_now_fix (), 4, & ex, 1,
562 BFD_RELOC_V850_LONGJUMP);
563
564 demand_empty_rest_of_line ();
565 }
566
567 /* The target specific pseudo-ops which we support. */
568 const pseudo_typeS md_pseudo_table[] =
569 {
570 { "sdata", v850_seg, SDATA_SECTION },
571 { "tdata", v850_seg, TDATA_SECTION },
572 { "zdata", v850_seg, ZDATA_SECTION },
573 { "sbss", v850_seg, SBSS_SECTION },
574 { "tbss", v850_seg, TBSS_SECTION },
575 { "zbss", v850_seg, ZBSS_SECTION },
576 { "rosdata", v850_seg, ROSDATA_SECTION },
577 { "rozdata", v850_seg, ROZDATA_SECTION },
578 { "bss", v850_seg, BSS_SECTION },
579 { "offset", v850_offset, 0 },
580 { "word", cons, 4 },
581 { "zcomm", v850_comm, ZCOMMON_SECTION },
582 { "scomm", v850_comm, SCOMMON_SECTION },
583 { "tcomm", v850_comm, TCOMMON_SECTION },
584 { "v850", set_machine, 0 },
585 { "call_table_data", v850_seg, CALL_TABLE_DATA_SECTION },
586 { "call_table_text", v850_seg, CALL_TABLE_TEXT_SECTION },
587 { "v850e", set_machine, bfd_mach_v850e },
588 { "v850e1", set_machine, bfd_mach_v850e1 },
589 { "v850e2", set_machine, bfd_mach_v850e2 },
590 { "v850e2v3", set_machine, bfd_mach_v850e2v3 },
591 { "longcall", v850_longcode, 1 },
592 { "longjump", v850_longcode, 2 },
593 { NULL, NULL, 0 }
594 };
595
596 /* Opcode hash table. */
597 static struct hash_control *v850_hash;
598
599 /* This table is sorted. Suitable for searching by a binary search. */
600 static const struct reg_name pre_defined_registers[] =
601 {
602 { "ep", 30, PROCESSOR_ALL }, /* ep - element ptr. */
603 { "gp", 4, PROCESSOR_ALL }, /* gp - global ptr. */
604 { "hp", 2, PROCESSOR_ALL }, /* hp - handler stack ptr. */
605 { "lp", 31, PROCESSOR_ALL }, /* lp - link ptr. */
606 { "r0", 0, PROCESSOR_ALL },
607 { "r1", 1, PROCESSOR_ALL },
608 { "r10", 10, PROCESSOR_ALL },
609 { "r11", 11, PROCESSOR_ALL },
610 { "r12", 12, PROCESSOR_ALL },
611 { "r13", 13, PROCESSOR_ALL },
612 { "r14", 14, PROCESSOR_ALL },
613 { "r15", 15, PROCESSOR_ALL },
614 { "r16", 16, PROCESSOR_ALL },
615 { "r17", 17, PROCESSOR_ALL },
616 { "r18", 18, PROCESSOR_ALL },
617 { "r19", 19, PROCESSOR_ALL },
618 { "r2", 2, PROCESSOR_ALL },
619 { "r20", 20, PROCESSOR_ALL },
620 { "r21", 21, PROCESSOR_ALL },
621 { "r22", 22, PROCESSOR_ALL },
622 { "r23", 23, PROCESSOR_ALL },
623 { "r24", 24, PROCESSOR_ALL },
624 { "r25", 25, PROCESSOR_ALL },
625 { "r26", 26, PROCESSOR_ALL },
626 { "r27", 27, PROCESSOR_ALL },
627 { "r28", 28, PROCESSOR_ALL },
628 { "r29", 29, PROCESSOR_ALL },
629 { "r3", 3, PROCESSOR_ALL },
630 { "r30", 30, PROCESSOR_ALL },
631 { "r31", 31, PROCESSOR_ALL },
632 { "r4", 4, PROCESSOR_ALL },
633 { "r5", 5, PROCESSOR_ALL },
634 { "r6", 6, PROCESSOR_ALL },
635 { "r7", 7, PROCESSOR_ALL },
636 { "r8", 8, PROCESSOR_ALL },
637 { "r9", 9, PROCESSOR_ALL },
638 { "sp", 3, PROCESSOR_ALL }, /* sp - stack ptr. */
639 { "tp", 5, PROCESSOR_ALL }, /* tp - text ptr. */
640 { "zero", 0, PROCESSOR_ALL },
641 };
642
643 #define REG_NAME_CNT \
644 (sizeof (pre_defined_registers) / sizeof (struct reg_name))
645
646 static const struct reg_name system_registers[] =
647 {
648 { "asid", 23, PROCESSOR_NOT_V850 },
649 { "bpam", 25, PROCESSOR_NOT_V850 },
650 { "bpav", 24, PROCESSOR_NOT_V850 },
651 { "bpc", 22, PROCESSOR_NOT_V850 },
652 { "bpdm", 27, PROCESSOR_NOT_V850 },
653 { "bpdv", 26, PROCESSOR_NOT_V850 },
654 { "bsel", 31, PROCESSOR_V850E2_ALL },
655 { "cfg", 7, PROCESSOR_V850E2V3 },
656 { "ctbp", 20, PROCESSOR_NOT_V850 },
657 { "ctpc", 16, PROCESSOR_NOT_V850 },
658 { "ctpsw", 17, PROCESSOR_NOT_V850 },
659 { "dbic", 15, PROCESSOR_V850E2_ALL },
660 { "dbpc", 18, PROCESSOR_NOT_V850 },
661 { "dbpsw", 19, PROCESSOR_NOT_V850 },
662 { "dbwr", 30, PROCESSOR_V850E2_ALL },
663 { "dir", 21, PROCESSOR_NOT_V850 },
664 { "dpa0l", 16, PROCESSOR_V850E2V3 },
665 { "dpa0u", 17, PROCESSOR_V850E2V3 },
666 { "dpa1l", 18, PROCESSOR_V850E2V3 },
667 { "dpa1u", 19, PROCESSOR_V850E2V3 },
668 { "dpa2l", 20, PROCESSOR_V850E2V3 },
669 { "dpa2u", 21, PROCESSOR_V850E2V3 },
670 { "dpa3l", 22, PROCESSOR_V850E2V3 },
671 { "dpa3u", 23, PROCESSOR_V850E2V3 },
672 { "dpa4l", 24, PROCESSOR_V850E2V3 },
673 { "dpa4u", 25, PROCESSOR_V850E2V3 },
674 { "dpa5l", 26, PROCESSOR_V850E2V3 },
675 { "dpa5u", 27, PROCESSOR_V850E2V3 },
676 { "ecr", 4, PROCESSOR_ALL },
677 { "eh_base", 3, PROCESSOR_V850E2V3 },
678 { "eh_cfg", 1, PROCESSOR_V850E2V3 },
679 { "eh_reset", 2, PROCESSOR_V850E2V3 },
680 { "eiic", 13, PROCESSOR_V850E2_ALL },
681 { "eipc", 0, PROCESSOR_ALL },
682 { "eipsw", 1, PROCESSOR_ALL },
683 { "eiwr", 28, PROCESSOR_V850E2_ALL },
684 { "feic", 14, PROCESSOR_V850E2_ALL },
685 { "fepc", 2, PROCESSOR_ALL },
686 { "fepsw", 3, PROCESSOR_ALL },
687 { "fewr", 29, PROCESSOR_V850E2_ALL },
688 { "fpcc", 9, PROCESSOR_V850E2V3 },
689 { "fpcfg", 10, PROCESSOR_V850E2V3 },
690 { "fpec", 11, PROCESSOR_V850E2V3 },
691 { "fpepc", 7, PROCESSOR_V850E2V3 },
692 { "fpspc", 27, PROCESSOR_V850E2V3 },
693 { "fpsr", 6, PROCESSOR_V850E2V3 },
694 { "fpst", 8, PROCESSOR_V850E2V3 },
695 { "ipa0l", 6, PROCESSOR_V850E2V3 },
696 { "ipa0u", 7, PROCESSOR_V850E2V3 },
697 { "ipa1l", 8, PROCESSOR_V850E2V3 },
698 { "ipa1u", 9, PROCESSOR_V850E2V3 },
699 { "ipa2l", 10, PROCESSOR_V850E2V3 },
700 { "ipa2u", 11, PROCESSOR_V850E2V3 },
701 { "ipa3l", 12, PROCESSOR_V850E2V3 },
702 { "ipa3u", 13, PROCESSOR_V850E2V3 },
703 { "ipa4l", 14, PROCESSOR_V850E2V3 },
704 { "ipa4u", 15, PROCESSOR_V850E2V3 },
705 { "mca", 24, PROCESSOR_V850E2V3 },
706 { "mcc", 26, PROCESSOR_V850E2V3 },
707 { "mcr", 27, PROCESSOR_V850E2V3 },
708 { "mcs", 25, PROCESSOR_V850E2V3 },
709 { "mpc", 1, PROCESSOR_V850E2V3 },
710 { "mpm", 0, PROCESSOR_V850E2V3 },
711 { "mpu10_dpa0l", 16, PROCESSOR_V850E2V3 },
712 { "mpu10_dpa0u", 17, PROCESSOR_V850E2V3 },
713 { "mpu10_dpa1l", 18, PROCESSOR_V850E2V3 },
714 { "mpu10_dpa1u", 19, PROCESSOR_V850E2V3 },
715 { "mpu10_dpa2l", 20, PROCESSOR_V850E2V3 },
716 { "mpu10_dpa2u", 21, PROCESSOR_V850E2V3 },
717 { "mpu10_dpa3l", 22, PROCESSOR_V850E2V3 },
718 { "mpu10_dpa3u", 23, PROCESSOR_V850E2V3 },
719 { "mpu10_dpa4l", 24, PROCESSOR_V850E2V3 },
720 { "mpu10_dpa4u", 25, PROCESSOR_V850E2V3 },
721 { "mpu10_dpa5l", 26, PROCESSOR_V850E2V3 },
722 { "mpu10_dpa5u", 27, PROCESSOR_V850E2V3 },
723 { "mpu10_ipa0l", 6, PROCESSOR_V850E2V3 },
724 { "mpu10_ipa0u", 7, PROCESSOR_V850E2V3 },
725 { "mpu10_ipa1l", 8, PROCESSOR_V850E2V3 },
726 { "mpu10_ipa1u", 9, PROCESSOR_V850E2V3 },
727 { "mpu10_ipa2l", 10, PROCESSOR_V850E2V3 },
728 { "mpu10_ipa2u", 11, PROCESSOR_V850E2V3 },
729 { "mpu10_ipa3l", 12, PROCESSOR_V850E2V3 },
730 { "mpu10_ipa3u", 13, PROCESSOR_V850E2V3 },
731 { "mpu10_ipa4l", 14, PROCESSOR_V850E2V3 },
732 { "mpu10_ipa4u", 15, PROCESSOR_V850E2V3 },
733 { "mpu10_mpc", 1, PROCESSOR_V850E2V3 },
734 { "mpu10_mpm", 0, PROCESSOR_V850E2V3 },
735 { "mpu10_tid", 2, PROCESSOR_V850E2V3 },
736 { "mpu10_vmadr", 5, PROCESSOR_V850E2V3 },
737 { "mpu10_vmecr", 3, PROCESSOR_V850E2V3 },
738 { "mpu10_vmtid", 4, PROCESSOR_V850E2V3 },
739 { "pid", 6, PROCESSOR_V850E2V3 },
740 { "pmcr0", 4, PROCESSOR_V850E2V3 },
741 { "pmis2", 14, PROCESSOR_V850E2V3 },
742 { "psw", 5, PROCESSOR_ALL },
743 { "scbp", 12, PROCESSOR_V850E2V3 },
744 { "sccfg", 11, PROCESSOR_V850E2V3 },
745 { "sr0", 0, PROCESSOR_ALL },
746 { "sr1", 1, PROCESSOR_ALL },
747 { "sr10", 10, PROCESSOR_ALL },
748 { "sr11", 11, PROCESSOR_ALL },
749 { "sr12", 12, PROCESSOR_ALL },
750 { "sr13", 13, PROCESSOR_ALL },
751 { "sr14", 14, PROCESSOR_ALL },
752 { "sr15", 15, PROCESSOR_ALL },
753 { "sr16", 16, PROCESSOR_ALL },
754 { "sr17", 17, PROCESSOR_ALL },
755 { "sr18", 18, PROCESSOR_ALL },
756 { "sr19", 19, PROCESSOR_ALL },
757 { "sr2", 2, PROCESSOR_ALL },
758 { "sr20", 20, PROCESSOR_ALL },
759 { "sr21", 21, PROCESSOR_ALL },
760 { "sr22", 22, PROCESSOR_ALL },
761 { "sr23", 23, PROCESSOR_ALL },
762 { "sr24", 24, PROCESSOR_ALL },
763 { "sr25", 25, PROCESSOR_ALL },
764 { "sr26", 26, PROCESSOR_ALL },
765 { "sr27", 27, PROCESSOR_ALL },
766 { "sr28", 28, PROCESSOR_ALL },
767 { "sr29", 29, PROCESSOR_ALL },
768 { "sr3", 3, PROCESSOR_ALL },
769 { "sr30", 30, PROCESSOR_ALL },
770 { "sr31", 31, PROCESSOR_ALL },
771 { "sr4", 4, PROCESSOR_ALL },
772 { "sr5", 5, PROCESSOR_ALL },
773 { "sr6", 6, PROCESSOR_ALL },
774 { "sr7", 7, PROCESSOR_ALL },
775 { "sr8", 8, PROCESSOR_ALL },
776 { "sr9", 9, PROCESSOR_ALL },
777 { "sw_base", 3, PROCESSOR_V850E2V3 },
778 { "sw_cfg", 1, PROCESSOR_V850E2V3 },
779 { "sw_ctl", 0, PROCESSOR_V850E2V3 },
780 { "tid", 2, PROCESSOR_V850E2V3 },
781 { "vmadr", 6, PROCESSOR_V850E2V3 },
782 { "vmecr", 4, PROCESSOR_V850E2V3 },
783 { "vmtid", 5, PROCESSOR_V850E2V3 },
784 { "vsadr", 2, PROCESSOR_V850E2V3 },
785 { "vsecr", 0, PROCESSOR_V850E2V3 },
786 { "vstid", 1, PROCESSOR_V850E2V3 },
787 };
788
789 #define SYSREG_NAME_CNT \
790 (sizeof (system_registers) / sizeof (struct reg_name))
791
792
793 static const struct reg_name cc_names[] =
794 {
795 { "c", 0x1, PROCESSOR_ALL },
796 { "e", 0x2, PROCESSOR_ALL },
797 { "ge", 0xe, PROCESSOR_ALL },
798 { "gt", 0xf, PROCESSOR_ALL },
799 { "h", 0xb, PROCESSOR_ALL },
800 { "l", 0x1, PROCESSOR_ALL },
801 { "le", 0x7, PROCESSOR_ALL },
802 { "lt", 0x6, PROCESSOR_ALL },
803 { "n", 0x4, PROCESSOR_ALL },
804 { "nc", 0x9, PROCESSOR_ALL },
805 { "ne", 0xa, PROCESSOR_ALL },
806 { "nh", 0x3, PROCESSOR_ALL },
807 { "nl", 0x9, PROCESSOR_ALL },
808 { "ns", 0xc, PROCESSOR_ALL },
809 { "nv", 0x8, PROCESSOR_ALL },
810 { "nz", 0xa, PROCESSOR_ALL },
811 { "p", 0xc, PROCESSOR_ALL },
812 { "s", 0x4, PROCESSOR_ALL },
813 #define COND_SA_NUM 0xd
814 { "sa", COND_SA_NUM, PROCESSOR_ALL },
815 { "t", 0x5, PROCESSOR_ALL },
816 { "v", 0x0, PROCESSOR_ALL },
817 { "z", 0x2, PROCESSOR_ALL },
818 };
819
820 #define CC_NAME_CNT \
821 (sizeof (cc_names) / sizeof (struct reg_name))
822
823 static const struct reg_name float_cc_names[] =
824 {
825 { "eq", 0x2, PROCESSOR_V850E2V3 }, /* true. */
826 { "f", 0x0, PROCESSOR_V850E2V3 }, /* true. */
827 { "ge", 0xd, PROCESSOR_V850E2V3 }, /* false. */
828 { "gl", 0xb, PROCESSOR_V850E2V3 }, /* false. */
829 { "gle", 0x9, PROCESSOR_V850E2V3 }, /* false. */
830 { "gt", 0xf, PROCESSOR_V850E2V3 }, /* false. */
831 { "le", 0xe, PROCESSOR_V850E2V3 }, /* true. */
832 { "lt", 0xc, PROCESSOR_V850E2V3 }, /* true. */
833 { "neq", 0x2, PROCESSOR_V850E2V3 }, /* false. */
834 { "nge", 0xd, PROCESSOR_V850E2V3 }, /* true. */
835 { "ngl", 0xb, PROCESSOR_V850E2V3 }, /* true. */
836 { "ngle",0x9, PROCESSOR_V850E2V3 }, /* true. */
837 { "ngt", 0xf, PROCESSOR_V850E2V3 }, /* true. */
838 { "nle", 0xe, PROCESSOR_V850E2V3 }, /* false. */
839 { "nlt", 0xc, PROCESSOR_V850E2V3 }, /* false. */
840 { "oge", 0x5, PROCESSOR_V850E2V3 }, /* false. */
841 { "ogl", 0x3, PROCESSOR_V850E2V3 }, /* false. */
842 { "ogt", 0x7, PROCESSOR_V850E2V3 }, /* false. */
843 { "ole", 0x6, PROCESSOR_V850E2V3 }, /* true. */
844 { "olt", 0x4, PROCESSOR_V850E2V3 }, /* true. */
845 { "or", 0x1, PROCESSOR_V850E2V3 }, /* false. */
846 { "seq", 0xa, PROCESSOR_V850E2V3 }, /* true. */
847 { "sf", 0x8, PROCESSOR_V850E2V3 }, /* true. */
848 { "sne", 0xa, PROCESSOR_V850E2V3 }, /* false. */
849 { "st", 0x8, PROCESSOR_V850E2V3 }, /* false. */
850 { "t", 0x0, PROCESSOR_V850E2V3 }, /* false. */
851 { "ueq", 0x3, PROCESSOR_V850E2V3 }, /* true. */
852 { "uge", 0x4, PROCESSOR_V850E2V3 }, /* false. */
853 { "ugt", 0x6, PROCESSOR_V850E2V3 }, /* false. */
854 { "ule", 0x7, PROCESSOR_V850E2V3 }, /* true. */
855 { "ult", 0x5, PROCESSOR_V850E2V3 }, /* true. */
856 { "un", 0x1, PROCESSOR_V850E2V3 }, /* true. */
857 };
858
859 #define FLOAT_CC_NAME_CNT \
860 (sizeof (float_cc_names) / sizeof (struct reg_name))
861
862 /* Do a binary search of the given register table to see if NAME is a
863 valid regiter name. Return the register number from the array on
864 success, or -1 on failure. */
865
866 static int
867 reg_name_search (const struct reg_name *regs,
868 int regcount,
869 const char *name,
870 bfd_boolean accept_numbers)
871 {
872 int middle, low, high;
873 int cmp;
874 symbolS *symbolP;
875
876 /* If the register name is a symbol, then evaluate it. */
877 if ((symbolP = symbol_find (name)) != NULL)
878 {
879 /* If the symbol is an alias for another name then use that.
880 If the symbol is an alias for a number, then return the number. */
881 if (symbol_equated_p (symbolP))
882 name
883 = S_GET_NAME (symbol_get_value_expression (symbolP)->X_add_symbol);
884 else if (accept_numbers)
885 {
886 int reg = S_GET_VALUE (symbolP);
887 return reg;
888 }
889
890 /* Otherwise drop through and try parsing name normally. */
891 }
892
893 low = 0;
894 high = regcount - 1;
895
896 do
897 {
898 middle = (low + high) / 2;
899 cmp = strcasecmp (name, regs[middle].name);
900 if (cmp < 0)
901 high = middle - 1;
902 else if (cmp > 0)
903 low = middle + 1;
904 else
905 return ((regs[middle].processors & processor_mask)
906 ? regs[middle].value
907 : -1);
908 }
909 while (low <= high);
910 return -1;
911 }
912
913 /* Summary of register_name().
914
915 in: Input_line_pointer points to 1st char of operand.
916
917 out: An expressionS.
918 The operand may have been a register: in this case, X_op == O_register,
919 X_add_number is set to the register number, and truth is returned.
920 Input_line_pointer->(next non-blank) char after operand, or is in
921 its original state. */
922
923 static bfd_boolean
924 register_name (expressionS *expressionP)
925 {
926 int reg_number;
927 char *name;
928 char *start;
929 char c;
930
931 /* Find the spelling of the operand. */
932 start = name = input_line_pointer;
933
934 c = get_symbol_end ();
935
936 reg_number = reg_name_search (pre_defined_registers, REG_NAME_CNT,
937 name, FALSE);
938
939 /* Put back the delimiting char. */
940 *input_line_pointer = c;
941
942 expressionP->X_add_symbol = NULL;
943 expressionP->X_op_symbol = NULL;
944
945 /* Look to see if it's in the register table. */
946 if (reg_number >= 0)
947 {
948 expressionP->X_op = O_register;
949 expressionP->X_add_number = reg_number;
950
951 return TRUE;
952 }
953
954 /* Reset the line as if we had not done anything. */
955 input_line_pointer = start;
956
957 expressionP->X_op = O_illegal;
958
959 return FALSE;
960 }
961
962 /* Summary of system_register_name().
963
964 in: INPUT_LINE_POINTER points to 1st char of operand.
965 EXPRESSIONP points to an expression structure to be filled in.
966 ACCEPT_NUMBERS is true iff numerical register names may be used.
967
968 out: An expressionS structure in expressionP.
969 The operand may have been a register: in this case, X_op == O_register,
970 X_add_number is set to the register number, and truth is returned.
971 Input_line_pointer->(next non-blank) char after operand, or is in
972 its original state. */
973
974 static bfd_boolean
975 system_register_name (expressionS *expressionP,
976 bfd_boolean accept_numbers)
977 {
978 int reg_number;
979 char *name;
980 char *start;
981 char c;
982
983 /* Find the spelling of the operand. */
984 start = name = input_line_pointer;
985
986 c = get_symbol_end ();
987 reg_number = reg_name_search (system_registers, SYSREG_NAME_CNT, name,
988 accept_numbers);
989
990 /* Put back the delimiting char. */
991 *input_line_pointer = c;
992
993 if (reg_number < 0
994 && accept_numbers)
995 {
996 /* Reset input_line pointer. */
997 input_line_pointer = start;
998
999 if (ISDIGIT (*input_line_pointer))
1000 {
1001 reg_number = strtol (input_line_pointer, &input_line_pointer, 0);
1002 }
1003 }
1004
1005 expressionP->X_add_symbol = NULL;
1006 expressionP->X_op_symbol = NULL;
1007
1008 /* Look to see if it's in the register table. */
1009 if (reg_number >= 0)
1010 {
1011 expressionP->X_op = O_register;
1012 expressionP->X_add_number = reg_number;
1013
1014 return TRUE;
1015 }
1016
1017 /* Reset the line as if we had not done anything. */
1018 input_line_pointer = start;
1019
1020 expressionP->X_op = O_illegal;
1021
1022 return FALSE;
1023 }
1024
1025 /* Summary of cc_name().
1026
1027 in: INPUT_LINE_POINTER points to 1st char of operand.
1028
1029 out: An expressionS.
1030 The operand may have been a register: in this case, X_op == O_register,
1031 X_add_number is set to the register number, and truth is returned.
1032 Input_line_pointer->(next non-blank) char after operand, or is in
1033 its original state. */
1034
1035 static bfd_boolean
1036 cc_name (expressionS *expressionP,
1037 bfd_boolean accept_numbers)
1038 {
1039 int reg_number;
1040 char *name;
1041 char *start;
1042 char c;
1043
1044 /* Find the spelling of the operand. */
1045 start = name = input_line_pointer;
1046
1047 c = get_symbol_end ();
1048 reg_number = reg_name_search (cc_names, CC_NAME_CNT, name, accept_numbers);
1049
1050 /* Put back the delimiting char. */
1051 *input_line_pointer = c;
1052
1053 if (reg_number < 0
1054 && accept_numbers)
1055 {
1056 /* Reset input_line pointer. */
1057 input_line_pointer = start;
1058
1059 if (ISDIGIT (*input_line_pointer))
1060 {
1061 reg_number = strtol (input_line_pointer, &input_line_pointer, 0);
1062 }
1063 }
1064
1065 expressionP->X_add_symbol = NULL;
1066 expressionP->X_op_symbol = NULL;
1067
1068 /* Look to see if it's in the register table. */
1069 if (reg_number >= 0)
1070 {
1071 expressionP->X_op = O_constant;
1072 expressionP->X_add_number = reg_number;
1073
1074 return TRUE;
1075 }
1076
1077 /* Reset the line as if we had not done anything. */
1078 input_line_pointer = start;
1079
1080 expressionP->X_op = O_illegal;
1081 expressionP->X_add_number = 0;
1082
1083 return FALSE;
1084 }
1085
1086 static bfd_boolean
1087 float_cc_name (expressionS *expressionP,
1088 bfd_boolean accept_numbers)
1089 {
1090 int reg_number;
1091 char *name;
1092 char *start;
1093 char c;
1094
1095 /* Find the spelling of the operand. */
1096 start = name = input_line_pointer;
1097
1098 c = get_symbol_end ();
1099 reg_number = reg_name_search (float_cc_names, FLOAT_CC_NAME_CNT, name, accept_numbers);
1100
1101 /* Put back the delimiting char. */
1102 *input_line_pointer = c;
1103
1104 if (reg_number < 0
1105 && accept_numbers)
1106 {
1107 /* Reset input_line pointer. */
1108 input_line_pointer = start;
1109
1110 if (ISDIGIT (*input_line_pointer))
1111 {
1112 reg_number = strtol (input_line_pointer, &input_line_pointer, 0);
1113 }
1114 }
1115
1116 expressionP->X_add_symbol = NULL;
1117 expressionP->X_op_symbol = NULL;
1118
1119 /* Look to see if it's in the register table. */
1120 if (reg_number >= 0)
1121 {
1122 expressionP->X_op = O_constant;
1123 expressionP->X_add_number = reg_number;
1124
1125 return TRUE;
1126 }
1127
1128 /* Reset the line as if we had not done anything. */
1129 input_line_pointer = start;
1130
1131 expressionP->X_op = O_illegal;
1132 expressionP->X_add_number = 0;
1133
1134 return FALSE;
1135 }
1136
1137 static void
1138 skip_white_space (void)
1139 {
1140 while (*input_line_pointer == ' '
1141 || *input_line_pointer == '\t')
1142 ++input_line_pointer;
1143 }
1144
1145 /* Summary of parse_register_list ().
1146
1147 in: INPUT_LINE_POINTER points to 1st char of a list of registers.
1148 INSN is the partially constructed instruction.
1149 OPERAND is the operand being inserted.
1150
1151 out: NULL if the parse completed successfully, otherwise a
1152 pointer to an error message is returned. If the parse
1153 completes the correct bit fields in the instruction
1154 will be filled in.
1155
1156 Parses register lists with the syntax:
1157
1158 { rX }
1159 { rX, rY }
1160 { rX - rY }
1161 { rX - rY, rZ }
1162 etc
1163
1164 and also parses constant expressions whoes bits indicate the
1165 registers in the lists. The LSB in the expression refers to
1166 the lowest numbered permissible register in the register list,
1167 and so on upwards. System registers are considered to be very
1168 high numbers. */
1169
1170 static char *
1171 parse_register_list (unsigned long *insn,
1172 const struct v850_operand *operand)
1173 {
1174 static int type1_regs[32] =
1175 {
1176 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1177 0, 0, 0, 0, 0, 31, 29, 28, 23, 22, 21, 20, 27, 26, 25, 24
1178 };
1179
1180 int *regs;
1181 expressionS exp;
1182
1183 /* Select a register array to parse. */
1184 switch (operand->shift)
1185 {
1186 case 0xffe00001: regs = type1_regs; break;
1187 default:
1188 as_bad (_("unknown operand shift: %x\n"), operand->shift);
1189 return _("internal failure in parse_register_list");
1190 }
1191
1192 skip_white_space ();
1193
1194 /* If the expression starts with a curly brace it is a register list.
1195 Otherwise it is a constant expression, whoes bits indicate which
1196 registers are to be included in the list. */
1197 if (*input_line_pointer != '{')
1198 {
1199 int reg;
1200 int i;
1201
1202 expression (&exp);
1203
1204 if (exp.X_op != O_constant)
1205 return _("constant expression or register list expected");
1206
1207 if (regs == type1_regs)
1208 {
1209 if (exp.X_add_number & 0xFFFFF000)
1210 return _("high bits set in register list expression");
1211
1212 for (reg = 20; reg < 32; reg++)
1213 if (exp.X_add_number & (1 << (reg - 20)))
1214 {
1215 for (i = 0; i < 32; i++)
1216 if (regs[i] == reg)
1217 *insn |= (1 << i);
1218 }
1219 }
1220
1221 return NULL;
1222 }
1223
1224 input_line_pointer++;
1225
1226 /* Parse the register list until a terminator (closing curly brace or
1227 new-line) is found. */
1228 for (;;)
1229 {
1230 skip_white_space ();
1231
1232 if (register_name (&exp))
1233 {
1234 int i;
1235
1236 /* Locate the given register in the list, and if it is there,
1237 insert the corresponding bit into the instruction. */
1238 for (i = 0; i < 32; i++)
1239 {
1240 if (regs[i] == exp.X_add_number)
1241 {
1242 *insn |= (1 << i);
1243 break;
1244 }
1245 }
1246
1247 if (i == 32)
1248 return _("illegal register included in list");
1249 }
1250 else if (system_register_name (&exp, TRUE))
1251 {
1252 if (regs == type1_regs)
1253 {
1254 return _("system registers cannot be included in list");
1255 }
1256 }
1257
1258 if (*input_line_pointer == '}')
1259 {
1260 input_line_pointer++;
1261 break;
1262 }
1263 else if (*input_line_pointer == ',')
1264 {
1265 input_line_pointer++;
1266 continue;
1267 }
1268 else if (*input_line_pointer == '-')
1269 {
1270 /* We have encountered a range of registers: rX - rY. */
1271 int j;
1272 expressionS exp2;
1273
1274 /* Skip the dash. */
1275 ++input_line_pointer;
1276
1277 /* Get the second register in the range. */
1278 if (! register_name (&exp2))
1279 {
1280 return _("second register should follow dash in register list");
1281 }
1282
1283 if (exp.X_add_number > exp2.X_add_number)
1284 {
1285 return _("second register should be greater than first register");
1286 }
1287
1288 /* Add the rest of the registers in the range. */
1289 for (j = exp.X_add_number + 1; j <= exp2.X_add_number; j++)
1290 {
1291 int i;
1292
1293 /* Locate the given register in the list, and if it is there,
1294 insert the corresponding bit into the instruction. */
1295 for (i = 0; i < 32; i++)
1296 {
1297 if (regs[i] == j)
1298 {
1299 *insn |= (1 << i);
1300 break;
1301 }
1302 }
1303
1304 if (i == 32)
1305 return _("illegal register included in list");
1306 }
1307
1308 exp = exp2;
1309 }
1310 else
1311 break;
1312 }
1313
1314 return NULL;
1315 }
1316
1317 const char *md_shortopts = "m:";
1318
1319 struct option md_longopts[] =
1320 {
1321 #define OPTION_DISP_SIZE_DEFAULT_22 (OPTION_MD_BASE)
1322 {"disp-size-default-22", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_22},
1323 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 1)
1324 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
1325 {NULL, no_argument, NULL, 0}
1326 };
1327
1328 size_t md_longopts_size = sizeof (md_longopts);
1329
1330 void
1331 md_show_usage (FILE *stream)
1332 {
1333 fprintf (stream, _(" V850 options:\n"));
1334 fprintf (stream, _(" -mwarn-signed-overflow Warn if signed immediate values overflow\n"));
1335 fprintf (stream, _(" -mwarn-unsigned-overflow Warn if unsigned immediate values overflow\n"));
1336 fprintf (stream, _(" -mv850 The code is targeted at the v850\n"));
1337 fprintf (stream, _(" -mv850e The code is targeted at the v850e\n"));
1338 fprintf (stream, _(" -mv850e1 The code is targeted at the v850e1\n"));
1339 fprintf (stream, _(" -mv850e2 The code is targeted at the v850e2\n"));
1340 fprintf (stream, _(" -mv850e2v3 The code is targeted at the v850e2v3\n"));
1341 fprintf (stream, _(" -mrelax Enable relaxation\n"));
1342 fprintf (stream, _(" --disp-size-default-22 branch displacement with unknown size is 22 bits (default)\n"));
1343 fprintf (stream, _(" --disp-size-default-32 branch displacement with unknown size is 32 bits\n"));
1344 fprintf (stream, _(" -mextension enable extension opcode support\n"));
1345 fprintf (stream, _(" -mno-bcond17 disable b<cond> disp17 instruction\n"));
1346 fprintf (stream, _(" -mno-stld23 disable st/ld offset23 instruction\n"));
1347 fprintf (stream, _(" -mgcc-abi Mark the binary as using the old GCC ABI\n"));
1348 fprintf (stream, _(" -mrh850-abi Mark the binary as using the RH850 ABI (default)\n"));
1349 fprintf (stream, _(" -m8byte-align Mark the binary as using 64-bit alignment\n"));
1350 fprintf (stream, _(" -m4byte-align Mark the binary as using 32-bit alignment (default)\n"));
1351 }
1352
1353 int
1354 md_parse_option (int c, char *arg)
1355 {
1356 if (c != 'm')
1357 {
1358 switch (c)
1359 {
1360 case OPTION_DISP_SIZE_DEFAULT_22:
1361 default_disp_size = 22;
1362 return 1;
1363
1364 case OPTION_DISP_SIZE_DEFAULT_32:
1365 default_disp_size = 32;
1366 return 1;
1367 }
1368 return 0;
1369 }
1370
1371 if (strcmp (arg, "warn-signed-overflow") == 0)
1372 warn_signed_overflows = TRUE;
1373
1374 else if (strcmp (arg, "warn-unsigned-overflow") == 0)
1375 warn_unsigned_overflows = TRUE;
1376
1377 else if (strcmp (arg, "v850") == 0)
1378 {
1379 machine = 0;
1380 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850);
1381 }
1382 else if (strcmp (arg, "v850e") == 0)
1383 {
1384 machine = bfd_mach_v850e;
1385 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E);
1386 }
1387 else if (strcmp (arg, "v850e1") == 0)
1388 {
1389 machine = bfd_mach_v850e1;
1390 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E1);
1391 }
1392 else if (strcmp (arg, "v850e2") == 0)
1393 {
1394 machine = bfd_mach_v850e2;
1395 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2);
1396 }
1397 else if (strcmp (arg, "v850e2v3") == 0)
1398 {
1399 machine = bfd_mach_v850e2v3;
1400 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2V3);
1401 }
1402 else if (strcmp (arg, "extension") == 0)
1403 {
1404 processor_mask |= PROCESSOR_OPTION_EXTENSION | PROCESSOR_OPTION_ALIAS;
1405 }
1406 else if (strcmp (arg, "no-bcond17") == 0)
1407 {
1408 no_bcond17 = 1;
1409 }
1410 else if (strcmp (arg, "no-stld23") == 0)
1411 {
1412 no_stld23 = 1;
1413 }
1414 else if (strcmp (arg, "relax") == 0)
1415 v850_relax = 1;
1416 else if (strcmp (arg, "gcc-abi") == 0)
1417 {
1418 v850_target_arch = bfd_arch_v850;
1419 v850_target_format = "elf32-v850";
1420 }
1421 else if (strcmp (arg, "rh850-abi") == 0)
1422 {
1423 v850_target_arch = bfd_arch_v850_rh850;
1424 v850_target_format = "elf32-v850-rh850";
1425 }
1426 else if (strcmp (arg, "8byte-align") == 0)
1427 v850_e_flags |= EF_RH850_DATA_ALIGN8;
1428 else if (strcmp (arg, "4byte-align") == 0)
1429 v850_e_flags &= ~ EF_RH850_DATA_ALIGN8;
1430 else
1431 return 0;
1432
1433 return 1;
1434 }
1435
1436 symbolS *
1437 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
1438 {
1439 return 0;
1440 }
1441
1442 char *
1443 md_atof (int type, char *litp, int *sizep)
1444 {
1445 return ieee_md_atof (type, litp, sizep, FALSE);
1446 }
1447
1448 /* Very gross. */
1449
1450 void
1451 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
1452 asection *sec,
1453 fragS *fragP)
1454 {
1455 union u
1456 {
1457 bfd_reloc_code_real_type fx_r_type;
1458 char * fr_opcode;
1459 }
1460 opcode_converter;
1461 subseg_change (sec, 0);
1462
1463 opcode_converter.fr_opcode = fragP->fr_opcode;
1464
1465 subseg_change (sec, 0);
1466
1467 /* In range conditional or unconditional branch. */
1468 if (fragP->fr_subtype == SUBYPTE_COND_9_22
1469 || fragP->fr_subtype == SUBYPTE_UNCOND_9_22
1470 || fragP->fr_subtype == SUBYPTE_COND_9_22_32
1471 || fragP->fr_subtype == SUBYPTE_UNCOND_9_22_32
1472 || fragP->fr_subtype == SUBYPTE_COND_9_17_22
1473 || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32
1474 || fragP->fr_subtype == SUBYPTE_SA_9_22
1475 || fragP->fr_subtype == SUBYPTE_SA_9_22_32
1476 || fragP->fr_subtype == SUBYPTE_SA_9_17_22
1477 || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32)
1478
1479 {
1480 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
1481 fragP->fr_offset, 1,
1482 BFD_RELOC_UNUSED + opcode_converter.fx_r_type);
1483 fragP->fr_fix += 2;
1484 }
1485 /* V850e2r-v3 17bit conditional branch. */
1486 else if (fragP->fr_subtype == SUBYPTE_COND_9_17_22 + 1
1487 || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32 + 1
1488 || fragP->fr_subtype == SUBYPTE_SA_9_17_22 + 1
1489 || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32 + 1)
1490 {
1491 unsigned char *buffer =
1492 (unsigned char *) (fragP->fr_fix + fragP->fr_literal);
1493
1494 buffer[0] &= 0x0f; /* Use condition. */
1495 buffer[0] |= 0xe0;
1496 buffer[1] = 0x07;
1497
1498 /* Now create the unconditional branch + fixup to the final
1499 target. */
1500 md_number_to_chars ((char *) buffer + 2, 0x0001, 2);
1501 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
1502 fragP->fr_offset, 1, BFD_RELOC_V850_17_PCREL);
1503 fragP->fr_fix += 4;
1504 }
1505 /* Out of range conditional branch. Emit a branch around a 22bit jump. */
1506 else if (fragP->fr_subtype == SUBYPTE_COND_9_22 + 1
1507 || fragP->fr_subtype == SUBYPTE_COND_9_22_32 + 1
1508 || fragP->fr_subtype == SUBYPTE_COND_9_17_22 + 2
1509 || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32 + 2)
1510 {
1511 unsigned char *buffer =
1512 (unsigned char *) (fragP->fr_fix + fragP->fr_literal);
1513
1514 /* Reverse the condition of the first branch. */
1515 buffer[0] ^= 0x08;
1516 /* Mask off all the displacement bits. */
1517 buffer[0] &= 0x8f;
1518 buffer[1] &= 0x07;
1519 /* Now set the displacement bits so that we branch
1520 around the unconditional branch. */
1521 buffer[0] |= 0x30;
1522
1523 /* Now create the unconditional branch + fixup to the final
1524 target. */
1525 md_number_to_chars ((char *) buffer + 2, 0x00000780, 4);
1526 fix_new (fragP, fragP->fr_fix + 2, 4, fragP->fr_symbol,
1527 fragP->fr_offset, 1, BFD_RELOC_V850_22_PCREL);
1528 fragP->fr_fix += 6;
1529 }
1530 /* Out of range conditional branch. Emit a branch around a 32bit jump. */
1531 else if (fragP->fr_subtype == SUBYPTE_COND_9_22_32 + 2
1532 || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32 + 3)
1533 {
1534 unsigned char *buffer =
1535 (unsigned char *) (fragP->fr_fix + fragP->fr_literal);
1536
1537 /* Reverse the condition of the first branch. */
1538 buffer[0] ^= 0x08;
1539 /* Mask off all the displacement bits. */
1540 buffer[0] &= 0x8f;
1541 buffer[1] &= 0x07;
1542 /* Now set the displacement bits so that we branch
1543 around the unconditional branch. */
1544 buffer[0] |= 0x40;
1545
1546 /* Now create the unconditional branch + fixup to the final
1547 target. */
1548 md_number_to_chars ((char *) buffer + 2, 0x02e0, 2);
1549 fix_new (fragP, fragP->fr_fix + 4, 4, fragP->fr_symbol,
1550 fragP->fr_offset + 2, 1, BFD_RELOC_V850_32_PCREL);
1551 fragP->fr_fix += 8;
1552 }
1553 /* Out of range unconditional branch. Emit a 22bit jump. */
1554 else if (fragP->fr_subtype == SUBYPTE_UNCOND_9_22 + 1
1555 || fragP->fr_subtype == SUBYPTE_UNCOND_9_22_32 + 1)
1556 {
1557 md_number_to_chars (fragP->fr_fix + fragP->fr_literal, 0x00000780, 4);
1558 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
1559 fragP->fr_offset, 1, BFD_RELOC_V850_22_PCREL);
1560 fragP->fr_fix += 4;
1561 }
1562 /* Out of range unconditional branch. Emit a 32bit jump. */
1563 else if (fragP->fr_subtype == SUBYPTE_UNCOND_9_22_32 + 2)
1564 {
1565 md_number_to_chars (fragP->fr_fix + fragP->fr_literal, 0x02e0, 2);
1566 fix_new (fragP, fragP->fr_fix + 4, 4, fragP->fr_symbol,
1567 fragP->fr_offset + 2, 1, BFD_RELOC_V850_32_PCREL);
1568 fragP->fr_fix += 6;
1569 }
1570 /* Out of range SA conditional branch. Emit a branch to a 22bit jump. */
1571 else if (fragP->fr_subtype == SUBYPTE_SA_9_22 + 1
1572 || fragP->fr_subtype == SUBYPTE_SA_9_22_32 + 1
1573 || fragP->fr_subtype == SUBYPTE_SA_9_17_22 + 2
1574 || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32 + 2)
1575 {
1576 unsigned char *buffer =
1577 (unsigned char *) (fragP->fr_fix + fragP->fr_literal);
1578
1579 /* bsa .+4 */
1580 buffer[0] &= 0x8f;
1581 buffer[0] |= 0x20;
1582 buffer[1] &= 0x07;
1583
1584 /* br .+6 */
1585 md_number_to_chars ((char *) buffer + 2, 0x05b5, 2);
1586
1587 /* Now create the unconditional branch + fixup to the final
1588 target. */
1589 /* jr SYM */
1590 md_number_to_chars ((char *) buffer + 4, 0x00000780, 4);
1591 fix_new (fragP, fragP->fr_fix + 4, 4, fragP->fr_symbol,
1592 fragP->fr_offset, 1,
1593 BFD_RELOC_V850_22_PCREL);
1594 fragP->fr_fix += 8;
1595 }
1596 /* Out of range SA conditional branch. Emit a branch around a 32bit jump. */
1597 else if (fragP->fr_subtype == SUBYPTE_SA_9_22_32 + 2
1598 || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32 + 3)
1599 {
1600 unsigned char *buffer =
1601 (unsigned char *) (fragP->fr_fix + fragP->fr_literal);
1602
1603 /* bsa .+2 */
1604 buffer[0] &= 0x8f;
1605 buffer[0] |= 0x20;
1606 buffer[1] &= 0x07;
1607
1608 /* br .+8 */
1609 md_number_to_chars ((char *) buffer + 2, 0x05c5, 2);
1610
1611 /* Now create the unconditional branch + fixup to the final
1612 target. */
1613 /* jr SYM */
1614 md_number_to_chars ((char *) buffer + 4, 0x02e0, 2);
1615 fix_new (fragP, fragP->fr_fix + 6, 4, fragP->fr_symbol,
1616 fragP->fr_offset + 2, 1, BFD_RELOC_V850_32_PCREL);
1617
1618 fragP->fr_fix += 10;
1619 }
1620 else
1621 abort ();
1622 }
1623
1624 valueT
1625 md_section_align (asection *seg, valueT addr)
1626 {
1627 int align = bfd_get_section_alignment (stdoutput, seg);
1628 return ((addr + (1 << align) - 1) & (-1 << align));
1629 }
1630
1631 void
1632 md_begin (void)
1633 {
1634 char *prev_name = "";
1635 const struct v850_opcode *op;
1636
1637 if (strncmp (TARGET_CPU, "v850e2v3", 8) == 0)
1638 {
1639 if (machine == -1)
1640 machine = bfd_mach_v850e2v3;
1641
1642 if (!processor_mask)
1643 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2V3);
1644 }
1645 else if (strncmp (TARGET_CPU, "v850e2", 6) == 0)
1646 {
1647 if (machine == -1)
1648 machine = bfd_mach_v850e2;
1649
1650 if (!processor_mask)
1651 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2);
1652 }
1653 else if (strncmp (TARGET_CPU, "v850e1", 6) == 0)
1654 {
1655 if (machine == -1)
1656 machine = bfd_mach_v850e1;
1657
1658 if (!processor_mask)
1659 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E1);
1660 }
1661 else if (strncmp (TARGET_CPU, "v850e", 5) == 0)
1662 {
1663 if (machine == -1)
1664 machine = bfd_mach_v850e;
1665
1666 if (!processor_mask)
1667 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E);
1668 }
1669 else if (strncmp (TARGET_CPU, "v850", 4) == 0)
1670 {
1671 if (machine == -1)
1672 machine = 0;
1673
1674 if (!processor_mask)
1675 SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850);
1676 }
1677 else
1678 /* xgettext:c-format */
1679 as_bad (_("Unable to determine default target processor from string: %s"),
1680 TARGET_CPU);
1681
1682 v850_hash = hash_new ();
1683
1684 /* Insert unique names into hash table. The V850 instruction set
1685 has many identical opcode names that have different opcodes based
1686 on the operands. This hash table then provides a quick index to
1687 the first opcode with a particular name in the opcode table. */
1688 op = v850_opcodes;
1689 while (op->name)
1690 {
1691 if (strcmp (prev_name, op->name))
1692 {
1693 prev_name = (char *) op->name;
1694 hash_insert (v850_hash, op->name, (char *) op);
1695 }
1696 op++;
1697 }
1698
1699 v850_seg_table[BSS_SECTION].s = bss_section;
1700 bfd_set_arch_mach (stdoutput, v850_target_arch, machine);
1701 bfd_set_private_flags (stdoutput, v850_e_flags);
1702 }
1703
1704
1705 static bfd_reloc_code_real_type
1706 handle_hi016 (const struct v850_operand *operand, const char **errmsg)
1707 {
1708 if (operand == NULL)
1709 return BFD_RELOC_HI16;
1710
1711 if (operand->default_reloc == BFD_RELOC_HI16)
1712 return BFD_RELOC_HI16;
1713
1714 if (operand->default_reloc == BFD_RELOC_HI16_S)
1715 return BFD_RELOC_HI16;
1716
1717 if (operand->default_reloc == BFD_RELOC_16)
1718 return BFD_RELOC_HI16;
1719
1720 *errmsg = _("hi0() relocation used on an instruction which does "
1721 "not support it");
1722 return BFD_RELOC_64; /* Used to indicate an error condition. */
1723 }
1724
1725 static bfd_reloc_code_real_type
1726 handle_hi16 (const struct v850_operand *operand, const char **errmsg)
1727 {
1728 if (operand == NULL)
1729 return BFD_RELOC_HI16_S;
1730
1731 if (operand->default_reloc == BFD_RELOC_HI16_S)
1732 return BFD_RELOC_HI16_S;
1733
1734 if (operand->default_reloc == BFD_RELOC_HI16)
1735 return BFD_RELOC_HI16_S;
1736
1737 if (operand->default_reloc == BFD_RELOC_16)
1738 return BFD_RELOC_HI16_S;
1739
1740 *errmsg = _("hi() relocation used on an instruction which does "
1741 "not support it");
1742 return BFD_RELOC_64; /* Used to indicate an error condition. */
1743 }
1744
1745 static bfd_reloc_code_real_type
1746 handle_lo16 (const struct v850_operand *operand, const char **errmsg)
1747 {
1748 if (operand == NULL)
1749 return BFD_RELOC_LO16;
1750
1751 if (operand->default_reloc == BFD_RELOC_LO16)
1752 return BFD_RELOC_LO16;
1753
1754 if (operand->default_reloc == BFD_RELOC_V850_16_SPLIT_OFFSET)
1755 return BFD_RELOC_V850_LO16_SPLIT_OFFSET;
1756
1757 if (operand->default_reloc == BFD_RELOC_V850_16_S1)
1758 return BFD_RELOC_V850_LO16_S1;
1759
1760 if (operand->default_reloc == BFD_RELOC_16)
1761 return BFD_RELOC_LO16;
1762
1763 *errmsg = _("lo() relocation used on an instruction which does "
1764 "not support it");
1765 return BFD_RELOC_64; /* Used to indicate an error condition. */
1766 }
1767
1768 static bfd_reloc_code_real_type
1769 handle_ctoff (const struct v850_operand *operand, const char **errmsg)
1770 {
1771 if (operand == NULL)
1772 return BFD_RELOC_V850_CALLT_16_16_OFFSET;
1773
1774 if (operand->default_reloc == BFD_RELOC_V850_CALLT_6_7_OFFSET)
1775 return operand->default_reloc;
1776
1777 if (operand->default_reloc == BFD_RELOC_V850_16_S1)
1778 return BFD_RELOC_V850_CALLT_15_16_OFFSET;
1779
1780 if (operand->default_reloc == BFD_RELOC_16)
1781 return BFD_RELOC_V850_CALLT_16_16_OFFSET;
1782
1783 *errmsg = _("ctoff() relocation used on an instruction which does not support it");
1784 return BFD_RELOC_64; /* Used to indicate an error condition. */
1785 }
1786
1787 static bfd_reloc_code_real_type
1788 handle_sdaoff (const struct v850_operand *operand, const char **errmsg)
1789 {
1790 if (operand == NULL)
1791 return BFD_RELOC_V850_SDA_16_16_OFFSET;
1792
1793 if (operand->default_reloc == BFD_RELOC_V850_16_SPLIT_OFFSET)
1794 return BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET;
1795
1796 if (operand->default_reloc == BFD_RELOC_16)
1797 return BFD_RELOC_V850_SDA_16_16_OFFSET;
1798
1799 if (operand->default_reloc == BFD_RELOC_V850_16_S1)
1800 return BFD_RELOC_V850_SDA_15_16_OFFSET;
1801
1802 *errmsg = _("sdaoff() relocation used on an instruction which does not support it");
1803 return BFD_RELOC_64; /* Used to indicate an error condition. */
1804 }
1805
1806 static bfd_reloc_code_real_type
1807 handle_zdaoff (const struct v850_operand *operand, const char **errmsg)
1808 {
1809 if (operand == NULL)
1810 return BFD_RELOC_V850_ZDA_16_16_OFFSET;
1811
1812 if (operand->default_reloc == BFD_RELOC_V850_16_SPLIT_OFFSET)
1813 return BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET;
1814
1815 if (operand->default_reloc == BFD_RELOC_16)
1816 return BFD_RELOC_V850_ZDA_16_16_OFFSET;
1817
1818 if (operand->default_reloc == BFD_RELOC_V850_16_S1)
1819 return BFD_RELOC_V850_ZDA_15_16_OFFSET;
1820
1821 *errmsg = _("zdaoff() relocation used on an instruction which does not support it");
1822 return BFD_RELOC_64; /* Used to indicate an error condition. */
1823 }
1824
1825 static bfd_reloc_code_real_type
1826 handle_tdaoff (const struct v850_operand *operand, const char **errmsg)
1827 {
1828 if (operand == NULL)
1829 /* Data item, not an instruction. */
1830 return BFD_RELOC_V850_TDA_16_16_OFFSET;
1831
1832 switch (operand->default_reloc)
1833 {
1834 /* sld.hu, operand: D5-4. */
1835 case BFD_RELOC_V850_TDA_4_5_OFFSET:
1836 /* sld.bu, operand: D4. */
1837 case BFD_RELOC_V850_TDA_4_4_OFFSET:
1838 /* sld.w/sst.w, operand: D8_6. */
1839 case BFD_RELOC_V850_TDA_6_8_OFFSET:
1840 /* sld.h/sst.h, operand: D8_7. */
1841 case BFD_RELOC_V850_TDA_7_8_OFFSET:
1842 /* sld.b/sst.b, operand: D7. */
1843 case BFD_RELOC_V850_TDA_7_7_OFFSET:
1844 return operand->default_reloc;
1845 default:
1846 break;
1847 }
1848
1849 if (operand->default_reloc == BFD_RELOC_16 && operand->shift == 16)
1850 /* set1 & chums, operands: D16. */
1851 return BFD_RELOC_V850_TDA_16_16_OFFSET;
1852
1853 *errmsg = _("tdaoff() relocation used on an instruction which does not support it");
1854 /* Used to indicate an error condition. */
1855 return BFD_RELOC_64;
1856 }
1857
1858 /* Warning: The code in this function relies upon the definitions
1859 in the v850_operands[] array (defined in opcodes/v850-opc.c)
1860 matching the hard coded values contained herein. */
1861
1862 static bfd_reloc_code_real_type
1863 v850_reloc_prefix (const struct v850_operand *operand, const char **errmsg)
1864 {
1865 bfd_boolean paren_skipped = FALSE;
1866
1867 /* Skip leading opening parenthesis. */
1868 if (*input_line_pointer == '(')
1869 {
1870 ++input_line_pointer;
1871 paren_skipped = TRUE;
1872 }
1873
1874 #define CHECK_(name, reloc) \
1875 if (strncmp (input_line_pointer, name "(", strlen (name) + 1) == 0) \
1876 { \
1877 input_line_pointer += strlen (name); \
1878 return reloc; \
1879 }
1880
1881 CHECK_ ("hi0", handle_hi016(operand, errmsg) );
1882 CHECK_ ("hi", handle_hi16(operand, errmsg) );
1883 CHECK_ ("lo", handle_lo16 (operand, errmsg) );
1884 CHECK_ ("sdaoff", handle_sdaoff (operand, errmsg));
1885 CHECK_ ("zdaoff", handle_zdaoff (operand, errmsg));
1886 CHECK_ ("tdaoff", handle_tdaoff (operand, errmsg));
1887 CHECK_ ("hilo", BFD_RELOC_32);
1888 CHECK_ ("lo23", BFD_RELOC_V850_23);
1889 CHECK_ ("ctoff", handle_ctoff (operand, errmsg) );
1890
1891 /* Restore skipped parenthesis. */
1892 if (paren_skipped)
1893 --input_line_pointer;
1894
1895 return BFD_RELOC_UNUSED;
1896 }
1897
1898 /* Insert an operand value into an instruction. */
1899
1900 static unsigned long
1901 v850_insert_operand (unsigned long insn,
1902 const struct v850_operand *operand,
1903 offsetT val,
1904 const char **errmsg)
1905 {
1906 if (operand->insert)
1907 {
1908 const char *message = NULL;
1909
1910 insn = operand->insert (insn, val, &message);
1911 if (message != NULL)
1912 {
1913 if ((operand->flags & V850_OPERAND_SIGNED)
1914 && ! warn_signed_overflows
1915 && v850_msg_is_out_of_range (message))
1916 {
1917 /* Skip warning... */
1918 }
1919 else if ((operand->flags & V850_OPERAND_SIGNED) == 0
1920 && ! warn_unsigned_overflows
1921 && v850_msg_is_out_of_range (message))
1922 {
1923 /* Skip warning... */
1924 }
1925 else
1926 {
1927 if (errmsg != NULL)
1928 *errmsg = message;
1929 }
1930 }
1931 }
1932 else if (operand->bits == -1
1933 || operand->flags & V850E_IMMEDIATE16
1934 || operand->flags & V850E_IMMEDIATE23
1935 || operand->flags & V850E_IMMEDIATE32)
1936 {
1937 abort ();
1938 }
1939 else
1940 {
1941 if (operand->bits < 32)
1942 {
1943 long min, max;
1944
1945 if ((operand->flags & V850_OPERAND_SIGNED) != 0)
1946 {
1947 if (! warn_signed_overflows)
1948 max = (1 << operand->bits) - 1;
1949 else
1950 max = (1 << (operand->bits - 1)) - 1;
1951
1952 min = -(1 << (operand->bits - 1));
1953 }
1954 else
1955 {
1956 max = (1 << operand->bits) - 1;
1957
1958 if (! warn_unsigned_overflows)
1959 min = -(1 << (operand->bits - 1));
1960 else
1961 min = 0;
1962 }
1963
1964 /* Some people write constants with the sign extension done by
1965 hand but only up to 32 bits. This shouldn't really be valid,
1966 but, to permit this code to assemble on a 64-bit host, we
1967 sign extend the 32-bit value to 64 bits if so doing makes the
1968 value valid. */
1969 if (val > max
1970 && (offsetT) (val - 0x80000000 - 0x80000000) >= min
1971 && (offsetT) (val - 0x80000000 - 0x80000000) <= max)
1972 val = val - 0x80000000 - 0x80000000;
1973
1974 /* Similarly, people write expressions like ~(1<<15), and expect
1975 this to be OK for a 32-bit unsigned value. */
1976 else if (val < min
1977 && (offsetT) (val + 0x80000000 + 0x80000000) >= min
1978 && (offsetT) (val + 0x80000000 + 0x80000000) <= max)
1979 val = val + 0x80000000 + 0x80000000;
1980
1981 else if (val < (offsetT) min || val > (offsetT) max)
1982 {
1983 static char buf [128];
1984
1985 /* Restore min and mix to expected values for decimal ranges. */
1986 if ((operand->flags & V850_OPERAND_SIGNED)
1987 && ! warn_signed_overflows)
1988 max = (1 << (operand->bits - 1)) - 1;
1989
1990 if (! (operand->flags & V850_OPERAND_SIGNED)
1991 && ! warn_unsigned_overflows)
1992 min = 0;
1993
1994 sprintf (buf, _("operand out of range (%d is not between %d and %d)"),
1995 (int) val, (int) min, (int) max);
1996 *errmsg = buf;
1997 }
1998
1999 insn |= (((long) val & ((1 << operand->bits) - 1)) << operand->shift);
2000 }
2001 else
2002 {
2003 insn |= (((long) val) << operand->shift);
2004 }
2005 }
2006
2007 return insn;
2008 }
2009 \f
2010 static char copy_of_instruction[128];
2011
2012 void
2013 md_assemble (char *str)
2014 {
2015 char *s;
2016 char *start_of_operands;
2017 struct v850_opcode *opcode;
2018 struct v850_opcode *next_opcode;
2019 const unsigned char *opindex_ptr;
2020 int next_opindex;
2021 int relaxable = 0;
2022 unsigned long insn;
2023 unsigned long insn_size;
2024 char *f = NULL;
2025 int i;
2026 int match;
2027 bfd_boolean extra_data_after_insn = FALSE;
2028 unsigned extra_data_len = 0;
2029 unsigned long extra_data = 0;
2030 char *saved_input_line_pointer;
2031 char most_match_errmsg[1024];
2032 int most_match_count = -1;
2033
2034 strncpy (copy_of_instruction, str, sizeof (copy_of_instruction) - 1);
2035 most_match_errmsg[0] = 0;
2036
2037 /* Get the opcode. */
2038 for (s = str; *s != '\0' && ! ISSPACE (*s); s++)
2039 continue;
2040
2041 if (*s != '\0')
2042 *s++ = '\0';
2043
2044 /* Find the first opcode with the proper name. */
2045 opcode = (struct v850_opcode *) hash_find (v850_hash, str);
2046 if (opcode == NULL)
2047 {
2048 /* xgettext:c-format */
2049 as_bad (_("Unrecognized opcode: `%s'"), str);
2050 ignore_rest_of_line ();
2051 return;
2052 }
2053
2054 str = s;
2055 while (ISSPACE (*str))
2056 ++str;
2057
2058 start_of_operands = str;
2059
2060 saved_input_line_pointer = input_line_pointer;
2061
2062 for (;;)
2063 {
2064 const char *errmsg = NULL;
2065 const char *warningmsg = NULL;
2066
2067 match = 0;
2068 opindex_ptr = opcode->operands;
2069
2070 if (no_stld23)
2071 {
2072 if ((strncmp (opcode->name, "st.", 3) == 0
2073 && v850_operands[opcode->operands[1]].bits == 23)
2074 || (strncmp (opcode->name, "ld.", 3) == 0
2075 && v850_operands[opcode->operands[0]].bits == 23))
2076 {
2077 errmsg = _("st/ld offset 23 instruction was disabled .");
2078 goto error;
2079 }
2080 }
2081
2082 if ((opcode->processors & processor_mask & PROCESSOR_MASK) == 0
2083 || (((opcode->processors & ~PROCESSOR_MASK) != 0)
2084 && ((opcode->processors & processor_mask & ~PROCESSOR_MASK) == 0)))
2085 {
2086 errmsg = _("Target processor does not support this instruction.");
2087 goto error;
2088 }
2089
2090 relaxable = 0;
2091 fc = 0;
2092 next_opindex = 0;
2093 insn = opcode->opcode;
2094 extra_data_len = 0;
2095 extra_data_after_insn = FALSE;
2096
2097 input_line_pointer = str = start_of_operands;
2098
2099 for (opindex_ptr = opcode->operands; *opindex_ptr != 0; opindex_ptr++)
2100 {
2101 const struct v850_operand *operand;
2102 char *hold;
2103 expressionS ex;
2104 bfd_reloc_code_real_type reloc;
2105
2106 if (next_opindex == 0)
2107 operand = &v850_operands[*opindex_ptr];
2108 else
2109 {
2110 operand = &v850_operands[next_opindex];
2111 next_opindex = 0;
2112 }
2113
2114 errmsg = NULL;
2115
2116 while (*str == ' ')
2117 ++str;
2118
2119 if (operand->flags & V850_OPERAND_BANG
2120 && *str == '!')
2121 ++str;
2122 else if (operand->flags & V850_OPERAND_PERCENT
2123 && *str == '%')
2124 ++str;
2125
2126 if (*str == ',' || *str == '[' || *str == ']')
2127 ++str;
2128
2129 while (*str == ' ')
2130 ++str;
2131
2132 if (operand->flags & V850_OPERAND_RELAX)
2133 relaxable = 1;
2134
2135 /* Gather the operand. */
2136 hold = input_line_pointer;
2137 input_line_pointer = str;
2138
2139 /* lo(), hi(), hi0(), etc... */
2140 if ((reloc = v850_reloc_prefix (operand, &errmsg)) != BFD_RELOC_UNUSED)
2141 {
2142 /* This is a fake reloc, used to indicate an error condition. */
2143 if (reloc == BFD_RELOC_64)
2144 {
2145 /* match = 1; */
2146 goto error;
2147 }
2148
2149 expression (&ex);
2150
2151 if (ex.X_op == O_constant)
2152 {
2153 switch (reloc)
2154 {
2155 case BFD_RELOC_V850_ZDA_16_16_OFFSET:
2156 case BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET:
2157 case BFD_RELOC_V850_ZDA_15_16_OFFSET:
2158 /* To cope with "not1 7, zdaoff(0xfffff006)[r0]"
2159 and the like. */
2160 /* Fall through. */
2161
2162 case BFD_RELOC_LO16:
2163 case BFD_RELOC_V850_LO16_S1:
2164 case BFD_RELOC_V850_LO16_SPLIT_OFFSET:
2165 {
2166 /* Truncate, then sign extend the value. */
2167 ex.X_add_number = SEXT16 (ex.X_add_number);
2168 break;
2169 }
2170
2171 case BFD_RELOC_HI16:
2172 {
2173 /* Truncate, then sign extend the value. */
2174 ex.X_add_number = SEXT16 (ex.X_add_number >> 16);
2175 break;
2176 }
2177
2178 case BFD_RELOC_HI16_S:
2179 {
2180 /* Truncate, then sign extend the value. */
2181 int temp = (ex.X_add_number >> 16) & 0xffff;
2182
2183 temp += (ex.X_add_number >> 15) & 1;
2184
2185 ex.X_add_number = SEXT16 (temp);
2186 break;
2187 }
2188
2189 case BFD_RELOC_V850_23:
2190 if ((operand->flags & V850E_IMMEDIATE23) == 0)
2191 {
2192 errmsg = _("immediate operand is too large");
2193 goto error;
2194 }
2195 break;
2196
2197 case BFD_RELOC_32:
2198 case BFD_RELOC_V850_32_ABS:
2199 case BFD_RELOC_V850_32_PCREL:
2200 if ((operand->flags & V850E_IMMEDIATE32) == 0)
2201 {
2202 errmsg = _("immediate operand is too large");
2203 goto error;
2204 }
2205
2206 break;
2207
2208 default:
2209 fprintf (stderr, "reloc: %d\n", reloc);
2210 as_bad (_("AAARG -> unhandled constant reloc"));
2211 break;
2212 }
2213
2214 if (operand->flags & V850E_IMMEDIATE32)
2215 {
2216 extra_data_after_insn = TRUE;
2217 extra_data_len = 4;
2218 extra_data = 0;
2219 }
2220 else if (operand->flags & V850E_IMMEDIATE23)
2221 {
2222 if (reloc != BFD_RELOC_V850_23)
2223 {
2224 errmsg = _("immediate operand is too large");
2225 goto error;
2226 }
2227 extra_data_after_insn = TRUE;
2228 extra_data_len = 2;
2229 extra_data = 0;
2230 }
2231 else if ((operand->flags & V850E_IMMEDIATE16)
2232 || (operand->flags & V850E_IMMEDIATE16HI))
2233 {
2234 if (operand->flags & V850E_IMMEDIATE16HI
2235 && reloc != BFD_RELOC_HI16
2236 && reloc != BFD_RELOC_HI16_S)
2237 {
2238 errmsg = _("immediate operand is too large");
2239 goto error;
2240 }
2241 else if (operand->flags & V850E_IMMEDIATE16
2242 && reloc != BFD_RELOC_LO16)
2243 {
2244 errmsg = _("immediate operand is too large");
2245 goto error;
2246 }
2247
2248 extra_data_after_insn = TRUE;
2249 extra_data_len = 2;
2250 extra_data = 0;
2251 }
2252
2253 if (fc > MAX_INSN_FIXUPS)
2254 as_fatal (_("too many fixups"));
2255
2256 fixups[fc].exp = ex;
2257 fixups[fc].opindex = *opindex_ptr;
2258 fixups[fc].reloc = reloc;
2259 fc++;
2260 }
2261 else /* ex.X_op != O_constant. */
2262 {
2263 if ((reloc == BFD_RELOC_32
2264 || reloc == BFD_RELOC_V850_32_ABS
2265 || reloc == BFD_RELOC_V850_32_PCREL)
2266 && operand->bits < 32)
2267 {
2268 errmsg = _("immediate operand is too large");
2269 goto error;
2270 }
2271 else if (reloc == BFD_RELOC_V850_23
2272 && (operand->flags & V850E_IMMEDIATE23) == 0)
2273 {
2274 errmsg = _("immediate operand is too large");
2275 goto error;
2276 }
2277 else if ((reloc == BFD_RELOC_HI16
2278 || reloc == BFD_RELOC_HI16_S)
2279 && operand->bits < 16)
2280 {
2281 errmsg = _("immediate operand is too large");
2282 goto error;
2283 }
2284
2285 if (operand->flags & V850E_IMMEDIATE32)
2286 {
2287 extra_data_after_insn = TRUE;
2288 extra_data_len = 4;
2289 extra_data = 0;
2290 }
2291 else if (operand->flags & V850E_IMMEDIATE23)
2292 {
2293 if (reloc != BFD_RELOC_V850_23)
2294 {
2295 errmsg = _("immediate operand is too large");
2296 goto error;
2297 }
2298 extra_data_after_insn = TRUE;
2299 extra_data_len = 2;
2300 extra_data = 0;
2301 }
2302 else if ((operand->flags & V850E_IMMEDIATE16)
2303 || (operand->flags & V850E_IMMEDIATE16HI))
2304 {
2305 if (operand->flags & V850E_IMMEDIATE16HI
2306 && reloc != BFD_RELOC_HI16
2307 && reloc != BFD_RELOC_HI16_S)
2308 {
2309 errmsg = _("immediate operand is too large");
2310 goto error;
2311 }
2312 else if (operand->flags & V850E_IMMEDIATE16
2313 && reloc != BFD_RELOC_LO16)
2314 {
2315 errmsg = _("immediate operand is too large");
2316 goto error;
2317 }
2318
2319 extra_data_after_insn = TRUE;
2320 extra_data_len = 2;
2321 extra_data = 0;
2322 }
2323
2324 if (fc > MAX_INSN_FIXUPS)
2325 as_fatal (_("too many fixups"));
2326
2327 fixups[fc].exp = ex;
2328 fixups[fc].opindex = *opindex_ptr;
2329 fixups[fc].reloc = reloc;
2330 fc++;
2331 }
2332 }
2333 else if (operand->flags & V850E_IMMEDIATE16
2334 || operand->flags & V850E_IMMEDIATE16HI)
2335 {
2336 expression (&ex);
2337
2338 switch (ex.X_op)
2339 {
2340 case O_constant:
2341 if (operand->flags & V850E_IMMEDIATE16HI)
2342 {
2343 if (ex.X_add_number & 0xffff)
2344 {
2345 errmsg = _("constant too big to fit into instruction");
2346 goto error;
2347 }
2348
2349 ex.X_add_number >>= 16;
2350 }
2351 if (operand->flags & V850E_IMMEDIATE16)
2352 {
2353 if ((ex.X_add_number & 0xffff0000)
2354 && ((ex.X_add_number & 0xffff0000) != 0xffff0000))
2355 {
2356 errmsg = _("constant too big to fit into instruction");
2357 goto error;
2358 }
2359 }
2360 break;
2361
2362 case O_illegal:
2363 errmsg = _("illegal operand");
2364 goto error;
2365
2366 case O_absent:
2367 errmsg = _("missing operand");
2368 goto error;
2369
2370 default:
2371 if (fc >= MAX_INSN_FIXUPS)
2372 as_fatal (_("too many fixups"));
2373
2374 fixups[fc].exp = ex;
2375 fixups[fc].opindex = *opindex_ptr;
2376 fixups[fc].reloc = operand->default_reloc;
2377 ++fc;
2378
2379 ex.X_add_number = 0;
2380 break;
2381 }
2382
2383 extra_data_after_insn = TRUE;
2384 extra_data_len = 2;
2385 extra_data = ex.X_add_number;
2386 }
2387 else if (operand->flags & V850E_IMMEDIATE23)
2388 {
2389 expression (&ex);
2390
2391 switch (ex.X_op)
2392 {
2393 case O_constant:
2394 break;
2395
2396 case O_illegal:
2397 errmsg = _("illegal operand");
2398 goto error;
2399
2400 case O_absent:
2401 errmsg = _("missing operand");
2402 goto error;
2403
2404 default:
2405 break;
2406 }
2407
2408 if (fc >= MAX_INSN_FIXUPS)
2409 as_fatal (_("too many fixups"));
2410
2411 fixups[fc].exp = ex;
2412 fixups[fc].opindex = *opindex_ptr;
2413 fixups[fc].reloc = operand->default_reloc;
2414 ++fc;
2415
2416 extra_data_after_insn = TRUE;
2417 extra_data_len = 2;
2418 extra_data = 0;
2419 }
2420 else if (operand->flags & V850E_IMMEDIATE32)
2421 {
2422 expression (&ex);
2423
2424 switch (ex.X_op)
2425 {
2426 case O_constant:
2427 if ((operand->default_reloc == BFD_RELOC_V850_32_ABS
2428 || operand->default_reloc == BFD_RELOC_V850_32_PCREL)
2429 && (ex.X_add_number & 1))
2430 {
2431 errmsg = _("odd number cannot be used here");
2432 goto error;
2433 }
2434 break;
2435
2436 case O_illegal:
2437 errmsg = _("illegal operand");
2438 goto error;
2439
2440 case O_absent:
2441 errmsg = _("missing operand");
2442 goto error;
2443
2444 default:
2445 if (fc >= MAX_INSN_FIXUPS)
2446 as_fatal (_("too many fixups"));
2447
2448 fixups[fc].exp = ex;
2449 fixups[fc].opindex = *opindex_ptr;
2450 fixups[fc].reloc = operand->default_reloc;
2451 ++fc;
2452
2453 ex.X_add_number = 0;
2454 break;
2455 }
2456
2457 extra_data_after_insn = TRUE;
2458 extra_data_len = 4;
2459 extra_data = ex.X_add_number;
2460 }
2461 else if (operand->flags & V850E_OPERAND_REG_LIST)
2462 {
2463 errmsg = parse_register_list (&insn, operand);
2464
2465 if (errmsg)
2466 goto error;
2467 }
2468 else
2469 {
2470 errmsg = NULL;
2471
2472 if ((operand->flags & V850_OPERAND_REG) != 0)
2473 {
2474 if (!register_name (&ex))
2475 {
2476 errmsg = _("invalid register name");
2477 }
2478
2479 if ((operand->flags & V850_NOT_R0)
2480 && ex.X_add_number == 0)
2481 {
2482 errmsg = _("register r0 cannot be used here");
2483 }
2484
2485 if (operand->flags & V850_REG_EVEN)
2486 {
2487 if (ex.X_add_number % 2)
2488 errmsg = _("odd register cannot be used here");
2489 ex.X_add_number = ex.X_add_number / 2;
2490 }
2491
2492 }
2493 else if ((operand->flags & V850_OPERAND_SRG) != 0)
2494 {
2495 if (!system_register_name (&ex, TRUE))
2496 {
2497 errmsg = _("invalid system register name");
2498 }
2499 }
2500 else if ((operand->flags & V850_OPERAND_EP) != 0)
2501 {
2502 char *start = input_line_pointer;
2503 char c = get_symbol_end ();
2504
2505 if (strcmp (start, "ep") != 0 && strcmp (start, "r30") != 0)
2506 {
2507 /* Put things back the way we found them. */
2508 *input_line_pointer = c;
2509 input_line_pointer = start;
2510 errmsg = _("expected EP register");
2511 goto error;
2512 }
2513
2514 *input_line_pointer = c;
2515 str = input_line_pointer;
2516 input_line_pointer = hold;
2517
2518 while (*str == ' ' || *str == ','
2519 || *str == '[' || *str == ']')
2520 ++str;
2521 continue;
2522 }
2523 else if ((operand->flags & V850_OPERAND_CC) != 0)
2524 {
2525 if (!cc_name (&ex, TRUE))
2526 {
2527 errmsg = _("invalid condition code name");
2528 }
2529
2530 if ((operand->flags & V850_NOT_SA)
2531 && ex.X_add_number == COND_SA_NUM)
2532 {
2533 errmsg = _("condition sa cannot be used here");
2534 }
2535 }
2536 else if ((operand->flags & V850_OPERAND_FLOAT_CC) != 0)
2537 {
2538 if (!float_cc_name (&ex, TRUE))
2539 {
2540 errmsg = _("invalid condition code name");
2541 }
2542 }
2543 else if ((register_name (&ex)
2544 && (operand->flags & V850_OPERAND_REG) == 0))
2545 {
2546 char c;
2547 int exists = 0;
2548
2549 /* It is possible that an alias has been defined that
2550 matches a register name. For example the code may
2551 include a ".set ZERO, 0" directive, which matches
2552 the register name "zero". Attempt to reparse the
2553 field as an expression, and only complain if we
2554 cannot generate a constant. */
2555
2556 input_line_pointer = str;
2557
2558 c = get_symbol_end ();
2559
2560 if (symbol_find (str) != NULL)
2561 exists = 1;
2562
2563 *input_line_pointer = c;
2564 input_line_pointer = str;
2565
2566 expression (&ex);
2567
2568 if (ex.X_op != O_constant)
2569 {
2570 /* If this register is actually occurring too early on
2571 the parsing of the instruction, (because another
2572 field is missing) then report this. */
2573 if (opindex_ptr[1] != 0
2574 && ((v850_operands[opindex_ptr[1]].flags
2575 & V850_OPERAND_REG)
2576 ||(v850_operands[opindex_ptr[1]].flags
2577 & V850_OPERAND_VREG)))
2578 errmsg = _("syntax error: value is missing before the register name");
2579 else
2580 errmsg = _("syntax error: register not expected");
2581
2582 /* If we created a symbol in the process of this
2583 test then delete it now, so that it will not
2584 be output with the real symbols... */
2585 if (exists == 0
2586 && ex.X_op == O_symbol)
2587 symbol_remove (ex.X_add_symbol,
2588 &symbol_rootP, &symbol_lastP);
2589 }
2590 }
2591 else if (system_register_name (&ex, FALSE)
2592 && (operand->flags & V850_OPERAND_SRG) == 0)
2593 {
2594 errmsg = _("syntax error: system register not expected");
2595 }
2596 else if (cc_name (&ex, FALSE)
2597 && (operand->flags & V850_OPERAND_CC) == 0)
2598 {
2599 errmsg = _("syntax error: condition code not expected");
2600 }
2601 else if (float_cc_name (&ex, FALSE)
2602 && (operand->flags & V850_OPERAND_FLOAT_CC) == 0)
2603 {
2604 errmsg = _("syntax error: condition code not expected");
2605 }
2606 else
2607 {
2608 expression (&ex);
2609
2610 if ((operand->flags & V850_NOT_IMM0)
2611 && ex.X_op == O_constant
2612 && ex.X_add_number == 0)
2613 {
2614 errmsg = _("immediate 0 cannot be used here");
2615 }
2616
2617 /* Special case:
2618 If we are assembling a MOV/JARL/JR instruction and the immediate
2619 value does not fit into the bits available then create a
2620 fake error so that the next MOV/JARL/JR instruction will be
2621 selected. This one has a 32 bit immediate field. */
2622
2623 if ((strcmp (opcode->name, "mov") == 0
2624 || strcmp (opcode->name, "jarl") == 0
2625 || strcmp (opcode->name, "jr") == 0)
2626 && ex.X_op == O_constant
2627 && (ex.X_add_number < (-(1 << (operand->bits - 1)))
2628 || ex.X_add_number > ((1 << (operand->bits - 1)) - 1)))
2629 {
2630 errmsg = _("immediate operand is too large");
2631 }
2632
2633 if ((strcmp (opcode->name, "jarl") == 0
2634 || strcmp (opcode->name, "jr") == 0)
2635 && ex.X_op != O_constant
2636 && operand->bits != default_disp_size)
2637 {
2638 errmsg = _("immediate operand is not match");
2639 }
2640 }
2641
2642 if (errmsg)
2643 goto error;
2644
2645 switch (ex.X_op)
2646 {
2647 case O_illegal:
2648 errmsg = _("illegal operand");
2649 goto error;
2650 case O_absent:
2651 errmsg = _("missing operand");
2652 goto error;
2653 case O_register:
2654 if ((operand->flags
2655 & (V850_OPERAND_REG | V850_OPERAND_SRG | V850_OPERAND_VREG)) == 0)
2656 {
2657 errmsg = _("invalid operand");
2658 goto error;
2659 }
2660
2661 insn = v850_insert_operand (insn, operand,
2662 ex.X_add_number,
2663 &warningmsg);
2664
2665 break;
2666
2667 case O_constant:
2668 insn = v850_insert_operand (insn, operand, ex.X_add_number,
2669 &warningmsg);
2670 break;
2671
2672 default:
2673 /* We need to generate a fixup for this expression. */
2674 if (fc >= MAX_INSN_FIXUPS)
2675 as_fatal (_("too many fixups"));
2676
2677 fixups[fc].exp = ex;
2678 fixups[fc].opindex = *opindex_ptr;
2679 fixups[fc].reloc = BFD_RELOC_UNUSED;
2680 ++fc;
2681 break;
2682 }
2683 }
2684
2685 str = input_line_pointer;
2686 input_line_pointer = hold;
2687
2688 while (*str == ' ' || *str == ',' || *str == '[' || *str == ']'
2689 || *str == ')')
2690 ++str;
2691 }
2692
2693 while (ISSPACE (*str))
2694 ++str;
2695
2696 if (*str == '\0')
2697 match = 1;
2698
2699 error:
2700 if (match == 0)
2701 {
2702 if ((opindex_ptr - opcode->operands) >= most_match_count)
2703 {
2704 most_match_count = opindex_ptr - opcode->operands;
2705 if (errmsg != NULL)
2706 strncpy (most_match_errmsg, errmsg, sizeof (most_match_errmsg)-1);
2707 }
2708
2709 next_opcode = opcode + 1;
2710 if (next_opcode->name != NULL
2711 && strcmp (next_opcode->name, opcode->name) == 0)
2712 {
2713 opcode = next_opcode;
2714
2715 /* Skip versions that are not supported by the target
2716 processor. */
2717 if ((opcode->processors & processor_mask) == 0)
2718 goto error;
2719
2720 continue;
2721 }
2722
2723 if (most_match_errmsg[0] == 0)
2724 /* xgettext:c-format. */
2725 as_bad (_("junk at end of line: `%s'"), str);
2726 else
2727 as_bad ("%s: %s", copy_of_instruction, most_match_errmsg);
2728
2729 if (*input_line_pointer == ']')
2730 ++input_line_pointer;
2731
2732 ignore_rest_of_line ();
2733 input_line_pointer = saved_input_line_pointer;
2734 return;
2735 }
2736
2737 if (warningmsg != NULL)
2738 as_warn ("%s", warningmsg);
2739 break;
2740 }
2741
2742 input_line_pointer = str;
2743
2744 /* Tie dwarf2 debug info to the address at the start of the insn.
2745 We can't do this after the insn has been output as the current
2746 frag may have been closed off. eg. by frag_var. */
2747 dwarf2_emit_insn (0);
2748
2749 /* Write out the instruction. */
2750
2751 if (relaxable && fc > 0)
2752 {
2753 insn_size = 2;
2754 fc = 0;
2755
2756 if (strcmp (opcode->name, "br") == 0
2757 || strcmp (opcode->name, "jbr") == 0)
2758 {
2759 if ((processor_mask & PROCESSOR_V850E2_ALL) == 0 || default_disp_size == 22)
2760 {
2761 f = frag_var (rs_machine_dependent, 4, 2, SUBYPTE_UNCOND_9_22,
2762 fixups[0].exp.X_add_symbol,
2763 fixups[0].exp.X_add_number,
2764 (char *)(size_t) fixups[0].opindex);
2765 md_number_to_chars (f, insn, insn_size);
2766 md_number_to_chars (f + 2, 0, 2);
2767 }
2768 else
2769 {
2770 f = frag_var (rs_machine_dependent, 6, 4, SUBYPTE_UNCOND_9_22_32,
2771 fixups[0].exp.X_add_symbol,
2772 fixups[0].exp.X_add_number,
2773 (char *)(size_t) fixups[0].opindex);
2774 md_number_to_chars (f, insn, insn_size);
2775 md_number_to_chars (f + 2, 0, 4);
2776 }
2777 }
2778 else /* b<cond>, j<cond>. */
2779 {
2780 if (default_disp_size == 22
2781 || (processor_mask & PROCESSOR_V850E2_ALL) == 0)
2782 {
2783 if (processor_mask & PROCESSOR_V850E2V3 && !no_bcond17)
2784 {
2785 if (strcmp (opcode->name, "bsa") == 0)
2786 {
2787 f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_SA_9_17_22,
2788 fixups[0].exp.X_add_symbol,
2789 fixups[0].exp.X_add_number,
2790 (char *)(size_t) fixups[0].opindex);
2791 md_number_to_chars (f, insn, insn_size);
2792 md_number_to_chars (f + 2, 0, 6);
2793 }
2794 else
2795 {
2796 f = frag_var (rs_machine_dependent, 6, 4, SUBYPTE_COND_9_17_22,
2797 fixups[0].exp.X_add_symbol,
2798 fixups[0].exp.X_add_number,
2799 (char *)(size_t) fixups[0].opindex);
2800 md_number_to_chars (f, insn, insn_size);
2801 md_number_to_chars (f + 2, 0, 4);
2802 }
2803 }
2804 else
2805 {
2806 if (strcmp (opcode->name, "bsa") == 0)
2807 {
2808 f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_SA_9_22,
2809 fixups[0].exp.X_add_symbol,
2810 fixups[0].exp.X_add_number,
2811 (char *)(size_t) fixups[0].opindex);
2812 md_number_to_chars (f, insn, insn_size);
2813 md_number_to_chars (f + 2, 0, 6);
2814 }
2815 else
2816 {
2817 f = frag_var (rs_machine_dependent, 6, 4, SUBYPTE_COND_9_22,
2818 fixups[0].exp.X_add_symbol,
2819 fixups[0].exp.X_add_number,
2820 (char *)(size_t) fixups[0].opindex);
2821 md_number_to_chars (f, insn, insn_size);
2822 md_number_to_chars (f + 2, 0, 4);
2823 }
2824 }
2825 }
2826 else
2827 {
2828 if (processor_mask & PROCESSOR_V850E2V3 && !no_bcond17)
2829 {
2830 if (strcmp (opcode->name, "bsa") == 0)
2831 {
2832 f = frag_var (rs_machine_dependent, 10, 8, SUBYPTE_SA_9_17_22_32,
2833 fixups[0].exp.X_add_symbol,
2834 fixups[0].exp.X_add_number,
2835 (char *)(size_t) fixups[0].opindex);
2836 md_number_to_chars (f, insn, insn_size);
2837 md_number_to_chars (f + 2, 0, 8);
2838 }
2839 else
2840 {
2841 f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_COND_9_17_22_32,
2842 fixups[0].exp.X_add_symbol,
2843 fixups[0].exp.X_add_number,
2844 (char *)(size_t) fixups[0].opindex);
2845 md_number_to_chars (f, insn, insn_size);
2846 md_number_to_chars (f + 2, 0, 6);
2847 }
2848 }
2849 else
2850 {
2851 if (strcmp (opcode->name, "bsa") == 0)
2852 {
2853 f = frag_var (rs_machine_dependent, 10, 8, SUBYPTE_SA_9_22_32,
2854 fixups[0].exp.X_add_symbol,
2855 fixups[0].exp.X_add_number,
2856 (char *)(size_t) fixups[0].opindex);
2857 md_number_to_chars (f, insn, insn_size);
2858 md_number_to_chars (f + 2, 0, 8);
2859 }
2860 else
2861 {
2862 f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_COND_9_22_32,
2863 fixups[0].exp.X_add_symbol,
2864 fixups[0].exp.X_add_number,
2865 (char *)(size_t) fixups[0].opindex);
2866 md_number_to_chars (f, insn, insn_size);
2867 md_number_to_chars (f + 2, 0, 6);
2868 }
2869 }
2870 }
2871 }
2872 }
2873 else
2874 {
2875 /* Four byte insns have an opcode with the two high bits on. */
2876 if ((insn & 0x0600) == 0x0600)
2877 insn_size = 4;
2878 else
2879 insn_size = 2;
2880
2881 /* Special case: 32 bit MOV. */
2882 if ((insn & 0xffe0) == 0x0620)
2883 insn_size = 2;
2884
2885 /* Special case: 32 bit JARL,JMP,JR. */
2886 if ((insn & 0x1ffe0) == 0x2e0 /* JARL. */
2887 || (insn & 0x1ffe0) == 0x6e0 /* JMP. */
2888 || (insn & 0x1ffff) == 0x2e0) /* JR. */
2889 insn_size = 2;
2890
2891 f = frag_more (insn_size);
2892 md_number_to_chars (f, insn, insn_size);
2893
2894 if (extra_data_after_insn)
2895 {
2896 f = frag_more (extra_data_len);
2897 md_number_to_chars (f, extra_data, extra_data_len);
2898
2899 extra_data_after_insn = FALSE;
2900 }
2901 }
2902
2903 /* Create any fixups. At this point we do not use a
2904 bfd_reloc_code_real_type, but instead just use the
2905 BFD_RELOC_UNUSED plus the operand index. This lets us easily
2906 handle fixups for any operand type, although that is admittedly
2907 not a very exciting feature. We pick a BFD reloc type in
2908 md_apply_fix. */
2909 for (i = 0; i < fc; i++)
2910 {
2911 const struct v850_operand *operand;
2912 bfd_reloc_code_real_type reloc;
2913
2914 operand = &v850_operands[fixups[i].opindex];
2915
2916 reloc = fixups[i].reloc;
2917
2918 if (reloc != BFD_RELOC_UNUSED)
2919 {
2920 reloc_howto_type *reloc_howto =
2921 bfd_reloc_type_lookup (stdoutput, reloc);
2922 int size;
2923 int address;
2924 fixS *fixP;
2925
2926 if (!reloc_howto)
2927 abort ();
2928
2929 size = bfd_get_reloc_size (reloc_howto);
2930
2931 /* XXX This will abort on an R_V850_8 reloc -
2932 is this reloc actually used? */
2933 if (size != 2 && size != 4)
2934 abort ();
2935
2936 if (extra_data_len == 0)
2937 {
2938 address = (f - frag_now->fr_literal) + insn_size - size;
2939 }
2940 else
2941 {
2942 address = (f - frag_now->fr_literal) + extra_data_len - size;
2943 }
2944
2945 if ((operand->flags & V850E_IMMEDIATE32) && (operand->flags & V850_PCREL))
2946 {
2947 fixups[i].exp.X_add_number += 2;
2948 }
2949 else if (operand->default_reloc == BFD_RELOC_V850_16_PCREL)
2950 {
2951 fixups[i].exp.X_add_number += 2;
2952 address += 2;
2953 }
2954
2955 /* fprintf (stderr, "0x%x %d %ld\n", address, size, fixups[i].exp.X_add_number); */
2956 fixP = fix_new_exp (frag_now, address, size,
2957 &fixups[i].exp,
2958 reloc_howto->pc_relative,
2959 reloc);
2960
2961 fixP->tc_fix_data = (void *) operand;
2962
2963 switch (reloc)
2964 {
2965 case BFD_RELOC_LO16:
2966 case BFD_RELOC_V850_LO16_S1:
2967 case BFD_RELOC_V850_LO16_SPLIT_OFFSET:
2968 case BFD_RELOC_HI16:
2969 case BFD_RELOC_HI16_S:
2970 fixP->fx_no_overflow = 1;
2971 break;
2972 default:
2973 break;
2974 }
2975 }
2976 else
2977 {
2978 fix_new_exp (frag_now,
2979 f - frag_now->fr_literal, 4,
2980 & fixups[i].exp,
2981 (operand->flags & V850_PCREL) != 0,
2982 (bfd_reloc_code_real_type) (fixups[i].opindex
2983 + (int) BFD_RELOC_UNUSED));
2984 }
2985 }
2986
2987 input_line_pointer = saved_input_line_pointer;
2988 }
2989
2990 /* If while processing a fixup, a reloc really needs to be created
2991 then it is done here. */
2992
2993 arelent *
2994 tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp)
2995 {
2996 arelent *reloc;
2997
2998 reloc = xmalloc (sizeof (arelent));
2999 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
3000 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
3001 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3002
3003 if ( fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY
3004 || fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3005 || fixp->fx_r_type == BFD_RELOC_V850_LONGCALL
3006 || fixp->fx_r_type == BFD_RELOC_V850_LONGJUMP
3007 || fixp->fx_r_type == BFD_RELOC_V850_ALIGN)
3008 reloc->addend = fixp->fx_offset;
3009 else
3010 {
3011 #if 0
3012 if (fixp->fx_r_type == BFD_RELOC_32
3013 && fixp->fx_pcrel)
3014 fixp->fx_r_type = BFD_RELOC_32_PCREL;
3015 #endif
3016
3017 reloc->addend = fixp->fx_addnumber;
3018 }
3019
3020 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
3021
3022 if (reloc->howto == NULL)
3023 {
3024 as_bad_where (fixp->fx_file, fixp->fx_line,
3025 /* xgettext:c-format */
3026 _("reloc %d not supported by object file format"),
3027 (int) fixp->fx_r_type);
3028
3029 xfree (reloc);
3030
3031 return NULL;
3032 }
3033
3034 return reloc;
3035 }
3036
3037 void
3038 v850_handle_align (fragS * frag)
3039 {
3040 if (v850_relax
3041 && frag->fr_type == rs_align
3042 && frag->fr_address + frag->fr_fix > 0
3043 && frag->fr_offset > 1
3044 && now_seg != bss_section
3045 && now_seg != v850_seg_table[SBSS_SECTION].s
3046 && now_seg != v850_seg_table[TBSS_SECTION].s
3047 && now_seg != v850_seg_table[ZBSS_SECTION].s)
3048 fix_new (frag, frag->fr_fix, 2, & abs_symbol, frag->fr_offset, 0,
3049 BFD_RELOC_V850_ALIGN);
3050 }
3051
3052 /* Return current size of variable part of frag. */
3053
3054 int
3055 md_estimate_size_before_relax (fragS *fragp, asection *seg ATTRIBUTE_UNUSED)
3056 {
3057 if (fragp->fr_subtype >= sizeof (md_relax_table) / sizeof (md_relax_table[0]))
3058 abort ();
3059
3060 return md_relax_table[fragp->fr_subtype].rlx_length;
3061 }
3062
3063 long
3064 v850_pcrel_from_section (fixS *fixp, segT section)
3065 {
3066 /* If the symbol is undefined, or in a section other than our own,
3067 or it is weak (in which case it may well be in another section,
3068 then let the linker figure it out. */
3069 if (fixp->fx_addsy != (symbolS *) NULL
3070 && (! S_IS_DEFINED (fixp->fx_addsy)
3071 || S_IS_WEAK (fixp->fx_addsy)
3072 || (S_GET_SEGMENT (fixp->fx_addsy) != section)))
3073 return 0;
3074
3075 return fixp->fx_frag->fr_address + fixp->fx_where;
3076 }
3077
3078 void
3079 md_apply_fix (fixS *fixP, valueT *valueP, segT seg ATTRIBUTE_UNUSED)
3080 {
3081 valueT value = * valueP;
3082 char *where;
3083
3084 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3085 || fixP->fx_r_type == BFD_RELOC_V850_LONGCALL
3086 || fixP->fx_r_type == BFD_RELOC_V850_LONGJUMP
3087 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3088 {
3089 fixP->fx_done = 0;
3090 return;
3091 }
3092
3093 if (fixP->fx_addsy == (symbolS *) NULL)
3094 fixP->fx_addnumber = value,
3095 fixP->fx_done = 1;
3096
3097 else if (fixP->fx_pcrel)
3098 fixP->fx_addnumber = fixP->fx_offset;
3099
3100 else
3101 {
3102 value = fixP->fx_offset;
3103 if (fixP->fx_subsy != (symbolS *) NULL)
3104 {
3105 if (S_GET_SEGMENT (fixP->fx_subsy) == absolute_section)
3106 value -= S_GET_VALUE (fixP->fx_subsy);
3107 else
3108 /* We don't actually support subtracting a symbol. */
3109 as_bad_where (fixP->fx_file, fixP->fx_line,
3110 _("expression too complex"));
3111 }
3112 fixP->fx_addnumber = value;
3113 }
3114
3115 if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED)
3116 {
3117 int opindex;
3118 const struct v850_operand *operand;
3119 unsigned long insn;
3120 const char *errmsg = NULL;
3121
3122 opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED;
3123 operand = &v850_operands[opindex];
3124
3125 /* Fetch the instruction, insert the fully resolved operand
3126 value, and stuff the instruction back again.
3127
3128 Note the instruction has been stored in little endian
3129 format! */
3130 where = fixP->fx_frag->fr_literal + fixP->fx_where;
3131
3132 if (fixP->fx_size > 2)
3133 insn = bfd_getl32 ((unsigned char *) where);
3134 else
3135 insn = bfd_getl16 ((unsigned char *) where);
3136
3137 insn = v850_insert_operand (insn, operand, (offsetT) value,
3138 &errmsg);
3139 if (errmsg)
3140 as_warn_where (fixP->fx_file, fixP->fx_line, "%s", errmsg);
3141
3142 if (fixP->fx_size > 2)
3143 bfd_putl32 ((bfd_vma) insn, (unsigned char *) where);
3144 else
3145 bfd_putl16 ((bfd_vma) insn, (unsigned char *) where);
3146
3147 if (fixP->fx_done)
3148 /* Nothing else to do here. */
3149 return;
3150
3151 /* Determine a BFD reloc value based on the operand information.
3152 We are only prepared to turn a few of the operands into relocs. */
3153
3154 if (operand->default_reloc == BFD_RELOC_NONE)
3155 {
3156 as_bad_where (fixP->fx_file, fixP->fx_line,
3157 _("unresolved expression that must be resolved"));
3158 fixP->fx_done = 1;
3159 return;
3160 }
3161
3162 {
3163 fixP->fx_r_type = operand->default_reloc;
3164 if (operand->default_reloc == BFD_RELOC_V850_16_PCREL)
3165 {
3166 fixP->fx_where += 2;
3167 fixP->fx_size = 2;
3168 fixP->fx_addnumber += 2;
3169 }
3170 }
3171 }
3172 else if (fixP->fx_done)
3173 {
3174 /* We still have to insert the value into memory! */
3175 where = fixP->fx_frag->fr_literal + fixP->fx_where;
3176
3177 if (fixP->tc_fix_data != NULL
3178 && ((struct v850_operand *) fixP->tc_fix_data)->insert != NULL)
3179 {
3180 const char * message = NULL;
3181 struct v850_operand * operand = (struct v850_operand *) fixP->tc_fix_data;
3182 unsigned long insn;
3183
3184 /* The variable "where" currently points at the exact point inside
3185 the insn where we need to insert the value. But we need to
3186 extract the entire insn so we probably need to move "where"
3187 back a few bytes. */
3188
3189 if (fixP->fx_size == 2)
3190 where -= 2;
3191 else if (fixP->fx_size == 1)
3192 where -= 3;
3193
3194 insn = bfd_getl32 ((unsigned char *) where);
3195
3196 /* Use the operand's insertion procedure, if present, in order to
3197 make sure that the value is correctly stored in the insn. */
3198 insn = operand->insert (insn, (offsetT) value, & message);
3199 /* Ignore message even if it is set. */
3200
3201 bfd_putl32 ((bfd_vma) insn, (unsigned char *) where);
3202 }
3203 else
3204 {
3205 switch (fixP->fx_r_type)
3206 {
3207 case BFD_RELOC_V850_32_ABS:
3208 case BFD_RELOC_V850_32_PCREL:
3209 bfd_putl32 (value & 0xfffffffe, (unsigned char *) where);
3210 break;
3211
3212 case BFD_RELOC_32:
3213 bfd_putl32 (value, (unsigned char *) where);
3214 break;
3215
3216 case BFD_RELOC_V850_23:
3217 bfd_putl32 (((value & 0x7f) << 4) | ((value & 0x7fff80) << (16-7))
3218 | (bfd_getl32 (where) & ~((0x7f << 4) | (0xffff << 16))),
3219 (unsigned char *) where);
3220 break;
3221
3222 case BFD_RELOC_16:
3223 case BFD_RELOC_HI16:
3224 case BFD_RELOC_HI16_S:
3225 case BFD_RELOC_LO16:
3226 case BFD_RELOC_V850_ZDA_16_16_OFFSET:
3227 case BFD_RELOC_V850_SDA_16_16_OFFSET:
3228 case BFD_RELOC_V850_TDA_16_16_OFFSET:
3229 case BFD_RELOC_V850_CALLT_16_16_OFFSET:
3230 bfd_putl16 (value & 0xffff, (unsigned char *) where);
3231 break;
3232
3233 case BFD_RELOC_8:
3234 *where = value & 0xff;
3235 break;
3236
3237 case BFD_RELOC_V850_9_PCREL:
3238 bfd_putl16 (((value & 0x1f0) << 7) | ((value & 0x0e) << 3)
3239 | (bfd_getl16 (where) & ~((0x1f0 << 7) | (0x0e << 3))), where);
3240 break;
3241
3242 case BFD_RELOC_V850_17_PCREL:
3243 bfd_putl32 (((value & 0x10000) >> (16 - 4)) | ((value & 0xfffe) << 16)
3244 | (bfd_getl32 (where) & ~((0x10000 >> (16 - 4)) | (0xfffe << 16))), where);
3245 break;
3246
3247 case BFD_RELOC_V850_16_PCREL:
3248 bfd_putl16 ((-value & 0xfffe) | (bfd_getl16 (where + 2) & 0x0001),
3249 (unsigned char *) (where + 2));
3250 break;
3251
3252 case BFD_RELOC_V850_22_PCREL:
3253 bfd_putl32 (((value & 0xfffe) << 16) | ((value & 0x3f0000) >> 16)
3254 | (bfd_getl32 (where) & ~((0xfffe << 16) | (0x3f0000 >> 16))), where);
3255 break;
3256
3257 case BFD_RELOC_V850_16_S1:
3258 case BFD_RELOC_V850_LO16_S1:
3259 case BFD_RELOC_V850_ZDA_15_16_OFFSET:
3260 case BFD_RELOC_V850_SDA_15_16_OFFSET:
3261 bfd_putl16 (value & 0xfffe, (unsigned char *) where);
3262 break;
3263
3264 case BFD_RELOC_V850_16_SPLIT_OFFSET:
3265 case BFD_RELOC_V850_LO16_SPLIT_OFFSET:
3266 case BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET:
3267 case BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET:
3268 bfd_putl32 (((value << 16) & 0xfffe0000)
3269 | ((value << 5) & 0x20)
3270 | (bfd_getl32 (where) & ~0xfffe0020), where);
3271 break;
3272
3273 case BFD_RELOC_V850_TDA_6_8_OFFSET:
3274 *where = (*where & ~0x7e) | ((value >> 1) & 0x7e);
3275 break;
3276
3277 case BFD_RELOC_V850_TDA_7_8_OFFSET:
3278 *where = (*where & ~0x7f) | ((value >> 1) & 0x7f);
3279 break;
3280
3281 case BFD_RELOC_V850_TDA_7_7_OFFSET:
3282 *where = (*where & ~0x7f) | (value & 0x7f);
3283 break;
3284
3285 case BFD_RELOC_V850_TDA_4_5_OFFSET:
3286 *where = (*where & ~0xf) | ((value >> 1) & 0xf);
3287 break;
3288
3289 case BFD_RELOC_V850_TDA_4_4_OFFSET:
3290 *where = (*where & ~0xf) | (value & 0xf);
3291 break;
3292
3293 case BFD_RELOC_V850_CALLT_6_7_OFFSET:
3294 *where = (*where & ~0x3f) | (value & 0x3f);
3295 break;
3296
3297 default:
3298 abort ();
3299 }
3300 }
3301 }
3302 }
3303
3304 /* Parse a cons expression. We have to handle hi(), lo(), etc
3305 on the v850. */
3306
3307 void
3308 parse_cons_expression_v850 (expressionS *exp)
3309 {
3310 const char *errmsg;
3311 /* See if there's a reloc prefix like hi() we have to handle. */
3312 hold_cons_reloc = v850_reloc_prefix (NULL, &errmsg);
3313
3314 /* Do normal expression parsing. */
3315 expression (exp);
3316 }
3317
3318 /* Create a fixup for a cons expression. If parse_cons_expression_v850
3319 found a reloc prefix, then we use that reloc, else we choose an
3320 appropriate one based on the size of the expression. */
3321
3322 void
3323 cons_fix_new_v850 (fragS *frag,
3324 int where,
3325 int size,
3326 expressionS *exp)
3327 {
3328 if (hold_cons_reloc == BFD_RELOC_UNUSED)
3329 {
3330 if (size == 4)
3331 hold_cons_reloc = BFD_RELOC_32;
3332 if (size == 2)
3333 hold_cons_reloc = BFD_RELOC_16;
3334 if (size == 1)
3335 hold_cons_reloc = BFD_RELOC_8;
3336 }
3337
3338 if (exp != NULL)
3339 fix_new_exp (frag, where, size, exp, 0, hold_cons_reloc);
3340 else
3341 fix_new (frag, where, size, NULL, 0, 0, hold_cons_reloc);
3342
3343 hold_cons_reloc = BFD_RELOC_UNUSED;
3344 }
3345
3346 bfd_boolean
3347 v850_fix_adjustable (fixS *fixP)
3348 {
3349 if (fixP->fx_addsy == NULL)
3350 return 1;
3351
3352 /* Don't adjust function names. */
3353 if (S_IS_FUNCTION (fixP->fx_addsy))
3354 return 0;
3355
3356 /* We need the symbol name for the VTABLE entries. */
3357 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3358 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3359 return 0;
3360
3361 return 1;
3362 }
3363
3364 int
3365 v850_force_relocation (struct fix *fixP)
3366 {
3367 if (fixP->fx_r_type == BFD_RELOC_V850_LONGCALL
3368 || fixP->fx_r_type == BFD_RELOC_V850_LONGJUMP)
3369 return 1;
3370
3371 if (v850_relax
3372 && (fixP->fx_pcrel
3373 || fixP->fx_r_type == BFD_RELOC_V850_ALIGN
3374 || fixP->fx_r_type == BFD_RELOC_V850_9_PCREL
3375 || fixP->fx_r_type == BFD_RELOC_V850_16_PCREL
3376 || fixP->fx_r_type == BFD_RELOC_V850_17_PCREL
3377 || fixP->fx_r_type == BFD_RELOC_V850_22_PCREL
3378 || fixP->fx_r_type == BFD_RELOC_V850_32_PCREL
3379 || fixP->fx_r_type >= BFD_RELOC_UNUSED))
3380 return 1;
3381
3382 return generic_force_reloc (fixP);
3383 }