1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright (C) 2003-2021 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
24 #include "safe-ctype.h"
25 #include "tc-xtensa.h"
27 #include "xtensa-relax.h"
28 #include "dwarf2dbg.h"
29 #include "xtensa-istack.h"
30 #include "xtensa-config.h"
31 #include "elf/xtensa.h"
33 /* Provide default values for new configuration settings. */
34 #ifndef XTHAL_ABI_WINDOWED
35 #define XTHAL_ABI_WINDOWED 0
38 #ifndef XTHAL_ABI_CALL0
39 #define XTHAL_ABI_CALL0 1
42 #ifndef XTENSA_MARCH_EARLIEST
43 #define XTENSA_MARCH_EARLIEST 0
47 #define uint32 unsigned int
50 #define int32 signed int
55 Naming conventions (used somewhat inconsistently):
56 The xtensa_ functions are exported
57 The xg_ functions are internal
59 We also have a couple of different extensibility mechanisms.
60 1) The idiom replacement:
61 This is used when a line is first parsed to
62 replace an instruction pattern with another instruction
63 It is currently limited to replacements of instructions
64 with constant operands.
65 2) The xtensa-relax.c mechanism that has stronger instruction
66 replacement patterns. When an instruction's immediate field
67 does not fit the next instruction sequence is attempted.
68 In addition, "narrow" opcodes are supported this way. */
71 /* Define characters with special meanings to GAS. */
72 const char comment_chars
[] = "#";
73 const char line_comment_chars
[] = "#";
74 const char line_separator_chars
[] = ";";
75 const char EXP_CHARS
[] = "eE";
76 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
79 /* Flags to indicate whether the hardware supports the density and
80 absolute literals options. */
82 bfd_boolean density_supported
;
83 bfd_boolean absolute_literals_supported
;
85 static unsigned microarch_earliest
;
87 static vliw_insn cur_vinsn
;
89 unsigned xtensa_num_pipe_stages
;
90 unsigned xtensa_fetch_width
;
92 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
94 /* Some functions are only valid in the front end. This variable
95 allows us to assert that we haven't crossed over into the
97 static bfd_boolean past_xtensa_end
= FALSE
;
99 /* Flags for properties of the last instruction in a segment. */
100 #define FLAG_IS_A0_WRITER 0x1
101 #define FLAG_IS_BAD_LOOPEND 0x2
104 /* We define a special segment names ".literal" to place literals
105 into. The .fini and .init sections are special because they
106 contain code that is moved together by the linker. We give them
107 their own special .fini.literal and .init.literal sections. */
109 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
110 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
111 #define INIT_SECTION_NAME xtensa_section_rename (".init")
112 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
115 /* This type is used for the directive_stack to keep track of the
116 state of the literal collection pools. If lit_prefix is set, it is
117 used to determine the literal section names; otherwise, the literal
118 sections are determined based on the current text section. The
119 lit_seg and lit4_seg fields cache these literal sections, with the
120 current_text_seg field used a tag to indicate whether the cached
123 typedef struct lit_state_struct
126 segT current_text_seg
;
131 static lit_state default_lit_sections
;
134 /* We keep a list of literal segments. The seg_list type is the node
135 for this list. The literal_head pointer is the head of the list,
136 with the literal_head_h dummy node at the start. */
138 typedef struct seg_list_struct
140 struct seg_list_struct
*next
;
144 static seg_list literal_head_h
;
145 static seg_list
*literal_head
= &literal_head_h
;
148 /* Lists of symbols. We keep a list of symbols that label the current
149 instruction, so that we can adjust the symbols when inserting alignment
150 for various instructions. We also keep a list of all the symbols on
151 literals, so that we can fix up those symbols when the literals are
152 later moved into the text sections. */
154 typedef struct sym_list_struct
156 struct sym_list_struct
*next
;
160 static sym_list
*insn_labels
= NULL
;
161 static sym_list
*free_insn_labels
= NULL
;
162 static sym_list
*saved_insn_labels
= NULL
;
164 static sym_list
*literal_syms
;
167 /* Flags to determine whether to prefer const16 or l32r
168 if both options are available. */
169 int prefer_const16
= 0;
172 /* Global flag to indicate when we are emitting literals. */
173 int generating_literals
= 0;
175 /* The following PROPERTY table definitions are copied from
176 <elf/xtensa.h> and must be kept in sync with the code there. */
178 /* Flags in the property tables to specify whether blocks of memory
179 are literals, instructions, data, or unreachable. For
180 instructions, blocks that begin loop targets and branch targets are
181 designated. Blocks that do not allow density, instruction
182 reordering or transformation are also specified. Finally, for
183 branch targets, branch target alignment priority is included.
184 Alignment of the next block is specified in the current block
185 and the size of the current block does not include any fill required
186 to align to the next block. */
188 #define XTENSA_PROP_LITERAL 0x00000001
189 #define XTENSA_PROP_INSN 0x00000002
190 #define XTENSA_PROP_DATA 0x00000004
191 #define XTENSA_PROP_UNREACHABLE 0x00000008
192 /* Instruction only properties at beginning of code. */
193 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
194 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
195 /* Instruction only properties about code. */
196 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
197 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
198 /* Historically, NO_TRANSFORM was a property of instructions,
199 but it should apply to literals under certain circumstances. */
200 #define XTENSA_PROP_NO_TRANSFORM 0x00000100
202 /* Branch target alignment information. This transmits information
203 to the linker optimization about the priority of aligning a
204 particular block for branch target alignment: None, low priority,
205 high priority, or required. These only need to be checked in
206 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
209 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
210 case XTENSA_PROP_BT_ALIGN_NONE:
211 case XTENSA_PROP_BT_ALIGN_LOW:
212 case XTENSA_PROP_BT_ALIGN_HIGH:
213 case XTENSA_PROP_BT_ALIGN_REQUIRE:
215 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
217 /* No branch target alignment. */
218 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
219 /* Low priority branch target alignment. */
220 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
221 /* High priority branch target alignment. */
222 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
223 /* Required branch target alignment. */
224 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
226 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
227 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
228 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
231 /* Alignment is specified in the block BEFORE the one that needs
232 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
233 get the required alignment specified as a power of 2. Use
234 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
235 alignment. Be careful of side effects since the SET will evaluate
236 flags twice. Also, note that the SIZE of a block in the property
237 table does not include the alignment size, so the alignment fill
238 must be calculated to determine if two blocks are contiguous.
239 TEXT_ALIGN is not currently implemented but is a placeholder for a
240 possible future implementation. */
242 #define XTENSA_PROP_ALIGN 0x00000800
244 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
246 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
247 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
248 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
250 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
253 /* Structure for saving instruction and alignment per-fragment data
254 that will be written to the object file. This structure is
255 equivalent to the actual data that will be written out to the file
256 but is easier to use. We provide a conversion to file flags
257 in frag_flags_to_number. */
259 typedef struct frag_flags_struct frag_flags
;
261 struct frag_flags_struct
263 /* is_literal should only be used after xtensa_move_literals.
264 If you need to check if you are generating a literal fragment,
265 then use the generating_literals global. */
267 unsigned is_literal
: 1;
268 unsigned is_insn
: 1;
269 unsigned is_data
: 1;
270 unsigned is_unreachable
: 1;
272 /* is_specific_opcode implies no_transform. */
273 unsigned is_no_transform
: 1;
277 unsigned is_loop_target
: 1;
278 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
279 unsigned bt_align_priority
: 2;
281 unsigned is_no_density
: 1;
282 /* no_longcalls flag does not need to be placed in the object file. */
284 unsigned is_no_reorder
: 1;
286 /* Uses absolute literal addressing for l32r. */
287 unsigned is_abslit
: 1;
289 unsigned is_align
: 1;
290 unsigned alignment
: 5;
294 /* Structure for saving information about a block of property data
295 for frags that have the same flags. */
296 struct xtensa_block_info_struct
302 struct xtensa_block_info_struct
*next
;
306 /* Structure for saving the current state before emitting literals. */
307 typedef struct emit_state_struct
312 int generating_literals
;
316 /* Opcode placement information */
318 typedef unsigned long long bitfield
;
319 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
320 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
321 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
323 #define MAX_FORMATS 32
325 typedef struct op_placement_info_struct
328 /* A number describing how restrictive the issue is for this
329 opcode. For example, an opcode that fits lots of different
330 formats has a high freedom, as does an opcode that fits
331 only one format but many slots in that format. The most
332 restrictive is the opcode that fits only one slot in one
335 xtensa_format narrowest
;
339 /* formats is a bitfield with the Nth bit set
340 if the opcode fits in the Nth xtensa_format. */
343 /* slots[N]'s Mth bit is set if the op fits in the
344 Mth slot of the Nth xtensa_format. */
345 bitfield slots
[MAX_FORMATS
];
347 /* A count of the number of slots in a given format
348 an op can fit (i.e., the bitcount of the slot field above). */
349 char slots_in_format
[MAX_FORMATS
];
351 } op_placement_info
, *op_placement_info_table
;
353 op_placement_info_table op_placement_table
;
356 /* Extra expression types. */
358 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
359 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
360 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
361 #define O_pcrel O_md4 /* value is a PC-relative offset */
362 #define O_tlsfunc O_md5 /* TLS_FUNC/TLSDESC_FN relocation */
363 #define O_tlsarg O_md6 /* TLS_ARG/TLSDESC_ARG relocation */
364 #define O_tlscall O_md7 /* TLS_CALL relocation */
365 #define O_tpoff O_md8 /* TPOFF relocation */
366 #define O_dtpoff O_md9 /* DTPOFF relocation */
368 struct suffix_reloc_map
372 bfd_reloc_code_real_type reloc
;
376 #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op }
378 static struct suffix_reloc_map suffix_relocs
[] =
380 SUFFIX_MAP ("l", BFD_RELOC_LO16
, O_lo16
),
381 SUFFIX_MAP ("h", BFD_RELOC_HI16
, O_hi16
),
382 SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT
, O_pltrel
),
383 SUFFIX_MAP ("pcrel", BFD_RELOC_32_PCREL
, O_pcrel
),
384 SUFFIX_MAP ("tlsfunc", BFD_RELOC_XTENSA_TLS_FUNC
, O_tlsfunc
),
385 SUFFIX_MAP ("tlsarg", BFD_RELOC_XTENSA_TLS_ARG
, O_tlsarg
),
386 SUFFIX_MAP ("tlscall", BFD_RELOC_XTENSA_TLS_CALL
, O_tlscall
),
387 SUFFIX_MAP ("tpoff", BFD_RELOC_XTENSA_TLS_TPOFF
, O_tpoff
),
388 SUFFIX_MAP ("dtpoff", BFD_RELOC_XTENSA_TLS_DTPOFF
, O_dtpoff
),
402 directive_literal_prefix
,
404 directive_absolute_literals
,
405 directive_last_directive
411 bfd_boolean can_be_negated
;
414 const directive_infoS directive_info
[] =
417 { "literal", FALSE
},
419 { "transform", TRUE
},
420 { "freeregs", FALSE
},
421 { "longcalls", TRUE
},
422 { "literal_prefix", FALSE
},
423 { "schedule", TRUE
},
424 { "absolute-literals", TRUE
}
427 bfd_boolean directive_state
[] =
432 TRUE
, /* transform */
433 FALSE
, /* freeregs */
434 FALSE
, /* longcalls */
435 FALSE
, /* literal_prefix */
436 FALSE
, /* schedule */
437 FALSE
/* absolute_literals */
440 /* A circular list of all potential and actual literal pool locations
444 struct litpool_frag
*next
;
445 struct litpool_frag
*prev
;
448 short priority
; /* 1, 2, or 3 -- 1 is highest */
449 short original_priority
;
453 /* Map a segment to its litpool_frag list. */
456 struct litpool_seg
*next
;
458 struct litpool_frag frag_list
;
459 int frag_count
; /* since last litpool location */
462 static struct litpool_seg litpool_seg_list
;
464 /* Limit maximal size of auto litpool by half of the j range. */
465 #define MAX_AUTO_POOL_LITERALS 16384
467 /* Limit maximal size of explicit literal pool by l32r range. */
468 #define MAX_EXPLICIT_POOL_LITERALS 65536
470 #define MAX_POOL_LITERALS \
471 (auto_litpools ? MAX_AUTO_POOL_LITERALS : MAX_EXPLICIT_POOL_LITERALS)
473 /* Directive functions. */
475 static void xtensa_begin_directive (int);
476 static void xtensa_end_directive (int);
477 static void xtensa_literal_prefix (void);
478 static void xtensa_literal_position (int);
479 static void xtensa_literal_pseudo (int);
480 static void xtensa_frequency_pseudo (int);
481 static void xtensa_elf_cons (int);
482 static void xtensa_leb128 (int);
484 /* Parsing and Idiom Translation. */
486 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
488 /* Various Other Internal Functions. */
490 extern bfd_boolean
xg_is_single_relaxable_insn (TInsn
*, TInsn
*, bfd_boolean
);
491 static bfd_boolean
xg_build_to_insn (TInsn
*, TInsn
*, BuildInstr
*);
492 static void xtensa_mark_literal_pool_location (void);
493 static addressT
get_expanded_loop_offset (xtensa_opcode
);
494 static fragS
*get_literal_pool_location (segT
);
495 static void set_literal_pool_location (segT
, fragS
*);
496 static void xtensa_set_frag_assembly_state (fragS
*);
497 static void finish_vinsn (vliw_insn
*);
498 static bfd_boolean
emit_single_op (TInsn
*);
499 static int total_frag_text_expansion (fragS
*);
500 static bfd_boolean use_trampolines
= TRUE
;
501 static void xtensa_check_frag_count (void);
502 static void xtensa_create_trampoline_frag (bfd_boolean
);
503 static void xtensa_maybe_create_trampoline_frag (void);
504 struct trampoline_frag
;
505 static int init_trampoline_frag (fragS
*);
506 static fixS
*xg_append_jump (fragS
*fragP
, symbolS
*sym
, offsetT offset
);
507 static void xtensa_maybe_create_literal_pool_frag (bfd_boolean
, bfd_boolean
);
508 static bfd_boolean auto_litpools
= FALSE
;
509 static int auto_litpool_limit
= 0;
510 static bfd_boolean
xtensa_is_init_fini (segT seg
);
512 /* Alignment Functions. */
514 static int get_text_align_power (unsigned);
515 static int get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
516 static int branch_align_power (segT
);
518 /* Helpers for xtensa_relax_frag(). */
520 static long relax_frag_add_nop (fragS
*);
522 /* Accessors for additional per-subsegment information. */
524 static unsigned get_last_insn_flags (segT
, subsegT
);
525 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
526 static float get_subseg_total_freq (segT
, subsegT
);
527 static float get_subseg_target_freq (segT
, subsegT
);
528 static void set_subseg_freq (segT
, subsegT
, float, float);
530 /* Segment list functions. */
532 static void xtensa_move_literals (void);
533 static void xtensa_reorder_segments (void);
534 static void xtensa_switch_to_literal_fragment (emit_state
*);
535 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
536 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
537 static void xtensa_restore_emit_state (emit_state
*);
538 static segT
cache_literal_section (bfd_boolean
);
540 /* op_placement_info functions. */
542 static void init_op_placement_info_table (void);
543 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
544 static int xg_get_single_size (xtensa_opcode
);
545 static xtensa_format
xg_get_single_format (xtensa_opcode
);
546 static int xg_get_single_slot (xtensa_opcode
);
548 /* TInsn and IStack functions. */
550 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
551 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
552 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
553 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
554 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
555 static void tinsn_from_chars (TInsn
*, char *, int);
556 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
557 static int get_num_stack_text_bytes (IStack
*);
558 static int get_num_stack_literal_bytes (IStack
*);
559 static bfd_boolean
tinsn_to_slotbuf (xtensa_format
, int, TInsn
*, xtensa_insnbuf
);
561 /* vliw_insn functions. */
563 static void xg_init_vinsn (vliw_insn
*);
564 static void xg_copy_vinsn (vliw_insn
*, vliw_insn
*);
565 static void xg_clear_vinsn (vliw_insn
*);
566 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
567 static void xg_free_vinsn (vliw_insn
*);
568 static bfd_boolean vinsn_to_insnbuf
569 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
570 static void vinsn_from_chars (vliw_insn
*, char *);
572 /* Expression Utilities. */
574 bfd_boolean
expr_is_const (const expressionS
*);
575 offsetT
get_expr_const (const expressionS
*);
576 void set_expr_const (expressionS
*, offsetT
);
577 bfd_boolean
expr_is_register (const expressionS
*);
578 offsetT
get_expr_register (const expressionS
*);
579 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
580 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
581 static void copy_expr (expressionS
*, const expressionS
*);
583 /* Section renaming. */
585 static void build_section_rename (const char *);
588 /* ISA imported from bfd. */
589 extern xtensa_isa xtensa_default_isa
;
591 extern int target_big_endian
;
593 static xtensa_opcode xtensa_addi_opcode
;
594 static xtensa_opcode xtensa_addmi_opcode
;
595 static xtensa_opcode xtensa_call0_opcode
;
596 static xtensa_opcode xtensa_call4_opcode
;
597 static xtensa_opcode xtensa_call8_opcode
;
598 static xtensa_opcode xtensa_call12_opcode
;
599 static xtensa_opcode xtensa_callx0_opcode
;
600 static xtensa_opcode xtensa_callx4_opcode
;
601 static xtensa_opcode xtensa_callx8_opcode
;
602 static xtensa_opcode xtensa_callx12_opcode
;
603 static xtensa_opcode xtensa_const16_opcode
;
604 static xtensa_opcode xtensa_entry_opcode
;
605 static xtensa_opcode xtensa_extui_opcode
;
606 static xtensa_opcode xtensa_movi_opcode
;
607 static xtensa_opcode xtensa_movi_n_opcode
;
608 static xtensa_opcode xtensa_isync_opcode
;
609 static xtensa_opcode xtensa_j_opcode
;
610 static xtensa_opcode xtensa_jx_opcode
;
611 static xtensa_opcode xtensa_l32r_opcode
;
612 static xtensa_opcode xtensa_loop_opcode
;
613 static xtensa_opcode xtensa_loopnez_opcode
;
614 static xtensa_opcode xtensa_loopgtz_opcode
;
615 static xtensa_opcode xtensa_nop_opcode
;
616 static xtensa_opcode xtensa_nop_n_opcode
;
617 static xtensa_opcode xtensa_or_opcode
;
618 static xtensa_opcode xtensa_ret_opcode
;
619 static xtensa_opcode xtensa_ret_n_opcode
;
620 static xtensa_opcode xtensa_retw_opcode
;
621 static xtensa_opcode xtensa_retw_n_opcode
;
622 static xtensa_opcode xtensa_rsr_lcount_opcode
;
623 static xtensa_opcode xtensa_waiti_opcode
;
624 static int config_max_slots
= 0;
627 /* Command-line Options. */
629 bfd_boolean use_literal_section
= TRUE
;
630 enum flix_level produce_flix
= FLIX_ALL
;
631 static bfd_boolean align_targets
= TRUE
;
632 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
633 static bfd_boolean has_a0_b_retw
= FALSE
;
634 static bfd_boolean workaround_a0_b_retw
= FALSE
;
635 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
636 static bfd_boolean workaround_short_loop
= FALSE
;
637 static bfd_boolean maybe_has_short_loop
= FALSE
;
638 static bfd_boolean workaround_close_loop_end
= FALSE
;
639 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
640 static bfd_boolean enforce_three_byte_loop_align
= FALSE
;
641 static bfd_boolean opt_linkrelax
= TRUE
;
643 /* When workaround_short_loops is TRUE, all loops with early exits must
644 have at least 3 instructions. workaround_all_short_loops is a modifier
645 to the workaround_short_loop flag. In addition to the
646 workaround_short_loop actions, all straightline loopgtz and loopnez
647 must have at least 3 instructions. */
649 static bfd_boolean workaround_all_short_loops
= FALSE
;
651 /* Generate individual property section for every section.
652 This option is defined in BDF library. */
653 extern bfd_boolean elf32xtensa_separate_props
;
656 This option is defined in BDF library. */
657 extern int elf32xtensa_abi
;
660 xtensa_setup_hw_workarounds (int earliest
, int latest
)
662 if (earliest
> latest
)
663 as_fatal (_("illegal range of target hardware versions"));
665 /* Enable all workarounds for pre-T1050.0 hardware. */
666 if (earliest
< 105000 || latest
< 105000)
668 workaround_a0_b_retw
|= TRUE
;
669 workaround_b_j_loop_end
|= TRUE
;
670 workaround_short_loop
|= TRUE
;
671 workaround_close_loop_end
|= TRUE
;
672 workaround_all_short_loops
|= TRUE
;
673 enforce_three_byte_loop_align
= TRUE
;
680 option_density
= OPTION_MD_BASE
,
684 option_no_generate_flix
,
691 option_no_link_relax
,
699 option_text_section_literals
,
700 option_no_text_section_literals
,
702 option_absolute_literals
,
703 option_no_absolute_literals
,
705 option_align_targets
,
706 option_no_align_targets
,
708 option_warn_unaligned_targets
,
713 option_workaround_a0_b_retw
,
714 option_no_workaround_a0_b_retw
,
716 option_workaround_b_j_loop_end
,
717 option_no_workaround_b_j_loop_end
,
719 option_workaround_short_loop
,
720 option_no_workaround_short_loop
,
722 option_workaround_all_short_loops
,
723 option_no_workaround_all_short_loops
,
725 option_workaround_close_loop_end
,
726 option_no_workaround_close_loop_end
,
728 option_no_workarounds
,
730 option_rename_section_name
,
733 option_prefer_const16
,
735 option_target_hardware
,
738 option_no_trampolines
,
740 option_auto_litpools
,
741 option_no_auto_litpools
,
742 option_auto_litpool_limit
,
744 option_separate_props
,
745 option_no_separate_props
,
751 const char *md_shortopts
= "";
753 struct option md_longopts
[] =
755 { "density", no_argument
, NULL
, option_density
},
756 { "no-density", no_argument
, NULL
, option_no_density
},
758 { "flix", no_argument
, NULL
, option_flix
},
759 { "no-generate-flix", no_argument
, NULL
, option_no_generate_flix
},
760 { "no-allow-flix", no_argument
, NULL
, option_no_flix
},
762 /* Both "relax" and "generics" are deprecated and treated as equivalent
763 to the "transform" option. */
764 { "relax", no_argument
, NULL
, option_relax
},
765 { "no-relax", no_argument
, NULL
, option_no_relax
},
766 { "generics", no_argument
, NULL
, option_generics
},
767 { "no-generics", no_argument
, NULL
, option_no_generics
},
769 { "transform", no_argument
, NULL
, option_transform
},
770 { "no-transform", no_argument
, NULL
, option_no_transform
},
771 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
772 { "no-text-section-literals", no_argument
, NULL
,
773 option_no_text_section_literals
},
774 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
775 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
776 /* This option was changed from -align-target to -target-align
777 because it conflicted with the "-al" option. */
778 { "target-align", no_argument
, NULL
, option_align_targets
},
779 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
780 { "warn-unaligned-targets", no_argument
, NULL
,
781 option_warn_unaligned_targets
},
782 { "longcalls", no_argument
, NULL
, option_longcalls
},
783 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
785 { "no-workaround-a0-b-retw", no_argument
, NULL
,
786 option_no_workaround_a0_b_retw
},
787 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
789 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
790 option_no_workaround_b_j_loop_end
},
791 { "workaround-b-j-loop-end", no_argument
, NULL
,
792 option_workaround_b_j_loop_end
},
794 { "no-workaround-short-loops", no_argument
, NULL
,
795 option_no_workaround_short_loop
},
796 { "workaround-short-loops", no_argument
, NULL
,
797 option_workaround_short_loop
},
799 { "no-workaround-all-short-loops", no_argument
, NULL
,
800 option_no_workaround_all_short_loops
},
801 { "workaround-all-short-loop", no_argument
, NULL
,
802 option_workaround_all_short_loops
},
804 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
805 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
807 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
809 { "no-workaround-close-loop-end", no_argument
, NULL
,
810 option_no_workaround_close_loop_end
},
811 { "workaround-close-loop-end", no_argument
, NULL
,
812 option_workaround_close_loop_end
},
814 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
816 { "link-relax", no_argument
, NULL
, option_link_relax
},
817 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
819 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
821 { "trampolines", no_argument
, NULL
, option_trampolines
},
822 { "no-trampolines", no_argument
, NULL
, option_no_trampolines
},
824 { "auto-litpools", no_argument
, NULL
, option_auto_litpools
},
825 { "no-auto-litpools", no_argument
, NULL
, option_no_auto_litpools
},
826 { "auto-litpool-limit", required_argument
, NULL
, option_auto_litpool_limit
},
828 { "separate-prop-tables", no_argument
, NULL
, option_separate_props
},
830 { "abi-windowed", no_argument
, NULL
, option_abi_windowed
},
831 { "abi-call0", no_argument
, NULL
, option_abi_call0
},
833 { NULL
, no_argument
, NULL
, 0 }
836 size_t md_longopts_size
= sizeof md_longopts
;
840 md_parse_option (int c
, const char *arg
)
845 as_warn (_("--density option is ignored"));
847 case option_no_density
:
848 as_warn (_("--no-density option is ignored"));
850 case option_link_relax
:
851 opt_linkrelax
= TRUE
;
853 case option_no_link_relax
:
854 opt_linkrelax
= FALSE
;
857 produce_flix
= FLIX_ALL
;
859 case option_no_generate_flix
:
860 produce_flix
= FLIX_NO_GENERATE
;
863 produce_flix
= FLIX_NONE
;
865 case option_generics
:
866 as_warn (_("--generics is deprecated; use --transform instead"));
867 return md_parse_option (option_transform
, arg
);
868 case option_no_generics
:
869 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
870 return md_parse_option (option_no_transform
, arg
);
872 as_warn (_("--relax is deprecated; use --transform instead"));
873 return md_parse_option (option_transform
, arg
);
874 case option_no_relax
:
875 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
876 return md_parse_option (option_no_transform
, arg
);
877 case option_longcalls
:
878 directive_state
[directive_longcalls
] = TRUE
;
880 case option_no_longcalls
:
881 directive_state
[directive_longcalls
] = FALSE
;
883 case option_text_section_literals
:
884 use_literal_section
= FALSE
;
886 case option_no_text_section_literals
:
887 use_literal_section
= TRUE
;
889 case option_absolute_literals
:
890 if (!absolute_literals_supported
)
892 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
895 directive_state
[directive_absolute_literals
] = TRUE
;
897 case option_no_absolute_literals
:
898 directive_state
[directive_absolute_literals
] = FALSE
;
901 case option_workaround_a0_b_retw
:
902 workaround_a0_b_retw
= TRUE
;
904 case option_no_workaround_a0_b_retw
:
905 workaround_a0_b_retw
= FALSE
;
907 case option_workaround_b_j_loop_end
:
908 workaround_b_j_loop_end
= TRUE
;
910 case option_no_workaround_b_j_loop_end
:
911 workaround_b_j_loop_end
= FALSE
;
914 case option_workaround_short_loop
:
915 workaround_short_loop
= TRUE
;
917 case option_no_workaround_short_loop
:
918 workaround_short_loop
= FALSE
;
921 case option_workaround_all_short_loops
:
922 workaround_all_short_loops
= TRUE
;
924 case option_no_workaround_all_short_loops
:
925 workaround_all_short_loops
= FALSE
;
928 case option_workaround_close_loop_end
:
929 workaround_close_loop_end
= TRUE
;
931 case option_no_workaround_close_loop_end
:
932 workaround_close_loop_end
= FALSE
;
935 case option_no_workarounds
:
936 workaround_a0_b_retw
= FALSE
;
937 workaround_b_j_loop_end
= FALSE
;
938 workaround_short_loop
= FALSE
;
939 workaround_all_short_loops
= FALSE
;
940 workaround_close_loop_end
= FALSE
;
943 case option_align_targets
:
944 align_targets
= TRUE
;
946 case option_no_align_targets
:
947 align_targets
= FALSE
;
950 case option_warn_unaligned_targets
:
951 warn_unaligned_branch_targets
= TRUE
;
954 case option_rename_section_name
:
955 build_section_rename (arg
);
959 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
960 should be emitted or not. FIXME: Not implemented. */
963 case option_prefer_l32r
:
965 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
969 case option_prefer_const16
:
971 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
975 case option_target_hardware
:
977 int earliest
, latest
= 0;
979 if (*arg
== 0 || *arg
== '-')
980 as_fatal (_("invalid target hardware version"));
982 earliest
= strtol (arg
, &end
, 0);
986 else if (*end
== '-')
989 as_fatal (_("invalid target hardware version"));
990 latest
= strtol (end
, &end
, 0);
993 as_fatal (_("invalid target hardware version"));
995 xtensa_setup_hw_workarounds (earliest
, latest
);
999 case option_transform
:
1000 /* This option has no affect other than to use the defaults,
1001 which are already set. */
1004 case option_no_transform
:
1005 /* This option turns off all transformations of any kind.
1006 However, because we want to preserve the state of other
1007 directives, we only change its own field. Thus, before
1008 you perform any transformation, always check if transform
1009 is available. If you use the functions we provide for this
1010 purpose, you will be ok. */
1011 directive_state
[directive_transform
] = FALSE
;
1014 case option_trampolines
:
1015 use_trampolines
= TRUE
;
1018 case option_no_trampolines
:
1019 use_trampolines
= FALSE
;
1022 case option_auto_litpools
:
1023 auto_litpools
= TRUE
;
1024 use_literal_section
= FALSE
;
1025 if (auto_litpool_limit
<= 0)
1026 auto_litpool_limit
= MAX_AUTO_POOL_LITERALS
/ 2;
1029 case option_no_auto_litpools
:
1030 auto_litpools
= FALSE
;
1031 auto_litpool_limit
= -1;
1034 case option_auto_litpool_limit
:
1038 if (auto_litpool_limit
< 0)
1039 as_fatal (_("no-auto-litpools is incompatible with auto-litpool-limit"));
1040 if (*arg
== 0 || *arg
== '-')
1041 as_fatal (_("invalid auto-litpool-limit argument"));
1042 value
= strtol (arg
, &end
, 10);
1044 as_fatal (_("invalid auto-litpool-limit argument"));
1045 if (value
< 100 || value
> 10000)
1046 as_fatal (_("invalid auto-litpool-limit argument (range is 100-10000)"));
1047 auto_litpool_limit
= value
;
1048 auto_litpools
= TRUE
;
1049 use_literal_section
= FALSE
;
1053 case option_separate_props
:
1054 elf32xtensa_separate_props
= TRUE
;
1057 case option_no_separate_props
:
1058 elf32xtensa_separate_props
= FALSE
;
1061 case option_abi_windowed
:
1062 elf32xtensa_abi
= XTHAL_ABI_WINDOWED
;
1065 case option_abi_call0
:
1066 elf32xtensa_abi
= XTHAL_ABI_CALL0
;
1076 md_show_usage (FILE *stream
)
1080 --[no-]text-section-literals\n\
1081 [Do not] put literals in the text section\n\
1082 --[no-]absolute-literals\n\
1083 [Do not] default to use non-PC-relative literals\n\
1084 --[no-]target-align [Do not] try to align branch targets\n\
1085 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
1086 --[no-]transform [Do not] transform instructions\n\
1087 --flix both allow hand-written and generate flix bundles\n\
1088 --no-generate-flix allow hand-written but do not generate\n\
1090 --no-allow-flix neither allow hand-written nor generate\n\
1092 --rename-section old=new Rename section 'old' to 'new'\n\
1093 --[no-]trampolines [Do not] generate trampolines (jumps to jumps)\n\
1094 when jumps do not reach their targets\n\
1095 --[no-]auto-litpools [Do not] automatically create literal pools\n\
1096 --auto-litpool-limit=<value>\n\
1097 (range 100-10000) Maximum number of blocks of\n\
1098 instructions to emit between literal pool\n\
1099 locations; implies --auto-litpools flag\n\
1100 --[no-]separate-prop-tables\n\
1101 [Do not] place Xtensa property records into\n\
1102 individual property sections for each section.\n\
1103 Default is to generate single property section.\n", stream
);
1107 /* Functions related to the list of current label symbols. */
1110 xtensa_add_insn_label (symbolS
*sym
)
1114 if (!free_insn_labels
)
1115 l
= XNEW (sym_list
);
1118 l
= free_insn_labels
;
1119 free_insn_labels
= l
->next
;
1123 l
->next
= insn_labels
;
1129 xtensa_clear_insn_labels (void)
1133 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1141 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
)
1145 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
1147 symbolS
*lit_sym
= lit
->sym
;
1148 S_SET_VALUE (lit_sym
, new_offset
);
1149 symbol_set_frag (lit_sym
, new_frag
);
1154 /* Directive data and functions. */
1156 typedef struct state_stackS_struct
1158 directiveE directive
;
1159 bfd_boolean negated
;
1160 bfd_boolean old_state
;
1164 struct state_stackS_struct
*prev
;
1167 state_stackS
*directive_state_stack
;
1169 const pseudo_typeS md_pseudo_table
[] =
1171 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
1172 { "literal_position", xtensa_literal_position
, 0 },
1173 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
1174 { "long", xtensa_elf_cons
, 4 },
1175 { "word", xtensa_elf_cons
, 4 },
1176 { "4byte", xtensa_elf_cons
, 4 },
1177 { "short", xtensa_elf_cons
, 2 },
1178 { "2byte", xtensa_elf_cons
, 2 },
1179 { "sleb128", xtensa_leb128
, 1},
1180 { "uleb128", xtensa_leb128
, 0},
1181 { "begin", xtensa_begin_directive
, 0 },
1182 { "end", xtensa_end_directive
, 0 },
1183 { "literal", xtensa_literal_pseudo
, 0 },
1184 { "frequency", xtensa_frequency_pseudo
, 0 },
1190 use_transform (void)
1192 /* After md_end, you should be checking frag by frag, rather
1193 than state directives. */
1194 gas_assert (!past_xtensa_end
);
1195 return directive_state
[directive_transform
];
1200 do_align_targets (void)
1202 /* Do not use this function after md_end; just look at align_targets
1203 instead. There is no target-align directive, so alignment is either
1204 enabled for all frags or not done at all. */
1205 gas_assert (!past_xtensa_end
);
1206 return align_targets
&& use_transform ();
1211 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1215 state_stackS
*stack
= XNEW (state_stackS
);
1217 file
= as_where (&line
);
1219 stack
->directive
= directive
;
1220 stack
->negated
= negated
;
1221 stack
->old_state
= directive_state
[directive
];
1224 stack
->datum
= datum
;
1225 stack
->prev
= directive_state_stack
;
1226 directive_state_stack
= stack
;
1228 directive_state
[directive
] = !negated
;
1233 directive_pop (directiveE
*directive
,
1234 bfd_boolean
*negated
,
1239 state_stackS
*top
= directive_state_stack
;
1241 if (!directive_state_stack
)
1243 as_bad (_("unmatched .end directive"));
1244 *directive
= directive_none
;
1248 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1249 *directive
= top
->directive
;
1250 *negated
= top
->negated
;
1253 *datum
= top
->datum
;
1254 directive_state_stack
= top
->prev
;
1260 directive_balance (void)
1262 while (directive_state_stack
)
1264 directiveE directive
;
1265 bfd_boolean negated
;
1270 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1271 as_warn_where ((char *) file
, line
,
1272 _(".begin directive with no matching .end directive"));
1278 inside_directive (directiveE dir
)
1280 state_stackS
*top
= directive_state_stack
;
1282 while (top
&& top
->directive
!= dir
)
1285 return (top
!= NULL
);
1290 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1294 const char *directive_string
;
1296 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1301 input_line_pointer
+= 3;
1304 len
= strspn (input_line_pointer
,
1305 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1307 /* This code is a hack to make .begin [no-][generics|relax] exactly
1308 equivalent to .begin [no-]transform. We should remove it when
1309 we stop accepting those options. */
1311 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1313 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1314 directive_string
= "transform";
1316 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1318 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1319 directive_string
= "transform";
1322 directive_string
= input_line_pointer
;
1324 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1326 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1328 input_line_pointer
+= len
;
1329 *directive
= (directiveE
) i
;
1330 if (*negated
&& !directive_info
[i
].can_be_negated
)
1331 as_bad (_("directive %s cannot be negated"),
1332 directive_info
[i
].name
);
1337 as_bad (_("unknown directive"));
1338 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1343 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1345 directiveE directive
;
1346 bfd_boolean negated
;
1350 get_directive (&directive
, &negated
);
1351 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1353 discard_rest_of_line ();
1357 if (cur_vinsn
.inside_bundle
)
1358 as_bad (_("directives are not valid inside bundles"));
1362 case directive_literal
:
1363 if (!inside_directive (directive_literal
))
1365 /* Previous labels go with whatever follows this directive, not with
1366 the literal, so save them now. */
1367 saved_insn_labels
= insn_labels
;
1370 as_warn (_(".begin literal is deprecated; use .literal instead"));
1371 state
= XNEW (emit_state
);
1372 xtensa_switch_to_literal_fragment (state
);
1373 directive_push (directive_literal
, negated
, state
);
1376 case directive_literal_prefix
:
1377 /* Have to flush pending output because a movi relaxed to an l32r
1378 might produce a literal. */
1379 md_flush_pending_output ();
1380 /* Check to see if the current fragment is a literal
1381 fragment. If it is, then this operation is not allowed. */
1382 if (generating_literals
)
1384 as_bad (_("cannot set literal_prefix inside literal fragment"));
1388 /* Allocate the literal state for this section and push
1389 onto the directive stack. */
1390 ls
= XNEW (lit_state
);
1393 *ls
= default_lit_sections
;
1394 directive_push (directive_literal_prefix
, negated
, ls
);
1396 /* Process the new prefix. */
1397 xtensa_literal_prefix ();
1400 case directive_freeregs
:
1401 /* This information is currently unused, but we'll accept the statement
1402 and just discard the rest of the line. This won't check the syntax,
1403 but it will accept every correct freeregs directive. */
1404 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1405 directive_push (directive_freeregs
, negated
, 0);
1408 case directive_schedule
:
1409 md_flush_pending_output ();
1410 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1411 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1412 directive_push (directive_schedule
, negated
, 0);
1413 xtensa_set_frag_assembly_state (frag_now
);
1416 case directive_density
:
1417 as_warn (_(".begin [no-]density is ignored"));
1420 case directive_absolute_literals
:
1421 md_flush_pending_output ();
1422 if (!absolute_literals_supported
&& !negated
)
1424 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1427 xtensa_set_frag_assembly_state (frag_now
);
1428 directive_push (directive
, negated
, 0);
1432 md_flush_pending_output ();
1433 xtensa_set_frag_assembly_state (frag_now
);
1434 directive_push (directive
, negated
, 0);
1438 demand_empty_rest_of_line ();
1443 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1445 directiveE begin_directive
, end_directive
;
1446 bfd_boolean begin_negated
, end_negated
;
1450 emit_state
**state_ptr
;
1453 if (cur_vinsn
.inside_bundle
)
1454 as_bad (_("directives are not valid inside bundles"));
1456 get_directive (&end_directive
, &end_negated
);
1458 md_flush_pending_output ();
1460 switch ((int) end_directive
)
1462 case XTENSA_UNDEFINED
:
1463 discard_rest_of_line ();
1466 case (int) directive_density
:
1467 as_warn (_(".end [no-]density is ignored"));
1468 demand_empty_rest_of_line ();
1471 case (int) directive_absolute_literals
:
1472 if (!absolute_literals_supported
&& !end_negated
)
1474 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1475 demand_empty_rest_of_line ();
1484 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1485 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1486 (const void **) state_ptr
);
1488 if (begin_directive
!= directive_none
)
1490 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1492 as_bad (_("does not match begin %s%s at %s:%d"),
1493 begin_negated
? "no-" : "",
1494 directive_info
[begin_directive
].name
, file
, line
);
1498 switch (end_directive
)
1500 case directive_literal
:
1501 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1502 xtensa_restore_emit_state (state
);
1503 xtensa_set_frag_assembly_state (frag_now
);
1505 if (!inside_directive (directive_literal
))
1507 /* Restore the list of current labels. */
1508 xtensa_clear_insn_labels ();
1509 insn_labels
= saved_insn_labels
;
1513 case directive_literal_prefix
:
1514 /* Restore the default collection sections from saved state. */
1515 s
= (lit_state
*) state
;
1517 default_lit_sections
= *s
;
1519 /* Free the state storage. */
1520 free (s
->lit_prefix
);
1524 case directive_schedule
:
1525 case directive_freeregs
:
1529 xtensa_set_frag_assembly_state (frag_now
);
1535 demand_empty_rest_of_line ();
1539 /* Place an aligned literal fragment at the current location. */
1542 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1544 md_flush_pending_output ();
1546 if (inside_directive (directive_literal
))
1547 as_warn (_(".literal_position inside literal directive; ignoring"));
1548 xtensa_mark_literal_pool_location ();
1550 demand_empty_rest_of_line ();
1551 xtensa_clear_insn_labels ();
1555 /* Support .literal label, expr, ... */
1558 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1561 char *p
, *base_name
;
1564 if (inside_directive (directive_literal
))
1566 as_bad (_(".literal not allowed inside .begin literal region"));
1567 ignore_rest_of_line ();
1571 md_flush_pending_output ();
1573 /* Previous labels go with whatever follows this directive, not with
1574 the literal, so save them now. */
1575 saved_insn_labels
= insn_labels
;
1578 base_name
= input_line_pointer
;
1580 xtensa_switch_to_literal_fragment (&state
);
1582 /* All literals are aligned to four-byte boundaries. */
1583 frag_align (2, 0, 0);
1584 record_alignment (now_seg
, 2);
1586 c
= get_symbol_name (&base_name
);
1587 /* Just after name is now '\0'. */
1588 p
= input_line_pointer
;
1590 SKIP_WHITESPACE_AFTER_NAME ();
1592 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1594 as_bad (_("expected comma or colon after symbol name; "
1595 "rest of line ignored"));
1596 ignore_rest_of_line ();
1597 xtensa_restore_emit_state (&state
);
1605 input_line_pointer
++; /* skip ',' or ':' */
1607 xtensa_elf_cons (4);
1609 xtensa_restore_emit_state (&state
);
1611 /* Restore the list of current labels. */
1612 xtensa_clear_insn_labels ();
1613 insn_labels
= saved_insn_labels
;
1618 xtensa_literal_prefix (void)
1623 /* Parse the new prefix from the input_line_pointer. */
1625 len
= strspn (input_line_pointer
,
1626 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1627 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1629 /* Get a null-terminated copy of the name. */
1630 name
= xmemdup0 (input_line_pointer
, len
);
1632 /* Skip the name in the input line. */
1633 input_line_pointer
+= len
;
1635 default_lit_sections
.lit_prefix
= name
;
1637 /* Clear cached literal sections, since the prefix has changed. */
1638 default_lit_sections
.lit_seg
= NULL
;
1639 default_lit_sections
.lit4_seg
= NULL
;
1643 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1646 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1648 float fall_through_f
, target_f
;
1650 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1651 if (fall_through_f
< 0)
1653 as_bad (_("fall through frequency must be greater than 0"));
1654 ignore_rest_of_line ();
1658 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1661 as_bad (_("branch target frequency must be greater than 0"));
1662 ignore_rest_of_line ();
1666 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1668 demand_empty_rest_of_line ();
1672 /* Like normal .long/.short/.word, except support @plt, etc.
1673 Clobbers input_line_pointer, checks end-of-line. */
1676 xtensa_elf_cons (int nbytes
)
1679 bfd_reloc_code_real_type reloc
;
1681 md_flush_pending_output ();
1683 if (cur_vinsn
.inside_bundle
)
1684 as_bad (_("directives are not valid inside bundles"));
1686 if (is_it_end_of_statement ())
1688 demand_empty_rest_of_line ();
1695 if (exp
.X_op
== O_symbol
1696 && *input_line_pointer
== '@'
1697 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1700 reloc_howto_type
*reloc_howto
=
1701 bfd_reloc_type_lookup (stdoutput
, reloc
);
1703 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1704 as_bad (_("unsupported relocation"));
1705 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1706 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1707 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1708 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1709 as_bad (_("opcode-specific %s relocation used outside "
1710 "an instruction"), reloc_howto
->name
);
1711 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1712 as_bad (ngettext ("%s relocations do not fit in %d byte",
1713 "%s relocations do not fit in %d bytes",
1715 reloc_howto
->name
, nbytes
);
1716 else if (reloc
== BFD_RELOC_XTENSA_TLS_FUNC
1717 || reloc
== BFD_RELOC_XTENSA_TLS_ARG
1718 || reloc
== BFD_RELOC_XTENSA_TLS_CALL
)
1719 as_bad (_("invalid use of %s relocation"), reloc_howto
->name
);
1722 char *p
= frag_more ((int) nbytes
);
1723 xtensa_set_frag_assembly_state (frag_now
);
1724 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1725 nbytes
, &exp
, reloc_howto
->pc_relative
, reloc
);
1730 xtensa_set_frag_assembly_state (frag_now
);
1731 emit_expr (&exp
, (unsigned int) nbytes
);
1734 while (*input_line_pointer
++ == ',');
1736 input_line_pointer
--; /* Put terminator back into stream. */
1737 demand_empty_rest_of_line ();
1740 static bfd_boolean is_leb128_expr
;
1743 xtensa_leb128 (int sign
)
1745 is_leb128_expr
= TRUE
;
1747 is_leb128_expr
= FALSE
;
1751 /* Parsing and Idiom Translation. */
1753 /* Parse @plt, etc. and return the desired relocation. */
1754 static bfd_reloc_code_real_type
1755 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1765 return BFD_RELOC_NONE
;
1767 for (ch
= *str
, str2
= ident
;
1768 (str2
< ident
+ sizeof (ident
) - 1
1769 && (ISALNUM (ch
) || ch
== '@'));
1772 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1779 for (i
= 0; i
< ARRAY_SIZE (suffix_relocs
); i
++)
1780 if (ch
== suffix_relocs
[i
].suffix
[0]
1781 && len
== suffix_relocs
[i
].length
1782 && memcmp (ident
, suffix_relocs
[i
].suffix
, suffix_relocs
[i
].length
) == 0)
1784 /* Now check for "identifier@suffix+constant". */
1785 if (*str
== '-' || *str
== '+')
1787 char *orig_line
= input_line_pointer
;
1788 expressionS new_exp
;
1790 input_line_pointer
= str
;
1791 expression (&new_exp
);
1792 if (new_exp
.X_op
== O_constant
)
1794 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1795 str
= input_line_pointer
;
1798 if (&input_line_pointer
!= str_p
)
1799 input_line_pointer
= orig_line
;
1803 return suffix_relocs
[i
].reloc
;
1806 return BFD_RELOC_UNUSED
;
1810 /* Find the matching operator type. */
1812 map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc
)
1814 operatorT
operator = O_illegal
;
1817 for (i
= 0; i
< ARRAY_SIZE (suffix_relocs
); i
++)
1819 if (suffix_relocs
[i
].reloc
== reloc
)
1821 operator = suffix_relocs
[i
].operator;
1825 gas_assert (operator != O_illegal
);
1830 /* Find the matching reloc type. */
1831 static bfd_reloc_code_real_type
1832 map_operator_to_reloc (unsigned char operator, bfd_boolean is_literal
)
1835 bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
1837 for (i
= 0; i
< ARRAY_SIZE (suffix_relocs
); i
++)
1839 if (suffix_relocs
[i
].operator == operator)
1841 reloc
= suffix_relocs
[i
].reloc
;
1848 if (reloc
== BFD_RELOC_XTENSA_TLS_FUNC
)
1849 return BFD_RELOC_XTENSA_TLSDESC_FN
;
1850 else if (reloc
== BFD_RELOC_XTENSA_TLS_ARG
)
1851 return BFD_RELOC_XTENSA_TLSDESC_ARG
;
1854 if (reloc
== BFD_RELOC_UNUSED
)
1855 return BFD_RELOC_32
;
1862 expression_end (const char *name
)
1885 #define ERROR_REG_NUM ((unsigned) -1)
1888 tc_get_register (const char *prefix
)
1891 const char *next_expr
;
1892 const char *old_line_pointer
;
1895 old_line_pointer
= input_line_pointer
;
1897 if (*input_line_pointer
== '$')
1898 ++input_line_pointer
;
1900 /* Accept "sp" as a synonym for "a1". */
1901 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1902 && expression_end (input_line_pointer
+ 2))
1904 input_line_pointer
+= 2;
1905 return 1; /* AR[1] */
1908 while (*input_line_pointer
++ == *prefix
++)
1910 --input_line_pointer
;
1915 as_bad (_("bad register name: %s"), old_line_pointer
);
1916 return ERROR_REG_NUM
;
1919 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1921 as_bad (_("bad register number: %s"), input_line_pointer
);
1922 return ERROR_REG_NUM
;
1927 while (ISDIGIT ((int) *input_line_pointer
))
1928 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1930 if (!(next_expr
= expression_end (input_line_pointer
)))
1932 as_bad (_("bad register name: %s"), old_line_pointer
);
1933 return ERROR_REG_NUM
;
1936 input_line_pointer
= (char *) next_expr
;
1943 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1945 xtensa_isa isa
= xtensa_default_isa
;
1947 /* Check if this is an immediate operand. */
1948 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1950 bfd_reloc_code_real_type reloc
;
1951 segT t
= expression (tok
);
1953 if (t
== absolute_section
1954 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1956 gas_assert (tok
->X_op
== O_constant
);
1957 tok
->X_op
= O_symbol
;
1958 tok
->X_add_symbol
= &abs_symbol
;
1961 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1962 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1967 case BFD_RELOC_LO16
:
1968 if (tok
->X_op
== O_constant
)
1970 tok
->X_add_number
&= 0xffff;
1974 case BFD_RELOC_HI16
:
1975 if (tok
->X_op
== O_constant
)
1977 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1981 case BFD_RELOC_UNUSED
:
1982 as_bad (_("unsupported relocation"));
1984 case BFD_RELOC_32_PCREL
:
1985 as_bad (_("pcrel relocation not allowed in an instruction"));
1990 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
1995 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1996 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1998 if (reg
!= ERROR_REG_NUM
) /* Already errored */
2001 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
2002 as_bad (_("register number out of range"));
2005 tok
->X_op
= O_register
;
2006 tok
->X_add_symbol
= 0;
2007 tok
->X_add_number
= reg
;
2012 /* Split up the arguments for an opcode or pseudo-op. */
2015 tokenize_arguments (char **args
, char *str
)
2017 char *old_input_line_pointer
;
2018 bfd_boolean saw_comma
= FALSE
;
2019 bfd_boolean saw_arg
= FALSE
;
2020 bfd_boolean saw_colon
= FALSE
;
2022 char *arg_end
, *arg
;
2025 /* Save and restore input_line_pointer around this function. */
2026 old_input_line_pointer
= input_line_pointer
;
2027 input_line_pointer
= str
;
2029 while (*input_line_pointer
)
2032 switch (*input_line_pointer
)
2039 input_line_pointer
++;
2040 if (saw_comma
|| saw_colon
|| !saw_arg
)
2046 input_line_pointer
++;
2047 if (saw_comma
|| saw_colon
|| !saw_arg
)
2053 if (!saw_comma
&& !saw_colon
&& saw_arg
)
2056 arg_end
= input_line_pointer
+ 1;
2057 while (!expression_end (arg_end
))
2060 arg_len
= arg_end
- input_line_pointer
;
2061 arg
= XNEWVEC (char, (saw_colon
? 1 : 0) + arg_len
+ 1);
2062 args
[num_args
] = arg
;
2066 strncpy (arg
, input_line_pointer
, arg_len
);
2067 arg
[arg_len
] = '\0';
2069 input_line_pointer
= arg_end
;
2079 if (saw_comma
|| saw_colon
)
2081 input_line_pointer
= old_input_line_pointer
;
2086 as_bad (_("extra comma"));
2088 as_bad (_("extra colon"));
2090 as_bad (_("missing argument"));
2092 as_bad (_("missing comma or colon"));
2093 input_line_pointer
= old_input_line_pointer
;
2098 /* Parse the arguments to an opcode. Return TRUE on error. */
2101 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
2103 expressionS
*tok
, *last_tok
;
2104 xtensa_opcode opcode
= insn
->opcode
;
2105 bfd_boolean had_error
= TRUE
;
2106 xtensa_isa isa
= xtensa_default_isa
;
2107 int n
, num_regs
= 0;
2108 int opcode_operand_count
;
2109 int opnd_cnt
, last_opnd_cnt
;
2110 unsigned int next_reg
= 0;
2111 char *old_input_line_pointer
;
2113 if (insn
->insn_type
== ITYPE_LITERAL
)
2114 opcode_operand_count
= 1;
2116 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
2119 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
2121 /* Save and restore input_line_pointer around this function. */
2122 old_input_line_pointer
= input_line_pointer
;
2128 /* Skip invisible operands. */
2129 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
2135 for (n
= 0; n
< num_args
; n
++)
2137 input_line_pointer
= arg_strings
[n
];
2138 if (*input_line_pointer
== ':')
2140 xtensa_regfile opnd_rf
;
2141 input_line_pointer
++;
2144 gas_assert (opnd_cnt
> 0);
2146 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
2148 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
2149 as_warn (_("incorrect register number, ignoring"));
2154 if (opnd_cnt
>= opcode_operand_count
)
2156 as_warn (_("too many arguments"));
2159 gas_assert (opnd_cnt
< MAX_INSN_ARGS
);
2161 expression_maybe_register (opcode
, opnd_cnt
, tok
);
2162 next_reg
= tok
->X_add_number
+ 1;
2164 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
2166 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
2168 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
2169 /* minus 1 because we are seeing one right now */
2175 last_opnd_cnt
= opnd_cnt
;
2176 demand_empty_rest_of_line ();
2183 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
2187 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
2190 insn
->ntok
= tok
- insn
->tok
;
2194 input_line_pointer
= old_input_line_pointer
;
2200 get_invisible_operands (TInsn
*insn
)
2202 xtensa_isa isa
= xtensa_default_isa
;
2203 static xtensa_insnbuf slotbuf
= NULL
;
2205 xtensa_opcode opc
= insn
->opcode
;
2206 int slot
, opnd
, fmt_found
;
2210 slotbuf
= xtensa_insnbuf_alloc (isa
);
2212 /* Find format/slot where this can be encoded. */
2215 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2217 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2219 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2225 if (fmt_found
) break;
2230 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2234 /* First encode all the visible operands
2235 (to deal with shared field operands). */
2236 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2238 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2239 && (insn
->tok
[opnd
].X_op
== O_register
2240 || insn
->tok
[opnd
].X_op
== O_constant
))
2242 val
= insn
->tok
[opnd
].X_add_number
;
2243 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2244 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2248 /* Then pull out the values for the invisible ones. */
2249 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2251 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2253 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2254 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2255 insn
->tok
[opnd
].X_add_number
= val
;
2256 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2257 insn
->tok
[opnd
].X_op
= O_register
;
2259 insn
->tok
[opnd
].X_op
= O_constant
;
2268 xg_reverse_shift_count (char **cnt_argp
)
2270 char *cnt_arg
, *new_arg
;
2271 cnt_arg
= *cnt_argp
;
2273 /* replace the argument with "31-(argument)" */
2274 new_arg
= concat ("31-(", cnt_arg
, ")", (char *) NULL
);
2277 *cnt_argp
= new_arg
;
2281 /* If "arg" is a constant expression, return non-zero with the value
2285 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2288 char *save_ptr
= input_line_pointer
;
2290 input_line_pointer
= arg
;
2292 input_line_pointer
= save_ptr
;
2294 if (exp
.X_op
== O_constant
)
2296 *valp
= exp
.X_add_number
;
2305 xg_replace_opname (char **popname
, const char *newop
)
2308 *popname
= xstrdup (newop
);
2313 xg_check_num_args (int *pnum_args
,
2318 int num_args
= *pnum_args
;
2320 if (num_args
< expected_num
)
2322 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2323 num_args
, opname
, expected_num
);
2327 if (num_args
> expected_num
)
2329 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2330 num_args
, opname
, expected_num
);
2331 while (num_args
-- > expected_num
)
2333 free (arg_strings
[num_args
]);
2334 arg_strings
[num_args
] = 0;
2336 *pnum_args
= expected_num
;
2344 /* If the register is not specified as part of the opcode,
2345 then get it from the operand and move it to the opcode. */
2348 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2350 xtensa_isa isa
= xtensa_default_isa
;
2352 char *opname
, *new_opname
;
2353 const char *sr_name
;
2354 int is_user
, is_write
;
2359 is_user
= (opname
[1] == 'u');
2360 is_write
= (opname
[0] == 'w');
2362 /* Opname == [rw]ur or [rwx]sr... */
2364 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2367 /* Check if the argument is a symbolic register name. */
2368 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2369 /* Handle WSR to "INTSET" as a special case. */
2370 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2371 && !strcasecmp (arg_strings
[1], "intset"))
2372 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2373 if (sr
== XTENSA_UNDEFINED
2374 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2376 /* Maybe it's a register number.... */
2378 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2380 as_bad (_("invalid register '%s' for '%s' instruction"),
2381 arg_strings
[1], opname
);
2384 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2385 if (sr
== XTENSA_UNDEFINED
)
2387 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2388 (long) val
, opname
);
2393 /* Remove the last argument, which is now part of the opcode. */
2394 free (arg_strings
[1]);
2398 /* Translate the opcode. */
2399 sr_name
= xtensa_sysreg_name (isa
, sr
);
2400 /* Another special case for "WSR.INTSET".... */
2401 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2403 new_opname
= concat (*popname
, ".", sr_name
, (char *) NULL
);
2405 *popname
= new_opname
;
2412 xtensa_translate_old_userreg_ops (char **popname
)
2414 xtensa_isa isa
= xtensa_default_isa
;
2416 char *opname
, *new_opname
;
2417 const char *sr_name
;
2418 bfd_boolean has_underbar
= FALSE
;
2421 if (opname
[0] == '_')
2423 has_underbar
= TRUE
;
2427 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2428 if (sr
!= XTENSA_UNDEFINED
)
2430 /* The new default name ("nnn") is different from the old default
2431 name ("URnnn"). The old default is handled below, and we don't
2432 want to recognize [RW]nnn, so do nothing if the name is the (new)
2434 static char namebuf
[10];
2435 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2436 if (strcmp (namebuf
, opname
+ 1) == 0)
2444 /* Only continue if the reg name is "URnnn". */
2445 if (opname
[1] != 'u' || opname
[2] != 'r')
2447 val
= strtoul (opname
+ 3, &end
, 10);
2451 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2452 if (sr
== XTENSA_UNDEFINED
)
2454 as_bad (_("invalid register number (%ld) for '%s'"),
2455 (long) val
, opname
);
2460 /* Translate the opcode. */
2461 sr_name
= xtensa_sysreg_name (isa
, sr
);
2462 new_opname
= XNEWVEC (char, strlen (sr_name
) + 6);
2463 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2464 opname
[0], sr_name
);
2466 *popname
= new_opname
;
2473 xtensa_translate_zero_immed (const char *old_op
,
2483 gas_assert (opname
[0] != '_');
2485 if (strcmp (opname
, old_op
) != 0)
2488 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2490 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2492 xg_replace_opname (popname
, new_op
);
2493 free (arg_strings
[1]);
2494 arg_strings
[1] = arg_strings
[2];
2503 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2504 Returns non-zero if an error was found. */
2507 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2509 char *opname
= *popname
;
2510 bfd_boolean has_underbar
= FALSE
;
2514 has_underbar
= TRUE
;
2518 if (strcmp (opname
, "mov") == 0)
2520 if (use_transform () && !has_underbar
&& density_supported
)
2521 xg_replace_opname (popname
, "mov.n");
2524 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2526 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2527 arg_strings
[2] = xstrdup (arg_strings
[1]);
2533 /* Without an operand, this is given a default immediate operand of 0. */
2534 if ((strcmp (opname
, "simcall") == 0 && microarch_earliest
>= 280000))
2536 if (*pnum_args
== 0)
2538 arg_strings
[0] = (char *) xmalloc (2);
2539 strcpy (arg_strings
[0], "0");
2545 if (strcmp (opname
, "bbsi.l") == 0)
2547 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2549 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2550 if (target_big_endian
)
2551 xg_reverse_shift_count (&arg_strings
[1]);
2555 if (strcmp (opname
, "bbci.l") == 0)
2557 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2559 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2560 if (target_big_endian
)
2561 xg_reverse_shift_count (&arg_strings
[1]);
2565 /* Don't do anything special with NOPs inside FLIX instructions. They
2566 are handled elsewhere. Real NOP instructions are always available
2567 in configurations with FLIX, so this should never be an issue but
2568 check for it anyway. */
2569 if (!cur_vinsn
.inside_bundle
&& xtensa_nop_opcode
== XTENSA_UNDEFINED
2570 && strcmp (opname
, "nop") == 0)
2572 if (use_transform () && !has_underbar
&& density_supported
)
2573 xg_replace_opname (popname
, "nop.n");
2576 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2578 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2579 arg_strings
[0] = xstrdup ("a1");
2580 arg_strings
[1] = xstrdup ("a1");
2581 arg_strings
[2] = xstrdup ("a1");
2587 /* Recognize [RW]UR and [RWX]SR. */
2588 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2589 && (opname
[1] == 'u' || opname
[1] == 's'))
2590 || (opname
[0] == 'x' && opname
[1] == 's'))
2592 && opname
[3] == '\0')
2593 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2595 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2596 [RW]<name> if <name> is the non-default name of a user register. */
2597 if ((opname
[0] == 'r' || opname
[0] == 'w')
2598 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2599 return xtensa_translate_old_userreg_ops (popname
);
2601 /* Relax branches that don't allow comparisons against an immediate value
2602 of zero to the corresponding branches with implicit zero immediates. */
2603 if (!has_underbar
&& use_transform ())
2605 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2606 pnum_args
, arg_strings
))
2609 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2610 pnum_args
, arg_strings
))
2613 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2614 pnum_args
, arg_strings
))
2617 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2618 pnum_args
, arg_strings
))
2626 /* Functions for dealing with the Xtensa ISA. */
2628 /* Currently the assembler only allows us to use a single target per
2629 fragment. Because of this, only one operand for a given
2630 instruction may be symbolic. If there is a PC-relative operand,
2631 the last one is chosen. Otherwise, the result is the number of the
2632 last immediate operand, and if there are none of those, we fail and
2636 get_relaxable_immed (xtensa_opcode opcode
)
2638 int last_immed
= -1;
2641 if (opcode
== XTENSA_UNDEFINED
)
2644 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2645 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2647 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2649 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2651 if (last_immed
== -1
2652 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2659 static xtensa_opcode
2660 get_opcode_from_buf (const char *buf
, int slot
)
2662 static xtensa_insnbuf insnbuf
= NULL
;
2663 static xtensa_insnbuf slotbuf
= NULL
;
2664 xtensa_isa isa
= xtensa_default_isa
;
2669 insnbuf
= xtensa_insnbuf_alloc (isa
);
2670 slotbuf
= xtensa_insnbuf_alloc (isa
);
2673 xtensa_insnbuf_from_chars (isa
, insnbuf
, (const unsigned char *) buf
, 0);
2674 fmt
= xtensa_format_decode (isa
, insnbuf
);
2675 if (fmt
== XTENSA_UNDEFINED
)
2676 return XTENSA_UNDEFINED
;
2678 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2679 return XTENSA_UNDEFINED
;
2681 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2682 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2686 #ifdef TENSILICA_DEBUG
2688 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2691 xtensa_print_insn_table (void)
2693 int num_opcodes
, num_operands
;
2694 xtensa_opcode opcode
;
2695 xtensa_isa isa
= xtensa_default_isa
;
2697 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2698 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2701 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2702 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2703 for (opn
= 0; opn
< num_operands
; opn
++)
2705 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2707 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2709 xtensa_regfile opnd_rf
=
2710 xtensa_operand_regfile (isa
, opcode
, opn
);
2711 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2713 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2714 fputs ("[lLr] ", stderr
);
2716 fputs ("i ", stderr
);
2718 fprintf (stderr
, "\n");
2724 print_vliw_insn (xtensa_insnbuf vbuf
)
2726 xtensa_isa isa
= xtensa_default_isa
;
2727 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2728 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2731 fprintf (stderr
, "format = %d\n", f
);
2733 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2735 xtensa_opcode opcode
;
2739 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2740 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2741 opname
= xtensa_opcode_name (isa
, opcode
);
2743 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2744 fprintf (stderr
, " operands = ");
2746 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2750 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2752 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2753 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2754 fprintf (stderr
, "%d ", val
);
2756 fprintf (stderr
, "\n");
2758 xtensa_insnbuf_free (isa
, sbuf
);
2761 #endif /* TENSILICA_DEBUG */
2765 is_direct_call_opcode (xtensa_opcode opcode
)
2767 xtensa_isa isa
= xtensa_default_isa
;
2768 int n
, num_operands
;
2770 if (xtensa_opcode_is_call (isa
, opcode
) != 1)
2773 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2774 for (n
= 0; n
< num_operands
; n
++)
2776 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2777 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2784 /* Convert from BFD relocation type code to slot and operand number.
2785 Returns non-zero on failure. */
2788 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2790 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2791 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2793 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2796 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2797 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2799 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2809 /* Convert from slot number to BFD relocation type code for the
2810 standard PC-relative relocations. Return BFD_RELOC_NONE on
2813 static bfd_reloc_code_real_type
2814 encode_reloc (int slot
)
2816 if (slot
< 0 || slot
> 14)
2817 return BFD_RELOC_NONE
;
2819 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2823 /* Convert from slot numbers to BFD relocation type code for the
2824 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2826 static bfd_reloc_code_real_type
2827 encode_alt_reloc (int slot
)
2829 if (slot
< 0 || slot
> 14)
2830 return BFD_RELOC_NONE
;
2832 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2837 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2840 xtensa_opcode opcode
,
2846 uint32 valbuf
= value
;
2848 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2850 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2852 as_bad_where ((char *) file
, line
,
2853 _("operand %d of '%s' has out of range value '%u'"),
2855 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2858 as_bad_where ((char *) file
, line
,
2859 _("operand %d of '%s' has invalid value '%u'"),
2861 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2866 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2872 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2875 xtensa_opcode opcode
,
2879 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2880 fmt
, slot
, slotbuf
, &val
);
2881 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2886 /* Checks for rules from xtensa-relax tables. */
2888 /* The routine xg_instruction_matches_option_term must return TRUE
2889 when a given option term is true. The meaning of all of the option
2890 terms is given interpretation by this function. */
2893 xg_instruction_matches_option_term (TInsn
*insn
, const ReqOrOption
*option
)
2895 if (strcmp (option
->option_name
, "realnop") == 0
2896 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2898 /* These conditions were evaluated statically when building the
2899 relaxation table. There's no need to reevaluate them now. */
2902 else if (strcmp (option
->option_name
, "FREEREG") == 0)
2903 return insn
->extra_arg
.X_op
== O_register
;
2906 as_fatal (_("internal error: unknown option name '%s'"),
2907 option
->option_name
);
2913 xg_instruction_matches_or_options (TInsn
*insn
,
2914 const ReqOrOptionList
*or_option
)
2916 const ReqOrOption
*option
;
2917 /* Must match each of the AND terms. */
2918 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2920 if (xg_instruction_matches_option_term (insn
, option
))
2928 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2930 const ReqOption
*req_options
;
2931 /* Must match each of the AND terms. */
2932 for (req_options
= options
;
2933 req_options
!= NULL
;
2934 req_options
= req_options
->next
)
2936 /* Must match one of the OR clauses. */
2937 if (!xg_instruction_matches_or_options (insn
,
2938 req_options
->or_option_terms
))
2945 /* Return the transition rule that matches or NULL if none matches. */
2948 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2950 PreconditionList
*condition_l
;
2952 if (rule
->opcode
!= insn
->opcode
)
2955 for (condition_l
= rule
->conditions
;
2956 condition_l
!= NULL
;
2957 condition_l
= condition_l
->next
)
2961 Precondition
*cond
= condition_l
->precond
;
2966 /* The expression must be the constant. */
2967 gas_assert (cond
->op_num
< insn
->ntok
);
2968 exp1
= &insn
->tok
[cond
->op_num
];
2969 if (expr_is_const (exp1
))
2974 if (get_expr_const (exp1
) != cond
->op_data
)
2978 if (get_expr_const (exp1
) == cond
->op_data
)
2985 else if (expr_is_register (exp1
))
2990 if (get_expr_register (exp1
) != cond
->op_data
)
2994 if (get_expr_register (exp1
) == cond
->op_data
)
3006 gas_assert (cond
->op_num
< insn
->ntok
);
3007 gas_assert (cond
->op_data
< insn
->ntok
);
3008 exp1
= &insn
->tok
[cond
->op_num
];
3009 exp2
= &insn
->tok
[cond
->op_data
];
3014 if (!expr_is_equal (exp1
, exp2
))
3018 if (expr_is_equal (exp1
, exp2
))
3030 if (!xg_instruction_matches_options (insn
, rule
->options
))
3038 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
3040 bfd_boolean a_greater
= FALSE
;
3041 bfd_boolean b_greater
= FALSE
;
3043 ReqOptionList
*l_a
= a
->options
;
3044 ReqOptionList
*l_b
= b
->options
;
3046 /* We only care if they both are the same except for
3047 a const16 vs. an l32r. */
3049 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
3051 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
3052 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
3053 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
3055 if (l_or_a
->is_true
!= l_or_b
->is_true
)
3057 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
3059 /* This is the case we care about. */
3060 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
3061 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
3068 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
3069 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
3079 l_or_a
= l_or_a
->next
;
3080 l_or_b
= l_or_b
->next
;
3082 if (l_or_a
|| l_or_b
)
3091 /* Incomparable if the substitution was used differently in two cases. */
3092 if (a_greater
&& b_greater
)
3104 static TransitionRule
*
3105 xg_instruction_match (TInsn
*insn
)
3107 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
3109 gas_assert (insn
->opcode
< table
->num_opcodes
);
3111 /* Walk through all of the possible transitions. */
3112 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3114 TransitionRule
*rule
= l
->rule
;
3115 if (xg_instruction_matches_rule (insn
, rule
))
3122 /* Various Other Internal Functions. */
3125 is_unique_insn_expansion (TransitionRule
*r
)
3127 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
3129 if (r
->to_instr
->typ
!= INSTR_INSTR
)
3135 /* Check if there is exactly one relaxation for INSN that converts it to
3136 another instruction of equal or larger size. If so, and if TARG is
3137 non-null, go ahead and generate the relaxed instruction into TARG. If
3138 NARROW_ONLY is true, then only consider relaxations that widen a narrow
3139 instruction, i.e., ignore relaxations that convert to an instruction of
3140 equal size. In some contexts where this function is used, only
3141 a single widening is allowed and the NARROW_ONLY argument is used to
3142 exclude cases like ADDI being "widened" to an ADDMI, which may
3143 later be relaxed to an ADDMI/ADDI pair. */
3146 xg_is_single_relaxable_insn (TInsn
*insn
, TInsn
*targ
, bfd_boolean narrow_only
)
3148 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3150 TransitionRule
*match
= 0;
3152 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3153 gas_assert (insn
->opcode
< table
->num_opcodes
);
3155 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3157 TransitionRule
*rule
= l
->rule
;
3159 if (xg_instruction_matches_rule (insn
, rule
)
3160 && is_unique_insn_expansion (rule
)
3161 && (xg_get_single_size (insn
->opcode
) + (narrow_only
? 1 : 0)
3162 <= xg_get_single_size (rule
->to_instr
->opcode
)))
3173 xg_build_to_insn (targ
, insn
, match
->to_instr
);
3178 /* Return the maximum number of bytes this opcode can expand to. */
3181 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
3183 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3185 int max_size
= xg_get_single_size (opcode
);
3187 gas_assert (opcode
< table
->num_opcodes
);
3189 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3191 TransitionRule
*rule
= l
->rule
;
3192 BuildInstr
*build_list
;
3197 build_list
= rule
->to_instr
;
3198 if (is_unique_insn_expansion (rule
))
3200 gas_assert (build_list
->typ
== INSTR_INSTR
);
3201 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
3204 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3206 switch (build_list
->typ
)
3209 this_size
+= xg_get_single_size (build_list
->opcode
);
3211 case INSTR_LITERAL_DEF
:
3212 case INSTR_LABEL_DEF
:
3217 if (this_size
> max_size
)
3218 max_size
= this_size
;
3224 /* Return the maximum number of literal bytes this opcode can generate. */
3227 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3229 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3233 gas_assert (opcode
< table
->num_opcodes
);
3235 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3237 TransitionRule
*rule
= l
->rule
;
3238 BuildInstr
*build_list
;
3243 build_list
= rule
->to_instr
;
3244 if (is_unique_insn_expansion (rule
))
3246 gas_assert (build_list
->typ
== INSTR_INSTR
);
3247 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3250 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3252 switch (build_list
->typ
)
3254 case INSTR_LITERAL_DEF
:
3255 /* Hard-coded 4-byte literal. */
3259 case INSTR_LABEL_DEF
:
3264 if (this_size
> max_size
)
3265 max_size
= this_size
;
3272 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3274 int steps_taken
= 0;
3275 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3278 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3279 gas_assert (insn
->opcode
< table
->num_opcodes
);
3281 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3283 TransitionRule
*rule
= l
->rule
;
3285 if (xg_instruction_matches_rule (insn
, rule
))
3287 if (steps_taken
== lateral_steps
)
3297 get_special_literal_symbol (void)
3299 static symbolS
*sym
= NULL
;
3302 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3308 get_special_label_symbol (void)
3310 static symbolS
*sym
= NULL
;
3313 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3319 xg_valid_literal_expression (const expressionS
*exp
)
3341 /* This will check to see if the value can be converted into the
3342 operand type. It will return TRUE if it does not fit. */
3345 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3347 uint32 valbuf
= value
;
3348 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3354 /* Assumes: All immeds are constants. Check that all constants fit
3355 into their immeds; return FALSE if not. */
3358 xg_immeds_fit (const TInsn
*insn
)
3360 xtensa_isa isa
= xtensa_default_isa
;
3364 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3365 for (i
= 0; i
< n
; ++i
)
3367 const expressionS
*exp
= &insn
->tok
[i
];
3369 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3376 if (xg_check_operand (exp
->X_add_number
, insn
->opcode
, i
))
3381 /* The symbol should have a fixup associated with it. */
3390 /* This should only be called after we have an initial
3391 estimate of the addresses. */
3394 xg_symbolic_immeds_fit (const TInsn
*insn
,
3400 xtensa_isa isa
= xtensa_default_isa
;
3408 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3410 for (i
= 0; i
< n
; ++i
)
3412 const expressionS
*exp
= &insn
->tok
[i
];
3414 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3421 if (xg_check_operand (exp
->X_add_number
, insn
->opcode
, i
))
3427 /* Check for the worst case. */
3428 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3433 /* We only allow symbols for PC-relative references.
3434 If pc_frag == 0, then we don't have frag locations yet. */
3436 || xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0)
3439 /* If it is a weak symbol or a symbol in a different section,
3440 it cannot be known to fit at assembly time. */
3441 if (S_IS_WEAK (exp
->X_add_symbol
)
3442 || S_GET_SEGMENT (exp
->X_add_symbol
) != pc_seg
)
3444 /* For a direct call with --no-longcalls, be optimistic and
3445 assume it will be in range. If the symbol is weak and
3446 undefined, it may remain undefined at link-time, in which
3447 case it will have a zero value and almost certainly be out
3448 of range for a direct call; thus, relax for undefined weak
3449 symbols even if longcalls is not enabled. */
3450 if (is_direct_call_opcode (insn
->opcode
)
3451 && ! pc_frag
->tc_frag_data
.use_longcalls
3452 && (! S_IS_WEAK (exp
->X_add_symbol
)
3453 || S_IS_DEFINED (exp
->X_add_symbol
)))
3459 symbolP
= exp
->X_add_symbol
;
3460 sym_frag
= symbol_get_frag (symbolP
);
3461 target
= S_GET_VALUE (symbolP
) + exp
->X_add_number
;
3462 pc
= pc_frag
->fr_address
+ pc_offset
;
3464 /* If frag has yet to be reached on this pass, assume it
3465 will move by STRETCH just as we did. If this is not so,
3466 it will be because some frag between grows, and that will
3467 force another pass. Beware zero-length frags. There
3468 should be a faster way to do this. */
3471 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3472 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3477 new_offset
= target
;
3478 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3479 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3484 /* The symbol should have a fixup associated with it. */
3493 /* Return TRUE on success. */
3496 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3502 targ
->debug_line
= insn
->debug_line
;
3503 targ
->loc_directive_seen
= insn
->loc_directive_seen
;
3508 targ
->opcode
= bi
->opcode
;
3509 targ
->insn_type
= ITYPE_INSN
;
3510 targ
->is_specific_opcode
= FALSE
;
3512 for (; op
!= NULL
; op
= op
->next
)
3514 int op_num
= op
->op_num
;
3515 int op_data
= op
->op_data
;
3517 gas_assert (op
->op_num
< MAX_INSN_ARGS
);
3519 if (targ
->ntok
<= op_num
)
3520 targ
->ntok
= op_num
+ 1;
3525 set_expr_const (&targ
->tok
[op_num
], op_data
);
3528 gas_assert (op_data
< insn
->ntok
);
3529 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3532 if (insn
->extra_arg
.X_op
!= O_register
)
3534 copy_expr (&targ
->tok
[op_num
], &insn
->extra_arg
);
3537 sym
= get_special_literal_symbol ();
3538 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3539 if (insn
->tok
[op_data
].X_op
== O_tlsfunc
3540 || insn
->tok
[op_data
].X_op
== O_tlsarg
)
3541 copy_expr (&targ
->extra_arg
, &insn
->tok
[op_data
]);
3544 sym
= get_special_label_symbol ();
3545 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3547 case OP_OPERAND_HI16U
:
3548 case OP_OPERAND_LOW16U
:
3549 gas_assert (op_data
< insn
->ntok
);
3550 if (expr_is_const (&insn
->tok
[op_data
]))
3553 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3554 val
= xg_apply_userdef_op_fn (op
->typ
,
3557 targ
->tok
[op_num
].X_add_number
= val
;
3561 /* For const16 we can create relocations for these. */
3562 if (targ
->opcode
== XTENSA_UNDEFINED
3563 || (targ
->opcode
!= xtensa_const16_opcode
))
3565 gas_assert (op_data
< insn
->ntok
);
3566 /* Need to build a O_lo16 or O_hi16. */
3567 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3568 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3570 if (op
->typ
== OP_OPERAND_HI16U
)
3571 targ
->tok
[op_num
].X_op
= O_hi16
;
3572 else if (op
->typ
== OP_OPERAND_LOW16U
)
3573 targ
->tok
[op_num
].X_op
= O_lo16
;
3580 /* currently handles:
3583 OP_OPERAND_F32MINUS */
3584 if (xg_has_userdef_op_fn (op
->typ
))
3586 gas_assert (op_data
< insn
->ntok
);
3587 if (expr_is_const (&insn
->tok
[op_data
]))
3590 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3591 val
= xg_apply_userdef_op_fn (op
->typ
,
3594 targ
->tok
[op_num
].X_add_number
= val
;
3597 return FALSE
; /* We cannot use a relocation for this. */
3606 case INSTR_LITERAL_DEF
:
3608 targ
->opcode
= XTENSA_UNDEFINED
;
3609 targ
->insn_type
= ITYPE_LITERAL
;
3610 targ
->is_specific_opcode
= FALSE
;
3611 for (; op
!= NULL
; op
= op
->next
)
3613 int op_num
= op
->op_num
;
3614 int op_data
= op
->op_data
;
3615 gas_assert (op
->op_num
< MAX_INSN_ARGS
);
3617 if (targ
->ntok
<= op_num
)
3618 targ
->ntok
= op_num
+ 1;
3623 gas_assert (op_data
< insn
->ntok
);
3624 /* We can only pass resolvable literals through. */
3625 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3627 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3639 case INSTR_LABEL_DEF
:
3641 targ
->opcode
= XTENSA_UNDEFINED
;
3642 targ
->insn_type
= ITYPE_LABEL
;
3643 targ
->is_specific_opcode
= FALSE
;
3644 /* Literal with no ops is a label? */
3645 gas_assert (op
== NULL
);
3656 /* Return TRUE on success. */
3659 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3661 for (; bi
!= NULL
; bi
= bi
->next
)
3663 TInsn
*next_insn
= istack_push_space (istack
);
3665 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3672 /* Return TRUE on valid expansion. */
3675 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3677 int stack_size
= istack
->ninsn
;
3678 int steps_taken
= 0;
3679 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3682 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3683 gas_assert (insn
->opcode
< table
->num_opcodes
);
3685 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3687 TransitionRule
*rule
= l
->rule
;
3689 if (xg_instruction_matches_rule (insn
, rule
))
3691 if (lateral_steps
== steps_taken
)
3695 /* This is it. Expand the rule to the stack. */
3696 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3699 /* Check to see if it fits. */
3700 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3702 TInsn
*tinsn
= &istack
->insn
[i
];
3704 if (tinsn
->insn_type
== ITYPE_INSN
3705 && !tinsn_has_symbolic_operands (tinsn
)
3706 && !xg_immeds_fit (tinsn
))
3708 istack
->ninsn
= stack_size
;
3721 /* Relax the assembly instruction at least "min_steps".
3722 Return the number of steps taken.
3724 For relaxation to correctly terminate, every relaxation chain must
3725 terminate in one of two ways:
3727 1. If the chain from one instruction to the next consists entirely of
3728 single instructions, then the chain *must* handle all possible
3729 immediates without failing. It must not ever fail because an
3730 immediate is out of range. The MOVI.N -> MOVI -> L32R relaxation
3731 chain is one example. L32R loads 32 bits, and there cannot be an
3732 immediate larger than 32 bits, so it satisfies this condition.
3733 Single instruction relaxation chains are as defined by
3734 xg_is_single_relaxable_instruction.
3736 2. Otherwise, the chain must end in a multi-instruction expansion: e.g.,
3737 BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J
3739 Strictly speaking, in most cases you can violate condition 1 and be OK
3740 -- in particular when the last two instructions have the same single
3741 size. But nevertheless, you should guarantee the above two conditions.
3743 We could fix this so that single-instruction expansions correctly
3744 terminate when they can't handle the range, but the error messages are
3745 worse, and it actually turns out that in every case but one (18-bit wide
3746 branches), you need a multi-instruction expansion to get the full range
3747 anyway. And because 18-bit branches are handled identically to 15-bit
3748 branches, there isn't any point in changing it. */
3751 xg_assembly_relax (IStack
*istack
,
3754 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3755 offsetT pc_offset
, /* offset in fragment */
3756 int min_steps
, /* minimum conversion steps */
3757 long stretch
) /* number of bytes stretched so far */
3759 int steps_taken
= 0;
3761 /* Some of its immeds don't fit. Try to build a relaxed version.
3762 This may go through a couple of stages of single instruction
3763 transformations before we get there. */
3765 TInsn single_target
;
3767 int lateral_steps
= 0;
3768 int istack_size
= istack
->ninsn
;
3770 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3771 && steps_taken
>= min_steps
)
3773 istack_push (istack
, insn
);
3776 current_insn
= *insn
;
3778 /* Walk through all of the single instruction expansions. */
3779 while (xg_is_single_relaxable_insn (¤t_insn
, &single_target
, FALSE
))
3782 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3785 if (steps_taken
>= min_steps
)
3787 istack_push (istack
, &single_target
);
3791 current_insn
= single_target
;
3794 /* Now check for a multi-instruction expansion. */
3795 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3797 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3800 if (steps_taken
>= min_steps
)
3802 istack_push (istack
, ¤t_insn
);
3807 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3809 if (steps_taken
>= min_steps
)
3813 istack
->ninsn
= istack_size
;
3816 /* It's not going to work -- use the original. */
3817 istack_push (istack
, insn
);
3823 xg_finish_frag (char *last_insn
,
3824 enum xtensa_relax_statesE frag_state
,
3825 enum xtensa_relax_statesE slot0_state
,
3827 bfd_boolean is_insn
)
3829 /* Finish off this fragment so that it has at LEAST the desired
3830 max_growth. If it doesn't fit in this fragment, close this one
3831 and start a new one. In either case, return a pointer to the
3832 beginning of the growth area. */
3836 frag_grow (max_growth
);
3837 old_frag
= frag_now
;
3839 frag_now
->fr_opcode
= last_insn
;
3841 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3843 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3844 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3846 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3847 xtensa_set_frag_assembly_state (frag_now
);
3849 /* Just to make sure that we did not split it up. */
3850 gas_assert (old_frag
->fr_next
== frag_now
);
3854 /* Return TRUE if the target frag is one of the next non-empty frags. */
3857 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3862 for (; fragP
; fragP
= fragP
->fr_next
)
3864 if (fragP
== target
)
3866 if (fragP
->fr_fix
!= 0)
3868 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3870 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3871 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3873 if (fragP
->fr_type
== rs_space
)
3881 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3883 xtensa_isa isa
= xtensa_default_isa
;
3885 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3890 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) != 1
3891 && xtensa_opcode_is_jump (isa
, insn
->opcode
) != 1)
3894 for (i
= 0; i
< num_ops
; i
++)
3896 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3902 if (target_op
== -1)
3905 if (insn
->ntok
<= target_op
)
3908 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3911 sym
= insn
->tok
[target_op
].X_add_symbol
;
3915 if (insn
->tok
[target_op
].X_add_number
!= 0)
3918 target_frag
= symbol_get_frag (sym
);
3919 if (target_frag
== NULL
)
3922 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3923 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3931 xg_add_branch_and_loop_targets (TInsn
*insn
)
3933 xtensa_isa isa
= xtensa_default_isa
;
3934 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3936 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3939 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3940 && insn
->tok
[i
].X_op
== O_symbol
)
3941 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3945 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3946 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3950 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3952 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3953 && insn
->tok
[i
].X_op
== O_symbol
)
3955 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3956 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3957 if (S_IS_DEFINED (sym
))
3958 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3965 /* Return FALSE if no error. */
3968 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3973 switch (instr_spec
->typ
)
3976 new_insn
->insn_type
= ITYPE_INSN
;
3977 new_insn
->opcode
= instr_spec
->opcode
;
3979 case INSTR_LITERAL_DEF
:
3980 new_insn
->insn_type
= ITYPE_LITERAL
;
3981 new_insn
->opcode
= XTENSA_UNDEFINED
;
3983 case INSTR_LABEL_DEF
:
3986 new_insn
->is_specific_opcode
= FALSE
;
3987 new_insn
->debug_line
= old_insn
->debug_line
;
3988 new_insn
->loc_directive_seen
= old_insn
->loc_directive_seen
;
3990 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3993 const expressionS
*src_exp
;
3999 /* The expression must be the constant. */
4000 gas_assert (b_op
->op_num
< MAX_INSN_ARGS
);
4001 exp
= &new_insn
->tok
[b_op
->op_num
];
4002 set_expr_const (exp
, b_op
->op_data
);
4006 gas_assert (b_op
->op_num
< MAX_INSN_ARGS
);
4007 gas_assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
4008 src_exp
= &old_insn
->tok
[b_op
->op_data
];
4009 exp
= &new_insn
->tok
[b_op
->op_num
];
4010 copy_expr (exp
, src_exp
);
4015 as_bad (_("can't handle generation of literal/labels yet"));
4019 as_bad (_("can't handle undefined OP TYPE"));
4024 new_insn
->ntok
= num_ops
;
4029 /* Return TRUE if it was simplified. */
4032 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
4034 TransitionRule
*rule
;
4035 BuildInstr
*insn_spec
;
4037 if (old_insn
->is_specific_opcode
|| !density_supported
)
4040 rule
= xg_instruction_match (old_insn
);
4044 insn_spec
= rule
->to_instr
;
4045 /* There should only be one. */
4046 gas_assert (insn_spec
!= NULL
);
4047 gas_assert (insn_spec
->next
== NULL
);
4048 if (insn_spec
->next
!= NULL
)
4051 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
4057 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
4058 l32i.n. (2) Check the number of operands. (3) Place the instruction
4059 tokens into the stack or relax it and place multiple
4060 instructions/literals onto the stack. Return FALSE if no error. */
4063 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
4067 bfd_boolean do_expand
;
4069 tinsn_init (&new_insn
);
4071 /* Narrow it if we can. xg_simplify_insn now does all the
4072 appropriate checking (e.g., for the density option). */
4073 if (xg_simplify_insn (orig_insn
, &new_insn
))
4074 orig_insn
= &new_insn
;
4076 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
4078 if (orig_insn
->ntok
< noperands
)
4080 as_bad (ngettext ("found %d operand for '%s': Expected %d",
4081 "found %d operands for '%s': Expected %d",
4084 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
4088 if (orig_insn
->ntok
> noperands
)
4089 as_warn (ngettext ("found %d operand for '%s': Expected %d",
4090 "found %d operands for '%s': Expected %d",
4093 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
4096 /* If there are not enough operands, we will assert above. If there
4097 are too many, just cut out the extras here. */
4098 orig_insn
->ntok
= noperands
;
4100 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
4103 /* Special case for extui opcode which has constraints not handled
4104 by the ordinary operand encoding checks. The number of operands
4105 and related syntax issues have already been checked. */
4106 if (orig_insn
->opcode
== xtensa_extui_opcode
)
4108 int shiftimm
= orig_insn
->tok
[2].X_add_number
;
4109 int maskimm
= orig_insn
->tok
[3].X_add_number
;
4110 if (shiftimm
+ maskimm
> 32)
4112 as_bad (_("immediate operands sum to greater than 32"));
4117 /* If the instruction will definitely need to be relaxed, it is better
4118 to expand it now for better scheduling. Decide whether to expand
4120 do_expand
= (!orig_insn
->is_specific_opcode
&& use_transform ());
4122 /* Calls should be expanded to longcalls only in the backend relaxation
4123 so that the assembly scheduler will keep the L32R/CALLX instructions
4125 if (is_direct_call_opcode (orig_insn
->opcode
))
4128 if (tinsn_has_symbolic_operands (orig_insn
))
4130 /* The values of symbolic operands are not known yet, so only expand
4131 now if an operand is "complex" (e.g., difference of symbols) and
4132 will have to be stored as a literal regardless of the value. */
4133 if (!tinsn_has_complex_operands (orig_insn
))
4136 else if (xg_immeds_fit (orig_insn
))
4140 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
4142 istack_push (istack
, orig_insn
);
4148 /* Return TRUE if the section flags are marked linkonce
4149 or the name is .gnu.linkonce.*. */
4151 static int linkonce_len
= sizeof (".gnu.linkonce.") - 1;
4154 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
4156 flagword flags
, link_once_flags
;
4158 flags
= bfd_section_flags (sec
);
4159 link_once_flags
= (flags
& SEC_LINK_ONCE
);
4161 /* Flags might not be set yet. */
4162 if (!link_once_flags
4163 && strncmp (segment_name (sec
), ".gnu.linkonce.", linkonce_len
) == 0)
4164 link_once_flags
= SEC_LINK_ONCE
;
4166 return (link_once_flags
!= 0);
4171 xtensa_add_literal_sym (symbolS
*sym
)
4175 l
= XNEW (sym_list
);
4177 l
->next
= literal_syms
;
4183 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
4185 static int lit_num
= 0;
4186 static char name
[256];
4189 sprintf (name
, ".L_lit_sym%d", lit_num
);
4191 /* Create a local symbol. If it is in a linkonce section, we have to
4192 be careful to make sure that if it is used in a relocation that the
4193 symbol will be in the output file. */
4194 if (get_is_linkonce_section (stdoutput
, sec
))
4196 symbolP
= symbol_new (name
, sec
, frag
, 0);
4197 S_CLEAR_EXTERNAL (symbolP
);
4198 /* symbolP->local = 1; */
4201 symbolP
= symbol_new (name
, sec
, frag
, 0);
4203 xtensa_add_literal_sym (symbolP
);
4210 /* Currently all literals that are generated here are 32-bit L32R targets. */
4213 xg_assemble_literal (/* const */ TInsn
*insn
)
4216 symbolS
*lit_sym
= NULL
;
4217 bfd_reloc_code_real_type reloc
;
4218 bfd_boolean pcrel
= FALSE
;
4221 /* size = 4 for L32R. It could easily be larger when we move to
4222 larger constants. Add a parameter later. */
4223 offsetT litsize
= 4;
4224 offsetT litalign
= 2; /* 2^2 = 4 */
4225 expressionS saved_loc
;
4226 expressionS
* emit_val
;
4228 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
4230 gas_assert (insn
->insn_type
== ITYPE_LITERAL
);
4231 gas_assert (insn
->ntok
== 1); /* must be only one token here */
4233 xtensa_switch_to_literal_fragment (&state
);
4235 emit_val
= &insn
->tok
[0];
4236 if (emit_val
->X_op
== O_big
)
4238 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
4241 /* This happens when someone writes a "movi a2, big_number". */
4242 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4243 _("invalid immediate"));
4244 xtensa_restore_emit_state (&state
);
4249 /* Force a 4-byte align here. Note that this opens a new frag, so all
4250 literals done with this function have a frag to themselves. That's
4251 important for the way text section literals work. */
4252 frag_align (litalign
, 0, 0);
4253 record_alignment (now_seg
, litalign
);
4255 switch (emit_val
->X_op
)
4265 p
= frag_more (litsize
);
4266 xtensa_set_frag_assembly_state (frag_now
);
4267 reloc
= map_operator_to_reloc (emit_val
->X_op
, TRUE
);
4268 if (emit_val
->X_add_symbol
)
4269 emit_val
->X_op
= O_symbol
;
4271 emit_val
->X_op
= O_constant
;
4272 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
4273 litsize
, emit_val
, pcrel
, reloc
);
4277 emit_expr (emit_val
, litsize
);
4281 gas_assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
4282 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4283 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4284 lit_sym
= frag_now
->fr_symbol
;
4287 xtensa_restore_emit_state (&state
);
4293 xg_assemble_literal_space (/* const */ int size
, int slot
)
4296 /* We might have to do something about this alignment. It only
4297 takes effect if something is placed here. */
4298 offsetT litalign
= 2; /* 2^2 = 4 */
4299 fragS
*lit_saved_frag
;
4301 gas_assert (size
% 4 == 0);
4303 xtensa_switch_to_literal_fragment (&state
);
4305 /* Force a 4-byte align here. */
4306 frag_align (litalign
, 0, 0);
4307 record_alignment (now_seg
, litalign
);
4311 lit_saved_frag
= frag_now
;
4312 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4313 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4314 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4317 xtensa_restore_emit_state (&state
);
4318 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4322 /* Put in a fixup record based on the opcode.
4323 Return TRUE on success. */
4326 xg_add_opcode_fix (TInsn
*tinsn
,
4334 xtensa_opcode opcode
= tinsn
->opcode
;
4335 bfd_reloc_code_real_type reloc
;
4336 reloc_howto_type
*howto
;
4340 reloc
= BFD_RELOC_NONE
;
4342 /* First try the special cases for "alternate" relocs. */
4343 if (opcode
== xtensa_l32r_opcode
)
4345 if (fragP
->tc_frag_data
.use_absolute_literals
)
4346 reloc
= encode_alt_reloc (slot
);
4348 else if (opcode
== xtensa_const16_opcode
)
4350 if (exp
->X_op
== O_lo16
)
4352 reloc
= encode_reloc (slot
);
4353 exp
->X_op
= O_symbol
;
4355 else if (exp
->X_op
== O_hi16
)
4357 reloc
= encode_alt_reloc (slot
);
4358 exp
->X_op
= O_symbol
;
4362 if (opnum
!= get_relaxable_immed (opcode
))
4364 as_bad (_("invalid relocation for operand %i of '%s'"),
4365 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4369 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4370 into the symbol table where the generic portions of the assembler
4371 won't know what to do with them. */
4372 if (exp
->X_op
== O_lo16
|| exp
->X_op
== O_hi16
)
4374 as_bad (_("invalid expression for operand %i of '%s'"),
4375 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4379 /* Next try the generic relocs. */
4380 if (reloc
== BFD_RELOC_NONE
)
4381 reloc
= encode_reloc (slot
);
4382 if (reloc
== BFD_RELOC_NONE
)
4384 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4388 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4391 as_bad (_("undefined symbol for opcode \"%s\""),
4392 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4396 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4397 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, exp
,
4398 howto
->pc_relative
, reloc
);
4399 the_fix
->fx_no_overflow
= 1;
4400 the_fix
->tc_fix_data
.X_add_symbol
= exp
->X_add_symbol
;
4401 the_fix
->tc_fix_data
.X_add_number
= exp
->X_add_number
;
4402 the_fix
->tc_fix_data
.slot
= slot
;
4409 xg_emit_insn_to_buf (TInsn
*tinsn
,
4413 bfd_boolean build_fix
)
4415 static xtensa_insnbuf insnbuf
= NULL
;
4416 bfd_boolean has_symbolic_immed
= FALSE
;
4417 bfd_boolean ok
= TRUE
;
4420 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4422 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4423 if (has_symbolic_immed
&& build_fix
)
4426 xtensa_format fmt
= xg_get_single_format (tinsn
->opcode
);
4427 int slot
= xg_get_single_slot (tinsn
->opcode
);
4428 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4429 expressionS
*exp
= &tinsn
->tok
[opnum
];
4431 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, slot
, exp
, fragP
, offset
))
4434 fragP
->tc_frag_data
.is_insn
= TRUE
;
4435 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4436 (unsigned char *) buf
, 0);
4442 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4444 symbolS
*sym
= get_special_literal_symbol ();
4448 gas_assert (insn
->insn_type
== ITYPE_INSN
);
4449 for (i
= 0; i
< insn
->ntok
; i
++)
4450 if (insn
->tok
[i
].X_add_symbol
== sym
)
4451 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4457 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4459 symbolS
*sym
= get_special_label_symbol ();
4461 for (i
= 0; i
< insn
->ntok
; i
++)
4462 if (insn
->tok
[i
].X_add_symbol
== sym
)
4463 insn
->tok
[i
].X_add_symbol
= label_sym
;
4468 /* Return TRUE if the instruction can write to the specified
4469 integer register. */
4472 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4476 xtensa_isa isa
= xtensa_default_isa
;
4478 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4480 for (i
= 0; i
< num_ops
; i
++)
4483 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4484 if ((inout
== 'o' || inout
== 'm')
4485 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4487 xtensa_regfile opnd_rf
=
4488 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4489 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4491 if ((insn
->tok
[i
].X_op
== O_register
)
4492 && (insn
->tok
[i
].X_add_number
== regnum
))
4502 is_bad_loopend_opcode (const TInsn
*tinsn
)
4504 xtensa_opcode opcode
= tinsn
->opcode
;
4506 if (opcode
== XTENSA_UNDEFINED
)
4509 if (opcode
== xtensa_call0_opcode
4510 || opcode
== xtensa_callx0_opcode
4511 || opcode
== xtensa_call4_opcode
4512 || opcode
== xtensa_callx4_opcode
4513 || opcode
== xtensa_call8_opcode
4514 || opcode
== xtensa_callx8_opcode
4515 || opcode
== xtensa_call12_opcode
4516 || opcode
== xtensa_callx12_opcode
4517 || opcode
== xtensa_isync_opcode
4518 || opcode
== xtensa_ret_opcode
4519 || opcode
== xtensa_ret_n_opcode
4520 || opcode
== xtensa_retw_opcode
4521 || opcode
== xtensa_retw_n_opcode
4522 || opcode
== xtensa_waiti_opcode
4523 || opcode
== xtensa_rsr_lcount_opcode
)
4530 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4531 This allows the debugger to add unaligned labels.
4532 Also, the assembler generates stabs labels that need
4533 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4536 is_unaligned_label (symbolS
*sym
)
4538 const char *name
= S_GET_NAME (sym
);
4539 static size_t fake_size
= 0;
4543 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4546 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4548 fake_size
= strlen (FAKE_LABEL_NAME
);
4551 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4552 && (name
[fake_size
] == 'F'
4553 || name
[fake_size
] == 'L'
4554 || (name
[fake_size
] == 'e'
4555 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4563 next_non_empty_frag (const fragS
*fragP
)
4565 fragS
*next_fragP
= fragP
->fr_next
;
4567 /* Sometimes an empty will end up here due storage allocation issues.
4568 So we have to skip until we find something legit. */
4569 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4570 next_fragP
= next_fragP
->fr_next
;
4572 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4580 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4582 xtensa_opcode out_opcode
;
4583 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4585 if (next_fragP
== NULL
)
4588 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4589 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4591 *opcode
= out_opcode
;
4599 frag_format_size (const fragS
*fragP
)
4601 static xtensa_insnbuf insnbuf
= NULL
;
4602 xtensa_isa isa
= xtensa_default_isa
;
4607 insnbuf
= xtensa_insnbuf_alloc (isa
);
4610 return XTENSA_UNDEFINED
;
4612 xtensa_insnbuf_from_chars (isa
, insnbuf
,
4613 (unsigned char *) fragP
->fr_literal
, 0);
4615 fmt
= xtensa_format_decode (isa
, insnbuf
);
4616 if (fmt
== XTENSA_UNDEFINED
)
4617 return XTENSA_UNDEFINED
;
4618 fmt_size
= xtensa_format_length (isa
, fmt
);
4620 /* If the next format won't be changing due to relaxation, just
4621 return the length of the first format. */
4622 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4625 /* If during relaxation we have to pull an instruction out of a
4626 multi-slot instruction, we will return the more conservative
4627 number. This works because alignment on bigger instructions
4628 is more restrictive than alignment on smaller instructions.
4629 This is more conservative than we would like, but it happens
4632 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4635 /* If we aren't doing one of our own relaxations or it isn't
4636 slot-based, then the insn size won't change. */
4637 if (fragP
->fr_type
!= rs_machine_dependent
)
4639 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4642 /* If an instruction is about to grow, return the longer size. */
4643 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4644 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
4645 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP3
)
4647 /* For most frags at RELAX_IMMED_STEPX, with X > 0, the first
4648 instruction in the relaxed version is of length 3. (The case
4649 where we have to pull the instruction out of a FLIX bundle
4650 is handled conservatively above.) However, frags with opcodes
4651 that are expanding to wide branches end up having formats that
4652 are not determinable by the RELAX_IMMED_STEPX enumeration, and
4653 we can't tell directly what format the relaxer picked. This
4654 is a wart in the design of the relaxer that should someday be
4655 fixed, but would require major changes, or at least should
4656 be accompanied by major changes to make use of that data.
4658 In any event, we can tell that we are expanding from a single-slot
4659 format to a wider one with the logic below. */
4662 int relaxed_size
= fmt_size
+ fragP
->tc_frag_data
.text_expansion
[0];
4664 for (i
= 0; i
< xtensa_isa_num_formats (isa
); i
++)
4666 if (relaxed_size
== xtensa_format_length (isa
, i
))
4667 return relaxed_size
;
4673 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4674 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4681 next_frag_format_size (const fragS
*fragP
)
4683 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4684 return frag_format_size (next_fragP
);
4688 /* In early Xtensa Processors, for reasons that are unclear, the ISA
4689 required two-byte instructions to be treated as three-byte instructions
4690 for loop instruction alignment. This restriction was removed beginning
4691 with Xtensa LX. Now the only requirement on loop instruction alignment
4692 is that the first instruction of the loop must appear at an address that
4693 does not cross a fetch boundary. */
4696 get_loop_align_size (int insn_size
)
4698 if (insn_size
== XTENSA_UNDEFINED
)
4699 return xtensa_fetch_width
;
4701 if (enforce_three_byte_loop_align
&& insn_size
== 2)
4708 /* If the next legit fragment is an end-of-loop marker,
4709 switch its state so it will instantiate a NOP. */
4712 update_next_frag_state (fragS
*fragP
)
4714 fragS
*next_fragP
= fragP
->fr_next
;
4715 fragS
*new_target
= NULL
;
4719 /* We are guaranteed there will be one of these... */
4720 while (!(next_fragP
->fr_type
== rs_machine_dependent
4721 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4722 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4723 next_fragP
= next_fragP
->fr_next
;
4725 gas_assert (next_fragP
->fr_type
== rs_machine_dependent
4726 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4727 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4729 /* ...and one of these. */
4730 new_target
= next_fragP
->fr_next
;
4731 while (!(new_target
->fr_type
== rs_machine_dependent
4732 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4733 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4734 new_target
= new_target
->fr_next
;
4736 gas_assert (new_target
->fr_type
== rs_machine_dependent
4737 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4738 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4741 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4743 if (next_fragP
->fr_type
== rs_machine_dependent
4744 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4746 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4750 next_fragP
= next_fragP
->fr_next
;
4756 next_frag_is_branch_target (const fragS
*fragP
)
4758 /* Sometimes an empty will end up here due to storage allocation issues,
4759 so we have to skip until we find something legit. */
4760 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4762 if (fragP
->tc_frag_data
.is_branch_target
)
4764 if (fragP
->fr_fix
!= 0)
4772 next_frag_is_loop_target (const fragS
*fragP
)
4774 /* Sometimes an empty will end up here due storage allocation issues.
4775 So we have to skip until we find something legit. */
4776 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4778 if (fragP
->tc_frag_data
.is_loop_target
)
4780 if (fragP
->fr_fix
!= 0)
4787 /* As specified in the relaxation table, when a loop instruction is
4788 relaxed, there are 24 bytes between the loop instruction itself and
4789 the first instruction in the loop. */
4791 #define RELAXED_LOOP_INSN_BYTES 24
4794 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4796 const fragS
*next_fragp
= fragp
->fr_next
;
4797 xtensa_opcode next_opcode
;
4799 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4802 /* Sometimes an empty will end up here due to storage allocation issues,
4803 so we have to skip until we find something legit. */
4804 while (next_fragp
->fr_fix
== 0)
4805 next_fragp
= next_fragp
->fr_next
;
4807 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4810 /* There is some implicit knowledge encoded in here.
4811 The LOOP instructions that are NOT RELAX_IMMED have
4812 been relaxed. Note that we can assume that the LOOP
4813 instruction is in slot 0 because loops aren't bundleable. */
4814 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4815 return get_expanded_loop_offset (next_opcode
) + RELAXED_LOOP_INSN_BYTES
;
4821 /* Mark a location where we can later insert literal frags. Update
4822 the section's literal_pool_loc, so subsequent literals can be
4823 placed nearest to their use. */
4826 xtensa_mark_literal_pool_location (void)
4828 /* Any labels pointing to the current location need
4829 to be adjusted to after the literal pool. */
4830 fragS
*pool_location
;
4832 if (use_literal_section
)
4835 /* We stash info in these frags so we can later move the literal's
4836 fixes into this frchain's fix list. */
4837 pool_location
= frag_now
;
4838 frag_now
->tc_frag_data
.lit_frchain
= frchain_now
;
4839 frag_now
->tc_frag_data
.literal_frag
= frag_now
;
4840 /* Just record this frag. */
4841 xtensa_maybe_create_literal_pool_frag (FALSE
, FALSE
);
4842 frag_variant (rs_machine_dependent
, 0, 0,
4843 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4844 xtensa_set_frag_assembly_state (frag_now
);
4845 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
4846 frag_variant (rs_machine_dependent
, 0, 0,
4847 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4848 xtensa_set_frag_assembly_state (frag_now
);
4850 set_literal_pool_location (now_seg
, pool_location
);
4854 /* Build a nop of the correct size into tinsn. */
4857 build_nop (TInsn
*tinsn
, int size
)
4863 tinsn
->opcode
= xtensa_nop_n_opcode
;
4865 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4866 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4870 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4872 tinsn
->opcode
= xtensa_or_opcode
;
4873 set_expr_const (&tinsn
->tok
[0], 1);
4874 set_expr_const (&tinsn
->tok
[1], 1);
4875 set_expr_const (&tinsn
->tok
[2], 1);
4879 tinsn
->opcode
= xtensa_nop_opcode
;
4881 gas_assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4886 /* Assemble a NOP of the requested size in the buffer. User must have
4887 allocated "buf" with at least "size" bytes. */
4890 assemble_nop (int size
, char *buf
)
4892 static xtensa_insnbuf insnbuf
= NULL
;
4895 build_nop (&tinsn
, size
);
4898 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4900 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4901 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4902 (unsigned char *) buf
, 0);
4906 /* Return the number of bytes for the offset of the expanded loop
4907 instruction. This should be incorporated into the relaxation
4908 specification but is hard-coded here. This is used to auto-align
4909 the loop instruction. It is invalid to call this function if the
4910 configuration does not have loops or if the opcode is not a loop
4914 get_expanded_loop_offset (xtensa_opcode opcode
)
4916 /* This is the OFFSET of the loop instruction in the expanded loop.
4917 This MUST correspond directly to the specification of the loop
4918 expansion. It will be validated on fragment conversion. */
4919 gas_assert (opcode
!= XTENSA_UNDEFINED
);
4920 if (opcode
== xtensa_loop_opcode
)
4922 if (opcode
== xtensa_loopnez_opcode
)
4924 if (opcode
== xtensa_loopgtz_opcode
)
4926 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4932 get_literal_pool_location (segT seg
)
4936 struct litpool_seg
*lps
= litpool_seg_list
.next
;
4937 struct litpool_frag
*lpf
;
4938 for ( ; lps
&& lps
->seg
->id
!= seg
->id
; lps
= lps
->next
)
4942 for (lpf
= lps
->frag_list
.prev
; lpf
->fragP
; lpf
= lpf
->prev
)
4943 { /* Skip "candidates" for now. */
4944 if (lpf
->fragP
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
&&
4948 /* Must convert a lower-priority pool. */
4949 for (lpf
= lps
->frag_list
.prev
; lpf
->fragP
; lpf
= lpf
->prev
)
4951 if (lpf
->fragP
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
)
4954 /* Still no match -- try for a low priority pool. */
4955 for (lpf
= lps
->frag_list
.prev
; lpf
->fragP
; lpf
= lpf
->prev
)
4957 if (lpf
->fragP
->fr_subtype
== RELAX_LITERAL_POOL_CANDIDATE_BEGIN
)
4962 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4967 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4969 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4973 /* Set frag assembly state should be called when a new frag is
4974 opened and after a frag has been closed. */
4977 xtensa_set_frag_assembly_state (fragS
*fragP
)
4979 if (!density_supported
)
4980 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4982 /* This function is called from subsegs_finish, which is called
4983 after xtensa_end, so we can't use "use_transform" or
4984 "use_schedule" here. */
4985 if (!directive_state
[directive_transform
])
4986 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4987 if (directive_state
[directive_longcalls
])
4988 fragP
->tc_frag_data
.use_longcalls
= TRUE
;
4989 fragP
->tc_frag_data
.use_absolute_literals
=
4990 directive_state
[directive_absolute_literals
];
4991 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4996 relaxable_section (asection
*sec
)
4998 return ((sec
->flags
& SEC_DEBUGGING
) == 0
4999 && strcmp (sec
->name
, ".eh_frame") != 0);
5004 xtensa_mark_frags_for_org (void)
5008 /* Walk over each fragment of all of the current segments. If we find
5009 a .org frag in any of the segments, mark all frags prior to it as
5010 "no transform", which will prevent linker optimizations from messing
5011 up the .org distance. This should be done after
5012 xtensa_find_unmarked_state_frags, because we don't want to worry here
5013 about that function trashing the data we save here. */
5015 for (seclist
= &stdoutput
->sections
;
5016 seclist
&& *seclist
;
5017 seclist
= &(*seclist
)->next
)
5019 segT sec
= *seclist
;
5020 segment_info_type
*seginfo
;
5023 flags
= bfd_section_flags (sec
);
5024 if (flags
& SEC_DEBUGGING
)
5026 if (!(flags
& SEC_ALLOC
))
5029 seginfo
= seg_info (sec
);
5030 if (seginfo
&& seginfo
->frchainP
)
5032 fragS
*last_fragP
= seginfo
->frchainP
->frch_root
;
5033 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
5034 fragP
= fragP
->fr_next
)
5036 /* cvt_frag_to_fill has changed the fr_type of org frags to
5037 rs_fill, so use the value as cached in rs_subtype here. */
5038 if (fragP
->fr_subtype
== RELAX_ORG
)
5040 while (last_fragP
!= fragP
->fr_next
)
5042 last_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
5043 last_fragP
= last_fragP
->fr_next
;
5053 xtensa_find_unmarked_state_frags (void)
5057 /* Walk over each fragment of all of the current segments. For each
5058 unmarked fragment, mark it with the same info as the previous
5060 for (seclist
= &stdoutput
->sections
;
5061 seclist
&& *seclist
;
5062 seclist
= &(*seclist
)->next
)
5064 segT sec
= *seclist
;
5065 segment_info_type
*seginfo
;
5068 flags
= bfd_section_flags (sec
);
5069 if (flags
& SEC_DEBUGGING
)
5071 if (!(flags
& SEC_ALLOC
))
5074 seginfo
= seg_info (sec
);
5075 if (seginfo
&& seginfo
->frchainP
)
5077 fragS
*last_fragP
= 0;
5078 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
5079 fragP
= fragP
->fr_next
)
5081 if (fragP
->fr_fix
!= 0
5082 && !fragP
->tc_frag_data
.is_assembly_state_set
)
5084 if (last_fragP
== 0)
5086 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
5087 _("assembly state not set for first frag in section %s"),
5092 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
5093 fragP
->tc_frag_data
.is_no_density
=
5094 last_fragP
->tc_frag_data
.is_no_density
;
5095 fragP
->tc_frag_data
.is_no_transform
=
5096 last_fragP
->tc_frag_data
.is_no_transform
;
5097 fragP
->tc_frag_data
.use_longcalls
=
5098 last_fragP
->tc_frag_data
.use_longcalls
;
5099 fragP
->tc_frag_data
.use_absolute_literals
=
5100 last_fragP
->tc_frag_data
.use_absolute_literals
;
5103 if (fragP
->tc_frag_data
.is_assembly_state_set
)
5112 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
5114 void *unused ATTRIBUTE_UNUSED
)
5116 flagword flags
= bfd_section_flags (sec
);
5117 segment_info_type
*seginfo
= seg_info (sec
);
5118 fragS
*frag
= seginfo
->frchainP
->frch_root
;
5120 if (flags
& SEC_CODE
)
5122 xtensa_isa isa
= xtensa_default_isa
;
5123 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
5124 while (frag
!= NULL
)
5126 if (frag
->tc_frag_data
.is_branch_target
)
5129 addressT branch_align
, frag_addr
;
5132 xtensa_insnbuf_from_chars
5133 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
5134 fmt
= xtensa_format_decode (isa
, insnbuf
);
5135 op_size
= xtensa_format_length (isa
, fmt
);
5136 branch_align
= 1 << branch_align_power (sec
);
5137 frag_addr
= frag
->fr_address
% branch_align
;
5138 if (frag_addr
+ op_size
> branch_align
)
5139 as_warn_where (frag
->fr_file
, frag
->fr_line
,
5140 _("unaligned branch target: %d bytes at 0x%lx"),
5141 op_size
, (long) frag
->fr_address
);
5143 frag
= frag
->fr_next
;
5145 xtensa_insnbuf_free (isa
, insnbuf
);
5151 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
5153 void *unused ATTRIBUTE_UNUSED
)
5155 flagword flags
= bfd_section_flags (sec
);
5156 segment_info_type
*seginfo
= seg_info (sec
);
5157 fragS
*frag
= seginfo
->frchainP
->frch_root
;
5158 xtensa_isa isa
= xtensa_default_isa
;
5160 if (flags
& SEC_CODE
)
5162 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
5163 while (frag
!= NULL
)
5165 if (frag
->tc_frag_data
.is_first_loop_insn
)
5171 if (frag
->fr_fix
== 0)
5172 frag
= next_non_empty_frag (frag
);
5176 xtensa_insnbuf_from_chars
5177 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
5178 fmt
= xtensa_format_decode (isa
, insnbuf
);
5179 op_size
= xtensa_format_length (isa
, fmt
);
5180 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
5182 if (frag_addr
+ op_size
> xtensa_fetch_width
)
5183 as_warn_where (frag
->fr_file
, frag
->fr_line
,
5184 _("unaligned loop: %d bytes at 0x%lx"),
5185 op_size
, (long) frag
->fr_address
);
5188 frag
= frag
->fr_next
;
5190 xtensa_insnbuf_free (isa
, insnbuf
);
5196 xg_apply_fix_value (fixS
*fixP
, valueT val
)
5198 xtensa_isa isa
= xtensa_default_isa
;
5199 static xtensa_insnbuf insnbuf
= NULL
;
5200 static xtensa_insnbuf slotbuf
= NULL
;
5203 bfd_boolean alt_reloc
;
5204 xtensa_opcode opcode
;
5205 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5207 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
)
5209 as_fatal (_("unexpected fix"));
5213 insnbuf
= xtensa_insnbuf_alloc (isa
);
5214 slotbuf
= xtensa_insnbuf_alloc (isa
);
5217 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
5218 fmt
= xtensa_format_decode (isa
, insnbuf
);
5219 if (fmt
== XTENSA_UNDEFINED
)
5220 as_fatal (_("undecodable fix"));
5221 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5222 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5223 if (opcode
== XTENSA_UNDEFINED
)
5224 as_fatal (_("undecodable fix"));
5226 /* CONST16 immediates are not PC-relative, despite the fact that we
5227 reuse the normal PC-relative operand relocations for the low part
5228 of a CONST16 operand. */
5229 if (opcode
== xtensa_const16_opcode
)
5232 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
5233 get_relaxable_immed (opcode
), val
,
5234 fixP
->fx_file
, fixP
->fx_line
);
5236 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5237 xtensa_insnbuf_to_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
5243 /* External Functions and Other GAS Hooks. */
5246 xtensa_target_format (void)
5248 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
5253 xtensa_file_arch_init (bfd
*abfd
)
5255 bfd_set_private_flags (abfd
, 0x100 | 0x200);
5260 md_number_to_chars (char *buf
, valueT val
, int n
)
5262 if (target_big_endian
)
5263 number_to_chars_bigendian (buf
, val
, n
);
5265 number_to_chars_littleendian (buf
, val
, n
);
5269 xg_init_global_config (void)
5271 target_big_endian
= XCHAL_HAVE_BE
;
5273 density_supported
= XCHAL_HAVE_DENSITY
;
5274 absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
5275 xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
5277 directive_state
[directive_density
] = XCHAL_HAVE_DENSITY
;
5278 directive_state
[directive_absolute_literals
] = XSHAL_USE_ABSOLUTE_LITERALS
;
5280 microarch_earliest
= XTENSA_MARCH_EARLIEST
;
5284 xtensa_init (int argc ATTRIBUTE_UNUSED
, char **argv ATTRIBUTE_UNUSED
)
5286 xg_init_global_config ();
5289 /* This function is called once, at assembler startup time. It should
5290 set up all the tables, etc. that the MD part of the assembler will
5296 segT current_section
= now_seg
;
5297 int current_subsec
= now_subseg
;
5301 xtensa_default_isa
= xtensa_isa_init (0, 0);
5302 isa
= xtensa_default_isa
;
5304 linkrelax
= opt_linkrelax
;
5306 /* Set up the literal sections. */
5307 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
5309 subseg_set (current_section
, current_subsec
);
5311 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
5312 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
5313 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
5314 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
5315 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
5316 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
5317 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
5318 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
5319 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
5320 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
5321 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
5322 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
5323 xtensa_extui_opcode
= xtensa_opcode_lookup (isa
, "extui");
5324 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
5325 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
5326 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
5327 xtensa_j_opcode
= xtensa_opcode_lookup (isa
, "j");
5328 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
5329 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
5330 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
5331 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
5332 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
5333 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
5334 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
5335 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
5336 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
5337 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
5338 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
5339 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
5340 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
5341 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
5343 for (i
= 0; i
< xtensa_isa_num_formats (isa
); i
++)
5345 int format_slots
= xtensa_format_num_slots (isa
, i
);
5346 if (format_slots
> config_max_slots
)
5347 config_max_slots
= format_slots
;
5350 xg_init_vinsn (&cur_vinsn
);
5352 xtensa_num_pipe_stages
= xtensa_isa_num_pipe_stages (isa
);
5354 init_op_placement_info_table ();
5356 /* Set up the assembly state. */
5357 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5358 xtensa_set_frag_assembly_state (frag_now
);
5360 if (!use_literal_section
)
5361 xtensa_mark_literal_pool_location ();
5365 /* TC_INIT_FIX_DATA hook */
5368 xtensa_init_fix_data (fixS
*x
)
5370 x
->tc_fix_data
.slot
= 0;
5371 x
->tc_fix_data
.X_add_symbol
= NULL
;
5372 x
->tc_fix_data
.X_add_number
= 0;
5376 /* tc_frob_label hook */
5379 xtensa_frob_label (symbolS
*sym
)
5383 if (cur_vinsn
.inside_bundle
)
5385 as_bad (_("labels are not valid inside bundles"));
5389 freq
= get_subseg_target_freq (now_seg
, now_subseg
);
5391 /* Since the label was already attached to a frag associated with the
5392 previous basic block, it now needs to be reset to the current frag. */
5393 symbol_set_frag (sym
, frag_now
);
5394 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5396 if (generating_literals
)
5397 xtensa_add_literal_sym (sym
);
5399 xtensa_add_insn_label (sym
);
5401 if (symbol_get_tc (sym
)->is_loop_target
)
5403 if ((get_last_insn_flags (now_seg
, now_subseg
)
5404 & FLAG_IS_BAD_LOOPEND
) != 0)
5405 as_bad (_("invalid last instruction for a zero-overhead loop"));
5407 xtensa_set_frag_assembly_state (frag_now
);
5408 frag_var (rs_machine_dependent
, 4, 4, RELAX_LOOP_END
,
5409 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5411 xtensa_set_frag_assembly_state (frag_now
);
5412 xtensa_move_labels (frag_now
, 0);
5415 /* No target aligning in the absolute section. */
5416 if (now_seg
!= absolute_section
5417 && !is_unaligned_label (sym
)
5418 && !generating_literals
)
5420 xtensa_set_frag_assembly_state (frag_now
);
5422 if (do_align_targets ())
5423 frag_var (rs_machine_dependent
, 0, (int) freq
,
5424 RELAX_DESIRE_ALIGN_IF_TARGET
, frag_now
->fr_symbol
,
5425 frag_now
->fr_offset
, NULL
);
5427 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
5428 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5429 xtensa_set_frag_assembly_state (frag_now
);
5430 xtensa_move_labels (frag_now
, 0);
5433 /* We need to mark the following properties even if we aren't aligning. */
5435 /* If the label is already known to be a branch target, i.e., a
5436 forward branch, mark the frag accordingly. Backward branches
5437 are handled by xg_add_branch_and_loop_targets. */
5438 if (symbol_get_tc (sym
)->is_branch_target
)
5439 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5441 /* Loops only go forward, so they can be identified here. */
5442 if (symbol_get_tc (sym
)->is_loop_target
)
5443 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5445 dwarf2_emit_label (sym
);
5449 /* tc_unrecognized_line hook */
5452 xtensa_unrecognized_line (int ch
)
5457 if (cur_vinsn
.inside_bundle
== 0)
5459 /* PR8110: Cannot emit line number info inside a FLIX bundle
5460 when using --gstabs. Temporarily disable debug info. */
5461 generate_lineno_debug ();
5462 if (debug_type
== DEBUG_STABS
)
5464 xt_saved_debug_type
= debug_type
;
5465 debug_type
= DEBUG_NONE
;
5468 cur_vinsn
.inside_bundle
= 1;
5472 as_bad (_("extra opening brace"));
5478 if (cur_vinsn
.inside_bundle
)
5479 finish_vinsn (&cur_vinsn
);
5482 as_bad (_("extra closing brace"));
5487 as_bad (_("syntax error"));
5494 /* md_flush_pending_output hook */
5497 xtensa_flush_pending_output (void)
5499 /* This line fixes a bug where automatically generated gstabs info
5500 separates a function label from its entry instruction, ending up
5501 with the literal position between the function label and the entry
5502 instruction and crashing code. It only happens with --gstabs and
5503 --text-section-literals, and when several other obscure relaxation
5504 conditions are met. */
5505 if (outputting_stabs_line_debug
)
5508 if (cur_vinsn
.inside_bundle
)
5509 as_bad (_("missing closing brace"));
5511 /* If there is a non-zero instruction fragment, close it. */
5512 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5514 frag_wane (frag_now
);
5516 xtensa_set_frag_assembly_state (frag_now
);
5518 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5520 xtensa_clear_insn_labels ();
5524 /* We had an error while parsing an instruction. The string might look
5525 like this: "insn arg1, arg2 }". If so, we need to see the closing
5526 brace and reset some fields. Otherwise, the vinsn never gets closed
5527 and the num_slots field will grow past the end of the array of slots,
5528 and bad things happen. */
5531 error_reset_cur_vinsn (void)
5533 if (cur_vinsn
.inside_bundle
)
5535 if (*input_line_pointer
== '}'
5536 || *(input_line_pointer
- 1) == '}'
5537 || *(input_line_pointer
- 2) == '}')
5538 xg_clear_vinsn (&cur_vinsn
);
5544 md_assemble (char *str
)
5546 xtensa_isa isa
= xtensa_default_isa
;
5549 bfd_boolean has_underbar
= FALSE
;
5550 char *arg_strings
[MAX_INSN_ARGS
];
5552 TInsn orig_insn
; /* Original instruction from the input. */
5554 tinsn_init (&orig_insn
);
5556 /* Split off the opcode. */
5557 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5558 opname
= xstrndup (str
, opnamelen
);
5560 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5563 as_bad (_("syntax error"));
5567 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5570 /* Check for an underbar prefix. */
5573 has_underbar
= TRUE
;
5577 orig_insn
.insn_type
= ITYPE_INSN
;
5579 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5580 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5582 /* Special case: Check for "CALLXn.TLS" pseudo op. If found, grab its
5583 extra argument and set the opcode to "CALLXn". */
5584 if (orig_insn
.opcode
== XTENSA_UNDEFINED
5585 && strncasecmp (opname
, "callx", 5) == 0)
5587 unsigned long window_size
;
5590 window_size
= strtoul (opname
+ 5, &suffix
, 10);
5591 if (suffix
!= opname
+ 5
5592 && (window_size
== 0
5595 || window_size
== 12)
5596 && strcasecmp (suffix
, ".tls") == 0)
5598 switch (window_size
)
5600 case 0: orig_insn
.opcode
= xtensa_callx0_opcode
; break;
5601 case 4: orig_insn
.opcode
= xtensa_callx4_opcode
; break;
5602 case 8: orig_insn
.opcode
= xtensa_callx8_opcode
; break;
5603 case 12: orig_insn
.opcode
= xtensa_callx12_opcode
; break;
5607 as_bad (_("wrong number of operands for '%s'"), opname
);
5610 bfd_reloc_code_real_type reloc
;
5611 char *old_input_line_pointer
;
5612 expressionS
*tok
= &orig_insn
.extra_arg
;
5614 old_input_line_pointer
= input_line_pointer
;
5615 input_line_pointer
= arg_strings
[num_args
- 1];
5618 if (tok
->X_op
== O_symbol
5619 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
5620 == BFD_RELOC_XTENSA_TLS_CALL
))
5621 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
5623 as_bad (_("bad relocation expression for '%s'"), opname
);
5625 input_line_pointer
= old_input_line_pointer
;
5631 /* Special case: Check for "j.l" pseudo op. */
5632 if (orig_insn
.opcode
== XTENSA_UNDEFINED
5633 && strncasecmp (opname
, "j.l", 3) == 0)
5636 as_bad (_("wrong number of operands for '%s'"), opname
);
5639 char *old_input_line_pointer
;
5640 expressionS
*tok
= &orig_insn
.extra_arg
;
5642 old_input_line_pointer
= input_line_pointer
;
5643 input_line_pointer
= arg_strings
[num_args
- 1];
5645 expression_maybe_register (xtensa_jx_opcode
, 0, tok
);
5646 input_line_pointer
= old_input_line_pointer
;
5649 orig_insn
.opcode
= xtensa_j_opcode
;
5653 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5655 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5656 if (fmt
== XTENSA_UNDEFINED
)
5658 as_bad (_("unknown opcode or format name '%s'"), opname
);
5659 error_reset_cur_vinsn ();
5662 if (!cur_vinsn
.inside_bundle
)
5664 as_bad (_("format names only valid inside bundles"));
5665 error_reset_cur_vinsn ();
5668 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5669 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5671 cur_vinsn
.format
= fmt
;
5672 free (has_underbar
? opname
- 1 : opname
);
5673 error_reset_cur_vinsn ();
5677 /* Parse the arguments. */
5678 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5680 as_bad (_("syntax error"));
5681 error_reset_cur_vinsn ();
5685 /* Free the opcode and argument strings, now that they've been parsed. */
5686 free (has_underbar
? opname
- 1 : opname
);
5688 while (num_args
-- > 0)
5689 free (arg_strings
[num_args
]);
5691 /* Get expressions for invisible operands. */
5692 if (get_invisible_operands (&orig_insn
))
5694 error_reset_cur_vinsn ();
5698 /* Check for the right number and type of arguments. */
5699 if (tinsn_check_arguments (&orig_insn
))
5701 error_reset_cur_vinsn ();
5705 /* Record the line number for each TInsn, because a FLIX bundle may be
5706 spread across multiple input lines and individual instructions may be
5707 moved around in some cases. */
5708 orig_insn
.loc_directive_seen
= dwarf2_loc_directive_seen
;
5709 dwarf2_where (&orig_insn
.debug_line
);
5710 dwarf2_consume_line_info ();
5712 xg_add_branch_and_loop_targets (&orig_insn
);
5714 /* Check that immediate value for ENTRY is >= 16. */
5715 if (orig_insn
.opcode
== xtensa_entry_opcode
&& orig_insn
.ntok
>= 3)
5717 expressionS
*exp
= &orig_insn
.tok
[2];
5718 if (exp
->X_op
== O_constant
&& exp
->X_add_number
< 16)
5719 as_warn (_("entry instruction with stack decrement < 16"));
5723 assemble_tokens (opcode, tok, ntok);
5724 expand the tokens from the orig_insn into the
5725 stack of instructions that will not expand
5726 unless required at relaxation time. */
5728 if (!cur_vinsn
.inside_bundle
)
5729 emit_single_op (&orig_insn
);
5730 else /* We are inside a bundle. */
5732 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5733 cur_vinsn
.num_slots
++;
5734 if (*input_line_pointer
== '}'
5735 || *(input_line_pointer
- 1) == '}'
5736 || *(input_line_pointer
- 2) == '}')
5737 finish_vinsn (&cur_vinsn
);
5740 /* We've just emitted a new instruction so clear the list of labels. */
5741 xtensa_clear_insn_labels ();
5743 xtensa_check_frag_count ();
5747 /* HANDLE_ALIGN hook */
5749 /* For a .align directive, we mark the previous block with the alignment
5750 information. This will be placed in the object file in the
5751 property section corresponding to this section. */
5754 xtensa_handle_align (fragS
*fragP
)
5757 && ! fragP
->tc_frag_data
.is_literal
5758 && (fragP
->fr_type
== rs_align
5759 || fragP
->fr_type
== rs_align_code
)
5760 && fragP
->fr_offset
> 0
5761 && now_seg
!= bss_section
)
5763 fragP
->tc_frag_data
.is_align
= TRUE
;
5764 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5767 if (fragP
->fr_type
== rs_align_test
)
5770 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5772 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5773 _("unaligned entry instruction"));
5776 if (linkrelax
&& fragP
->fr_type
== rs_org
)
5777 fragP
->fr_subtype
= RELAX_ORG
;
5781 /* TC_FRAG_INIT hook */
5784 xtensa_frag_init (fragS
*frag
)
5786 xtensa_set_frag_assembly_state (frag
);
5791 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5797 /* Round up a section size to the appropriate boundary. */
5800 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5802 return size
; /* Byte alignment is fine. */
5807 md_pcrel_from (fixS
*fixP
)
5810 static xtensa_insnbuf insnbuf
= NULL
;
5811 static xtensa_insnbuf slotbuf
= NULL
;
5814 xtensa_opcode opcode
;
5817 xtensa_isa isa
= xtensa_default_isa
;
5818 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5819 bfd_boolean alt_reloc
;
5821 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5824 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
5829 insnbuf
= xtensa_insnbuf_alloc (isa
);
5830 slotbuf
= xtensa_insnbuf_alloc (isa
);
5833 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5834 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) insn_p
, 0);
5835 fmt
= xtensa_format_decode (isa
, insnbuf
);
5837 if (fmt
== XTENSA_UNDEFINED
)
5838 as_fatal (_("bad instruction format"));
5840 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5841 as_fatal (_("invalid relocation"));
5843 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5844 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5846 /* Check for "alternate" relocations (operand not specified). None
5847 of the current uses for these are really PC-relative. */
5848 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5850 if (opcode
!= xtensa_l32r_opcode
5851 && opcode
!= xtensa_const16_opcode
)
5852 as_fatal (_("invalid relocation for '%s' instruction"),
5853 xtensa_opcode_name (isa
, opcode
));
5857 opnum
= get_relaxable_immed (opcode
);
5859 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5860 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5862 as_bad_where (fixP
->fx_file
,
5864 _("invalid relocation for operand %d of '%s'"),
5865 opnum
, xtensa_opcode_name (isa
, opcode
));
5868 return 0 - opnd_value
;
5872 /* TC_FORCE_RELOCATION hook */
5875 xtensa_force_relocation (fixS
*fix
)
5877 switch (fix
->fx_r_type
)
5879 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5880 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5881 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5882 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5883 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5884 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5885 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5886 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5887 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5888 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5889 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5890 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5891 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5892 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5893 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5894 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5900 if (linkrelax
&& fix
->fx_addsy
5901 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5904 return generic_force_reloc (fix
);
5908 /* TC_VALIDATE_FIX_SUB hook */
5911 xtensa_validate_fix_sub (fixS
*fix
)
5913 segT add_symbol_segment
, sub_symbol_segment
;
5915 /* The difference of two symbols should be resolved by the assembler when
5916 linkrelax is not set. If the linker may relax the section containing
5917 the symbols, then an Xtensa DIFF relocation must be generated so that
5918 the linker knows to adjust the difference value. */
5919 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
5922 /* Make sure both symbols are in the same segment, and that segment is
5923 "normal" and relaxable. If the segment is not "normal", then the
5924 fix is not valid. If the segment is not "relaxable", then the fix
5925 should have been handled earlier. */
5926 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
5927 if (! SEG_NORMAL (add_symbol_segment
) ||
5928 ! relaxable_section (add_symbol_segment
))
5930 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
5931 return (sub_symbol_segment
== add_symbol_segment
);
5935 /* NO_PSEUDO_DOT hook */
5937 /* This function has nothing to do with pseudo dots, but this is the
5938 nearest macro to where the check needs to take place. FIXME: This
5942 xtensa_check_inside_bundle (void)
5944 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5945 as_bad (_("directives are not valid inside bundles"));
5947 /* This function must always return FALSE because it is called via a
5948 macro that has nothing to do with bundling. */
5953 /* md_elf_section_change_hook */
5956 xtensa_elf_section_change_hook (void)
5958 /* Set up the assembly state. */
5959 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5960 xtensa_set_frag_assembly_state (frag_now
);
5962 if (!use_literal_section
5963 && seg_info (now_seg
)->tc_segment_info_data
.literal_pool_loc
== NULL
5964 && !xtensa_is_init_fini (now_seg
))
5965 xtensa_mark_literal_pool_location ();
5969 /* tc_fix_adjustable hook */
5972 xtensa_fix_adjustable (fixS
*fixP
)
5974 /* We need the symbol name for the VTABLE entries. */
5975 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5976 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5983 /* tc_symbol_new_hook */
5985 symbolS
*expr_symbols
= NULL
;
5988 xtensa_symbol_new_hook (symbolS
*sym
)
5990 if (is_leb128_expr
&& S_GET_SEGMENT (sym
) == expr_section
)
5992 symbol_get_tc (sym
)->next_expr_symbol
= expr_symbols
;
5999 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg
)
6001 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
6004 /* Subtracted symbols are only allowed for a few relocation types, and
6005 unless linkrelax is enabled, they should not make it to this point. */
6006 if (fixP
->fx_subsy
&& !(linkrelax
&& (fixP
->fx_r_type
== BFD_RELOC_32
6007 || fixP
->fx_r_type
== BFD_RELOC_16
6008 || fixP
->fx_r_type
== BFD_RELOC_8
)))
6009 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("expression too complex"));
6011 switch (fixP
->fx_r_type
)
6013 case BFD_RELOC_32_PCREL
:
6019 bfd_boolean neg
= S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
6020 < S_GET_VALUE (fixP
->fx_subsy
);
6022 switch (fixP
->fx_r_type
)
6025 fixP
->fx_r_type
= neg
6026 ? BFD_RELOC_XTENSA_NDIFF8
: BFD_RELOC_XTENSA_PDIFF8
;
6027 fixP
->fx_signed
= 0;
6030 fixP
->fx_r_type
= neg
6031 ? BFD_RELOC_XTENSA_NDIFF16
: BFD_RELOC_XTENSA_PDIFF16
;
6032 fixP
->fx_signed
= 0;
6035 fixP
->fx_r_type
= neg
6036 ? BFD_RELOC_XTENSA_NDIFF32
: BFD_RELOC_XTENSA_PDIFF32
;
6037 fixP
->fx_signed
= 0;
6043 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
6044 - S_GET_VALUE (fixP
->fx_subsy
));
6046 /* The difference value gets written out, and the DIFF reloc
6047 identifies the address of the subtracted symbol (i.e., the one
6048 with the lowest address). */
6050 fixP
->fx_offset
-= val
;
6051 fixP
->fx_subsy
= NULL
;
6053 else if (! fixP
->fx_addsy
)
6058 else if (S_GET_SEGMENT (fixP
->fx_addsy
) == absolute_section
)
6060 val
= S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
;
6066 case BFD_RELOC_XTENSA_PLT
:
6067 md_number_to_chars (fixpos
, val
, fixP
->fx_size
);
6068 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
6071 case BFD_RELOC_XTENSA_TLSDESC_FN
:
6072 case BFD_RELOC_XTENSA_TLSDESC_ARG
:
6073 case BFD_RELOC_XTENSA_TLS_TPOFF
:
6074 case BFD_RELOC_XTENSA_TLS_DTPOFF
:
6075 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6076 md_number_to_chars (fixpos
, 0, fixP
->fx_size
);
6077 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
6080 case BFD_RELOC_XTENSA_SLOT0_OP
:
6081 case BFD_RELOC_XTENSA_SLOT1_OP
:
6082 case BFD_RELOC_XTENSA_SLOT2_OP
:
6083 case BFD_RELOC_XTENSA_SLOT3_OP
:
6084 case BFD_RELOC_XTENSA_SLOT4_OP
:
6085 case BFD_RELOC_XTENSA_SLOT5_OP
:
6086 case BFD_RELOC_XTENSA_SLOT6_OP
:
6087 case BFD_RELOC_XTENSA_SLOT7_OP
:
6088 case BFD_RELOC_XTENSA_SLOT8_OP
:
6089 case BFD_RELOC_XTENSA_SLOT9_OP
:
6090 case BFD_RELOC_XTENSA_SLOT10_OP
:
6091 case BFD_RELOC_XTENSA_SLOT11_OP
:
6092 case BFD_RELOC_XTENSA_SLOT12_OP
:
6093 case BFD_RELOC_XTENSA_SLOT13_OP
:
6094 case BFD_RELOC_XTENSA_SLOT14_OP
:
6097 /* Write the tentative value of a PC-relative relocation to a
6098 local symbol into the instruction. The value will be ignored
6099 by the linker, and it makes the object file disassembly
6100 readable when all branch targets are encoded in relocations. */
6102 gas_assert (fixP
->fx_addsy
);
6103 if (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
6104 && !S_FORCE_RELOC (fixP
->fx_addsy
, 1))
6106 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
6107 - md_pcrel_from (fixP
));
6108 (void) xg_apply_fix_value (fixP
, val
);
6111 else if (! fixP
->fx_addsy
)
6114 if (xg_apply_fix_value (fixP
, val
))
6119 case BFD_RELOC_XTENSA_ASM_EXPAND
:
6120 case BFD_RELOC_XTENSA_TLS_FUNC
:
6121 case BFD_RELOC_XTENSA_TLS_ARG
:
6122 case BFD_RELOC_XTENSA_TLS_CALL
:
6123 case BFD_RELOC_XTENSA_SLOT0_ALT
:
6124 case BFD_RELOC_XTENSA_SLOT1_ALT
:
6125 case BFD_RELOC_XTENSA_SLOT2_ALT
:
6126 case BFD_RELOC_XTENSA_SLOT3_ALT
:
6127 case BFD_RELOC_XTENSA_SLOT4_ALT
:
6128 case BFD_RELOC_XTENSA_SLOT5_ALT
:
6129 case BFD_RELOC_XTENSA_SLOT6_ALT
:
6130 case BFD_RELOC_XTENSA_SLOT7_ALT
:
6131 case BFD_RELOC_XTENSA_SLOT8_ALT
:
6132 case BFD_RELOC_XTENSA_SLOT9_ALT
:
6133 case BFD_RELOC_XTENSA_SLOT10_ALT
:
6134 case BFD_RELOC_XTENSA_SLOT11_ALT
:
6135 case BFD_RELOC_XTENSA_SLOT12_ALT
:
6136 case BFD_RELOC_XTENSA_SLOT13_ALT
:
6137 case BFD_RELOC_XTENSA_SLOT14_ALT
:
6138 /* These all need to be resolved at link-time. Do nothing now. */
6141 case BFD_RELOC_VTABLE_INHERIT
:
6142 case BFD_RELOC_VTABLE_ENTRY
:
6147 as_bad (_("unhandled local relocation fix %s"),
6148 bfd_get_reloc_code_name (fixP
->fx_r_type
));
6154 md_atof (int type
, char *litP
, int *sizeP
)
6156 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
6161 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
6163 return total_frag_text_expansion (fragP
);
6167 /* Translate internal representation of relocation info to BFD target
6171 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
6175 reloc
= XNEW (arelent
);
6176 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
6177 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
6178 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6180 /* Make sure none of our internal relocations make it this far.
6181 They'd better have been fully resolved by this point. */
6182 gas_assert ((int) fixp
->fx_r_type
> 0);
6184 reloc
->addend
= fixp
->fx_offset
;
6186 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
6187 if (reloc
->howto
== NULL
)
6189 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6190 _("cannot represent `%s' relocation in object file"),
6191 bfd_get_reloc_code_name (fixp
->fx_r_type
));
6192 free (reloc
->sym_ptr_ptr
);
6197 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
6198 as_fatal (_("internal error; cannot generate `%s' relocation"),
6199 bfd_get_reloc_code_name (fixp
->fx_r_type
));
6205 /* Checks for resource conflicts between instructions. */
6207 /* The func unit stuff could be implemented as bit-vectors rather
6208 than the iterative approach here. If it ends up being too
6209 slow, we will switch it. */
6212 new_resource_table (void *data
,
6215 unit_num_copies_func uncf
,
6216 opcode_num_units_func onuf
,
6217 opcode_funcUnit_use_unit_func ouuf
,
6218 opcode_funcUnit_use_stage_func ousf
)
6221 resource_table
*rt
= XNEW (resource_table
);
6223 rt
->cycles
= cycles
;
6224 rt
->allocated_cycles
= cycles
;
6226 rt
->unit_num_copies
= uncf
;
6227 rt
->opcode_num_units
= onuf
;
6228 rt
->opcode_unit_use
= ouuf
;
6229 rt
->opcode_unit_stage
= ousf
;
6231 rt
->units
= XCNEWVEC (unsigned char *, cycles
);
6232 for (i
= 0; i
< cycles
; i
++)
6233 rt
->units
[i
] = XCNEWVEC (unsigned char, nu
);
6240 clear_resource_table (resource_table
*rt
)
6243 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
6244 for (j
= 0; j
< rt
->num_units
; j
++)
6245 rt
->units
[i
][j
] = 0;
6249 /* We never shrink it, just fake it into thinking so. */
6252 resize_resource_table (resource_table
*rt
, int cycles
)
6256 rt
->cycles
= cycles
;
6257 if (cycles
<= rt
->allocated_cycles
)
6260 old_cycles
= rt
->allocated_cycles
;
6261 rt
->allocated_cycles
= cycles
;
6263 rt
->units
= XRESIZEVEC (unsigned char *, rt
->units
, rt
->allocated_cycles
);
6264 for (i
= 0; i
< old_cycles
; i
++)
6265 rt
->units
[i
] = XRESIZEVEC (unsigned char, rt
->units
[i
], rt
->num_units
);
6266 for (i
= old_cycles
; i
< cycles
; i
++)
6267 rt
->units
[i
] = XCNEWVEC (unsigned char, rt
->num_units
);
6272 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6275 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6277 for (i
= 0; i
< uses
; i
++)
6279 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6280 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6281 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
6282 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
6283 if (copies_in_use
>= copies
)
6291 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6294 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6296 for (i
= 0; i
< uses
; i
++)
6298 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6299 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6300 /* Note that this allows resources to be oversubscribed. That's
6301 essential to the way the optional scheduler works.
6302 resources_available reports when a resource is over-subscribed,
6303 so it's easy to tell. */
6304 rt
->units
[stage
+ cycle
][unit
]++;
6310 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6313 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6315 for (i
= 0; i
< uses
; i
++)
6317 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6318 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6319 gas_assert (rt
->units
[stage
+ cycle
][unit
] > 0);
6320 rt
->units
[stage
+ cycle
][unit
]--;
6325 /* Wrapper functions make parameterized resource reservation
6329 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
6331 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
6337 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
6339 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
6344 /* Note that this function does not check issue constraints, but
6345 solely whether the hardware is available to execute the given
6346 instructions together. It also doesn't check if the tinsns
6347 write the same state, or access the same tieports. That is
6348 checked by check_t1_t2_reads_and_writes. */
6351 resources_conflict (vliw_insn
*vinsn
)
6354 static resource_table
*rt
= NULL
;
6356 /* This is the most common case by far. Optimize it. */
6357 if (vinsn
->num_slots
== 1)
6362 xtensa_isa isa
= xtensa_default_isa
;
6363 rt
= new_resource_table
6364 (isa
, xtensa_num_pipe_stages
,
6365 xtensa_isa_num_funcUnits (isa
),
6366 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
6367 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
6368 opcode_funcUnit_use_unit
,
6369 opcode_funcUnit_use_stage
);
6372 clear_resource_table (rt
);
6374 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6376 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
6378 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
6385 /* finish_vinsn, emit_single_op and helper functions. */
6387 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
6388 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
6389 static void xg_assemble_vliw_tokens (vliw_insn
*);
6392 /* We have reached the end of a bundle; emit into the frag. */
6395 finish_vinsn (vliw_insn
*vinsn
)
6401 if (find_vinsn_conflicts (vinsn
))
6403 xg_clear_vinsn (vinsn
);
6407 /* First, find a format that works. */
6408 if (vinsn
->format
== XTENSA_UNDEFINED
)
6409 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6411 slots
= xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
);
6413 && produce_flix
== FLIX_NONE
)
6415 as_bad (_("The option \"--no-allow-flix\" prohibits multi-slot flix."));
6416 xg_clear_vinsn (vinsn
);
6420 if (vinsn
->format
== XTENSA_UNDEFINED
)
6422 as_bad (_("couldn't find a valid instruction format"));
6423 fprintf (stderr
, _(" ops were: "));
6424 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6425 fprintf (stderr
, _(" %s;"),
6426 xtensa_opcode_name (xtensa_default_isa
,
6427 vinsn
->slots
[i
].opcode
));
6428 fprintf (stderr
, _("\n"));
6429 xg_clear_vinsn (vinsn
);
6433 if (vinsn
->num_slots
!= slots
)
6435 as_bad (_("mismatch for format '%s': #slots = %d, #opcodes = %d"),
6436 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
6437 slots
, vinsn
->num_slots
);
6438 xg_clear_vinsn (vinsn
);
6442 if (resources_conflict (vinsn
))
6444 as_bad (_("illegal resource usage in bundle"));
6445 fprintf (stderr
, " ops were: ");
6446 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6447 fprintf (stderr
, " %s;",
6448 xtensa_opcode_name (xtensa_default_isa
,
6449 vinsn
->slots
[i
].opcode
));
6450 fprintf (stderr
, "\n");
6451 xg_clear_vinsn (vinsn
);
6455 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6457 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
6459 symbolS
*lit_sym
= NULL
;
6461 bfd_boolean e
= FALSE
;
6462 bfd_boolean saved_density
= density_supported
;
6464 /* We don't want to narrow ops inside multi-slot bundles. */
6465 if (vinsn
->num_slots
> 1)
6466 density_supported
= FALSE
;
6468 istack_init (&slotstack
);
6469 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
6471 vinsn
->slots
[i
].opcode
=
6472 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6474 vinsn
->slots
[i
].ntok
= 0;
6477 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
6483 density_supported
= saved_density
;
6487 xg_clear_vinsn (vinsn
);
6491 for (j
= 0; j
< slotstack
.ninsn
; j
++)
6493 TInsn
*insn
= &slotstack
.insn
[j
];
6494 if (insn
->insn_type
== ITYPE_LITERAL
)
6496 gas_assert (lit_sym
== NULL
);
6497 lit_sym
= xg_assemble_literal (insn
);
6501 gas_assert (insn
->insn_type
== ITYPE_INSN
);
6503 xg_resolve_literals (insn
, lit_sym
);
6504 if (j
!= slotstack
.ninsn
- 1)
6505 emit_single_op (insn
);
6509 if (vinsn
->num_slots
> 1)
6511 if (opcode_fits_format_slot
6512 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6515 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6519 emit_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6520 if (vinsn
->format
== XTENSA_UNDEFINED
)
6521 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6523 vinsn
->slots
[i
].opcode
6524 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6527 vinsn
->slots
[i
].ntok
= 0;
6532 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6533 vinsn
->format
= XTENSA_UNDEFINED
;
6538 /* Now check resource conflicts on the modified bundle. */
6539 if (resources_conflict (vinsn
))
6541 as_bad (_("illegal resource usage in bundle"));
6542 fprintf (stderr
, " ops were: ");
6543 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6544 fprintf (stderr
, " %s;",
6545 xtensa_opcode_name (xtensa_default_isa
,
6546 vinsn
->slots
[i
].opcode
));
6547 fprintf (stderr
, "\n");
6548 xg_clear_vinsn (vinsn
);
6552 /* First, find a format that works. */
6553 if (vinsn
->format
== XTENSA_UNDEFINED
)
6554 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6556 xg_assemble_vliw_tokens (vinsn
);
6558 xg_clear_vinsn (vinsn
);
6560 xtensa_check_frag_count ();
6564 /* Given an vliw instruction, what conflicts are there in register
6565 usage and in writes to states and queues?
6567 This function does two things:
6568 1. Reports an error when a vinsn contains illegal combinations
6569 of writes to registers states or queues.
6570 2. Marks individual tinsns as not relaxable if the combination
6571 contains antidependencies.
6573 Job 2 handles things like swap semantics in instructions that need
6574 to be relaxed. For example,
6578 normally would be relaxed to
6583 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6585 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6587 then we can't relax it into
6590 { add a0, a1, a0 ; add a2, a0, a4 ; }
6592 because the value of a0 is trashed before the second add can read it. */
6594 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6597 find_vinsn_conflicts (vliw_insn
*vinsn
)
6601 xtensa_isa isa
= xtensa_default_isa
;
6603 gas_assert (!past_xtensa_end
);
6605 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6607 TInsn
*op1
= &vinsn
->slots
[i
];
6608 if (op1
->is_specific_opcode
)
6609 op1
->keep_wide
= TRUE
;
6611 op1
->keep_wide
= FALSE
;
6614 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6616 TInsn
*op1
= &vinsn
->slots
[i
];
6618 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6621 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6625 TInsn
*op2
= &vinsn
->slots
[j
];
6626 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6627 switch (conflict_type
)
6630 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6631 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6632 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6635 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6636 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6637 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6640 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"),
6641 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6642 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6645 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"),
6646 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6647 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6650 /* Everything is OK. */
6653 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6654 || conflict_type
== 'a');
6661 as_bad (_("multiple branches or jumps in the same bundle"));
6669 /* Check how the state used by t1 and t2 relate.
6672 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6673 case B: no relationship between what is read and written (both could
6674 read the same reg though)
6675 case C: t1 writes a register t2 writes (a register conflict within a
6677 case D: t1 writes a state that t2 also writes
6678 case E: t1 writes a tie queue that t2 also writes
6679 case F: two volatile queue accesses
6683 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6685 xtensa_isa isa
= xtensa_default_isa
;
6686 xtensa_regfile t1_regfile
, t2_regfile
;
6688 int t1_base_reg
, t1_last_reg
;
6689 int t2_base_reg
, t2_last_reg
;
6690 char t1_inout
, t2_inout
;
6692 char conflict
= 'b';
6697 bfd_boolean t1_volatile
= FALSE
;
6698 bfd_boolean t2_volatile
= FALSE
;
6700 /* Check registers. */
6701 for (j
= 0; j
< t2
->ntok
; j
++)
6703 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6706 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6707 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6708 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6710 for (i
= 0; i
< t1
->ntok
; i
++)
6712 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6715 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6717 if (t1_regfile
!= t2_regfile
)
6720 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6721 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6723 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6724 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6726 if (t1_inout
== 'm' || t1_inout
== 'o'
6727 || t2_inout
== 'm' || t2_inout
== 'o')
6734 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6735 t1_last_reg
= (t1_base_reg
6736 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6738 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6740 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6742 if (t1_reg
!= t2_reg
)
6745 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6751 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6757 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6765 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6766 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6767 for (j
= 0; j
< t2_states
; j
++)
6769 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6770 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6771 for (i
= 0; i
< t1_states
; i
++)
6773 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6774 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6775 if (t1_so
!= t2_so
|| xtensa_state_is_shared_or (isa
, t1_so
) == 1)
6778 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6784 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6790 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6795 /* Check tieports. */
6796 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6797 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6798 for (j
= 0; j
< t2_interfaces
; j
++)
6800 xtensa_interface t2_int
6801 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6802 int t2_class
= xtensa_interface_class_id (isa
, t2_int
);
6804 t2_inout
= xtensa_interface_inout (isa
, t2_int
);
6805 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1)
6808 for (i
= 0; i
< t1_interfaces
; i
++)
6810 xtensa_interface t1_int
6811 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6812 int t1_class
= xtensa_interface_class_id (isa
, t1_int
);
6814 t1_inout
= xtensa_interface_inout (isa
, t1_int
);
6815 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1)
6818 if (t1_volatile
&& t2_volatile
&& (t1_class
== t2_class
))
6821 if (t1_int
!= t2_int
)
6824 if (t2_inout
== 'i' && t1_inout
== 'o')
6830 if (t1_inout
== 'i' && t2_inout
== 'o')
6836 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6845 static xtensa_format
6846 xg_find_narrowest_format (vliw_insn
*vinsn
)
6848 /* Right now we assume that the ops within the vinsn are properly
6849 ordered for the slots that the programmer wanted them in. In
6850 other words, we don't rearrange the ops in hopes of finding a
6851 better format. The scheduler handles that. */
6853 xtensa_isa isa
= xtensa_default_isa
;
6854 xtensa_format format
;
6855 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6857 if (vinsn
->num_slots
== 1)
6858 return xg_get_single_format (vinsn
->slots
[0].opcode
);
6860 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6863 xg_copy_vinsn (&v_copy
, vinsn
);
6864 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6868 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6870 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6872 v_copy
.slots
[slot
].opcode
=
6873 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6874 v_copy
.slots
[slot
].ntok
= 0;
6877 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6880 else if (v_copy
.num_slots
> 1)
6883 /* Try the widened version. */
6884 if (!v_copy
.slots
[slot
].keep_wide
6885 && !v_copy
.slots
[slot
].is_specific_opcode
6886 && xg_is_single_relaxable_insn (&v_copy
.slots
[slot
],
6888 && opcode_fits_format_slot (widened
.opcode
,
6891 v_copy
.slots
[slot
] = widened
;
6896 if (fit
== v_copy
.num_slots
)
6898 xg_copy_vinsn (vinsn
, &v_copy
);
6899 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6900 vinsn
->format
= format
;
6906 if (format
== xtensa_isa_num_formats (isa
))
6907 return XTENSA_UNDEFINED
;
6913 /* Return the additional space needed in a frag
6914 for possible relaxations of any ops in a VLIW insn.
6915 Also fill out the relaxations that might be required of
6916 each tinsn in the vinsn. */
6919 relaxation_requirements (vliw_insn
*vinsn
, bfd_boolean
*pfinish_frag
)
6921 bfd_boolean finish_frag
= FALSE
;
6922 int extra_space
= 0;
6925 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6927 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6928 if (!tinsn_has_symbolic_operands (tinsn
))
6930 /* A narrow instruction could be widened later to help
6931 alignment issues. */
6932 if (xg_is_single_relaxable_insn (tinsn
, 0, TRUE
)
6933 && !tinsn
->is_specific_opcode
6934 && vinsn
->num_slots
== 1)
6936 /* Difference in bytes between narrow and wide insns... */
6938 tinsn
->subtype
= RELAX_NARROW
;
6943 if (workaround_b_j_loop_end
6944 && tinsn
->opcode
== xtensa_jx_opcode
6945 && use_transform ())
6947 /* Add 2 of these. */
6948 extra_space
+= 3; /* for the nop size */
6949 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6952 /* Need to assemble it with space for the relocation. */
6953 if (xg_is_relaxable_insn (tinsn
, 0)
6954 && !tinsn
->is_specific_opcode
)
6956 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6957 int max_literal_size
=
6958 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6960 tinsn
->literal_space
= max_literal_size
;
6962 tinsn
->subtype
= RELAX_IMMED
;
6963 extra_space
+= max_size
;
6967 /* A fix record will be added for this instruction prior
6968 to relaxation, so make it end the frag. */
6973 *pfinish_frag
= finish_frag
;
6979 bundle_tinsn (TInsn
*tinsn
, vliw_insn
*vinsn
)
6981 xtensa_isa isa
= xtensa_default_isa
;
6982 int slot
, chosen_slot
;
6984 vinsn
->format
= xg_get_single_format (tinsn
->opcode
);
6985 gas_assert (vinsn
->format
!= XTENSA_UNDEFINED
);
6986 vinsn
->num_slots
= xtensa_format_num_slots (isa
, vinsn
->format
);
6988 chosen_slot
= xg_get_single_slot (tinsn
->opcode
);
6989 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6991 if (slot
== chosen_slot
)
6992 vinsn
->slots
[slot
] = *tinsn
;
6995 vinsn
->slots
[slot
].opcode
=
6996 xtensa_format_slot_nop_opcode (isa
, vinsn
->format
, slot
);
6997 vinsn
->slots
[slot
].ntok
= 0;
6998 vinsn
->slots
[slot
].insn_type
= ITYPE_INSN
;
7005 emit_single_op (TInsn
*orig_insn
)
7008 IStack istack
; /* put instructions into here */
7009 symbolS
*lit_sym
= NULL
;
7010 symbolS
*label_sym
= NULL
;
7012 istack_init (&istack
);
7014 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
7015 Because the scheduling and bundling characteristics of movi and
7016 l32r or const16 are so different, we can do much better if we relax
7017 it prior to scheduling and bundling, rather than after. */
7018 if ((orig_insn
->opcode
== xtensa_movi_opcode
7019 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
7020 && !cur_vinsn
.inside_bundle
7021 && (orig_insn
->tok
[1].X_op
== O_symbol
7022 || orig_insn
->tok
[1].X_op
== O_pltrel
7023 || orig_insn
->tok
[1].X_op
== O_tlsfunc
7024 || orig_insn
->tok
[1].X_op
== O_tlsarg
7025 || orig_insn
->tok
[1].X_op
== O_tpoff
7026 || orig_insn
->tok
[1].X_op
== O_dtpoff
)
7027 && !orig_insn
->is_specific_opcode
&& use_transform ())
7028 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
7030 if (xg_expand_assembly_insn (&istack
, orig_insn
))
7033 for (i
= 0; i
< istack
.ninsn
; i
++)
7035 TInsn
*insn
= &istack
.insn
[i
];
7036 switch (insn
->insn_type
)
7039 gas_assert (lit_sym
== NULL
);
7040 lit_sym
= xg_assemble_literal (insn
);
7044 static int relaxed_sym_idx
= 0;
7045 char *label
= XNEWVEC (char, strlen (FAKE_LABEL_NAME
) + 12);
7046 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
7048 gas_assert (label_sym
== NULL
);
7049 label_sym
= symbol_find_or_make (label
);
7050 gas_assert (label_sym
);
7058 xg_resolve_literals (insn
, lit_sym
);
7060 xg_resolve_labels (insn
, label_sym
);
7062 bundle_tinsn (insn
, &v
);
7077 total_frag_text_expansion (fragS
*fragP
)
7080 int total_expansion
= 0;
7082 for (slot
= 0; slot
< config_max_slots
; slot
++)
7083 total_expansion
+= fragP
->tc_frag_data
.text_expansion
[slot
];
7085 return total_expansion
;
7089 /* Emit a vliw instruction to the current fragment. */
7092 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
7094 bfd_boolean finish_frag
;
7095 bfd_boolean is_jump
= FALSE
;
7096 bfd_boolean is_branch
= FALSE
;
7097 xtensa_isa isa
= xtensa_default_isa
;
7102 struct dwarf2_line_info debug_line
;
7103 bfd_boolean loc_directive_seen
= FALSE
;
7106 memset (&debug_line
, 0, sizeof (struct dwarf2_line_info
));
7108 if (generating_literals
)
7110 static int reported
= 0;
7112 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
7113 _("cannot assemble into a literal fragment"));
7120 if (frag_now_fix () != 0
7121 && (! frag_now
->tc_frag_data
.is_insn
7122 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7123 || (!use_transform ()) != frag_now
->tc_frag_data
.is_no_transform
7124 || (directive_state
[directive_longcalls
]
7125 != frag_now
->tc_frag_data
.use_longcalls
)
7126 || (directive_state
[directive_absolute_literals
]
7127 != frag_now
->tc_frag_data
.use_absolute_literals
)))
7129 frag_wane (frag_now
);
7131 xtensa_set_frag_assembly_state (frag_now
);
7134 if (workaround_a0_b_retw
7135 && vinsn
->num_slots
== 1
7136 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
7137 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
7138 && use_transform ())
7140 has_a0_b_retw
= TRUE
;
7142 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
7143 After the first assembly pass we will check all of them and
7144 add a nop if needed. */
7145 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7146 frag_var (rs_machine_dependent
, 4, 4,
7147 RELAX_ADD_NOP_IF_A0_B_RETW
,
7148 frag_now
->fr_symbol
,
7149 frag_now
->fr_offset
,
7151 xtensa_set_frag_assembly_state (frag_now
);
7152 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7153 frag_var (rs_machine_dependent
, 4, 4,
7154 RELAX_ADD_NOP_IF_A0_B_RETW
,
7155 frag_now
->fr_symbol
,
7156 frag_now
->fr_offset
,
7158 xtensa_set_frag_assembly_state (frag_now
);
7161 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
7163 tinsn
= &vinsn
->slots
[slot
];
7165 /* See if the instruction implies an aligned section. */
7166 if (xtensa_opcode_is_loop (isa
, tinsn
->opcode
) == 1)
7167 record_alignment (now_seg
, 2);
7169 /* Determine the best line number for debug info. */
7170 if ((tinsn
->loc_directive_seen
|| !loc_directive_seen
)
7171 && (tinsn
->debug_line
.filenum
!= debug_line
.filenum
7172 || tinsn
->debug_line
.line
< debug_line
.line
7173 || tinsn
->debug_line
.column
< debug_line
.column
))
7174 debug_line
= tinsn
->debug_line
;
7175 if (tinsn
->loc_directive_seen
)
7176 loc_directive_seen
= TRUE
;
7179 /* Special cases for instructions that force an alignment... */
7180 /* None of these opcodes are bundle-able. */
7181 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
7185 /* Remember the symbol that marks the end of the loop in the frag
7186 that marks the start of the loop. This way we can easily find
7187 the end of the loop at the beginning, without adding special code
7188 to mark the loop instructions themselves. */
7189 symbolS
*target_sym
= NULL
;
7190 if (vinsn
->slots
[0].tok
[1].X_op
== O_symbol
)
7191 target_sym
= vinsn
->slots
[0].tok
[1].X_add_symbol
;
7193 xtensa_set_frag_assembly_state (frag_now
);
7194 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7196 max_fill
= get_text_align_max_fill_size
7197 (get_text_align_power (xtensa_fetch_width
),
7198 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
7200 if (use_transform ())
7201 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
7202 RELAX_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
7204 frag_var (rs_machine_dependent
, 0, 0,
7205 RELAX_CHECK_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
7206 xtensa_set_frag_assembly_state (frag_now
);
7209 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
7210 && !vinsn
->slots
[0].is_specific_opcode
)
7212 xtensa_mark_literal_pool_location ();
7213 xtensa_move_labels (frag_now
, 0);
7214 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
7217 if (vinsn
->num_slots
== 1)
7219 if (workaround_a0_b_retw
&& use_transform ())
7220 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
7221 is_register_writer (&vinsn
->slots
[0], "a", 0));
7223 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
7224 is_bad_loopend_opcode (&vinsn
->slots
[0]));
7227 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
7229 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
7231 extra_space
= relaxation_requirements (vinsn
, &finish_frag
);
7233 /* vinsn_to_insnbuf will produce the error. */
7234 if (vinsn
->format
!= XTENSA_UNDEFINED
)
7236 f
= frag_more (insn_size
+ extra_space
);
7237 xtensa_set_frag_assembly_state (frag_now
);
7238 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7241 vinsn_to_insnbuf (vinsn
, f
, frag_now
, FALSE
);
7242 if (vinsn
->format
== XTENSA_UNDEFINED
)
7245 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, (unsigned char *) f
, 0);
7247 if (debug_type
== DEBUG_DWARF2
|| loc_directive_seen
)
7248 dwarf2_gen_line_info (frag_now_fix () - (insn_size
+ extra_space
),
7251 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
7253 tinsn
= &vinsn
->slots
[slot
];
7254 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
7255 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
7256 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
7257 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
7258 if (tinsn
->opcode
== xtensa_l32r_opcode
)
7259 frag_now
->tc_frag_data
.literal_frags
[slot
]
7260 = symbol_get_frag (tinsn
->tok
[1].X_add_symbol
);
7261 if (tinsn
->literal_space
!= 0)
7262 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
7263 frag_now
->tc_frag_data
.free_reg
[slot
] = tinsn
->extra_arg
;
7265 if (tinsn
->subtype
== RELAX_NARROW
)
7266 gas_assert (vinsn
->num_slots
== 1);
7267 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
7269 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
7272 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->offset
7273 || tinsn
->literal_frag
|| is_jump
|| is_branch
)
7277 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7278 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
7282 frag_variant (rs_machine_dependent
,
7283 extra_space
, extra_space
, RELAX_SLOTS
,
7284 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
7285 xtensa_set_frag_assembly_state (frag_now
);
7288 /* Special cases for loops:
7289 close_loop_end should be inserted AFTER short_loop.
7290 Make sure that CLOSE loops are processed BEFORE short_loops
7291 when converting them. */
7293 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
7294 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1
7295 && !vinsn
->slots
[0].is_specific_opcode
)
7297 if (workaround_short_loop
&& use_transform ())
7299 maybe_has_short_loop
= TRUE
;
7300 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7301 frag_var (rs_machine_dependent
, 4, 4,
7302 RELAX_ADD_NOP_IF_SHORT_LOOP
,
7303 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7304 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7305 frag_var (rs_machine_dependent
, 4, 4,
7306 RELAX_ADD_NOP_IF_SHORT_LOOP
,
7307 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7310 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
7311 loop at least 12 bytes away from another loop's end. */
7312 if (workaround_close_loop_end
&& use_transform ())
7314 maybe_has_close_loop_end
= TRUE
;
7315 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7316 frag_var (rs_machine_dependent
, 12, 12,
7317 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
7318 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7322 if (use_transform ())
7326 gas_assert (finish_frag
);
7327 frag_var (rs_machine_dependent
,
7328 xtensa_fetch_width
, xtensa_fetch_width
,
7330 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7331 xtensa_set_frag_assembly_state (frag_now
);
7332 xtensa_maybe_create_trampoline_frag ();
7333 /* Always create one here. */
7334 xtensa_maybe_create_literal_pool_frag (TRUE
, FALSE
);
7336 else if (is_branch
&& do_align_targets ())
7338 gas_assert (finish_frag
);
7339 frag_var (rs_machine_dependent
,
7340 xtensa_fetch_width
, xtensa_fetch_width
,
7341 RELAX_MAYBE_UNREACHABLE
,
7342 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7343 xtensa_set_frag_assembly_state (frag_now
);
7344 frag_var (rs_machine_dependent
,
7346 RELAX_MAYBE_DESIRE_ALIGN
,
7347 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7348 xtensa_set_frag_assembly_state (frag_now
);
7352 /* Now, if the original opcode was a call... */
7353 if (do_align_targets ()
7354 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
7356 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
7357 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7358 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
7359 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7360 xtensa_set_frag_assembly_state (frag_now
);
7363 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7365 frag_wane (frag_now
);
7367 xtensa_set_frag_assembly_state (frag_now
);
7372 /* xtensa_end and helper functions. */
7374 static void xtensa_cleanup_align_frags (void);
7375 static void xtensa_fix_target_frags (void);
7376 static void xtensa_mark_narrow_branches (void);
7377 static void xtensa_mark_zcl_first_insns (void);
7378 static void xtensa_mark_difference_of_two_symbols (void);
7379 static void xtensa_fix_a0_b_retw_frags (void);
7380 static void xtensa_fix_b_j_loop_end_frags (void);
7381 static void xtensa_fix_close_loop_end_frags (void);
7382 static void xtensa_fix_short_loop_frags (void);
7383 static void xtensa_sanity_check (void);
7384 static void xtensa_add_config_info (void);
7389 directive_balance ();
7390 xtensa_flush_pending_output ();
7392 past_xtensa_end
= TRUE
;
7394 xtensa_move_literals ();
7396 xtensa_reorder_segments ();
7397 xtensa_cleanup_align_frags ();
7398 xtensa_fix_target_frags ();
7399 if (workaround_a0_b_retw
&& has_a0_b_retw
)
7400 xtensa_fix_a0_b_retw_frags ();
7401 if (workaround_b_j_loop_end
)
7402 xtensa_fix_b_j_loop_end_frags ();
7404 /* "close_loop_end" should be processed BEFORE "short_loop". */
7405 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
7406 xtensa_fix_close_loop_end_frags ();
7408 if (workaround_short_loop
&& maybe_has_short_loop
)
7409 xtensa_fix_short_loop_frags ();
7411 xtensa_mark_narrow_branches ();
7412 xtensa_mark_zcl_first_insns ();
7414 xtensa_sanity_check ();
7416 xtensa_add_config_info ();
7418 xtensa_check_frag_count ();
7421 struct trampoline_chain_entry
7427 /* Trampoline chain for a given (sym, offset) pair is a sorted array
7428 of locations of trampoline jumps leading there. Jumps are represented
7429 as pairs (sym, offset): trampoline frag symbol and offset of the jump
7431 struct trampoline_chain
7433 struct trampoline_chain_entry target
;
7434 struct trampoline_chain_entry
*entry
;
7437 bfd_boolean needs_sorting
;
7440 struct trampoline_chain_index
7442 struct trampoline_chain
*entry
;
7445 bfd_boolean needs_sorting
;
7448 struct trampoline_index
7455 struct trampoline_seg
7457 struct trampoline_seg
*next
;
7459 /* Trampolines ordered by their frag fr_address */
7460 struct trampoline_index index
;
7461 /* Known trampoline chains ordered by (sym, offset) pair */
7462 struct trampoline_chain_index chain_index
;
7465 static struct trampoline_seg trampoline_seg_list
;
7466 #define J_RANGE (128 * 1024)
7467 #define J_MARGIN 4096
7469 static int unreachable_count
= 0;
7473 xtensa_maybe_create_trampoline_frag (void)
7475 if (!use_trampolines
)
7478 /* We create an area for possible trampolines every 10 unreachable frags.
7479 These are preferred over the ones not preceded by an unreachable frag,
7480 because we don't have to jump around them. This function is called after
7481 each RELAX_UNREACHABLE frag is created. */
7483 if (++unreachable_count
> 10)
7485 xtensa_create_trampoline_frag (FALSE
);
7486 clear_frag_count ();
7487 unreachable_count
= 0;
7492 xtensa_check_frag_count (void)
7494 if (!use_trampolines
|| frag_now
->tc_frag_data
.is_no_transform
)
7497 /* We create an area for possible trampolines every 8000 frags or so. This
7498 is an estimate based on the max range of a "j" insn (+/-128K) divided
7499 by a typical frag byte count (16), minus a few for safety. This function
7500 is called after each source line is processed. */
7502 if (get_frag_count () > 8000)
7504 xtensa_create_trampoline_frag (TRUE
);
7505 clear_frag_count ();
7506 unreachable_count
= 0;
7509 /* We create an area for a possible literal pool every N (default 5000)
7511 xtensa_maybe_create_literal_pool_frag (TRUE
, TRUE
);
7514 static xtensa_insnbuf trampoline_buf
= NULL
;
7515 static xtensa_insnbuf trampoline_slotbuf
= NULL
;
7517 static xtensa_insnbuf litpool_buf
= NULL
;
7518 static xtensa_insnbuf litpool_slotbuf
= NULL
;
7520 #define TRAMPOLINE_FRAG_SIZE 3000
7522 static struct trampoline_seg
*
7523 find_trampoline_seg (asection
*seg
)
7525 struct trampoline_seg
*ts
= trampoline_seg_list
.next
;
7526 static struct trampoline_seg
*mr
;
7528 if (mr
&& mr
->seg
== seg
)
7531 for ( ; ts
; ts
= ts
->next
)
7543 static size_t xg_find_trampoline (const struct trampoline_index
*idx
,
7547 size_t b
= idx
->n_entries
;
7551 size_t c
= (a
+ b
) / 2;
7553 if (idx
->entry
[c
]->fr_address
<= addr
)
7561 static void xg_add_trampoline_to_index (struct trampoline_index
*idx
,
7564 if (idx
->n_entries
== idx
->n_max
)
7566 idx
->n_max
= (idx
->n_entries
+ 1) * 2;
7567 idx
->entry
= xrealloc (idx
->entry
,
7568 sizeof (*idx
->entry
) * idx
->n_max
);
7570 idx
->entry
[idx
->n_entries
] = fragP
;
7574 static void xg_remove_trampoline_from_index (struct trampoline_index
*idx
,
7577 gas_assert (i
< idx
->n_entries
);
7578 memmove (idx
->entry
+ i
, idx
->entry
+ i
+ 1,
7579 (idx
->n_entries
- i
- 1) * sizeof (*idx
->entry
));
7583 static void xg_add_trampoline_to_seg (struct trampoline_seg
*ts
,
7586 xg_add_trampoline_to_index (&ts
->index
, fragP
);
7590 xtensa_create_trampoline_frag (bfd_boolean needs_jump_around
)
7592 /* Emit a frag where we can place intermediate jump instructions,
7593 in case we need to jump farther than 128K bytes.
7594 Each jump instruction takes three bytes.
7595 We allocate enough for 1000 trampolines in each frag.
7596 If that's not enough, oh well. */
7598 struct trampoline_seg
*ts
= find_trampoline_seg (now_seg
);
7601 int size
= TRAMPOLINE_FRAG_SIZE
;
7605 ts
= XCNEW(struct trampoline_seg
);
7606 ts
->next
= trampoline_seg_list
.next
;
7607 trampoline_seg_list
.next
= ts
;
7611 frag_wane (frag_now
);
7613 xtensa_set_frag_assembly_state (frag_now
);
7614 varP
= frag_var (rs_machine_dependent
, size
, size
, RELAX_TRAMPOLINE
, NULL
, 0, NULL
);
7615 fragP
= (fragS
*)(varP
- SIZEOF_STRUCT_FRAG
);
7616 if (trampoline_buf
== NULL
)
7618 trampoline_buf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7619 trampoline_slotbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7621 fragP
->tc_frag_data
.needs_jump_around
= needs_jump_around
;
7622 xg_add_trampoline_to_seg (ts
, fragP
);
7625 static bfd_boolean
xg_is_trampoline_frag_full (const fragS
*fragP
)
7627 return fragP
->fr_var
< 3;
7630 static int xg_order_trampoline_chain_entry (const void *a
, const void *b
)
7632 const struct trampoline_chain_entry
*pa
= a
;
7633 const struct trampoline_chain_entry
*pb
= b
;
7635 if (pa
->sym
!= pb
->sym
)
7637 valueT aval
= S_GET_VALUE (pa
->sym
);
7638 valueT bval
= S_GET_VALUE (pb
->sym
);
7641 return aval
< bval
? -1 : 1;
7643 if (pa
->offset
!= pb
->offset
)
7644 return pa
->offset
< pb
->offset
? -1 : 1;
7648 static void xg_sort_trampoline_chain (struct trampoline_chain
*tc
)
7650 qsort (tc
->entry
, tc
->n_entries
, sizeof (*tc
->entry
),
7651 xg_order_trampoline_chain_entry
);
7652 tc
->needs_sorting
= FALSE
;
7655 /* Find entry index in the given chain with maximal address <= source. */
7656 static size_t xg_find_chain_entry (struct trampoline_chain
*tc
,
7660 size_t b
= tc
->n_entries
;
7662 if (tc
->needs_sorting
)
7663 xg_sort_trampoline_chain (tc
);
7667 size_t c
= (a
+ b
) / 2;
7668 struct trampoline_chain_entry
*e
= tc
->entry
+ c
;
7670 if (S_GET_VALUE(e
->sym
) + e
->offset
<= source
)
7678 /* Find the best jump target for the source in the given trampoline chain.
7679 The best jump target is the one that results in the shortest path to the
7680 final target, it's the location of the jump closest to the final target,
7681 but within the J_RANGE - J_MARGIN from the source. */
7682 static struct trampoline_chain_entry
*
7683 xg_get_best_chain_entry (struct trampoline_chain
*tc
, addressT source
)
7685 addressT target
= S_GET_VALUE(tc
->target
.sym
) + tc
->target
.offset
;
7686 size_t i
= xg_find_chain_entry (tc
, source
);
7687 struct trampoline_chain_entry
*e
= tc
->entry
+ i
;
7688 int step
= target
< source
? -1 : 1;
7689 addressT chained_target
;
7692 if (target
> source
&&
7693 S_GET_VALUE(e
->sym
) + e
->offset
<= source
&&
7694 i
+ 1 < tc
->n_entries
)
7697 while (i
+ step
< tc
->n_entries
)
7699 struct trampoline_chain_entry
*next
= tc
->entry
+ i
+ step
;
7701 chained_target
= S_GET_VALUE(next
->sym
) + next
->offset
;
7702 off
= source
- chained_target
;
7704 if (labs (off
) >= J_RANGE
- J_MARGIN
)
7711 chained_target
= S_GET_VALUE(e
->sym
) + e
->offset
;
7712 off
= source
- chained_target
;
7714 if (labs (off
) < J_MARGIN
||
7715 labs (off
) >= J_RANGE
- J_MARGIN
)
7717 return tc
->entry
+ i
;
7720 static int xg_order_trampoline_chain (const void *a
, const void *b
)
7722 const struct trampoline_chain
*_pa
= a
;
7723 const struct trampoline_chain
*_pb
= b
;
7724 const struct trampoline_chain_entry
*pa
= &_pa
->target
;
7725 const struct trampoline_chain_entry
*pb
= &_pb
->target
;
7726 symbolS
*s1
= pa
->sym
;
7727 symbolS
*s2
= pb
->sym
;
7731 symbolS
*tmp
= symbol_symbolS (s1
);
7735 tmp
= symbol_symbolS (s2
);
7740 return s1
< s2
? -1 : 1;
7743 if (pa
->offset
!= pb
->offset
)
7744 return pa
->offset
< pb
->offset
? -1 : 1;
7748 static struct trampoline_chain
*
7749 xg_get_trampoline_chain (struct trampoline_seg
*ts
,
7753 struct trampoline_chain_index
*idx
= &ts
->chain_index
;
7754 struct trampoline_chain c
;
7756 if (idx
->n_entries
== 0)
7759 if (idx
->needs_sorting
)
7761 qsort (idx
->entry
, idx
->n_entries
, sizeof (*idx
->entry
),
7762 xg_order_trampoline_chain
);
7763 idx
->needs_sorting
= FALSE
;
7766 c
.target
.offset
= offset
;
7767 return bsearch (&c
, idx
->entry
, idx
->n_entries
,
7768 sizeof (struct trampoline_chain
),
7769 xg_order_trampoline_chain
);
7772 /* Find trampoline chain in the given trampoline segment that is going
7773 to the *sym + *offset. If found, replace *sym and *offset with the
7774 best jump target in that chain. */
7775 static struct trampoline_chain
*
7776 xg_find_best_eq_target (struct trampoline_seg
*ts
,
7777 addressT source
, symbolS
**sym
,
7780 struct trampoline_chain
*tc
= xg_get_trampoline_chain (ts
, *sym
, *offset
);
7784 struct trampoline_chain_entry
*e
= xg_get_best_chain_entry (tc
, source
);
7787 *offset
= e
->offset
;
7792 static void xg_add_location_to_chain (struct trampoline_chain
*tc
,
7793 symbolS
*sym
, addressT offset
)
7795 struct trampoline_chain_entry
*e
;
7797 if (tc
->n_entries
== tc
->n_max
)
7799 tc
->n_max
= (tc
->n_max
+ 1) * 2;
7800 tc
->entry
= xrealloc (tc
->entry
, sizeof (*tc
->entry
) * tc
->n_max
);
7802 e
= tc
->entry
+ tc
->n_entries
;
7806 tc
->needs_sorting
= TRUE
;
7809 static struct trampoline_chain
*
7810 xg_create_trampoline_chain (struct trampoline_seg
*ts
,
7811 symbolS
*sym
, addressT offset
)
7813 struct trampoline_chain_index
*idx
= &ts
->chain_index
;
7814 struct trampoline_chain
*tc
;
7816 if (idx
->n_entries
== idx
->n_max
)
7818 idx
->n_max
= (idx
->n_max
+ 1) * 2;
7819 idx
->entry
= xrealloc (idx
->entry
,
7820 sizeof (*idx
->entry
) * idx
->n_max
);
7823 tc
= idx
->entry
+ idx
->n_entries
;
7824 tc
->target
.sym
= sym
;
7825 tc
->target
.offset
= offset
;
7829 xg_add_location_to_chain (tc
, sym
, offset
);
7832 idx
->needs_sorting
= TRUE
;
7837 void dump_trampolines (void);
7840 dump_trampolines (void)
7842 struct trampoline_seg
*ts
= trampoline_seg_list
.next
;
7844 for ( ; ts
; ts
= ts
->next
)
7847 asection
*seg
= ts
->seg
;
7851 fprintf(stderr
, "SECTION %s\n", seg
->name
);
7853 for (i
= 0; i
< ts
->index
.n_entries
; ++i
)
7855 fragS
*tf
= ts
->index
.entry
[i
];
7857 fprintf(stderr
, " 0x%08x: fix=%d, jump_around=%s\n",
7858 (int)tf
->fr_address
, (int)tf
->fr_fix
,
7859 tf
->tc_frag_data
.needs_jump_around
? "T" : "F");
7864 static void dump_litpools (void) __attribute__ ((unused
));
7867 dump_litpools (void)
7869 struct litpool_seg
*lps
= litpool_seg_list
.next
;
7870 struct litpool_frag
*lpf
;
7872 for ( ; lps
; lps
= lps
->next
)
7874 printf("litpool seg %s\n", lps
->seg
->name
);
7875 for ( lpf
= lps
->frag_list
.next
; lpf
->fragP
; lpf
= lpf
->next
)
7877 fragS
*litfrag
= lpf
->fragP
->fr_next
;
7879 while (litfrag
&& litfrag
->fr_subtype
!= RELAX_LITERAL_POOL_END
)
7881 if (litfrag
->fr_fix
== 4)
7883 litfrag
= litfrag
->fr_next
;
7885 printf(" %ld <%d:%d> (%d) [%d]: ",
7886 lpf
->addr
, lpf
->priority
, lpf
->original_priority
,
7887 lpf
->fragP
->fr_line
, count
);
7888 /* dump_frag(lpf->fragP); */
7894 xtensa_maybe_create_literal_pool_frag (bfd_boolean create
,
7895 bfd_boolean only_if_needed
)
7897 struct litpool_seg
*lps
= litpool_seg_list
.next
;
7899 struct litpool_frag
*lpf
;
7900 bfd_boolean needed
= FALSE
;
7902 if (use_literal_section
|| !auto_litpools
)
7905 for ( ; lps
; lps
= lps
->next
)
7907 if (lps
->seg
== now_seg
)
7913 lps
= XCNEW (struct litpool_seg
);
7914 lps
->next
= litpool_seg_list
.next
;
7915 litpool_seg_list
.next
= lps
;
7917 lps
->frag_list
.next
= &lps
->frag_list
;
7918 lps
->frag_list
.prev
= &lps
->frag_list
;
7919 /* Put candidate literal pool at the beginning of every section,
7920 so that even when section starts with literal load there's a
7921 literal pool available. */
7922 lps
->frag_count
= auto_litpool_limit
;
7931 if (past_xtensa_end
|| !use_transform() ||
7932 frag_now
->tc_frag_data
.is_no_transform
)
7936 if (auto_litpool_limit
<= 0)
7938 /* Don't create a litpool based only on frag count. */
7941 else if (lps
->frag_count
> auto_litpool_limit
)
7958 int size
= (only_if_needed
) ? 3 : 0; /* Space for a "j" insn. */
7959 /* Create a potential site for a literal pool. */
7960 frag_wane (frag_now
);
7962 xtensa_set_frag_assembly_state (frag_now
);
7964 fragP
->tc_frag_data
.lit_frchain
= frchain_now
;
7965 fragP
->tc_frag_data
.literal_frag
= fragP
;
7966 frag_var (rs_machine_dependent
, size
, size
,
7968 RELAX_LITERAL_POOL_CANDIDATE_BEGIN
:
7969 RELAX_LITERAL_POOL_BEGIN
,
7971 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
7972 frag_variant (rs_machine_dependent
, 0, 0,
7973 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
7974 xtensa_set_frag_assembly_state (frag_now
);
7978 /* RELAX_LITERAL_POOL_BEGIN frag is being created;
7979 just record it here. */
7983 lpf
= XNEW (struct litpool_frag
);
7984 /* Insert at tail of circular list. */
7986 lps
->frag_list
.prev
->next
= lpf
;
7987 lpf
->next
= &lps
->frag_list
;
7988 lpf
->prev
= lps
->frag_list
.prev
;
7989 lps
->frag_list
.prev
= lpf
;
7991 lpf
->priority
= (needed
) ? (only_if_needed
) ? 3 : 2 : 1;
7992 lpf
->original_priority
= lpf
->priority
;
7993 lpf
->literal_count
= 0;
7995 lps
->frag_count
= 0;
7999 xtensa_cleanup_align_frags (void)
8004 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8005 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8008 /* Walk over all of the fragments in a subsection. */
8009 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8011 if ((fragP
->fr_type
== rs_align
8012 || fragP
->fr_type
== rs_align_code
8013 || (fragP
->fr_type
== rs_machine_dependent
8014 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
8015 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
8016 && fragP
->fr_fix
== 0)
8018 fragS
*next
= fragP
->fr_next
;
8021 && next
->fr_fix
== 0
8022 && next
->fr_type
== rs_machine_dependent
8023 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
8026 next
= next
->fr_next
;
8029 /* If we don't widen branch targets, then they
8030 will be easier to align. */
8031 if (fragP
->tc_frag_data
.is_branch_target
8032 && fragP
->fr_opcode
== fragP
->fr_literal
8033 && fragP
->fr_type
== rs_machine_dependent
8034 && fragP
->fr_subtype
== RELAX_SLOTS
8035 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8037 if (fragP
->fr_type
== rs_machine_dependent
8038 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
8039 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
8045 /* Re-process all of the fragments looking to convert all of the
8046 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
8047 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
8048 Otherwise, convert to a .fill 0. */
8051 xtensa_fix_target_frags (void)
8056 /* When this routine is called, all of the subsections are still intact
8057 so we walk over subsections instead of sections. */
8058 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8059 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8063 /* Walk over all of the fragments in a subsection. */
8064 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8066 if (fragP
->fr_type
== rs_machine_dependent
8067 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
8069 if (next_frag_is_branch_target (fragP
))
8070 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
8079 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
8082 xtensa_mark_narrow_branches (void)
8087 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8088 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8091 /* Walk over all of the fragments in a subsection. */
8092 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8094 if (fragP
->fr_type
== rs_machine_dependent
8095 && fragP
->fr_subtype
== RELAX_SLOTS
8096 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
8100 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
8101 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
8103 if (vinsn
.num_slots
== 1
8104 && xtensa_opcode_is_branch (xtensa_default_isa
,
8105 vinsn
.slots
[0].opcode
) == 1
8106 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
8107 && is_narrow_branch_guaranteed_in_range (fragP
,
8110 fragP
->fr_subtype
= RELAX_SLOTS
;
8111 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
8112 fragP
->tc_frag_data
.is_aligning_branch
= 1;
8120 /* A branch is typically widened only when its target is out of
8121 range. However, we would like to widen them to align a subsequent
8122 branch target when possible.
8124 Because the branch relaxation code is so convoluted, the optimal solution
8125 (combining the two cases) is difficult to get right in all circumstances.
8126 We therefore go with an "almost as good" solution, where we only
8127 use for alignment narrow branches that definitely will not expand to a
8128 jump and a branch. These functions find and mark these cases. */
8130 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
8131 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
8132 We start counting beginning with the frag after the 2-byte branch, so the
8133 maximum offset is (4 - 2) + 63 = 65. */
8134 #define MAX_IMMED6 65
8136 static offsetT
unrelaxed_frag_max_size (fragS
*);
8139 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
8141 const expressionS
*exp
= &tinsn
->tok
[1];
8142 symbolS
*symbolP
= exp
->X_add_symbol
;
8143 offsetT max_distance
= exp
->X_add_number
;
8146 if (exp
->X_op
!= O_symbol
)
8149 target_frag
= symbol_get_frag (symbolP
);
8151 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
8152 if (is_branch_jmp_to_next (tinsn
, fragP
))
8155 /* The branch doesn't branch over it's own frag,
8156 but over the subsequent ones. */
8157 fragP
= fragP
->fr_next
;
8158 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
8160 max_distance
+= unrelaxed_frag_max_size (fragP
);
8161 fragP
= fragP
->fr_next
;
8163 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
8170 xtensa_mark_zcl_first_insns (void)
8175 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8176 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8179 /* Walk over all of the fragments in a subsection. */
8180 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8182 if (fragP
->fr_type
== rs_machine_dependent
8183 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
8184 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
8186 /* Find the loop frag. */
8187 fragS
*loop_frag
= next_non_empty_frag (fragP
);
8188 /* Find the first insn frag. */
8189 fragS
*targ_frag
= next_non_empty_frag (loop_frag
);
8191 /* Handle a corner case that comes up in hardware
8192 diagnostics. The original assembly looks like this:
8195 <empty_frag>--not found by next_non_empty_frag
8198 Depending on the start address, the assembler may or
8199 may not change it to look something like this:
8202 nop--frag isn't empty anymore
8205 So set up to check the alignment of the nop if it
8207 while (loop_frag
!= targ_frag
)
8209 if (loop_frag
->fr_type
== rs_machine_dependent
8210 && (loop_frag
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
8211 || loop_frag
->fr_subtype
8212 == RELAX_CHECK_ALIGN_NEXT_OPCODE
))
8213 targ_frag
= loop_frag
;
8215 loop_frag
= loop_frag
->fr_next
;
8218 /* Of course, sometimes (mostly for toy test cases) a
8219 zero-cost loop instruction is the last in a section. */
8222 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
8223 /* Do not widen a frag that is the first instruction of a
8224 zero-cost loop. It makes that loop harder to align. */
8225 if (targ_frag
->fr_type
== rs_machine_dependent
8226 && targ_frag
->fr_subtype
== RELAX_SLOTS
8227 && (targ_frag
->tc_frag_data
.slot_subtypes
[0]
8230 if (targ_frag
->tc_frag_data
.is_aligning_branch
)
8231 targ_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
8234 frag_wane (targ_frag
);
8235 targ_frag
->tc_frag_data
.slot_subtypes
[0] = 0;
8239 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
8247 /* When a difference-of-symbols expression is encoded as a uleb128 or
8248 sleb128 value, the linker is unable to adjust that value to account for
8249 link-time relaxation. Mark all the code between such symbols so that
8250 its size cannot be changed by linker relaxation. */
8253 xtensa_mark_difference_of_two_symbols (void)
8257 for (expr_sym
= expr_symbols
; expr_sym
;
8258 expr_sym
= symbol_get_tc (expr_sym
)->next_expr_symbol
)
8260 expressionS
*exp
= symbol_get_value_expression (expr_sym
);
8262 if (exp
->X_op
== O_subtract
)
8264 symbolS
*left
= exp
->X_add_symbol
;
8265 symbolS
*right
= exp
->X_op_symbol
;
8267 /* Difference of two symbols not in the same section
8268 are handled with relocations in the linker. */
8269 if (S_GET_SEGMENT (left
) == S_GET_SEGMENT (right
))
8275 if (symbol_get_frag (left
)->fr_address
8276 <= symbol_get_frag (right
)->fr_address
)
8278 start
= symbol_get_frag (left
);
8279 end
= symbol_get_frag (right
);
8283 start
= symbol_get_frag (right
);
8284 end
= symbol_get_frag (left
);
8287 if (start
->tc_frag_data
.no_transform_end
!= NULL
)
8288 walk
= start
->tc_frag_data
.no_transform_end
;
8293 walk
->tc_frag_data
.is_no_transform
= 1;
8294 walk
= walk
->fr_next
;
8296 while (walk
&& walk
->fr_address
< end
->fr_address
);
8298 start
->tc_frag_data
.no_transform_end
= walk
;
8305 /* Re-process all of the fragments looking to convert all of the
8306 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
8307 conditional branch or a retw/retw.n, convert this frag to one that
8308 will generate a NOP. In any case close it off with a .fill 0. */
8310 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
8313 xtensa_fix_a0_b_retw_frags (void)
8318 /* When this routine is called, all of the subsections are still intact
8319 so we walk over subsections instead of sections. */
8320 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8321 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8325 /* Walk over all of the fragments in a subsection. */
8326 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8328 if (fragP
->fr_type
== rs_machine_dependent
8329 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
8331 if (next_instrs_are_b_retw (fragP
))
8333 if (fragP
->tc_frag_data
.is_no_transform
)
8334 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
8336 relax_frag_add_nop (fragP
);
8346 next_instrs_are_b_retw (fragS
*fragP
)
8348 xtensa_opcode opcode
;
8350 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
8351 static xtensa_insnbuf insnbuf
= NULL
;
8352 static xtensa_insnbuf slotbuf
= NULL
;
8353 xtensa_isa isa
= xtensa_default_isa
;
8354 unsigned int offset
= 0;
8356 bfd_boolean branch_seen
= FALSE
;
8360 insnbuf
= xtensa_insnbuf_alloc (isa
);
8361 slotbuf
= xtensa_insnbuf_alloc (isa
);
8364 if (next_fragP
== NULL
)
8367 /* Check for the conditional branch. */
8368 xtensa_insnbuf_from_chars
8369 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
8370 fmt
= xtensa_format_decode (isa
, insnbuf
);
8371 if (fmt
== XTENSA_UNDEFINED
)
8374 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
8376 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
8377 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
8379 branch_seen
= (branch_seen
8380 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
8386 offset
+= xtensa_format_length (isa
, fmt
);
8387 if (offset
== next_fragP
->fr_fix
)
8389 next_fragP
= next_non_empty_frag (next_fragP
);
8393 if (next_fragP
== NULL
)
8396 /* Check for the retw/retw.n. */
8397 xtensa_insnbuf_from_chars
8398 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
8399 fmt
= xtensa_format_decode (isa
, insnbuf
);
8401 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
8402 have no problems. */
8403 if (fmt
== XTENSA_UNDEFINED
8404 || xtensa_format_num_slots (isa
, fmt
) != 1)
8407 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
8408 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
8410 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
8417 /* Re-process all of the fragments looking to convert all of the
8418 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
8419 loop end label, convert this frag to one that will generate a NOP.
8420 In any case close it off with a .fill 0. */
8422 static bfd_boolean
next_instr_is_loop_end (fragS
*);
8425 xtensa_fix_b_j_loop_end_frags (void)
8430 /* When this routine is called, all of the subsections are still intact
8431 so we walk over subsections instead of sections. */
8432 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8433 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8437 /* Walk over all of the fragments in a subsection. */
8438 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8440 if (fragP
->fr_type
== rs_machine_dependent
8441 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
8443 if (next_instr_is_loop_end (fragP
))
8445 if (fragP
->tc_frag_data
.is_no_transform
)
8446 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
8448 relax_frag_add_nop (fragP
);
8458 next_instr_is_loop_end (fragS
*fragP
)
8460 const fragS
*next_fragP
;
8462 if (next_frag_is_loop_target (fragP
))
8465 next_fragP
= next_non_empty_frag (fragP
);
8466 if (next_fragP
== NULL
)
8469 if (!next_frag_is_loop_target (next_fragP
))
8472 /* If the size is >= 3 then there is more than one instruction here.
8473 The hardware bug will not fire. */
8474 if (next_fragP
->fr_fix
> 3)
8481 /* Re-process all of the fragments looking to convert all of the
8482 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
8483 not MY loop's loop end within 12 bytes, add enough nops here to
8484 make it at least 12 bytes away. In any case close it off with a
8487 static offsetT min_bytes_to_other_loop_end
8488 (fragS
*, fragS
*, offsetT
);
8491 xtensa_fix_close_loop_end_frags (void)
8496 /* When this routine is called, all of the subsections are still intact
8497 so we walk over subsections instead of sections. */
8498 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8499 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8503 fragS
*current_target
= NULL
;
8505 /* Walk over all of the fragments in a subsection. */
8506 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8508 if (fragP
->fr_type
== rs_machine_dependent
8509 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
8510 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
8511 current_target
= symbol_get_frag (fragP
->fr_symbol
);
8514 && fragP
->fr_type
== rs_machine_dependent
8515 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
8518 int bytes_added
= 0;
8520 #define REQUIRED_LOOP_DIVIDING_BYTES 12
8521 /* Max out at 12. */
8522 min_bytes
= min_bytes_to_other_loop_end
8523 (fragP
->fr_next
, current_target
, REQUIRED_LOOP_DIVIDING_BYTES
);
8525 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
8527 if (fragP
->tc_frag_data
.is_no_transform
)
8528 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
8531 while (min_bytes
+ bytes_added
8532 < REQUIRED_LOOP_DIVIDING_BYTES
)
8536 if (fragP
->fr_var
< length
)
8537 as_fatal (_("fr_var %lu < length %d"),
8538 (long) fragP
->fr_var
, length
);
8541 assemble_nop (length
,
8542 fragP
->fr_literal
+ fragP
->fr_fix
);
8543 fragP
->fr_fix
+= length
;
8544 fragP
->fr_var
-= length
;
8546 bytes_added
+= length
;
8552 gas_assert (fragP
->fr_type
!= rs_machine_dependent
8553 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
8559 static offsetT
unrelaxed_frag_min_size (fragS
*);
8562 min_bytes_to_other_loop_end (fragS
*fragP
,
8563 fragS
*current_target
,
8567 fragS
*current_fragP
;
8569 for (current_fragP
= fragP
;
8571 current_fragP
= current_fragP
->fr_next
)
8573 if (current_fragP
->tc_frag_data
.is_loop_target
8574 && current_fragP
!= current_target
)
8577 offset
+= unrelaxed_frag_min_size (current_fragP
);
8579 if (offset
>= max_size
)
8587 unrelaxed_frag_min_size (fragS
*fragP
)
8589 offsetT size
= fragP
->fr_fix
;
8591 /* Add fill size. */
8592 if (fragP
->fr_type
== rs_fill
)
8593 size
+= fragP
->fr_offset
;
8600 unrelaxed_frag_max_size (fragS
*fragP
)
8602 offsetT size
= fragP
->fr_fix
;
8603 switch (fragP
->fr_type
)
8606 /* Empty frags created by the obstack allocation scheme
8607 end up with type 0. */
8612 size
+= fragP
->fr_offset
;
8620 /* No further adjustments needed. */
8622 case rs_machine_dependent
:
8623 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
8624 size
+= fragP
->fr_var
;
8627 /* We had darn well better know how big it is. */
8636 /* Re-process all of the fragments looking to convert all
8637 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
8640 1) the instruction size count to the loop end label
8641 is too short (<= 2 instructions),
8642 2) loop has a jump or branch in it
8645 1) workaround_all_short_loops is TRUE
8646 2) The generating loop was a 'loopgtz' or 'loopnez'
8647 3) the instruction size count to the loop end label is too short
8649 then convert this frag (and maybe the next one) to generate a NOP.
8650 In any case close it off with a .fill 0. */
8652 static int count_insns_to_loop_end (fragS
*, bfd_boolean
, int);
8653 static bfd_boolean
branch_before_loop_end (fragS
*);
8656 xtensa_fix_short_loop_frags (void)
8661 /* When this routine is called, all of the subsections are still intact
8662 so we walk over subsections instead of sections. */
8663 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8664 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8667 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
8669 /* Walk over all of the fragments in a subsection. */
8670 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8672 if (fragP
->fr_type
== rs_machine_dependent
8673 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
8674 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
8677 fragS
*loop_frag
= next_non_empty_frag (fragP
);
8678 tinsn_from_chars (&t_insn
, loop_frag
->fr_opcode
, 0);
8679 current_opcode
= t_insn
.opcode
;
8680 gas_assert (xtensa_opcode_is_loop (xtensa_default_isa
,
8681 current_opcode
) == 1);
8684 if (fragP
->fr_type
== rs_machine_dependent
8685 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
8687 if (count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3) < 3
8688 && (branch_before_loop_end (fragP
->fr_next
)
8689 || (workaround_all_short_loops
8690 && current_opcode
!= XTENSA_UNDEFINED
8691 && current_opcode
!= xtensa_loop_opcode
)))
8693 if (fragP
->tc_frag_data
.is_no_transform
)
8694 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
8696 relax_frag_add_nop (fragP
);
8705 static int unrelaxed_frag_min_insn_count (fragS
*);
8708 count_insns_to_loop_end (fragS
*base_fragP
,
8709 bfd_boolean count_relax_add
,
8712 fragS
*fragP
= NULL
;
8717 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
8719 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
8720 if (insn_count
>= max_count
)
8723 if (count_relax_add
)
8725 if (fragP
->fr_type
== rs_machine_dependent
8726 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
8728 /* In order to add the appropriate number of
8729 NOPs, we count an instruction for downstream
8732 if (insn_count
>= max_count
)
8742 unrelaxed_frag_min_insn_count (fragS
*fragP
)
8744 xtensa_isa isa
= xtensa_default_isa
;
8745 static xtensa_insnbuf insnbuf
= NULL
;
8747 unsigned int offset
= 0;
8749 if (!fragP
->tc_frag_data
.is_insn
)
8753 insnbuf
= xtensa_insnbuf_alloc (isa
);
8755 /* Decode the fixed instructions. */
8756 while (offset
< fragP
->fr_fix
)
8760 xtensa_insnbuf_from_chars
8761 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
8762 fmt
= xtensa_format_decode (isa
, insnbuf
);
8764 if (fmt
== XTENSA_UNDEFINED
)
8766 as_fatal (_("undecodable instruction in instruction frag"));
8769 offset
+= xtensa_format_length (isa
, fmt
);
8777 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
8780 branch_before_loop_end (fragS
*base_fragP
)
8784 for (fragP
= base_fragP
;
8785 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
8786 fragP
= fragP
->fr_next
)
8788 if (unrelaxed_frag_has_b_j (fragP
))
8796 unrelaxed_frag_has_b_j (fragS
*fragP
)
8798 static xtensa_insnbuf insnbuf
= NULL
;
8799 xtensa_isa isa
= xtensa_default_isa
;
8800 unsigned int offset
= 0;
8802 if (!fragP
->tc_frag_data
.is_insn
)
8806 insnbuf
= xtensa_insnbuf_alloc (isa
);
8808 /* Decode the fixed instructions. */
8809 while (offset
< fragP
->fr_fix
)
8814 xtensa_insnbuf_from_chars
8815 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
8816 fmt
= xtensa_format_decode (isa
, insnbuf
);
8817 if (fmt
== XTENSA_UNDEFINED
)
8820 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
8822 xtensa_opcode opcode
=
8823 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
8824 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
8825 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
8828 offset
+= xtensa_format_length (isa
, fmt
);
8834 /* Checks to be made after initial assembly but before relaxation. */
8836 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
8837 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
8840 xtensa_sanity_check (void)
8842 const char *file_name
;
8847 file_name
= as_where (&line
);
8848 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8849 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8853 /* Walk over all of the fragments in a subsection. */
8854 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8856 if (fragP
->fr_type
== rs_machine_dependent
8857 && fragP
->fr_subtype
== RELAX_SLOTS
8858 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
8860 static xtensa_insnbuf insnbuf
= NULL
;
8863 if (fragP
->fr_opcode
!= NULL
)
8866 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
8867 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
8868 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
8870 if (xtensa_opcode_is_loop (xtensa_default_isa
,
8871 t_insn
.opcode
) == 1)
8873 if (is_empty_loop (&t_insn
, fragP
))
8875 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8876 as_bad (_("invalid empty loop"));
8878 if (!is_local_forward_loop (&t_insn
, fragP
))
8880 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8881 as_bad (_("loop target does not follow "
8882 "loop instruction in section"));
8889 new_logical_line (file_name
, line
);
8893 #define LOOP_IMMED_OPN 1
8895 /* Return TRUE if the loop target is the next non-zero fragment. */
8898 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
8900 const expressionS
*exp
;
8904 if (insn
->insn_type
!= ITYPE_INSN
)
8907 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
8910 if (insn
->ntok
<= LOOP_IMMED_OPN
)
8913 exp
= &insn
->tok
[LOOP_IMMED_OPN
];
8915 if (exp
->X_op
!= O_symbol
)
8918 symbolP
= exp
->X_add_symbol
;
8922 if (symbol_get_frag (symbolP
) == NULL
)
8925 if (S_GET_VALUE (symbolP
) != 0)
8928 /* Walk through the zero-size fragments from this one. If we find
8929 the target fragment, then this is a zero-size loop. */
8931 for (next_fragP
= fragP
->fr_next
;
8933 next_fragP
= next_fragP
->fr_next
)
8935 if (next_fragP
== symbol_get_frag (symbolP
))
8937 if (next_fragP
->fr_fix
!= 0)
8945 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
8947 const expressionS
*exp
;
8951 if (insn
->insn_type
!= ITYPE_INSN
)
8954 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
8957 if (insn
->ntok
<= LOOP_IMMED_OPN
)
8960 exp
= &insn
->tok
[LOOP_IMMED_OPN
];
8962 if (exp
->X_op
!= O_symbol
)
8965 symbolP
= exp
->X_add_symbol
;
8969 if (symbol_get_frag (symbolP
) == NULL
)
8972 /* Walk through fragments until we find the target.
8973 If we do not find the target, then this is an invalid loop. */
8975 for (next_fragP
= fragP
->fr_next
;
8977 next_fragP
= next_fragP
->fr_next
)
8979 if (next_fragP
== symbol_get_frag (symbolP
))
8986 #define XTINFO_NAME "Xtensa_Info"
8987 #define XTINFO_NAMESZ 12
8988 #define XTINFO_TYPE 1
8991 xtensa_add_config_info (void)
8997 info_sec
= subseg_new (".xtensa.info", 0);
8998 bfd_set_section_flags (info_sec
, SEC_HAS_CONTENTS
| SEC_READONLY
);
9000 data
= XNEWVEC (char, 100);
9001 sprintf (data
, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n",
9002 XSHAL_USE_ABSOLUTE_LITERALS
, xtensa_abi_choice ());
9003 sz
= strlen (data
) + 1;
9005 /* Add enough null terminators to pad to a word boundary. */
9008 while ((sz
& 3) != 0);
9010 /* Follow the standard note section layout:
9011 First write the length of the name string. */
9013 md_number_to_chars (p
, (valueT
) XTINFO_NAMESZ
, 4);
9015 /* Next comes the length of the "descriptor", i.e., the actual data. */
9017 md_number_to_chars (p
, (valueT
) sz
, 4);
9019 /* Write the note type. */
9021 md_number_to_chars (p
, (valueT
) XTINFO_TYPE
, 4);
9023 /* Write the name field. */
9024 p
= frag_more (XTINFO_NAMESZ
);
9025 memcpy (p
, XTINFO_NAME
, XTINFO_NAMESZ
);
9027 /* Finally, write the descriptor. */
9029 memcpy (p
, data
, sz
);
9035 /* Alignment Functions. */
9038 get_text_align_power (unsigned target_size
)
9040 if (target_size
<= 4)
9043 if (target_size
<= 8)
9046 if (target_size
<= 16)
9049 if (target_size
<= 32)
9052 if (target_size
<= 64)
9055 if (target_size
<= 128)
9058 if (target_size
<= 256)
9061 if (target_size
<= 512)
9064 if (target_size
<= 1024)
9073 get_text_align_max_fill_size (int align_pow
,
9074 bfd_boolean use_nops
,
9075 bfd_boolean use_no_density
)
9078 return (1 << align_pow
);
9080 return 3 * (1 << align_pow
);
9082 return 1 + (1 << align_pow
);
9086 /* Calculate the minimum bytes of fill needed at "address" to align a
9087 target instruction of size "target_size" so that it does not cross a
9088 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE,
9089 the fill can be an arbitrary number of bytes. Otherwise, the space must
9090 be filled by NOP instructions. */
9093 get_text_align_fill_size (addressT address
,
9096 bfd_boolean use_nops
,
9097 bfd_boolean use_no_density
)
9099 addressT alignment
, fill
, fill_limit
, fill_step
;
9100 bfd_boolean skip_one
= FALSE
;
9102 alignment
= (1 << align_pow
);
9103 gas_assert (target_size
> 0 && alignment
>= (addressT
) target_size
);
9107 fill_limit
= alignment
;
9110 else if (!use_no_density
)
9112 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */
9113 fill_limit
= alignment
* 2;
9119 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */
9120 fill_limit
= alignment
* 3;
9124 /* Try all fill sizes until finding one that works. */
9125 for (fill
= 0; fill
< fill_limit
; fill
+= fill_step
)
9127 if (skip_one
&& fill
== 1)
9129 if ((address
+ fill
) >> align_pow
9130 == (address
+ fill
+ target_size
- 1) >> align_pow
)
9139 branch_align_power (segT sec
)
9141 /* If the Xtensa processor has a fetch width of X, and
9142 the section is aligned to at least that boundary, then a branch
9143 target need only fit within that aligned block of memory to avoid
9144 a stall. Otherwise, try to fit branch targets within 4-byte
9145 aligned blocks (which may be insufficient, e.g., if the section
9146 has no alignment, but it's good enough). */
9147 int fetch_align
= get_text_align_power(xtensa_fetch_width
);
9148 int sec_align
= get_recorded_alignment (sec
);
9150 if (sec_align
>= fetch_align
)
9157 /* This will assert if it is not possible. */
9160 get_text_align_nop_count (offsetT fill_size
, bfd_boolean use_no_density
)
9166 gas_assert (fill_size
% 3 == 0);
9167 return (fill_size
/ 3);
9170 gas_assert (fill_size
!= 1); /* Bad argument. */
9172 while (fill_size
> 1)
9175 if (fill_size
== 2 || fill_size
== 4)
9177 fill_size
-= insn_size
;
9180 gas_assert (fill_size
!= 1); /* Bad algorithm. */
9186 get_text_align_nth_nop_size (offsetT fill_size
,
9188 bfd_boolean use_no_density
)
9195 gas_assert (fill_size
!= 1); /* Bad argument. */
9197 while (fill_size
> 1)
9200 if (fill_size
== 2 || fill_size
== 4)
9202 fill_size
-= insn_size
;
9212 /* For the given fragment, find the appropriate address
9213 for it to begin at if we are using NOPs to align it. */
9216 get_noop_aligned_address (fragS
*fragP
, addressT address
)
9218 /* The rule is: get next fragment's FIRST instruction. Find
9219 the smallest number of bytes that need to be added to
9220 ensure that the next fragment's FIRST instruction will fit
9223 E.G., 2 bytes : 0, 1, 2 mod 4
9226 If the FIRST instruction MIGHT be relaxed,
9227 assume that it will become a 3-byte instruction.
9229 Note again here that LOOP instructions are not bundleable,
9230 and this relaxation only applies to LOOP opcodes. */
9233 int first_insn_size
;
9235 addressT pre_opcode_bytes
;
9238 xtensa_opcode opcode
;
9239 bfd_boolean is_loop
;
9241 gas_assert (fragP
->fr_type
== rs_machine_dependent
);
9242 gas_assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
9244 /* Find the loop frag. */
9245 first_insn
= next_non_empty_frag (fragP
);
9246 /* Now find the first insn frag. */
9247 first_insn
= next_non_empty_frag (first_insn
);
9249 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
9250 gas_assert (is_loop
);
9251 loop_insn_size
= xg_get_single_size (opcode
);
9253 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
9254 pre_opcode_bytes
+= loop_insn_size
;
9256 /* For loops, the alignment depends on the size of the
9257 instruction following the loop, not the LOOP instruction. */
9259 if (first_insn
== NULL
)
9260 first_insn_size
= xtensa_fetch_width
;
9262 first_insn_size
= get_loop_align_size (frag_format_size (first_insn
));
9264 /* If it was 8, then we'll need a larger alignment for the section. */
9265 align_power
= get_text_align_power (first_insn_size
);
9266 record_alignment (now_seg
, align_power
);
9268 fill_size
= get_text_align_fill_size
9269 (address
+ pre_opcode_bytes
, align_power
, first_insn_size
, TRUE
,
9270 fragP
->tc_frag_data
.is_no_density
);
9272 return address
+ fill_size
;
9276 /* 3 mechanisms for relaxing an alignment:
9278 Align to a power of 2.
9279 Align so the next fragment's instruction does not cross a word boundary.
9280 Align the current instruction so that if the next instruction
9281 were 3 bytes, it would not cross a word boundary.
9285 zeros - This is easy; always insert zeros.
9286 nops - 3-byte and 2-byte instructions
9290 >=5 : 3-byte instruction + fn (n-3)
9291 widening - widen previous instructions. */
9294 get_aligned_diff (fragS
*fragP
, addressT address
, offsetT
*max_diff
)
9296 addressT target_address
, loop_insn_offset
;
9298 xtensa_opcode loop_opcode
;
9299 bfd_boolean is_loop
;
9302 offsetT branch_align
;
9305 gas_assert (fragP
->fr_type
== rs_machine_dependent
);
9306 switch (fragP
->fr_subtype
)
9308 case RELAX_DESIRE_ALIGN
:
9309 target_size
= next_frag_format_size (fragP
);
9310 if (target_size
== XTENSA_UNDEFINED
)
9312 align_power
= branch_align_power (now_seg
);
9313 branch_align
= 1 << align_power
;
9314 /* Don't count on the section alignment being as large as the target. */
9315 if (target_size
> branch_align
)
9316 target_size
= branch_align
;
9317 opt_diff
= get_text_align_fill_size (address
, align_power
,
9318 target_size
, FALSE
, FALSE
);
9320 *max_diff
= (opt_diff
+ branch_align
9321 - (target_size
+ ((address
+ opt_diff
) % branch_align
)));
9322 gas_assert (*max_diff
>= opt_diff
);
9325 case RELAX_ALIGN_NEXT_OPCODE
:
9326 /* The next non-empty frag after this one holds the LOOP instruction
9327 that needs to be aligned. The required alignment depends on the
9328 size of the next non-empty frag after the loop frag, i.e., the
9329 first instruction in the loop. */
9330 loop_frag
= next_non_empty_frag (fragP
);
9331 target_size
= get_loop_align_size (next_frag_format_size (loop_frag
));
9332 loop_insn_offset
= 0;
9333 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
9334 gas_assert (is_loop
);
9336 /* If the loop has been expanded then the LOOP instruction
9337 could be at an offset from this fragment. */
9338 if (loop_frag
->tc_frag_data
.slot_subtypes
[0] != RELAX_IMMED
)
9339 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
9341 /* In an ideal world, which is what we are shooting for here,
9342 we wouldn't need to use any NOPs immediately prior to the
9343 LOOP instruction. If this approach fails, relax_frag_loop_align
9344 will call get_noop_aligned_address. */
9346 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
9347 align_power
= get_text_align_power (target_size
);
9348 opt_diff
= get_text_align_fill_size (target_address
, align_power
,
9349 target_size
, FALSE
, FALSE
);
9351 *max_diff
= xtensa_fetch_width
9352 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
9353 - target_size
+ opt_diff
;
9354 gas_assert (*max_diff
>= opt_diff
);
9365 /* md_relax_frag Hook and Helper Functions. */
9367 static long relax_frag_loop_align (fragS
*, long);
9368 static long relax_frag_for_align (fragS
*, long);
9369 static long relax_frag_immed
9370 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
9372 /* Get projected address for the first fulcrum on a path from source to
9374 static addressT
xg_get_fulcrum (addressT source
, addressT target
)
9376 offsetT delta
= target
- source
;
9379 n
= (labs (delta
) + J_RANGE
- J_MARGIN
- 1) / (J_RANGE
- J_MARGIN
);
9380 return source
+ delta
/ n
;
9383 /* Given trampoline index, source and target of a jump find the best
9384 candidate trampoline for the first fulcrum. The best trampoline is
9385 the one in the reach of "j' instruction from the source, closest to
9386 the projected fulcrum address, and preferrably w/o a jump around or
9387 with already initialized jump around. */
9388 static size_t xg_find_best_trampoline (struct trampoline_index
*idx
,
9389 addressT source
, addressT target
)
9391 addressT fulcrum
= xg_get_fulcrum (source
, target
);
9394 size_t base_tr
= xg_find_trampoline (idx
, fulcrum
);
9397 /* Check trampoline frags around the base_tr to find the best. */
9398 for (dist
= 0; checked
; ++dist
)
9401 size_t tr
= base_tr
- dist
;
9405 /* Trampolines are checked in the following order:
9406 base_tr, base_tr + 1, base_tr - 1, base_tr + 2, base_tr - 2 */
9407 for (i
= 0; i
< 2; ++i
, tr
= base_tr
+ dist
+ 1)
9408 if (tr
< idx
->n_entries
)
9410 fragS
*trampoline_frag
= idx
->entry
[tr
];
9413 /* Don't check trampolines outside source - target interval. */
9414 if ((trampoline_frag
->fr_address
< source
&&
9415 trampoline_frag
->fr_address
< target
) ||
9416 (trampoline_frag
->fr_address
> source
&&
9417 trampoline_frag
->fr_address
> target
))
9420 /* Don't choose trampoline that contains the source. */
9421 if (source
>= trampoline_frag
->fr_address
9422 && source
<= trampoline_frag
->fr_address
+
9423 trampoline_frag
->fr_fix
)
9426 off
= trampoline_frag
->fr_address
- fulcrum
;
9427 /* Stop if some trampoline is found and the search is more than
9428 J_RANGE / 4 from the projected fulcrum. A trampoline w/o jump
9429 around is nice, but it shouldn't have much overhead. */
9430 if (best
< idx
->n_entries
&& labs (off
) > J_RANGE
/ 4)
9433 off
= trampoline_frag
->fr_address
- source
;
9434 if (labs (off
) < J_RANGE
- J_MARGIN
)
9437 /* Stop if a trampoline w/o jump around is found or initialized
9438 trampoline with jump around is found. */
9439 if (!trampoline_frag
->tc_frag_data
.needs_jump_around
||
9440 trampoline_frag
->fr_fix
)
9442 else if (best
>= idx
->n_entries
)
9448 if (best
< idx
->n_entries
)
9451 as_fatal (_("cannot find suitable trampoline"));
9454 static fixS
*xg_relax_fixup (struct trampoline_index
*idx
, fixS
*fixP
)
9456 symbolS
*s
= fixP
->fx_addsy
;
9457 addressT source
= fixP
->fx_frag
->fr_address
;
9458 addressT target
= S_GET_VALUE (s
) + fixP
->fx_offset
;
9459 size_t tr
= xg_find_best_trampoline (idx
, source
, target
);
9460 fragS
*trampoline_frag
= idx
->entry
[tr
];
9463 init_trampoline_frag (trampoline_frag
);
9464 newfixP
= xg_append_jump (trampoline_frag
,
9465 fixP
->fx_addsy
, fixP
->fx_offset
);
9467 /* Adjust the fixup for the original "j" instruction to
9468 point to the newly added jump. */
9469 fixP
->fx_addsy
= trampoline_frag
->fr_symbol
;
9470 fixP
->fx_offset
= trampoline_frag
->fr_fix
- 3;
9471 fixP
->tc_fix_data
.X_add_symbol
= trampoline_frag
->fr_symbol
;
9472 fixP
->tc_fix_data
.X_add_number
= trampoline_frag
->fr_fix
- 3;
9474 trampoline_frag
->tc_frag_data
.relax_seen
= FALSE
;
9476 if (xg_is_trampoline_frag_full (trampoline_frag
))
9477 xg_remove_trampoline_from_index (idx
, tr
);
9482 static bfd_boolean
xg_is_relaxable_fixup (fixS
*fixP
)
9484 xtensa_isa isa
= xtensa_default_isa
;
9485 addressT addr
= fixP
->fx_frag
->fr_address
;
9488 symbolS
*s
= fixP
->fx_addsy
;
9491 xtensa_opcode opcode
;
9493 if (fixP
->fx_r_type
< BFD_RELOC_XTENSA_SLOT0_OP
||
9494 fixP
->fx_r_type
> BFD_RELOC_XTENSA_SLOT14_OP
)
9497 target
= S_GET_VALUE (s
) + fixP
->fx_offset
;
9498 delta
= target
- addr
;
9500 if (labs (delta
) < J_RANGE
- J_MARGIN
)
9503 xtensa_insnbuf_from_chars (isa
, trampoline_buf
,
9504 (unsigned char *) fixP
->fx_frag
->fr_literal
+
9506 fmt
= xtensa_format_decode (isa
, trampoline_buf
);
9507 gas_assert (fmt
!= XTENSA_UNDEFINED
);
9508 slot
= fixP
->tc_fix_data
.slot
;
9509 xtensa_format_get_slot (isa
, fmt
, slot
, trampoline_buf
, trampoline_slotbuf
);
9510 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, trampoline_slotbuf
);
9511 return opcode
== xtensa_j_opcode
;
9514 static void xg_relax_fixups (struct trampoline_seg
*ts
)
9516 struct trampoline_index
*idx
= &ts
->index
;
9517 segment_info_type
*seginfo
= seg_info (now_seg
);
9520 for (fx
= seginfo
->fix_root
; fx
; fx
= fx
->fx_next
)
9523 struct trampoline_chain
*tc
= NULL
;
9525 if (xg_is_relaxable_fixup (fixP
))
9527 tc
= xg_find_best_eq_target (ts
, fixP
->fx_frag
->fr_address
,
9528 &fixP
->fx_addsy
, &fixP
->fx_offset
);
9530 tc
= xg_create_trampoline_chain (ts
, fixP
->fx_addsy
,
9535 while (xg_is_relaxable_fixup (fixP
))
9537 fixP
= xg_relax_fixup (idx
, fixP
);
9538 xg_add_location_to_chain (tc
, fixP
->fx_frag
->fr_symbol
,
9544 /* Given a trampoline frag relax all jumps that might want to use this
9545 trampoline. Only do real work once per relaxation cycle, when
9546 xg_relax_trampoline is called for the first trampoline in the now_seg.
9547 Don't use stretch, don't update new_stretch: place fulcrums with a
9548 slack to tolerate code movement. In the worst case if a jump between
9549 two trampolines wouldn't reach the next relaxation pass will fix it. */
9550 static void xg_relax_trampoline (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
,
9551 long *new_stretch ATTRIBUTE_UNUSED
)
9553 struct trampoline_seg
*ts
= find_trampoline_seg (now_seg
);
9555 if (ts
->index
.n_entries
&& ts
->index
.entry
[0] == fragP
)
9556 xg_relax_fixups (ts
);
9559 /* Return the number of bytes added to this fragment, given that the
9560 input has been stretched already by "stretch". */
9563 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
9565 xtensa_isa isa
= xtensa_default_isa
;
9566 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
9567 long new_stretch
= 0;
9568 const char *file_name
;
9571 static xtensa_insnbuf vbuf
= NULL
;
9572 int slot
, num_slots
;
9575 file_name
= as_where (&line
);
9576 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
9578 fragP
->tc_frag_data
.unreported_expansion
= 0;
9580 switch (fragP
->fr_subtype
)
9582 case RELAX_ALIGN_NEXT_OPCODE
:
9583 /* Always convert. */
9584 if (fragP
->tc_frag_data
.relax_seen
)
9585 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
9588 case RELAX_LOOP_END
:
9592 case RELAX_LOOP_END_ADD_NOP
:
9593 /* Add a NOP and switch to .fill 0. */
9594 new_stretch
= relax_frag_add_nop (fragP
);
9598 case RELAX_DESIRE_ALIGN
:
9599 /* Do nothing. The narrowing before this frag will either align
9604 case RELAX_LITERAL_FINAL
:
9607 case RELAX_LITERAL_NR
:
9609 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
9610 gas_assert (unreported
== lit_size
);
9611 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
9612 fragP
->fr_var
-= lit_size
;
9613 fragP
->fr_fix
+= lit_size
;
9619 vbuf
= xtensa_insnbuf_alloc (isa
);
9621 xtensa_insnbuf_from_chars
9622 (isa
, vbuf
, (unsigned char *) fragP
->fr_opcode
, 0);
9623 fmt
= xtensa_format_decode (isa
, vbuf
);
9624 num_slots
= xtensa_format_num_slots (isa
, fmt
);
9626 for (slot
= 0; slot
< num_slots
; slot
++)
9628 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
9631 if (fragP
->tc_frag_data
.relax_seen
)
9632 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
9636 case RELAX_IMMED_STEP1
:
9637 case RELAX_IMMED_STEP2
:
9638 case RELAX_IMMED_STEP3
:
9639 /* Place the immediate. */
9640 new_stretch
+= relax_frag_immed
9641 (now_seg
, fragP
, stretch
,
9642 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
9643 fmt
, slot
, stretched_p
, FALSE
);
9647 /* This is OK; see the note in xg_assemble_vliw_tokens. */
9653 case RELAX_LITERAL_POOL_BEGIN
:
9654 if (fragP
->fr_var
!= 0)
9656 /* We have a converted "candidate" literal pool;
9657 assemble a jump around it. */
9659 if (!litpool_slotbuf
)
9661 litpool_buf
= xtensa_insnbuf_alloc (isa
);
9662 litpool_slotbuf
= xtensa_insnbuf_alloc (isa
);
9665 fragP
->tc_frag_data
.relax_seen
= FALSE
; /* Need another pass. */
9666 fragP
->tc_frag_data
.is_insn
= TRUE
;
9668 insn
.insn_type
= ITYPE_INSN
;
9669 insn
.opcode
= xtensa_j_opcode
;
9671 set_expr_symbol_offset (&insn
.tok
[0], fragP
->fr_symbol
,
9673 fmt
= xg_get_single_format (xtensa_j_opcode
);
9674 tinsn_to_slotbuf (fmt
, 0, &insn
, litpool_slotbuf
);
9675 xtensa_format_set_slot (isa
, fmt
, 0, litpool_buf
, litpool_slotbuf
);
9676 xtensa_insnbuf_to_chars (isa
, litpool_buf
,
9677 (unsigned char *)fragP
->fr_literal
+
9682 fix_new (fragP
, 0, 3, fragP
->fr_symbol
, 0, TRUE
,
9683 BFD_RELOC_XTENSA_SLOT0_OP
);
9687 case RELAX_LITERAL_POOL_END
:
9688 case RELAX_LITERAL_POOL_CANDIDATE_BEGIN
:
9689 case RELAX_MAYBE_UNREACHABLE
:
9690 case RELAX_MAYBE_DESIRE_ALIGN
:
9691 /* No relaxation required. */
9694 case RELAX_FILL_NOP
:
9695 case RELAX_UNREACHABLE
:
9696 if (fragP
->tc_frag_data
.relax_seen
)
9697 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
9700 case RELAX_TRAMPOLINE
:
9701 if (fragP
->tc_frag_data
.relax_seen
)
9702 xg_relax_trampoline (fragP
, stretch
, &new_stretch
);
9706 as_bad (_("bad relaxation state"));
9709 /* Tell gas we need another relaxation pass. */
9710 if (! fragP
->tc_frag_data
.relax_seen
)
9712 fragP
->tc_frag_data
.relax_seen
= TRUE
;
9716 new_logical_line (file_name
, line
);
9722 relax_frag_loop_align (fragS
*fragP
, long stretch
)
9724 addressT old_address
, old_next_address
, old_size
;
9725 addressT new_address
, new_next_address
, new_size
;
9728 /* All the frags with relax_frag_for_alignment prior to this one in the
9729 section have been done, hopefully eliminating the need for a NOP here.
9730 But, this will put it in if necessary. */
9732 /* Calculate the old address of this fragment and the next fragment. */
9733 old_address
= fragP
->fr_address
- stretch
;
9734 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
9735 fragP
->tc_frag_data
.text_expansion
[0]);
9736 old_size
= old_next_address
- old_address
;
9738 /* Calculate the new address of this fragment and the next fragment. */
9739 new_address
= fragP
->fr_address
;
9741 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
9742 new_size
= new_next_address
- new_address
;
9744 growth
= new_size
- old_size
;
9746 /* Fix up the text_expansion field and return the new growth. */
9747 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
9752 /* Add a NOP instruction. */
9755 relax_frag_add_nop (fragS
*fragP
)
9757 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
9758 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
9759 assemble_nop (length
, nop_buf
);
9760 fragP
->tc_frag_data
.is_insn
= TRUE
;
9762 if (fragP
->fr_var
< length
)
9764 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP
->fr_var
, length
);
9768 fragP
->fr_fix
+= length
;
9769 fragP
->fr_var
-= length
;
9774 static long future_alignment_required (fragS
*, long);
9777 relax_frag_for_align (fragS
*fragP
, long stretch
)
9779 /* Overview of the relaxation procedure for alignment:
9780 We can widen with NOPs or by widening instructions or by filling
9781 bytes after jump instructions. Find the opportune places and widen
9782 them if necessary. */
9787 gas_assert (fragP
->fr_subtype
== RELAX_FILL_NOP
9788 || fragP
->fr_subtype
== RELAX_UNREACHABLE
9789 || (fragP
->fr_subtype
== RELAX_SLOTS
9790 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
9792 stretch_me
= future_alignment_required (fragP
, stretch
);
9793 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
9799 /* We expanded on a previous pass. Can we shrink now? */
9800 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
9801 if (shrink
<= stretch
&& stretch
> 0)
9803 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
9809 /* Below here, diff > 0. */
9810 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
9816 /* Return the address of the next frag that should be aligned.
9818 By "address" we mean the address it _would_ be at if there
9819 is no action taken to align it between here and the target frag.
9820 In other words, if no narrows and no fill nops are used between
9821 here and the frag to align, _even_if_ some of the frags we use
9822 to align targets have already expanded on a previous relaxation
9825 Also, count each frag that may be used to help align the target.
9827 Return 0 if there are no frags left in the chain that need to be
9831 find_address_of_next_align_frag (fragS
**fragPP
,
9835 bfd_boolean
*paddable
)
9837 fragS
*fragP
= *fragPP
;
9838 addressT address
= fragP
->fr_address
;
9840 /* Do not reset the counts to 0. */
9844 /* Limit this to a small search. */
9845 if (*widens
>= (int) xtensa_fetch_width
)
9850 address
+= fragP
->fr_fix
;
9852 if (fragP
->fr_type
== rs_fill
)
9853 address
+= fragP
->fr_offset
* fragP
->fr_var
;
9854 else if (fragP
->fr_type
== rs_machine_dependent
)
9856 switch (fragP
->fr_subtype
)
9858 case RELAX_UNREACHABLE
:
9862 case RELAX_FILL_NOP
:
9864 if (!fragP
->tc_frag_data
.is_no_density
)
9869 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
9874 address
+= total_frag_text_expansion (fragP
);
9878 address
+= fragP
->tc_frag_data
.text_expansion
[0];
9881 case RELAX_ALIGN_NEXT_OPCODE
:
9882 case RELAX_DESIRE_ALIGN
:
9886 case RELAX_MAYBE_UNREACHABLE
:
9887 case RELAX_MAYBE_DESIRE_ALIGN
:
9892 /* Just punt if we don't know the type. */
9899 /* Just punt if we don't know the type. */
9903 fragP
= fragP
->fr_next
;
9911 static long bytes_to_stretch (fragS
*, int, int, int, int);
9914 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
9916 fragS
*this_frag
= fragP
;
9920 int narrow_nops
= 0;
9921 bfd_boolean paddable
= FALSE
;
9922 offsetT local_opt_diff
;
9925 int stretch_amount
= 0;
9926 int local_stretch_amount
;
9927 int global_stretch_amount
;
9929 address
= find_address_of_next_align_frag
9930 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
9934 if (this_frag
->tc_frag_data
.is_aligning_branch
)
9935 this_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
9937 frag_wane (this_frag
);
9941 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
9942 opt_diff
= local_opt_diff
;
9943 gas_assert (opt_diff
>= 0);
9944 gas_assert (max_diff
>= opt_diff
);
9949 fragP
= fragP
->fr_next
;
9951 while (fragP
&& opt_diff
< max_diff
&& address
)
9953 /* We only use these to determine if we can exit early
9954 because there will be plenty of ways to align future
9956 int glob_widens
= 0;
9959 bfd_boolean glob_pad
= 0;
9960 address
= find_address_of_next_align_frag
9961 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
9962 /* If there is a padable portion, then skip. */
9963 if (glob_pad
|| glob_widens
>= (1 << branch_align_power (now_seg
)))
9968 offsetT next_m_diff
;
9969 offsetT next_o_diff
;
9971 /* Downrange frags haven't had stretch added to them yet. */
9974 /* The address also includes any text expansion from this
9975 frag in a previous pass, but we don't want that. */
9976 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
9978 /* Assume we are going to move at least opt_diff. In
9979 reality, we might not be able to, but assuming that
9980 we will helps catch cases where moving opt_diff pushes
9981 the next target from aligned to unaligned. */
9982 address
+= opt_diff
;
9984 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
9986 /* Now cleanup for the adjustments to address. */
9987 next_o_diff
+= opt_diff
;
9988 next_m_diff
+= opt_diff
;
9989 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
9990 opt_diff
= next_o_diff
;
9991 if (next_m_diff
< max_diff
)
9992 max_diff
= next_m_diff
;
9993 fragP
= fragP
->fr_next
;
9997 /* If there are enough wideners in between, do it. */
10000 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
10002 gas_assert (opt_diff
<= (signed) xtensa_fetch_width
);
10007 local_stretch_amount
10008 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
10009 num_widens
, local_opt_diff
);
10010 global_stretch_amount
10011 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
10012 num_widens
, opt_diff
);
10013 /* If the condition below is true, then the frag couldn't
10014 stretch the correct amount for the global case, so we just
10015 optimize locally. We'll rely on the subsequent frags to get
10016 the correct alignment in the global case. */
10017 if (global_stretch_amount
< local_stretch_amount
)
10018 stretch_amount
= local_stretch_amount
;
10020 stretch_amount
= global_stretch_amount
;
10022 if (this_frag
->fr_subtype
== RELAX_SLOTS
10023 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
10024 gas_assert (stretch_amount
<= 1);
10025 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
10027 if (this_frag
->tc_frag_data
.is_no_density
)
10028 gas_assert (stretch_amount
== 3 || stretch_amount
== 0);
10030 gas_assert (stretch_amount
<= 3);
10033 return stretch_amount
;
10037 /* The idea: widen everything you can to get a target or loop aligned,
10038 then start using NOPs.
10040 wide_nops = the number of wide NOPs available for aligning
10041 narrow_nops = the number of narrow NOPs available for aligning
10042 (a subset of wide_nops)
10043 widens = the number of narrow instructions that should be widened
10048 bytes_to_stretch (fragS
*this_frag
,
10057 int bytes_short
= desired_diff
- num_widens
;
10059 gas_assert (desired_diff
>= 0
10060 && desired_diff
< (signed) xtensa_fetch_width
);
10061 if (desired_diff
== 0)
10064 gas_assert (wide_nops
> 0 || num_widens
> 0);
10066 /* Always prefer widening to NOP-filling. */
10067 if (bytes_short
< 0)
10069 /* There are enough RELAX_NARROW frags after this one
10070 to align the target without widening this frag in any way. */
10074 if (bytes_short
== 0)
10076 /* Widen every narrow between here and the align target
10077 and the align target will be properly aligned. */
10078 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
10084 /* From here we will need at least one NOP to get an alignment.
10085 However, we may not be able to align at all, in which case,
10087 nops_needed
= desired_diff
/ 3;
10089 /* If there aren't enough nops, don't widen. */
10090 if (nops_needed
> wide_nops
)
10093 /* First try it with all wide nops. */
10094 nop_bytes
= nops_needed
* 3;
10095 extra_bytes
= desired_diff
- nop_bytes
;
10097 if (nop_bytes
+ num_widens
>= desired_diff
)
10099 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
10101 else if (num_widens
== extra_bytes
)
10106 /* Add a narrow nop. */
10110 if (narrow_nops
== 0 || nops_needed
> wide_nops
)
10113 if (nop_bytes
+ num_widens
>= desired_diff
&& extra_bytes
>= 0)
10115 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
10116 return !this_frag
->tc_frag_data
.is_no_density
? 2 : 3;
10117 else if (num_widens
== extra_bytes
)
10122 /* Replace a wide nop with a narrow nop--we can get here if
10123 extra_bytes was negative in the previous conditional. */
10124 if (narrow_nops
== 1)
10128 if (nop_bytes
+ num_widens
>= desired_diff
)
10130 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
10131 return !this_frag
->tc_frag_data
.is_no_density
? 2 : 3;
10132 else if (num_widens
== extra_bytes
)
10137 /* If we can't satisfy any of the above cases, then we can't align
10138 using padding or fill nops. */
10144 xg_find_best_trampoline_for_tinsn (TInsn
*tinsn
, fragS
*fragP
)
10146 symbolS
*sym
= tinsn
->tok
[0].X_add_symbol
;
10147 addressT source
= fragP
->fr_address
;
10148 addressT target
= S_GET_VALUE (sym
) + tinsn
->tok
[0].X_add_number
;
10149 struct trampoline_seg
*ts
= find_trampoline_seg (now_seg
);
10152 if (!ts
|| !ts
->index
.n_entries
)
10155 i
= xg_find_best_trampoline (&ts
->index
, source
, target
);
10157 return ts
->index
.entry
[i
];
10161 /* Append jump to sym + offset to the end of the trampoline frag fragP.
10162 Adjust fragP's jump around if it's present. Adjust fragP's fr_fix/fr_var
10163 and finish the frag if it's full (but don't remove it from the trampoline
10164 frag index). Return fixup for the newly created jump. */
10165 static fixS
*xg_append_jump (fragS
*fragP
, symbolS
*sym
, offsetT offset
)
10170 xtensa_isa isa
= xtensa_default_isa
;
10172 gas_assert (fragP
->fr_var
>= 3);
10173 tinsn_init (&insn
);
10174 insn
.insn_type
= ITYPE_INSN
;
10175 insn
.opcode
= xtensa_j_opcode
;
10177 set_expr_symbol_offset (&insn
.tok
[0], sym
, offset
);
10178 fmt
= xg_get_single_format (xtensa_j_opcode
);
10179 tinsn_to_slotbuf (fmt
, 0, &insn
, trampoline_slotbuf
);
10180 xtensa_format_set_slot (isa
, fmt
, 0, trampoline_buf
, trampoline_slotbuf
);
10181 xtensa_insnbuf_to_chars (isa
, trampoline_buf
,
10182 (unsigned char *)fragP
->fr_literal
+ fragP
->fr_fix
, 3);
10183 fixP
= fix_new (fragP
, fragP
->fr_fix
, 3, sym
, offset
, TRUE
,
10184 BFD_RELOC_XTENSA_SLOT0_OP
);
10185 fixP
->tc_fix_data
.slot
= 0;
10187 fragP
->fr_fix
+= 3;
10188 fragP
->fr_var
-= 3;
10190 /* Adjust the jump around this trampoline (if present). */
10191 if (fragP
->tc_frag_data
.jump_around_fix
)
10192 fragP
->tc_frag_data
.jump_around_fix
->fx_offset
+= 3;
10194 /* Do we have room for more? */
10195 if (xg_is_trampoline_frag_full (fragP
))
10198 fragP
->fr_subtype
= 0;
10206 init_trampoline_frag (fragS
*fp
)
10210 if (fp
->fr_fix
== 0)
10213 char label
[10 + 2 * sizeof(fp
)];
10215 sprintf (label
, ".L0_TR_%p", fp
);
10216 lsym
= (symbolS
*) local_symbol_make (label
, now_seg
, fp
, 0);
10217 fp
->fr_symbol
= lsym
;
10218 if (fp
->tc_frag_data
.needs_jump_around
)
10220 fp
->tc_frag_data
.jump_around_fix
= xg_append_jump (fp
, lsym
, 3);
10228 xg_get_single_symbol_slot (fragS
*fragP
)
10233 for (i
= 0; i
< MAX_SLOTS
; ++i
)
10234 if (fragP
->tc_frag_data
.slot_symbols
[i
])
10236 gas_assert (slot
== -1);
10240 gas_assert (slot
>= 0 && slot
< MAX_SLOTS
);
10246 add_jump_to_trampoline (fragS
*tramp
, fragS
*origfrag
)
10248 int slot
= xg_get_single_symbol_slot (origfrag
);
10251 /* Assemble a jump to the target label in the trampoline frag. */
10252 fixP
= xg_append_jump (tramp
,
10253 origfrag
->tc_frag_data
.slot_symbols
[slot
],
10254 origfrag
->tc_frag_data
.slot_offsets
[slot
]);
10256 /* Modify the original j to point here. */
10257 origfrag
->tc_frag_data
.slot_symbols
[slot
] = tramp
->fr_symbol
;
10258 origfrag
->tc_frag_data
.slot_offsets
[slot
] = tramp
->fr_fix
- 3;
10260 /* If trampoline is full, remove it from the list. */
10261 if (xg_is_trampoline_frag_full (tramp
))
10263 struct trampoline_seg
*ts
= find_trampoline_seg (now_seg
);
10264 size_t tr
= xg_find_trampoline (&ts
->index
, tramp
->fr_address
);
10266 gas_assert (ts
->index
.entry
[tr
] == tramp
);
10267 xg_remove_trampoline_from_index (&ts
->index
, tr
);
10275 relax_frag_immed (segT segP
,
10282 bfd_boolean estimate_only
)
10286 bfd_boolean negatable_branch
= FALSE
;
10287 bfd_boolean branch_jmp_to_next
= FALSE
;
10288 bfd_boolean from_wide_insn
= FALSE
;
10289 xtensa_isa isa
= xtensa_default_isa
;
10291 offsetT frag_offset
;
10293 int num_text_bytes
, num_literal_bytes
;
10294 int literal_diff
, total_text_diff
, this_text_diff
;
10296 gas_assert (fragP
->fr_opcode
!= NULL
);
10298 xg_clear_vinsn (&cur_vinsn
);
10299 vinsn_from_chars (&cur_vinsn
, fragP
->fr_opcode
);
10300 if (cur_vinsn
.num_slots
> 1)
10301 from_wide_insn
= TRUE
;
10303 tinsn
= cur_vinsn
.slots
[slot
];
10304 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
10306 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
) == 1)
10309 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
10310 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
10312 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
10314 old_size
= xtensa_format_length (isa
, fmt
);
10316 /* Special case: replace a branch to the next instruction with a NOP.
10317 This is required to work around a hardware bug in T1040.0 and also
10318 serves as an optimization. */
10320 if (branch_jmp_to_next
10321 && ((old_size
== 2) || (old_size
== 3))
10322 && !next_frag_is_loop_target (fragP
))
10325 /* Here is the fun stuff: Get the immediate field from this
10326 instruction. If it fits, we are done. If not, find the next
10327 instruction sequence that fits. */
10329 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
10330 istack_init (&istack
);
10331 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
10332 min_steps
, stretch
);
10333 gas_assert (num_steps
>= min_steps
&& num_steps
<= RELAX_IMMED_MAXSTEPS
);
10335 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
10337 /* Figure out the number of bytes needed. */
10338 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
10340 = num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
10341 num_text_bytes
= get_num_stack_text_bytes (&istack
);
10343 if (from_wide_insn
)
10346 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
10349 num_text_bytes
+= old_size
;
10350 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
10351 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
10354 /* The first instruction in the relaxed sequence will go after
10355 the current wide instruction, and thus its symbolic immediates
10358 istack_init (&istack
);
10359 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
,
10360 frag_offset
+ old_size
,
10361 min_steps
, stretch
+ old_size
);
10362 gas_assert (num_steps
>= min_steps
&& num_steps
<= RELAX_IMMED_MAXSTEPS
);
10364 fragP
->tc_frag_data
.slot_subtypes
[slot
]
10365 = (int) RELAX_IMMED
+ num_steps
;
10367 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
10369 = num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
10371 num_text_bytes
= get_num_stack_text_bytes (&istack
) + old_size
;
10375 total_text_diff
= num_text_bytes
- old_size
;
10376 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
10378 /* It MUST get larger. If not, we could get an infinite loop. */
10379 gas_assert (num_text_bytes
>= 0);
10380 gas_assert (literal_diff
>= 0);
10381 gas_assert (total_text_diff
>= 0);
10383 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
10384 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
10385 gas_assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
10386 gas_assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
10388 /* Find the associated expandable literal for this. */
10389 if (literal_diff
!= 0)
10391 fragS
*lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
10394 gas_assert (literal_diff
== 4);
10395 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
10397 /* We expect that the literal section state has NOT been
10399 gas_assert (lit_fragP
->fr_type
== rs_machine_dependent
10400 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
10401 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
10403 /* We need to mark this section for another iteration
10409 if (negatable_branch
&& istack
.ninsn
> 1)
10410 update_next_frag_state (fragP
);
10412 /* If last insn is a jump, and it cannot reach its target, try to find a trampoline. */
10413 if (istack
.ninsn
> 2 &&
10414 istack
.insn
[istack
.ninsn
- 1].insn_type
== ITYPE_LABEL
&&
10415 istack
.insn
[istack
.ninsn
- 2].insn_type
== ITYPE_INSN
&&
10416 istack
.insn
[istack
.ninsn
- 2].opcode
== xtensa_j_opcode
)
10418 TInsn
*jinsn
= &istack
.insn
[istack
.ninsn
- 2];
10419 struct trampoline_seg
*ts
= find_trampoline_seg (segP
);
10420 struct trampoline_chain
*tc
= NULL
;
10423 !xg_symbolic_immeds_fit (jinsn
, segP
, fragP
, fragP
->fr_offset
,
10426 int s
= xg_get_single_symbol_slot (fragP
);
10427 addressT offset
= fragP
->tc_frag_data
.slot_offsets
[s
];
10429 tc
= xg_find_best_eq_target (ts
, fragP
->fr_address
,
10430 &fragP
->tc_frag_data
.slot_symbols
[s
],
10434 tc
= xg_create_trampoline_chain (ts
,
10435 fragP
->tc_frag_data
.slot_symbols
[s
],
10437 fragP
->tc_frag_data
.slot_offsets
[s
] = offset
;
10438 tinsn_immed_from_frag (jinsn
, fragP
, s
);
10441 if (!xg_symbolic_immeds_fit (jinsn
, segP
, fragP
, fragP
->fr_offset
,
10444 fragS
*tf
= xg_find_best_trampoline_for_tinsn (jinsn
, fragP
);
10450 this_text_diff
+= init_trampoline_frag (tf
) + 3;
10451 fixP
= add_jump_to_trampoline (tf
, fragP
);
10452 xg_add_location_to_chain (tc
, fixP
->fx_frag
->fr_symbol
,
10454 fragP
->tc_frag_data
.relax_seen
= FALSE
;
10458 /* If target symbol is undefined, assume it will reach once linked. */
10459 expressionS
*exp
= &istack
.insn
[istack
.ninsn
- 2].tok
[0];
10461 if (exp
->X_op
== O_symbol
&& S_IS_DEFINED (exp
->X_add_symbol
))
10463 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
10464 _("jump target out of range; no usable trampoline found"));
10470 return this_text_diff
;
10474 /* md_convert_frag Hook and Helper Functions. */
10476 static void convert_frag_align_next_opcode (fragS
*);
10477 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
10478 static void convert_frag_fill_nop (fragS
*);
10479 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
10482 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
10484 static xtensa_insnbuf vbuf
= NULL
;
10485 xtensa_isa isa
= xtensa_default_isa
;
10489 const char *file_name
;
10492 file_name
= as_where (&line
);
10493 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
10495 switch (fragp
->fr_subtype
)
10497 case RELAX_ALIGN_NEXT_OPCODE
:
10498 /* Always convert. */
10499 convert_frag_align_next_opcode (fragp
);
10502 case RELAX_DESIRE_ALIGN
:
10503 /* Do nothing. If not aligned already, too bad. */
10506 case RELAX_LITERAL
:
10507 case RELAX_LITERAL_FINAL
:
10512 vbuf
= xtensa_insnbuf_alloc (isa
);
10514 xtensa_insnbuf_from_chars
10515 (isa
, vbuf
, (unsigned char *) fragp
->fr_opcode
, 0);
10516 fmt
= xtensa_format_decode (isa
, vbuf
);
10517 num_slots
= xtensa_format_num_slots (isa
, fmt
);
10519 for (slot
= 0; slot
< num_slots
; slot
++)
10521 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
10524 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
10528 case RELAX_IMMED_STEP1
:
10529 case RELAX_IMMED_STEP2
:
10530 case RELAX_IMMED_STEP3
:
10531 /* Place the immediate. */
10534 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
10539 /* This is OK because some slots could have
10540 relaxations and others have none. */
10546 case RELAX_UNREACHABLE
:
10547 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
10548 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
10549 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
10553 case RELAX_MAYBE_UNREACHABLE
:
10554 case RELAX_MAYBE_DESIRE_ALIGN
:
10558 case RELAX_FILL_NOP
:
10559 convert_frag_fill_nop (fragp
);
10562 case RELAX_LITERAL_NR
:
10563 if (use_literal_section
)
10565 /* This should have been handled during relaxation. When
10566 relaxing a code segment, literals sometimes need to be
10567 added to the corresponding literal segment. If that
10568 literal segment has already been relaxed, then we end up
10569 in this situation. Marking the literal segments as data
10570 would make this happen less often (since GAS always relaxes
10571 code before data), but we could still get into trouble if
10572 there are instructions in a segment that is not marked as
10573 containing code. Until we can implement a better solution,
10574 cheat and adjust the addresses of all the following frags.
10575 This could break subsequent alignments, but the linker's
10576 literal coalescing will do that anyway. */
10579 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
10580 gas_assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
10581 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
10582 fragp
->fr_var
-= 4;
10583 fragp
->fr_fix
+= 4;
10584 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
10585 f
->fr_address
+= 4;
10588 as_bad (_("invalid relaxation fragment result"));
10591 case RELAX_TRAMPOLINE
:
10596 new_logical_line (file_name
, line
);
10601 convert_frag_align_next_opcode (fragS
*fragp
)
10603 char *nop_buf
; /* Location for Writing. */
10604 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
10605 addressT aligned_address
;
10607 int nop
, nop_count
;
10609 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
10611 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
10612 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
10613 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
10615 for (nop
= 0; nop
< nop_count
; nop
++)
10618 nop_size
= get_text_align_nth_nop_size (fill_size
, nop
, use_no_density
);
10620 assemble_nop (nop_size
, nop_buf
);
10621 nop_buf
+= nop_size
;
10624 fragp
->fr_fix
+= fill_size
;
10625 fragp
->fr_var
-= fill_size
;
10630 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
10632 TInsn tinsn
, single_target
;
10633 int size
, old_size
, diff
;
10634 offsetT frag_offset
;
10636 gas_assert (slot
== 0);
10637 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
10639 if (fragP
->tc_frag_data
.is_aligning_branch
== 1)
10641 gas_assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
10642 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
10643 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
10648 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
10650 /* No conversion. */
10655 gas_assert (fragP
->fr_opcode
!= NULL
);
10657 /* Frags in this relaxation state should only contain
10658 single instruction bundles. */
10659 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
10661 /* Just convert it to a wide form.... */
10663 old_size
= xg_get_single_size (tinsn
.opcode
);
10665 tinsn_init (&single_target
);
10666 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
10668 if (! xg_is_single_relaxable_insn (&tinsn
, &single_target
, FALSE
))
10670 as_bad (_("unable to widen instruction"));
10674 size
= xg_get_single_size (single_target
.opcode
);
10675 xg_emit_insn_to_buf (&single_target
, fragP
->fr_opcode
, fragP
,
10676 frag_offset
, TRUE
);
10678 diff
= size
- old_size
;
10679 gas_assert (diff
>= 0);
10680 gas_assert (diff
<= fragP
->fr_var
);
10681 fragP
->fr_var
-= diff
;
10682 fragP
->fr_fix
+= diff
;
10690 convert_frag_fill_nop (fragS
*fragP
)
10692 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
10693 int size
= fragP
->tc_frag_data
.text_expansion
[0];
10694 gas_assert ((unsigned) size
== (fragP
->fr_next
->fr_address
10695 - fragP
->fr_address
- fragP
->fr_fix
));
10698 /* No conversion. */
10702 assemble_nop (size
, loc
);
10703 fragP
->tc_frag_data
.is_insn
= TRUE
;
10704 fragP
->fr_var
-= size
;
10705 fragP
->fr_fix
+= size
;
10710 static fixS
*fix_new_exp_in_seg
10711 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
10712 bfd_reloc_code_real_type
);
10715 convert_frag_immed (segT segP
,
10721 char *immed_instr
= fragP
->fr_opcode
;
10723 bfd_boolean expanded
= FALSE
;
10724 bfd_boolean branch_jmp_to_next
= FALSE
;
10725 char *fr_opcode
= fragP
->fr_opcode
;
10726 xtensa_isa isa
= xtensa_default_isa
;
10727 bfd_boolean from_wide_insn
= FALSE
;
10729 bfd_boolean is_loop
;
10731 gas_assert (fr_opcode
!= NULL
);
10733 xg_clear_vinsn (&cur_vinsn
);
10735 vinsn_from_chars (&cur_vinsn
, fr_opcode
);
10736 if (cur_vinsn
.num_slots
> 1)
10737 from_wide_insn
= TRUE
;
10739 orig_tinsn
= cur_vinsn
.slots
[slot
];
10740 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
10742 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
10744 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
10745 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
10747 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
10749 /* Conversion just inserts a NOP and marks the fix as completed. */
10750 bytes
= xtensa_format_length (isa
, fmt
);
10753 cur_vinsn
.slots
[slot
].opcode
=
10754 xtensa_format_slot_nop_opcode (isa
, cur_vinsn
.format
, slot
);
10755 cur_vinsn
.slots
[slot
].ntok
= 0;
10759 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
10760 gas_assert (bytes
== 2 || bytes
== 3);
10761 build_nop (&cur_vinsn
.slots
[0], bytes
);
10762 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
10764 vinsn_to_insnbuf (&cur_vinsn
, fr_opcode
, frag_now
, TRUE
);
10765 xtensa_insnbuf_to_chars
10766 (isa
, cur_vinsn
.insnbuf
, (unsigned char *) fr_opcode
, 0);
10771 /* Here is the fun stuff: Get the immediate field from this
10772 instruction. If it fits, we're done. If not, find the next
10773 instruction sequence that fits. */
10777 symbolS
*lit_sym
= NULL
;
10778 int total_size
= 0;
10779 int target_offset
= 0;
10782 symbolS
*gen_label
= NULL
;
10783 offsetT frag_offset
;
10784 bfd_boolean first
= TRUE
;
10786 /* It does not fit. Find something that does and
10787 convert immediately. */
10788 frag_offset
= fr_opcode
- fragP
->fr_literal
;
10789 istack_init (&istack
);
10790 xg_assembly_relax (&istack
, &orig_tinsn
,
10791 segP
, fragP
, frag_offset
, min_steps
, 0);
10793 old_size
= xtensa_format_length (isa
, fmt
);
10795 /* Assemble this right inline. */
10797 /* First, create the mapping from a label name to the REAL label. */
10799 for (i
= 0; i
< istack
.ninsn
; i
++)
10801 TInsn
*tinsn
= &istack
.insn
[i
];
10804 switch (tinsn
->insn_type
)
10806 case ITYPE_LITERAL
:
10807 if (lit_sym
!= NULL
)
10808 as_bad (_("multiple literals in expansion"));
10809 /* First find the appropriate space in the literal pool. */
10810 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
10811 if (lit_frag
== NULL
)
10812 as_bad (_("no registered fragment for literal"));
10813 if (tinsn
->ntok
!= 1)
10814 as_bad (_("number of literal tokens != 1"));
10816 /* Set the literal symbol and add a fixup. */
10817 lit_sym
= lit_frag
->fr_symbol
;
10821 if (align_targets
&& !is_loop
)
10823 fragS
*unreach
= fragP
->fr_next
;
10824 while (!(unreach
->fr_type
== rs_machine_dependent
10825 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
10826 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
10828 unreach
= unreach
->fr_next
;
10831 gas_assert (unreach
->fr_type
== rs_machine_dependent
10832 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
10833 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
10835 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
10837 gas_assert (gen_label
== NULL
);
10838 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
, fragP
,
10839 fr_opcode
- fragP
->fr_literal
10844 if (first
&& from_wide_insn
)
10846 target_offset
+= xtensa_format_length (isa
, fmt
);
10848 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
10849 target_offset
+= xg_get_single_size (tinsn
->opcode
);
10852 target_offset
+= xg_get_single_size (tinsn
->opcode
);
10859 for (i
= 0; i
< istack
.ninsn
; i
++)
10861 TInsn
*tinsn
= &istack
.insn
[i
];
10865 bfd_reloc_code_real_type reloc_type
;
10867 switch (tinsn
->insn_type
)
10869 case ITYPE_LITERAL
:
10870 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
10871 /* Already checked. */
10872 gas_assert (lit_frag
!= NULL
);
10873 gas_assert (lit_sym
!= NULL
);
10874 gas_assert (tinsn
->ntok
== 1);
10876 target_seg
= S_GET_SEGMENT (lit_sym
);
10877 gas_assert (target_seg
);
10878 reloc_type
= map_operator_to_reloc (tinsn
->tok
[0].X_op
, TRUE
);
10879 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
10880 &tinsn
->tok
[0], FALSE
, reloc_type
);
10887 xg_resolve_labels (tinsn
, gen_label
);
10888 xg_resolve_literals (tinsn
, lit_sym
);
10889 if (from_wide_insn
&& first
)
10892 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
10894 cur_vinsn
.slots
[slot
] = *tinsn
;
10898 cur_vinsn
.slots
[slot
].opcode
=
10899 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
10900 cur_vinsn
.slots
[slot
].ntok
= 0;
10902 vinsn_to_insnbuf (&cur_vinsn
, immed_instr
, fragP
, TRUE
);
10903 xtensa_insnbuf_to_chars (isa
, cur_vinsn
.insnbuf
,
10904 (unsigned char *) immed_instr
, 0);
10905 fragP
->tc_frag_data
.is_insn
= TRUE
;
10906 size
= xtensa_format_length (isa
, fmt
);
10907 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
10909 xg_emit_insn_to_buf
10910 (tinsn
, immed_instr
+ size
, fragP
,
10911 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
10912 size
+= xg_get_single_size (tinsn
->opcode
);
10917 size
= xg_get_single_size (tinsn
->opcode
);
10918 xg_emit_insn_to_buf (tinsn
, immed_instr
, fragP
,
10919 immed_instr
- fragP
->fr_literal
, TRUE
);
10921 immed_instr
+= size
;
10922 total_size
+= size
;
10927 diff
= total_size
- old_size
;
10928 gas_assert (diff
>= 0);
10931 gas_assert (diff
<= fragP
->fr_var
);
10932 fragP
->fr_var
-= diff
;
10933 fragP
->fr_fix
+= diff
;
10936 /* Check for undefined immediates in LOOP instructions. */
10940 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
10941 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
10943 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
10946 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
10947 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
10949 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
10954 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
10956 /* Add an expansion note on the expanded instruction. */
10957 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
10958 &orig_tinsn
.tok
[0], TRUE
,
10959 BFD_RELOC_XTENSA_ASM_EXPAND
);
10964 /* Add a new fix expression into the desired segment. We have to
10965 switch to that segment to do this. */
10968 fix_new_exp_in_seg (segT new_seg
,
10969 subsegT new_subseg
,
10975 bfd_reloc_code_real_type r_type
)
10978 segT seg
= now_seg
;
10979 subsegT subseg
= now_subseg
;
10981 gas_assert (new_seg
!= 0);
10982 subseg_set (new_seg
, new_subseg
);
10984 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
10985 subseg_set (seg
, subseg
);
10991 /* A map that keeps information on a per-subsegment basis. This is
10992 maintained during initial assembly, but is invalid once the
10993 subsegments are smashed together. I.E., it cannot be used during
10996 typedef struct subseg_map_struct
11004 float total_freq
; /* fall-through + branch target frequency */
11005 float target_freq
; /* branch target frequency alone */
11007 struct subseg_map_struct
*next
;
11011 static subseg_map
*sseg_map
= NULL
;
11013 static subseg_map
*
11014 get_subseg_info (segT seg
, subsegT subseg
)
11016 subseg_map
*subseg_e
;
11018 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
11020 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
11027 static subseg_map
*
11028 add_subseg_info (segT seg
, subsegT subseg
)
11030 subseg_map
*subseg_e
= XNEW (subseg_map
);
11031 memset (subseg_e
, 0, sizeof (subseg_map
));
11032 subseg_e
->seg
= seg
;
11033 subseg_e
->subseg
= subseg
;
11034 subseg_e
->flags
= 0;
11035 /* Start off considering every branch target very important. */
11036 subseg_e
->target_freq
= 1.0;
11037 subseg_e
->total_freq
= 1.0;
11038 subseg_e
->next
= sseg_map
;
11039 sseg_map
= subseg_e
;
11045 get_last_insn_flags (segT seg
, subsegT subseg
)
11047 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
11049 return subseg_e
->flags
;
11055 set_last_insn_flags (segT seg
,
11060 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
11062 subseg_e
= add_subseg_info (seg
, subseg
);
11064 subseg_e
->flags
|= fl
;
11066 subseg_e
->flags
&= ~fl
;
11071 get_subseg_total_freq (segT seg
, subsegT subseg
)
11073 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
11075 return subseg_e
->total_freq
;
11081 get_subseg_target_freq (segT seg
, subsegT subseg
)
11083 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
11085 return subseg_e
->target_freq
;
11091 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
11093 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
11095 subseg_e
= add_subseg_info (seg
, subseg
);
11096 subseg_e
->total_freq
= total_f
;
11097 subseg_e
->target_freq
= target_f
;
11101 /* Segment Lists and emit_state Stuff. */
11104 xtensa_move_seg_list_to_beginning (seg_list
*head
)
11109 segT literal_section
= head
->seg
;
11111 /* Move the literal section to the front of the section list. */
11112 gas_assert (literal_section
);
11113 if (literal_section
!= stdoutput
->sections
)
11115 bfd_section_list_remove (stdoutput
, literal_section
);
11116 bfd_section_list_prepend (stdoutput
, literal_section
);
11123 static void mark_literal_frags (seg_list
*);
11126 xg_promote_candidate_litpool (struct litpool_seg
*lps
,
11127 struct litpool_frag
*lp
)
11132 char label
[10 + 2 * sizeof (fragS
*)];
11134 poolbeg
= lp
->fragP
;
11136 poolbeg
->fr_subtype
= RELAX_LITERAL_POOL_BEGIN
;
11137 poolend
= poolbeg
->fr_next
;
11138 gas_assert (poolend
->fr_type
== rs_machine_dependent
&&
11139 poolend
->fr_subtype
== RELAX_LITERAL_POOL_END
);
11140 /* Create a local symbol pointing to the
11141 end of the pool. */
11142 sprintf (label
, ".L0_LT_%p", poolbeg
);
11143 lsym
= (symbolS
*) local_symbol_make (label
, lps
->seg
, poolend
, 0);
11144 poolbeg
->fr_symbol
= lsym
;
11145 /* Rest is done in xtensa_relax_frag. */
11148 static struct litpool_frag
*xg_find_litpool (struct litpool_seg
*lps
,
11149 struct litpool_frag
*lpf
,
11152 struct litpool_frag
*lp
= lpf
->prev
;
11154 gas_assert (lp
->fragP
);
11156 while (lp
->fragP
->fr_subtype
== RELAX_LITERAL_POOL_CANDIDATE_BEGIN
)
11159 if (lp
->fragP
== NULL
)
11161 /* End of list; have to bite the bullet.
11162 Take the nearest. */
11166 /* Does it (conservatively) reach? */
11167 if (addr
- lp
->addr
<= 128 * 1024)
11169 if (lp
->fragP
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
&&
11170 lp
->literal_count
< MAX_POOL_LITERALS
)
11172 /* Found a good one. */
11175 else if (lp
->prev
->fragP
&&
11176 addr
- lp
->prev
->addr
> 128 * 1024 &&
11177 lp
->prev
->literal_count
< MAX_POOL_LITERALS
)
11179 /* This is still a "candidate" but the next one
11180 will be too far away, so revert to the nearest
11181 one, convert it and add the jump around. */
11188 if (lp
->literal_count
>= MAX_POOL_LITERALS
)
11191 while (lp
&& lp
->fragP
&& lp
->literal_count
>= MAX_POOL_LITERALS
)
11198 gas_assert (lp
&& lp
->fragP
&& lp
->literal_count
< MAX_POOL_LITERALS
);
11199 ++lp
->literal_count
;
11201 /* Convert candidate and add the jump around. */
11202 if (lp
->fragP
->fr_subtype
== RELAX_LITERAL_POOL_CANDIDATE_BEGIN
)
11203 xg_promote_candidate_litpool (lps
, lp
);
11208 static bfd_boolean
xtensa_is_init_fini (segT seg
)
11212 return strcmp (segment_name (seg
), INIT_SECTION_NAME
) == 0
11213 || strcmp (segment_name (seg
), FINI_SECTION_NAME
) == 0;
11217 xtensa_assign_litpool_addresses (void)
11219 struct litpool_seg
*lps
;
11221 for (lps
= litpool_seg_list
.next
; lps
; lps
= lps
->next
)
11223 frchainS
*frchP
= seg_info (lps
->seg
)->frchainP
;
11224 struct litpool_frag
*lpf
= lps
->frag_list
.next
;
11227 if (xtensa_is_init_fini (lps
->seg
))
11230 for ( ; frchP
; frchP
= frchP
->frch_next
)
11233 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
11235 if (lpf
&& fragP
== lpf
->fragP
)
11237 gas_assert(fragP
->fr_type
== rs_machine_dependent
&&
11238 (fragP
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
||
11239 fragP
->fr_subtype
== RELAX_LITERAL_POOL_CANDIDATE_BEGIN
));
11240 /* Found a litpool location. */
11244 if (fragP
->fr_type
== rs_machine_dependent
&&
11245 fragP
->fr_subtype
== RELAX_SLOTS
)
11248 for (slot
= 0; slot
< MAX_SLOTS
; slot
++)
11250 fragS
*litfrag
= fragP
->tc_frag_data
.literal_frags
[slot
];
11253 && litfrag
->tc_frag_data
.is_literal
11254 && !litfrag
->tc_frag_data
.literal_frag
)
11256 /* L32R referring .literal or generated as a result
11257 of relaxation. Point its literal to the nearest
11258 litpool preferring non-"candidate" positions to
11259 avoid the jump-around. */
11261 struct litpool_frag
*lp
;
11263 lp
= xg_find_litpool (lps
, lpf
, addr
);
11264 /* Take earliest use of this literal to avoid
11266 litfrag
->tc_frag_data
.literal_frag
= lp
->fragP
;
11270 addr
+= fragP
->fr_fix
;
11271 if (fragP
->fr_type
== rs_fill
)
11272 addr
+= fragP
->fr_offset
;
11279 xtensa_move_literals (void)
11282 frchainS
*frchain_from
, *frchain_to
;
11283 fragS
*search_frag
, *next_frag
, *literal_pool
, *insert_after
;
11284 fragS
**frag_splice
;
11287 fixS
*fix
, *next_fix
, **fix_splice
;
11289 const char *init_name
= INIT_SECTION_NAME
;
11290 const char *fini_name
= FINI_SECTION_NAME
;
11291 int init_name_len
= strlen(init_name
);
11292 int fini_name_len
= strlen(fini_name
);
11294 mark_literal_frags (literal_head
->next
);
11296 if (use_literal_section
)
11299 /* Assign addresses (rough estimates) to the potential literal pool locations
11300 and create new ones if the gaps are too large. */
11302 xtensa_assign_litpool_addresses ();
11304 /* Walk through the literal segments. */
11305 for (segment
= literal_head
->next
; segment
; segment
= segment
->next
)
11307 const char *seg_name
= segment_name (segment
->seg
);
11309 /* Keep the literals for .init and .fini in separate sections. */
11310 if ((!memcmp (seg_name
, init_name
, init_name_len
) &&
11311 !strcmp (seg_name
+ init_name_len
, ".literal")) ||
11312 (!memcmp (seg_name
, fini_name
, fini_name_len
) &&
11313 !strcmp (seg_name
+ fini_name_len
, ".literal")))
11316 frchain_from
= seg_info (segment
->seg
)->frchainP
;
11317 search_frag
= frchain_from
->frch_root
;
11318 literal_pool
= NULL
;
11320 frag_splice
= &(frchain_from
->frch_root
);
11322 while (search_frag
&& !search_frag
->tc_frag_data
.literal_frag
)
11324 gas_assert (search_frag
->fr_fix
== 0
11325 || search_frag
->fr_type
== rs_align
);
11326 search_frag
= search_frag
->fr_next
;
11332 gas_assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
11333 == RELAX_LITERAL_POOL_BEGIN
);
11334 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
11336 /* Make sure that all the frags in this series are closed, and
11337 that there is at least one left over of zero-size. This
11338 prevents us from making a segment with an frchain without any
11340 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
11341 xtensa_set_frag_assembly_state (frag_now
);
11342 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
11343 xtensa_set_frag_assembly_state (frag_now
);
11345 while (search_frag
!= frag_now
)
11347 next_frag
= search_frag
->fr_next
;
11348 if (search_frag
->tc_frag_data
.literal_frag
)
11350 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
11351 gas_assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
11352 frchain_to
= literal_pool
->tc_frag_data
.lit_frchain
;
11353 gas_assert (frchain_to
);
11356 if (search_frag
->fr_type
== rs_fill
&& search_frag
->fr_fix
== 0)
11358 /* Skip empty fill frags. */
11359 *frag_splice
= next_frag
;
11360 search_frag
= next_frag
;
11364 if (search_frag
->fr_type
== rs_align
)
11366 /* Skip alignment frags, because the pool as a whole will be
11367 aligned if used, and we don't want to force alignment if the
11369 *frag_splice
= next_frag
;
11370 search_frag
= next_frag
;
11374 /* First, move the frag out of the literal section and
11375 to the appropriate place. */
11377 /* Insert an alignment frag at start of pool. */
11378 if (literal_pool
->fr_next
->fr_type
== rs_machine_dependent
&&
11379 literal_pool
->fr_next
->fr_subtype
== RELAX_LITERAL_POOL_END
)
11381 segT pool_seg
= literal_pool
->fr_next
->tc_frag_data
.lit_seg
;
11382 emit_state prev_state
;
11385 xtensa_switch_section_emit_state (&prev_state
, pool_seg
, 0);
11386 prev_frag
= frag_now
;
11387 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
11388 align_frag
= frag_now
;
11389 frag_align (2, 0, 0);
11390 /* Splice it into the right place. */
11391 prev_frag
->fr_next
= align_frag
->fr_next
;
11392 align_frag
->fr_next
= literal_pool
->fr_next
;
11393 literal_pool
->fr_next
= align_frag
;
11394 /* Insert after this one. */
11395 literal_pool
->tc_frag_data
.literal_frag
= align_frag
;
11396 xtensa_restore_emit_state (&prev_state
);
11398 insert_after
= literal_pool
->tc_frag_data
.literal_frag
;
11399 dest_seg
= insert_after
->fr_next
->tc_frag_data
.lit_seg
;
11400 /* Skip align frag. */
11401 if (insert_after
->fr_next
->fr_type
== rs_align
)
11403 insert_after
= insert_after
->fr_next
;
11406 *frag_splice
= next_frag
;
11407 search_frag
->fr_next
= insert_after
->fr_next
;
11408 insert_after
->fr_next
= search_frag
;
11409 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
11410 literal_pool
->tc_frag_data
.literal_frag
= search_frag
;
11412 /* Now move any fixups associated with this frag to the
11414 fix
= frchain_from
->fix_root
;
11415 fix_splice
= &(frchain_from
->fix_root
);
11418 next_fix
= fix
->fx_next
;
11419 if (fix
->fx_frag
== search_frag
)
11421 *fix_splice
= next_fix
;
11422 fix
->fx_next
= frchain_to
->fix_root
;
11423 frchain_to
->fix_root
= fix
;
11424 if (frchain_to
->fix_tail
== NULL
)
11425 frchain_to
->fix_tail
= fix
;
11428 fix_splice
= &(fix
->fx_next
);
11431 search_frag
= next_frag
;
11434 if (frchain_from
->fix_root
!= NULL
)
11436 frchain_from
= seg_info (segment
->seg
)->frchainP
;
11437 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
11439 gas_assert (frchain_from
->fix_root
== NULL
);
11441 frchain_from
->fix_tail
= NULL
;
11442 xtensa_restore_emit_state (&state
);
11445 /* Now fix up the SEGMENT value for all the literal symbols. */
11446 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
11448 symbolS
*lit_sym
= lit
->sym
;
11449 segT dseg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
11451 S_SET_SEGMENT (lit_sym
, dseg
);
11456 /* Walk over all the frags for segments in a list and mark them as
11457 containing literals. As clunky as this is, we can't rely on frag_var
11458 and frag_variant to get called in all situations. */
11461 mark_literal_frags (seg_list
*segment
)
11463 frchainS
*frchain_from
;
11464 fragS
*search_frag
;
11468 frchain_from
= seg_info (segment
->seg
)->frchainP
;
11469 search_frag
= frchain_from
->frch_root
;
11470 while (search_frag
)
11472 search_frag
->tc_frag_data
.is_literal
= TRUE
;
11473 search_frag
= search_frag
->fr_next
;
11475 segment
= segment
->next
;
11481 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
11483 /* Move all of the sections in the section list to come
11484 after "after" in the gnu segment list. */
11489 segT literal_section
= head
->seg
;
11491 /* Move the literal section after "after". */
11492 gas_assert (literal_section
);
11493 if (literal_section
!= after
)
11495 bfd_section_list_remove (stdoutput
, literal_section
);
11496 bfd_section_list_insert_after (stdoutput
, after
, literal_section
);
11504 /* Push all the literal segments to the end of the gnu list. */
11507 xtensa_reorder_segments (void)
11514 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
11520 /* Now that we have the last section, push all the literal
11521 sections to the end. */
11522 xtensa_reorder_seg_list (literal_head
, last_sec
);
11524 /* Now perform the final error check. */
11525 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
11527 gas_assert (new_count
== old_count
);
11531 /* Change the emit state (seg, subseg, and frag related stuff) to the
11532 correct location. Return a emit_state which can be passed to
11533 xtensa_restore_emit_state to return to current fragment. */
11536 xtensa_switch_to_literal_fragment (emit_state
*result
)
11538 if (directive_state
[directive_absolute_literals
])
11540 segT lit4_seg
= cache_literal_section (TRUE
);
11541 xtensa_switch_section_emit_state (result
, lit4_seg
, 0);
11544 xtensa_switch_to_non_abs_literal_fragment (result
);
11546 /* Do a 4-byte align here. */
11547 frag_align (2, 0, 0);
11548 record_alignment (now_seg
, 2);
11553 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
11555 fragS
*pool_location
= get_literal_pool_location (now_seg
);
11557 bfd_boolean is_init_fini
= xtensa_is_init_fini (now_seg
);
11559 if (pool_location
== NULL
11560 && !use_literal_section
11563 if (!auto_litpools
)
11565 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
11567 xtensa_maybe_create_literal_pool_frag (TRUE
, TRUE
);
11568 pool_location
= get_literal_pool_location (now_seg
);
11571 lit_seg
= cache_literal_section (FALSE
);
11572 xtensa_switch_section_emit_state (result
, lit_seg
, 0);
11574 if (!use_literal_section
11576 && get_literal_pool_location (now_seg
) != pool_location
)
11578 /* Close whatever frag is there. */
11579 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
11580 xtensa_set_frag_assembly_state (frag_now
);
11581 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
11582 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
11583 xtensa_set_frag_assembly_state (frag_now
);
11588 /* Call this function before emitting data into the literal section.
11589 This is a helper function for xtensa_switch_to_literal_fragment.
11590 This is similar to a .section new_now_seg subseg. */
11593 xtensa_switch_section_emit_state (emit_state
*state
,
11595 subsegT new_now_subseg
)
11597 state
->name
= now_seg
->name
;
11598 state
->now_seg
= now_seg
;
11599 state
->now_subseg
= now_subseg
;
11600 state
->generating_literals
= generating_literals
;
11601 generating_literals
++;
11602 subseg_set (new_now_seg
, new_now_subseg
);
11606 /* Use to restore the emitting into the normal place. */
11609 xtensa_restore_emit_state (emit_state
*state
)
11611 generating_literals
= state
->generating_literals
;
11612 subseg_set (state
->now_seg
, state
->now_subseg
);
11616 /* Predicate function used to look up a section in a particular group. */
11619 match_section_group (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
, void *inf
)
11621 const char *gname
= inf
;
11622 const char *group_name
= elf_group_name (sec
);
11624 return (group_name
== gname
11625 || (group_name
!= NULL
11627 && strcmp (group_name
, gname
) == 0));
11631 /* Get the literal section to be used for the current text section.
11632 The result may be cached in the default_lit_sections structure. */
11635 cache_literal_section (bfd_boolean use_abs_literals
)
11637 const char *text_name
, *group_name
= 0;
11638 const char *base_name
, *suffix
;
11641 segT seg
, current_section
;
11642 int current_subsec
;
11643 bfd_boolean linkonce
= FALSE
;
11645 /* Save the current section/subsection. */
11646 current_section
= now_seg
;
11647 current_subsec
= now_subseg
;
11649 /* Clear the cached values if they are no longer valid. */
11650 if (now_seg
!= default_lit_sections
.current_text_seg
)
11652 default_lit_sections
.current_text_seg
= now_seg
;
11653 default_lit_sections
.lit_seg
= NULL
;
11654 default_lit_sections
.lit4_seg
= NULL
;
11657 /* Check if the literal section is already cached. */
11658 if (use_abs_literals
)
11659 pcached
= &default_lit_sections
.lit4_seg
;
11661 pcached
= &default_lit_sections
.lit_seg
;
11666 text_name
= default_lit_sections
.lit_prefix
;
11667 if (! text_name
|| ! *text_name
)
11669 text_name
= segment_name (current_section
);
11670 group_name
= elf_group_name (current_section
);
11671 linkonce
= (current_section
->flags
& SEC_LINK_ONCE
) != 0;
11674 base_name
= use_abs_literals
? ".lit4" : ".literal";
11677 name
= concat (base_name
, ".", group_name
, (char *) NULL
);
11679 else if (strncmp (text_name
, ".gnu.linkonce.", linkonce_len
) == 0)
11681 suffix
= strchr (text_name
+ linkonce_len
, '.');
11683 name
= concat (".gnu.linkonce", base_name
, suffix
? suffix
: "",
11689 /* If the section name begins or ends with ".text", then replace
11690 that portion instead of appending an additional suffix. */
11691 size_t len
= strlen (text_name
);
11693 && (strcmp (text_name
+ len
- 5, ".text") == 0
11694 || strncmp (text_name
, ".text", 5) == 0))
11697 name
= XNEWVEC (char, len
+ strlen (base_name
) + 1);
11698 if (strncmp (text_name
, ".text", 5) == 0)
11700 strcpy (name
, base_name
);
11701 strcat (name
, text_name
+ 5);
11705 strcpy (name
, text_name
);
11706 strcpy (name
+ len
, base_name
);
11710 /* Canonicalize section names to allow renaming literal sections.
11711 The group name, if any, came from the current text section and
11712 has already been canonicalized. */
11713 name
= tc_canonicalize_symbol_name (name
);
11715 seg
= bfd_get_section_by_name_if (stdoutput
, name
, match_section_group
,
11716 (void *) group_name
);
11721 seg
= subseg_force_new (name
, 0);
11723 if (! use_abs_literals
)
11725 /* Add the newly created literal segment to the list. */
11726 seg_list
*n
= XNEW (seg_list
);
11728 n
->next
= literal_head
->next
;
11729 literal_head
->next
= n
;
11732 flags
= (SEC_HAS_CONTENTS
| SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
11733 | (linkonce
? (SEC_LINK_ONCE
| SEC_LINK_DUPLICATES_DISCARD
) : 0)
11734 | (use_abs_literals
? SEC_DATA
: SEC_CODE
));
11736 elf_group_name (seg
) = group_name
;
11738 bfd_set_section_flags (seg
, flags
);
11739 bfd_set_section_alignment (seg
, 2);
11743 subseg_set (current_section
, current_subsec
);
11748 /* Property Tables Stuff. */
11750 #define XTENSA_INSN_SEC_NAME ".xt.insn"
11751 #define XTENSA_LIT_SEC_NAME ".xt.lit"
11752 #define XTENSA_PROP_SEC_NAME ".xt.prop"
11754 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
11755 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
11757 static bfd_boolean
get_frag_is_literal (const fragS
*);
11758 static void xtensa_create_property_segments
11759 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
11760 static void xtensa_create_xproperty_segments
11761 (frag_flags_fn
, const char *, xt_section_type
);
11762 static bfd_boolean
exclude_section_from_property_tables (segT
);
11763 static bfd_boolean
section_has_property (segT
, frag_predicate
);
11764 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
11765 static void add_xt_block_frags
11766 (segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
11767 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
11768 static void xtensa_frag_flags_init (frag_flags
*);
11769 static void get_frag_property_flags (const fragS
*, frag_flags
*);
11770 static flagword
frag_flags_to_number (const frag_flags
*);
11771 static void add_xt_prop_frags (segT
, xtensa_block_info
**, frag_flags_fn
);
11773 /* Set up property tables after relaxation. */
11776 xtensa_post_relax_hook (void)
11778 xtensa_move_seg_list_to_beginning (literal_head
);
11780 xtensa_find_unmarked_state_frags ();
11781 xtensa_mark_frags_for_org ();
11782 xtensa_mark_difference_of_two_symbols ();
11784 xtensa_create_property_segments (get_frag_is_literal
,
11786 XTENSA_LIT_SEC_NAME
,
11788 xtensa_create_xproperty_segments (get_frag_property_flags
,
11789 XTENSA_PROP_SEC_NAME
,
11792 if (warn_unaligned_branch_targets
)
11793 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
11794 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
11798 /* This function is only meaningful after xtensa_move_literals. */
11801 get_frag_is_literal (const fragS
*fragP
)
11803 gas_assert (fragP
!= NULL
);
11804 return fragP
->tc_frag_data
.is_literal
;
11809 xtensa_create_property_segments (frag_predicate property_function
,
11810 frag_predicate end_property_function
,
11811 const char *section_name_base
,
11812 xt_section_type sec_type
)
11816 /* Walk over all of the current segments.
11817 Walk over each fragment
11818 For each non-empty fragment,
11819 Build a property record (append where possible). */
11821 for (seclist
= &stdoutput
->sections
;
11822 seclist
&& *seclist
;
11823 seclist
= &(*seclist
)->next
)
11825 segT sec
= *seclist
;
11827 if (exclude_section_from_property_tables (sec
))
11830 if (section_has_property (sec
, property_function
))
11832 segment_info_type
*xt_seg_info
;
11833 xtensa_block_info
**xt_blocks
;
11834 segT prop_sec
= xtensa_make_property_section (sec
, section_name_base
);
11836 prop_sec
->output_section
= prop_sec
;
11837 subseg_set (prop_sec
, 0);
11838 xt_seg_info
= seg_info (prop_sec
);
11839 xt_blocks
= &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
11841 /* Walk over all of the frchains here and add new sections. */
11842 add_xt_block_frags (sec
, xt_blocks
, property_function
,
11843 end_property_function
);
11847 /* Now we fill them out.... */
11849 for (seclist
= &stdoutput
->sections
;
11850 seclist
&& *seclist
;
11851 seclist
= &(*seclist
)->next
)
11853 segment_info_type
*seginfo
;
11854 xtensa_block_info
*block
;
11855 segT sec
= *seclist
;
11857 seginfo
= seg_info (sec
);
11858 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
11862 xtensa_block_info
*cur_block
;
11864 bfd_size_type rec_size
;
11866 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
11869 rec_size
= num_recs
* 8;
11870 bfd_set_section_size (sec
, rec_size
);
11877 subseg_set (sec
, 0);
11878 frag_data
= frag_more (rec_size
);
11880 for (i
= 0; i
< num_recs
; i
++)
11884 /* Write the fixup. */
11885 gas_assert (cur_block
);
11886 fix
= fix_new (frag_now
, i
* 8, 4,
11887 section_symbol (cur_block
->sec
),
11889 FALSE
, BFD_RELOC_32
);
11890 fix
->fx_file
= "<internal>";
11893 /* Write the length. */
11894 md_number_to_chars (&frag_data
[4 + i
* 8],
11895 cur_block
->size
, 4);
11896 cur_block
= cur_block
->next
;
11898 frag_wane (frag_now
);
11900 frag_wane (frag_now
);
11908 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
11909 const char *section_name_base
,
11910 xt_section_type sec_type
)
11914 /* Walk over all of the current segments.
11915 Walk over each fragment.
11916 For each fragment that has instructions,
11917 build an instruction record (append where possible). */
11919 for (seclist
= &stdoutput
->sections
;
11920 seclist
&& *seclist
;
11921 seclist
= &(*seclist
)->next
)
11923 segT sec
= *seclist
;
11925 if (exclude_section_from_property_tables (sec
))
11928 if (section_has_xproperty (sec
, flag_fn
))
11930 segment_info_type
*xt_seg_info
;
11931 xtensa_block_info
**xt_blocks
;
11932 segT prop_sec
= xtensa_make_property_section (sec
, section_name_base
);
11934 prop_sec
->output_section
= prop_sec
;
11935 subseg_set (prop_sec
, 0);
11936 xt_seg_info
= seg_info (prop_sec
);
11937 xt_blocks
= &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
11939 /* Walk over all of the frchains here and add new sections. */
11940 add_xt_prop_frags (sec
, xt_blocks
, flag_fn
);
11944 /* Now we fill them out.... */
11946 for (seclist
= &stdoutput
->sections
;
11947 seclist
&& *seclist
;
11948 seclist
= &(*seclist
)->next
)
11950 segment_info_type
*seginfo
;
11951 xtensa_block_info
*block
;
11952 segT sec
= *seclist
;
11954 seginfo
= seg_info (sec
);
11955 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
11959 xtensa_block_info
*cur_block
;
11961 bfd_size_type rec_size
;
11963 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
11966 rec_size
= num_recs
* (8 + 4);
11967 bfd_set_section_size (sec
, rec_size
);
11968 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
11975 subseg_set (sec
, 0);
11976 frag_data
= frag_more (rec_size
);
11978 for (i
= 0; i
< num_recs
; i
++)
11982 /* Write the fixup. */
11983 gas_assert (cur_block
);
11984 fix
= fix_new (frag_now
, i
* 12, 4,
11985 section_symbol (cur_block
->sec
),
11987 FALSE
, BFD_RELOC_32
);
11988 fix
->fx_file
= "<internal>";
11991 /* Write the length. */
11992 md_number_to_chars (&frag_data
[4 + i
* 12],
11993 cur_block
->size
, 4);
11994 md_number_to_chars (&frag_data
[8 + i
* 12],
11995 frag_flags_to_number (&cur_block
->flags
),
11996 sizeof (flagword
));
11997 cur_block
= cur_block
->next
;
11999 frag_wane (frag_now
);
12001 frag_wane (frag_now
);
12009 exclude_section_from_property_tables (segT sec
)
12011 flagword flags
= bfd_section_flags (sec
);
12013 /* Sections that don't contribute to the memory footprint are excluded. */
12014 if ((flags
& SEC_DEBUGGING
)
12015 || !(flags
& SEC_ALLOC
)
12016 || (flags
& SEC_MERGE
))
12019 /* Linker cie and fde optimizations mess up property entries for
12020 eh_frame sections, but there is nothing inside them relevant to
12021 property tables anyway. */
12022 if (strcmp (sec
->name
, ".eh_frame") == 0)
12030 section_has_property (segT sec
, frag_predicate property_function
)
12032 segment_info_type
*seginfo
= seg_info (sec
);
12035 if (seginfo
&& seginfo
->frchainP
)
12037 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
12039 if (property_function (fragP
)
12040 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
12049 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
12051 segment_info_type
*seginfo
= seg_info (sec
);
12054 if (seginfo
&& seginfo
->frchainP
)
12056 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
12058 frag_flags prop_flags
;
12059 property_function (fragP
, &prop_flags
);
12060 if (!xtensa_frag_flags_is_empty (&prop_flags
))
12068 /* Two types of block sections exist right now: literal and insns. */
12071 add_xt_block_frags (segT sec
,
12072 xtensa_block_info
**xt_block
,
12073 frag_predicate property_function
,
12074 frag_predicate end_property_function
)
12078 /* Build it if needed. */
12079 while (*xt_block
!= NULL
)
12080 xt_block
= &(*xt_block
)->next
;
12081 /* We are either at NULL at the beginning or at the end. */
12083 /* Walk through the frags. */
12084 if (seg_info (sec
)->frchainP
)
12086 for (fragP
= seg_info (sec
)->frchainP
->frch_root
;
12088 fragP
= fragP
->fr_next
)
12090 if (property_function (fragP
)
12091 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
12093 if (*xt_block
!= NULL
)
12095 if ((*xt_block
)->offset
+ (*xt_block
)->size
12096 == fragP
->fr_address
)
12097 (*xt_block
)->size
+= fragP
->fr_fix
;
12099 xt_block
= &((*xt_block
)->next
);
12101 if (*xt_block
== NULL
)
12103 xtensa_block_info
*new_block
= XNEW (xtensa_block_info
);
12104 new_block
->sec
= sec
;
12105 new_block
->offset
= fragP
->fr_address
;
12106 new_block
->size
= fragP
->fr_fix
;
12107 new_block
->next
= NULL
;
12108 xtensa_frag_flags_init (&new_block
->flags
);
12109 *xt_block
= new_block
;
12111 if (end_property_function
12112 && end_property_function (fragP
))
12114 xt_block
= &((*xt_block
)->next
);
12122 /* Break the encapsulation of add_xt_prop_frags here. */
12125 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
12127 if (prop_flags
->is_literal
12128 || prop_flags
->is_insn
12129 || prop_flags
->is_data
12130 || prop_flags
->is_unreachable
)
12137 xtensa_frag_flags_init (frag_flags
*prop_flags
)
12139 memset (prop_flags
, 0, sizeof (frag_flags
));
12144 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
12146 xtensa_frag_flags_init (prop_flags
);
12147 if (fragP
->tc_frag_data
.is_literal
)
12148 prop_flags
->is_literal
= TRUE
;
12149 if (fragP
->tc_frag_data
.is_specific_opcode
12150 || fragP
->tc_frag_data
.is_no_transform
)
12152 prop_flags
->is_no_transform
= TRUE
;
12153 if (xtensa_frag_flags_is_empty (prop_flags
))
12154 prop_flags
->is_data
= TRUE
;
12156 if (fragP
->tc_frag_data
.is_unreachable
)
12157 prop_flags
->is_unreachable
= TRUE
;
12158 else if (fragP
->tc_frag_data
.is_insn
)
12160 prop_flags
->is_insn
= TRUE
;
12161 if (fragP
->tc_frag_data
.is_loop_target
)
12162 prop_flags
->insn
.is_loop_target
= TRUE
;
12163 if (fragP
->tc_frag_data
.is_branch_target
)
12164 prop_flags
->insn
.is_branch_target
= TRUE
;
12165 if (fragP
->tc_frag_data
.is_no_density
)
12166 prop_flags
->insn
.is_no_density
= TRUE
;
12167 if (fragP
->tc_frag_data
.use_absolute_literals
)
12168 prop_flags
->insn
.is_abslit
= TRUE
;
12170 if (fragP
->tc_frag_data
.is_align
)
12172 prop_flags
->is_align
= TRUE
;
12173 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
12174 if (xtensa_frag_flags_is_empty (prop_flags
))
12175 prop_flags
->is_data
= TRUE
;
12181 frag_flags_to_number (const frag_flags
*prop_flags
)
12184 if (prop_flags
->is_literal
)
12185 num
|= XTENSA_PROP_LITERAL
;
12186 if (prop_flags
->is_insn
)
12187 num
|= XTENSA_PROP_INSN
;
12188 if (prop_flags
->is_data
)
12189 num
|= XTENSA_PROP_DATA
;
12190 if (prop_flags
->is_unreachable
)
12191 num
|= XTENSA_PROP_UNREACHABLE
;
12192 if (prop_flags
->insn
.is_loop_target
)
12193 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
12194 if (prop_flags
->insn
.is_branch_target
)
12196 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
12197 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
12200 if (prop_flags
->insn
.is_no_density
)
12201 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
12202 if (prop_flags
->is_no_transform
)
12203 num
|= XTENSA_PROP_NO_TRANSFORM
;
12204 if (prop_flags
->insn
.is_no_reorder
)
12205 num
|= XTENSA_PROP_INSN_NO_REORDER
;
12206 if (prop_flags
->insn
.is_abslit
)
12207 num
|= XTENSA_PROP_INSN_ABSLIT
;
12209 if (prop_flags
->is_align
)
12211 num
|= XTENSA_PROP_ALIGN
;
12212 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
12220 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
12221 const frag_flags
*prop_flags_2
)
12223 /* Cannot combine with an end marker. */
12225 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
12227 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
12229 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
12232 if (prop_flags_1
->is_insn
)
12234 /* Properties of the beginning of the frag. */
12235 if (prop_flags_2
->insn
.is_loop_target
)
12237 if (prop_flags_2
->insn
.is_branch_target
)
12239 if (prop_flags_1
->insn
.is_no_density
!=
12240 prop_flags_2
->insn
.is_no_density
)
12242 if (prop_flags_1
->is_no_transform
!=
12243 prop_flags_2
->is_no_transform
)
12245 if (prop_flags_1
->insn
.is_no_reorder
!=
12246 prop_flags_2
->insn
.is_no_reorder
)
12248 if (prop_flags_1
->insn
.is_abslit
!=
12249 prop_flags_2
->insn
.is_abslit
)
12253 if (prop_flags_1
->is_align
)
12261 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
12264 unsigned align_bits
;
12266 if (!xt_block
->flags
.is_align
)
12267 return xt_block
->size
;
12269 end_addr
= xt_block
->offset
+ xt_block
->size
;
12270 align_bits
= xt_block
->flags
.alignment
;
12271 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
12272 return end_addr
- xt_block
->offset
;
12277 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
12278 const xtensa_block_info
*xt_block_2
)
12280 if (xt_block
->sec
!= xt_block_2
->sec
)
12282 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
12283 != xt_block_2
->offset
)
12286 if (xt_block_2
->size
== 0
12287 && (!xt_block_2
->flags
.is_unreachable
12288 || xt_block
->flags
.is_unreachable
))
12290 if (xt_block_2
->flags
.is_align
12291 && xt_block
->flags
.is_align
)
12293 /* Nothing needed. */
12294 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
12299 if (xt_block_2
->flags
.is_align
)
12301 /* Push alignment to previous entry. */
12302 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
12303 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
12308 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
12309 &xt_block_2
->flags
))
12312 xt_block
->size
+= xt_block_2
->size
;
12314 if (xt_block_2
->flags
.is_align
)
12316 xt_block
->flags
.is_align
= TRUE
;
12317 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
12325 add_xt_prop_frags (segT sec
,
12326 xtensa_block_info
**xt_block
,
12327 frag_flags_fn property_function
)
12331 /* Build it if needed. */
12332 while (*xt_block
!= NULL
)
12334 xt_block
= &(*xt_block
)->next
;
12336 /* We are either at NULL at the beginning or at the end. */
12338 /* Walk through the frags. */
12339 if (seg_info (sec
)->frchainP
)
12341 for (fragP
= seg_info (sec
)->frchainP
->frch_root
; fragP
;
12342 fragP
= fragP
->fr_next
)
12344 xtensa_block_info tmp_block
;
12345 tmp_block
.sec
= sec
;
12346 tmp_block
.offset
= fragP
->fr_address
;
12347 tmp_block
.size
= fragP
->fr_fix
;
12348 tmp_block
.next
= NULL
;
12349 property_function (fragP
, &tmp_block
.flags
);
12351 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
12352 /* && fragP->fr_fix != 0) */
12354 if ((*xt_block
) == NULL
12355 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
12357 xtensa_block_info
*new_block
;
12358 if ((*xt_block
) != NULL
)
12359 xt_block
= &(*xt_block
)->next
;
12360 new_block
= XNEW (xtensa_block_info
);
12361 *new_block
= tmp_block
;
12362 *xt_block
= new_block
;
12370 /* op_placement_info_table */
12372 /* op_placement_info makes it easier to determine which
12373 ops can go in which slots. */
12376 init_op_placement_info_table (void)
12378 xtensa_isa isa
= xtensa_default_isa
;
12379 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
12380 xtensa_opcode opcode
;
12383 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
12385 op_placement_table
= XNEWVEC (op_placement_info
, num_opcodes
);
12386 gas_assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
12388 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
12390 op_placement_info
*opi
= &op_placement_table
[opcode
];
12391 /* FIXME: Make tinsn allocation dynamic. */
12392 if (xtensa_opcode_num_operands (isa
, opcode
) > MAX_INSN_ARGS
)
12393 as_fatal (_("too many operands in instruction"));
12394 opi
->narrowest
= XTENSA_UNDEFINED
;
12395 opi
->narrowest_size
= 0x7F;
12396 opi
->narrowest_slot
= 0;
12398 opi
->num_formats
= 0;
12400 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
12402 opi
->slots
[fmt
] = 0;
12403 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
12405 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
12407 int fmt_length
= xtensa_format_length (isa
, fmt
);
12409 set_bit (fmt
, opi
->formats
);
12410 set_bit (slot
, opi
->slots
[fmt
]);
12411 if (fmt_length
< opi
->narrowest_size
12412 || (fmt_length
== opi
->narrowest_size
12413 && (xtensa_format_num_slots (isa
, fmt
)
12414 < xtensa_format_num_slots (isa
,
12417 opi
->narrowest
= fmt
;
12418 opi
->narrowest_size
= fmt_length
;
12419 opi
->narrowest_slot
= slot
;
12424 opi
->num_formats
++;
12427 xtensa_insnbuf_free (isa
, ibuf
);
12432 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
12434 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
12438 /* If the opcode is available in a single slot format, return its size. */
12441 xg_get_single_size (xtensa_opcode opcode
)
12443 return op_placement_table
[opcode
].narrowest_size
;
12447 static xtensa_format
12448 xg_get_single_format (xtensa_opcode opcode
)
12450 return op_placement_table
[opcode
].narrowest
;
12455 xg_get_single_slot (xtensa_opcode opcode
)
12457 return op_placement_table
[opcode
].narrowest_slot
;
12461 /* Instruction Stack Functions (from "xtensa-istack.h"). */
12464 istack_init (IStack
*stack
)
12471 istack_empty (IStack
*stack
)
12473 return (stack
->ninsn
== 0);
12478 istack_full (IStack
*stack
)
12480 return (stack
->ninsn
== MAX_ISTACK
);
12484 /* Return a pointer to the top IStack entry.
12485 It is an error to call this if istack_empty () is TRUE. */
12488 istack_top (IStack
*stack
)
12490 int rec
= stack
->ninsn
- 1;
12491 gas_assert (!istack_empty (stack
));
12492 return &stack
->insn
[rec
];
12496 /* Add a new TInsn to an IStack.
12497 It is an error to call this if istack_full () is TRUE. */
12500 istack_push (IStack
*stack
, TInsn
*insn
)
12502 int rec
= stack
->ninsn
;
12503 gas_assert (!istack_full (stack
));
12504 stack
->insn
[rec
] = *insn
;
12509 /* Clear space for the next TInsn on the IStack and return a pointer
12510 to it. It is an error to call this if istack_full () is TRUE. */
12513 istack_push_space (IStack
*stack
)
12515 int rec
= stack
->ninsn
;
12517 gas_assert (!istack_full (stack
));
12518 insn
= &stack
->insn
[rec
];
12525 /* Remove the last pushed instruction. It is an error to call this if
12526 istack_empty () returns TRUE. */
12529 istack_pop (IStack
*stack
)
12531 int rec
= stack
->ninsn
- 1;
12532 gas_assert (!istack_empty (stack
));
12534 tinsn_init (&stack
->insn
[rec
]);
12538 /* TInsn functions. */
12541 tinsn_init (TInsn
*dst
)
12543 memset (dst
, 0, sizeof (TInsn
));
12547 /* Return TRUE if ANY of the operands in the insn are symbolic. */
12550 tinsn_has_symbolic_operands (const TInsn
*insn
)
12553 int n
= insn
->ntok
;
12555 gas_assert (insn
->insn_type
== ITYPE_INSN
);
12557 for (i
= 0; i
< n
; ++i
)
12559 switch (insn
->tok
[i
].X_op
)
12573 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
12575 xtensa_isa isa
= xtensa_default_isa
;
12577 int n
= insn
->ntok
;
12579 gas_assert (insn
->insn_type
== ITYPE_INSN
);
12581 for (i
= 0; i
< n
; ++i
)
12583 switch (insn
->tok
[i
].X_op
)
12591 /* Errors for these types are caught later. */
12596 /* Symbolic immediates are only allowed on the last immediate
12597 operand. At this time, CONST16 is the only opcode where we
12598 support non-PC-relative relocations. */
12599 if (i
!= get_relaxable_immed (insn
->opcode
)
12600 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
12601 && insn
->opcode
!= xtensa_const16_opcode
))
12603 as_bad (_("invalid symbolic operand"));
12612 /* For assembly code with complex expressions (e.g. subtraction),
12613 we have to build them in the literal pool so that
12614 their results are calculated correctly after relaxation.
12615 The relaxation only handles expressions that
12616 boil down to SYMBOL + OFFSET. */
12619 tinsn_has_complex_operands (const TInsn
*insn
)
12622 int n
= insn
->ntok
;
12623 gas_assert (insn
->insn_type
== ITYPE_INSN
);
12624 for (i
= 0; i
< n
; ++i
)
12626 switch (insn
->tok
[i
].X_op
)
12642 /* Encode a TInsn opcode and its constant operands into slotbuf.
12643 Return TRUE if there is a symbol in the immediate field. This
12644 function assumes that:
12645 1) The number of operands are correct.
12646 2) The insn_type is ITYPE_INSN.
12647 3) The opcode can be encoded in the specified format and slot.
12648 4) Operands are either O_constant or O_symbol, and all constants fit. */
12651 tinsn_to_slotbuf (xtensa_format fmt
,
12654 xtensa_insnbuf slotbuf
)
12656 xtensa_isa isa
= xtensa_default_isa
;
12657 xtensa_opcode opcode
= tinsn
->opcode
;
12658 bfd_boolean has_fixup
= FALSE
;
12659 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
12662 gas_assert (tinsn
->insn_type
== ITYPE_INSN
);
12663 if (noperands
!= tinsn
->ntok
)
12664 as_fatal (_("operand number mismatch"));
12666 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
12668 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
12669 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
12673 for (i
= 0; i
< noperands
; i
++)
12675 expressionS
*exp
= &tinsn
->tok
[i
];
12678 const char *file_name
;
12684 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
12686 /* The register number has already been checked in
12687 expression_maybe_register, so we don't need to check here. */
12688 opnd_value
= exp
->X_add_number
;
12689 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
12690 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
12693 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
12697 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
12699 file_name
= as_where (&line
);
12700 /* It is a constant and we called this function
12701 then we have to try to fit it. */
12702 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
12703 exp
->X_add_number
, file_name
, line
);
12716 /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded
12717 into a multi-slot instruction, fill the other slots with NOPs.
12718 Return TRUE if there is a symbol in the immediate field. See also the
12719 assumptions listed for tinsn_to_slotbuf. */
12722 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
12724 static xtensa_insnbuf slotbuf
= 0;
12725 static vliw_insn vinsn
;
12726 xtensa_isa isa
= xtensa_default_isa
;
12727 bfd_boolean has_fixup
= FALSE
;
12732 slotbuf
= xtensa_insnbuf_alloc (isa
);
12733 xg_init_vinsn (&vinsn
);
12736 xg_clear_vinsn (&vinsn
);
12738 bundle_tinsn (tinsn
, &vinsn
);
12740 xtensa_format_encode (isa
, vinsn
.format
, insnbuf
);
12742 for (i
= 0; i
< vinsn
.num_slots
; i
++)
12744 /* Only one slot may have a fix-up because the rest contains NOPs. */
12746 tinsn_to_slotbuf (vinsn
.format
, i
, &vinsn
.slots
[i
], vinsn
.slotbuf
[i
]);
12747 xtensa_format_set_slot (isa
, vinsn
.format
, i
, insnbuf
, vinsn
.slotbuf
[i
]);
12754 /* Check the instruction arguments. Return TRUE on failure. */
12757 tinsn_check_arguments (const TInsn
*insn
)
12759 xtensa_isa isa
= xtensa_default_isa
;
12760 xtensa_opcode opcode
= insn
->opcode
;
12761 xtensa_regfile t1_regfile
, t2_regfile
;
12762 int t1_reg
, t2_reg
;
12763 int t1_base_reg
, t1_last_reg
;
12764 int t2_base_reg
, t2_last_reg
;
12765 char t1_inout
, t2_inout
;
12768 if (opcode
== XTENSA_UNDEFINED
)
12770 as_bad (_("invalid opcode"));
12774 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
12776 as_bad (_("too few operands"));
12780 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
12782 as_bad (_("too many operands"));
12786 /* Check registers. */
12787 for (j
= 0; j
< insn
->ntok
; j
++)
12789 if (xtensa_operand_is_register (isa
, insn
->opcode
, j
) != 1)
12792 t2_regfile
= xtensa_operand_regfile (isa
, insn
->opcode
, j
);
12793 t2_base_reg
= insn
->tok
[j
].X_add_number
;
12795 = t2_base_reg
+ xtensa_operand_num_regs (isa
, insn
->opcode
, j
);
12797 for (i
= 0; i
< insn
->ntok
; i
++)
12802 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) != 1)
12805 t1_regfile
= xtensa_operand_regfile (isa
, insn
->opcode
, i
);
12807 if (t1_regfile
!= t2_regfile
)
12810 t1_inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
12811 t2_inout
= xtensa_operand_inout (isa
, insn
->opcode
, j
);
12813 t1_base_reg
= insn
->tok
[i
].X_add_number
;
12814 t1_last_reg
= (t1_base_reg
12815 + xtensa_operand_num_regs (isa
, insn
->opcode
, i
));
12817 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
12819 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
12821 if (t1_reg
!= t2_reg
)
12824 if (t1_inout
!= 'i' && t2_inout
!= 'i')
12826 as_bad (_("multiple writes to the same register"));
12837 /* Load an instruction from its encoded form. */
12840 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
12844 xg_init_vinsn (&vinsn
);
12845 vinsn_from_chars (&vinsn
, f
);
12847 *tinsn
= vinsn
.slots
[slot
];
12848 xg_free_vinsn (&vinsn
);
12853 tinsn_from_insnbuf (TInsn
*tinsn
,
12854 xtensa_insnbuf slotbuf
,
12859 xtensa_isa isa
= xtensa_default_isa
;
12861 /* Find the immed. */
12862 tinsn_init (tinsn
);
12863 tinsn
->insn_type
= ITYPE_INSN
;
12864 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
12865 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
12866 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
12867 for (i
= 0; i
< tinsn
->ntok
; i
++)
12869 set_expr_const (&tinsn
->tok
[i
],
12870 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
12871 tinsn
->opcode
, i
));
12876 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
12879 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
12881 xtensa_opcode opcode
= tinsn
->opcode
;
12884 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
12886 opnum
= get_relaxable_immed (opcode
);
12887 gas_assert (opnum
>= 0);
12888 set_expr_symbol_offset (&tinsn
->tok
[opnum
],
12889 fragP
->tc_frag_data
.slot_symbols
[slot
],
12890 fragP
->tc_frag_data
.slot_offsets
[slot
]);
12892 tinsn
->extra_arg
= fragP
->tc_frag_data
.free_reg
[slot
];
12897 get_num_stack_text_bytes (IStack
*istack
)
12900 int text_bytes
= 0;
12902 for (i
= 0; i
< istack
->ninsn
; i
++)
12904 TInsn
*tinsn
= &istack
->insn
[i
];
12905 if (tinsn
->insn_type
== ITYPE_INSN
)
12906 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
12913 get_num_stack_literal_bytes (IStack
*istack
)
12918 for (i
= 0; i
< istack
->ninsn
; i
++)
12920 TInsn
*tinsn
= &istack
->insn
[i
];
12921 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
12928 /* vliw_insn functions. */
12931 xg_init_vinsn (vliw_insn
*v
)
12934 xtensa_isa isa
= xtensa_default_isa
;
12936 xg_clear_vinsn (v
);
12938 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
12939 if (v
->insnbuf
== NULL
)
12940 as_fatal (_("out of memory"));
12942 for (i
= 0; i
< config_max_slots
; i
++)
12944 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
12945 if (v
->slotbuf
[i
] == NULL
)
12946 as_fatal (_("out of memory"));
12952 xg_clear_vinsn (vliw_insn
*v
)
12956 memset (v
, 0, offsetof (vliw_insn
, slots
)
12957 + sizeof(TInsn
) * config_max_slots
);
12959 v
->format
= XTENSA_UNDEFINED
;
12961 v
->inside_bundle
= FALSE
;
12963 if (xt_saved_debug_type
!= DEBUG_NONE
)
12964 debug_type
= xt_saved_debug_type
;
12966 for (i
= 0; i
< config_max_slots
; i
++)
12967 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
12972 xg_copy_vinsn (vliw_insn
*dst
, vliw_insn
*src
)
12975 offsetof(vliw_insn
, slots
) + src
->num_slots
* sizeof(TInsn
));
12976 dst
->insnbuf
= src
->insnbuf
;
12977 memcpy (dst
->slotbuf
, src
->slotbuf
, src
->num_slots
* sizeof(xtensa_insnbuf
));
12982 vinsn_has_specific_opcodes (vliw_insn
*v
)
12986 for (i
= 0; i
< v
->num_slots
; i
++)
12988 if (v
->slots
[i
].is_specific_opcode
)
12996 xg_free_vinsn (vliw_insn
*v
)
12999 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
13000 for (i
= 0; i
< config_max_slots
; i
++)
13001 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
13005 /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic
13006 operands. See also the assumptions listed for tinsn_to_slotbuf. */
13009 vinsn_to_insnbuf (vliw_insn
*vinsn
,
13012 bfd_boolean record_fixup
)
13014 xtensa_isa isa
= xtensa_default_isa
;
13015 xtensa_format fmt
= vinsn
->format
;
13016 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
13018 bfd_boolean has_fixup
= FALSE
;
13020 xtensa_format_encode (isa
, fmt
, insnbuf
);
13022 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
13024 TInsn
*tinsn
= &vinsn
->slots
[slot
];
13025 expressionS
*extra_arg
= &tinsn
->extra_arg
;
13026 bfd_boolean tinsn_has_fixup
=
13027 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
13028 vinsn
->slotbuf
[slot
]);
13030 xtensa_format_set_slot (isa
, fmt
, slot
,
13031 insnbuf
, vinsn
->slotbuf
[slot
]);
13032 if (extra_arg
->X_op
!= O_illegal
&& extra_arg
->X_op
!= O_register
)
13034 if (vinsn
->num_slots
!= 1)
13035 as_bad (_("TLS relocation not allowed in FLIX bundle"));
13036 else if (record_fixup
)
13037 /* Instructions that generate TLS relocations should always be
13038 relaxed in the front-end. If "record_fixup" is set, then this
13039 function is being called during back-end relaxation, so flag
13040 the unexpected behavior as an error. */
13041 as_bad (_("unexpected TLS relocation"));
13043 fix_new (fragP
, frag_offset
- fragP
->fr_literal
,
13044 xtensa_format_length (isa
, fmt
),
13045 extra_arg
->X_add_symbol
, extra_arg
->X_add_number
,
13046 FALSE
, map_operator_to_reloc (extra_arg
->X_op
, FALSE
));
13048 if (tinsn_has_fixup
)
13051 xtensa_opcode opcode
= tinsn
->opcode
;
13052 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
13055 for (i
= 0; i
< noperands
; i
++)
13057 expressionS
* exp
= &tinsn
->tok
[i
];
13063 if (get_relaxable_immed (opcode
) == i
)
13065 /* Add a fix record for the instruction, except if this
13066 function is being called prior to relaxation, i.e.,
13067 if record_fixup is false, and the instruction might
13068 be relaxed later. */
13070 || tinsn
->is_specific_opcode
13071 || !xg_is_relaxable_insn (tinsn
, 0))
13073 xg_add_opcode_fix (tinsn
, i
, fmt
, slot
, exp
, fragP
,
13074 frag_offset
- fragP
->fr_literal
);
13078 if (exp
->X_op
!= O_symbol
)
13079 as_bad (_("invalid operand"));
13080 tinsn
->symbol
= exp
->X_add_symbol
;
13081 tinsn
->offset
= exp
->X_add_number
;
13085 as_bad (_("symbolic operand not allowed"));
13093 as_bad (_("expression too complex"));
13105 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
13107 static xtensa_insnbuf insnbuf
= NULL
;
13108 static xtensa_insnbuf slotbuf
= NULL
;
13111 xtensa_isa isa
= xtensa_default_isa
;
13115 insnbuf
= xtensa_insnbuf_alloc (isa
);
13116 slotbuf
= xtensa_insnbuf_alloc (isa
);
13119 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) f
, 0);
13120 fmt
= xtensa_format_decode (isa
, insnbuf
);
13121 if (fmt
== XTENSA_UNDEFINED
)
13122 as_fatal (_("cannot decode instruction format"));
13123 vinsn
->format
= fmt
;
13124 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
13126 for (i
= 0; i
< vinsn
->num_slots
; i
++)
13128 TInsn
*tinsn
= &vinsn
->slots
[i
];
13129 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
13130 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
13135 /* Expression utilities. */
13137 /* Return TRUE if the expression is an integer constant. */
13140 expr_is_const (const expressionS
*s
)
13142 return (s
->X_op
== O_constant
);
13146 /* Get the expression constant.
13147 Calling this is illegal if expr_is_const () returns TRUE. */
13150 get_expr_const (const expressionS
*s
)
13152 gas_assert (expr_is_const (s
));
13153 return s
->X_add_number
;
13157 /* Set the expression to a constant value. */
13160 set_expr_const (expressionS
*s
, offsetT val
)
13162 s
->X_op
= O_constant
;
13163 s
->X_add_number
= val
;
13164 s
->X_add_symbol
= NULL
;
13165 s
->X_op_symbol
= NULL
;
13170 expr_is_register (const expressionS
*s
)
13172 return (s
->X_op
== O_register
);
13176 /* Get the expression constant.
13177 Calling this is illegal if expr_is_const () returns TRUE. */
13180 get_expr_register (const expressionS
*s
)
13182 gas_assert (expr_is_register (s
));
13183 return s
->X_add_number
;
13187 /* Set the expression to a symbol + constant offset. */
13190 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
13192 s
->X_op
= O_symbol
;
13193 s
->X_add_symbol
= sym
;
13194 s
->X_op_symbol
= NULL
; /* unused */
13195 s
->X_add_number
= offset
;
13199 /* Return TRUE if the two expressions are equal. */
13202 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
13204 if (s1
->X_op
!= s2
->X_op
)
13206 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
13208 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
13210 if (s1
->X_add_number
!= s2
->X_add_number
)
13217 copy_expr (expressionS
*dst
, const expressionS
*src
)
13219 memcpy (dst
, src
, sizeof (expressionS
));
13223 /* Support for the "--rename-section" option. */
13225 struct rename_section_struct
13227 const char *old_name
;
13229 struct rename_section_struct
*next
;
13232 static struct rename_section_struct
*section_rename
;
13235 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
13236 entries to the section_rename list. Note: Specifying multiple
13237 renamings separated by colons is not documented and is retained only
13238 for backward compatibility. */
13241 build_section_rename (const char *arg
)
13243 struct rename_section_struct
*r
;
13244 char *this_arg
= NULL
;
13245 char *next_arg
= NULL
;
13247 for (this_arg
= xstrdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
13249 char *old_name
, *new_name
;
13253 next_arg
= strchr (this_arg
, ':');
13261 old_name
= this_arg
;
13262 new_name
= strchr (this_arg
, '=');
13264 if (*old_name
== '\0')
13266 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
13269 if (!new_name
|| new_name
[1] == '\0')
13271 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
13278 /* Check for invalid section renaming. */
13279 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
13281 if (strcmp (r
->old_name
, old_name
) == 0)
13282 as_bad (_("section %s renamed multiple times"), old_name
);
13283 if (strcmp (r
->new_name
, new_name
) == 0)
13284 as_bad (_("multiple sections remapped to output section %s"),
13289 r
= XNEW (struct rename_section_struct
);
13290 r
->old_name
= xstrdup (old_name
);
13291 r
->new_name
= xstrdup (new_name
);
13292 r
->next
= section_rename
;
13293 section_rename
= r
;
13299 xtensa_section_rename (const char *name
)
13301 struct rename_section_struct
*r
= section_rename
;
13303 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
13305 if (strcmp (r
->old_name
, name
) == 0)
13306 return r
->new_name
;
13309 return (char *) name
;