1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright 2003, 2004, 2005 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
25 #include "safe-ctype.h"
26 #include "tc-xtensa.h"
29 #include "xtensa-relax.h"
30 #include "xtensa-istack.h"
31 #include "dwarf2dbg.h"
32 #include "struc-symbol.h"
33 #include "xtensa-config.h"
36 #define uint32 unsigned int
39 #define int32 signed int
44 Naming conventions (used somewhat inconsistently):
45 The xtensa_ functions are exported
46 The xg_ functions are internal
48 We also have a couple of different extensibility mechanisms.
49 1) The idiom replacement:
50 This is used when a line is first parsed to
51 replace an instruction pattern with another instruction
52 It is currently limited to replacements of instructions
53 with constant operands.
54 2) The xtensa-relax.c mechanism that has stronger instruction
55 replacement patterns. When an instruction's immediate field
56 does not fit the next instruction sequence is attempted.
57 In addition, "narrow" opcodes are supported this way. */
60 /* Define characters with special meanings to GAS. */
61 const char comment_chars
[] = "#";
62 const char line_comment_chars
[] = "#";
63 const char line_separator_chars
[] = ";";
64 const char EXP_CHARS
[] = "eE";
65 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
68 /* Flags to indicate whether the hardware supports the density and
69 absolute literals options. */
71 bfd_boolean density_supported
= XCHAL_HAVE_DENSITY
;
72 bfd_boolean absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
74 /* Maximum width we would pad an unreachable frag to get alignment. */
75 #define UNREACHABLE_MAX_WIDTH 8
77 static vliw_insn cur_vinsn
;
79 unsigned xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
81 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
83 /* Some functions are only valid in the front end. This variable
84 allows us to assert that we haven't crossed over into the
86 static bfd_boolean past_xtensa_end
= FALSE
;
88 /* Flags for properties of the last instruction in a segment. */
89 #define FLAG_IS_A0_WRITER 0x1
90 #define FLAG_IS_BAD_LOOPEND 0x2
93 /* We define a special segment names ".literal" to place literals
94 into. The .fini and .init sections are special because they
95 contain code that is moved together by the linker. We give them
96 their own special .fini.literal and .init.literal sections. */
98 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
99 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
100 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
101 #define INIT_SECTION_NAME xtensa_section_rename (".init")
102 #define FINI_LITERAL_SECTION_NAME xtensa_section_rename (".fini.literal")
103 #define INIT_LITERAL_SECTION_NAME xtensa_section_rename (".init.literal")
106 /* This type is used for the directive_stack to keep track of the
107 state of the literal collection pools. */
109 typedef struct lit_state_struct
111 const char *lit_seg_name
;
112 const char *lit4_seg_name
;
113 const char *init_lit_seg_name
;
114 const char *fini_lit_seg_name
;
121 static lit_state default_lit_sections
;
124 /* We keep lists of literal segments. The seg_list type is the node
125 for such a list. The *_literal_head locals are the heads of the
126 various lists. All of these lists have a dummy node at the start. */
128 typedef struct seg_list_struct
130 struct seg_list_struct
*next
;
134 static seg_list literal_head_h
;
135 static seg_list
*literal_head
= &literal_head_h
;
136 static seg_list init_literal_head_h
;
137 static seg_list
*init_literal_head
= &init_literal_head_h
;
138 static seg_list fini_literal_head_h
;
139 static seg_list
*fini_literal_head
= &fini_literal_head_h
;
142 /* Lists of symbols. We keep a list of symbols that label the current
143 instruction, so that we can adjust the symbols when inserting alignment
144 for various instructions. We also keep a list of all the symbols on
145 literals, so that we can fix up those symbols when the literals are
146 later moved into the text sections. */
148 typedef struct sym_list_struct
150 struct sym_list_struct
*next
;
154 static sym_list
*insn_labels
= NULL
;
155 static sym_list
*free_insn_labels
= NULL
;
156 static sym_list
*saved_insn_labels
= NULL
;
158 static sym_list
*literal_syms
;
161 /* Flags to determine whether to prefer const16 or l32r
162 if both options are available. */
163 int prefer_const16
= 0;
166 /* Global flag to indicate when we are emitting literals. */
167 int generating_literals
= 0;
169 /* The following PROPERTY table definitions are copied from
170 <elf/xtensa.h> and must be kept in sync with the code there. */
172 /* Flags in the property tables to specify whether blocks of memory
173 are literals, instructions, data, or unreachable. For
174 instructions, blocks that begin loop targets and branch targets are
175 designated. Blocks that do not allow density, instruction
176 reordering or transformation are also specified. Finally, for
177 branch targets, branch target alignment priority is included.
178 Alignment of the next block is specified in the current block
179 and the size of the current block does not include any fill required
180 to align to the next block. */
182 #define XTENSA_PROP_LITERAL 0x00000001
183 #define XTENSA_PROP_INSN 0x00000002
184 #define XTENSA_PROP_DATA 0x00000004
185 #define XTENSA_PROP_UNREACHABLE 0x00000008
186 /* Instruction only properties at beginning of code. */
187 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
188 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
189 /* Instruction only properties about code. */
190 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
191 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
192 #define XTENSA_PROP_INSN_NO_TRANSFORM 0x00000100
194 /* Branch target alignment information. This transmits information
195 to the linker optimization about the priority of aligning a
196 particular block for branch target alignment: None, low priority,
197 high priority, or required. These only need to be checked in
198 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
201 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
202 case XTENSA_PROP_BT_ALIGN_NONE:
203 case XTENSA_PROP_BT_ALIGN_LOW:
204 case XTENSA_PROP_BT_ALIGN_HIGH:
205 case XTENSA_PROP_BT_ALIGN_REQUIRE:
207 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
209 /* No branch target alignment. */
210 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
211 /* Low priority branch target alignment. */
212 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
213 /* High priority branch target alignment. */
214 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
215 /* Required branch target alignment. */
216 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
218 #define GET_XTENSA_PROP_BT_ALIGN(flag) \
219 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
220 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
221 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
222 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
225 /* Alignment is specified in the block BEFORE the one that needs
226 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
227 get the required alignment specified as a power of 2. Use
228 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
229 alignment. Be careful of side effects since the SET will evaluate
230 flags twice. Also, note that the SIZE of a block in the property
231 table does not include the alignment size, so the alignment fill
232 must be calculated to determine if two blocks are contiguous.
233 TEXT_ALIGN is not currently implemented but is a placeholder for a
234 possible future implementation. */
236 #define XTENSA_PROP_ALIGN 0x00000800
238 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
240 #define GET_XTENSA_PROP_ALIGNMENT(flag) \
241 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
242 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
243 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
244 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
246 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
249 /* Structure for saving instruction and alignment per-fragment data
250 that will be written to the object file. This structure is
251 equivalent to the actual data that will be written out to the file
252 but is easier to use. We provide a conversion to file flags
253 in frag_flags_to_number. */
255 typedef struct frag_flags_struct frag_flags
;
257 struct frag_flags_struct
259 /* is_literal should only be used after xtensa_move_literals.
260 If you need to check if you are generating a literal fragment,
261 then use the generating_literals global. */
263 unsigned is_literal
: 1;
264 unsigned is_insn
: 1;
265 unsigned is_data
: 1;
266 unsigned is_unreachable
: 1;
270 unsigned is_loop_target
: 1;
271 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
272 unsigned bt_align_priority
: 2;
274 unsigned is_no_density
: 1;
275 /* no_longcalls flag does not need to be placed in the object file. */
276 /* is_specific_opcode implies no_transform. */
277 unsigned is_no_transform
: 1;
279 unsigned is_no_reorder
: 1;
281 /* Uses absolute literal addressing for l32r. */
282 unsigned is_abslit
: 1;
284 unsigned is_align
: 1;
285 unsigned alignment
: 5;
289 /* Structure for saving information about a block of property data
290 for frags that have the same flags. */
291 struct xtensa_block_info_struct
297 struct xtensa_block_info_struct
*next
;
301 /* Structure for saving the current state before emitting literals. */
302 typedef struct emit_state_struct
307 int generating_literals
;
311 /* Opcode placement information */
313 typedef unsigned long long bitfield
;
314 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
315 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
316 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
318 #define MAX_FORMATS 32
320 typedef struct op_placement_info_struct
323 /* A number describing how restrictive the issue is for this
324 opcode. For example, an opcode that fits lots of different
325 formats has a high freedom, as does an opcode that fits
326 only one format but many slots in that format. The most
327 restrictive is the opcode that fits only one slot in one
330 /* The single format (i.e., if the op can live in a bundle by itself),
331 narrowest format, and widest format the op can be bundled in
333 xtensa_format single
;
334 xtensa_format narrowest
;
335 xtensa_format widest
;
340 /* formats is a bitfield with the Nth bit set
341 if the opcode fits in the Nth xtensa_format. */
344 /* slots[N]'s Mth bit is set if the op fits in the
345 Mth slot of the Nth xtensa_format. */
346 bitfield slots
[MAX_FORMATS
];
348 /* A count of the number of slots in a given format
349 an op can fit (i.e., the bitcount of the slot field above). */
350 char slots_in_format
[MAX_FORMATS
];
352 } op_placement_info
, *op_placement_info_table
;
354 op_placement_info_table op_placement_table
;
357 /* Extra expression types. */
359 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
360 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
361 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
374 directive_literal_prefix
,
376 directive_absolute_literals
,
377 directive_last_directive
383 bfd_boolean can_be_negated
;
386 const directive_infoS directive_info
[] =
389 { "literal", FALSE
},
391 { "transform", TRUE
},
392 { "freeregs", FALSE
},
393 { "longcalls", TRUE
},
394 { "literal_prefix", FALSE
},
395 { "schedule", TRUE
},
396 { "absolute-literals", TRUE
}
399 bfd_boolean directive_state
[] =
403 #if !XCHAL_HAVE_DENSITY
408 TRUE
, /* transform */
409 FALSE
, /* freeregs */
410 FALSE
, /* longcalls */
411 FALSE
, /* literal_prefix */
413 #if XSHAL_USE_ABSOLUTE_LITERALS
414 TRUE
/* absolute_literals */
416 FALSE
/* absolute_literals */
421 /* Directive functions. */
423 static void xtensa_begin_directive (int);
424 static void xtensa_end_directive (int);
425 static void xtensa_dwarf2_directive_loc (int);
426 static void xtensa_literal_prefix (char const *, int);
427 static void xtensa_literal_position (int);
428 static void xtensa_literal_pseudo (int);
429 static void xtensa_frequency_pseudo (int);
430 static void xtensa_elf_cons (int);
432 /* Parsing and Idiom Translation. */
434 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
436 /* Various Other Internal Functions. */
438 extern bfd_boolean
xg_is_single_relaxable_insn (TInsn
*, TInsn
*, bfd_boolean
);
439 static bfd_boolean
xg_build_to_insn (TInsn
*, TInsn
*, BuildInstr
*);
440 static void xtensa_mark_literal_pool_location (void);
441 static addressT
get_expanded_loop_offset (xtensa_opcode
);
442 static fragS
*get_literal_pool_location (segT
);
443 static void set_literal_pool_location (segT
, fragS
*);
444 static void xtensa_set_frag_assembly_state (fragS
*);
445 static void finish_vinsn (vliw_insn
*);
446 static bfd_boolean
emit_single_op (TInsn
*);
447 static int total_frag_text_expansion (fragS
*);
449 /* Alignment Functions. */
451 static int get_text_align_power (unsigned);
452 static int get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
453 static int branch_align_power (segT
);
455 /* Helpers for xtensa_relax_frag(). */
457 static long relax_frag_add_nop (fragS
*);
459 /* Accessors for additional per-subsegment information. */
461 static unsigned get_last_insn_flags (segT
, subsegT
);
462 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
463 static float get_subseg_total_freq (segT
, subsegT
);
464 static float get_subseg_target_freq (segT
, subsegT
);
465 static void set_subseg_freq (segT
, subsegT
, float, float);
467 /* Segment list functions. */
469 static void xtensa_move_literals (void);
470 static void xtensa_reorder_segments (void);
471 static void xtensa_switch_to_literal_fragment (emit_state
*);
472 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
473 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
474 static void xtensa_restore_emit_state (emit_state
*);
475 static void cache_literal_section
476 (seg_list
*, const char *, segT
*, bfd_boolean
);
478 /* Import from elf32-xtensa.c in BFD library. */
480 extern char *xtensa_get_property_section_name (asection
*, const char *);
482 /* op_placement_info functions. */
484 static void init_op_placement_info_table (void);
485 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
486 static int xg_get_single_size (xtensa_opcode
);
487 static xtensa_format
xg_get_single_format (xtensa_opcode
);
489 /* TInsn and IStack functions. */
491 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
492 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
493 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
494 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
495 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
496 static void tinsn_from_chars (TInsn
*, char *, int);
497 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
498 static int get_num_stack_text_bytes (IStack
*);
499 static int get_num_stack_literal_bytes (IStack
*);
501 /* vliw_insn functions. */
503 static void xg_init_vinsn (vliw_insn
*);
504 static void xg_clear_vinsn (vliw_insn
*);
505 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
506 static void xg_free_vinsn (vliw_insn
*);
507 static bfd_boolean vinsn_to_insnbuf
508 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
509 static void vinsn_from_chars (vliw_insn
*, char *);
511 /* Expression Utilities. */
513 bfd_boolean
expr_is_const (const expressionS
*);
514 offsetT
get_expr_const (const expressionS
*);
515 void set_expr_const (expressionS
*, offsetT
);
516 bfd_boolean
expr_is_register (const expressionS
*);
517 offsetT
get_expr_register (const expressionS
*);
518 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
519 static void set_expr_symbol_offset_diff
520 (expressionS
*, symbolS
*, symbolS
*, offsetT
);
521 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
522 static void copy_expr (expressionS
*, const expressionS
*);
524 /* Section renaming. */
526 static void build_section_rename (const char *);
529 /* ISA imported from bfd. */
530 extern xtensa_isa xtensa_default_isa
;
532 extern int target_big_endian
;
534 static xtensa_opcode xtensa_addi_opcode
;
535 static xtensa_opcode xtensa_addmi_opcode
;
536 static xtensa_opcode xtensa_call0_opcode
;
537 static xtensa_opcode xtensa_call4_opcode
;
538 static xtensa_opcode xtensa_call8_opcode
;
539 static xtensa_opcode xtensa_call12_opcode
;
540 static xtensa_opcode xtensa_callx0_opcode
;
541 static xtensa_opcode xtensa_callx4_opcode
;
542 static xtensa_opcode xtensa_callx8_opcode
;
543 static xtensa_opcode xtensa_callx12_opcode
;
544 static xtensa_opcode xtensa_const16_opcode
;
545 static xtensa_opcode xtensa_entry_opcode
;
546 static xtensa_opcode xtensa_movi_opcode
;
547 static xtensa_opcode xtensa_movi_n_opcode
;
548 static xtensa_opcode xtensa_isync_opcode
;
549 static xtensa_opcode xtensa_jx_opcode
;
550 static xtensa_opcode xtensa_l32r_opcode
;
551 static xtensa_opcode xtensa_loop_opcode
;
552 static xtensa_opcode xtensa_loopnez_opcode
;
553 static xtensa_opcode xtensa_loopgtz_opcode
;
554 static xtensa_opcode xtensa_nop_opcode
;
555 static xtensa_opcode xtensa_nop_n_opcode
;
556 static xtensa_opcode xtensa_or_opcode
;
557 static xtensa_opcode xtensa_ret_opcode
;
558 static xtensa_opcode xtensa_ret_n_opcode
;
559 static xtensa_opcode xtensa_retw_opcode
;
560 static xtensa_opcode xtensa_retw_n_opcode
;
561 static xtensa_opcode xtensa_rsr_lcount_opcode
;
562 static xtensa_opcode xtensa_waiti_opcode
;
565 /* Command-line Options. */
567 bfd_boolean use_literal_section
= TRUE
;
568 static bfd_boolean align_targets
= TRUE
;
569 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
570 static bfd_boolean has_a0_b_retw
= FALSE
;
571 static bfd_boolean workaround_a0_b_retw
= FALSE
;
572 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
573 static bfd_boolean workaround_short_loop
= FALSE
;
574 static bfd_boolean maybe_has_short_loop
= FALSE
;
575 static bfd_boolean workaround_close_loop_end
= FALSE
;
576 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
578 /* When workaround_short_loops is TRUE, all loops with early exits must
579 have at least 3 instructions. workaround_all_short_loops is a modifier
580 to the workaround_short_loop flag. In addition to the
581 workaround_short_loop actions, all straightline loopgtz and loopnez
582 must have at least 3 instructions. */
584 static bfd_boolean workaround_all_short_loops
= FALSE
;
588 xtensa_setup_hw_workarounds (int earliest
, int latest
)
590 if (earliest
> latest
)
591 as_fatal (_("illegal range of target hardware versions"));
593 /* Enable all workarounds for pre-T1050.0 hardware. */
594 if (earliest
< 105000 || latest
< 105000)
596 workaround_a0_b_retw
|= TRUE
;
597 workaround_b_j_loop_end
|= TRUE
;
598 workaround_short_loop
|= TRUE
;
599 workaround_close_loop_end
|= TRUE
;
600 workaround_all_short_loops
|= TRUE
;
607 option_density
= OPTION_MD_BASE
,
614 option_no_link_relax
,
622 option_text_section_literals
,
623 option_no_text_section_literals
,
625 option_absolute_literals
,
626 option_no_absolute_literals
,
628 option_align_targets
,
629 option_no_align_targets
,
631 option_warn_unaligned_targets
,
636 option_workaround_a0_b_retw
,
637 option_no_workaround_a0_b_retw
,
639 option_workaround_b_j_loop_end
,
640 option_no_workaround_b_j_loop_end
,
642 option_workaround_short_loop
,
643 option_no_workaround_short_loop
,
645 option_workaround_all_short_loops
,
646 option_no_workaround_all_short_loops
,
648 option_workaround_close_loop_end
,
649 option_no_workaround_close_loop_end
,
651 option_no_workarounds
,
653 option_rename_section_name
,
656 option_prefer_const16
,
658 option_target_hardware
661 const char *md_shortopts
= "";
663 struct option md_longopts
[] =
665 { "density", no_argument
, NULL
, option_density
},
666 { "no-density", no_argument
, NULL
, option_no_density
},
668 /* Both "relax" and "generics" are deprecated and treated as equivalent
669 to the "transform" option. */
670 { "relax", no_argument
, NULL
, option_relax
},
671 { "no-relax", no_argument
, NULL
, option_no_relax
},
672 { "generics", no_argument
, NULL
, option_generics
},
673 { "no-generics", no_argument
, NULL
, option_no_generics
},
675 { "transform", no_argument
, NULL
, option_transform
},
676 { "no-transform", no_argument
, NULL
, option_no_transform
},
677 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
678 { "no-text-section-literals", no_argument
, NULL
,
679 option_no_text_section_literals
},
680 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
681 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
682 /* This option was changed from -align-target to -target-align
683 because it conflicted with the "-al" option. */
684 { "target-align", no_argument
, NULL
, option_align_targets
},
685 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
686 { "warn-unaligned-targets", no_argument
, NULL
,
687 option_warn_unaligned_targets
},
688 { "longcalls", no_argument
, NULL
, option_longcalls
},
689 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
691 { "no-workaround-a0-b-retw", no_argument
, NULL
,
692 option_no_workaround_a0_b_retw
},
693 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
695 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
696 option_no_workaround_b_j_loop_end
},
697 { "workaround-b-j-loop-end", no_argument
, NULL
,
698 option_workaround_b_j_loop_end
},
700 { "no-workaround-short-loops", no_argument
, NULL
,
701 option_no_workaround_short_loop
},
702 { "workaround-short-loops", no_argument
, NULL
,
703 option_workaround_short_loop
},
705 { "no-workaround-all-short-loops", no_argument
, NULL
,
706 option_no_workaround_all_short_loops
},
707 { "workaround-all-short-loop", no_argument
, NULL
,
708 option_workaround_all_short_loops
},
710 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
711 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
713 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
715 { "no-workaround-close-loop-end", no_argument
, NULL
,
716 option_no_workaround_close_loop_end
},
717 { "workaround-close-loop-end", no_argument
, NULL
,
718 option_workaround_close_loop_end
},
720 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
722 { "link-relax", no_argument
, NULL
, option_link_relax
},
723 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
725 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
727 { NULL
, no_argument
, NULL
, 0 }
730 size_t md_longopts_size
= sizeof md_longopts
;
734 md_parse_option (int c
, char *arg
)
739 as_warn (_("--density option is ignored"));
741 case option_no_density
:
742 as_warn (_("--no-density option is ignored"));
744 case option_link_relax
:
747 case option_no_link_relax
:
750 case option_generics
:
751 as_warn (_("--generics is deprecated; use --transform instead"));
752 return md_parse_option (option_transform
, arg
);
753 case option_no_generics
:
754 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
755 return md_parse_option (option_no_transform
, arg
);
757 as_warn (_("--relax is deprecated; use --transform instead"));
758 return md_parse_option (option_transform
, arg
);
759 case option_no_relax
:
760 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
761 return md_parse_option (option_no_transform
, arg
);
762 case option_longcalls
:
763 directive_state
[directive_longcalls
] = TRUE
;
765 case option_no_longcalls
:
766 directive_state
[directive_longcalls
] = FALSE
;
768 case option_text_section_literals
:
769 use_literal_section
= FALSE
;
771 case option_no_text_section_literals
:
772 use_literal_section
= TRUE
;
774 case option_absolute_literals
:
775 if (!absolute_literals_supported
)
777 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
780 directive_state
[directive_absolute_literals
] = TRUE
;
782 case option_no_absolute_literals
:
783 directive_state
[directive_absolute_literals
] = FALSE
;
786 case option_workaround_a0_b_retw
:
787 workaround_a0_b_retw
= TRUE
;
789 case option_no_workaround_a0_b_retw
:
790 workaround_a0_b_retw
= FALSE
;
792 case option_workaround_b_j_loop_end
:
793 workaround_b_j_loop_end
= TRUE
;
795 case option_no_workaround_b_j_loop_end
:
796 workaround_b_j_loop_end
= FALSE
;
799 case option_workaround_short_loop
:
800 workaround_short_loop
= TRUE
;
802 case option_no_workaround_short_loop
:
803 workaround_short_loop
= FALSE
;
806 case option_workaround_all_short_loops
:
807 workaround_all_short_loops
= TRUE
;
809 case option_no_workaround_all_short_loops
:
810 workaround_all_short_loops
= FALSE
;
813 case option_workaround_close_loop_end
:
814 workaround_close_loop_end
= TRUE
;
816 case option_no_workaround_close_loop_end
:
817 workaround_close_loop_end
= FALSE
;
820 case option_no_workarounds
:
821 workaround_a0_b_retw
= FALSE
;
822 workaround_b_j_loop_end
= FALSE
;
823 workaround_short_loop
= FALSE
;
824 workaround_all_short_loops
= FALSE
;
825 workaround_close_loop_end
= FALSE
;
828 case option_align_targets
:
829 align_targets
= TRUE
;
831 case option_no_align_targets
:
832 align_targets
= FALSE
;
835 case option_warn_unaligned_targets
:
836 warn_unaligned_branch_targets
= TRUE
;
839 case option_rename_section_name
:
840 build_section_rename (arg
);
844 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
845 should be emitted or not. FIXME: Not implemented. */
848 case option_prefer_l32r
:
850 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
854 case option_prefer_const16
:
856 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
860 case option_target_hardware
:
862 int earliest
, latest
= 0;
863 if (*arg
== 0 || *arg
== '-')
864 as_fatal (_("invalid target hardware version"));
866 earliest
= strtol (arg
, &arg
, 0);
870 else if (*arg
== '-')
873 as_fatal (_("invalid target hardware version"));
874 latest
= strtol (arg
, &arg
, 0);
877 as_fatal (_("invalid target hardware version"));
879 xtensa_setup_hw_workarounds (earliest
, latest
);
883 case option_transform
:
884 /* This option has no affect other than to use the defaults,
885 which are already set. */
888 case option_no_transform
:
889 /* This option turns off all transformations of any kind.
890 However, because we want to preserve the state of other
891 directives, we only change its own field. Thus, before
892 you perform any transformation, always check if transform
893 is available. If you use the functions we provide for this
894 purpose, you will be ok. */
895 directive_state
[directive_transform
] = FALSE
;
905 md_show_usage (FILE *stream
)
909 --[no-]text-section-literals\n\
910 [Do not] put literals in the text section\n\
911 --[no-]absolute-literals\n\
912 [Do not] default to use non-PC-relative literals\n\
913 --[no-]target-align [Do not] try to align branch targets\n\
914 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
915 --[no-]transform [Do not] transform instructions\n\
916 --rename-section old=new Rename section 'old' to 'new'\n", stream
);
920 /* Functions related to the list of current label symbols. */
923 xtensa_add_insn_label (symbolS
*sym
)
927 if (!free_insn_labels
)
928 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
931 l
= free_insn_labels
;
932 free_insn_labels
= l
->next
;
936 l
->next
= insn_labels
;
942 xtensa_clear_insn_labels (void)
946 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
953 /* The "loops_ok" argument is provided to allow ignoring labels that
954 define loop ends. This fixes a bug where the NOPs to align a
955 loop opcode were included in a previous zero-cost loop:
974 This argument is used to prevent moving the NOP to before the
975 loop-end label, which is what you want in this special case. */
978 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
, bfd_boolean loops_ok
)
982 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
984 symbolS
*lit_sym
= lit
->sym
;
985 if (loops_ok
|| ! symbol_get_tc (lit_sym
)->is_loop_target
)
987 S_SET_VALUE (lit_sym
, new_offset
);
988 symbol_set_frag (lit_sym
, new_frag
);
994 /* Directive data and functions. */
996 typedef struct state_stackS_struct
998 directiveE directive
;
1000 bfd_boolean old_state
;
1004 struct state_stackS_struct
*prev
;
1007 state_stackS
*directive_state_stack
;
1009 const pseudo_typeS md_pseudo_table
[] =
1011 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
1012 { "literal_position", xtensa_literal_position
, 0 },
1013 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
1014 { "long", xtensa_elf_cons
, 4 },
1015 { "word", xtensa_elf_cons
, 4 },
1016 { "short", xtensa_elf_cons
, 2 },
1017 { "begin", xtensa_begin_directive
, 0 },
1018 { "end", xtensa_end_directive
, 0 },
1019 { "loc", xtensa_dwarf2_directive_loc
, 0 },
1020 { "literal", xtensa_literal_pseudo
, 0 },
1021 { "frequency", xtensa_frequency_pseudo
, 0 },
1027 use_transform (void)
1029 /* After md_end, you should be checking frag by frag, rather
1030 than state directives. */
1031 assert (!past_xtensa_end
);
1032 return directive_state
[directive_transform
];
1037 do_align_targets (void)
1039 /* Do not use this function after md_end; just look at align_targets
1040 instead. There is no target-align directive, so alignment is either
1041 enabled for all frags or not done at all. */
1042 assert (!past_xtensa_end
);
1043 return align_targets
&& use_transform ();
1048 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1052 state_stackS
*stack
= (state_stackS
*) xmalloc (sizeof (state_stackS
));
1054 as_where (&file
, &line
);
1056 stack
->directive
= directive
;
1057 stack
->negated
= negated
;
1058 stack
->old_state
= directive_state
[directive
];
1061 stack
->datum
= datum
;
1062 stack
->prev
= directive_state_stack
;
1063 directive_state_stack
= stack
;
1065 directive_state
[directive
] = !negated
;
1070 directive_pop (directiveE
*directive
,
1071 bfd_boolean
*negated
,
1076 state_stackS
*top
= directive_state_stack
;
1078 if (!directive_state_stack
)
1080 as_bad (_("unmatched end directive"));
1081 *directive
= directive_none
;
1085 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1086 *directive
= top
->directive
;
1087 *negated
= top
->negated
;
1090 *datum
= top
->datum
;
1091 directive_state_stack
= top
->prev
;
1097 directive_balance (void)
1099 while (directive_state_stack
)
1101 directiveE directive
;
1102 bfd_boolean negated
;
1107 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1108 as_warn_where ((char *) file
, line
,
1109 _(".begin directive with no matching .end directive"));
1115 inside_directive (directiveE dir
)
1117 state_stackS
*top
= directive_state_stack
;
1119 while (top
&& top
->directive
!= dir
)
1122 return (top
!= NULL
);
1127 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1131 char *directive_string
;
1133 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1138 input_line_pointer
+= 3;
1141 len
= strspn (input_line_pointer
,
1142 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1144 /* This code is a hack to make .begin [no-][generics|relax] exactly
1145 equivalent to .begin [no-]transform. We should remove it when
1146 we stop accepting those options. */
1148 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1150 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1151 directive_string
= "transform";
1153 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1155 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1156 directive_string
= "transform";
1159 directive_string
= input_line_pointer
;
1161 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1163 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1165 input_line_pointer
+= len
;
1166 *directive
= (directiveE
) i
;
1167 if (*negated
&& !directive_info
[i
].can_be_negated
)
1168 as_bad (_("directive %s cannot be negated"),
1169 directive_info
[i
].name
);
1174 as_bad (_("unknown directive"));
1175 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1180 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1182 directiveE directive
;
1183 bfd_boolean negated
;
1188 get_directive (&directive
, &negated
);
1189 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1191 discard_rest_of_line ();
1195 if (cur_vinsn
.inside_bundle
)
1196 as_bad (_("directives are not valid inside bundles"));
1200 case directive_literal
:
1201 if (!inside_directive (directive_literal
))
1203 /* Previous labels go with whatever follows this directive, not with
1204 the literal, so save them now. */
1205 saved_insn_labels
= insn_labels
;
1208 as_warn (_(".begin literal is deprecated; use .literal instead"));
1209 state
= (emit_state
*) xmalloc (sizeof (emit_state
));
1210 xtensa_switch_to_literal_fragment (state
);
1211 directive_push (directive_literal
, negated
, state
);
1214 case directive_literal_prefix
:
1215 /* Have to flush pending output because a movi relaxed to an l32r
1216 might produce a literal. */
1217 md_flush_pending_output ();
1218 /* Check to see if the current fragment is a literal
1219 fragment. If it is, then this operation is not allowed. */
1220 if (generating_literals
)
1222 as_bad (_("cannot set literal_prefix inside literal fragment"));
1226 /* Allocate the literal state for this section and push
1227 onto the directive stack. */
1228 ls
= xmalloc (sizeof (lit_state
));
1231 *ls
= default_lit_sections
;
1233 directive_push (directive_literal_prefix
, negated
, ls
);
1235 /* Parse the new prefix from the input_line_pointer. */
1237 len
= strspn (input_line_pointer
,
1238 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1239 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1241 /* Process the new prefix. */
1242 xtensa_literal_prefix (input_line_pointer
, len
);
1244 /* Skip the name in the input line. */
1245 input_line_pointer
+= len
;
1248 case directive_freeregs
:
1249 /* This information is currently unused, but we'll accept the statement
1250 and just discard the rest of the line. This won't check the syntax,
1251 but it will accept every correct freeregs directive. */
1252 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1253 directive_push (directive_freeregs
, negated
, 0);
1256 case directive_schedule
:
1257 md_flush_pending_output ();
1258 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1259 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1260 directive_push (directive_schedule
, negated
, 0);
1261 xtensa_set_frag_assembly_state (frag_now
);
1264 case directive_density
:
1265 as_warn (_(".begin [no-]density is ignored"));
1268 case directive_absolute_literals
:
1269 md_flush_pending_output ();
1270 if (!absolute_literals_supported
&& !negated
)
1272 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1275 xtensa_set_frag_assembly_state (frag_now
);
1276 directive_push (directive
, negated
, 0);
1280 md_flush_pending_output ();
1281 xtensa_set_frag_assembly_state (frag_now
);
1282 directive_push (directive
, negated
, 0);
1286 demand_empty_rest_of_line ();
1291 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1293 directiveE begin_directive
, end_directive
;
1294 bfd_boolean begin_negated
, end_negated
;
1298 emit_state
**state_ptr
;
1301 if (cur_vinsn
.inside_bundle
)
1302 as_bad (_("directives are not valid inside bundles"));
1304 get_directive (&end_directive
, &end_negated
);
1306 md_flush_pending_output ();
1308 switch (end_directive
)
1310 case (directiveE
) XTENSA_UNDEFINED
:
1311 discard_rest_of_line ();
1314 case directive_density
:
1315 as_warn (_(".end [no-]density is ignored"));
1316 demand_empty_rest_of_line ();
1319 case directive_absolute_literals
:
1320 if (!absolute_literals_supported
&& !end_negated
)
1322 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1323 demand_empty_rest_of_line ();
1332 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1333 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1334 (const void **) state_ptr
);
1336 if (begin_directive
!= directive_none
)
1338 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1340 as_bad (_("does not match begin %s%s at %s:%d"),
1341 begin_negated
? "no-" : "",
1342 directive_info
[begin_directive
].name
, file
, line
);
1346 switch (end_directive
)
1348 case directive_literal
:
1349 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1350 xtensa_restore_emit_state (state
);
1351 xtensa_set_frag_assembly_state (frag_now
);
1353 if (!inside_directive (directive_literal
))
1355 /* Restore the list of current labels. */
1356 xtensa_clear_insn_labels ();
1357 insn_labels
= saved_insn_labels
;
1361 case directive_literal_prefix
:
1362 /* Restore the default collection sections from saved state. */
1363 s
= (lit_state
*) state
;
1366 if (use_literal_section
)
1367 default_lit_sections
= *s
;
1369 /* free the state storage */
1373 case directive_schedule
:
1374 case directive_freeregs
:
1378 xtensa_set_frag_assembly_state (frag_now
);
1384 demand_empty_rest_of_line ();
1388 /* Wrap dwarf2 functions so that we correctly support the .loc directive. */
1390 static bfd_boolean xtensa_loc_directive_seen
= FALSE
;
1393 xtensa_dwarf2_directive_loc (int x
)
1395 xtensa_loc_directive_seen
= TRUE
;
1396 dwarf2_directive_loc (x
);
1401 xtensa_dwarf2_emit_insn (int size
, struct dwarf2_line_info
*loc
)
1403 if (debug_type
!= DEBUG_DWARF2
&& ! xtensa_loc_directive_seen
)
1405 xtensa_loc_directive_seen
= FALSE
;
1406 dwarf2_gen_line_info (frag_now_fix () - size
, loc
);
1410 /* Place an aligned literal fragment at the current location. */
1413 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1415 md_flush_pending_output ();
1417 if (inside_directive (directive_literal
))
1418 as_warn (_(".literal_position inside literal directive; ignoring"));
1419 xtensa_mark_literal_pool_location ();
1421 demand_empty_rest_of_line ();
1422 xtensa_clear_insn_labels ();
1426 /* Support .literal label, expr, ... */
1429 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1432 char *p
, *base_name
;
1436 if (inside_directive (directive_literal
))
1438 as_bad (_(".literal not allowed inside .begin literal region"));
1439 ignore_rest_of_line ();
1443 md_flush_pending_output ();
1445 /* Previous labels go with whatever follows this directive, not with
1446 the literal, so save them now. */
1447 saved_insn_labels
= insn_labels
;
1450 /* If we are using text-section literals, then this is the right value... */
1453 base_name
= input_line_pointer
;
1455 xtensa_switch_to_literal_fragment (&state
);
1457 /* ...but if we aren't using text-section-literals, then we
1458 need to put them in the section we just switched to. */
1459 if (use_literal_section
|| directive_state
[directive_absolute_literals
])
1462 /* All literals are aligned to four-byte boundaries. */
1463 frag_align (2, 0, 0);
1464 record_alignment (now_seg
, 2);
1466 c
= get_symbol_end ();
1467 /* Just after name is now '\0'. */
1468 p
= input_line_pointer
;
1472 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1474 as_bad (_("expected comma or colon after symbol name; "
1475 "rest of line ignored"));
1476 ignore_rest_of_line ();
1477 xtensa_restore_emit_state (&state
);
1485 input_line_pointer
++; /* skip ',' or ':' */
1487 xtensa_elf_cons (4);
1489 xtensa_restore_emit_state (&state
);
1491 /* Restore the list of current labels. */
1492 xtensa_clear_insn_labels ();
1493 insn_labels
= saved_insn_labels
;
1498 xtensa_literal_prefix (char const *start
, int len
)
1500 char *name
, *linkonce_suffix
;
1501 char *newname
, *newname4
;
1502 size_t linkonce_len
;
1504 /* Get a null-terminated copy of the name. */
1505 name
= xmalloc (len
+ 1);
1508 strncpy (name
, start
, len
);
1511 /* Allocate the sections (interesting note: the memory pointing to
1512 the name is actually used for the name by the new section). */
1514 newname
= xmalloc (len
+ strlen (".literal") + 1);
1515 newname4
= xmalloc (len
+ strlen (".lit4") + 1);
1517 linkonce_len
= sizeof (".gnu.linkonce.") - 1;
1518 if (strncmp (name
, ".gnu.linkonce.", linkonce_len
) == 0
1519 && (linkonce_suffix
= strchr (name
+ linkonce_len
, '.')) != 0)
1521 strcpy (newname
, ".gnu.linkonce.literal");
1522 strcpy (newname4
, ".gnu.linkonce.lit4");
1524 strcat (newname
, linkonce_suffix
);
1525 strcat (newname4
, linkonce_suffix
);
1529 int suffix_pos
= len
;
1531 /* If the section name ends with ".text", then replace that suffix
1532 instead of appending an additional suffix. */
1533 if (len
>= 5 && strcmp (name
+ len
- 5, ".text") == 0)
1536 strcpy (newname
, name
);
1537 strcpy (newname4
, name
);
1539 strcpy (newname
+ suffix_pos
, ".literal");
1540 strcpy (newname4
+ suffix_pos
, ".lit4");
1543 /* Note that cache_literal_section does not create a segment if
1544 it already exists. */
1545 default_lit_sections
.lit_seg
= NULL
;
1546 default_lit_sections
.lit4_seg
= NULL
;
1548 /* Canonicalizing section names allows renaming literal
1549 sections to occur correctly. */
1550 default_lit_sections
.lit_seg_name
= tc_canonicalize_symbol_name (newname
);
1551 default_lit_sections
.lit4_seg_name
= tc_canonicalize_symbol_name (newname4
);
1557 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1560 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1562 float fall_through_f
, target_f
;
1564 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1565 if (fall_through_f
< 0)
1567 as_bad (_("fall through frequency must be greater than 0"));
1568 ignore_rest_of_line ();
1572 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1575 as_bad (_("branch target frequency must be greater than 0"));
1576 ignore_rest_of_line ();
1580 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1582 demand_empty_rest_of_line ();
1586 /* Like normal .long/.short/.word, except support @plt, etc.
1587 Clobbers input_line_pointer, checks end-of-line. */
1590 xtensa_elf_cons (int nbytes
)
1593 bfd_reloc_code_real_type reloc
;
1595 md_flush_pending_output ();
1597 if (cur_vinsn
.inside_bundle
)
1598 as_bad (_("directives are not valid inside bundles"));
1600 if (is_it_end_of_statement ())
1602 demand_empty_rest_of_line ();
1609 if (exp
.X_op
== O_symbol
1610 && *input_line_pointer
== '@'
1611 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1614 reloc_howto_type
*reloc_howto
=
1615 bfd_reloc_type_lookup (stdoutput
, reloc
);
1617 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1618 as_bad (_("unsupported relocation"));
1619 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1620 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1621 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1622 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1623 as_bad (_("opcode-specific %s relocation used outside "
1624 "an instruction"), reloc_howto
->name
);
1625 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1626 as_bad (_("%s relocations do not fit in %d bytes"),
1627 reloc_howto
->name
, nbytes
);
1630 char *p
= frag_more ((int) nbytes
);
1631 xtensa_set_frag_assembly_state (frag_now
);
1632 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1633 nbytes
, &exp
, 0, reloc
);
1637 emit_expr (&exp
, (unsigned int) nbytes
);
1639 while (*input_line_pointer
++ == ',');
1641 input_line_pointer
--; /* Put terminator back into stream. */
1642 demand_empty_rest_of_line ();
1646 /* Parsing and Idiom Translation. */
1648 /* Parse @plt, etc. and return the desired relocation. */
1649 static bfd_reloc_code_real_type
1650 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1656 bfd_reloc_code_real_type reloc
;
1664 struct map_bfd
*ptr
;
1666 #define MAP(str,reloc) { str, sizeof (str) - 1, reloc }
1668 static struct map_bfd mapping
[] =
1670 MAP ("l", BFD_RELOC_LO16
),
1671 MAP ("h", BFD_RELOC_HI16
),
1672 MAP ("plt", BFD_RELOC_XTENSA_PLT
),
1673 { (char *) 0, 0, BFD_RELOC_UNUSED
}
1677 return BFD_RELOC_NONE
;
1679 for (ch
= *str
, str2
= ident
;
1680 (str2
< ident
+ sizeof (ident
) - 1
1681 && (ISALNUM (ch
) || ch
== '@'));
1684 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1691 for (ptr
= &mapping
[0]; ptr
->length
> 0; ptr
++)
1692 if (ch
== ptr
->string
[0]
1693 && len
== ptr
->length
1694 && memcmp (ident
, ptr
->string
, ptr
->length
) == 0)
1696 /* Now check for "identifier@suffix+constant". */
1697 if (*str
== '-' || *str
== '+')
1699 char *orig_line
= input_line_pointer
;
1700 expressionS new_exp
;
1702 input_line_pointer
= str
;
1703 expression (&new_exp
);
1704 if (new_exp
.X_op
== O_constant
)
1706 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1707 str
= input_line_pointer
;
1710 if (&input_line_pointer
!= str_p
)
1711 input_line_pointer
= orig_line
;
1718 return BFD_RELOC_UNUSED
;
1723 expression_end (const char *name
)
1746 #define ERROR_REG_NUM ((unsigned) -1)
1749 tc_get_register (const char *prefix
)
1752 const char *next_expr
;
1753 const char *old_line_pointer
;
1756 old_line_pointer
= input_line_pointer
;
1758 if (*input_line_pointer
== '$')
1759 ++input_line_pointer
;
1761 /* Accept "sp" as a synonym for "a1". */
1762 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1763 && expression_end (input_line_pointer
+ 2))
1765 input_line_pointer
+= 2;
1766 return 1; /* AR[1] */
1769 while (*input_line_pointer
++ == *prefix
++)
1771 --input_line_pointer
;
1776 as_bad (_("bad register name: %s"), old_line_pointer
);
1777 return ERROR_REG_NUM
;
1780 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1782 as_bad (_("bad register number: %s"), input_line_pointer
);
1783 return ERROR_REG_NUM
;
1788 while (ISDIGIT ((int) *input_line_pointer
))
1789 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1791 if (!(next_expr
= expression_end (input_line_pointer
)))
1793 as_bad (_("bad register name: %s"), old_line_pointer
);
1794 return ERROR_REG_NUM
;
1797 input_line_pointer
= (char *) next_expr
;
1804 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1806 xtensa_isa isa
= xtensa_default_isa
;
1808 /* Check if this is an immediate operand. */
1809 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1811 bfd_reloc_code_real_type reloc
;
1812 segT t
= expression (tok
);
1813 if (t
== absolute_section
1814 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1816 assert (tok
->X_op
== O_constant
);
1817 tok
->X_op
= O_symbol
;
1818 tok
->X_add_symbol
= &abs_symbol
;
1821 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1822 && (reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1823 && (reloc
!= BFD_RELOC_NONE
))
1828 case BFD_RELOC_UNUSED
:
1829 as_bad (_("unsupported relocation"));
1832 case BFD_RELOC_XTENSA_PLT
:
1833 tok
->X_op
= O_pltrel
;
1836 case BFD_RELOC_LO16
:
1837 if (tok
->X_op
== O_constant
)
1838 tok
->X_add_number
&= 0xffff;
1843 case BFD_RELOC_HI16
:
1844 if (tok
->X_op
== O_constant
)
1845 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1854 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1855 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1857 if (reg
!= ERROR_REG_NUM
) /* Already errored */
1860 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
1861 as_bad (_("register number out of range"));
1864 tok
->X_op
= O_register
;
1865 tok
->X_add_symbol
= 0;
1866 tok
->X_add_number
= reg
;
1871 /* Split up the arguments for an opcode or pseudo-op. */
1874 tokenize_arguments (char **args
, char *str
)
1876 char *old_input_line_pointer
;
1877 bfd_boolean saw_comma
= FALSE
;
1878 bfd_boolean saw_arg
= FALSE
;
1879 bfd_boolean saw_colon
= FALSE
;
1881 char *arg_end
, *arg
;
1884 /* Save and restore input_line_pointer around this function. */
1885 old_input_line_pointer
= input_line_pointer
;
1886 input_line_pointer
= str
;
1888 while (*input_line_pointer
)
1891 switch (*input_line_pointer
)
1898 input_line_pointer
++;
1899 if (saw_comma
|| saw_colon
|| !saw_arg
)
1905 input_line_pointer
++;
1906 if (saw_comma
|| saw_colon
|| !saw_arg
)
1912 if (!saw_comma
&& !saw_colon
&& saw_arg
)
1915 arg_end
= input_line_pointer
+ 1;
1916 while (!expression_end (arg_end
))
1919 arg_len
= arg_end
- input_line_pointer
;
1920 arg
= (char *) xmalloc ((saw_colon
? 1 : 0) + arg_len
+ 1);
1921 args
[num_args
] = arg
;
1925 strncpy (arg
, input_line_pointer
, arg_len
);
1926 arg
[arg_len
] = '\0';
1928 input_line_pointer
= arg_end
;
1938 if (saw_comma
|| saw_colon
)
1940 input_line_pointer
= old_input_line_pointer
;
1945 as_bad (_("extra comma"));
1947 as_bad (_("extra colon"));
1949 as_bad (_("missing argument"));
1951 as_bad (_("missing comma or colon"));
1952 input_line_pointer
= old_input_line_pointer
;
1957 /* Parse the arguments to an opcode. Return TRUE on error. */
1960 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
1962 expressionS
*tok
, *last_tok
;
1963 xtensa_opcode opcode
= insn
->opcode
;
1964 bfd_boolean had_error
= TRUE
;
1965 xtensa_isa isa
= xtensa_default_isa
;
1966 int n
, num_regs
= 0;
1967 int opcode_operand_count
;
1968 int opnd_cnt
, last_opnd_cnt
;
1969 unsigned int next_reg
= 0;
1970 char *old_input_line_pointer
;
1972 if (insn
->insn_type
== ITYPE_LITERAL
)
1973 opcode_operand_count
= 1;
1975 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
1978 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
1980 /* Save and restore input_line_pointer around this function. */
1981 old_input_line_pointer
= input_line_pointer
;
1987 /* Skip invisible operands. */
1988 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
1994 for (n
= 0; n
< num_args
; n
++)
1996 input_line_pointer
= arg_strings
[n
];
1997 if (*input_line_pointer
== ':')
1999 xtensa_regfile opnd_rf
;
2000 input_line_pointer
++;
2003 assert (opnd_cnt
> 0);
2005 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
2007 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
2008 as_warn (_("incorrect register number, ignoring"));
2013 if (opnd_cnt
>= opcode_operand_count
)
2015 as_warn (_("too many arguments"));
2018 assert (opnd_cnt
< MAX_INSN_ARGS
);
2020 expression_maybe_register (opcode
, opnd_cnt
, tok
);
2021 next_reg
= tok
->X_add_number
+ 1;
2023 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
2025 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
2027 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
2028 /* minus 1 because we are seeing one right now */
2034 last_opnd_cnt
= opnd_cnt
;
2041 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
2045 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
2048 insn
->ntok
= tok
- insn
->tok
;
2052 input_line_pointer
= old_input_line_pointer
;
2058 get_invisible_operands (TInsn
*insn
)
2060 xtensa_isa isa
= xtensa_default_isa
;
2061 static xtensa_insnbuf slotbuf
= NULL
;
2063 xtensa_opcode opc
= insn
->opcode
;
2064 int slot
, opnd
, fmt_found
;
2068 slotbuf
= xtensa_insnbuf_alloc (isa
);
2070 /* Find format/slot where this can be encoded. */
2073 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2075 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2077 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2083 if (fmt_found
) break;
2088 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2092 /* First encode all the visible operands
2093 (to deal with shared field operands). */
2094 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2096 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2097 && (insn
->tok
[opnd
].X_op
== O_register
2098 || insn
->tok
[opnd
].X_op
== O_constant
))
2100 val
= insn
->tok
[opnd
].X_add_number
;
2101 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2102 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2106 /* Then pull out the values for the invisible ones. */
2107 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2109 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2111 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2112 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2113 insn
->tok
[opnd
].X_add_number
= val
;
2114 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2115 insn
->tok
[opnd
].X_op
= O_register
;
2117 insn
->tok
[opnd
].X_op
= O_constant
;
2126 xg_reverse_shift_count (char **cnt_argp
)
2128 char *cnt_arg
, *new_arg
;
2129 cnt_arg
= *cnt_argp
;
2131 /* replace the argument with "31-(argument)" */
2132 new_arg
= (char *) xmalloc (strlen (cnt_arg
) + 6);
2133 sprintf (new_arg
, "31-(%s)", cnt_arg
);
2136 *cnt_argp
= new_arg
;
2140 /* If "arg" is a constant expression, return non-zero with the value
2144 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2147 char *save_ptr
= input_line_pointer
;
2149 input_line_pointer
= arg
;
2151 input_line_pointer
= save_ptr
;
2153 if (exp
.X_op
== O_constant
)
2155 *valp
= exp
.X_add_number
;
2164 xg_replace_opname (char **popname
, char *newop
)
2167 *popname
= (char *) xmalloc (strlen (newop
) + 1);
2168 strcpy (*popname
, newop
);
2173 xg_check_num_args (int *pnum_args
,
2178 int num_args
= *pnum_args
;
2180 if (num_args
< expected_num
)
2182 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2183 num_args
, opname
, expected_num
);
2187 if (num_args
> expected_num
)
2189 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2190 num_args
, opname
, expected_num
);
2191 while (num_args
-- > expected_num
)
2193 free (arg_strings
[num_args
]);
2194 arg_strings
[num_args
] = 0;
2196 *pnum_args
= expected_num
;
2204 /* If the register is not specified as part of the opcode,
2205 then get it from the operand and move it to the opcode. */
2208 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2210 xtensa_isa isa
= xtensa_default_isa
;
2212 char *opname
, *new_opname
;
2213 const char *sr_name
;
2214 int is_user
, is_write
;
2215 bfd_boolean has_underbar
= FALSE
;
2220 has_underbar
= TRUE
;
2223 is_user
= (opname
[1] == 'u');
2224 is_write
= (opname
[0] == 'w');
2226 /* Opname == [rw]ur or [rwx]sr... */
2228 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2231 /* Check if the argument is a symbolic register name. */
2232 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2233 /* Handle WSR to "INTSET" as a special case. */
2234 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2235 && !strcasecmp (arg_strings
[1], "intset"))
2236 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2237 if (sr
== XTENSA_UNDEFINED
2238 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2240 /* Maybe it's a register number.... */
2242 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2244 as_bad (_("invalid register '%s' for '%s' instruction"),
2245 arg_strings
[1], opname
);
2248 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2249 if (sr
== XTENSA_UNDEFINED
)
2251 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2252 (long) val
, opname
);
2257 /* Remove the last argument, which is now part of the opcode. */
2258 free (arg_strings
[1]);
2262 /* Translate the opcode. */
2263 sr_name
= xtensa_sysreg_name (isa
, sr
);
2264 /* Another special case for "WSR.INTSET".... */
2265 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2267 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2268 sprintf (new_opname
, "%s%s.%s", (has_underbar
? "_" : ""),
2271 *popname
= new_opname
;
2278 xtensa_translate_old_userreg_ops (char **popname
)
2280 xtensa_isa isa
= xtensa_default_isa
;
2282 char *opname
, *new_opname
;
2283 const char *sr_name
;
2284 bfd_boolean has_underbar
= FALSE
;
2287 if (opname
[0] == '_')
2289 has_underbar
= TRUE
;
2293 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2294 if (sr
!= XTENSA_UNDEFINED
)
2296 /* The new default name ("nnn") is different from the old default
2297 name ("URnnn"). The old default is handled below, and we don't
2298 want to recognize [RW]nnn, so do nothing if the name is the (new)
2300 static char namebuf
[10];
2301 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2302 if (strcmp (namebuf
, opname
+ 1) == 0)
2310 /* Only continue if the reg name is "URnnn". */
2311 if (opname
[1] != 'u' || opname
[2] != 'r')
2313 val
= strtoul (opname
+ 3, &end
, 10);
2317 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2318 if (sr
== XTENSA_UNDEFINED
)
2320 as_bad (_("invalid register number (%ld) for '%s'"),
2321 (long) val
, opname
);
2326 /* Translate the opcode. */
2327 sr_name
= xtensa_sysreg_name (isa
, sr
);
2328 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2329 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2330 opname
[0], sr_name
);
2332 *popname
= new_opname
;
2339 xtensa_translate_zero_immed (char *old_op
,
2349 assert (opname
[0] != '_');
2351 if (strcmp (opname
, old_op
) != 0)
2354 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2356 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2358 xg_replace_opname (popname
, new_op
);
2359 free (arg_strings
[1]);
2360 arg_strings
[1] = arg_strings
[2];
2369 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2370 Returns non-zero if an error was found. */
2373 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2375 char *opname
= *popname
;
2376 bfd_boolean has_underbar
= FALSE
;
2378 if (cur_vinsn
.inside_bundle
)
2383 has_underbar
= TRUE
;
2387 if (strcmp (opname
, "mov") == 0)
2389 if (use_transform () && !has_underbar
&& density_supported
)
2390 xg_replace_opname (popname
, "mov.n");
2393 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2395 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2396 arg_strings
[2] = (char *) xmalloc (strlen (arg_strings
[1]) + 1);
2397 strcpy (arg_strings
[2], arg_strings
[1]);
2403 if (strcmp (opname
, "bbsi.l") == 0)
2405 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2407 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2408 if (target_big_endian
)
2409 xg_reverse_shift_count (&arg_strings
[1]);
2413 if (strcmp (opname
, "bbci.l") == 0)
2415 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2417 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2418 if (target_big_endian
)
2419 xg_reverse_shift_count (&arg_strings
[1]);
2423 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
2424 && strcmp (opname
, "nop") == 0)
2426 if (use_transform () && !has_underbar
&& density_supported
)
2427 xg_replace_opname (popname
, "nop.n");
2430 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2432 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2433 arg_strings
[0] = (char *) xmalloc (3);
2434 arg_strings
[1] = (char *) xmalloc (3);
2435 arg_strings
[2] = (char *) xmalloc (3);
2436 strcpy (arg_strings
[0], "a1");
2437 strcpy (arg_strings
[1], "a1");
2438 strcpy (arg_strings
[2], "a1");
2444 /* Recognize [RW]UR and [RWX]SR. */
2445 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2446 && (opname
[1] == 'u' || opname
[1] == 's'))
2447 || (opname
[0] == 'x' && opname
[1] == 's'))
2449 && opname
[3] == '\0')
2450 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2452 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2453 [RW]<name> if <name> is the non-default name of a user register. */
2454 if ((opname
[0] == 'r' || opname
[0] == 'w')
2455 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2456 return xtensa_translate_old_userreg_ops (popname
);
2458 /* Relax branches that don't allow comparisons against an immediate value
2459 of zero to the corresponding branches with implicit zero immediates. */
2460 if (!has_underbar
&& use_transform ())
2462 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2463 pnum_args
, arg_strings
))
2466 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2467 pnum_args
, arg_strings
))
2470 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2471 pnum_args
, arg_strings
))
2474 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2475 pnum_args
, arg_strings
))
2483 /* Functions for dealing with the Xtensa ISA. */
2485 /* Currently the assembler only allows us to use a single target per
2486 fragment. Because of this, only one operand for a given
2487 instruction may be symbolic. If there is a PC-relative operand,
2488 the last one is chosen. Otherwise, the result is the number of the
2489 last immediate operand, and if there are none of those, we fail and
2493 get_relaxable_immed (xtensa_opcode opcode
)
2495 int last_immed
= -1;
2498 if (opcode
== XTENSA_UNDEFINED
)
2501 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2502 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2504 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2506 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2508 if (last_immed
== -1
2509 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2516 static xtensa_opcode
2517 get_opcode_from_buf (const char *buf
, int slot
)
2519 static xtensa_insnbuf insnbuf
= NULL
;
2520 static xtensa_insnbuf slotbuf
= NULL
;
2521 xtensa_isa isa
= xtensa_default_isa
;
2526 insnbuf
= xtensa_insnbuf_alloc (isa
);
2527 slotbuf
= xtensa_insnbuf_alloc (isa
);
2530 xtensa_insnbuf_from_chars (isa
, insnbuf
, (const unsigned char *) buf
, 0);
2531 fmt
= xtensa_format_decode (isa
, insnbuf
);
2532 if (fmt
== XTENSA_UNDEFINED
)
2533 return XTENSA_UNDEFINED
;
2535 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2536 return XTENSA_UNDEFINED
;
2538 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2539 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2543 #ifdef TENSILICA_DEBUG
2545 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2548 xtensa_print_insn_table (void)
2550 int num_opcodes
, num_operands
;
2551 xtensa_opcode opcode
;
2552 xtensa_isa isa
= xtensa_default_isa
;
2554 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2555 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2558 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2559 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2560 for (opn
= 0; opn
< num_operands
; opn
++)
2562 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2564 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2566 xtensa_regfile opnd_rf
=
2567 xtensa_operand_regfile (isa
, opcode
, opn
);
2568 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2570 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2571 fputs ("[lLr] ", stderr
);
2573 fputs ("i ", stderr
);
2575 fprintf (stderr
, "\n");
2581 print_vliw_insn (xtensa_insnbuf vbuf
)
2583 xtensa_isa isa
= xtensa_default_isa
;
2584 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2585 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2588 fprintf (stderr
, "format = %d\n", f
);
2590 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2592 xtensa_opcode opcode
;
2596 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2597 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2598 opname
= xtensa_opcode_name (isa
, opcode
);
2600 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2601 fprintf (stderr
, " operands = ");
2603 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2607 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2609 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2610 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2611 fprintf (stderr
, "%d ", val
);
2613 fprintf (stderr
, "\n");
2615 xtensa_insnbuf_free (isa
, sbuf
);
2618 #endif /* TENSILICA_DEBUG */
2622 is_direct_call_opcode (xtensa_opcode opcode
)
2624 xtensa_isa isa
= xtensa_default_isa
;
2625 int n
, num_operands
;
2627 if (xtensa_opcode_is_call (isa
, opcode
) == 0)
2630 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2631 for (n
= 0; n
< num_operands
; n
++)
2633 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2634 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2641 /* Convert from BFD relocation type code to slot and operand number.
2642 Returns non-zero on failure. */
2645 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2647 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2648 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2650 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2653 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2654 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2656 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2666 /* Convert from slot number to BFD relocation type code for the
2667 standard PC-relative relocations. Return BFD_RELOC_NONE on
2670 static bfd_reloc_code_real_type
2671 encode_reloc (int slot
)
2673 if (slot
< 0 || slot
> 14)
2674 return BFD_RELOC_NONE
;
2676 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2680 /* Convert from slot numbers to BFD relocation type code for the
2681 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2683 static bfd_reloc_code_real_type
2684 encode_alt_reloc (int slot
)
2686 if (slot
< 0 || slot
> 14)
2687 return BFD_RELOC_NONE
;
2689 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2694 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2697 xtensa_opcode opcode
,
2703 uint32 valbuf
= value
;
2705 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2707 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2709 as_bad_where ((char *) file
, line
,
2710 _("operand %d of '%s' has out of range value '%u'"),
2712 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2715 as_bad_where ((char *) file
, line
,
2716 _("operand %d of '%s' has invalid value '%u'"),
2718 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2723 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2729 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2732 xtensa_opcode opcode
,
2736 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2737 fmt
, slot
, slotbuf
, &val
);
2738 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2743 /* Checks for rules from xtensa-relax tables. */
2745 /* The routine xg_instruction_matches_option_term must return TRUE
2746 when a given option term is true. The meaning of all of the option
2747 terms is given interpretation by this function. This is needed when
2748 an option depends on the state of a directive, but there are no such
2749 options in use right now. */
2752 xg_instruction_matches_option_term (TInsn
*insn ATTRIBUTE_UNUSED
,
2753 const ReqOrOption
*option
)
2755 if (strcmp (option
->option_name
, "realnop") == 0
2756 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2758 /* These conditions were evaluated statically when building the
2759 relaxation table. There's no need to reevaluate them now. */
2764 as_fatal (_("internal error: unknown option name '%s'"),
2765 option
->option_name
);
2771 xg_instruction_matches_or_options (TInsn
*insn
,
2772 const ReqOrOptionList
*or_option
)
2774 const ReqOrOption
*option
;
2775 /* Must match each of the AND terms. */
2776 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2778 if (xg_instruction_matches_option_term (insn
, option
))
2786 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2788 const ReqOption
*req_options
;
2789 /* Must match each of the AND terms. */
2790 for (req_options
= options
;
2791 req_options
!= NULL
;
2792 req_options
= req_options
->next
)
2794 /* Must match one of the OR clauses. */
2795 if (!xg_instruction_matches_or_options (insn
,
2796 req_options
->or_option_terms
))
2803 /* Return the transition rule that matches or NULL if none matches. */
2806 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2808 PreconditionList
*condition_l
;
2810 if (rule
->opcode
!= insn
->opcode
)
2813 for (condition_l
= rule
->conditions
;
2814 condition_l
!= NULL
;
2815 condition_l
= condition_l
->next
)
2819 Precondition
*cond
= condition_l
->precond
;
2824 /* The expression must be the constant. */
2825 assert (cond
->op_num
< insn
->ntok
);
2826 exp1
= &insn
->tok
[cond
->op_num
];
2827 if (expr_is_const (exp1
))
2832 if (get_expr_const (exp1
) != cond
->op_data
)
2836 if (get_expr_const (exp1
) == cond
->op_data
)
2843 else if (expr_is_register (exp1
))
2848 if (get_expr_register (exp1
) != cond
->op_data
)
2852 if (get_expr_register (exp1
) == cond
->op_data
)
2864 assert (cond
->op_num
< insn
->ntok
);
2865 assert (cond
->op_data
< insn
->ntok
);
2866 exp1
= &insn
->tok
[cond
->op_num
];
2867 exp2
= &insn
->tok
[cond
->op_data
];
2872 if (!expr_is_equal (exp1
, exp2
))
2876 if (expr_is_equal (exp1
, exp2
))
2888 if (!xg_instruction_matches_options (insn
, rule
->options
))
2896 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
2898 bfd_boolean a_greater
= FALSE
;
2899 bfd_boolean b_greater
= FALSE
;
2901 ReqOptionList
*l_a
= a
->options
;
2902 ReqOptionList
*l_b
= b
->options
;
2904 /* We only care if they both are the same except for
2905 a const16 vs. an l32r. */
2907 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2909 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
2910 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
2911 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2913 if (l_or_a
->is_true
!= l_or_b
->is_true
)
2915 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
2917 /* This is the case we care about. */
2918 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
2919 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
2926 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
2927 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
2937 l_or_a
= l_or_a
->next
;
2938 l_or_b
= l_or_b
->next
;
2940 if (l_or_a
|| l_or_b
)
2949 /* Incomparable if the substitution was used differently in two cases. */
2950 if (a_greater
&& b_greater
)
2962 static TransitionRule
*
2963 xg_instruction_match (TInsn
*insn
)
2965 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
2967 assert (insn
->opcode
< table
->num_opcodes
);
2969 /* Walk through all of the possible transitions. */
2970 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2972 TransitionRule
*rule
= l
->rule
;
2973 if (xg_instruction_matches_rule (insn
, rule
))
2980 /* Various Other Internal Functions. */
2983 is_unique_insn_expansion (TransitionRule
*r
)
2985 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
2987 if (r
->to_instr
->typ
!= INSTR_INSTR
)
2993 /* Check if there is exactly one relaxation for INSN that converts it to
2994 another instruction of equal or larger size. If so, and if TARG is
2995 non-null, go ahead and generate the relaxed instruction into TARG. If
2996 NARROW_ONLY is true, then only consider relaxations that widen a narrow
2997 instruction, i.e., ignore relaxations that convert to an instruction of
2998 equal size. In some contexts where this function is used, only
2999 a single widening is allowed and the NARROW_ONLY argument is used to
3000 exclude cases like ADDI being "widened" to an ADDMI, which may
3001 later be relaxed to an ADDMI/ADDI pair. */
3004 xg_is_single_relaxable_insn (TInsn
*insn
, TInsn
*targ
, bfd_boolean narrow_only
)
3006 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3008 TransitionRule
*match
= 0;
3010 assert (insn
->insn_type
== ITYPE_INSN
);
3011 assert (insn
->opcode
< table
->num_opcodes
);
3013 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3015 TransitionRule
*rule
= l
->rule
;
3017 if (xg_instruction_matches_rule (insn
, rule
)
3018 && is_unique_insn_expansion (rule
)
3019 && (xg_get_single_size (insn
->opcode
) + (narrow_only
? 1 : 0)
3020 <= xg_get_single_size (rule
->to_instr
->opcode
)))
3031 xg_build_to_insn (targ
, insn
, match
->to_instr
);
3036 /* Return the maximum number of bytes this opcode can expand to. */
3039 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
3041 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3043 int max_size
= xg_get_single_size (opcode
);
3045 assert (opcode
< table
->num_opcodes
);
3047 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3049 TransitionRule
*rule
= l
->rule
;
3050 BuildInstr
*build_list
;
3055 build_list
= rule
->to_instr
;
3056 if (is_unique_insn_expansion (rule
))
3058 assert (build_list
->typ
== INSTR_INSTR
);
3059 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
3062 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3064 switch (build_list
->typ
)
3067 this_size
+= xg_get_single_size (build_list
->opcode
);
3069 case INSTR_LITERAL_DEF
:
3070 case INSTR_LABEL_DEF
:
3075 if (this_size
> max_size
)
3076 max_size
= this_size
;
3082 /* Return the maximum number of literal bytes this opcode can generate. */
3085 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3087 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3091 assert (opcode
< table
->num_opcodes
);
3093 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3095 TransitionRule
*rule
= l
->rule
;
3096 BuildInstr
*build_list
;
3101 build_list
= rule
->to_instr
;
3102 if (is_unique_insn_expansion (rule
))
3104 assert (build_list
->typ
== INSTR_INSTR
);
3105 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3108 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3110 switch (build_list
->typ
)
3112 case INSTR_LITERAL_DEF
:
3113 /* Hard-coded 4-byte literal. */
3117 case INSTR_LABEL_DEF
:
3122 if (this_size
> max_size
)
3123 max_size
= this_size
;
3130 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3132 int steps_taken
= 0;
3133 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3136 assert (insn
->insn_type
== ITYPE_INSN
);
3137 assert (insn
->opcode
< table
->num_opcodes
);
3139 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3141 TransitionRule
*rule
= l
->rule
;
3143 if (xg_instruction_matches_rule (insn
, rule
))
3145 if (steps_taken
== lateral_steps
)
3155 get_special_literal_symbol (void)
3157 static symbolS
*sym
= NULL
;
3160 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3166 get_special_label_symbol (void)
3168 static symbolS
*sym
= NULL
;
3171 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3177 xg_valid_literal_expression (const expressionS
*exp
)
3194 /* This will check to see if the value can be converted into the
3195 operand type. It will return TRUE if it does not fit. */
3198 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3200 uint32 valbuf
= value
;
3201 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3207 /* Assumes: All immeds are constants. Check that all constants fit
3208 into their immeds; return FALSE if not. */
3211 xg_immeds_fit (const TInsn
*insn
)
3213 xtensa_isa isa
= xtensa_default_isa
;
3217 assert (insn
->insn_type
== ITYPE_INSN
);
3218 for (i
= 0; i
< n
; ++i
)
3220 const expressionS
*expr
= &insn
->tok
[i
];
3221 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3228 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3233 /* The symbol should have a fixup associated with it. */
3242 /* This should only be called after we have an initial
3243 estimate of the addresses. */
3246 xg_symbolic_immeds_fit (const TInsn
*insn
,
3252 xtensa_isa isa
= xtensa_default_isa
;
3260 assert (insn
->insn_type
== ITYPE_INSN
);
3262 for (i
= 0; i
< n
; ++i
)
3264 const expressionS
*expr
= &insn
->tok
[i
];
3265 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3272 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3278 /* Check for the worst case. */
3279 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3284 /* We only allow symbols for PC-relative references.
3285 If pc_frag == 0, then we don't have frag locations yet. */
3287 || xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0)
3290 /* If it is a weak symbol, then assume it won't reach. */
3291 if (S_IS_WEAK (expr
->X_add_symbol
))
3294 if (is_direct_call_opcode (insn
->opcode
)
3295 && ! pc_frag
->tc_frag_data
.use_longcalls
)
3297 /* If callee is undefined or in a different segment, be
3298 optimistic and assume it will be in range. */
3299 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3303 /* Only references within a segment can be known to fit in the
3304 operands at assembly time. */
3305 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3308 symbolP
= expr
->X_add_symbol
;
3309 sym_frag
= symbol_get_frag (symbolP
);
3310 target
= S_GET_VALUE (symbolP
) + expr
->X_add_number
;
3311 pc
= pc_frag
->fr_address
+ pc_offset
;
3313 /* If frag has yet to be reached on this pass, assume it
3314 will move by STRETCH just as we did. If this is not so,
3315 it will be because some frag between grows, and that will
3316 force another pass. Beware zero-length frags. There
3317 should be a faster way to do this. */
3320 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3321 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3326 new_offset
= target
;
3327 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3328 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3333 /* The symbol should have a fixup associated with it. */
3342 /* Return TRUE on success. */
3345 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3350 memset (targ
, 0, sizeof (TInsn
));
3351 targ
->loc
= insn
->loc
;
3356 targ
->opcode
= bi
->opcode
;
3357 targ
->insn_type
= ITYPE_INSN
;
3358 targ
->is_specific_opcode
= FALSE
;
3360 for (; op
!= NULL
; op
= op
->next
)
3362 int op_num
= op
->op_num
;
3363 int op_data
= op
->op_data
;
3365 assert (op
->op_num
< MAX_INSN_ARGS
);
3367 if (targ
->ntok
<= op_num
)
3368 targ
->ntok
= op_num
+ 1;
3373 set_expr_const (&targ
->tok
[op_num
], op_data
);
3376 assert (op_data
< insn
->ntok
);
3377 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3380 sym
= get_special_literal_symbol ();
3381 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3384 sym
= get_special_label_symbol ();
3385 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3387 case OP_OPERAND_HI16U
:
3388 case OP_OPERAND_LOW16U
:
3389 assert (op_data
< insn
->ntok
);
3390 if (expr_is_const (&insn
->tok
[op_data
]))
3393 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3394 val
= xg_apply_userdef_op_fn (op
->typ
,
3397 targ
->tok
[op_num
].X_add_number
= val
;
3401 /* For const16 we can create relocations for these. */
3402 if (targ
->opcode
== XTENSA_UNDEFINED
3403 || (targ
->opcode
!= xtensa_const16_opcode
))
3405 assert (op_data
< insn
->ntok
);
3406 /* Need to build a O_lo16 or O_hi16. */
3407 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3408 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3410 if (op
->typ
== OP_OPERAND_HI16U
)
3411 targ
->tok
[op_num
].X_op
= O_hi16
;
3412 else if (op
->typ
== OP_OPERAND_LOW16U
)
3413 targ
->tok
[op_num
].X_op
= O_lo16
;
3420 /* currently handles:
3423 OP_OPERAND_F32MINUS */
3424 if (xg_has_userdef_op_fn (op
->typ
))
3426 assert (op_data
< insn
->ntok
);
3427 if (expr_is_const (&insn
->tok
[op_data
]))
3430 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3431 val
= xg_apply_userdef_op_fn (op
->typ
,
3434 targ
->tok
[op_num
].X_add_number
= val
;
3437 return FALSE
; /* We cannot use a relocation for this. */
3446 case INSTR_LITERAL_DEF
:
3448 targ
->opcode
= XTENSA_UNDEFINED
;
3449 targ
->insn_type
= ITYPE_LITERAL
;
3450 targ
->is_specific_opcode
= FALSE
;
3451 for (; op
!= NULL
; op
= op
->next
)
3453 int op_num
= op
->op_num
;
3454 int op_data
= op
->op_data
;
3455 assert (op
->op_num
< MAX_INSN_ARGS
);
3457 if (targ
->ntok
<= op_num
)
3458 targ
->ntok
= op_num
+ 1;
3463 assert (op_data
< insn
->ntok
);
3464 /* We can only pass resolvable literals through. */
3465 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3467 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3479 case INSTR_LABEL_DEF
:
3481 targ
->opcode
= XTENSA_UNDEFINED
;
3482 targ
->insn_type
= ITYPE_LABEL
;
3483 targ
->is_specific_opcode
= FALSE
;
3484 /* Literal with no ops is a label? */
3485 assert (op
== NULL
);
3496 /* Return TRUE on success. */
3499 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3501 for (; bi
!= NULL
; bi
= bi
->next
)
3503 TInsn
*next_insn
= istack_push_space (istack
);
3505 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3512 /* Return TRUE on valid expansion. */
3515 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3517 int stack_size
= istack
->ninsn
;
3518 int steps_taken
= 0;
3519 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3522 assert (insn
->insn_type
== ITYPE_INSN
);
3523 assert (insn
->opcode
< table
->num_opcodes
);
3525 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3527 TransitionRule
*rule
= l
->rule
;
3529 if (xg_instruction_matches_rule (insn
, rule
))
3531 if (lateral_steps
== steps_taken
)
3535 /* This is it. Expand the rule to the stack. */
3536 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3539 /* Check to see if it fits. */
3540 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3542 TInsn
*insn
= &istack
->insn
[i
];
3544 if (insn
->insn_type
== ITYPE_INSN
3545 && !tinsn_has_symbolic_operands (insn
)
3546 && !xg_immeds_fit (insn
))
3548 istack
->ninsn
= stack_size
;
3561 /* Relax the assembly instruction at least "min_steps".
3562 Return the number of steps taken. */
3565 xg_assembly_relax (IStack
*istack
,
3568 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3569 offsetT pc_offset
, /* offset in fragment */
3570 int min_steps
, /* minimum conversion steps */
3571 long stretch
) /* number of bytes stretched so far */
3573 int steps_taken
= 0;
3575 /* assert (has no symbolic operands)
3576 Some of its immeds don't fit.
3577 Try to build a relaxed version.
3578 This may go through a couple of stages
3579 of single instruction transformations before
3582 TInsn single_target
;
3584 int lateral_steps
= 0;
3585 int istack_size
= istack
->ninsn
;
3587 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3588 && steps_taken
>= min_steps
)
3590 istack_push (istack
, insn
);
3593 current_insn
= *insn
;
3595 /* Walk through all of the single instruction expansions. */
3596 while (xg_is_single_relaxable_insn (¤t_insn
, &single_target
, FALSE
))
3598 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3602 if (steps_taken
>= min_steps
)
3604 istack_push (istack
, &single_target
);
3608 current_insn
= single_target
;
3611 /* Now check for a multi-instruction expansion. */
3612 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3614 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3617 if (steps_taken
>= min_steps
)
3619 istack_push (istack
, ¤t_insn
);
3624 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3626 if (steps_taken
>= min_steps
)
3630 istack
->ninsn
= istack_size
;
3633 /* It's not going to work -- use the original. */
3634 istack_push (istack
, insn
);
3640 xg_force_frag_space (int size
)
3642 /* This may have the side effect of creating a new fragment for the
3643 space to go into. I just do not like the name of the "frag"
3650 xg_finish_frag (char *last_insn
,
3651 enum xtensa_relax_statesE frag_state
,
3652 enum xtensa_relax_statesE slot0_state
,
3654 bfd_boolean is_insn
)
3656 /* Finish off this fragment so that it has at LEAST the desired
3657 max_growth. If it doesn't fit in this fragment, close this one
3658 and start a new one. In either case, return a pointer to the
3659 beginning of the growth area. */
3663 xg_force_frag_space (max_growth
);
3665 old_frag
= frag_now
;
3667 frag_now
->fr_opcode
= last_insn
;
3669 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3671 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3672 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3674 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3675 xtensa_set_frag_assembly_state (frag_now
);
3677 /* Just to make sure that we did not split it up. */
3678 assert (old_frag
->fr_next
== frag_now
);
3682 /* Return TRUE if the target frag is one of the next non-empty frags. */
3685 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3690 for (; fragP
; fragP
= fragP
->fr_next
)
3692 if (fragP
== target
)
3694 if (fragP
->fr_fix
!= 0)
3696 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3698 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3699 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3701 if (fragP
->fr_type
== rs_space
)
3709 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3711 xtensa_isa isa
= xtensa_default_isa
;
3713 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3718 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 0
3719 && xtensa_opcode_is_jump (isa
, insn
->opcode
) == 0)
3722 for (i
= 0; i
< num_ops
; i
++)
3724 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3730 if (target_op
== -1)
3733 if (insn
->ntok
<= target_op
)
3736 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3739 sym
= insn
->tok
[target_op
].X_add_symbol
;
3743 if (insn
->tok
[target_op
].X_add_number
!= 0)
3746 target_frag
= symbol_get_frag (sym
);
3747 if (target_frag
== NULL
)
3750 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3751 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3759 xg_add_branch_and_loop_targets (TInsn
*insn
)
3761 xtensa_isa isa
= xtensa_default_isa
;
3762 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3764 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3767 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3768 && insn
->tok
[i
].X_op
== O_symbol
)
3769 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3773 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3774 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3778 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3780 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3781 && insn
->tok
[i
].X_op
== O_symbol
)
3783 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3784 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3785 if (S_IS_DEFINED (sym
))
3786 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3793 /* Return FALSE if no error. */
3796 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3801 switch (instr_spec
->typ
)
3804 new_insn
->insn_type
= ITYPE_INSN
;
3805 new_insn
->opcode
= instr_spec
->opcode
;
3806 new_insn
->is_specific_opcode
= FALSE
;
3807 new_insn
->loc
= old_insn
->loc
;
3809 case INSTR_LITERAL_DEF
:
3810 new_insn
->insn_type
= ITYPE_LITERAL
;
3811 new_insn
->opcode
= XTENSA_UNDEFINED
;
3812 new_insn
->is_specific_opcode
= FALSE
;
3813 new_insn
->loc
= old_insn
->loc
;
3815 case INSTR_LABEL_DEF
:
3816 as_bad (_("INSTR_LABEL_DEF not supported yet"));
3820 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3823 const expressionS
*src_exp
;
3829 /* The expression must be the constant. */
3830 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3831 exp
= &new_insn
->tok
[b_op
->op_num
];
3832 set_expr_const (exp
, b_op
->op_data
);
3836 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3837 assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
3838 src_exp
= &old_insn
->tok
[b_op
->op_data
];
3839 exp
= &new_insn
->tok
[b_op
->op_num
];
3840 copy_expr (exp
, src_exp
);
3845 as_bad (_("can't handle generation of literal/labels yet"));
3849 as_bad (_("can't handle undefined OP TYPE"));
3854 new_insn
->ntok
= num_ops
;
3859 /* Return TRUE if it was simplified. */
3862 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
3864 TransitionRule
*rule
;
3865 BuildInstr
*insn_spec
;
3867 if (old_insn
->is_specific_opcode
|| !density_supported
)
3870 rule
= xg_instruction_match (old_insn
);
3874 insn_spec
= rule
->to_instr
;
3875 /* There should only be one. */
3876 assert (insn_spec
!= NULL
);
3877 assert (insn_spec
->next
== NULL
);
3878 if (insn_spec
->next
!= NULL
)
3881 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
3887 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3888 l32i.n. (2) Check the number of operands. (3) Place the instruction
3889 tokens into the stack or relax it and place multiple
3890 instructions/literals onto the stack. Return FALSE if no error. */
3893 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
3897 bfd_boolean do_expand
;
3899 memset (&new_insn
, 0, sizeof (TInsn
));
3901 /* Narrow it if we can. xg_simplify_insn now does all the
3902 appropriate checking (e.g., for the density option). */
3903 if (xg_simplify_insn (orig_insn
, &new_insn
))
3904 orig_insn
= &new_insn
;
3906 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
3908 if (orig_insn
->ntok
< noperands
)
3910 as_bad (_("found %d operands for '%s': Expected %d"),
3912 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3916 if (orig_insn
->ntok
> noperands
)
3917 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
3919 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3922 /* If there are not enough operands, we will assert above. If there
3923 are too many, just cut out the extras here. */
3924 orig_insn
->ntok
= noperands
;
3926 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
3929 /* If the instruction will definitely need to be relaxed, it is better
3930 to expand it now for better scheduling. Decide whether to expand
3932 do_expand
= (!orig_insn
->is_specific_opcode
&& use_transform ());
3934 /* Calls should be expanded to longcalls only in the backend relaxation
3935 so that the assembly scheduler will keep the L32R/CALLX instructions
3937 if (is_direct_call_opcode (orig_insn
->opcode
))
3940 if (tinsn_has_symbolic_operands (orig_insn
))
3942 /* The values of symbolic operands are not known yet, so only expand
3943 now if an operand is "complex" (e.g., difference of symbols) and
3944 will have to be stored as a literal regardless of the value. */
3945 if (!tinsn_has_complex_operands (orig_insn
))
3948 else if (xg_immeds_fit (orig_insn
))
3952 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
3954 istack_push (istack
, orig_insn
);
3960 /* Return TRUE if the section flags are marked linkonce
3961 or the name is .gnu.linkonce*. */
3964 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
3966 flagword flags
, link_once_flags
;
3968 flags
= bfd_get_section_flags (abfd
, sec
);
3969 link_once_flags
= (flags
& SEC_LINK_ONCE
);
3971 /* Flags might not be set yet. */
3972 if (!link_once_flags
)
3974 static size_t len
= sizeof ".gnu.linkonce.t.";
3976 if (strncmp (segment_name (sec
), ".gnu.linkonce.t.", len
- 1) == 0)
3977 link_once_flags
= SEC_LINK_ONCE
;
3979 return (link_once_flags
!= 0);
3984 xtensa_add_literal_sym (symbolS
*sym
)
3988 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
3990 l
->next
= literal_syms
;
3996 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
3998 static int lit_num
= 0;
3999 static char name
[256];
4002 sprintf (name
, ".L_lit_sym%d", lit_num
);
4004 /* Create a local symbol. If it is in a linkonce section, we have to
4005 be careful to make sure that if it is used in a relocation that the
4006 symbol will be in the output file. */
4007 if (get_is_linkonce_section (stdoutput
, sec
))
4009 symbolP
= symbol_new (name
, sec
, 0, frag
);
4010 S_CLEAR_EXTERNAL (symbolP
);
4011 /* symbolP->local = 1; */
4014 symbolP
= symbol_new (name
, sec
, 0, frag
);
4016 xtensa_add_literal_sym (symbolP
);
4018 frag
->tc_frag_data
.is_literal
= TRUE
;
4024 /* Currently all literals that are generated here are 32-bit L32R targets. */
4027 xg_assemble_literal (/* const */ TInsn
*insn
)
4030 symbolS
*lit_sym
= NULL
;
4032 /* size = 4 for L32R. It could easily be larger when we move to
4033 larger constants. Add a parameter later. */
4034 offsetT litsize
= 4;
4035 offsetT litalign
= 2; /* 2^2 = 4 */
4036 expressionS saved_loc
;
4037 expressionS
* emit_val
;
4039 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
4041 assert (insn
->insn_type
== ITYPE_LITERAL
);
4042 assert (insn
->ntok
== 1); /* must be only one token here */
4044 xtensa_switch_to_literal_fragment (&state
);
4046 emit_val
= &insn
->tok
[0];
4047 if (emit_val
->X_op
== O_big
)
4049 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
4052 /* This happens when someone writes a "movi a2, big_number". */
4053 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4054 _("invalid immediate"));
4055 xtensa_restore_emit_state (&state
);
4060 /* Force a 4-byte align here. Note that this opens a new frag, so all
4061 literals done with this function have a frag to themselves. That's
4062 important for the way text section literals work. */
4063 frag_align (litalign
, 0, 0);
4064 record_alignment (now_seg
, litalign
);
4066 if (emit_val
->X_op
== O_pltrel
)
4068 char *p
= frag_more (litsize
);
4069 xtensa_set_frag_assembly_state (frag_now
);
4070 if (emit_val
->X_add_symbol
)
4071 emit_val
->X_op
= O_symbol
;
4073 emit_val
->X_op
= O_constant
;
4074 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
4075 litsize
, emit_val
, 0, BFD_RELOC_XTENSA_PLT
);
4078 emit_expr (emit_val
, litsize
);
4080 assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
4081 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4082 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4083 lit_sym
= frag_now
->fr_symbol
;
4084 frag_now
->tc_frag_data
.is_literal
= TRUE
;
4087 xtensa_restore_emit_state (&state
);
4093 xg_assemble_literal_space (/* const */ int size
, int slot
)
4096 /* We might have to do something about this alignment. It only
4097 takes effect if something is placed here. */
4098 offsetT litalign
= 2; /* 2^2 = 4 */
4099 fragS
*lit_saved_frag
;
4101 assert (size
% 4 == 0);
4103 xtensa_switch_to_literal_fragment (&state
);
4105 /* Force a 4-byte align here. */
4106 frag_align (litalign
, 0, 0);
4107 record_alignment (now_seg
, litalign
);
4109 xg_force_frag_space (size
);
4111 lit_saved_frag
= frag_now
;
4112 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4113 frag_now
->tc_frag_data
.is_literal
= TRUE
;
4114 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4115 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4118 xtensa_restore_emit_state (&state
);
4119 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4123 /* Put in a fixup record based on the opcode.
4124 Return TRUE on success. */
4127 xg_add_opcode_fix (TInsn
*tinsn
,
4135 xtensa_opcode opcode
= tinsn
->opcode
;
4136 bfd_reloc_code_real_type reloc
;
4137 reloc_howto_type
*howto
;
4141 reloc
= BFD_RELOC_NONE
;
4143 /* First try the special cases for "alternate" relocs. */
4144 if (opcode
== xtensa_l32r_opcode
)
4146 if (fragP
->tc_frag_data
.use_absolute_literals
)
4147 reloc
= encode_alt_reloc (slot
);
4149 else if (opcode
== xtensa_const16_opcode
)
4151 if (expr
->X_op
== O_lo16
)
4153 reloc
= encode_reloc (slot
);
4154 expr
->X_op
= O_symbol
;
4156 else if (expr
->X_op
== O_hi16
)
4158 reloc
= encode_alt_reloc (slot
);
4159 expr
->X_op
= O_symbol
;
4163 if (opnum
!= get_relaxable_immed (opcode
))
4165 as_bad (_("invalid relocation for operand %i of '%s'"),
4166 opnum
, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4170 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4171 into the symbol table where the generic portions of the assembler
4172 won't know what to do with them. */
4173 if (expr
->X_op
== O_lo16
|| expr
->X_op
== O_hi16
)
4175 as_bad (_("invalid expression for operand %i of '%s'"),
4176 opnum
, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4180 /* Next try the generic relocs. */
4181 if (reloc
== BFD_RELOC_NONE
)
4182 reloc
= encode_reloc (slot
);
4183 if (reloc
== BFD_RELOC_NONE
)
4185 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4189 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4192 as_bad (_("undefined symbol for opcode \"%s\""),
4193 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4197 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4198 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, expr
,
4199 howto
->pc_relative
, reloc
);
4200 the_fix
->fx_no_overflow
= 1;
4202 if (expr
->X_add_symbol
4203 && (S_IS_EXTERNAL (expr
->X_add_symbol
)
4204 || S_IS_WEAK (expr
->X_add_symbol
)))
4205 the_fix
->fx_plt
= TRUE
;
4207 the_fix
->tc_fix_data
.X_add_symbol
= expr
->X_add_symbol
;
4208 the_fix
->tc_fix_data
.X_add_number
= expr
->X_add_number
;
4209 the_fix
->tc_fix_data
.slot
= slot
;
4216 xg_emit_insn_to_buf (TInsn
*tinsn
,
4221 bfd_boolean build_fix
)
4223 static xtensa_insnbuf insnbuf
= NULL
;
4224 bfd_boolean has_symbolic_immed
= FALSE
;
4225 bfd_boolean ok
= TRUE
;
4227 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4229 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4230 if (has_symbolic_immed
&& build_fix
)
4233 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4234 expressionS
*exp
= &tinsn
->tok
[opnum
];
4236 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, 0, exp
, fragP
, offset
))
4239 fragP
->tc_frag_data
.is_insn
= TRUE
;
4240 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4241 (unsigned char *) buf
, 0);
4247 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4249 symbolS
*sym
= get_special_literal_symbol ();
4253 assert (insn
->insn_type
== ITYPE_INSN
);
4254 for (i
= 0; i
< insn
->ntok
; i
++)
4255 if (insn
->tok
[i
].X_add_symbol
== sym
)
4256 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4262 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4264 symbolS
*sym
= get_special_label_symbol ();
4266 /* assert (!insn->is_literal); */
4267 for (i
= 0; i
< insn
->ntok
; i
++)
4268 if (insn
->tok
[i
].X_add_symbol
== sym
)
4269 insn
->tok
[i
].X_add_symbol
= label_sym
;
4274 /* Return TRUE if the instruction can write to the specified
4275 integer register. */
4278 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4282 xtensa_isa isa
= xtensa_default_isa
;
4284 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4286 for (i
= 0; i
< num_ops
; i
++)
4289 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4290 if ((inout
== 'o' || inout
== 'm')
4291 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4293 xtensa_regfile opnd_rf
=
4294 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4295 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4297 if ((insn
->tok
[i
].X_op
== O_register
)
4298 && (insn
->tok
[i
].X_add_number
== regnum
))
4308 is_bad_loopend_opcode (const TInsn
*tinsn
)
4310 xtensa_opcode opcode
= tinsn
->opcode
;
4312 if (opcode
== XTENSA_UNDEFINED
)
4315 if (opcode
== xtensa_call0_opcode
4316 || opcode
== xtensa_callx0_opcode
4317 || opcode
== xtensa_call4_opcode
4318 || opcode
== xtensa_callx4_opcode
4319 || opcode
== xtensa_call8_opcode
4320 || opcode
== xtensa_callx8_opcode
4321 || opcode
== xtensa_call12_opcode
4322 || opcode
== xtensa_callx12_opcode
4323 || opcode
== xtensa_isync_opcode
4324 || opcode
== xtensa_ret_opcode
4325 || opcode
== xtensa_ret_n_opcode
4326 || opcode
== xtensa_retw_opcode
4327 || opcode
== xtensa_retw_n_opcode
4328 || opcode
== xtensa_waiti_opcode
4329 || opcode
== xtensa_rsr_lcount_opcode
)
4336 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4337 This allows the debugger to add unaligned labels.
4338 Also, the assembler generates stabs labels that need
4339 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4342 is_unaligned_label (symbolS
*sym
)
4344 const char *name
= S_GET_NAME (sym
);
4345 static size_t fake_size
= 0;
4349 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4352 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4354 fake_size
= strlen (FAKE_LABEL_NAME
);
4357 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4358 && (name
[fake_size
] == 'F'
4359 || name
[fake_size
] == 'L'
4360 || (name
[fake_size
] == 'e'
4361 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4369 next_non_empty_frag (const fragS
*fragP
)
4371 fragS
*next_fragP
= fragP
->fr_next
;
4373 /* Sometimes an empty will end up here due storage allocation issues.
4374 So we have to skip until we find something legit. */
4375 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4376 next_fragP
= next_fragP
->fr_next
;
4378 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4386 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4388 xtensa_opcode out_opcode
;
4389 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4391 if (next_fragP
== NULL
)
4394 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4395 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4397 *opcode
= out_opcode
;
4405 frag_format_size (const fragS
*fragP
)
4407 static xtensa_insnbuf insnbuf
= NULL
;
4408 xtensa_isa isa
= xtensa_default_isa
;
4413 insnbuf
= xtensa_insnbuf_alloc (isa
);
4416 return XTENSA_UNDEFINED
;
4418 xtensa_insnbuf_from_chars (isa
, insnbuf
,
4419 (unsigned char *) fragP
->fr_literal
, 0);
4421 fmt
= xtensa_format_decode (isa
, insnbuf
);
4422 if (fmt
== XTENSA_UNDEFINED
)
4423 return XTENSA_UNDEFINED
;
4424 fmt_size
= xtensa_format_length (isa
, fmt
);
4426 /* If the next format won't be changing due to relaxation, just
4427 return the length of the first format. */
4428 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4431 /* If during relaxation we have to pull an instruction out of a
4432 multi-slot instruction, we will return the more conservative
4433 number. This works because alignment on bigger instructions
4434 is more restrictive than alignment on smaller instructions.
4435 This is more conservative than we would like, but it happens
4438 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4441 /* If we aren't doing one of our own relaxations or it isn't
4442 slot-based, then the insn size won't change. */
4443 if (fragP
->fr_type
!= rs_machine_dependent
)
4445 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4448 /* If an instruction is about to grow, return the longer size. */
4449 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4450 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
)
4453 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4454 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4461 next_frag_format_size (const fragS
*fragP
)
4463 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4464 return frag_format_size (next_fragP
);
4468 /* If the next legit fragment is an end-of-loop marker,
4469 switch its state so it will instantiate a NOP. */
4472 update_next_frag_state (fragS
*fragP
)
4474 fragS
*next_fragP
= fragP
->fr_next
;
4475 fragS
*new_target
= NULL
;
4479 /* We are guaranteed there will be one of these... */
4480 while (!(next_fragP
->fr_type
== rs_machine_dependent
4481 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4482 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4483 next_fragP
= next_fragP
->fr_next
;
4485 assert (next_fragP
->fr_type
== rs_machine_dependent
4486 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4487 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4489 /* ...and one of these. */
4490 new_target
= next_fragP
->fr_next
;
4491 while (!(new_target
->fr_type
== rs_machine_dependent
4492 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4493 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4494 new_target
= new_target
->fr_next
;
4496 assert (new_target
->fr_type
== rs_machine_dependent
4497 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4498 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4501 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4503 if (next_fragP
->fr_type
== rs_machine_dependent
4504 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4506 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4510 next_fragP
= next_fragP
->fr_next
;
4516 next_frag_is_branch_target (const fragS
*fragP
)
4518 /* Sometimes an empty will end up here due to storage allocation issues,
4519 so we have to skip until we find something legit. */
4520 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4522 if (fragP
->tc_frag_data
.is_branch_target
)
4524 if (fragP
->fr_fix
!= 0)
4532 next_frag_is_loop_target (const fragS
*fragP
)
4534 /* Sometimes an empty will end up here due storage allocation issues.
4535 So we have to skip until we find something legit. */
4536 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4538 if (fragP
->tc_frag_data
.is_loop_target
)
4540 if (fragP
->fr_fix
!= 0)
4548 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4550 const fragS
*next_fragp
= fragp
->fr_next
;
4551 xtensa_opcode next_opcode
;
4553 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4556 /* Sometimes an empty will end up here due to storage allocation issues,
4557 so we have to skip until we find something legit. */
4558 while (next_fragp
->fr_fix
== 0)
4559 next_fragp
= next_fragp
->fr_next
;
4561 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4564 /* There is some implicit knowledge encoded in here.
4565 The LOOP instructions that are NOT RELAX_IMMED have
4566 been relaxed. Note that we can assume that the LOOP
4567 instruction is in slot 0 because loops aren't bundleable. */
4568 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4569 return get_expanded_loop_offset (next_opcode
);
4575 /* Mark a location where we can later insert literal frags. Update
4576 the section's literal_pool_loc, so subsequent literals can be
4577 placed nearest to their use. */
4580 xtensa_mark_literal_pool_location (void)
4582 /* Any labels pointing to the current location need
4583 to be adjusted to after the literal pool. */
4585 fragS
*pool_location
;
4587 if (use_literal_section
&& !directive_state
[directive_absolute_literals
])
4590 frag_align (2, 0, 0);
4591 record_alignment (now_seg
, 2);
4593 /* We stash info in these frags so we can later move the literal's
4594 fixes into this frchain's fix list. */
4595 pool_location
= frag_now
;
4596 frag_now
->tc_frag_data
.lit_frchain
= frchain_now
;
4597 frag_variant (rs_machine_dependent
, 0, 0,
4598 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4599 xtensa_set_frag_assembly_state (frag_now
);
4600 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
4601 frag_variant (rs_machine_dependent
, 0, 0,
4602 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4603 xtensa_set_frag_assembly_state (frag_now
);
4605 /* Now put a frag into the literal pool that points to this location. */
4606 set_literal_pool_location (now_seg
, pool_location
);
4607 xtensa_switch_to_non_abs_literal_fragment (&s
);
4608 frag_align (2, 0, 0);
4609 record_alignment (now_seg
, 2);
4611 /* Close whatever frag is there. */
4612 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4613 xtensa_set_frag_assembly_state (frag_now
);
4614 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
4615 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4616 xtensa_restore_emit_state (&s
);
4617 xtensa_set_frag_assembly_state (frag_now
);
4621 /* Build a nop of the correct size into tinsn. */
4624 build_nop (TInsn
*tinsn
, int size
)
4630 tinsn
->opcode
= xtensa_nop_n_opcode
;
4632 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4633 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4637 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4639 tinsn
->opcode
= xtensa_or_opcode
;
4640 set_expr_const (&tinsn
->tok
[0], 1);
4641 set_expr_const (&tinsn
->tok
[1], 1);
4642 set_expr_const (&tinsn
->tok
[2], 1);
4646 tinsn
->opcode
= xtensa_nop_opcode
;
4648 assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4653 /* Assemble a NOP of the requested size in the buffer. User must have
4654 allocated "buf" with at least "size" bytes. */
4657 assemble_nop (int size
, char *buf
)
4659 static xtensa_insnbuf insnbuf
= NULL
;
4662 build_nop (&tinsn
, size
);
4665 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4667 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4668 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4669 (unsigned char *) buf
, 0);
4673 /* Return the number of bytes for the offset of the expanded loop
4674 instruction. This should be incorporated into the relaxation
4675 specification but is hard-coded here. This is used to auto-align
4676 the loop instruction. It is invalid to call this function if the
4677 configuration does not have loops or if the opcode is not a loop
4681 get_expanded_loop_offset (xtensa_opcode opcode
)
4683 /* This is the OFFSET of the loop instruction in the expanded loop.
4684 This MUST correspond directly to the specification of the loop
4685 expansion. It will be validated on fragment conversion. */
4686 assert (opcode
!= XTENSA_UNDEFINED
);
4687 if (opcode
== xtensa_loop_opcode
)
4689 if (opcode
== xtensa_loopnez_opcode
)
4691 if (opcode
== xtensa_loopgtz_opcode
)
4693 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4699 get_literal_pool_location (segT seg
)
4701 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4706 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4708 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4712 /* Set frag assembly state should be called when a new frag is
4713 opened and after a frag has been closed. */
4716 xtensa_set_frag_assembly_state (fragS
*fragP
)
4718 if (!density_supported
)
4719 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4721 /* This function is called from subsegs_finish, which is called
4722 after xtensa_end, so we can't use "use_transform" or
4723 "use_schedule" here. */
4724 if (!directive_state
[directive_transform
])
4725 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4726 if (directive_state
[directive_longcalls
])
4727 fragP
->tc_frag_data
.use_longcalls
= TRUE
;
4728 fragP
->tc_frag_data
.use_absolute_literals
=
4729 directive_state
[directive_absolute_literals
];
4730 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4735 relaxable_section (asection
*sec
)
4737 return (sec
->flags
& SEC_DEBUGGING
) == 0;
4742 xtensa_find_unmarked_state_frags (void)
4746 /* Walk over each fragment of all of the current segments. For each
4747 unmarked fragment, mark it with the same info as the previous
4749 for (seclist
= &stdoutput
->sections
;
4750 seclist
&& *seclist
;
4751 seclist
= &(*seclist
)->next
)
4753 segT sec
= *seclist
;
4754 segment_info_type
*seginfo
;
4757 flags
= bfd_get_section_flags (stdoutput
, sec
);
4758 if (flags
& SEC_DEBUGGING
)
4760 if (!(flags
& SEC_ALLOC
))
4763 seginfo
= seg_info (sec
);
4764 if (seginfo
&& seginfo
->frchainP
)
4766 fragS
*last_fragP
= 0;
4767 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4768 fragP
= fragP
->fr_next
)
4770 if (fragP
->fr_fix
!= 0
4771 && !fragP
->tc_frag_data
.is_assembly_state_set
)
4773 if (last_fragP
== 0)
4775 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
4776 _("assembly state not set for first frag in section %s"),
4781 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4782 fragP
->tc_frag_data
.is_no_density
=
4783 last_fragP
->tc_frag_data
.is_no_density
;
4784 fragP
->tc_frag_data
.is_no_transform
=
4785 last_fragP
->tc_frag_data
.is_no_transform
;
4786 fragP
->tc_frag_data
.use_longcalls
=
4787 last_fragP
->tc_frag_data
.use_longcalls
;
4788 fragP
->tc_frag_data
.use_absolute_literals
=
4789 last_fragP
->tc_frag_data
.use_absolute_literals
;
4792 if (fragP
->tc_frag_data
.is_assembly_state_set
)
4801 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
4803 void *unused ATTRIBUTE_UNUSED
)
4805 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4806 segment_info_type
*seginfo
= seg_info (sec
);
4807 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4809 if (flags
& SEC_CODE
)
4811 xtensa_isa isa
= xtensa_default_isa
;
4812 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4813 while (frag
!= NULL
)
4815 if (frag
->tc_frag_data
.is_branch_target
)
4818 addressT branch_align
, frag_addr
;
4821 xtensa_insnbuf_from_chars
4822 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4823 fmt
= xtensa_format_decode (isa
, insnbuf
);
4824 op_size
= xtensa_format_length (isa
, fmt
);
4825 branch_align
= 1 << branch_align_power (sec
);
4826 frag_addr
= frag
->fr_address
% branch_align
;
4827 if (frag_addr
+ op_size
> branch_align
)
4828 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4829 _("unaligned branch target: %d bytes at 0x%lx"),
4830 op_size
, (long) frag
->fr_address
);
4832 frag
= frag
->fr_next
;
4834 xtensa_insnbuf_free (isa
, insnbuf
);
4840 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
4842 void *unused ATTRIBUTE_UNUSED
)
4844 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4845 segment_info_type
*seginfo
= seg_info (sec
);
4846 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4847 xtensa_isa isa
= xtensa_default_isa
;
4849 if (flags
& SEC_CODE
)
4851 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4852 while (frag
!= NULL
)
4854 if (frag
->tc_frag_data
.is_first_loop_insn
)
4860 xtensa_insnbuf_from_chars
4861 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4862 fmt
= xtensa_format_decode (isa
, insnbuf
);
4863 op_size
= xtensa_format_length (isa
, fmt
);
4864 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
4866 if (frag_addr
+ op_size
> xtensa_fetch_width
)
4867 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4868 _("unaligned loop: %d bytes at 0x%lx"),
4869 op_size
, (long) frag
->fr_address
);
4871 frag
= frag
->fr_next
;
4873 xtensa_insnbuf_free (isa
, insnbuf
);
4879 xg_apply_fix_value (fixS
*fixP
, valueT val
)
4881 xtensa_isa isa
= xtensa_default_isa
;
4882 static xtensa_insnbuf insnbuf
= NULL
;
4883 static xtensa_insnbuf slotbuf
= NULL
;
4886 bfd_boolean alt_reloc
;
4887 xtensa_opcode opcode
;
4888 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
4890 (void) decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
);
4892 as_fatal (_("unexpected fix"));
4896 insnbuf
= xtensa_insnbuf_alloc (isa
);
4897 slotbuf
= xtensa_insnbuf_alloc (isa
);
4900 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4901 fmt
= xtensa_format_decode (isa
, insnbuf
);
4902 if (fmt
== XTENSA_UNDEFINED
)
4903 as_fatal (_("undecodable fix"));
4904 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4905 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
4906 if (opcode
== XTENSA_UNDEFINED
)
4907 as_fatal (_("undecodable fix"));
4909 /* CONST16 immediates are not PC-relative, despite the fact that we
4910 reuse the normal PC-relative operand relocations for the low part
4911 of a CONST16 operand. */
4912 if (opcode
== xtensa_const16_opcode
)
4915 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
4916 get_relaxable_immed (opcode
), val
,
4917 fixP
->fx_file
, fixP
->fx_line
);
4919 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4920 xtensa_insnbuf_to_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4926 /* External Functions and Other GAS Hooks. */
4929 xtensa_target_format (void)
4931 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
4936 xtensa_file_arch_init (bfd
*abfd
)
4938 bfd_set_private_flags (abfd
, 0x100 | 0x200);
4943 md_number_to_chars (char *buf
, valueT val
, int n
)
4945 if (target_big_endian
)
4946 number_to_chars_bigendian (buf
, val
, n
);
4948 number_to_chars_littleendian (buf
, val
, n
);
4952 /* This function is called once, at assembler startup time. It should
4953 set up all the tables, etc. that the MD part of the assembler will
4959 segT current_section
= now_seg
;
4960 int current_subsec
= now_subseg
;
4963 xtensa_default_isa
= xtensa_isa_init (0, 0);
4964 isa
= xtensa_default_isa
;
4968 /* Set up the .literal, .fini.literal and .init.literal sections. */
4969 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
4970 default_lit_sections
.init_lit_seg_name
= INIT_LITERAL_SECTION_NAME
;
4971 default_lit_sections
.fini_lit_seg_name
= FINI_LITERAL_SECTION_NAME
;
4972 default_lit_sections
.lit_seg_name
= LITERAL_SECTION_NAME
;
4973 default_lit_sections
.lit4_seg_name
= LIT4_SECTION_NAME
;
4975 subseg_set (current_section
, current_subsec
);
4977 xg_init_vinsn (&cur_vinsn
);
4979 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
4980 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
4981 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
4982 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
4983 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
4984 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
4985 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
4986 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
4987 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
4988 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
4989 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
4990 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
4991 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
4992 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
4993 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
4994 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
4995 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
4996 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
4997 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
4998 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
4999 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
5000 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
5001 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
5002 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
5003 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
5004 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
5005 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
5006 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
5007 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
5009 init_op_placement_info_table ();
5011 /* Set up the assembly state. */
5012 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5013 xtensa_set_frag_assembly_state (frag_now
);
5017 /* TC_INIT_FIX_DATA hook */
5020 xtensa_init_fix_data (fixS
*x
)
5022 x
->tc_fix_data
.slot
= 0;
5023 x
->tc_fix_data
.X_add_symbol
= NULL
;
5024 x
->tc_fix_data
.X_add_number
= 0;
5028 /* tc_frob_label hook */
5031 xtensa_frob_label (symbolS
*sym
)
5033 float freq
= get_subseg_target_freq (now_seg
, now_subseg
);
5035 /* Since the label was already attached to a frag associated with the
5036 previous basic block, it now needs to be reset to the current frag. */
5037 symbol_set_frag (sym
, frag_now
);
5038 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5040 if (generating_literals
)
5041 xtensa_add_literal_sym (sym
);
5043 xtensa_add_insn_label (sym
);
5045 if (symbol_get_tc (sym
)->is_loop_target
)
5047 if ((get_last_insn_flags (now_seg
, now_subseg
)
5048 & FLAG_IS_BAD_LOOPEND
) != 0)
5049 as_bad (_("invalid last instruction for a zero-overhead loop"));
5051 xtensa_set_frag_assembly_state (frag_now
);
5052 frag_var (rs_machine_dependent
, 4, 4, RELAX_LOOP_END
,
5053 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5055 xtensa_set_frag_assembly_state (frag_now
);
5056 xtensa_move_labels (frag_now
, 0, TRUE
);
5059 /* No target aligning in the absolute section. */
5060 if (now_seg
!= absolute_section
5061 && do_align_targets ()
5062 && !is_unaligned_label (sym
)
5063 && !generating_literals
)
5065 xtensa_set_frag_assembly_state (frag_now
);
5067 frag_var (rs_machine_dependent
,
5069 RELAX_DESIRE_ALIGN_IF_TARGET
,
5070 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5071 xtensa_set_frag_assembly_state (frag_now
);
5072 xtensa_move_labels (frag_now
, 0, TRUE
);
5075 /* We need to mark the following properties even if we aren't aligning. */
5077 /* If the label is already known to be a branch target, i.e., a
5078 forward branch, mark the frag accordingly. Backward branches
5079 are handled by xg_add_branch_and_loop_targets. */
5080 if (symbol_get_tc (sym
)->is_branch_target
)
5081 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5083 /* Loops only go forward, so they can be identified here. */
5084 if (symbol_get_tc (sym
)->is_loop_target
)
5085 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5087 dwarf2_emit_label (sym
);
5091 /* tc_unrecognized_line hook */
5094 xtensa_unrecognized_line (int ch
)
5099 if (cur_vinsn
.inside_bundle
== 0)
5101 /* PR8110: Cannot emit line number info inside a FLIX bundle
5102 when using --gstabs. Temporarily disable debug info. */
5103 generate_lineno_debug ();
5104 if (debug_type
== DEBUG_STABS
)
5106 xt_saved_debug_type
= debug_type
;
5107 debug_type
= DEBUG_NONE
;
5110 cur_vinsn
.inside_bundle
= 1;
5114 as_bad (_("extra opening brace"));
5120 if (cur_vinsn
.inside_bundle
)
5121 finish_vinsn (&cur_vinsn
);
5124 as_bad (_("extra closing brace"));
5129 as_bad (_("syntax error"));
5136 /* md_flush_pending_output hook */
5139 xtensa_flush_pending_output (void)
5141 if (cur_vinsn
.inside_bundle
)
5142 as_bad (_("missing closing brace"));
5144 /* If there is a non-zero instruction fragment, close it. */
5145 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5147 frag_wane (frag_now
);
5149 xtensa_set_frag_assembly_state (frag_now
);
5151 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5153 xtensa_clear_insn_labels ();
5157 /* We had an error while parsing an instruction. The string might look
5158 like this: "insn arg1, arg2 }". If so, we need to see the closing
5159 brace and reset some fields. Otherwise, the vinsn never gets closed
5160 and the num_slots field will grow past the end of the array of slots,
5161 and bad things happen. */
5164 error_reset_cur_vinsn (void)
5166 if (cur_vinsn
.inside_bundle
)
5168 if (*input_line_pointer
== '}'
5169 || *(input_line_pointer
- 1) == '}'
5170 || *(input_line_pointer
- 2) == '}')
5171 xg_clear_vinsn (&cur_vinsn
);
5177 md_assemble (char *str
)
5179 xtensa_isa isa
= xtensa_default_isa
;
5182 bfd_boolean has_underbar
= FALSE
;
5183 char *arg_strings
[MAX_INSN_ARGS
];
5185 TInsn orig_insn
; /* Original instruction from the input. */
5187 tinsn_init (&orig_insn
);
5189 /* Split off the opcode. */
5190 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5191 opname
= xmalloc (opnamelen
+ 1);
5192 memcpy (opname
, str
, opnamelen
);
5193 opname
[opnamelen
] = '\0';
5195 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5198 as_bad (_("syntax error"));
5202 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5205 /* Check for an underbar prefix. */
5208 has_underbar
= TRUE
;
5212 orig_insn
.insn_type
= ITYPE_INSN
;
5214 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5216 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5217 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5219 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5220 if (fmt
== XTENSA_UNDEFINED
)
5222 as_bad (_("unknown opcode or format name '%s'"), opname
);
5223 error_reset_cur_vinsn ();
5226 if (!cur_vinsn
.inside_bundle
)
5228 as_bad (_("format names only valid inside bundles"));
5229 error_reset_cur_vinsn ();
5232 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5233 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5235 cur_vinsn
.format
= fmt
;
5236 free (has_underbar
? opname
- 1 : opname
);
5237 error_reset_cur_vinsn ();
5241 /* Parse the arguments. */
5242 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5244 as_bad (_("syntax error"));
5245 error_reset_cur_vinsn ();
5249 /* Free the opcode and argument strings, now that they've been parsed. */
5250 free (has_underbar
? opname
- 1 : opname
);
5252 while (num_args
-- > 0)
5253 free (arg_strings
[num_args
]);
5255 /* Get expressions for invisible operands. */
5256 if (get_invisible_operands (&orig_insn
))
5258 error_reset_cur_vinsn ();
5262 /* Check for the right number and type of arguments. */
5263 if (tinsn_check_arguments (&orig_insn
))
5265 error_reset_cur_vinsn ();
5269 dwarf2_where (&orig_insn
.loc
);
5271 xg_add_branch_and_loop_targets (&orig_insn
);
5273 /* Special-case for "entry" instruction. */
5274 if (orig_insn
.opcode
== xtensa_entry_opcode
)
5276 /* Check that the third opcode (#2) is >= 16. */
5277 if (orig_insn
.ntok
>= 3)
5279 expressionS
*exp
= &orig_insn
.tok
[2];
5283 if (exp
->X_add_number
< 16)
5284 as_warn (_("entry instruction with stack decrement < 16"));
5288 as_warn (_("entry instruction with non-constant decrement"));
5294 assemble_tokens (opcode, tok, ntok);
5295 expand the tokens from the orig_insn into the
5296 stack of instructions that will not expand
5297 unless required at relaxation time. */
5299 if (!cur_vinsn
.inside_bundle
)
5300 emit_single_op (&orig_insn
);
5301 else /* We are inside a bundle. */
5303 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5304 cur_vinsn
.num_slots
++;
5305 if (*input_line_pointer
== '}'
5306 || *(input_line_pointer
- 1) == '}'
5307 || *(input_line_pointer
- 2) == '}')
5308 finish_vinsn (&cur_vinsn
);
5311 /* We've just emitted a new instruction so clear the list of labels. */
5312 xtensa_clear_insn_labels ();
5316 /* HANDLE_ALIGN hook */
5318 /* For a .align directive, we mark the previous block with the alignment
5319 information. This will be placed in the object file in the
5320 property section corresponding to this section. */
5323 xtensa_handle_align (fragS
*fragP
)
5326 && ! fragP
->tc_frag_data
.is_literal
5327 && (fragP
->fr_type
== rs_align
5328 || fragP
->fr_type
== rs_align_code
)
5329 && fragP
->fr_address
+ fragP
->fr_fix
> 0
5330 && fragP
->fr_offset
> 0
5331 && now_seg
!= bss_section
)
5333 fragP
->tc_frag_data
.is_align
= TRUE
;
5334 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5337 if (fragP
->fr_type
== rs_align_test
)
5340 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5342 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5343 _("unaligned entry instruction"));
5348 /* TC_FRAG_INIT hook */
5351 xtensa_frag_init (fragS
*frag
)
5353 xtensa_set_frag_assembly_state (frag
);
5358 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5364 /* Round up a section size to the appropriate boundary. */
5367 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5369 return size
; /* Byte alignment is fine. */
5374 md_pcrel_from (fixS
*fixP
)
5377 static xtensa_insnbuf insnbuf
= NULL
;
5378 static xtensa_insnbuf slotbuf
= NULL
;
5381 xtensa_opcode opcode
;
5384 xtensa_isa isa
= xtensa_default_isa
;
5385 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5386 bfd_boolean alt_reloc
;
5388 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5393 insnbuf
= xtensa_insnbuf_alloc (isa
);
5394 slotbuf
= xtensa_insnbuf_alloc (isa
);
5397 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5398 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) insn_p
, 0);
5399 fmt
= xtensa_format_decode (isa
, insnbuf
);
5401 if (fmt
== XTENSA_UNDEFINED
)
5402 as_fatal (_("bad instruction format"));
5404 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5405 as_fatal (_("invalid relocation"));
5407 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5408 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5410 /* Check for "alternate" relocations (operand not specified). None
5411 of the current uses for these are really PC-relative. */
5412 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5414 if (opcode
!= xtensa_l32r_opcode
5415 && opcode
!= xtensa_const16_opcode
)
5416 as_fatal (_("invalid relocation for '%s' instruction"),
5417 xtensa_opcode_name (isa
, opcode
));
5421 opnum
= get_relaxable_immed (opcode
);
5423 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5424 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5426 as_bad_where (fixP
->fx_file
,
5428 _("invalid relocation for operand %d of '%s'"),
5429 opnum
, xtensa_opcode_name (isa
, opcode
));
5432 return 0 - opnd_value
;
5436 /* TC_FORCE_RELOCATION hook */
5439 xtensa_force_relocation (fixS
*fix
)
5441 switch (fix
->fx_r_type
)
5443 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5444 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5445 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5446 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5447 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5448 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5449 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5450 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5451 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5452 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5453 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5454 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5455 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5456 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5457 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5458 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5464 if (linkrelax
&& fix
->fx_addsy
5465 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5468 return generic_force_reloc (fix
);
5472 /* TC_VALIDATE_FIX_SUB hook */
5475 xtensa_validate_fix_sub (fixS
*fix
)
5477 segT add_symbol_segment
, sub_symbol_segment
;
5479 /* The difference of two symbols should be resolved by the assembler when
5480 linkrelax is not set. If the linker may relax the section containing
5481 the symbols, then an Xtensa DIFF relocation must be generated so that
5482 the linker knows to adjust the difference value. */
5483 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
5486 /* Make sure both symbols are in the same segment, and that segment is
5487 "normal" and relaxable. If the segment is not "normal", then the
5488 fix is not valid. If the segment is not "relaxable", then the fix
5489 should have been handled earlier. */
5490 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
5491 if (! SEG_NORMAL (add_symbol_segment
) ||
5492 ! relaxable_section (add_symbol_segment
))
5494 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
5495 return (sub_symbol_segment
== add_symbol_segment
);
5499 /* NO_PSEUDO_DOT hook */
5501 /* This function has nothing to do with pseudo dots, but this is the
5502 nearest macro to where the check needs to take place. FIXME: This
5506 xtensa_check_inside_bundle (void)
5508 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5509 as_bad (_("directives are not valid inside bundles"));
5511 /* This function must always return FALSE because it is called via a
5512 macro that has nothing to do with bundling. */
5517 /* md_elf_section_change_hook */
5520 xtensa_elf_section_change_hook (void)
5522 /* Set up the assembly state. */
5523 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5524 xtensa_set_frag_assembly_state (frag_now
);
5528 /* tc_fix_adjustable hook */
5531 xtensa_fix_adjustable (fixS
*fixP
)
5533 /* An offset is not allowed in combination with the difference of two
5534 symbols, but that cannot be easily detected after a local symbol
5535 has been adjusted to a (section+offset) form. Return 0 so that such
5536 an fix will not be adjusted. */
5537 if (fixP
->fx_subsy
&& fixP
->fx_addsy
&& fixP
->fx_offset
5538 && relaxable_section (S_GET_SEGMENT (fixP
->fx_subsy
)))
5541 /* We need the symbol name for the VTABLE entries. */
5542 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5543 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5551 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg
)
5553 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5556 switch (fixP
->fx_r_type
)
5561 if (linkrelax
&& fixP
->fx_subsy
)
5563 switch (fixP
->fx_r_type
)
5566 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF8
;
5569 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF16
;
5572 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF32
;
5578 /* An offset is only allowed when it results from adjusting a
5579 local symbol into a section-relative offset. If the offset
5580 came from the original expression, tc_fix_adjustable will have
5581 prevented the fix from being converted to a section-relative
5582 form so that we can flag the error here. */
5583 if (fixP
->fx_offset
!= 0 && !symbol_section_p (fixP
->fx_addsy
))
5584 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5585 _("cannot represent subtraction with an offset"));
5587 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5588 - S_GET_VALUE (fixP
->fx_subsy
));
5590 /* The difference value gets written out, and the DIFF reloc
5591 identifies the address of the subtracted symbol (i.e., the one
5592 with the lowest address). */
5594 fixP
->fx_offset
-= val
;
5595 fixP
->fx_subsy
= NULL
;
5597 else if (! fixP
->fx_addsy
)
5604 md_number_to_chars (fixpos
, val
, fixP
->fx_size
);
5605 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5608 case BFD_RELOC_XTENSA_SLOT0_OP
:
5609 case BFD_RELOC_XTENSA_SLOT1_OP
:
5610 case BFD_RELOC_XTENSA_SLOT2_OP
:
5611 case BFD_RELOC_XTENSA_SLOT3_OP
:
5612 case BFD_RELOC_XTENSA_SLOT4_OP
:
5613 case BFD_RELOC_XTENSA_SLOT5_OP
:
5614 case BFD_RELOC_XTENSA_SLOT6_OP
:
5615 case BFD_RELOC_XTENSA_SLOT7_OP
:
5616 case BFD_RELOC_XTENSA_SLOT8_OP
:
5617 case BFD_RELOC_XTENSA_SLOT9_OP
:
5618 case BFD_RELOC_XTENSA_SLOT10_OP
:
5619 case BFD_RELOC_XTENSA_SLOT11_OP
:
5620 case BFD_RELOC_XTENSA_SLOT12_OP
:
5621 case BFD_RELOC_XTENSA_SLOT13_OP
:
5622 case BFD_RELOC_XTENSA_SLOT14_OP
:
5625 /* Write the tentative value of a PC-relative relocation to a
5626 local symbol into the instruction. The value will be ignored
5627 by the linker, and it makes the object file disassembly
5628 readable when all branch targets are encoded in relocations. */
5630 assert (fixP
->fx_addsy
);
5631 if (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
&& !fixP
->fx_plt
5632 && !S_FORCE_RELOC (fixP
->fx_addsy
, 1))
5634 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5635 - md_pcrel_from (fixP
));
5636 (void) xg_apply_fix_value (fixP
, val
);
5639 else if (! fixP
->fx_addsy
)
5642 if (xg_apply_fix_value (fixP
, val
))
5647 case BFD_RELOC_XTENSA_PLT
:
5648 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5649 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5650 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5651 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5652 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5653 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5654 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5655 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5656 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5657 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5658 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5659 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5660 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5661 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5662 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5663 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5664 /* These all need to be resolved at link-time. Do nothing now. */
5667 case BFD_RELOC_VTABLE_INHERIT
:
5668 case BFD_RELOC_VTABLE_ENTRY
:
5673 as_bad (_("unhandled local relocation fix %s"),
5674 bfd_get_reloc_code_name (fixP
->fx_r_type
));
5680 md_atof (int type
, char *litP
, int *sizeP
)
5683 LITTLENUM_TYPE words
[4];
5699 return "bad call to md_atof";
5702 t
= atof_ieee (input_line_pointer
, type
, words
);
5704 input_line_pointer
= t
;
5708 for (i
= prec
- 1; i
>= 0; i
--)
5711 if (target_big_endian
)
5712 idx
= (prec
- 1 - i
);
5714 md_number_to_chars (litP
, (valueT
) words
[idx
], 2);
5723 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
5725 return total_frag_text_expansion (fragP
);
5729 /* Translate internal representation of relocation info to BFD target
5733 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
5737 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
5738 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5739 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5740 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5742 /* Make sure none of our internal relocations make it this far.
5743 They'd better have been fully resolved by this point. */
5744 assert ((int) fixp
->fx_r_type
> 0);
5746 reloc
->addend
= fixp
->fx_offset
;
5748 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
5749 if (reloc
->howto
== NULL
)
5751 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5752 _("cannot represent `%s' relocation in object file"),
5753 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5754 free (reloc
->sym_ptr_ptr
);
5759 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
5760 as_fatal (_("internal error? cannot generate `%s' relocation"),
5761 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5767 /* Checks for resource conflicts between instructions. */
5769 /* The func unit stuff could be implemented as bit-vectors rather
5770 than the iterative approach here. If it ends up being too
5771 slow, we will switch it. */
5774 new_resource_table (void *data
,
5777 unit_num_copies_func uncf
,
5778 opcode_num_units_func onuf
,
5779 opcode_funcUnit_use_unit_func ouuf
,
5780 opcode_funcUnit_use_stage_func ousf
)
5783 resource_table
*rt
= (resource_table
*) xmalloc (sizeof (resource_table
));
5785 rt
->cycles
= cycles
;
5786 rt
->allocated_cycles
= cycles
;
5788 rt
->unit_num_copies
= uncf
;
5789 rt
->opcode_num_units
= onuf
;
5790 rt
->opcode_unit_use
= ouuf
;
5791 rt
->opcode_unit_stage
= ousf
;
5793 rt
->units
= (unsigned char **) xcalloc (cycles
, sizeof (unsigned char *));
5794 for (i
= 0; i
< cycles
; i
++)
5795 rt
->units
[i
] = (unsigned char *) xcalloc (nu
, sizeof (unsigned char));
5802 clear_resource_table (resource_table
*rt
)
5805 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
5806 for (j
= 0; j
< rt
->num_units
; j
++)
5807 rt
->units
[i
][j
] = 0;
5811 /* We never shrink it, just fake it into thinking so. */
5814 resize_resource_table (resource_table
*rt
, int cycles
)
5818 rt
->cycles
= cycles
;
5819 if (cycles
<= rt
->allocated_cycles
)
5822 old_cycles
= rt
->allocated_cycles
;
5823 rt
->allocated_cycles
= cycles
;
5825 rt
->units
= xrealloc (rt
->units
,
5826 rt
->allocated_cycles
* sizeof (unsigned char *));
5827 for (i
= 0; i
< old_cycles
; i
++)
5828 rt
->units
[i
] = xrealloc (rt
->units
[i
],
5829 rt
->num_units
* sizeof (unsigned char));
5830 for (i
= old_cycles
; i
< cycles
; i
++)
5831 rt
->units
[i
] = xcalloc (rt
->num_units
, sizeof (unsigned char));
5836 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5839 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5841 for (i
= 0; i
< uses
; i
++)
5843 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5844 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5845 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
5846 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
5847 if (copies_in_use
>= copies
)
5855 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5858 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5860 for (i
= 0; i
< uses
; i
++)
5862 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5863 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5864 /* Note that this allows resources to be oversubscribed. That's
5865 essential to the way the optional scheduler works.
5866 resources_available reports when a resource is over-subscribed,
5867 so it's easy to tell. */
5868 rt
->units
[stage
+ cycle
][unit
]++;
5874 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5877 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5879 for (i
= 0; i
< uses
; i
++)
5881 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5882 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5883 assert (rt
->units
[stage
+ cycle
][unit
] > 0);
5884 rt
->units
[stage
+ cycle
][unit
]--;
5889 /* Wrapper functions make parameterized resource reservation
5893 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
5895 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5901 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
5903 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5908 /* Note that this function does not check issue constraints, but
5909 solely whether the hardware is available to execute the given
5910 instructions together. It also doesn't check if the tinsns
5911 write the same state, or access the same tieports. That is
5912 checked by check_t1_t2_reads_and_writes. */
5915 resources_conflict (vliw_insn
*vinsn
)
5918 static resource_table
*rt
= NULL
;
5920 /* This is the most common case by far. Optimize it. */
5921 if (vinsn
->num_slots
== 1)
5926 xtensa_isa isa
= xtensa_default_isa
;
5927 rt
= new_resource_table
5928 (isa
, xtensa_isa_num_pipe_stages (isa
),
5929 xtensa_isa_num_funcUnits (isa
),
5930 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
5931 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
5932 opcode_funcUnit_use_unit
,
5933 opcode_funcUnit_use_stage
);
5936 clear_resource_table (rt
);
5938 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5940 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
5942 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
5949 /* finish_vinsn, emit_single_op and helper functions. */
5951 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
5952 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
5953 static void bundle_single_op (TInsn
*);
5954 static void xg_assemble_vliw_tokens (vliw_insn
*);
5957 /* We have reached the end of a bundle; emit into the frag. */
5960 finish_vinsn (vliw_insn
*vinsn
)
5967 if (find_vinsn_conflicts (vinsn
))
5969 xg_clear_vinsn (vinsn
);
5973 /* First, find a format that works. */
5974 if (vinsn
->format
== XTENSA_UNDEFINED
)
5975 vinsn
->format
= xg_find_narrowest_format (vinsn
);
5977 if (vinsn
->format
== XTENSA_UNDEFINED
)
5979 as_where (&file_name
, &line
);
5980 as_bad_where (file_name
, line
,
5981 _("couldn't find a valid instruction format"));
5982 fprintf (stderr
, _(" ops were: "));
5983 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5984 fprintf (stderr
, _(" %s;"),
5985 xtensa_opcode_name (xtensa_default_isa
,
5986 vinsn
->slots
[i
].opcode
));
5987 fprintf (stderr
, _("\n"));
5988 xg_clear_vinsn (vinsn
);
5992 if (vinsn
->num_slots
5993 != xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
))
5995 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
5996 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
5997 xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
),
5999 xg_clear_vinsn (vinsn
);
6003 if (resources_conflict (vinsn
))
6005 as_where (&file_name
, &line
);
6006 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6007 fprintf (stderr
, " ops were: ");
6008 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6009 fprintf (stderr
, " %s;",
6010 xtensa_opcode_name (xtensa_default_isa
,
6011 vinsn
->slots
[i
].opcode
));
6012 fprintf (stderr
, "\n");
6013 xg_clear_vinsn (vinsn
);
6017 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6019 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
6021 symbolS
*lit_sym
= NULL
;
6023 bfd_boolean e
= FALSE
;
6024 bfd_boolean saved_density
= density_supported
;
6026 /* We don't want to narrow ops inside multi-slot bundles. */
6027 if (vinsn
->num_slots
> 1)
6028 density_supported
= FALSE
;
6030 istack_init (&slotstack
);
6031 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
6033 vinsn
->slots
[i
].opcode
=
6034 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6036 vinsn
->slots
[i
].ntok
= 0;
6039 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
6045 density_supported
= saved_density
;
6049 xg_clear_vinsn (vinsn
);
6053 for (j
= 0; j
< slotstack
.ninsn
; j
++)
6055 TInsn
*insn
= &slotstack
.insn
[j
];
6056 if (insn
->insn_type
== ITYPE_LITERAL
)
6058 assert (lit_sym
== NULL
);
6059 lit_sym
= xg_assemble_literal (insn
);
6063 assert (insn
->insn_type
== ITYPE_INSN
);
6065 xg_resolve_literals (insn
, lit_sym
);
6066 if (j
!= slotstack
.ninsn
- 1)
6067 emit_single_op (insn
);
6071 if (vinsn
->num_slots
> 1)
6073 if (opcode_fits_format_slot
6074 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6077 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6081 bundle_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6082 if (vinsn
->format
== XTENSA_UNDEFINED
)
6083 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6085 vinsn
->slots
[i
].opcode
6086 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6089 vinsn
->slots
[i
].ntok
= 0;
6094 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6095 vinsn
->format
= XTENSA_UNDEFINED
;
6100 /* Now check resource conflicts on the modified bundle. */
6101 if (resources_conflict (vinsn
))
6103 as_where (&file_name
, &line
);
6104 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6105 fprintf (stderr
, " ops were: ");
6106 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6107 fprintf (stderr
, " %s;",
6108 xtensa_opcode_name (xtensa_default_isa
,
6109 vinsn
->slots
[i
].opcode
));
6110 fprintf (stderr
, "\n");
6111 xg_clear_vinsn (vinsn
);
6115 /* First, find a format that works. */
6116 if (vinsn
->format
== XTENSA_UNDEFINED
)
6117 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6119 xg_assemble_vliw_tokens (vinsn
);
6121 xg_clear_vinsn (vinsn
);
6125 /* Given an vliw instruction, what conflicts are there in register
6126 usage and in writes to states and queues?
6128 This function does two things:
6129 1. Reports an error when a vinsn contains illegal combinations
6130 of writes to registers states or queues.
6131 2. Marks individual tinsns as not relaxable if the combination
6132 contains antidependencies.
6134 Job 2 handles things like swap semantics in instructions that need
6135 to be relaxed. For example,
6139 normally would be relaxed to
6144 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6146 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6148 then we can't relax it into
6151 { add a0, a1, a0 ; add a2, a0, a4 ; }
6153 because the value of a0 is trashed before the second add can read it. */
6155 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6158 find_vinsn_conflicts (vliw_insn
*vinsn
)
6162 xtensa_isa isa
= xtensa_default_isa
;
6164 assert (!past_xtensa_end
);
6166 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6168 TInsn
*op1
= &vinsn
->slots
[i
];
6169 if (op1
->is_specific_opcode
)
6170 op1
->keep_wide
= TRUE
;
6172 op1
->keep_wide
= FALSE
;
6175 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6177 TInsn
*op1
= &vinsn
->slots
[i
];
6179 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6182 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6186 TInsn
*op2
= &vinsn
->slots
[j
];
6187 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6188 switch (conflict_type
)
6191 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6192 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6193 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6196 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6197 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6198 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6201 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same queue"),
6202 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6203 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6206 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile queue accesses"),
6207 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6208 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6211 /* Everything is OK. */
6214 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6215 || conflict_type
== 'a');
6222 as_bad (_("multiple branches or jumps in the same bundle"));
6230 /* Check how the state used by t1 and t2 relate.
6233 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6234 case B: no relationship between what is read and written (both could
6235 read the same reg though)
6236 case C: t1 writes a register t2 writes (a register conflict within a
6238 case D: t1 writes a state that t2 also writes
6239 case E: t1 writes a tie queue that t2 also writes
6240 case F: two volatile queue accesses
6244 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6246 xtensa_isa isa
= xtensa_default_isa
;
6247 xtensa_regfile t1_regfile
, t2_regfile
;
6249 int t1_base_reg
, t1_last_reg
;
6250 int t2_base_reg
, t2_last_reg
;
6251 char t1_inout
, t2_inout
;
6253 char conflict
= 'b';
6258 bfd_boolean t1_volatile
= FALSE
;
6259 bfd_boolean t2_volatile
= FALSE
;
6261 /* Check registers. */
6262 for (j
= 0; j
< t2
->ntok
; j
++)
6264 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6267 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6268 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6269 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6271 for (i
= 0; i
< t1
->ntok
; i
++)
6273 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6276 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6278 if (t1_regfile
!= t2_regfile
)
6281 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6282 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6284 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6285 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6287 if (t1_inout
== 'm' || t1_inout
== 'o'
6288 || t2_inout
== 'm' || t2_inout
== 'o')
6295 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6296 t1_last_reg
= (t1_base_reg
6297 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6299 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6301 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6303 if (t1_reg
!= t2_reg
)
6306 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6312 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6318 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6326 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6327 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6328 for (j
= 0; j
< t2_states
; j
++)
6330 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6331 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6332 for (i
= 0; i
< t1_states
; i
++)
6334 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6335 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6339 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6345 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6351 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6356 /* Check tieports. */
6357 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6358 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6359 for (j
= 0; j
< t2_interfaces
; j
++)
6361 xtensa_interface t2_int
6362 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6363 int t2_class
= xtensa_interface_class_id (isa
, t2_int
);
6365 t2_inout
= xtensa_interface_inout (isa
, j
);
6366 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1)
6369 for (i
= 0; i
< t1_interfaces
; i
++)
6371 xtensa_interface t1_int
6372 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6373 int t1_class
= xtensa_interface_class_id (isa
, t1_int
);
6375 t1_inout
= xtensa_interface_inout (isa
, i
);
6376 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1)
6379 if (t1_volatile
&& t2_volatile
&& (t1_class
== t2_class
))
6382 if (t1_int
!= t2_int
)
6385 if (t2_inout
== 'i' && t1_inout
== 'o')
6391 if (t1_inout
== 'i' && t2_inout
== 'o')
6397 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6406 static xtensa_format
6407 xg_find_narrowest_format (vliw_insn
*vinsn
)
6409 /* Right now we assume that the ops within the vinsn are properly
6410 ordered for the slots that the programmer wanted them in. In
6411 other words, we don't rearrange the ops in hopes of finding a
6412 better format. The scheduler handles that. */
6414 xtensa_isa isa
= xtensa_default_isa
;
6415 xtensa_format format
;
6416 vliw_insn v_copy
= *vinsn
;
6417 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6419 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6422 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6426 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6428 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6430 v_copy
.slots
[slot
].opcode
=
6431 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6432 v_copy
.slots
[slot
].ntok
= 0;
6435 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6438 else if (v_copy
.num_slots
> 1)
6441 /* Try the widened version. */
6442 if (!v_copy
.slots
[slot
].keep_wide
6443 && !v_copy
.slots
[slot
].is_specific_opcode
6444 && xg_is_single_relaxable_insn (&v_copy
.slots
[slot
],
6446 && opcode_fits_format_slot (widened
.opcode
,
6449 v_copy
.slots
[slot
] = widened
;
6454 if (fit
== v_copy
.num_slots
)
6457 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6458 vinsn
->format
= format
;
6464 if (format
== xtensa_isa_num_formats (isa
))
6465 return XTENSA_UNDEFINED
;
6471 /* Return the additional space needed in a frag
6472 for possible relaxations of any ops in a VLIW insn.
6473 Also fill out the relaxations that might be required of
6474 each tinsn in the vinsn. */
6477 relaxation_requirements (vliw_insn
*vinsn
)
6479 int extra_space
= 0;
6482 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6484 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6485 if (!tinsn_has_symbolic_operands (tinsn
))
6487 /* A narrow instruction could be widened later to help
6488 alignment issues. */
6489 if (xg_is_single_relaxable_insn (tinsn
, 0, TRUE
)
6490 && !tinsn
->is_specific_opcode
6491 && vinsn
->num_slots
== 1)
6493 /* Difference in bytes between narrow and wide insns... */
6495 tinsn
->subtype
= RELAX_NARROW
;
6496 tinsn
->record_fix
= TRUE
;
6501 tinsn
->record_fix
= FALSE
;
6502 /* No extra_space needed. */
6507 if (workaround_b_j_loop_end
6508 && tinsn
->opcode
== xtensa_jx_opcode
6509 && use_transform ())
6511 /* Add 2 of these. */
6512 extra_space
+= 3; /* for the nop size */
6513 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6516 /* Need to assemble it with space for the relocation. */
6517 if (xg_is_relaxable_insn (tinsn
, 0)
6518 && !tinsn
->is_specific_opcode
)
6520 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6521 int max_literal_size
=
6522 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6524 tinsn
->literal_space
= max_literal_size
;
6526 tinsn
->subtype
= RELAX_IMMED
;
6527 tinsn
->record_fix
= FALSE
;
6528 extra_space
+= max_size
;
6532 tinsn
->record_fix
= TRUE
;
6533 /* No extra space needed. */
6542 bundle_single_op (TInsn
*orig_insn
)
6544 xtensa_isa isa
= xtensa_default_isa
;
6549 v
.format
= op_placement_table
[orig_insn
->opcode
].narrowest
;
6550 assert (v
.format
!= XTENSA_UNDEFINED
);
6551 v
.num_slots
= xtensa_format_num_slots (isa
, v
.format
);
6554 !opcode_fits_format_slot (orig_insn
->opcode
, v
.format
, slot
);
6557 v
.slots
[slot
].opcode
=
6558 xtensa_format_slot_nop_opcode (isa
, v
.format
, slot
);
6559 v
.slots
[slot
].ntok
= 0;
6560 v
.slots
[slot
].insn_type
= ITYPE_INSN
;
6563 v
.slots
[slot
] = *orig_insn
;
6566 for ( ; slot
< v
.num_slots
; slot
++)
6568 v
.slots
[slot
].opcode
=
6569 xtensa_format_slot_nop_opcode (isa
, v
.format
, slot
);
6570 v
.slots
[slot
].ntok
= 0;
6571 v
.slots
[slot
].insn_type
= ITYPE_INSN
;
6580 emit_single_op (TInsn
*orig_insn
)
6583 IStack istack
; /* put instructions into here */
6584 symbolS
*lit_sym
= NULL
;
6585 symbolS
*label_sym
= NULL
;
6587 istack_init (&istack
);
6589 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6590 Because the scheduling and bundling characteristics of movi and
6591 l32r or const16 are so different, we can do much better if we relax
6592 it prior to scheduling and bundling, rather than after. */
6593 if ((orig_insn
->opcode
== xtensa_movi_opcode
6594 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
6595 && !cur_vinsn
.inside_bundle
6596 && (orig_insn
->tok
[1].X_op
== O_symbol
6597 || orig_insn
->tok
[1].X_op
== O_pltrel
))
6598 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
6600 if (xg_expand_assembly_insn (&istack
, orig_insn
))
6603 for (i
= 0; i
< istack
.ninsn
; i
++)
6605 TInsn
*insn
= &istack
.insn
[i
];
6606 switch (insn
->insn_type
)
6609 assert (lit_sym
== NULL
);
6610 lit_sym
= xg_assemble_literal (insn
);
6614 static int relaxed_sym_idx
= 0;
6615 char *label
= xmalloc (strlen (FAKE_LABEL_NAME
) + 12);
6616 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
6618 assert (label_sym
== NULL
);
6619 label_sym
= symbol_find_or_make (label
);
6626 xg_resolve_literals (insn
, lit_sym
);
6628 xg_resolve_labels (insn
, label_sym
);
6629 bundle_single_op (insn
);
6641 total_frag_text_expansion (fragS
*fragP
)
6644 int total_expansion
= 0;
6646 for (slot
= 0; slot
< MAX_SLOTS
; slot
++)
6647 total_expansion
+= fragP
->tc_frag_data
.text_expansion
[slot
];
6649 return total_expansion
;
6653 /* Emit a vliw instruction to the current fragment. */
6656 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
6658 bfd_boolean finish_frag
= FALSE
;
6659 bfd_boolean is_jump
= FALSE
;
6660 bfd_boolean is_branch
= FALSE
;
6661 xtensa_isa isa
= xtensa_default_isa
;
6667 struct dwarf2_line_info best_loc
;
6669 best_loc
.line
= INT_MAX
;
6671 if (generating_literals
)
6673 static int reported
= 0;
6675 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
6676 _("cannot assemble into a literal fragment"));
6683 if (frag_now_fix () != 0
6684 && (! frag_now
->tc_frag_data
.is_insn
6685 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6686 || !use_transform () != frag_now
->tc_frag_data
.is_no_transform
6687 || (directive_state
[directive_longcalls
]
6688 != frag_now
->tc_frag_data
.use_longcalls
)
6689 || (directive_state
[directive_absolute_literals
]
6690 != frag_now
->tc_frag_data
.use_absolute_literals
)))
6692 frag_wane (frag_now
);
6694 xtensa_set_frag_assembly_state (frag_now
);
6697 if (workaround_a0_b_retw
6698 && vinsn
->num_slots
== 1
6699 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
6700 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
6701 && use_transform ())
6703 has_a0_b_retw
= TRUE
;
6705 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
6706 After the first assembly pass we will check all of them and
6707 add a nop if needed. */
6708 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6709 frag_var (rs_machine_dependent
, 4, 4,
6710 RELAX_ADD_NOP_IF_A0_B_RETW
,
6711 frag_now
->fr_symbol
,
6712 frag_now
->fr_offset
,
6714 xtensa_set_frag_assembly_state (frag_now
);
6715 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6716 frag_var (rs_machine_dependent
, 4, 4,
6717 RELAX_ADD_NOP_IF_A0_B_RETW
,
6718 frag_now
->fr_symbol
,
6719 frag_now
->fr_offset
,
6721 xtensa_set_frag_assembly_state (frag_now
);
6724 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6726 /* See if the instruction implies an aligned section. */
6727 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[i
].opcode
) == 1)
6728 record_alignment (now_seg
, 2);
6730 /* Also determine the best line number for debug info. */
6731 best_loc
= vinsn
->slots
[i
].loc
.line
< best_loc
.line
6732 ? vinsn
->slots
[i
].loc
: best_loc
;
6735 /* Special cases for instructions that force an alignment... */
6736 /* None of these opcodes are bundle-able. */
6737 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
6741 xtensa_set_frag_assembly_state (frag_now
);
6742 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6744 max_fill
= get_text_align_max_fill_size
6745 (get_text_align_power (xtensa_fetch_width
),
6746 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
6748 if (use_transform ())
6749 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
6750 RELAX_ALIGN_NEXT_OPCODE
,
6751 frag_now
->fr_symbol
,
6752 frag_now
->fr_offset
,
6755 frag_var (rs_machine_dependent
, 0, 0,
6756 RELAX_CHECK_ALIGN_NEXT_OPCODE
, 0, 0, NULL
);
6757 xtensa_set_frag_assembly_state (frag_now
);
6759 xtensa_move_labels (frag_now
, 0, FALSE
);
6762 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
6763 && !vinsn
->slots
[0].is_specific_opcode
)
6765 xtensa_mark_literal_pool_location ();
6766 xtensa_move_labels (frag_now
, 0, TRUE
);
6767 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
6770 if (vinsn
->num_slots
== 1)
6772 if (workaround_a0_b_retw
&& use_transform ())
6773 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
6774 is_register_writer (&vinsn
->slots
[0], "a", 0));
6776 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
6777 is_bad_loopend_opcode (&vinsn
->slots
[0]));
6780 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
6782 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
6784 extra_space
= relaxation_requirements (vinsn
);
6786 /* vinsn_to_insnbuf will produce the error. */
6787 if (vinsn
->format
!= XTENSA_UNDEFINED
)
6789 f
= frag_more (insn_size
+ extra_space
);
6790 xtensa_set_frag_assembly_state (frag_now
);
6791 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6794 vinsn_to_insnbuf (vinsn
, f
, frag_now
, TRUE
);
6795 if (vinsn
->format
== XTENSA_UNDEFINED
)
6798 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, (unsigned char *) f
, 0);
6800 xtensa_dwarf2_emit_insn (insn_size
+ extra_space
, &best_loc
);
6802 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6804 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6805 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
6806 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
6807 frag_now
->tc_frag_data
.slot_sub_symbols
[slot
] = tinsn
->sub_symbol
;
6808 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
6809 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
6810 if (tinsn
->literal_space
!= 0)
6811 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
6813 if (tinsn
->subtype
== RELAX_NARROW
)
6814 assert (vinsn
->num_slots
== 1);
6815 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
6817 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
6820 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->record_fix
6821 || tinsn
->offset
|| tinsn
->literal_frag
|| is_jump
|| is_branch
)
6825 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6826 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
6830 frag_variant (rs_machine_dependent
,
6831 extra_space
, extra_space
, RELAX_SLOTS
,
6832 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
6833 xtensa_set_frag_assembly_state (frag_now
);
6836 /* Special cases for loops:
6837 close_loop_end should be inserted AFTER short_loop.
6838 Make sure that CLOSE loops are processed BEFORE short_loops
6839 when converting them. */
6841 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
6842 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
)
6843 && !vinsn
->slots
[0].is_specific_opcode
)
6845 if (workaround_short_loop
&& use_transform ())
6847 maybe_has_short_loop
= TRUE
;
6848 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6849 frag_var (rs_machine_dependent
, 4, 4,
6850 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6851 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6852 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6853 frag_var (rs_machine_dependent
, 4, 4,
6854 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6855 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6858 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
6859 loop at least 12 bytes away from another loop's end. */
6860 if (workaround_close_loop_end
&& use_transform ())
6862 maybe_has_close_loop_end
= TRUE
;
6863 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6864 frag_var (rs_machine_dependent
, 12, 12,
6865 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
6866 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6870 if (use_transform ())
6874 assert (finish_frag
);
6875 frag_var (rs_machine_dependent
,
6876 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6878 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6879 xtensa_set_frag_assembly_state (frag_now
);
6881 else if (is_branch
&& do_align_targets ())
6883 assert (finish_frag
);
6884 frag_var (rs_machine_dependent
,
6885 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6886 RELAX_MAYBE_UNREACHABLE
,
6887 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6888 xtensa_set_frag_assembly_state (frag_now
);
6889 frag_var (rs_machine_dependent
,
6891 RELAX_MAYBE_DESIRE_ALIGN
,
6892 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6893 xtensa_set_frag_assembly_state (frag_now
);
6897 /* Now, if the original opcode was a call... */
6898 if (do_align_targets ()
6899 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
6901 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
6902 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6903 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
6904 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6905 xtensa_set_frag_assembly_state (frag_now
);
6908 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6910 frag_wane (frag_now
);
6912 xtensa_set_frag_assembly_state (frag_now
);
6917 /* xtensa_end and helper functions. */
6919 static void xtensa_cleanup_align_frags (void);
6920 static void xtensa_fix_target_frags (void);
6921 static void xtensa_mark_narrow_branches (void);
6922 static void xtensa_mark_zcl_first_insns (void);
6923 static void xtensa_fix_a0_b_retw_frags (void);
6924 static void xtensa_fix_b_j_loop_end_frags (void);
6925 static void xtensa_fix_close_loop_end_frags (void);
6926 static void xtensa_fix_short_loop_frags (void);
6927 static void xtensa_sanity_check (void);
6932 directive_balance ();
6933 xtensa_flush_pending_output ();
6935 past_xtensa_end
= TRUE
;
6937 xtensa_move_literals ();
6939 xtensa_reorder_segments ();
6940 xtensa_cleanup_align_frags ();
6941 xtensa_fix_target_frags ();
6942 if (workaround_a0_b_retw
&& has_a0_b_retw
)
6943 xtensa_fix_a0_b_retw_frags ();
6944 if (workaround_b_j_loop_end
)
6945 xtensa_fix_b_j_loop_end_frags ();
6947 /* "close_loop_end" should be processed BEFORE "short_loop". */
6948 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
6949 xtensa_fix_close_loop_end_frags ();
6951 if (workaround_short_loop
&& maybe_has_short_loop
)
6952 xtensa_fix_short_loop_frags ();
6953 xtensa_mark_narrow_branches ();
6954 xtensa_mark_zcl_first_insns ();
6956 xtensa_sanity_check ();
6961 xtensa_cleanup_align_frags (void)
6965 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
6968 /* Walk over all of the fragments in a subsection. */
6969 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
6971 if ((fragP
->fr_type
== rs_align
6972 || fragP
->fr_type
== rs_align_code
6973 || (fragP
->fr_type
== rs_machine_dependent
6974 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
6975 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
6976 && fragP
->fr_fix
== 0)
6978 fragS
*next
= fragP
->fr_next
;
6981 && next
->fr_fix
== 0
6982 && next
->fr_type
== rs_machine_dependent
6983 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
6986 next
= next
->fr_next
;
6989 /* If we don't widen branch targets, then they
6990 will be easier to align. */
6991 if (fragP
->tc_frag_data
.is_branch_target
6992 && fragP
->fr_opcode
== fragP
->fr_literal
6993 && fragP
->fr_type
== rs_machine_dependent
6994 && fragP
->fr_subtype
== RELAX_SLOTS
6995 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
6997 if (fragP
->fr_type
== rs_machine_dependent
6998 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
6999 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
7005 /* Re-process all of the fragments looking to convert all of the
7006 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
7007 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7008 Otherwise, convert to a .fill 0. */
7011 xtensa_fix_target_frags (void)
7015 /* When this routine is called, all of the subsections are still intact
7016 so we walk over subsections instead of sections. */
7017 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7021 /* Walk over all of the fragments in a subsection. */
7022 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7024 if (fragP
->fr_type
== rs_machine_dependent
7025 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7027 if (next_frag_is_branch_target (fragP
))
7028 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7037 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
7040 xtensa_mark_narrow_branches (void)
7044 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7047 /* Walk over all of the fragments in a subsection. */
7048 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7050 if (fragP
->fr_type
== rs_machine_dependent
7051 && fragP
->fr_subtype
== RELAX_SLOTS
7052 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7055 const expressionS
*expr
;
7058 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7059 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
7061 expr
= &vinsn
.slots
[0].tok
[1];
7062 symbolP
= expr
->X_add_symbol
;
7064 if (vinsn
.num_slots
== 1
7065 && xtensa_opcode_is_branch (xtensa_default_isa
,
7066 vinsn
.slots
[0].opcode
)
7067 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
7068 && is_narrow_branch_guaranteed_in_range (fragP
,
7071 fragP
->fr_subtype
= RELAX_SLOTS
;
7072 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
7080 /* A branch is typically widened only when its target is out of
7081 range. However, we would like to widen them to align a subsequent
7082 branch target when possible.
7084 Because the branch relaxation code is so convoluted, the optimal solution
7085 (combining the two cases) is difficult to get right in all circumstances.
7086 We therefore go with an "almost as good" solution, where we only
7087 use for alignment narrow branches that definitely will not expand to a
7088 jump and a branch. These functions find and mark these cases. */
7090 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
7091 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7092 We start counting beginning with the frag after the 2-byte branch, so the
7093 maximum offset is (4 - 2) + 63 = 65. */
7094 #define MAX_IMMED6 65
7096 static offsetT
unrelaxed_frag_max_size (fragS
*);
7099 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
7101 const expressionS
*expr
= &tinsn
->tok
[1];
7102 symbolS
*symbolP
= expr
->X_add_symbol
;
7103 fragS
*target_frag
= symbol_get_frag (symbolP
);
7104 offsetT max_distance
= expr
->X_add_number
;
7105 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
7106 if (is_branch_jmp_to_next (tinsn
, fragP
))
7109 /* The branch doesn't branch over it's own frag,
7110 but over the subsequent ones. */
7111 fragP
= fragP
->fr_next
;
7112 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
7114 max_distance
+= unrelaxed_frag_max_size (fragP
);
7115 fragP
= fragP
->fr_next
;
7117 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
7124 xtensa_mark_zcl_first_insns (void)
7128 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7131 /* Walk over all of the fragments in a subsection. */
7132 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7134 if (fragP
->fr_type
== rs_machine_dependent
7135 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7136 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7138 /* Find the loop frag. */
7139 fragS
*targ_frag
= next_non_empty_frag (fragP
);
7140 /* Find the first insn frag. */
7141 targ_frag
= next_non_empty_frag (targ_frag
);
7143 /* Of course, sometimes (mostly for toy test cases) a
7144 zero-cost loop instruction is the last in a section. */
7146 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
7147 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
7155 /* Re-process all of the fragments looking to convert all of the
7156 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7157 conditional branch or a retw/retw.n, convert this frag to one that
7158 will generate a NOP. In any case close it off with a .fill 0. */
7160 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
7163 xtensa_fix_a0_b_retw_frags (void)
7167 /* When this routine is called, all of the subsections are still intact
7168 so we walk over subsections instead of sections. */
7169 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7173 /* Walk over all of the fragments in a subsection. */
7174 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7176 if (fragP
->fr_type
== rs_machine_dependent
7177 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
7179 if (next_instrs_are_b_retw (fragP
))
7181 if (fragP
->tc_frag_data
.is_no_transform
)
7182 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7184 relax_frag_add_nop (fragP
);
7194 next_instrs_are_b_retw (fragS
*fragP
)
7196 xtensa_opcode opcode
;
7198 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
7199 static xtensa_insnbuf insnbuf
= NULL
;
7200 static xtensa_insnbuf slotbuf
= NULL
;
7201 xtensa_isa isa
= xtensa_default_isa
;
7204 bfd_boolean branch_seen
= FALSE
;
7208 insnbuf
= xtensa_insnbuf_alloc (isa
);
7209 slotbuf
= xtensa_insnbuf_alloc (isa
);
7212 if (next_fragP
== NULL
)
7215 /* Check for the conditional branch. */
7216 xtensa_insnbuf_from_chars
7217 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7218 fmt
= xtensa_format_decode (isa
, insnbuf
);
7219 if (fmt
== XTENSA_UNDEFINED
)
7222 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7224 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
7225 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
7227 branch_seen
= (branch_seen
7228 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
7234 offset
+= xtensa_format_length (isa
, fmt
);
7235 if (offset
== next_fragP
->fr_fix
)
7237 next_fragP
= next_non_empty_frag (next_fragP
);
7241 if (next_fragP
== NULL
)
7244 /* Check for the retw/retw.n. */
7245 xtensa_insnbuf_from_chars
7246 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7247 fmt
= xtensa_format_decode (isa
, insnbuf
);
7249 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
7250 have no problems. */
7251 if (fmt
== XTENSA_UNDEFINED
7252 || xtensa_format_num_slots (isa
, fmt
) != 1)
7255 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
7256 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
7258 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
7265 /* Re-process all of the fragments looking to convert all of the
7266 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
7267 loop end label, convert this frag to one that will generate a NOP.
7268 In any case close it off with a .fill 0. */
7270 static bfd_boolean
next_instr_is_loop_end (fragS
*);
7273 xtensa_fix_b_j_loop_end_frags (void)
7277 /* When this routine is called, all of the subsections are still intact
7278 so we walk over subsections instead of sections. */
7279 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7283 /* Walk over all of the fragments in a subsection. */
7284 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7286 if (fragP
->fr_type
== rs_machine_dependent
7287 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
7289 if (next_instr_is_loop_end (fragP
))
7291 if (fragP
->tc_frag_data
.is_no_transform
)
7292 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
7294 relax_frag_add_nop (fragP
);
7304 next_instr_is_loop_end (fragS
*fragP
)
7306 const fragS
*next_fragP
;
7308 if (next_frag_is_loop_target (fragP
))
7311 next_fragP
= next_non_empty_frag (fragP
);
7312 if (next_fragP
== NULL
)
7315 if (!next_frag_is_loop_target (next_fragP
))
7318 /* If the size is >= 3 then there is more than one instruction here.
7319 The hardware bug will not fire. */
7320 if (next_fragP
->fr_fix
> 3)
7327 /* Re-process all of the fragments looking to convert all of the
7328 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
7329 not MY loop's loop end within 12 bytes, add enough nops here to
7330 make it at least 12 bytes away. In any case close it off with a
7333 static offsetT min_bytes_to_other_loop_end
7334 (fragS
*, fragS
*, offsetT
, offsetT
);
7337 xtensa_fix_close_loop_end_frags (void)
7341 /* When this routine is called, all of the subsections are still intact
7342 so we walk over subsections instead of sections. */
7343 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7347 fragS
*current_target
= NULL
;
7348 offsetT current_offset
= 0;
7350 /* Walk over all of the fragments in a subsection. */
7351 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7353 if (fragP
->fr_type
== rs_machine_dependent
7354 && ((fragP
->fr_subtype
== RELAX_IMMED
)
7355 || ((fragP
->fr_subtype
== RELAX_SLOTS
)
7356 && (fragP
->tc_frag_data
.slot_subtypes
[0]
7359 /* Read it. If the instruction is a loop, get the target. */
7361 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7362 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7363 t_insn
.opcode
) == 1)
7365 /* Get the current fragment target. */
7366 if (fragP
->tc_frag_data
.slot_symbols
[0])
7368 symbolS
*sym
= fragP
->tc_frag_data
.slot_symbols
[0];
7369 current_target
= symbol_get_frag (sym
);
7370 current_offset
= fragP
->fr_offset
;
7376 && fragP
->fr_type
== rs_machine_dependent
7377 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
7380 int bytes_added
= 0;
7382 #define REQUIRED_LOOP_DIVIDING_BYTES 12
7383 /* Max out at 12. */
7384 min_bytes
= min_bytes_to_other_loop_end
7385 (fragP
->fr_next
, current_target
, current_offset
,
7386 REQUIRED_LOOP_DIVIDING_BYTES
);
7388 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
7390 if (fragP
->tc_frag_data
.is_no_transform
)
7391 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
7394 while (min_bytes
+ bytes_added
7395 < REQUIRED_LOOP_DIVIDING_BYTES
)
7399 if (fragP
->fr_var
< length
)
7400 as_fatal (_("fr_var %lu < length %d"),
7401 (long) fragP
->fr_var
, length
);
7404 assemble_nop (length
,
7405 fragP
->fr_literal
+ fragP
->fr_fix
);
7406 fragP
->fr_fix
+= length
;
7407 fragP
->fr_var
-= length
;
7409 bytes_added
+= length
;
7415 assert (fragP
->fr_type
!= rs_machine_dependent
7416 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
7422 static offsetT
unrelaxed_frag_min_size (fragS
*);
7425 min_bytes_to_other_loop_end (fragS
*fragP
,
7426 fragS
*current_target
,
7427 offsetT current_offset
,
7431 fragS
*current_fragP
;
7433 for (current_fragP
= fragP
;
7435 current_fragP
= current_fragP
->fr_next
)
7437 if (current_fragP
->tc_frag_data
.is_loop_target
7438 && current_fragP
!= current_target
)
7439 return offset
+ current_offset
;
7441 offset
+= unrelaxed_frag_min_size (current_fragP
);
7443 if (offset
+ current_offset
>= max_size
)
7451 unrelaxed_frag_min_size (fragS
*fragP
)
7453 offsetT size
= fragP
->fr_fix
;
7455 /* Add fill size. */
7456 if (fragP
->fr_type
== rs_fill
)
7457 size
+= fragP
->fr_offset
;
7464 unrelaxed_frag_max_size (fragS
*fragP
)
7466 offsetT size
= fragP
->fr_fix
;
7467 switch (fragP
->fr_type
)
7470 /* Empty frags created by the obstack allocation scheme
7471 end up with type 0. */
7476 size
+= fragP
->fr_offset
;
7484 /* No further adjustments needed. */
7486 case rs_machine_dependent
:
7487 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
7488 size
+= fragP
->fr_var
;
7491 /* We had darn well better know how big it is. */
7500 /* Re-process all of the fragments looking to convert all
7501 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
7504 1) the instruction size count to the loop end label
7505 is too short (<= 2 instructions),
7506 2) loop has a jump or branch in it
7509 1) workaround_all_short_loops is TRUE
7510 2) The generating loop was a 'loopgtz' or 'loopnez'
7511 3) the instruction size count to the loop end label is too short
7513 then convert this frag (and maybe the next one) to generate a NOP.
7514 In any case close it off with a .fill 0. */
7516 static int count_insns_to_loop_end (fragS
*, bfd_boolean
, int);
7517 static bfd_boolean
branch_before_loop_end (fragS
*);
7520 xtensa_fix_short_loop_frags (void)
7524 /* When this routine is called, all of the subsections are still intact
7525 so we walk over subsections instead of sections. */
7526 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7529 fragS
*current_target
= NULL
;
7530 offsetT current_offset
= 0;
7531 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
7533 /* Walk over all of the fragments in a subsection. */
7534 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7536 /* Check on the current loop. */
7537 if (fragP
->fr_type
== rs_machine_dependent
7538 && ((fragP
->fr_subtype
== RELAX_IMMED
)
7539 || ((fragP
->fr_subtype
== RELAX_SLOTS
)
7540 && (fragP
->tc_frag_data
.slot_subtypes
[0]
7545 /* Read it. If the instruction is a loop, get the target. */
7546 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7547 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7548 t_insn
.opcode
) == 1)
7550 /* Get the current fragment target. */
7551 if (fragP
->tc_frag_data
.slot_symbols
[0])
7553 symbolS
*sym
= fragP
->tc_frag_data
.slot_symbols
[0];
7554 current_target
= symbol_get_frag (sym
);
7555 current_offset
= fragP
->fr_offset
;
7556 current_opcode
= t_insn
.opcode
;
7561 if (fragP
->fr_type
== rs_machine_dependent
7562 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7564 if (count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3) < 3
7565 && (branch_before_loop_end (fragP
->fr_next
)
7566 || (workaround_all_short_loops
7567 && current_opcode
!= XTENSA_UNDEFINED
7568 && current_opcode
!= xtensa_loop_opcode
)))
7570 if (fragP
->tc_frag_data
.is_no_transform
)
7571 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
7573 relax_frag_add_nop (fragP
);
7582 static int unrelaxed_frag_min_insn_count (fragS
*);
7585 count_insns_to_loop_end (fragS
*base_fragP
,
7586 bfd_boolean count_relax_add
,
7589 fragS
*fragP
= NULL
;
7594 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
7596 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
7597 if (insn_count
>= max_count
)
7600 if (count_relax_add
)
7602 if (fragP
->fr_type
== rs_machine_dependent
7603 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7605 /* In order to add the appropriate number of
7606 NOPs, we count an instruction for downstream
7609 if (insn_count
>= max_count
)
7619 unrelaxed_frag_min_insn_count (fragS
*fragP
)
7621 xtensa_isa isa
= xtensa_default_isa
;
7622 static xtensa_insnbuf insnbuf
= NULL
;
7626 if (!fragP
->tc_frag_data
.is_insn
)
7630 insnbuf
= xtensa_insnbuf_alloc (isa
);
7632 /* Decode the fixed instructions. */
7633 while (offset
< fragP
->fr_fix
)
7637 xtensa_insnbuf_from_chars
7638 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7639 fmt
= xtensa_format_decode (isa
, insnbuf
);
7641 if (fmt
== XTENSA_UNDEFINED
)
7643 as_fatal (_("undecodable instruction in instruction frag"));
7646 offset
+= xtensa_format_length (isa
, fmt
);
7654 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
7657 branch_before_loop_end (fragS
*base_fragP
)
7661 for (fragP
= base_fragP
;
7662 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
7663 fragP
= fragP
->fr_next
)
7665 if (unrelaxed_frag_has_b_j (fragP
))
7673 unrelaxed_frag_has_b_j (fragS
*fragP
)
7675 static xtensa_insnbuf insnbuf
= NULL
;
7676 xtensa_isa isa
= xtensa_default_isa
;
7679 if (!fragP
->tc_frag_data
.is_insn
)
7683 insnbuf
= xtensa_insnbuf_alloc (isa
);
7685 /* Decode the fixed instructions. */
7686 while (offset
< fragP
->fr_fix
)
7691 xtensa_insnbuf_from_chars
7692 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7693 fmt
= xtensa_format_decode (isa
, insnbuf
);
7694 if (fmt
== XTENSA_UNDEFINED
)
7697 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7699 xtensa_opcode opcode
=
7700 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
7701 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
7702 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
7705 offset
+= xtensa_format_length (isa
, fmt
);
7711 /* Checks to be made after initial assembly but before relaxation. */
7713 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
7714 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
7717 xtensa_sanity_check (void)
7724 as_where (&file_name
, &line
);
7725 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7729 /* Walk over all of the fragments in a subsection. */
7730 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7732 /* Currently we only check for empty loops here. */
7733 if (fragP
->fr_type
== rs_machine_dependent
7734 && fragP
->fr_subtype
== RELAX_IMMED
)
7736 static xtensa_insnbuf insnbuf
= NULL
;
7739 if (fragP
->fr_opcode
!= NULL
)
7742 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7743 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7744 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
7746 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7747 t_insn
.opcode
) == 1)
7749 if (is_empty_loop (&t_insn
, fragP
))
7751 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7752 as_bad (_("invalid empty loop"));
7754 if (!is_local_forward_loop (&t_insn
, fragP
))
7756 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7757 as_bad (_("loop target does not follow "
7758 "loop instruction in section"));
7765 new_logical_line (file_name
, line
);
7769 #define LOOP_IMMED_OPN 1
7771 /* Return TRUE if the loop target is the next non-zero fragment. */
7774 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
7776 const expressionS
*expr
;
7780 if (insn
->insn_type
!= ITYPE_INSN
)
7783 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
7786 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7789 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7791 if (expr
->X_op
!= O_symbol
)
7794 symbolP
= expr
->X_add_symbol
;
7798 if (symbol_get_frag (symbolP
) == NULL
)
7801 if (S_GET_VALUE (symbolP
) != 0)
7804 /* Walk through the zero-size fragments from this one. If we find
7805 the target fragment, then this is a zero-size loop. */
7807 for (next_fragP
= fragP
->fr_next
;
7809 next_fragP
= next_fragP
->fr_next
)
7811 if (next_fragP
== symbol_get_frag (symbolP
))
7813 if (next_fragP
->fr_fix
!= 0)
7821 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
7823 const expressionS
*expr
;
7827 if (insn
->insn_type
!= ITYPE_INSN
)
7830 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) == 0)
7833 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7836 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7838 if (expr
->X_op
!= O_symbol
)
7841 symbolP
= expr
->X_add_symbol
;
7845 if (symbol_get_frag (symbolP
) == NULL
)
7848 /* Walk through fragments until we find the target.
7849 If we do not find the target, then this is an invalid loop. */
7851 for (next_fragP
= fragP
->fr_next
;
7853 next_fragP
= next_fragP
->fr_next
)
7855 if (next_fragP
== symbol_get_frag (symbolP
))
7863 /* Alignment Functions. */
7866 get_text_align_power (unsigned target_size
)
7871 assert (target_size
<= INT_MAX
);
7872 while (target_size
> power
)
7882 get_text_align_max_fill_size (int align_pow
,
7883 bfd_boolean use_nops
,
7884 bfd_boolean use_no_density
)
7887 return (1 << align_pow
);
7889 return 3 * (1 << align_pow
);
7891 return 1 + (1 << align_pow
);
7895 /* Calculate the minimum bytes of fill needed at "address" to align a
7896 target instruction of size "target_size" so that it does not cross a
7897 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE,
7898 the fill can be an arbitrary number of bytes. Otherwise, the space must
7899 be filled by NOP instructions. */
7902 get_text_align_fill_size (addressT address
,
7905 bfd_boolean use_nops
,
7906 bfd_boolean use_no_density
)
7908 addressT alignment
, fill
, fill_limit
, fill_step
;
7909 bfd_boolean skip_one
= FALSE
;
7911 alignment
= (1 << align_pow
);
7912 assert (target_size
> 0 && alignment
>= (addressT
) target_size
);
7916 fill_limit
= alignment
;
7919 else if (!use_no_density
)
7921 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */
7922 fill_limit
= alignment
* 2;
7928 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */
7929 fill_limit
= alignment
* 3;
7933 /* Try all fill sizes until finding one that works. */
7934 for (fill
= 0; fill
< fill_limit
; fill
+= fill_step
)
7936 if (skip_one
&& fill
== 1)
7938 if ((address
+ fill
) >> align_pow
7939 == (address
+ fill
+ target_size
- 1) >> align_pow
)
7948 branch_align_power (segT sec
)
7950 /* If the Xtensa processor has a fetch width of 8 bytes, and the section
7951 is aligned to at least an 8-byte boundary, then a branch target need
7952 only fit within an 8-byte aligned block of memory to avoid a stall.
7953 Otherwise, try to fit branch targets within 4-byte aligned blocks
7954 (which may be insufficient, e.g., if the section has no alignment, but
7955 it's good enough). */
7956 if (xtensa_fetch_width
== 8)
7958 if (get_recorded_alignment (sec
) >= 3)
7962 assert (xtensa_fetch_width
== 4);
7968 /* This will assert if it is not possible. */
7971 get_text_align_nop_count (offsetT fill_size
, bfd_boolean use_no_density
)
7977 assert (fill_size
% 3 == 0);
7978 return (fill_size
/ 3);
7981 assert (fill_size
!= 1); /* Bad argument. */
7983 while (fill_size
> 1)
7986 if (fill_size
== 2 || fill_size
== 4)
7988 fill_size
-= insn_size
;
7991 assert (fill_size
!= 1); /* Bad algorithm. */
7997 get_text_align_nth_nop_size (offsetT fill_size
,
7999 bfd_boolean use_no_density
)
8006 assert (fill_size
!= 1); /* Bad argument. */
8008 while (fill_size
> 1)
8011 if (fill_size
== 2 || fill_size
== 4)
8013 fill_size
-= insn_size
;
8023 /* For the given fragment, find the appropriate address
8024 for it to begin at if we are using NOPs to align it. */
8027 get_noop_aligned_address (fragS
*fragP
, addressT address
)
8029 /* The rule is: get next fragment's FIRST instruction. Find
8030 the smallest number of bytes that need to be added to
8031 ensure that the next fragment's FIRST instruction will fit
8034 E.G., 2 bytes : 0, 1, 2 mod 4
8037 If the FIRST instruction MIGHT be relaxed,
8038 assume that it will become a 3-byte instruction.
8040 Note again here that LOOP instructions are not bundleable,
8041 and this relaxation only applies to LOOP opcodes. */
8044 int first_insn_size
;
8046 addressT pre_opcode_bytes
;
8049 xtensa_opcode opcode
;
8050 bfd_boolean is_loop
;
8052 assert (fragP
->fr_type
== rs_machine_dependent
);
8053 assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
8055 /* Find the loop frag. */
8056 first_insn
= next_non_empty_frag (fragP
);
8057 /* Now find the first insn frag. */
8058 first_insn
= next_non_empty_frag (first_insn
);
8060 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
8062 loop_insn_size
= xg_get_single_size (opcode
);
8064 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
8065 pre_opcode_bytes
+= loop_insn_size
;
8067 /* For loops, the alignment depends on the size of the
8068 instruction following the loop, not the LOOP instruction. */
8070 if (first_insn
== NULL
)
8073 assert (first_insn
->tc_frag_data
.is_first_loop_insn
);
8075 first_insn_size
= frag_format_size (first_insn
);
8077 if (first_insn_size
== 2 || first_insn_size
== XTENSA_UNDEFINED
)
8078 first_insn_size
= 3; /* ISA specifies this */
8080 /* If it was 8, then we'll need a larger alignment for the section. */
8081 align_power
= get_text_align_power (first_insn_size
);
8082 record_alignment (now_seg
, align_power
);
8084 fill_size
= get_text_align_fill_size
8085 (address
+ pre_opcode_bytes
, align_power
, first_insn_size
, TRUE
,
8086 fragP
->tc_frag_data
.is_no_density
);
8088 return address
+ fill_size
;
8092 /* 3 mechanisms for relaxing an alignment:
8094 Align to a power of 2.
8095 Align so the next fragment's instruction does not cross a word boundary.
8096 Align the current instruction so that if the next instruction
8097 were 3 bytes, it would not cross a word boundary.
8101 zeros - This is easy; always insert zeros.
8102 nops - 3-byte and 2-byte instructions
8106 >=5 : 3-byte instruction + fn (n-3)
8107 widening - widen previous instructions. */
8110 get_aligned_diff (fragS
*fragP
, addressT address
, offsetT
*max_diff
)
8112 addressT target_address
, loop_insn_offset
;
8114 xtensa_opcode loop_opcode
;
8115 bfd_boolean is_loop
;
8118 offsetT branch_align
;
8120 assert (fragP
->fr_type
== rs_machine_dependent
);
8121 switch (fragP
->fr_subtype
)
8123 case RELAX_DESIRE_ALIGN
:
8124 target_size
= next_frag_format_size (fragP
);
8125 if (target_size
== XTENSA_UNDEFINED
)
8127 align_power
= branch_align_power (now_seg
);
8128 branch_align
= 1 << align_power
;
8129 /* Don't count on the section alignment being as large as the target. */
8130 if (target_size
> branch_align
)
8131 target_size
= branch_align
;
8132 opt_diff
= get_text_align_fill_size (address
, align_power
,
8133 target_size
, FALSE
, FALSE
);
8135 *max_diff
= (opt_diff
+ branch_align
8136 - (target_size
+ ((address
+ opt_diff
) % branch_align
)));
8137 assert (*max_diff
>= opt_diff
);
8140 case RELAX_ALIGN_NEXT_OPCODE
:
8141 target_size
= next_frag_format_size (fragP
);
8142 loop_insn_offset
= 0;
8143 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
8146 /* If the loop has been expanded then the LOOP instruction
8147 could be at an offset from this fragment. */
8148 if (next_non_empty_frag(fragP
)->tc_frag_data
.slot_subtypes
[0]
8150 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
8152 if (target_size
== 2)
8153 target_size
= 3; /* ISA specifies this */
8155 /* In an ideal world, which is what we are shooting for here,
8156 we wouldn't need to use any NOPs immediately prior to the
8157 LOOP instruction. If this approach fails, relax_frag_loop_align
8158 will call get_noop_aligned_address. */
8160 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
8161 align_power
= get_text_align_power (target_size
),
8162 opt_diff
= get_text_align_fill_size (target_address
, align_power
,
8163 target_size
, FALSE
, FALSE
);
8165 *max_diff
= xtensa_fetch_width
8166 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
8167 - target_size
+ opt_diff
;
8168 assert (*max_diff
>= opt_diff
);
8179 /* md_relax_frag Hook and Helper Functions. */
8181 static long relax_frag_loop_align (fragS
*, long);
8182 static long relax_frag_for_align (fragS
*, long);
8183 static long relax_frag_immed
8184 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
8187 /* Return the number of bytes added to this fragment, given that the
8188 input has been stretched already by "stretch". */
8191 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
8193 xtensa_isa isa
= xtensa_default_isa
;
8194 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
8195 long new_stretch
= 0;
8199 static xtensa_insnbuf vbuf
= NULL
;
8200 int slot
, num_slots
;
8203 as_where (&file_name
, &line
);
8204 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8206 fragP
->tc_frag_data
.unreported_expansion
= 0;
8208 switch (fragP
->fr_subtype
)
8210 case RELAX_ALIGN_NEXT_OPCODE
:
8211 /* Always convert. */
8212 if (fragP
->tc_frag_data
.relax_seen
)
8213 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
8216 case RELAX_LOOP_END
:
8220 case RELAX_LOOP_END_ADD_NOP
:
8221 /* Add a NOP and switch to .fill 0. */
8222 new_stretch
= relax_frag_add_nop (fragP
);
8226 case RELAX_DESIRE_ALIGN
:
8227 /* Do nothing. The narrowing before this frag will either align
8232 case RELAX_LITERAL_FINAL
:
8235 case RELAX_LITERAL_NR
:
8237 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
8238 assert (unreported
== lit_size
);
8239 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
8240 fragP
->fr_var
-= lit_size
;
8241 fragP
->fr_fix
+= lit_size
;
8247 vbuf
= xtensa_insnbuf_alloc (isa
);
8249 xtensa_insnbuf_from_chars
8250 (isa
, vbuf
, (unsigned char *) fragP
->fr_opcode
, 0);
8251 fmt
= xtensa_format_decode (isa
, vbuf
);
8252 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8254 for (slot
= 0; slot
< num_slots
; slot
++)
8256 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
8259 if (fragP
->tc_frag_data
.relax_seen
)
8260 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8264 case RELAX_IMMED_STEP1
:
8265 case RELAX_IMMED_STEP2
:
8266 /* Place the immediate. */
8267 new_stretch
+= relax_frag_immed
8268 (now_seg
, fragP
, stretch
,
8269 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8270 fmt
, slot
, stretched_p
, FALSE
);
8274 /* This is OK; see the note in xg_assemble_vliw_tokens. */
8280 case RELAX_LITERAL_POOL_BEGIN
:
8281 case RELAX_LITERAL_POOL_END
:
8282 case RELAX_MAYBE_UNREACHABLE
:
8283 case RELAX_MAYBE_DESIRE_ALIGN
:
8284 /* No relaxation required. */
8287 case RELAX_FILL_NOP
:
8288 case RELAX_UNREACHABLE
:
8289 if (fragP
->tc_frag_data
.relax_seen
)
8290 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8294 as_bad (_("bad relaxation state"));
8297 /* Tell gas we need another relaxation pass. */
8298 if (! fragP
->tc_frag_data
.relax_seen
)
8300 fragP
->tc_frag_data
.relax_seen
= TRUE
;
8304 new_logical_line (file_name
, line
);
8310 relax_frag_loop_align (fragS
*fragP
, long stretch
)
8312 addressT old_address
, old_next_address
, old_size
;
8313 addressT new_address
, new_next_address
, new_size
;
8316 /* All the frags with relax_frag_for_alignment prior to this one in the
8317 section have been done, hopefully eliminating the need for a NOP here.
8318 But, this will put it in if necessary. */
8320 /* Calculate the old address of this fragment and the next fragment. */
8321 old_address
= fragP
->fr_address
- stretch
;
8322 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
8323 fragP
->tc_frag_data
.text_expansion
[0]);
8324 old_size
= old_next_address
- old_address
;
8326 /* Calculate the new address of this fragment and the next fragment. */
8327 new_address
= fragP
->fr_address
;
8329 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
8330 new_size
= new_next_address
- new_address
;
8332 growth
= new_size
- old_size
;
8334 /* Fix up the text_expansion field and return the new growth. */
8335 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
8340 /* Add a NOP instruction. */
8343 relax_frag_add_nop (fragS
*fragP
)
8345 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
8346 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
8347 assemble_nop (length
, nop_buf
);
8348 fragP
->tc_frag_data
.is_insn
= TRUE
;
8350 if (fragP
->fr_var
< length
)
8352 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP
->fr_var
, length
);
8356 fragP
->fr_fix
+= length
;
8357 fragP
->fr_var
-= length
;
8362 static long future_alignment_required (fragS
*, long);
8365 relax_frag_for_align (fragS
*fragP
, long stretch
)
8367 /* Overview of the relaxation procedure for alignment:
8368 We can widen with NOPs or by widening instructions or by filling
8369 bytes after jump instructions. Find the opportune places and widen
8370 them if necessary. */
8375 assert (fragP
->fr_subtype
== RELAX_FILL_NOP
8376 || fragP
->fr_subtype
== RELAX_UNREACHABLE
8377 || (fragP
->fr_subtype
== RELAX_SLOTS
8378 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
8380 stretch_me
= future_alignment_required (fragP
, stretch
);
8381 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
8387 /* We expanded on a previous pass. Can we shrink now? */
8388 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
8389 if (shrink
<= stretch
&& stretch
> 0)
8391 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8397 /* Below here, diff > 0. */
8398 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8404 /* Return the address of the next frag that should be aligned.
8406 By "address" we mean the address it _would_ be at if there
8407 is no action taken to align it between here and the target frag.
8408 In other words, if no narrows and no fill nops are used between
8409 here and the frag to align, _even_if_ some of the frags we use
8410 to align targets have already expanded on a previous relaxation
8413 Also, count each frag that may be used to help align the target.
8415 Return 0 if there are no frags left in the chain that need to be
8419 find_address_of_next_align_frag (fragS
**fragPP
,
8423 bfd_boolean
*paddable
)
8425 fragS
*fragP
= *fragPP
;
8426 addressT address
= fragP
->fr_address
;
8428 /* Do not reset the counts to 0. */
8432 /* Limit this to a small search. */
8438 address
+= fragP
->fr_fix
;
8440 if (fragP
->fr_type
== rs_fill
)
8441 address
+= fragP
->fr_offset
* fragP
->fr_var
;
8442 else if (fragP
->fr_type
== rs_machine_dependent
)
8444 switch (fragP
->fr_subtype
)
8446 case RELAX_UNREACHABLE
:
8450 case RELAX_FILL_NOP
:
8452 if (!fragP
->tc_frag_data
.is_no_density
)
8457 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8462 address
+= total_frag_text_expansion (fragP
);;
8466 address
+= fragP
->tc_frag_data
.text_expansion
[0];
8469 case RELAX_ALIGN_NEXT_OPCODE
:
8470 case RELAX_DESIRE_ALIGN
:
8474 case RELAX_MAYBE_UNREACHABLE
:
8475 case RELAX_MAYBE_DESIRE_ALIGN
:
8480 /* Just punt if we don't know the type. */
8487 /* Just punt if we don't know the type. */
8491 fragP
= fragP
->fr_next
;
8499 static long bytes_to_stretch (fragS
*, int, int, int, int);
8502 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
8504 fragS
*this_frag
= fragP
;
8508 int narrow_nops
= 0;
8509 bfd_boolean paddable
= FALSE
;
8510 offsetT local_opt_diff
;
8513 int stretch_amount
= 0;
8514 int local_stretch_amount
;
8515 int global_stretch_amount
;
8517 address
= find_address_of_next_align_frag
8518 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
8522 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
8523 opt_diff
= local_opt_diff
;
8524 assert (opt_diff
>= 0);
8525 assert (max_diff
>= opt_diff
);
8530 fragP
= fragP
->fr_next
;
8532 while (fragP
&& opt_diff
< max_diff
&& address
)
8534 /* We only use these to determine if we can exit early
8535 because there will be plenty of ways to align future
8537 int glob_widens
= 0;
8540 bfd_boolean glob_pad
= 0;
8541 address
= find_address_of_next_align_frag
8542 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
8543 /* If there is a padable portion, then skip. */
8544 if (glob_pad
|| glob_widens
>= (1 << branch_align_power (now_seg
)))
8549 offsetT next_m_diff
;
8550 offsetT next_o_diff
;
8552 /* Downrange frags haven't had stretch added to them yet. */
8555 /* The address also includes any text expansion from this
8556 frag in a previous pass, but we don't want that. */
8557 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
8559 /* Assume we are going to move at least opt_diff. In
8560 reality, we might not be able to, but assuming that
8561 we will helps catch cases where moving opt_diff pushes
8562 the next target from aligned to unaligned. */
8563 address
+= opt_diff
;
8565 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
8567 /* Now cleanup for the adjustments to address. */
8568 next_o_diff
+= opt_diff
;
8569 next_m_diff
+= opt_diff
;
8570 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
8571 opt_diff
= next_o_diff
;
8572 if (next_m_diff
< max_diff
)
8573 max_diff
= next_m_diff
;
8574 fragP
= fragP
->fr_next
;
8578 /* If there are enough wideners in between, do it. */
8581 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
8583 assert (opt_diff
<= UNREACHABLE_MAX_WIDTH
);
8588 local_stretch_amount
8589 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8590 num_widens
, local_opt_diff
);
8591 global_stretch_amount
8592 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8593 num_widens
, opt_diff
);
8594 /* If the condition below is true, then the frag couldn't
8595 stretch the correct amount for the global case, so we just
8596 optimize locally. We'll rely on the subsequent frags to get
8597 the correct alignment in the global case. */
8598 if (global_stretch_amount
< local_stretch_amount
)
8599 stretch_amount
= local_stretch_amount
;
8601 stretch_amount
= global_stretch_amount
;
8603 if (this_frag
->fr_subtype
== RELAX_SLOTS
8604 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8605 assert (stretch_amount
<= 1);
8606 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8608 if (this_frag
->tc_frag_data
.is_no_density
)
8609 assert (stretch_amount
== 3 || stretch_amount
== 0);
8611 assert (stretch_amount
<= 3);
8614 return stretch_amount
;
8618 /* The idea: widen everything you can to get a target or loop aligned,
8619 then start using NOPs.
8621 When we must have a NOP, here is a table of how we decide
8622 (so you don't have to fight through the control flow below):
8624 wide_nops = the number of wide NOPs available for aligning
8625 narrow_nops = the number of narrow NOPs available for aligning
8626 (a subset of wide_nops)
8627 widens = the number of narrow instructions that should be widened
8634 b 0 1 1 (case 3a makes this case unnecessary)
8637 c 0 1 2 (case 4a makes this case unnecessary)
8640 c 0 2 1 (case 5b makes this case unnecessary)
8643 c 0 1 4 (case 6b makes this case unneccesary)
8644 d 1 1 1 (case 6a makes this case unnecessary)
8645 e 0 2 2 (case 6a makes this case unnecessary)
8646 f 0 3 0 (case 6a makes this case unnecessary)
8649 c 1 1 2 (case 7b makes this case unnecessary)
8650 d 0 1 5 (case 7a makes this case unnecessary)
8651 e 0 2 3 (case 7b makes this case unnecessary)
8652 f 0 3 1 (case 7b makes this case unnecessary)
8653 g 1 2 1 (case 7b makes this case unnecessary)
8657 bytes_to_stretch (fragS
*this_frag
,
8663 int bytes_short
= desired_diff
- num_widens
;
8665 assert (desired_diff
>= 0 && desired_diff
< 8);
8666 if (desired_diff
== 0)
8669 assert (wide_nops
> 0 || num_widens
> 0);
8671 /* Always prefer widening to NOP-filling. */
8672 if (bytes_short
< 0)
8674 /* There are enough RELAX_NARROW frags after this one
8675 to align the target without widening this frag in any way. */
8679 if (bytes_short
== 0)
8681 /* Widen every narrow between here and the align target
8682 and the align target will be properly aligned. */
8683 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8689 /* From here we will need at least one NOP to get an alignment.
8690 However, we may not be able to align at all, in which case,
8692 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8694 switch (desired_diff
)
8699 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 1)
8700 return 2; /* case 2 */
8706 return 3; /* case 3a */
8708 if (num_widens
>= 1 && wide_nops
== 1)
8709 return 3; /* case 4a */
8710 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 2)
8711 return 2; /* case 4b */
8714 if (num_widens
>= 2 && wide_nops
== 1)
8715 return 3; /* case 5a */
8716 /* We will need two nops. Are there enough nops
8717 between here and the align target? */
8718 if (wide_nops
< 2 || narrow_nops
== 0)
8720 /* Are there other nops closer that can serve instead? */
8721 if (wide_nops
> 2 && narrow_nops
> 1)
8723 /* Take the density one first, because there might not be
8724 another density one available. */
8725 if (!this_frag
->tc_frag_data
.is_no_density
)
8726 return 2; /* case 5b narrow */
8728 return 3; /* case 5b wide */
8732 return 3; /* case 6a */
8733 else if (num_widens
>= 3 && wide_nops
== 1)
8734 return 3; /* case 6b */
8737 if (wide_nops
== 1 && num_widens
>= 4)
8738 return 3; /* case 7a */
8739 else if (wide_nops
== 2 && num_widens
>= 1)
8740 return 3; /* case 7b */
8748 /* We will need a NOP no matter what, but should we widen
8749 this instruction to help?
8751 This is a RELAX_FRAG_NARROW frag. */
8752 switch (desired_diff
)
8761 if (wide_nops
>= 1 && num_widens
== 1)
8762 return 1; /* case 4a */
8765 if (wide_nops
>= 1 && num_widens
== 2)
8766 return 1; /* case 5a */
8770 return 0; /* case 6a */
8771 else if (wide_nops
>= 1 && num_widens
== 3)
8772 return 1; /* case 6b */
8775 if (wide_nops
>= 1 && num_widens
== 4)
8776 return 1; /* case 7a */
8777 else if (wide_nops
>= 2 && num_widens
== 1)
8778 return 1; /* case 7b */
8791 relax_frag_immed (segT segP
,
8798 bfd_boolean estimate_only
)
8801 vliw_insn orig_vinsn
;
8803 bfd_boolean negatable_branch
= FALSE
;
8804 bfd_boolean branch_jmp_to_next
= FALSE
;
8805 bfd_boolean wide_insn
= FALSE
;
8806 xtensa_isa isa
= xtensa_default_isa
;
8808 offsetT frag_offset
;
8811 int num_text_bytes
, num_literal_bytes
;
8812 int literal_diff
, total_text_diff
, this_text_diff
, first
;
8814 assert (fragP
->fr_opcode
!= NULL
);
8816 xg_init_vinsn (&orig_vinsn
);
8817 vinsn_from_chars (&orig_vinsn
, fragP
->fr_opcode
);
8818 if (xtensa_format_num_slots (isa
, fmt
) > 1)
8821 tinsn
= orig_vinsn
.slots
[slot
];
8822 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
8824 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
))
8827 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
8828 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
8830 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
8832 old_size
= xtensa_format_length (isa
, fmt
);
8834 /* Special case: replace a branch to the next instruction with a NOP.
8835 This is required to work around a hardware bug in T1040.0 and also
8836 serves as an optimization. */
8838 if (branch_jmp_to_next
8839 && ((old_size
== 2) || (old_size
== 3))
8840 && !next_frag_is_loop_target (fragP
))
8843 /* Here is the fun stuff: Get the immediate field from this
8844 instruction. If it fits, we are done. If not, find the next
8845 instruction sequence that fits. */
8847 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
8848 istack_init (&istack
);
8849 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
8850 min_steps
, stretch
);
8851 if (num_steps
< min_steps
)
8853 as_fatal (_("internal error: relaxation failed"));
8857 if (num_steps
> RELAX_IMMED_MAXSTEPS
)
8859 as_fatal (_("internal error: relaxation requires too many steps"));
8863 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
8865 /* Figure out the number of bytes needed. */
8867 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
8869 num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
8871 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
8873 num_text_bytes
= get_num_stack_text_bytes (&istack
);
8876 num_text_bytes
+= old_size
;
8877 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
8878 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
8880 total_text_diff
= num_text_bytes
- old_size
;
8881 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
8883 /* It MUST get larger. If not, we could get an infinite loop. */
8884 assert (num_text_bytes
>= 0);
8885 assert (literal_diff
>= 0);
8886 assert (total_text_diff
>= 0);
8888 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
8889 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
8890 assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
8891 assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
8893 /* Find the associated expandable literal for this. */
8894 if (literal_diff
!= 0)
8896 lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
8899 assert (literal_diff
== 4);
8900 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
8902 /* We expect that the literal section state has NOT been
8904 assert (lit_fragP
->fr_type
== rs_machine_dependent
8905 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
8906 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
8908 /* We need to mark this section for another iteration
8914 if (negatable_branch
&& istack
.ninsn
> 1)
8915 update_next_frag_state (fragP
);
8917 return this_text_diff
;
8921 /* md_convert_frag Hook and Helper Functions. */
8923 static void convert_frag_align_next_opcode (fragS
*);
8924 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
8925 static void convert_frag_fill_nop (fragS
*);
8926 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
8929 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
8931 static xtensa_insnbuf vbuf
= NULL
;
8932 xtensa_isa isa
= xtensa_default_isa
;
8939 as_where (&file_name
, &line
);
8940 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
8942 switch (fragp
->fr_subtype
)
8944 case RELAX_ALIGN_NEXT_OPCODE
:
8945 /* Always convert. */
8946 convert_frag_align_next_opcode (fragp
);
8949 case RELAX_DESIRE_ALIGN
:
8950 /* Do nothing. If not aligned already, too bad. */
8954 case RELAX_LITERAL_FINAL
:
8959 vbuf
= xtensa_insnbuf_alloc (isa
);
8961 xtensa_insnbuf_from_chars
8962 (isa
, vbuf
, (unsigned char *) fragp
->fr_opcode
, 0);
8963 fmt
= xtensa_format_decode (isa
, vbuf
);
8964 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8966 for (slot
= 0; slot
< num_slots
; slot
++)
8968 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
8971 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
8975 case RELAX_IMMED_STEP1
:
8976 case RELAX_IMMED_STEP2
:
8977 /* Place the immediate. */
8980 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8985 /* This is OK because some slots could have
8986 relaxations and others have none. */
8992 case RELAX_UNREACHABLE
:
8993 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
8994 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
8995 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
8999 case RELAX_MAYBE_UNREACHABLE
:
9000 case RELAX_MAYBE_DESIRE_ALIGN
:
9004 case RELAX_FILL_NOP
:
9005 convert_frag_fill_nop (fragp
);
9008 case RELAX_LITERAL_NR
:
9009 if (use_literal_section
)
9011 /* This should have been handled during relaxation. When
9012 relaxing a code segment, literals sometimes need to be
9013 added to the corresponding literal segment. If that
9014 literal segment has already been relaxed, then we end up
9015 in this situation. Marking the literal segments as data
9016 would make this happen less often (since GAS always relaxes
9017 code before data), but we could still get into trouble if
9018 there are instructions in a segment that is not marked as
9019 containing code. Until we can implement a better solution,
9020 cheat and adjust the addresses of all the following frags.
9021 This could break subsequent alignments, but the linker's
9022 literal coalescing will do that anyway. */
9025 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
9026 assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
9027 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
9030 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
9034 as_bad (_("invalid relaxation fragment result"));
9039 new_logical_line (file_name
, line
);
9044 convert_frag_align_next_opcode (fragS
*fragp
)
9046 char *nop_buf
; /* Location for Writing. */
9047 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
9048 addressT aligned_address
;
9052 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
9054 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
9055 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
9056 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
9058 for (nop
= 0; nop
< nop_count
; nop
++)
9061 nop_size
= get_text_align_nth_nop_size (fill_size
, nop
, use_no_density
);
9063 assemble_nop (nop_size
, nop_buf
);
9064 nop_buf
+= nop_size
;
9067 fragp
->fr_fix
+= fill_size
;
9068 fragp
->fr_var
-= fill_size
;
9073 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
9075 TInsn tinsn
, single_target
;
9076 xtensa_format single_fmt
;
9077 int size
, old_size
, diff
;
9078 offsetT frag_offset
;
9081 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
9083 if (xtensa_opcode_is_branch (xtensa_default_isa
, tinsn
.opcode
) == 1)
9085 assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
9086 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
9087 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
9092 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
9094 /* No conversion. */
9099 assert (fragP
->fr_opcode
!= NULL
);
9101 /* Frags in this relaxation state should only contain
9102 single instruction bundles. */
9103 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
9105 /* Just convert it to a wide form.... */
9107 old_size
= xg_get_single_size (tinsn
.opcode
);
9109 tinsn_init (&single_target
);
9110 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9112 if (! xg_is_single_relaxable_insn (&tinsn
, &single_target
, FALSE
))
9114 as_bad (_("unable to widen instruction"));
9118 size
= xg_get_single_size (single_target
.opcode
);
9119 single_fmt
= xg_get_single_format (single_target
.opcode
);
9121 xg_emit_insn_to_buf (&single_target
, single_fmt
, fragP
->fr_opcode
,
9122 fragP
, frag_offset
, TRUE
);
9124 diff
= size
- old_size
;
9126 assert (diff
<= fragP
->fr_var
);
9127 fragP
->fr_var
-= diff
;
9128 fragP
->fr_fix
+= diff
;
9136 convert_frag_fill_nop (fragS
*fragP
)
9138 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
9139 int size
= fragP
->tc_frag_data
.text_expansion
[0];
9140 assert ((unsigned) size
== (fragP
->fr_next
->fr_address
9141 - fragP
->fr_address
- fragP
->fr_fix
));
9144 /* No conversion. */
9148 assemble_nop (size
, loc
);
9149 fragP
->tc_frag_data
.is_insn
= TRUE
;
9150 fragP
->fr_var
-= size
;
9151 fragP
->fr_fix
+= size
;
9156 static fixS
*fix_new_exp_in_seg
9157 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
9158 bfd_reloc_code_real_type
);
9159 static void convert_frag_immed_finish_loop (segT
, fragS
*, TInsn
*);
9162 convert_frag_immed (segT segP
,
9168 char *immed_instr
= fragP
->fr_opcode
;
9170 bfd_boolean expanded
= FALSE
;
9171 bfd_boolean branch_jmp_to_next
= FALSE
;
9172 char *fr_opcode
= fragP
->fr_opcode
;
9173 vliw_insn orig_vinsn
;
9174 xtensa_isa isa
= xtensa_default_isa
;
9175 bfd_boolean wide_insn
= FALSE
;
9177 bfd_boolean is_loop
;
9179 assert (fr_opcode
!= NULL
);
9181 xg_init_vinsn (&orig_vinsn
);
9183 vinsn_from_chars (&orig_vinsn
, fr_opcode
);
9184 if (xtensa_format_num_slots (isa
, fmt
) > 1)
9187 orig_tinsn
= orig_vinsn
.slots
[slot
];
9188 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
9190 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
9192 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9193 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
9195 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
9197 /* Conversion just inserts a NOP and marks the fix as completed. */
9198 bytes
= xtensa_format_length (isa
, fmt
);
9201 orig_vinsn
.slots
[slot
].opcode
=
9202 xtensa_format_slot_nop_opcode (isa
, orig_vinsn
.format
, slot
);
9203 orig_vinsn
.slots
[slot
].ntok
= 0;
9207 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
9208 assert (bytes
== 2 || bytes
== 3);
9209 build_nop (&orig_vinsn
.slots
[0], bytes
);
9210 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
9212 vinsn_to_insnbuf (&orig_vinsn
, fr_opcode
, frag_now
, FALSE
);
9213 xtensa_insnbuf_to_chars
9214 (isa
, orig_vinsn
.insnbuf
, (unsigned char *) fr_opcode
, 0);
9219 /* Here is the fun stuff: Get the immediate field from this
9220 instruction. If it fits, we're done. If not, find the next
9221 instruction sequence that fits. */
9225 symbolS
*lit_sym
= NULL
;
9227 int target_offset
= 0;
9230 symbolS
*gen_label
= NULL
;
9231 offsetT frag_offset
;
9232 bfd_boolean first
= TRUE
;
9233 bfd_boolean last_is_jump
;
9235 /* It does not fit. Find something that does and
9236 convert immediately. */
9237 frag_offset
= fr_opcode
- fragP
->fr_literal
;
9238 istack_init (&istack
);
9239 xg_assembly_relax (&istack
, &orig_tinsn
,
9240 segP
, fragP
, frag_offset
, min_steps
, 0);
9242 old_size
= xtensa_format_length (isa
, fmt
);
9244 /* Assemble this right inline. */
9246 /* First, create the mapping from a label name to the REAL label. */
9248 for (i
= 0; i
< istack
.ninsn
; i
++)
9250 TInsn
*tinsn
= &istack
.insn
[i
];
9253 switch (tinsn
->insn_type
)
9256 if (lit_sym
!= NULL
)
9257 as_bad (_("multiple literals in expansion"));
9258 /* First find the appropriate space in the literal pool. */
9259 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9260 if (lit_frag
== NULL
)
9261 as_bad (_("no registered fragment for literal"));
9262 if (tinsn
->ntok
!= 1)
9263 as_bad (_("number of literal tokens != 1"));
9265 /* Set the literal symbol and add a fixup. */
9266 lit_sym
= lit_frag
->fr_symbol
;
9270 if (align_targets
&& !is_loop
)
9272 fragS
*unreach
= fragP
->fr_next
;
9273 while (!(unreach
->fr_type
== rs_machine_dependent
9274 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9275 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
9277 unreach
= unreach
->fr_next
;
9280 assert (unreach
->fr_type
== rs_machine_dependent
9281 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9282 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
9284 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
9286 assert (gen_label
== NULL
);
9287 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
9288 fr_opcode
- fragP
->fr_literal
9289 + target_offset
, fragP
);
9293 if (first
&& wide_insn
)
9295 target_offset
+= xtensa_format_length (isa
, fmt
);
9297 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9298 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9301 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9308 last_is_jump
= FALSE
;
9309 for (i
= 0; i
< istack
.ninsn
; i
++)
9311 TInsn
*tinsn
= &istack
.insn
[i
];
9315 bfd_reloc_code_real_type reloc_type
;
9317 switch (tinsn
->insn_type
)
9320 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9321 /* Already checked. */
9322 assert (lit_frag
!= NULL
);
9323 assert (lit_sym
!= NULL
);
9324 assert (tinsn
->ntok
== 1);
9326 target_seg
= S_GET_SEGMENT (lit_sym
);
9327 assert (target_seg
);
9328 if (tinsn
->tok
[0].X_op
== O_pltrel
)
9329 reloc_type
= BFD_RELOC_XTENSA_PLT
;
9331 reloc_type
= BFD_RELOC_32
;
9332 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
9333 &tinsn
->tok
[0], FALSE
, reloc_type
);
9340 xg_resolve_labels (tinsn
, gen_label
);
9341 xg_resolve_literals (tinsn
, lit_sym
);
9342 if (wide_insn
&& first
)
9345 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9347 tinsn
->record_fix
= TRUE
;
9348 orig_vinsn
.slots
[slot
] = *tinsn
;
9352 orig_vinsn
.slots
[slot
].opcode
=
9353 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
9354 orig_vinsn
.slots
[slot
].ntok
= 0;
9355 orig_vinsn
.slots
[slot
].record_fix
= FALSE
;
9357 vinsn_to_insnbuf (&orig_vinsn
, immed_instr
, fragP
, TRUE
);
9358 xtensa_insnbuf_to_chars (isa
, orig_vinsn
.insnbuf
,
9359 (unsigned char *) immed_instr
, 0);
9360 fragP
->tc_frag_data
.is_insn
= TRUE
;
9361 size
= xtensa_format_length (isa
, fmt
);
9362 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9364 xtensa_format single_fmt
=
9365 xg_get_single_format (tinsn
->opcode
);
9368 (tinsn
, single_fmt
, immed_instr
+ size
, fragP
,
9369 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
9370 size
+= xg_get_single_size (tinsn
->opcode
);
9375 xtensa_format single_format
;
9376 size
= xg_get_single_size (tinsn
->opcode
);
9377 single_format
= xg_get_single_format (tinsn
->opcode
);
9378 xg_emit_insn_to_buf (tinsn
, single_format
, immed_instr
,
9380 immed_instr
- fragP
->fr_literal
, TRUE
);
9382 immed_instr
+= size
;
9388 diff
= total_size
- old_size
;
9392 assert (diff
<= fragP
->fr_var
);
9393 fragP
->fr_var
-= diff
;
9394 fragP
->fr_fix
+= diff
;
9398 xg_free_vinsn (&orig_vinsn
);
9400 /* Check for undefined immediates in LOOP instructions. */
9404 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
9405 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9407 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9410 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
9411 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9413 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9418 if (expanded
&& xtensa_opcode_is_loop (isa
, orig_tinsn
.opcode
) == 1)
9419 convert_frag_immed_finish_loop (segP
, fragP
, &orig_tinsn
);
9421 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
9423 /* Add an expansion note on the expanded instruction. */
9424 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
9425 &orig_tinsn
.tok
[0], TRUE
,
9426 BFD_RELOC_XTENSA_ASM_EXPAND
);
9431 /* Add a new fix expression into the desired segment. We have to
9432 switch to that segment to do this. */
9435 fix_new_exp_in_seg (segT new_seg
,
9442 bfd_reloc_code_real_type r_type
)
9446 subsegT subseg
= now_subseg
;
9448 assert (new_seg
!= 0);
9449 subseg_set (new_seg
, new_subseg
);
9451 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
9452 subseg_set (seg
, subseg
);
9457 /* Relax a loop instruction so that it can span loop >256 bytes.
9463 addi as, as, lo8 (label-.L1)
9464 addmi as, as, mid8 (label-.L1)
9475 convert_frag_immed_finish_loop (segT segP
, fragS
*fragP
, TInsn
*tinsn
)
9480 unsigned long target
;
9481 static xtensa_insnbuf insnbuf
= NULL
;
9482 unsigned int loop_length
, loop_length_hi
, loop_length_lo
;
9483 xtensa_isa isa
= xtensa_default_isa
;
9484 addressT loop_offset
;
9485 addressT addi_offset
= 9;
9486 addressT addmi_offset
= 12;
9491 insnbuf
= xtensa_insnbuf_alloc (isa
);
9493 /* Get the loop offset. */
9494 loop_offset
= get_expanded_loop_offset (tinsn
->opcode
);
9496 /* Validate that there really is a LOOP at the loop_offset. Because
9497 loops are not bundleable, we can assume that the instruction will be
9499 tinsn_from_chars (&loop_insn
, fragP
->fr_opcode
+ loop_offset
, 0);
9500 tinsn_immed_from_frag (&loop_insn
, fragP
, 0);
9502 assert (xtensa_opcode_is_loop (isa
, loop_insn
.opcode
) == 1);
9503 addi_offset
+= loop_offset
;
9504 addmi_offset
+= loop_offset
;
9506 assert (tinsn
->ntok
== 2);
9507 if (tinsn
->tok
[1].X_op
== O_constant
)
9508 target
= tinsn
->tok
[1].X_add_number
;
9509 else if (tinsn
->tok
[1].X_op
== O_symbol
)
9511 /* Find the fragment. */
9512 symbolS
*sym
= tinsn
->tok
[1].X_add_symbol
;
9513 assert (S_GET_SEGMENT (sym
) == segP
9514 || S_GET_SEGMENT (sym
) == absolute_section
);
9515 target
= (S_GET_VALUE (sym
) + tinsn
->tok
[1].X_add_number
);
9519 as_bad (_("invalid expression evaluation type %d"), tinsn
->tok
[1].X_op
);
9524 know (symbolP
->sy_frag
);
9525 know (!(S_GET_SEGMENT (symbolP
) == absolute_section
)
9526 || symbol_get_frag (symbolP
) == &zero_address_frag
);
9528 loop_length
= target
- (fragP
->fr_address
+ fragP
->fr_fix
);
9529 loop_length_hi
= loop_length
& ~0x0ff;
9530 loop_length_lo
= loop_length
& 0x0ff;
9531 if (loop_length_lo
>= 128)
9533 loop_length_lo
-= 256;
9534 loop_length_hi
+= 256;
9537 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
9538 32512. If the loop is larger than that, then we just fail. */
9539 if (loop_length_hi
> 32512)
9540 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9541 _("loop too long for LOOP instruction"));
9543 tinsn_from_chars (&addi_insn
, fragP
->fr_opcode
+ addi_offset
, 0);
9544 assert (addi_insn
.opcode
== xtensa_addi_opcode
);
9546 tinsn_from_chars (&addmi_insn
, fragP
->fr_opcode
+ addmi_offset
, 0);
9547 assert (addmi_insn
.opcode
== xtensa_addmi_opcode
);
9549 set_expr_const (&addi_insn
.tok
[2], loop_length_lo
);
9550 tinsn_to_insnbuf (&addi_insn
, insnbuf
);
9552 fragP
->tc_frag_data
.is_insn
= TRUE
;
9553 xtensa_insnbuf_to_chars
9554 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addi_offset
, 0);
9556 set_expr_const (&addmi_insn
.tok
[2], loop_length_hi
);
9557 tinsn_to_insnbuf (&addmi_insn
, insnbuf
);
9558 xtensa_insnbuf_to_chars
9559 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addmi_offset
, 0);
9561 /* Walk through all of the frags from here to the loop end
9562 and mark them as no_transform to keep them from being modified
9563 by the linker. If we ever have a relocation for the
9564 addi/addmi of the difference of two symbols we can remove this. */
9567 for (next_fragP
= fragP
; next_fragP
!= NULL
;
9568 next_fragP
= next_fragP
->fr_next
)
9570 next_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
9571 if (next_fragP
->tc_frag_data
.is_loop_target
)
9573 if (target_count
== 2)
9579 /* A map that keeps information on a per-subsegment basis. This is
9580 maintained during initial assembly, but is invalid once the
9581 subsegments are smashed together. I.E., it cannot be used during
9584 typedef struct subseg_map_struct
9592 float total_freq
; /* fall-through + branch target frequency */
9593 float target_freq
; /* branch target frequency alone */
9595 struct subseg_map_struct
*next
;
9599 static subseg_map
*sseg_map
= NULL
;
9602 get_subseg_info (segT seg
, subsegT subseg
)
9604 subseg_map
*subseg_e
;
9606 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
9608 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
9616 add_subseg_info (segT seg
, subsegT subseg
)
9618 subseg_map
*subseg_e
= (subseg_map
*) xmalloc (sizeof (subseg_map
));
9619 memset (subseg_e
, 0, sizeof (subseg_map
));
9620 subseg_e
->seg
= seg
;
9621 subseg_e
->subseg
= subseg
;
9622 subseg_e
->flags
= 0;
9623 /* Start off considering every branch target very important. */
9624 subseg_e
->target_freq
= 1.0;
9625 subseg_e
->total_freq
= 1.0;
9626 subseg_e
->next
= sseg_map
;
9627 sseg_map
= subseg_e
;
9633 get_last_insn_flags (segT seg
, subsegT subseg
)
9635 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9637 return subseg_e
->flags
;
9643 set_last_insn_flags (segT seg
,
9648 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9650 subseg_e
= add_subseg_info (seg
, subseg
);
9652 subseg_e
->flags
|= fl
;
9654 subseg_e
->flags
&= ~fl
;
9659 get_subseg_total_freq (segT seg
, subsegT subseg
)
9661 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9663 return subseg_e
->total_freq
;
9669 get_subseg_target_freq (segT seg
, subsegT subseg
)
9671 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9673 return subseg_e
->target_freq
;
9679 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
9681 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9683 subseg_e
= add_subseg_info (seg
, subseg
);
9684 subseg_e
->total_freq
= total_f
;
9685 subseg_e
->target_freq
= target_f
;
9689 /* Segment Lists and emit_state Stuff. */
9692 xtensa_move_seg_list_to_beginning (seg_list
*head
)
9697 segT literal_section
= head
->seg
;
9699 /* Move the literal section to the front of the section list. */
9700 assert (literal_section
);
9701 if (literal_section
!= stdoutput
->sections
)
9703 bfd_section_list_remove (stdoutput
, literal_section
);
9704 bfd_section_list_prepend (stdoutput
, literal_section
);
9711 static void mark_literal_frags (seg_list
*);
9714 xtensa_move_literals (void)
9717 frchainS
*frchain_from
, *frchain_to
;
9718 fragS
*search_frag
, *next_frag
, *last_frag
, *literal_pool
, *insert_after
;
9719 fragS
**frag_splice
;
9722 fixS
*fix
, *next_fix
, **fix_splice
;
9725 mark_literal_frags (literal_head
->next
);
9726 mark_literal_frags (init_literal_head
->next
);
9727 mark_literal_frags (fini_literal_head
->next
);
9729 if (use_literal_section
)
9732 segment
= literal_head
->next
;
9735 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9736 search_frag
= frchain_from
->frch_root
;
9737 literal_pool
= NULL
;
9739 frag_splice
= &(frchain_from
->frch_root
);
9741 while (!search_frag
->tc_frag_data
.literal_frag
)
9743 assert (search_frag
->fr_fix
== 0
9744 || search_frag
->fr_type
== rs_align
);
9745 search_frag
= search_frag
->fr_next
;
9748 assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
9749 == RELAX_LITERAL_POOL_BEGIN
);
9750 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
9752 /* Make sure that all the frags in this series are closed, and
9753 that there is at least one left over of zero-size. This
9754 prevents us from making a segment with an frchain without any
9756 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9757 xtensa_set_frag_assembly_state (frag_now
);
9758 last_frag
= frag_now
;
9759 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9760 xtensa_set_frag_assembly_state (frag_now
);
9762 while (search_frag
!= frag_now
)
9764 next_frag
= search_frag
->fr_next
;
9766 /* First, move the frag out of the literal section and
9767 to the appropriate place. */
9768 if (search_frag
->tc_frag_data
.literal_frag
)
9770 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
9771 assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
9772 frchain_to
= literal_pool
->tc_frag_data
.lit_frchain
;
9773 assert (frchain_to
);
9775 insert_after
= literal_pool
;
9777 while (insert_after
->fr_next
->fr_subtype
!= RELAX_LITERAL_POOL_END
)
9778 insert_after
= insert_after
->fr_next
;
9780 dest_seg
= insert_after
->fr_next
->tc_frag_data
.lit_seg
;
9782 *frag_splice
= next_frag
;
9783 search_frag
->fr_next
= insert_after
->fr_next
;
9784 insert_after
->fr_next
= search_frag
;
9785 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
9787 /* Now move any fixups associated with this frag to the
9789 fix
= frchain_from
->fix_root
;
9790 fix_splice
= &(frchain_from
->fix_root
);
9793 next_fix
= fix
->fx_next
;
9794 if (fix
->fx_frag
== search_frag
)
9796 *fix_splice
= next_fix
;
9797 fix
->fx_next
= frchain_to
->fix_root
;
9798 frchain_to
->fix_root
= fix
;
9799 if (frchain_to
->fix_tail
== NULL
)
9800 frchain_to
->fix_tail
= fix
;
9803 fix_splice
= &(fix
->fx_next
);
9806 search_frag
= next_frag
;
9809 if (frchain_from
->fix_root
!= NULL
)
9811 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9812 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
9814 assert (frchain_from
->fix_root
== NULL
);
9816 frchain_from
->fix_tail
= NULL
;
9817 xtensa_restore_emit_state (&state
);
9818 segment
= segment
->next
;
9821 /* Now fix up the SEGMENT value for all the literal symbols. */
9822 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
9824 symbolS
*lit_sym
= lit
->sym
;
9825 segT dest_seg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
9827 S_SET_SEGMENT (lit_sym
, dest_seg
);
9832 /* Walk over all the frags for segments in a list and mark them as
9833 containing literals. As clunky as this is, we can't rely on frag_var
9834 and frag_variant to get called in all situations. */
9837 mark_literal_frags (seg_list
*segment
)
9839 frchainS
*frchain_from
;
9844 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9845 search_frag
= frchain_from
->frch_root
;
9848 search_frag
->tc_frag_data
.is_literal
= TRUE
;
9849 search_frag
= search_frag
->fr_next
;
9851 segment
= segment
->next
;
9857 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
9859 /* Move all of the sections in the section list to come
9860 after "after" in the gnu segment list. */
9865 segT literal_section
= head
->seg
;
9867 /* Move the literal section after "after". */
9868 assert (literal_section
);
9869 if (literal_section
!= after
)
9871 bfd_section_list_remove (stdoutput
, literal_section
);
9872 bfd_section_list_insert_after (stdoutput
, after
, literal_section
);
9880 /* Push all the literal segments to the end of the gnu list. */
9883 xtensa_reorder_segments (void)
9890 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
9896 /* Now that we have the last section, push all the literal
9897 sections to the end. */
9898 xtensa_reorder_seg_list (literal_head
, last_sec
);
9899 xtensa_reorder_seg_list (init_literal_head
, last_sec
);
9900 xtensa_reorder_seg_list (fini_literal_head
, last_sec
);
9902 /* Now perform the final error check. */
9903 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
9905 assert (new_count
== old_count
);
9909 /* Change the emit state (seg, subseg, and frag related stuff) to the
9910 correct location. Return a emit_state which can be passed to
9911 xtensa_restore_emit_state to return to current fragment. */
9914 xtensa_switch_to_literal_fragment (emit_state
*result
)
9916 if (directive_state
[directive_absolute_literals
])
9918 cache_literal_section (0, default_lit_sections
.lit4_seg_name
,
9919 &default_lit_sections
.lit4_seg
, FALSE
);
9920 xtensa_switch_section_emit_state (result
,
9921 default_lit_sections
.lit4_seg
, 0);
9924 xtensa_switch_to_non_abs_literal_fragment (result
);
9926 /* Do a 4-byte align here. */
9927 frag_align (2, 0, 0);
9928 record_alignment (now_seg
, 2);
9933 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
9935 /* When we mark a literal pool location, we want to put a frag in
9936 the literal pool that points to it. But to do that, we want to
9937 switch_to_literal_fragment. But literal sections don't have
9938 literal pools, so their location is always null, so we would
9939 recurse forever. This is kind of hacky, but it works. */
9941 static bfd_boolean recursive
= FALSE
;
9942 fragS
*pool_location
= get_literal_pool_location (now_seg
);
9943 bfd_boolean is_init
=
9944 (now_seg
&& !strcmp (segment_name (now_seg
), INIT_SECTION_NAME
));
9946 bfd_boolean is_fini
=
9947 (now_seg
&& !strcmp (segment_name (now_seg
), FINI_SECTION_NAME
));
9949 if (pool_location
== NULL
9950 && !use_literal_section
9952 && !is_init
&& ! is_fini
)
9954 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
9956 xtensa_mark_literal_pool_location ();
9960 /* Special case: If we are in the ".fini" or ".init" section, then
9961 we will ALWAYS be generating to the ".fini.literal" and
9962 ".init.literal" sections. */
9966 cache_literal_section (init_literal_head
,
9967 default_lit_sections
.init_lit_seg_name
,
9968 &default_lit_sections
.init_lit_seg
, TRUE
);
9969 xtensa_switch_section_emit_state (result
,
9970 default_lit_sections
.init_lit_seg
, 0);
9974 cache_literal_section (fini_literal_head
,
9975 default_lit_sections
.fini_lit_seg_name
,
9976 &default_lit_sections
.fini_lit_seg
, TRUE
);
9977 xtensa_switch_section_emit_state (result
,
9978 default_lit_sections
.fini_lit_seg
, 0);
9982 cache_literal_section (literal_head
,
9983 default_lit_sections
.lit_seg_name
,
9984 &default_lit_sections
.lit_seg
, TRUE
);
9985 xtensa_switch_section_emit_state (result
,
9986 default_lit_sections
.lit_seg
, 0);
9989 if (!use_literal_section
9990 && !is_init
&& !is_fini
9991 && get_literal_pool_location (now_seg
) != pool_location
)
9993 /* Close whatever frag is there. */
9994 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9995 xtensa_set_frag_assembly_state (frag_now
);
9996 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
9997 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9998 xtensa_set_frag_assembly_state (frag_now
);
10003 /* Call this function before emitting data into the literal section.
10004 This is a helper function for xtensa_switch_to_literal_fragment.
10005 This is similar to a .section new_now_seg subseg. */
10008 xtensa_switch_section_emit_state (emit_state
*state
,
10010 subsegT new_now_subseg
)
10012 state
->name
= now_seg
->name
;
10013 state
->now_seg
= now_seg
;
10014 state
->now_subseg
= now_subseg
;
10015 state
->generating_literals
= generating_literals
;
10016 generating_literals
++;
10017 subseg_set (new_now_seg
, new_now_subseg
);
10021 /* Use to restore the emitting into the normal place. */
10024 xtensa_restore_emit_state (emit_state
*state
)
10026 generating_literals
= state
->generating_literals
;
10027 subseg_set (state
->now_seg
, state
->now_subseg
);
10031 /* Get a segment of a given name. If the segment is already
10032 present, return it; otherwise, create a new one. */
10035 cache_literal_section (seg_list
*head
,
10038 bfd_boolean is_code
)
10040 segT current_section
= now_seg
;
10041 int current_subsec
= now_subseg
;
10047 /* Check if the named section exists. */
10048 for (seg
= stdoutput
->sections
; seg
; seg
= seg
->next
)
10050 if (!strcmp (segment_name (seg
), name
))
10056 /* Create a new literal section. */
10057 seg
= subseg_new (name
, (subsegT
) 0);
10060 /* Add the newly created literal segment to the specified list. */
10061 seg_list
*n
= (seg_list
*) xmalloc (sizeof (seg_list
));
10063 n
->next
= head
->next
;
10066 bfd_set_section_flags (stdoutput
, seg
, SEC_HAS_CONTENTS
|
10067 SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
10068 | (is_code
? SEC_CODE
: SEC_DATA
));
10069 bfd_set_section_alignment (stdoutput
, seg
, 2);
10073 subseg_set (current_section
, current_subsec
);
10077 /* Property Tables Stuff. */
10079 #define XTENSA_INSN_SEC_NAME ".xt.insn"
10080 #define XTENSA_LIT_SEC_NAME ".xt.lit"
10081 #define XTENSA_PROP_SEC_NAME ".xt.prop"
10083 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
10084 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
10086 static bfd_boolean
get_frag_is_literal (const fragS
*);
10087 static void xtensa_create_property_segments
10088 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
10089 static void xtensa_create_xproperty_segments
10090 (frag_flags_fn
, const char *, xt_section_type
);
10091 static segment_info_type
*retrieve_segment_info (segT
);
10092 static segT
retrieve_xtensa_section (char *);
10093 static bfd_boolean
section_has_property (segT
, frag_predicate
);
10094 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
10095 static void add_xt_block_frags
10096 (segT
, segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
10097 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
10098 static void xtensa_frag_flags_init (frag_flags
*);
10099 static void get_frag_property_flags (const fragS
*, frag_flags
*);
10100 static bfd_vma
frag_flags_to_number (const frag_flags
*);
10101 static void add_xt_prop_frags
10102 (segT
, segT
, xtensa_block_info
**, frag_flags_fn
);
10104 /* Set up property tables after relaxation. */
10107 xtensa_post_relax_hook (void)
10109 xtensa_move_seg_list_to_beginning (literal_head
);
10110 xtensa_move_seg_list_to_beginning (init_literal_head
);
10111 xtensa_move_seg_list_to_beginning (fini_literal_head
);
10113 xtensa_find_unmarked_state_frags ();
10115 if (use_literal_section
)
10116 xtensa_create_property_segments (get_frag_is_literal
,
10118 XTENSA_LIT_SEC_NAME
,
10120 xtensa_create_xproperty_segments (get_frag_property_flags
,
10121 XTENSA_PROP_SEC_NAME
,
10124 if (warn_unaligned_branch_targets
)
10125 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
10126 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
10130 /* This function is only meaningful after xtensa_move_literals. */
10133 get_frag_is_literal (const fragS
*fragP
)
10135 assert (fragP
!= NULL
);
10136 return fragP
->tc_frag_data
.is_literal
;
10141 xtensa_create_property_segments (frag_predicate property_function
,
10142 frag_predicate end_property_function
,
10143 const char *section_name_base
,
10144 xt_section_type sec_type
)
10148 /* Walk over all of the current segments.
10149 Walk over each fragment
10150 For each non-empty fragment,
10151 Build a property record (append where possible). */
10153 for (seclist
= &stdoutput
->sections
;
10154 seclist
&& *seclist
;
10155 seclist
= &(*seclist
)->next
)
10157 segT sec
= *seclist
;
10160 flags
= bfd_get_section_flags (stdoutput
, sec
);
10161 if (flags
& SEC_DEBUGGING
)
10163 if (!(flags
& SEC_ALLOC
))
10166 if (section_has_property (sec
, property_function
))
10168 char *property_section_name
=
10169 xtensa_get_property_section_name (sec
, section_name_base
);
10170 segT insn_sec
= retrieve_xtensa_section (property_section_name
);
10171 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10172 xtensa_block_info
**xt_blocks
=
10173 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10174 /* Walk over all of the frchains here and add new sections. */
10175 add_xt_block_frags (sec
, insn_sec
, xt_blocks
, property_function
,
10176 end_property_function
);
10180 /* Now we fill them out.... */
10182 for (seclist
= &stdoutput
->sections
;
10183 seclist
&& *seclist
;
10184 seclist
= &(*seclist
)->next
)
10186 segment_info_type
*seginfo
;
10187 xtensa_block_info
*block
;
10188 segT sec
= *seclist
;
10190 seginfo
= seg_info (sec
);
10191 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10195 xtensa_block_info
*cur_block
;
10196 /* This is a section with some data. */
10198 bfd_size_type rec_size
;
10200 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10203 rec_size
= num_recs
* 8;
10204 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10206 /* In order to make this work with the assembler, we have to
10207 build some frags and then build the "fixups" for it. It
10208 would be easier to just set the contents then set the
10213 /* Allocate a fragment and leak it. */
10215 bfd_size_type frag_size
;
10217 frchainS
*frchainP
;
10221 frag_size
= sizeof (fragS
) + rec_size
;
10222 fragP
= (fragS
*) xmalloc (frag_size
);
10224 memset (fragP
, 0, frag_size
);
10225 fragP
->fr_address
= 0;
10226 fragP
->fr_next
= NULL
;
10227 fragP
->fr_fix
= rec_size
;
10229 fragP
->fr_type
= rs_fill
;
10230 /* The rest are zeros. */
10232 frchainP
= seginfo
->frchainP
;
10233 frchainP
->frch_root
= fragP
;
10234 frchainP
->frch_last
= fragP
;
10236 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10237 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10239 seginfo
->fix_root
= fixes
;
10240 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10242 frag_data
= &fragP
->fr_literal
[0];
10243 for (i
= 0; i
< num_recs
; i
++)
10245 fixS
*fix
= &fixes
[i
];
10246 assert (cur_block
);
10248 /* Write the fixup. */
10249 if (i
!= num_recs
- 1)
10250 fix
->fx_next
= &fixes
[i
+ 1];
10252 fix
->fx_next
= NULL
;
10255 fix
->fx_frag
= fragP
;
10256 fix
->fx_where
= i
* 8;
10257 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10258 fix
->fx_offset
= cur_block
->offset
;
10259 fix
->fx_r_type
= BFD_RELOC_32
;
10260 fix
->fx_file
= "Internal Assembly";
10263 /* Write the length. */
10264 md_number_to_chars (&frag_data
[4 + 8 * i
],
10265 cur_block
->size
, 4);
10266 cur_block
= cur_block
->next
;
10275 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
10276 const char *section_name_base
,
10277 xt_section_type sec_type
)
10281 /* Walk over all of the current segments.
10282 Walk over each fragment.
10283 For each fragment that has instructions,
10284 build an instruction record (append where possible). */
10286 for (seclist
= &stdoutput
->sections
;
10287 seclist
&& *seclist
;
10288 seclist
= &(*seclist
)->next
)
10290 segT sec
= *seclist
;
10293 flags
= bfd_get_section_flags (stdoutput
, sec
);
10294 if ((flags
& SEC_DEBUGGING
)
10295 || !(flags
& SEC_ALLOC
)
10296 || (flags
& SEC_MERGE
))
10299 if (section_has_xproperty (sec
, flag_fn
))
10301 char *property_section_name
=
10302 xtensa_get_property_section_name (sec
, section_name_base
);
10303 segT insn_sec
= retrieve_xtensa_section (property_section_name
);
10304 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10305 xtensa_block_info
**xt_blocks
=
10306 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10307 /* Walk over all of the frchains here and add new sections. */
10308 add_xt_prop_frags (sec
, insn_sec
, xt_blocks
, flag_fn
);
10312 /* Now we fill them out.... */
10314 for (seclist
= &stdoutput
->sections
;
10315 seclist
&& *seclist
;
10316 seclist
= &(*seclist
)->next
)
10318 segment_info_type
*seginfo
;
10319 xtensa_block_info
*block
;
10320 segT sec
= *seclist
;
10322 seginfo
= seg_info (sec
);
10323 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10327 xtensa_block_info
*cur_block
;
10328 /* This is a section with some data. */
10330 bfd_size_type rec_size
;
10332 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10335 rec_size
= num_recs
* (8 + 4);
10336 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10338 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
10340 /* In order to make this work with the assembler, we have to build
10341 some frags then build the "fixups" for it. It would be easier to
10342 just set the contents then set the arlents. */
10346 /* Allocate a fragment and (unfortunately) leak it. */
10348 bfd_size_type frag_size
;
10350 frchainS
*frchainP
;
10354 frag_size
= sizeof (fragS
) + rec_size
;
10355 fragP
= (fragS
*) xmalloc (frag_size
);
10357 memset (fragP
, 0, frag_size
);
10358 fragP
->fr_address
= 0;
10359 fragP
->fr_next
= NULL
;
10360 fragP
->fr_fix
= rec_size
;
10362 fragP
->fr_type
= rs_fill
;
10363 /* The rest are zeros. */
10365 frchainP
= seginfo
->frchainP
;
10366 frchainP
->frch_root
= fragP
;
10367 frchainP
->frch_last
= fragP
;
10369 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10370 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10372 seginfo
->fix_root
= fixes
;
10373 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10375 frag_data
= &fragP
->fr_literal
[0];
10376 for (i
= 0; i
< num_recs
; i
++)
10378 fixS
*fix
= &fixes
[i
];
10379 assert (cur_block
);
10381 /* Write the fixup. */
10382 if (i
!= num_recs
- 1)
10383 fix
->fx_next
= &fixes
[i
+ 1];
10385 fix
->fx_next
= NULL
;
10388 fix
->fx_frag
= fragP
;
10389 fix
->fx_where
= i
* (8 + 4);
10390 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10391 fix
->fx_offset
= cur_block
->offset
;
10392 fix
->fx_r_type
= BFD_RELOC_32
;
10393 fix
->fx_file
= "Internal Assembly";
10396 /* Write the length. */
10397 md_number_to_chars (&frag_data
[4 + (8+4) * i
],
10398 cur_block
->size
, 4);
10399 md_number_to_chars (&frag_data
[8 + (8+4) * i
],
10400 frag_flags_to_number (&cur_block
->flags
),
10402 cur_block
= cur_block
->next
;
10410 static segment_info_type
*
10411 retrieve_segment_info (segT seg
)
10413 segment_info_type
*seginfo
;
10414 seginfo
= (segment_info_type
*) bfd_get_section_userdata (stdoutput
, seg
);
10417 frchainS
*frchainP
;
10419 seginfo
= (segment_info_type
*) xmalloc (sizeof (*seginfo
));
10420 memset ((void *) seginfo
, 0, sizeof (*seginfo
));
10421 seginfo
->fix_root
= NULL
;
10422 seginfo
->fix_tail
= NULL
;
10423 seginfo
->bfd_section
= seg
;
10425 /* We will not be dealing with these, only our special ones. */
10426 bfd_set_section_userdata (stdoutput
, seg
, (void *) seginfo
);
10428 frchainP
= (frchainS
*) xmalloc (sizeof (frchainS
));
10429 frchainP
->frch_root
= NULL
;
10430 frchainP
->frch_last
= NULL
;
10431 frchainP
->frch_next
= NULL
;
10432 frchainP
->frch_seg
= seg
;
10433 frchainP
->frch_subseg
= 0;
10434 frchainP
->fix_root
= NULL
;
10435 frchainP
->fix_tail
= NULL
;
10436 /* Do not init the objstack. */
10437 /* obstack_begin (&frchainP->frch_obstack, chunksize); */
10438 /* frchainP->frch_frag_now = fragP; */
10439 frchainP
->frch_frag_now
= NULL
;
10441 seginfo
->frchainP
= frchainP
;
10449 retrieve_xtensa_section (char *sec_name
)
10451 bfd
*abfd
= stdoutput
;
10452 flagword flags
, out_flags
, link_once_flags
;
10455 flags
= bfd_get_section_flags (abfd
, now_seg
);
10456 link_once_flags
= (flags
& SEC_LINK_ONCE
);
10457 if (link_once_flags
)
10458 link_once_flags
|= (flags
& SEC_LINK_DUPLICATES
);
10459 out_flags
= (SEC_RELOC
| SEC_HAS_CONTENTS
| SEC_READONLY
| link_once_flags
);
10461 s
= bfd_make_section_old_way (abfd
, sec_name
);
10463 as_bad (_("could not create section %s"), sec_name
);
10464 if (!bfd_set_section_flags (abfd
, s
, out_flags
))
10465 as_bad (_("invalid flag combination on section %s"), sec_name
);
10472 section_has_property (segT sec
, frag_predicate property_function
)
10474 segment_info_type
*seginfo
= seg_info (sec
);
10477 if (seginfo
&& seginfo
->frchainP
)
10479 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10481 if (property_function (fragP
)
10482 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10491 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
10493 segment_info_type
*seginfo
= seg_info (sec
);
10496 if (seginfo
&& seginfo
->frchainP
)
10498 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10500 frag_flags prop_flags
;
10501 property_function (fragP
, &prop_flags
);
10502 if (!xtensa_frag_flags_is_empty (&prop_flags
))
10510 /* Two types of block sections exist right now: literal and insns. */
10513 add_xt_block_frags (segT sec
,
10515 xtensa_block_info
**xt_block
,
10516 frag_predicate property_function
,
10517 frag_predicate end_property_function
)
10519 segment_info_type
*seg_info
;
10520 segment_info_type
*xt_seg_info
;
10521 bfd_vma seg_offset
;
10524 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
10525 seg_info
= retrieve_segment_info (sec
);
10527 /* Build it if needed. */
10528 while (*xt_block
!= NULL
)
10529 xt_block
= &(*xt_block
)->next
;
10530 /* We are either at NULL at the beginning or at the end. */
10532 /* Walk through the frags. */
10535 if (seg_info
->frchainP
)
10537 for (fragP
= seg_info
->frchainP
->frch_root
;
10539 fragP
= fragP
->fr_next
)
10541 if (property_function (fragP
)
10542 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10544 if (*xt_block
!= NULL
)
10546 if ((*xt_block
)->offset
+ (*xt_block
)->size
10547 == fragP
->fr_address
)
10548 (*xt_block
)->size
+= fragP
->fr_fix
;
10550 xt_block
= &((*xt_block
)->next
);
10552 if (*xt_block
== NULL
)
10554 xtensa_block_info
*new_block
= (xtensa_block_info
*)
10555 xmalloc (sizeof (xtensa_block_info
));
10556 new_block
->sec
= sec
;
10557 new_block
->offset
= fragP
->fr_address
;
10558 new_block
->size
= fragP
->fr_fix
;
10559 new_block
->next
= NULL
;
10560 xtensa_frag_flags_init (&new_block
->flags
);
10561 *xt_block
= new_block
;
10563 if (end_property_function
10564 && end_property_function (fragP
))
10566 xt_block
= &((*xt_block
)->next
);
10574 /* Break the encapsulation of add_xt_prop_frags here. */
10577 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
10579 if (prop_flags
->is_literal
10580 || prop_flags
->is_insn
10581 || prop_flags
->is_data
10582 || prop_flags
->is_unreachable
)
10589 xtensa_frag_flags_init (frag_flags
*prop_flags
)
10591 memset (prop_flags
, 0, sizeof (frag_flags
));
10596 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
10598 xtensa_frag_flags_init (prop_flags
);
10599 if (fragP
->tc_frag_data
.is_literal
)
10600 prop_flags
->is_literal
= TRUE
;
10601 if (fragP
->tc_frag_data
.is_unreachable
)
10602 prop_flags
->is_unreachable
= TRUE
;
10603 else if (fragP
->tc_frag_data
.is_insn
)
10605 prop_flags
->is_insn
= TRUE
;
10606 if (fragP
->tc_frag_data
.is_loop_target
)
10607 prop_flags
->insn
.is_loop_target
= TRUE
;
10608 if (fragP
->tc_frag_data
.is_branch_target
)
10609 prop_flags
->insn
.is_branch_target
= TRUE
;
10610 if (fragP
->tc_frag_data
.is_specific_opcode
10611 || fragP
->tc_frag_data
.is_no_transform
)
10612 prop_flags
->insn
.is_no_transform
= TRUE
;
10613 if (fragP
->tc_frag_data
.is_no_density
)
10614 prop_flags
->insn
.is_no_density
= TRUE
;
10615 if (fragP
->tc_frag_data
.use_absolute_literals
)
10616 prop_flags
->insn
.is_abslit
= TRUE
;
10618 if (fragP
->tc_frag_data
.is_align
)
10620 prop_flags
->is_align
= TRUE
;
10621 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
10622 if (xtensa_frag_flags_is_empty (prop_flags
))
10623 prop_flags
->is_data
= TRUE
;
10629 frag_flags_to_number (const frag_flags
*prop_flags
)
10632 if (prop_flags
->is_literal
)
10633 num
|= XTENSA_PROP_LITERAL
;
10634 if (prop_flags
->is_insn
)
10635 num
|= XTENSA_PROP_INSN
;
10636 if (prop_flags
->is_data
)
10637 num
|= XTENSA_PROP_DATA
;
10638 if (prop_flags
->is_unreachable
)
10639 num
|= XTENSA_PROP_UNREACHABLE
;
10640 if (prop_flags
->insn
.is_loop_target
)
10641 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
10642 if (prop_flags
->insn
.is_branch_target
)
10644 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
10645 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
10648 if (prop_flags
->insn
.is_no_density
)
10649 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
10650 if (prop_flags
->insn
.is_no_transform
)
10651 num
|= XTENSA_PROP_INSN_NO_TRANSFORM
;
10652 if (prop_flags
->insn
.is_no_reorder
)
10653 num
|= XTENSA_PROP_INSN_NO_REORDER
;
10654 if (prop_flags
->insn
.is_abslit
)
10655 num
|= XTENSA_PROP_INSN_ABSLIT
;
10657 if (prop_flags
->is_align
)
10659 num
|= XTENSA_PROP_ALIGN
;
10660 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
10668 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
10669 const frag_flags
*prop_flags_2
)
10671 /* Cannot combine with an end marker. */
10673 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
10675 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
10677 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
10680 if (prop_flags_1
->is_insn
)
10682 /* Properties of the beginning of the frag. */
10683 if (prop_flags_2
->insn
.is_loop_target
)
10685 if (prop_flags_2
->insn
.is_branch_target
)
10687 if (prop_flags_1
->insn
.is_no_density
!=
10688 prop_flags_2
->insn
.is_no_density
)
10690 if (prop_flags_1
->insn
.is_no_transform
!=
10691 prop_flags_2
->insn
.is_no_transform
)
10693 if (prop_flags_1
->insn
.is_no_reorder
!=
10694 prop_flags_2
->insn
.is_no_reorder
)
10696 if (prop_flags_1
->insn
.is_abslit
!=
10697 prop_flags_2
->insn
.is_abslit
)
10701 if (prop_flags_1
->is_align
)
10709 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
10712 unsigned align_bits
;
10714 if (!xt_block
->flags
.is_align
)
10715 return xt_block
->size
;
10717 end_addr
= xt_block
->offset
+ xt_block
->size
;
10718 align_bits
= xt_block
->flags
.alignment
;
10719 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
10720 return end_addr
- xt_block
->offset
;
10725 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
10726 const xtensa_block_info
*xt_block_2
)
10728 if (xt_block
->sec
!= xt_block_2
->sec
)
10730 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
10731 != xt_block_2
->offset
)
10734 if (xt_block_2
->size
== 0
10735 && (!xt_block_2
->flags
.is_unreachable
10736 || xt_block
->flags
.is_unreachable
))
10738 if (xt_block_2
->flags
.is_align
10739 && xt_block
->flags
.is_align
)
10741 /* Nothing needed. */
10742 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
10747 if (xt_block_2
->flags
.is_align
)
10749 /* Push alignment to previous entry. */
10750 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
10751 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10756 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
10757 &xt_block_2
->flags
))
10760 xt_block
->size
+= xt_block_2
->size
;
10762 if (xt_block_2
->flags
.is_align
)
10764 xt_block
->flags
.is_align
= TRUE
;
10765 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10773 add_xt_prop_frags (segT sec
,
10775 xtensa_block_info
**xt_block
,
10776 frag_flags_fn property_function
)
10778 segment_info_type
*seg_info
;
10779 segment_info_type
*xt_seg_info
;
10780 bfd_vma seg_offset
;
10783 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
10784 seg_info
= retrieve_segment_info (sec
);
10785 /* Build it if needed. */
10786 while (*xt_block
!= NULL
)
10788 xt_block
= &(*xt_block
)->next
;
10790 /* We are either at NULL at the beginning or at the end. */
10792 /* Walk through the frags. */
10795 if (seg_info
->frchainP
)
10797 for (fragP
= seg_info
->frchainP
->frch_root
; fragP
;
10798 fragP
= fragP
->fr_next
)
10800 xtensa_block_info tmp_block
;
10801 tmp_block
.sec
= sec
;
10802 tmp_block
.offset
= fragP
->fr_address
;
10803 tmp_block
.size
= fragP
->fr_fix
;
10804 tmp_block
.next
= NULL
;
10805 property_function (fragP
, &tmp_block
.flags
);
10807 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
10808 /* && fragP->fr_fix != 0) */
10810 if ((*xt_block
) == NULL
10811 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
10813 xtensa_block_info
*new_block
;
10814 if ((*xt_block
) != NULL
)
10815 xt_block
= &(*xt_block
)->next
;
10816 new_block
= (xtensa_block_info
*)
10817 xmalloc (sizeof (xtensa_block_info
));
10818 *new_block
= tmp_block
;
10819 *xt_block
= new_block
;
10827 /* op_placement_info_table */
10829 /* op_placement_info makes it easier to determine which
10830 ops can go in which slots. */
10833 init_op_placement_info_table (void)
10835 xtensa_isa isa
= xtensa_default_isa
;
10836 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
10837 xtensa_opcode opcode
;
10840 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
10842 op_placement_table
= (op_placement_info_table
)
10843 xmalloc (sizeof (op_placement_info
) * num_opcodes
);
10844 assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
10846 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
10848 op_placement_info
*opi
= &op_placement_table
[opcode
];
10849 /* FIXME: Make tinsn allocation dynamic. */
10850 if (xtensa_opcode_num_operands (isa
, opcode
) >= MAX_INSN_ARGS
)
10851 as_fatal (_("too many operands in instruction"));
10852 opi
->single
= XTENSA_UNDEFINED
;
10853 opi
->single_size
= 0;
10854 opi
->widest
= XTENSA_UNDEFINED
;
10855 opi
->widest_size
= 0;
10856 opi
->narrowest
= XTENSA_UNDEFINED
;
10857 opi
->narrowest_size
= 0x7F;
10859 opi
->num_formats
= 0;
10861 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
10863 opi
->slots
[fmt
] = 0;
10864 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
10866 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
10868 int fmt_length
= xtensa_format_length (isa
, fmt
);
10870 set_bit (fmt
, opi
->formats
);
10871 set_bit (slot
, opi
->slots
[fmt
]);
10872 /* opi->slot_count[fmt]++; */
10873 if (fmt_length
< opi
->narrowest_size
)
10875 opi
->narrowest
= fmt
;
10876 opi
->narrowest_size
= fmt_length
;
10878 if (fmt_length
> opi
->widest_size
)
10881 opi
->widest_size
= fmt_length
;
10883 if (xtensa_format_num_slots (isa
, fmt
) == 1)
10885 if (opi
->single_size
== 0
10886 || fmt_length
< opi
->single_size
)
10889 opi
->single_size
= fmt_length
;
10895 opi
->num_formats
++;
10898 xtensa_insnbuf_free (isa
, ibuf
);
10903 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
10905 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
10909 /* If the opcode is available in a single slot format, return its size. */
10912 xg_get_single_size (xtensa_opcode opcode
)
10914 assert (op_placement_table
[opcode
].single
!= XTENSA_UNDEFINED
);
10915 return op_placement_table
[opcode
].single_size
;
10919 static xtensa_format
10920 xg_get_single_format (xtensa_opcode opcode
)
10922 return op_placement_table
[opcode
].single
;
10926 /* Instruction Stack Functions (from "xtensa-istack.h"). */
10929 istack_init (IStack
*stack
)
10931 memset (stack
, 0, sizeof (IStack
));
10937 istack_empty (IStack
*stack
)
10939 return (stack
->ninsn
== 0);
10944 istack_full (IStack
*stack
)
10946 return (stack
->ninsn
== MAX_ISTACK
);
10950 /* Return a pointer to the top IStack entry.
10951 It is an error to call this if istack_empty () is TRUE. */
10954 istack_top (IStack
*stack
)
10956 int rec
= stack
->ninsn
- 1;
10957 assert (!istack_empty (stack
));
10958 return &stack
->insn
[rec
];
10962 /* Add a new TInsn to an IStack.
10963 It is an error to call this if istack_full () is TRUE. */
10966 istack_push (IStack
*stack
, TInsn
*insn
)
10968 int rec
= stack
->ninsn
;
10969 assert (!istack_full (stack
));
10970 stack
->insn
[rec
] = *insn
;
10975 /* Clear space for the next TInsn on the IStack and return a pointer
10976 to it. It is an error to call this if istack_full () is TRUE. */
10979 istack_push_space (IStack
*stack
)
10981 int rec
= stack
->ninsn
;
10983 assert (!istack_full (stack
));
10984 insn
= &stack
->insn
[rec
];
10985 memset (insn
, 0, sizeof (TInsn
));
10991 /* Remove the last pushed instruction. It is an error to call this if
10992 istack_empty () returns TRUE. */
10995 istack_pop (IStack
*stack
)
10997 int rec
= stack
->ninsn
- 1;
10998 assert (!istack_empty (stack
));
11000 memset (&stack
->insn
[rec
], 0, sizeof (TInsn
));
11004 /* TInsn functions. */
11007 tinsn_init (TInsn
*dst
)
11009 memset (dst
, 0, sizeof (TInsn
));
11013 /* Get the ``num''th token of the TInsn.
11014 It is illegal to call this if num > insn->ntoks. */
11017 tinsn_get_tok (TInsn
*insn
, int num
)
11019 assert (num
< insn
->ntok
);
11020 return &insn
->tok
[num
];
11024 /* Return TRUE if ANY of the operands in the insn are symbolic. */
11027 tinsn_has_symbolic_operands (const TInsn
*insn
)
11030 int n
= insn
->ntok
;
11032 assert (insn
->insn_type
== ITYPE_INSN
);
11034 for (i
= 0; i
< n
; ++i
)
11036 switch (insn
->tok
[i
].X_op
)
11050 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
11052 xtensa_isa isa
= xtensa_default_isa
;
11054 int n
= insn
->ntok
;
11056 assert (insn
->insn_type
== ITYPE_INSN
);
11058 for (i
= 0; i
< n
; ++i
)
11060 switch (insn
->tok
[i
].X_op
)
11068 /* Errors for these types are caught later. */
11073 /* Symbolic immediates are only allowed on the last immediate
11074 operand. At this time, CONST16 is the only opcode where we
11075 support non-PC-relative relocations. (It isn't necessary
11076 to complain about non-PC-relative relocations here, but
11077 otherwise, no error is reported until the relocations are
11078 generated, and the assembler won't get that far if there
11079 are any other errors. It's nice to see all the problems
11081 if (i
!= get_relaxable_immed (insn
->opcode
)
11082 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
11083 && insn
->opcode
!= xtensa_const16_opcode
))
11085 as_bad (_("invalid symbolic operand %d on '%s'"),
11086 i
, xtensa_opcode_name (isa
, insn
->opcode
));
11095 /* For assembly code with complex expressions (e.g. subtraction),
11096 we have to build them in the literal pool so that
11097 their results are calculated correctly after relaxation.
11098 The relaxation only handles expressions that
11099 boil down to SYMBOL + OFFSET. */
11102 tinsn_has_complex_operands (const TInsn
*insn
)
11105 int n
= insn
->ntok
;
11106 assert (insn
->insn_type
== ITYPE_INSN
);
11107 for (i
= 0; i
< n
; ++i
)
11109 switch (insn
->tok
[i
].X_op
)
11125 /* Convert the constant operands in the tinsn to insnbuf.
11126 Return TRUE if there is a symbol in the immediate field.
11128 Before this is called,
11129 1) the number of operands are correct
11130 2) the tinsn is a ITYPE_INSN
11131 3) ONLY the relaxable_ is built
11132 4) All operands are O_constant, O_symbol. All constants fit
11133 The return value tells whether there are any remaining O_symbols. */
11136 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
11138 static xtensa_insnbuf slotbuf
= 0;
11139 xtensa_isa isa
= xtensa_default_isa
;
11140 xtensa_opcode opcode
= tinsn
->opcode
;
11141 xtensa_format fmt
= xg_get_single_format (opcode
);
11142 bfd_boolean has_fixup
= FALSE
;
11143 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11150 slotbuf
= xtensa_insnbuf_alloc (isa
);
11152 assert (tinsn
->insn_type
== ITYPE_INSN
);
11153 if (noperands
!= tinsn
->ntok
)
11154 as_fatal (_("operand number mismatch"));
11156 if (xtensa_opcode_encode (isa
, fmt
, 0, slotbuf
, opcode
))
11157 as_fatal (_("cannot encode opcode"));
11159 for (i
= 0; i
< noperands
; ++i
)
11161 expressionS
*expr
= &tinsn
->tok
[i
];
11162 switch (expr
->X_op
)
11165 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11167 /* The register number has already been checked in
11168 expression_maybe_register, so we don't need to check here. */
11169 opnd_value
= expr
->X_add_number
;
11170 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11171 xtensa_operand_set_field (isa
, opcode
, i
, fmt
, 0,
11172 slotbuf
, opnd_value
);
11176 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11178 as_where (&file_name
, &line
);
11179 /* It is a constant and we called this function,
11180 then we have to try to fit it. */
11181 xtensa_insnbuf_set_operand (slotbuf
, fmt
, 0, opcode
, i
,
11182 expr
->X_add_number
, file_name
, line
);
11191 xtensa_format_encode (isa
, fmt
, insnbuf
);
11192 xtensa_format_set_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
11198 /* Convert the constant operands in the tinsn to slotbuf.
11199 Return TRUE if there is a symbol in the immediate field.
11200 (Eventually this should replace tinsn_to_insnbuf.) */
11202 /* Before this is called,
11203 1) the number of operands are correct
11204 2) the tinsn is a ITYPE_INSN
11205 3) ONLY the relaxable_ is built
11206 4) All operands are
11207 O_constant, O_symbol
11210 The return value tells whether there are any remaining O_symbols. */
11213 tinsn_to_slotbuf (xtensa_format fmt
,
11216 xtensa_insnbuf slotbuf
)
11218 xtensa_isa isa
= xtensa_default_isa
;
11219 xtensa_opcode opcode
= tinsn
->opcode
;
11220 bfd_boolean has_fixup
= FALSE
;
11221 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11224 *((int *) &slotbuf
[0]) = 0;
11225 *((int *) &slotbuf
[1]) = 0;
11226 assert (tinsn
->insn_type
== ITYPE_INSN
);
11227 if (noperands
!= tinsn
->ntok
)
11228 as_fatal (_("operand number mismatch"));
11230 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
11232 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
11233 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
11237 for (i
= 0; i
< noperands
; i
++)
11239 expressionS
*expr
= &tinsn
->tok
[i
];
11245 switch (expr
->X_op
)
11248 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11250 /* The register number has already been checked in
11251 expression_maybe_register, so we don't need to check here. */
11252 opnd_value
= expr
->X_add_number
;
11253 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11254 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
11257 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
11261 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11263 as_where (&file_name
, &line
);
11264 /* It is a constant and we called this function
11265 then we have to try to fit it. */
11266 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
11267 expr
->X_add_number
, file_name
, line
);
11280 /* Check the instruction arguments. Return TRUE on failure. */
11283 tinsn_check_arguments (const TInsn
*insn
)
11285 xtensa_isa isa
= xtensa_default_isa
;
11286 xtensa_opcode opcode
= insn
->opcode
;
11288 if (opcode
== XTENSA_UNDEFINED
)
11290 as_bad (_("invalid opcode"));
11294 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
11296 as_bad (_("too few operands"));
11300 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
11302 as_bad (_("too many operands"));
11309 /* Load an instruction from its encoded form. */
11312 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
11316 xg_init_vinsn (&vinsn
);
11317 vinsn_from_chars (&vinsn
, f
);
11319 *tinsn
= vinsn
.slots
[slot
];
11320 xg_free_vinsn (&vinsn
);
11325 tinsn_from_insnbuf (TInsn
*tinsn
,
11326 xtensa_insnbuf slotbuf
,
11331 xtensa_isa isa
= xtensa_default_isa
;
11333 /* Find the immed. */
11334 tinsn_init (tinsn
);
11335 tinsn
->insn_type
= ITYPE_INSN
;
11336 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
11337 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
11338 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
11339 for (i
= 0; i
< tinsn
->ntok
; i
++)
11341 set_expr_const (&tinsn
->tok
[i
],
11342 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
11343 tinsn
->opcode
, i
));
11348 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
11351 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
11353 xtensa_opcode opcode
= tinsn
->opcode
;
11356 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
11358 opnum
= get_relaxable_immed (opcode
);
11359 assert (opnum
>= 0);
11360 if (fragP
->tc_frag_data
.slot_sub_symbols
[slot
])
11362 set_expr_symbol_offset_diff
11363 (&tinsn
->tok
[opnum
],
11364 fragP
->tc_frag_data
.slot_symbols
[slot
],
11365 fragP
->tc_frag_data
.slot_sub_symbols
[slot
],
11366 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11370 set_expr_symbol_offset
11371 (&tinsn
->tok
[opnum
],
11372 fragP
->tc_frag_data
.slot_symbols
[slot
],
11373 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11380 get_num_stack_text_bytes (IStack
*istack
)
11383 int text_bytes
= 0;
11385 for (i
= 0; i
< istack
->ninsn
; i
++)
11387 TInsn
*tinsn
= &istack
->insn
[i
];
11388 if (tinsn
->insn_type
== ITYPE_INSN
)
11389 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
11396 get_num_stack_literal_bytes (IStack
*istack
)
11401 for (i
= 0; i
< istack
->ninsn
; i
++)
11403 TInsn
*tinsn
= &istack
->insn
[i
];
11404 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
11411 /* vliw_insn functions. */
11414 xg_init_vinsn (vliw_insn
*v
)
11417 xtensa_isa isa
= xtensa_default_isa
;
11419 xg_clear_vinsn (v
);
11421 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
11422 if (v
->insnbuf
== NULL
)
11423 as_fatal (_("out of memory"));
11425 for (i
= 0; i
< MAX_SLOTS
; i
++)
11427 tinsn_init (&v
->slots
[i
]);
11428 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
11429 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
11430 if (v
->slotbuf
[i
] == NULL
)
11431 as_fatal (_("out of memory"));
11437 xg_clear_vinsn (vliw_insn
*v
)
11440 v
->format
= XTENSA_UNDEFINED
;
11442 v
->inside_bundle
= FALSE
;
11444 if (xt_saved_debug_type
!= DEBUG_NONE
)
11445 debug_type
= xt_saved_debug_type
;
11447 for (i
= 0; i
< MAX_SLOTS
; i
++)
11449 memset (&v
->slots
[i
], 0, sizeof (TInsn
));
11450 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
11456 vinsn_has_specific_opcodes (vliw_insn
*v
)
11460 for (i
= 0; i
< v
->num_slots
; i
++)
11462 if (v
->slots
[i
].is_specific_opcode
)
11470 xg_free_vinsn (vliw_insn
*v
)
11473 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
11474 for (i
= 0; i
< MAX_SLOTS
; i
++)
11475 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
11479 /* Before this is called, we should have
11480 filled out the following fields:
11482 1) the number of operands for each opcode are correct
11483 2) the tinsn in the slots are ITYPE_INSN
11484 3) ONLY the relaxable_ is built
11485 4) All operands are
11486 O_constant, O_symbol
11489 The return value tells whether there are any remaining O_symbols. */
11492 vinsn_to_insnbuf (vliw_insn
*vinsn
,
11495 bfd_boolean record_fixup
)
11497 xtensa_isa isa
= xtensa_default_isa
;
11498 xtensa_format fmt
= vinsn
->format
;
11499 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
11501 bfd_boolean has_fixup
= FALSE
;
11503 xtensa_format_encode (isa
, fmt
, insnbuf
);
11505 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
11507 TInsn
*tinsn
= &vinsn
->slots
[slot
];
11508 bfd_boolean tinsn_has_fixup
=
11509 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
11510 vinsn
->slotbuf
[slot
]);
11512 xtensa_format_set_slot (isa
, fmt
, slot
,
11513 insnbuf
, vinsn
->slotbuf
[slot
]);
11514 /* tinsn_has_fixup tracks if there is a fixup at all.
11515 record_fixup controls globally. I.E., we use this
11516 function from several places, some of which are after
11517 fixups have already been recorded. Finally,
11518 tinsn->record_fixup controls based on the individual ops,
11519 which may or may not need it based on the relaxation
11521 if (tinsn_has_fixup
&& record_fixup
)
11524 xtensa_opcode opcode
= tinsn
->opcode
;
11525 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11528 for (i
= 0; i
< noperands
; i
++)
11530 expressionS
* expr
= &tinsn
->tok
[i
];
11531 switch (expr
->X_op
)
11536 if (get_relaxable_immed (opcode
) == i
)
11538 if (tinsn
->record_fix
|| expr
->X_op
!= O_symbol
)
11540 if (!xg_add_opcode_fix
11541 (tinsn
, i
, fmt
, slot
, expr
, fragP
,
11542 frag_offset
- fragP
->fr_literal
))
11543 as_bad (_("instruction with constant operands does not fit"));
11547 tinsn
->symbol
= expr
->X_add_symbol
;
11548 tinsn
->offset
= expr
->X_add_number
;
11552 as_bad (_("invalid operand %d on '%s'"),
11553 i
, xtensa_opcode_name (isa
, opcode
));
11561 if (get_relaxable_immed (opcode
) == i
)
11563 if (tinsn
->record_fix
)
11564 as_bad (_("invalid subtract operand"));
11567 tinsn
->symbol
= expr
->X_add_symbol
;
11568 tinsn
->sub_symbol
= expr
->X_op_symbol
;
11569 tinsn
->offset
= expr
->X_add_number
;
11573 as_bad (_("invalid operand %d on '%s'"),
11574 i
, xtensa_opcode_name (isa
, opcode
));
11578 as_bad (_("invalid expression for operand %d on '%s'"),
11579 i
, xtensa_opcode_name (isa
, opcode
));
11591 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
11593 static xtensa_insnbuf insnbuf
= NULL
;
11594 static xtensa_insnbuf slotbuf
= NULL
;
11597 xtensa_isa isa
= xtensa_default_isa
;
11601 insnbuf
= xtensa_insnbuf_alloc (isa
);
11602 slotbuf
= xtensa_insnbuf_alloc (isa
);
11605 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) f
, 0);
11606 fmt
= xtensa_format_decode (isa
, insnbuf
);
11607 if (fmt
== XTENSA_UNDEFINED
)
11608 as_fatal (_("cannot decode instruction format"));
11609 vinsn
->format
= fmt
;
11610 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
11612 for (i
= 0; i
< vinsn
->num_slots
; i
++)
11614 TInsn
*tinsn
= &vinsn
->slots
[i
];
11615 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
11616 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
11621 /* Expression utilities. */
11623 /* Return TRUE if the expression is an integer constant. */
11626 expr_is_const (const expressionS
*s
)
11628 return (s
->X_op
== O_constant
);
11632 /* Get the expression constant.
11633 Calling this is illegal if expr_is_const () returns TRUE. */
11636 get_expr_const (const expressionS
*s
)
11638 assert (expr_is_const (s
));
11639 return s
->X_add_number
;
11643 /* Set the expression to a constant value. */
11646 set_expr_const (expressionS
*s
, offsetT val
)
11648 s
->X_op
= O_constant
;
11649 s
->X_add_number
= val
;
11650 s
->X_add_symbol
= NULL
;
11651 s
->X_op_symbol
= NULL
;
11656 expr_is_register (const expressionS
*s
)
11658 return (s
->X_op
== O_register
);
11662 /* Get the expression constant.
11663 Calling this is illegal if expr_is_const () returns TRUE. */
11666 get_expr_register (const expressionS
*s
)
11668 assert (expr_is_register (s
));
11669 return s
->X_add_number
;
11673 /* Set the expression to a symbol + constant offset. */
11676 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
11678 s
->X_op
= O_symbol
;
11679 s
->X_add_symbol
= sym
;
11680 s
->X_op_symbol
= NULL
; /* unused */
11681 s
->X_add_number
= offset
;
11685 /* Set the expression to symbol - minus_sym + offset. */
11688 set_expr_symbol_offset_diff (expressionS
*s
,
11690 symbolS
*minus_sym
,
11693 s
->X_op
= O_subtract
;
11694 s
->X_add_symbol
= sym
;
11695 s
->X_op_symbol
= minus_sym
; /* unused */
11696 s
->X_add_number
= offset
;
11700 /* Return TRUE if the two expressions are equal. */
11703 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
11705 if (s1
->X_op
!= s2
->X_op
)
11707 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
11709 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
11711 if (s1
->X_add_number
!= s2
->X_add_number
)
11718 copy_expr (expressionS
*dst
, const expressionS
*src
)
11720 memcpy (dst
, src
, sizeof (expressionS
));
11724 /* Support for the "--rename-section" option. */
11726 struct rename_section_struct
11730 struct rename_section_struct
*next
;
11733 static struct rename_section_struct
*section_rename
;
11736 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
11737 entries to the section_rename list. Note: Specifying multiple
11738 renamings separated by colons is not documented and is retained only
11739 for backward compatibility. */
11742 build_section_rename (const char *arg
)
11744 struct rename_section_struct
*r
;
11745 char *this_arg
= NULL
;
11746 char *next_arg
= NULL
;
11748 for (this_arg
= xstrdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
11750 char *old_name
, *new_name
;
11754 next_arg
= strchr (this_arg
, ':');
11762 old_name
= this_arg
;
11763 new_name
= strchr (this_arg
, '=');
11765 if (*old_name
== '\0')
11767 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
11770 if (!new_name
|| new_name
[1] == '\0')
11772 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
11779 /* Check for invalid section renaming. */
11780 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11782 if (strcmp (r
->old_name
, old_name
) == 0)
11783 as_bad (_("section %s renamed multiple times"), old_name
);
11784 if (strcmp (r
->new_name
, new_name
) == 0)
11785 as_bad (_("multiple sections remapped to output section %s"),
11790 r
= (struct rename_section_struct
*)
11791 xmalloc (sizeof (struct rename_section_struct
));
11792 r
->old_name
= xstrdup (old_name
);
11793 r
->new_name
= xstrdup (new_name
);
11794 r
->next
= section_rename
;
11795 section_rename
= r
;
11801 xtensa_section_rename (char *name
)
11803 struct rename_section_struct
*r
= section_rename
;
11805 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11807 if (strcmp (r
->old_name
, name
) == 0)
11808 return r
->new_name
;