1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
24 #include "safe-ctype.h"
25 #include "tc-xtensa.h"
27 #include "xtensa-relax.h"
28 #include "xtensa-istack.h"
29 #include "dwarf2dbg.h"
30 #include "struc-symbol.h"
31 #include "xtensa-config.h"
34 #define uint32 unsigned int
37 #define int32 signed int
42 Naming conventions (used somewhat inconsistently):
43 The xtensa_ functions are exported
44 The xg_ functions are internal
46 We also have a couple of different extensibility mechanisms.
47 1) The idiom replacement:
48 This is used when a line is first parsed to
49 replace an instruction pattern with another instruction
50 It is currently limited to replacements of instructions
51 with constant operands.
52 2) The xtensa-relax.c mechanism that has stronger instruction
53 replacement patterns. When an instruction's immediate field
54 does not fit the next instruction sequence is attempted.
55 In addition, "narrow" opcodes are supported this way. */
58 /* Define characters with special meanings to GAS. */
59 const char comment_chars
[] = "#";
60 const char line_comment_chars
[] = "#";
61 const char line_separator_chars
[] = ";";
62 const char EXP_CHARS
[] = "eE";
63 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
66 /* Flags to indicate whether the hardware supports the density and
67 absolute literals options. */
69 bfd_boolean density_supported
= XCHAL_HAVE_DENSITY
;
70 bfd_boolean absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
72 /* Maximum width we would pad an unreachable frag to get alignment. */
73 #define UNREACHABLE_MAX_WIDTH 8
75 static vliw_insn cur_vinsn
;
77 unsigned xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
79 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
81 /* Some functions are only valid in the front end. This variable
82 allows us to assert that we haven't crossed over into the
84 static bfd_boolean past_xtensa_end
= FALSE
;
86 /* Flags for properties of the last instruction in a segment. */
87 #define FLAG_IS_A0_WRITER 0x1
88 #define FLAG_IS_BAD_LOOPEND 0x2
91 /* We define a special segment names ".literal" to place literals
92 into. The .fini and .init sections are special because they
93 contain code that is moved together by the linker. We give them
94 their own special .fini.literal and .init.literal sections. */
96 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
97 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
98 #define INIT_SECTION_NAME xtensa_section_rename (".init")
99 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
102 /* This type is used for the directive_stack to keep track of the
103 state of the literal collection pools. If lit_prefix is set, it is
104 used to determine the literal section names; otherwise, the literal
105 sections are determined based on the current text section. The
106 lit_seg and lit4_seg fields cache these literal sections, with the
107 current_text_seg field used a tag to indicate whether the cached
110 typedef struct lit_state_struct
113 segT current_text_seg
;
118 static lit_state default_lit_sections
;
121 /* We keep a list of literal segments. The seg_list type is the node
122 for this list. The literal_head pointer is the head of the list,
123 with the literal_head_h dummy node at the start. */
125 typedef struct seg_list_struct
127 struct seg_list_struct
*next
;
131 static seg_list literal_head_h
;
132 static seg_list
*literal_head
= &literal_head_h
;
135 /* Lists of symbols. We keep a list of symbols that label the current
136 instruction, so that we can adjust the symbols when inserting alignment
137 for various instructions. We also keep a list of all the symbols on
138 literals, so that we can fix up those symbols when the literals are
139 later moved into the text sections. */
141 typedef struct sym_list_struct
143 struct sym_list_struct
*next
;
147 static sym_list
*insn_labels
= NULL
;
148 static sym_list
*free_insn_labels
= NULL
;
149 static sym_list
*saved_insn_labels
= NULL
;
151 static sym_list
*literal_syms
;
154 /* Flags to determine whether to prefer const16 or l32r
155 if both options are available. */
156 int prefer_const16
= 0;
159 /* Global flag to indicate when we are emitting literals. */
160 int generating_literals
= 0;
162 /* The following PROPERTY table definitions are copied from
163 <elf/xtensa.h> and must be kept in sync with the code there. */
165 /* Flags in the property tables to specify whether blocks of memory
166 are literals, instructions, data, or unreachable. For
167 instructions, blocks that begin loop targets and branch targets are
168 designated. Blocks that do not allow density, instruction
169 reordering or transformation are also specified. Finally, for
170 branch targets, branch target alignment priority is included.
171 Alignment of the next block is specified in the current block
172 and the size of the current block does not include any fill required
173 to align to the next block. */
175 #define XTENSA_PROP_LITERAL 0x00000001
176 #define XTENSA_PROP_INSN 0x00000002
177 #define XTENSA_PROP_DATA 0x00000004
178 #define XTENSA_PROP_UNREACHABLE 0x00000008
179 /* Instruction only properties at beginning of code. */
180 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
181 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
182 /* Instruction only properties about code. */
183 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
184 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
185 #define XTENSA_PROP_INSN_NO_TRANSFORM 0x00000100
187 /* Branch target alignment information. This transmits information
188 to the linker optimization about the priority of aligning a
189 particular block for branch target alignment: None, low priority,
190 high priority, or required. These only need to be checked in
191 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
194 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
195 case XTENSA_PROP_BT_ALIGN_NONE:
196 case XTENSA_PROP_BT_ALIGN_LOW:
197 case XTENSA_PROP_BT_ALIGN_HIGH:
198 case XTENSA_PROP_BT_ALIGN_REQUIRE:
200 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
202 /* No branch target alignment. */
203 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
204 /* Low priority branch target alignment. */
205 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
206 /* High priority branch target alignment. */
207 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
208 /* Required branch target alignment. */
209 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
211 #define GET_XTENSA_PROP_BT_ALIGN(flag) \
212 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
213 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
214 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
215 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
218 /* Alignment is specified in the block BEFORE the one that needs
219 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
220 get the required alignment specified as a power of 2. Use
221 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
222 alignment. Be careful of side effects since the SET will evaluate
223 flags twice. Also, note that the SIZE of a block in the property
224 table does not include the alignment size, so the alignment fill
225 must be calculated to determine if two blocks are contiguous.
226 TEXT_ALIGN is not currently implemented but is a placeholder for a
227 possible future implementation. */
229 #define XTENSA_PROP_ALIGN 0x00000800
231 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
233 #define GET_XTENSA_PROP_ALIGNMENT(flag) \
234 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
235 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
236 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
237 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
239 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
242 /* Structure for saving instruction and alignment per-fragment data
243 that will be written to the object file. This structure is
244 equivalent to the actual data that will be written out to the file
245 but is easier to use. We provide a conversion to file flags
246 in frag_flags_to_number. */
248 typedef struct frag_flags_struct frag_flags
;
250 struct frag_flags_struct
252 /* is_literal should only be used after xtensa_move_literals.
253 If you need to check if you are generating a literal fragment,
254 then use the generating_literals global. */
256 unsigned is_literal
: 1;
257 unsigned is_insn
: 1;
258 unsigned is_data
: 1;
259 unsigned is_unreachable
: 1;
263 unsigned is_loop_target
: 1;
264 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
265 unsigned bt_align_priority
: 2;
267 unsigned is_no_density
: 1;
268 /* no_longcalls flag does not need to be placed in the object file. */
269 /* is_specific_opcode implies no_transform. */
270 unsigned is_no_transform
: 1;
272 unsigned is_no_reorder
: 1;
274 /* Uses absolute literal addressing for l32r. */
275 unsigned is_abslit
: 1;
277 unsigned is_align
: 1;
278 unsigned alignment
: 5;
282 /* Structure for saving information about a block of property data
283 for frags that have the same flags. */
284 struct xtensa_block_info_struct
290 struct xtensa_block_info_struct
*next
;
294 /* Structure for saving the current state before emitting literals. */
295 typedef struct emit_state_struct
300 int generating_literals
;
304 /* Opcode placement information */
306 typedef unsigned long long bitfield
;
307 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
308 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
309 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
311 #define MAX_FORMATS 32
313 typedef struct op_placement_info_struct
316 /* A number describing how restrictive the issue is for this
317 opcode. For example, an opcode that fits lots of different
318 formats has a high freedom, as does an opcode that fits
319 only one format but many slots in that format. The most
320 restrictive is the opcode that fits only one slot in one
323 xtensa_format narrowest
;
327 /* formats is a bitfield with the Nth bit set
328 if the opcode fits in the Nth xtensa_format. */
331 /* slots[N]'s Mth bit is set if the op fits in the
332 Mth slot of the Nth xtensa_format. */
333 bitfield slots
[MAX_FORMATS
];
335 /* A count of the number of slots in a given format
336 an op can fit (i.e., the bitcount of the slot field above). */
337 char slots_in_format
[MAX_FORMATS
];
339 } op_placement_info
, *op_placement_info_table
;
341 op_placement_info_table op_placement_table
;
344 /* Extra expression types. */
346 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
347 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
348 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
361 directive_literal_prefix
,
363 directive_absolute_literals
,
364 directive_last_directive
370 bfd_boolean can_be_negated
;
373 const directive_infoS directive_info
[] =
376 { "literal", FALSE
},
378 { "transform", TRUE
},
379 { "freeregs", FALSE
},
380 { "longcalls", TRUE
},
381 { "literal_prefix", FALSE
},
382 { "schedule", TRUE
},
383 { "absolute-literals", TRUE
}
386 bfd_boolean directive_state
[] =
390 #if !XCHAL_HAVE_DENSITY
395 TRUE
, /* transform */
396 FALSE
, /* freeregs */
397 FALSE
, /* longcalls */
398 FALSE
, /* literal_prefix */
400 #if XSHAL_USE_ABSOLUTE_LITERALS
401 TRUE
/* absolute_literals */
403 FALSE
/* absolute_literals */
408 /* Directive functions. */
410 static void xtensa_begin_directive (int);
411 static void xtensa_end_directive (int);
412 static void xtensa_literal_prefix (void);
413 static void xtensa_literal_position (int);
414 static void xtensa_literal_pseudo (int);
415 static void xtensa_frequency_pseudo (int);
416 static void xtensa_elf_cons (int);
418 /* Parsing and Idiom Translation. */
420 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
422 /* Various Other Internal Functions. */
424 extern bfd_boolean
xg_is_single_relaxable_insn (TInsn
*, TInsn
*, bfd_boolean
);
425 static bfd_boolean
xg_build_to_insn (TInsn
*, TInsn
*, BuildInstr
*);
426 static void xtensa_mark_literal_pool_location (void);
427 static addressT
get_expanded_loop_offset (xtensa_opcode
);
428 static fragS
*get_literal_pool_location (segT
);
429 static void set_literal_pool_location (segT
, fragS
*);
430 static void xtensa_set_frag_assembly_state (fragS
*);
431 static void finish_vinsn (vliw_insn
*);
432 static bfd_boolean
emit_single_op (TInsn
*);
433 static int total_frag_text_expansion (fragS
*);
435 /* Alignment Functions. */
437 static int get_text_align_power (unsigned);
438 static int get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
439 static int branch_align_power (segT
);
441 /* Helpers for xtensa_relax_frag(). */
443 static long relax_frag_add_nop (fragS
*);
445 /* Accessors for additional per-subsegment information. */
447 static unsigned get_last_insn_flags (segT
, subsegT
);
448 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
449 static float get_subseg_total_freq (segT
, subsegT
);
450 static float get_subseg_target_freq (segT
, subsegT
);
451 static void set_subseg_freq (segT
, subsegT
, float, float);
453 /* Segment list functions. */
455 static void xtensa_move_literals (void);
456 static void xtensa_reorder_segments (void);
457 static void xtensa_switch_to_literal_fragment (emit_state
*);
458 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
459 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
460 static void xtensa_restore_emit_state (emit_state
*);
461 static segT
cache_literal_section (bfd_boolean
);
463 /* Import from elf32-xtensa.c in BFD library. */
465 extern asection
*xtensa_get_property_section (asection
*, const char *);
467 /* op_placement_info functions. */
469 static void init_op_placement_info_table (void);
470 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
471 static int xg_get_single_size (xtensa_opcode
);
472 static xtensa_format
xg_get_single_format (xtensa_opcode
);
473 static int xg_get_single_slot (xtensa_opcode
);
475 /* TInsn and IStack functions. */
477 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
478 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
479 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
480 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
481 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
482 static void tinsn_from_chars (TInsn
*, char *, int);
483 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
484 static int get_num_stack_text_bytes (IStack
*);
485 static int get_num_stack_literal_bytes (IStack
*);
487 /* vliw_insn functions. */
489 static void xg_init_vinsn (vliw_insn
*);
490 static void xg_clear_vinsn (vliw_insn
*);
491 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
492 static void xg_free_vinsn (vliw_insn
*);
493 static bfd_boolean vinsn_to_insnbuf
494 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
495 static void vinsn_from_chars (vliw_insn
*, char *);
497 /* Expression Utilities. */
499 bfd_boolean
expr_is_const (const expressionS
*);
500 offsetT
get_expr_const (const expressionS
*);
501 void set_expr_const (expressionS
*, offsetT
);
502 bfd_boolean
expr_is_register (const expressionS
*);
503 offsetT
get_expr_register (const expressionS
*);
504 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
505 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
506 static void copy_expr (expressionS
*, const expressionS
*);
508 /* Section renaming. */
510 static void build_section_rename (const char *);
513 /* ISA imported from bfd. */
514 extern xtensa_isa xtensa_default_isa
;
516 extern int target_big_endian
;
518 static xtensa_opcode xtensa_addi_opcode
;
519 static xtensa_opcode xtensa_addmi_opcode
;
520 static xtensa_opcode xtensa_call0_opcode
;
521 static xtensa_opcode xtensa_call4_opcode
;
522 static xtensa_opcode xtensa_call8_opcode
;
523 static xtensa_opcode xtensa_call12_opcode
;
524 static xtensa_opcode xtensa_callx0_opcode
;
525 static xtensa_opcode xtensa_callx4_opcode
;
526 static xtensa_opcode xtensa_callx8_opcode
;
527 static xtensa_opcode xtensa_callx12_opcode
;
528 static xtensa_opcode xtensa_const16_opcode
;
529 static xtensa_opcode xtensa_entry_opcode
;
530 static xtensa_opcode xtensa_movi_opcode
;
531 static xtensa_opcode xtensa_movi_n_opcode
;
532 static xtensa_opcode xtensa_isync_opcode
;
533 static xtensa_opcode xtensa_jx_opcode
;
534 static xtensa_opcode xtensa_l32r_opcode
;
535 static xtensa_opcode xtensa_loop_opcode
;
536 static xtensa_opcode xtensa_loopnez_opcode
;
537 static xtensa_opcode xtensa_loopgtz_opcode
;
538 static xtensa_opcode xtensa_nop_opcode
;
539 static xtensa_opcode xtensa_nop_n_opcode
;
540 static xtensa_opcode xtensa_or_opcode
;
541 static xtensa_opcode xtensa_ret_opcode
;
542 static xtensa_opcode xtensa_ret_n_opcode
;
543 static xtensa_opcode xtensa_retw_opcode
;
544 static xtensa_opcode xtensa_retw_n_opcode
;
545 static xtensa_opcode xtensa_rsr_lcount_opcode
;
546 static xtensa_opcode xtensa_waiti_opcode
;
549 /* Command-line Options. */
551 bfd_boolean use_literal_section
= TRUE
;
552 static bfd_boolean align_targets
= TRUE
;
553 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
554 static bfd_boolean has_a0_b_retw
= FALSE
;
555 static bfd_boolean workaround_a0_b_retw
= FALSE
;
556 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
557 static bfd_boolean workaround_short_loop
= FALSE
;
558 static bfd_boolean maybe_has_short_loop
= FALSE
;
559 static bfd_boolean workaround_close_loop_end
= FALSE
;
560 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
561 static bfd_boolean enforce_three_byte_loop_align
= FALSE
;
563 /* When workaround_short_loops is TRUE, all loops with early exits must
564 have at least 3 instructions. workaround_all_short_loops is a modifier
565 to the workaround_short_loop flag. In addition to the
566 workaround_short_loop actions, all straightline loopgtz and loopnez
567 must have at least 3 instructions. */
569 static bfd_boolean workaround_all_short_loops
= FALSE
;
573 xtensa_setup_hw_workarounds (int earliest
, int latest
)
575 if (earliest
> latest
)
576 as_fatal (_("illegal range of target hardware versions"));
578 /* Enable all workarounds for pre-T1050.0 hardware. */
579 if (earliest
< 105000 || latest
< 105000)
581 workaround_a0_b_retw
|= TRUE
;
582 workaround_b_j_loop_end
|= TRUE
;
583 workaround_short_loop
|= TRUE
;
584 workaround_close_loop_end
|= TRUE
;
585 workaround_all_short_loops
|= TRUE
;
586 enforce_three_byte_loop_align
= TRUE
;
593 option_density
= OPTION_MD_BASE
,
600 option_no_link_relax
,
608 option_text_section_literals
,
609 option_no_text_section_literals
,
611 option_absolute_literals
,
612 option_no_absolute_literals
,
614 option_align_targets
,
615 option_no_align_targets
,
617 option_warn_unaligned_targets
,
622 option_workaround_a0_b_retw
,
623 option_no_workaround_a0_b_retw
,
625 option_workaround_b_j_loop_end
,
626 option_no_workaround_b_j_loop_end
,
628 option_workaround_short_loop
,
629 option_no_workaround_short_loop
,
631 option_workaround_all_short_loops
,
632 option_no_workaround_all_short_loops
,
634 option_workaround_close_loop_end
,
635 option_no_workaround_close_loop_end
,
637 option_no_workarounds
,
639 option_rename_section_name
,
642 option_prefer_const16
,
644 option_target_hardware
647 const char *md_shortopts
= "";
649 struct option md_longopts
[] =
651 { "density", no_argument
, NULL
, option_density
},
652 { "no-density", no_argument
, NULL
, option_no_density
},
654 /* Both "relax" and "generics" are deprecated and treated as equivalent
655 to the "transform" option. */
656 { "relax", no_argument
, NULL
, option_relax
},
657 { "no-relax", no_argument
, NULL
, option_no_relax
},
658 { "generics", no_argument
, NULL
, option_generics
},
659 { "no-generics", no_argument
, NULL
, option_no_generics
},
661 { "transform", no_argument
, NULL
, option_transform
},
662 { "no-transform", no_argument
, NULL
, option_no_transform
},
663 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
664 { "no-text-section-literals", no_argument
, NULL
,
665 option_no_text_section_literals
},
666 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
667 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
668 /* This option was changed from -align-target to -target-align
669 because it conflicted with the "-al" option. */
670 { "target-align", no_argument
, NULL
, option_align_targets
},
671 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
672 { "warn-unaligned-targets", no_argument
, NULL
,
673 option_warn_unaligned_targets
},
674 { "longcalls", no_argument
, NULL
, option_longcalls
},
675 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
677 { "no-workaround-a0-b-retw", no_argument
, NULL
,
678 option_no_workaround_a0_b_retw
},
679 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
681 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
682 option_no_workaround_b_j_loop_end
},
683 { "workaround-b-j-loop-end", no_argument
, NULL
,
684 option_workaround_b_j_loop_end
},
686 { "no-workaround-short-loops", no_argument
, NULL
,
687 option_no_workaround_short_loop
},
688 { "workaround-short-loops", no_argument
, NULL
,
689 option_workaround_short_loop
},
691 { "no-workaround-all-short-loops", no_argument
, NULL
,
692 option_no_workaround_all_short_loops
},
693 { "workaround-all-short-loop", no_argument
, NULL
,
694 option_workaround_all_short_loops
},
696 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
697 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
699 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
701 { "no-workaround-close-loop-end", no_argument
, NULL
,
702 option_no_workaround_close_loop_end
},
703 { "workaround-close-loop-end", no_argument
, NULL
,
704 option_workaround_close_loop_end
},
706 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
708 { "link-relax", no_argument
, NULL
, option_link_relax
},
709 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
711 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
713 { NULL
, no_argument
, NULL
, 0 }
716 size_t md_longopts_size
= sizeof md_longopts
;
720 md_parse_option (int c
, char *arg
)
725 as_warn (_("--density option is ignored"));
727 case option_no_density
:
728 as_warn (_("--no-density option is ignored"));
730 case option_link_relax
:
733 case option_no_link_relax
:
736 case option_generics
:
737 as_warn (_("--generics is deprecated; use --transform instead"));
738 return md_parse_option (option_transform
, arg
);
739 case option_no_generics
:
740 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
741 return md_parse_option (option_no_transform
, arg
);
743 as_warn (_("--relax is deprecated; use --transform instead"));
744 return md_parse_option (option_transform
, arg
);
745 case option_no_relax
:
746 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
747 return md_parse_option (option_no_transform
, arg
);
748 case option_longcalls
:
749 directive_state
[directive_longcalls
] = TRUE
;
751 case option_no_longcalls
:
752 directive_state
[directive_longcalls
] = FALSE
;
754 case option_text_section_literals
:
755 use_literal_section
= FALSE
;
757 case option_no_text_section_literals
:
758 use_literal_section
= TRUE
;
760 case option_absolute_literals
:
761 if (!absolute_literals_supported
)
763 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
766 directive_state
[directive_absolute_literals
] = TRUE
;
768 case option_no_absolute_literals
:
769 directive_state
[directive_absolute_literals
] = FALSE
;
772 case option_workaround_a0_b_retw
:
773 workaround_a0_b_retw
= TRUE
;
775 case option_no_workaround_a0_b_retw
:
776 workaround_a0_b_retw
= FALSE
;
778 case option_workaround_b_j_loop_end
:
779 workaround_b_j_loop_end
= TRUE
;
781 case option_no_workaround_b_j_loop_end
:
782 workaround_b_j_loop_end
= FALSE
;
785 case option_workaround_short_loop
:
786 workaround_short_loop
= TRUE
;
788 case option_no_workaround_short_loop
:
789 workaround_short_loop
= FALSE
;
792 case option_workaround_all_short_loops
:
793 workaround_all_short_loops
= TRUE
;
795 case option_no_workaround_all_short_loops
:
796 workaround_all_short_loops
= FALSE
;
799 case option_workaround_close_loop_end
:
800 workaround_close_loop_end
= TRUE
;
802 case option_no_workaround_close_loop_end
:
803 workaround_close_loop_end
= FALSE
;
806 case option_no_workarounds
:
807 workaround_a0_b_retw
= FALSE
;
808 workaround_b_j_loop_end
= FALSE
;
809 workaround_short_loop
= FALSE
;
810 workaround_all_short_loops
= FALSE
;
811 workaround_close_loop_end
= FALSE
;
814 case option_align_targets
:
815 align_targets
= TRUE
;
817 case option_no_align_targets
:
818 align_targets
= FALSE
;
821 case option_warn_unaligned_targets
:
822 warn_unaligned_branch_targets
= TRUE
;
825 case option_rename_section_name
:
826 build_section_rename (arg
);
830 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
831 should be emitted or not. FIXME: Not implemented. */
834 case option_prefer_l32r
:
836 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
840 case option_prefer_const16
:
842 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
846 case option_target_hardware
:
848 int earliest
, latest
= 0;
849 if (*arg
== 0 || *arg
== '-')
850 as_fatal (_("invalid target hardware version"));
852 earliest
= strtol (arg
, &arg
, 0);
856 else if (*arg
== '-')
859 as_fatal (_("invalid target hardware version"));
860 latest
= strtol (arg
, &arg
, 0);
863 as_fatal (_("invalid target hardware version"));
865 xtensa_setup_hw_workarounds (earliest
, latest
);
869 case option_transform
:
870 /* This option has no affect other than to use the defaults,
871 which are already set. */
874 case option_no_transform
:
875 /* This option turns off all transformations of any kind.
876 However, because we want to preserve the state of other
877 directives, we only change its own field. Thus, before
878 you perform any transformation, always check if transform
879 is available. If you use the functions we provide for this
880 purpose, you will be ok. */
881 directive_state
[directive_transform
] = FALSE
;
891 md_show_usage (FILE *stream
)
895 --[no-]text-section-literals\n\
896 [Do not] put literals in the text section\n\
897 --[no-]absolute-literals\n\
898 [Do not] default to use non-PC-relative literals\n\
899 --[no-]target-align [Do not] try to align branch targets\n\
900 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
901 --[no-]transform [Do not] transform instructions\n\
902 --rename-section old=new Rename section 'old' to 'new'\n", stream
);
906 /* Functions related to the list of current label symbols. */
909 xtensa_add_insn_label (symbolS
*sym
)
913 if (!free_insn_labels
)
914 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
917 l
= free_insn_labels
;
918 free_insn_labels
= l
->next
;
922 l
->next
= insn_labels
;
928 xtensa_clear_insn_labels (void)
932 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
939 /* The "loops_ok" argument is provided to allow ignoring labels that
940 define loop ends. This fixes a bug where the NOPs to align a
941 loop opcode were included in a previous zero-cost loop:
960 This argument is used to prevent moving the NOP to before the
961 loop-end label, which is what you want in this special case. */
964 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
, bfd_boolean loops_ok
)
968 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
970 symbolS
*lit_sym
= lit
->sym
;
971 if (loops_ok
|| ! symbol_get_tc (lit_sym
)->is_loop_target
)
973 S_SET_VALUE (lit_sym
, new_offset
);
974 symbol_set_frag (lit_sym
, new_frag
);
980 /* Directive data and functions. */
982 typedef struct state_stackS_struct
984 directiveE directive
;
986 bfd_boolean old_state
;
990 struct state_stackS_struct
*prev
;
993 state_stackS
*directive_state_stack
;
995 const pseudo_typeS md_pseudo_table
[] =
997 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
998 { "literal_position", xtensa_literal_position
, 0 },
999 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
1000 { "long", xtensa_elf_cons
, 4 },
1001 { "word", xtensa_elf_cons
, 4 },
1002 { "short", xtensa_elf_cons
, 2 },
1003 { "begin", xtensa_begin_directive
, 0 },
1004 { "end", xtensa_end_directive
, 0 },
1005 { "literal", xtensa_literal_pseudo
, 0 },
1006 { "frequency", xtensa_frequency_pseudo
, 0 },
1012 use_transform (void)
1014 /* After md_end, you should be checking frag by frag, rather
1015 than state directives. */
1016 assert (!past_xtensa_end
);
1017 return directive_state
[directive_transform
];
1022 do_align_targets (void)
1024 /* Do not use this function after md_end; just look at align_targets
1025 instead. There is no target-align directive, so alignment is either
1026 enabled for all frags or not done at all. */
1027 assert (!past_xtensa_end
);
1028 return align_targets
&& use_transform ();
1033 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1037 state_stackS
*stack
= (state_stackS
*) xmalloc (sizeof (state_stackS
));
1039 as_where (&file
, &line
);
1041 stack
->directive
= directive
;
1042 stack
->negated
= negated
;
1043 stack
->old_state
= directive_state
[directive
];
1046 stack
->datum
= datum
;
1047 stack
->prev
= directive_state_stack
;
1048 directive_state_stack
= stack
;
1050 directive_state
[directive
] = !negated
;
1055 directive_pop (directiveE
*directive
,
1056 bfd_boolean
*negated
,
1061 state_stackS
*top
= directive_state_stack
;
1063 if (!directive_state_stack
)
1065 as_bad (_("unmatched end directive"));
1066 *directive
= directive_none
;
1070 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1071 *directive
= top
->directive
;
1072 *negated
= top
->negated
;
1075 *datum
= top
->datum
;
1076 directive_state_stack
= top
->prev
;
1082 directive_balance (void)
1084 while (directive_state_stack
)
1086 directiveE directive
;
1087 bfd_boolean negated
;
1092 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1093 as_warn_where ((char *) file
, line
,
1094 _(".begin directive with no matching .end directive"));
1100 inside_directive (directiveE dir
)
1102 state_stackS
*top
= directive_state_stack
;
1104 while (top
&& top
->directive
!= dir
)
1107 return (top
!= NULL
);
1112 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1116 char *directive_string
;
1118 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1123 input_line_pointer
+= 3;
1126 len
= strspn (input_line_pointer
,
1127 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1129 /* This code is a hack to make .begin [no-][generics|relax] exactly
1130 equivalent to .begin [no-]transform. We should remove it when
1131 we stop accepting those options. */
1133 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1135 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1136 directive_string
= "transform";
1138 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1140 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1141 directive_string
= "transform";
1144 directive_string
= input_line_pointer
;
1146 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1148 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1150 input_line_pointer
+= len
;
1151 *directive
= (directiveE
) i
;
1152 if (*negated
&& !directive_info
[i
].can_be_negated
)
1153 as_bad (_("directive %s cannot be negated"),
1154 directive_info
[i
].name
);
1159 as_bad (_("unknown directive"));
1160 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1165 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1167 directiveE directive
;
1168 bfd_boolean negated
;
1172 get_directive (&directive
, &negated
);
1173 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1175 discard_rest_of_line ();
1179 if (cur_vinsn
.inside_bundle
)
1180 as_bad (_("directives are not valid inside bundles"));
1184 case directive_literal
:
1185 if (!inside_directive (directive_literal
))
1187 /* Previous labels go with whatever follows this directive, not with
1188 the literal, so save them now. */
1189 saved_insn_labels
= insn_labels
;
1192 as_warn (_(".begin literal is deprecated; use .literal instead"));
1193 state
= (emit_state
*) xmalloc (sizeof (emit_state
));
1194 xtensa_switch_to_literal_fragment (state
);
1195 directive_push (directive_literal
, negated
, state
);
1198 case directive_literal_prefix
:
1199 /* Have to flush pending output because a movi relaxed to an l32r
1200 might produce a literal. */
1201 md_flush_pending_output ();
1202 /* Check to see if the current fragment is a literal
1203 fragment. If it is, then this operation is not allowed. */
1204 if (generating_literals
)
1206 as_bad (_("cannot set literal_prefix inside literal fragment"));
1210 /* Allocate the literal state for this section and push
1211 onto the directive stack. */
1212 ls
= xmalloc (sizeof (lit_state
));
1215 *ls
= default_lit_sections
;
1216 directive_push (directive_literal_prefix
, negated
, ls
);
1218 /* Process the new prefix. */
1219 xtensa_literal_prefix ();
1222 case directive_freeregs
:
1223 /* This information is currently unused, but we'll accept the statement
1224 and just discard the rest of the line. This won't check the syntax,
1225 but it will accept every correct freeregs directive. */
1226 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1227 directive_push (directive_freeregs
, negated
, 0);
1230 case directive_schedule
:
1231 md_flush_pending_output ();
1232 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1233 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1234 directive_push (directive_schedule
, negated
, 0);
1235 xtensa_set_frag_assembly_state (frag_now
);
1238 case directive_density
:
1239 as_warn (_(".begin [no-]density is ignored"));
1242 case directive_absolute_literals
:
1243 md_flush_pending_output ();
1244 if (!absolute_literals_supported
&& !negated
)
1246 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1249 xtensa_set_frag_assembly_state (frag_now
);
1250 directive_push (directive
, negated
, 0);
1254 md_flush_pending_output ();
1255 xtensa_set_frag_assembly_state (frag_now
);
1256 directive_push (directive
, negated
, 0);
1260 demand_empty_rest_of_line ();
1265 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1267 directiveE begin_directive
, end_directive
;
1268 bfd_boolean begin_negated
, end_negated
;
1272 emit_state
**state_ptr
;
1275 if (cur_vinsn
.inside_bundle
)
1276 as_bad (_("directives are not valid inside bundles"));
1278 get_directive (&end_directive
, &end_negated
);
1280 md_flush_pending_output ();
1282 switch (end_directive
)
1284 case (directiveE
) XTENSA_UNDEFINED
:
1285 discard_rest_of_line ();
1288 case directive_density
:
1289 as_warn (_(".end [no-]density is ignored"));
1290 demand_empty_rest_of_line ();
1293 case directive_absolute_literals
:
1294 if (!absolute_literals_supported
&& !end_negated
)
1296 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1297 demand_empty_rest_of_line ();
1306 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1307 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1308 (const void **) state_ptr
);
1310 if (begin_directive
!= directive_none
)
1312 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1314 as_bad (_("does not match begin %s%s at %s:%d"),
1315 begin_negated
? "no-" : "",
1316 directive_info
[begin_directive
].name
, file
, line
);
1320 switch (end_directive
)
1322 case directive_literal
:
1323 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1324 xtensa_restore_emit_state (state
);
1325 xtensa_set_frag_assembly_state (frag_now
);
1327 if (!inside_directive (directive_literal
))
1329 /* Restore the list of current labels. */
1330 xtensa_clear_insn_labels ();
1331 insn_labels
= saved_insn_labels
;
1335 case directive_literal_prefix
:
1336 /* Restore the default collection sections from saved state. */
1337 s
= (lit_state
*) state
;
1339 default_lit_sections
= *s
;
1341 /* Free the state storage. */
1342 free (s
->lit_prefix
);
1346 case directive_schedule
:
1347 case directive_freeregs
:
1351 xtensa_set_frag_assembly_state (frag_now
);
1357 demand_empty_rest_of_line ();
1361 /* Place an aligned literal fragment at the current location. */
1364 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1366 md_flush_pending_output ();
1368 if (inside_directive (directive_literal
))
1369 as_warn (_(".literal_position inside literal directive; ignoring"));
1370 xtensa_mark_literal_pool_location ();
1372 demand_empty_rest_of_line ();
1373 xtensa_clear_insn_labels ();
1377 /* Support .literal label, expr, ... */
1380 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1383 char *p
, *base_name
;
1387 if (inside_directive (directive_literal
))
1389 as_bad (_(".literal not allowed inside .begin literal region"));
1390 ignore_rest_of_line ();
1394 md_flush_pending_output ();
1396 /* Previous labels go with whatever follows this directive, not with
1397 the literal, so save them now. */
1398 saved_insn_labels
= insn_labels
;
1401 /* If we are using text-section literals, then this is the right value... */
1404 base_name
= input_line_pointer
;
1406 xtensa_switch_to_literal_fragment (&state
);
1408 /* ...but if we aren't using text-section-literals, then we
1409 need to put them in the section we just switched to. */
1410 if (use_literal_section
|| directive_state
[directive_absolute_literals
])
1413 /* All literals are aligned to four-byte boundaries. */
1414 frag_align (2, 0, 0);
1415 record_alignment (now_seg
, 2);
1417 c
= get_symbol_end ();
1418 /* Just after name is now '\0'. */
1419 p
= input_line_pointer
;
1423 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1425 as_bad (_("expected comma or colon after symbol name; "
1426 "rest of line ignored"));
1427 ignore_rest_of_line ();
1428 xtensa_restore_emit_state (&state
);
1436 input_line_pointer
++; /* skip ',' or ':' */
1438 xtensa_elf_cons (4);
1440 xtensa_restore_emit_state (&state
);
1442 /* Restore the list of current labels. */
1443 xtensa_clear_insn_labels ();
1444 insn_labels
= saved_insn_labels
;
1449 xtensa_literal_prefix (void)
1454 /* Parse the new prefix from the input_line_pointer. */
1456 len
= strspn (input_line_pointer
,
1457 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1458 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1460 /* Get a null-terminated copy of the name. */
1461 name
= xmalloc (len
+ 1);
1463 strncpy (name
, input_line_pointer
, len
);
1466 /* Skip the name in the input line. */
1467 input_line_pointer
+= len
;
1469 default_lit_sections
.lit_prefix
= name
;
1471 /* Clear cached literal sections, since the prefix has changed. */
1472 default_lit_sections
.lit_seg
= NULL
;
1473 default_lit_sections
.lit4_seg
= NULL
;
1477 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1480 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1482 float fall_through_f
, target_f
;
1484 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1485 if (fall_through_f
< 0)
1487 as_bad (_("fall through frequency must be greater than 0"));
1488 ignore_rest_of_line ();
1492 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1495 as_bad (_("branch target frequency must be greater than 0"));
1496 ignore_rest_of_line ();
1500 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1502 demand_empty_rest_of_line ();
1506 /* Like normal .long/.short/.word, except support @plt, etc.
1507 Clobbers input_line_pointer, checks end-of-line. */
1510 xtensa_elf_cons (int nbytes
)
1513 bfd_reloc_code_real_type reloc
;
1515 md_flush_pending_output ();
1517 if (cur_vinsn
.inside_bundle
)
1518 as_bad (_("directives are not valid inside bundles"));
1520 if (is_it_end_of_statement ())
1522 demand_empty_rest_of_line ();
1529 if (exp
.X_op
== O_symbol
1530 && *input_line_pointer
== '@'
1531 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1534 reloc_howto_type
*reloc_howto
=
1535 bfd_reloc_type_lookup (stdoutput
, reloc
);
1537 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1538 as_bad (_("unsupported relocation"));
1539 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1540 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1541 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1542 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1543 as_bad (_("opcode-specific %s relocation used outside "
1544 "an instruction"), reloc_howto
->name
);
1545 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1546 as_bad (_("%s relocations do not fit in %d bytes"),
1547 reloc_howto
->name
, nbytes
);
1550 char *p
= frag_more ((int) nbytes
);
1551 xtensa_set_frag_assembly_state (frag_now
);
1552 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1553 nbytes
, &exp
, 0, reloc
);
1557 emit_expr (&exp
, (unsigned int) nbytes
);
1559 while (*input_line_pointer
++ == ',');
1561 input_line_pointer
--; /* Put terminator back into stream. */
1562 demand_empty_rest_of_line ();
1566 /* Parsing and Idiom Translation. */
1568 /* Parse @plt, etc. and return the desired relocation. */
1569 static bfd_reloc_code_real_type
1570 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1576 bfd_reloc_code_real_type reloc
;
1584 struct map_bfd
*ptr
;
1586 #define MAP(str,reloc) { str, sizeof (str) - 1, reloc }
1588 static struct map_bfd mapping
[] =
1590 MAP ("l", BFD_RELOC_LO16
),
1591 MAP ("h", BFD_RELOC_HI16
),
1592 MAP ("plt", BFD_RELOC_XTENSA_PLT
),
1593 { (char *) 0, 0, BFD_RELOC_UNUSED
}
1597 return BFD_RELOC_NONE
;
1599 for (ch
= *str
, str2
= ident
;
1600 (str2
< ident
+ sizeof (ident
) - 1
1601 && (ISALNUM (ch
) || ch
== '@'));
1604 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1611 for (ptr
= &mapping
[0]; ptr
->length
> 0; ptr
++)
1612 if (ch
== ptr
->string
[0]
1613 && len
== ptr
->length
1614 && memcmp (ident
, ptr
->string
, ptr
->length
) == 0)
1616 /* Now check for "identifier@suffix+constant". */
1617 if (*str
== '-' || *str
== '+')
1619 char *orig_line
= input_line_pointer
;
1620 expressionS new_exp
;
1622 input_line_pointer
= str
;
1623 expression (&new_exp
);
1624 if (new_exp
.X_op
== O_constant
)
1626 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1627 str
= input_line_pointer
;
1630 if (&input_line_pointer
!= str_p
)
1631 input_line_pointer
= orig_line
;
1638 return BFD_RELOC_UNUSED
;
1643 expression_end (const char *name
)
1666 #define ERROR_REG_NUM ((unsigned) -1)
1669 tc_get_register (const char *prefix
)
1672 const char *next_expr
;
1673 const char *old_line_pointer
;
1676 old_line_pointer
= input_line_pointer
;
1678 if (*input_line_pointer
== '$')
1679 ++input_line_pointer
;
1681 /* Accept "sp" as a synonym for "a1". */
1682 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1683 && expression_end (input_line_pointer
+ 2))
1685 input_line_pointer
+= 2;
1686 return 1; /* AR[1] */
1689 while (*input_line_pointer
++ == *prefix
++)
1691 --input_line_pointer
;
1696 as_bad (_("bad register name: %s"), old_line_pointer
);
1697 return ERROR_REG_NUM
;
1700 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1702 as_bad (_("bad register number: %s"), input_line_pointer
);
1703 return ERROR_REG_NUM
;
1708 while (ISDIGIT ((int) *input_line_pointer
))
1709 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1711 if (!(next_expr
= expression_end (input_line_pointer
)))
1713 as_bad (_("bad register name: %s"), old_line_pointer
);
1714 return ERROR_REG_NUM
;
1717 input_line_pointer
= (char *) next_expr
;
1724 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1726 xtensa_isa isa
= xtensa_default_isa
;
1728 /* Check if this is an immediate operand. */
1729 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1731 bfd_reloc_code_real_type reloc
;
1732 segT t
= expression (tok
);
1733 if (t
== absolute_section
1734 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1736 assert (tok
->X_op
== O_constant
);
1737 tok
->X_op
= O_symbol
;
1738 tok
->X_add_symbol
= &abs_symbol
;
1741 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1742 && (reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1743 && (reloc
!= BFD_RELOC_NONE
))
1748 case BFD_RELOC_UNUSED
:
1749 as_bad (_("unsupported relocation"));
1752 case BFD_RELOC_XTENSA_PLT
:
1753 tok
->X_op
= O_pltrel
;
1756 case BFD_RELOC_LO16
:
1757 if (tok
->X_op
== O_constant
)
1758 tok
->X_add_number
&= 0xffff;
1763 case BFD_RELOC_HI16
:
1764 if (tok
->X_op
== O_constant
)
1765 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1774 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1775 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1777 if (reg
!= ERROR_REG_NUM
) /* Already errored */
1780 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
1781 as_bad (_("register number out of range"));
1784 tok
->X_op
= O_register
;
1785 tok
->X_add_symbol
= 0;
1786 tok
->X_add_number
= reg
;
1791 /* Split up the arguments for an opcode or pseudo-op. */
1794 tokenize_arguments (char **args
, char *str
)
1796 char *old_input_line_pointer
;
1797 bfd_boolean saw_comma
= FALSE
;
1798 bfd_boolean saw_arg
= FALSE
;
1799 bfd_boolean saw_colon
= FALSE
;
1801 char *arg_end
, *arg
;
1804 /* Save and restore input_line_pointer around this function. */
1805 old_input_line_pointer
= input_line_pointer
;
1806 input_line_pointer
= str
;
1808 while (*input_line_pointer
)
1811 switch (*input_line_pointer
)
1818 input_line_pointer
++;
1819 if (saw_comma
|| saw_colon
|| !saw_arg
)
1825 input_line_pointer
++;
1826 if (saw_comma
|| saw_colon
|| !saw_arg
)
1832 if (!saw_comma
&& !saw_colon
&& saw_arg
)
1835 arg_end
= input_line_pointer
+ 1;
1836 while (!expression_end (arg_end
))
1839 arg_len
= arg_end
- input_line_pointer
;
1840 arg
= (char *) xmalloc ((saw_colon
? 1 : 0) + arg_len
+ 1);
1841 args
[num_args
] = arg
;
1845 strncpy (arg
, input_line_pointer
, arg_len
);
1846 arg
[arg_len
] = '\0';
1848 input_line_pointer
= arg_end
;
1858 if (saw_comma
|| saw_colon
)
1860 input_line_pointer
= old_input_line_pointer
;
1865 as_bad (_("extra comma"));
1867 as_bad (_("extra colon"));
1869 as_bad (_("missing argument"));
1871 as_bad (_("missing comma or colon"));
1872 input_line_pointer
= old_input_line_pointer
;
1877 /* Parse the arguments to an opcode. Return TRUE on error. */
1880 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
1882 expressionS
*tok
, *last_tok
;
1883 xtensa_opcode opcode
= insn
->opcode
;
1884 bfd_boolean had_error
= TRUE
;
1885 xtensa_isa isa
= xtensa_default_isa
;
1886 int n
, num_regs
= 0;
1887 int opcode_operand_count
;
1888 int opnd_cnt
, last_opnd_cnt
;
1889 unsigned int next_reg
= 0;
1890 char *old_input_line_pointer
;
1892 if (insn
->insn_type
== ITYPE_LITERAL
)
1893 opcode_operand_count
= 1;
1895 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
1898 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
1900 /* Save and restore input_line_pointer around this function. */
1901 old_input_line_pointer
= input_line_pointer
;
1907 /* Skip invisible operands. */
1908 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
1914 for (n
= 0; n
< num_args
; n
++)
1916 input_line_pointer
= arg_strings
[n
];
1917 if (*input_line_pointer
== ':')
1919 xtensa_regfile opnd_rf
;
1920 input_line_pointer
++;
1923 assert (opnd_cnt
> 0);
1925 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
1927 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
1928 as_warn (_("incorrect register number, ignoring"));
1933 if (opnd_cnt
>= opcode_operand_count
)
1935 as_warn (_("too many arguments"));
1938 assert (opnd_cnt
< MAX_INSN_ARGS
);
1940 expression_maybe_register (opcode
, opnd_cnt
, tok
);
1941 next_reg
= tok
->X_add_number
+ 1;
1943 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
1945 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
1947 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
1948 /* minus 1 because we are seeing one right now */
1954 last_opnd_cnt
= opnd_cnt
;
1961 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
1965 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
1968 insn
->ntok
= tok
- insn
->tok
;
1972 input_line_pointer
= old_input_line_pointer
;
1978 get_invisible_operands (TInsn
*insn
)
1980 xtensa_isa isa
= xtensa_default_isa
;
1981 static xtensa_insnbuf slotbuf
= NULL
;
1983 xtensa_opcode opc
= insn
->opcode
;
1984 int slot
, opnd
, fmt_found
;
1988 slotbuf
= xtensa_insnbuf_alloc (isa
);
1990 /* Find format/slot where this can be encoded. */
1993 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
1995 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
1997 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2003 if (fmt_found
) break;
2008 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2012 /* First encode all the visible operands
2013 (to deal with shared field operands). */
2014 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2016 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2017 && (insn
->tok
[opnd
].X_op
== O_register
2018 || insn
->tok
[opnd
].X_op
== O_constant
))
2020 val
= insn
->tok
[opnd
].X_add_number
;
2021 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2022 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2026 /* Then pull out the values for the invisible ones. */
2027 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2029 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2031 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2032 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2033 insn
->tok
[opnd
].X_add_number
= val
;
2034 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2035 insn
->tok
[opnd
].X_op
= O_register
;
2037 insn
->tok
[opnd
].X_op
= O_constant
;
2046 xg_reverse_shift_count (char **cnt_argp
)
2048 char *cnt_arg
, *new_arg
;
2049 cnt_arg
= *cnt_argp
;
2051 /* replace the argument with "31-(argument)" */
2052 new_arg
= (char *) xmalloc (strlen (cnt_arg
) + 6);
2053 sprintf (new_arg
, "31-(%s)", cnt_arg
);
2056 *cnt_argp
= new_arg
;
2060 /* If "arg" is a constant expression, return non-zero with the value
2064 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2067 char *save_ptr
= input_line_pointer
;
2069 input_line_pointer
= arg
;
2071 input_line_pointer
= save_ptr
;
2073 if (exp
.X_op
== O_constant
)
2075 *valp
= exp
.X_add_number
;
2084 xg_replace_opname (char **popname
, char *newop
)
2087 *popname
= (char *) xmalloc (strlen (newop
) + 1);
2088 strcpy (*popname
, newop
);
2093 xg_check_num_args (int *pnum_args
,
2098 int num_args
= *pnum_args
;
2100 if (num_args
< expected_num
)
2102 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2103 num_args
, opname
, expected_num
);
2107 if (num_args
> expected_num
)
2109 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2110 num_args
, opname
, expected_num
);
2111 while (num_args
-- > expected_num
)
2113 free (arg_strings
[num_args
]);
2114 arg_strings
[num_args
] = 0;
2116 *pnum_args
= expected_num
;
2124 /* If the register is not specified as part of the opcode,
2125 then get it from the operand and move it to the opcode. */
2128 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2130 xtensa_isa isa
= xtensa_default_isa
;
2132 char *opname
, *new_opname
;
2133 const char *sr_name
;
2134 int is_user
, is_write
;
2139 is_user
= (opname
[1] == 'u');
2140 is_write
= (opname
[0] == 'w');
2142 /* Opname == [rw]ur or [rwx]sr... */
2144 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2147 /* Check if the argument is a symbolic register name. */
2148 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2149 /* Handle WSR to "INTSET" as a special case. */
2150 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2151 && !strcasecmp (arg_strings
[1], "intset"))
2152 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2153 if (sr
== XTENSA_UNDEFINED
2154 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2156 /* Maybe it's a register number.... */
2158 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2160 as_bad (_("invalid register '%s' for '%s' instruction"),
2161 arg_strings
[1], opname
);
2164 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2165 if (sr
== XTENSA_UNDEFINED
)
2167 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2168 (long) val
, opname
);
2173 /* Remove the last argument, which is now part of the opcode. */
2174 free (arg_strings
[1]);
2178 /* Translate the opcode. */
2179 sr_name
= xtensa_sysreg_name (isa
, sr
);
2180 /* Another special case for "WSR.INTSET".... */
2181 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2183 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2184 sprintf (new_opname
, "%s.%s", *popname
, sr_name
);
2186 *popname
= new_opname
;
2193 xtensa_translate_old_userreg_ops (char **popname
)
2195 xtensa_isa isa
= xtensa_default_isa
;
2197 char *opname
, *new_opname
;
2198 const char *sr_name
;
2199 bfd_boolean has_underbar
= FALSE
;
2202 if (opname
[0] == '_')
2204 has_underbar
= TRUE
;
2208 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2209 if (sr
!= XTENSA_UNDEFINED
)
2211 /* The new default name ("nnn") is different from the old default
2212 name ("URnnn"). The old default is handled below, and we don't
2213 want to recognize [RW]nnn, so do nothing if the name is the (new)
2215 static char namebuf
[10];
2216 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2217 if (strcmp (namebuf
, opname
+ 1) == 0)
2225 /* Only continue if the reg name is "URnnn". */
2226 if (opname
[1] != 'u' || opname
[2] != 'r')
2228 val
= strtoul (opname
+ 3, &end
, 10);
2232 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2233 if (sr
== XTENSA_UNDEFINED
)
2235 as_bad (_("invalid register number (%ld) for '%s'"),
2236 (long) val
, opname
);
2241 /* Translate the opcode. */
2242 sr_name
= xtensa_sysreg_name (isa
, sr
);
2243 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2244 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2245 opname
[0], sr_name
);
2247 *popname
= new_opname
;
2254 xtensa_translate_zero_immed (char *old_op
,
2264 assert (opname
[0] != '_');
2266 if (strcmp (opname
, old_op
) != 0)
2269 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2271 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2273 xg_replace_opname (popname
, new_op
);
2274 free (arg_strings
[1]);
2275 arg_strings
[1] = arg_strings
[2];
2284 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2285 Returns non-zero if an error was found. */
2288 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2290 char *opname
= *popname
;
2291 bfd_boolean has_underbar
= FALSE
;
2293 if (cur_vinsn
.inside_bundle
)
2298 has_underbar
= TRUE
;
2302 if (strcmp (opname
, "mov") == 0)
2304 if (use_transform () && !has_underbar
&& density_supported
)
2305 xg_replace_opname (popname
, "mov.n");
2308 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2310 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2311 arg_strings
[2] = (char *) xmalloc (strlen (arg_strings
[1]) + 1);
2312 strcpy (arg_strings
[2], arg_strings
[1]);
2318 if (strcmp (opname
, "bbsi.l") == 0)
2320 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2322 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2323 if (target_big_endian
)
2324 xg_reverse_shift_count (&arg_strings
[1]);
2328 if (strcmp (opname
, "bbci.l") == 0)
2330 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2332 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2333 if (target_big_endian
)
2334 xg_reverse_shift_count (&arg_strings
[1]);
2338 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
2339 && strcmp (opname
, "nop") == 0)
2341 if (use_transform () && !has_underbar
&& density_supported
)
2342 xg_replace_opname (popname
, "nop.n");
2345 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2347 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2348 arg_strings
[0] = (char *) xmalloc (3);
2349 arg_strings
[1] = (char *) xmalloc (3);
2350 arg_strings
[2] = (char *) xmalloc (3);
2351 strcpy (arg_strings
[0], "a1");
2352 strcpy (arg_strings
[1], "a1");
2353 strcpy (arg_strings
[2], "a1");
2359 /* Recognize [RW]UR and [RWX]SR. */
2360 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2361 && (opname
[1] == 'u' || opname
[1] == 's'))
2362 || (opname
[0] == 'x' && opname
[1] == 's'))
2364 && opname
[3] == '\0')
2365 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2367 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2368 [RW]<name> if <name> is the non-default name of a user register. */
2369 if ((opname
[0] == 'r' || opname
[0] == 'w')
2370 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2371 return xtensa_translate_old_userreg_ops (popname
);
2373 /* Relax branches that don't allow comparisons against an immediate value
2374 of zero to the corresponding branches with implicit zero immediates. */
2375 if (!has_underbar
&& use_transform ())
2377 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2378 pnum_args
, arg_strings
))
2381 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2382 pnum_args
, arg_strings
))
2385 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2386 pnum_args
, arg_strings
))
2389 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2390 pnum_args
, arg_strings
))
2398 /* Functions for dealing with the Xtensa ISA. */
2400 /* Currently the assembler only allows us to use a single target per
2401 fragment. Because of this, only one operand for a given
2402 instruction may be symbolic. If there is a PC-relative operand,
2403 the last one is chosen. Otherwise, the result is the number of the
2404 last immediate operand, and if there are none of those, we fail and
2408 get_relaxable_immed (xtensa_opcode opcode
)
2410 int last_immed
= -1;
2413 if (opcode
== XTENSA_UNDEFINED
)
2416 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2417 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2419 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2421 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2423 if (last_immed
== -1
2424 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2431 static xtensa_opcode
2432 get_opcode_from_buf (const char *buf
, int slot
)
2434 static xtensa_insnbuf insnbuf
= NULL
;
2435 static xtensa_insnbuf slotbuf
= NULL
;
2436 xtensa_isa isa
= xtensa_default_isa
;
2441 insnbuf
= xtensa_insnbuf_alloc (isa
);
2442 slotbuf
= xtensa_insnbuf_alloc (isa
);
2445 xtensa_insnbuf_from_chars (isa
, insnbuf
, (const unsigned char *) buf
, 0);
2446 fmt
= xtensa_format_decode (isa
, insnbuf
);
2447 if (fmt
== XTENSA_UNDEFINED
)
2448 return XTENSA_UNDEFINED
;
2450 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2451 return XTENSA_UNDEFINED
;
2453 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2454 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2458 #ifdef TENSILICA_DEBUG
2460 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2463 xtensa_print_insn_table (void)
2465 int num_opcodes
, num_operands
;
2466 xtensa_opcode opcode
;
2467 xtensa_isa isa
= xtensa_default_isa
;
2469 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2470 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2473 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2474 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2475 for (opn
= 0; opn
< num_operands
; opn
++)
2477 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2479 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2481 xtensa_regfile opnd_rf
=
2482 xtensa_operand_regfile (isa
, opcode
, opn
);
2483 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2485 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2486 fputs ("[lLr] ", stderr
);
2488 fputs ("i ", stderr
);
2490 fprintf (stderr
, "\n");
2496 print_vliw_insn (xtensa_insnbuf vbuf
)
2498 xtensa_isa isa
= xtensa_default_isa
;
2499 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2500 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2503 fprintf (stderr
, "format = %d\n", f
);
2505 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2507 xtensa_opcode opcode
;
2511 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2512 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2513 opname
= xtensa_opcode_name (isa
, opcode
);
2515 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2516 fprintf (stderr
, " operands = ");
2518 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2522 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2524 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2525 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2526 fprintf (stderr
, "%d ", val
);
2528 fprintf (stderr
, "\n");
2530 xtensa_insnbuf_free (isa
, sbuf
);
2533 #endif /* TENSILICA_DEBUG */
2537 is_direct_call_opcode (xtensa_opcode opcode
)
2539 xtensa_isa isa
= xtensa_default_isa
;
2540 int n
, num_operands
;
2542 if (xtensa_opcode_is_call (isa
, opcode
) != 1)
2545 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2546 for (n
= 0; n
< num_operands
; n
++)
2548 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2549 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2556 /* Convert from BFD relocation type code to slot and operand number.
2557 Returns non-zero on failure. */
2560 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2562 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2563 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2565 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2568 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2569 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2571 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2581 /* Convert from slot number to BFD relocation type code for the
2582 standard PC-relative relocations. Return BFD_RELOC_NONE on
2585 static bfd_reloc_code_real_type
2586 encode_reloc (int slot
)
2588 if (slot
< 0 || slot
> 14)
2589 return BFD_RELOC_NONE
;
2591 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2595 /* Convert from slot numbers to BFD relocation type code for the
2596 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2598 static bfd_reloc_code_real_type
2599 encode_alt_reloc (int slot
)
2601 if (slot
< 0 || slot
> 14)
2602 return BFD_RELOC_NONE
;
2604 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2609 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2612 xtensa_opcode opcode
,
2618 uint32 valbuf
= value
;
2620 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2622 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2624 as_bad_where ((char *) file
, line
,
2625 _("operand %d of '%s' has out of range value '%u'"),
2627 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2630 as_bad_where ((char *) file
, line
,
2631 _("operand %d of '%s' has invalid value '%u'"),
2633 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2638 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2644 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2647 xtensa_opcode opcode
,
2651 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2652 fmt
, slot
, slotbuf
, &val
);
2653 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2658 /* Checks for rules from xtensa-relax tables. */
2660 /* The routine xg_instruction_matches_option_term must return TRUE
2661 when a given option term is true. The meaning of all of the option
2662 terms is given interpretation by this function. This is needed when
2663 an option depends on the state of a directive, but there are no such
2664 options in use right now. */
2667 xg_instruction_matches_option_term (TInsn
*insn ATTRIBUTE_UNUSED
,
2668 const ReqOrOption
*option
)
2670 if (strcmp (option
->option_name
, "realnop") == 0
2671 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2673 /* These conditions were evaluated statically when building the
2674 relaxation table. There's no need to reevaluate them now. */
2679 as_fatal (_("internal error: unknown option name '%s'"),
2680 option
->option_name
);
2686 xg_instruction_matches_or_options (TInsn
*insn
,
2687 const ReqOrOptionList
*or_option
)
2689 const ReqOrOption
*option
;
2690 /* Must match each of the AND terms. */
2691 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2693 if (xg_instruction_matches_option_term (insn
, option
))
2701 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2703 const ReqOption
*req_options
;
2704 /* Must match each of the AND terms. */
2705 for (req_options
= options
;
2706 req_options
!= NULL
;
2707 req_options
= req_options
->next
)
2709 /* Must match one of the OR clauses. */
2710 if (!xg_instruction_matches_or_options (insn
,
2711 req_options
->or_option_terms
))
2718 /* Return the transition rule that matches or NULL if none matches. */
2721 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2723 PreconditionList
*condition_l
;
2725 if (rule
->opcode
!= insn
->opcode
)
2728 for (condition_l
= rule
->conditions
;
2729 condition_l
!= NULL
;
2730 condition_l
= condition_l
->next
)
2734 Precondition
*cond
= condition_l
->precond
;
2739 /* The expression must be the constant. */
2740 assert (cond
->op_num
< insn
->ntok
);
2741 exp1
= &insn
->tok
[cond
->op_num
];
2742 if (expr_is_const (exp1
))
2747 if (get_expr_const (exp1
) != cond
->op_data
)
2751 if (get_expr_const (exp1
) == cond
->op_data
)
2758 else if (expr_is_register (exp1
))
2763 if (get_expr_register (exp1
) != cond
->op_data
)
2767 if (get_expr_register (exp1
) == cond
->op_data
)
2779 assert (cond
->op_num
< insn
->ntok
);
2780 assert (cond
->op_data
< insn
->ntok
);
2781 exp1
= &insn
->tok
[cond
->op_num
];
2782 exp2
= &insn
->tok
[cond
->op_data
];
2787 if (!expr_is_equal (exp1
, exp2
))
2791 if (expr_is_equal (exp1
, exp2
))
2803 if (!xg_instruction_matches_options (insn
, rule
->options
))
2811 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
2813 bfd_boolean a_greater
= FALSE
;
2814 bfd_boolean b_greater
= FALSE
;
2816 ReqOptionList
*l_a
= a
->options
;
2817 ReqOptionList
*l_b
= b
->options
;
2819 /* We only care if they both are the same except for
2820 a const16 vs. an l32r. */
2822 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2824 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
2825 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
2826 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2828 if (l_or_a
->is_true
!= l_or_b
->is_true
)
2830 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
2832 /* This is the case we care about. */
2833 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
2834 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
2841 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
2842 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
2852 l_or_a
= l_or_a
->next
;
2853 l_or_b
= l_or_b
->next
;
2855 if (l_or_a
|| l_or_b
)
2864 /* Incomparable if the substitution was used differently in two cases. */
2865 if (a_greater
&& b_greater
)
2877 static TransitionRule
*
2878 xg_instruction_match (TInsn
*insn
)
2880 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
2882 assert (insn
->opcode
< table
->num_opcodes
);
2884 /* Walk through all of the possible transitions. */
2885 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2887 TransitionRule
*rule
= l
->rule
;
2888 if (xg_instruction_matches_rule (insn
, rule
))
2895 /* Various Other Internal Functions. */
2898 is_unique_insn_expansion (TransitionRule
*r
)
2900 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
2902 if (r
->to_instr
->typ
!= INSTR_INSTR
)
2908 /* Check if there is exactly one relaxation for INSN that converts it to
2909 another instruction of equal or larger size. If so, and if TARG is
2910 non-null, go ahead and generate the relaxed instruction into TARG. If
2911 NARROW_ONLY is true, then only consider relaxations that widen a narrow
2912 instruction, i.e., ignore relaxations that convert to an instruction of
2913 equal size. In some contexts where this function is used, only
2914 a single widening is allowed and the NARROW_ONLY argument is used to
2915 exclude cases like ADDI being "widened" to an ADDMI, which may
2916 later be relaxed to an ADDMI/ADDI pair. */
2919 xg_is_single_relaxable_insn (TInsn
*insn
, TInsn
*targ
, bfd_boolean narrow_only
)
2921 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
2923 TransitionRule
*match
= 0;
2925 assert (insn
->insn_type
== ITYPE_INSN
);
2926 assert (insn
->opcode
< table
->num_opcodes
);
2928 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2930 TransitionRule
*rule
= l
->rule
;
2932 if (xg_instruction_matches_rule (insn
, rule
)
2933 && is_unique_insn_expansion (rule
)
2934 && (xg_get_single_size (insn
->opcode
) + (narrow_only
? 1 : 0)
2935 <= xg_get_single_size (rule
->to_instr
->opcode
)))
2946 xg_build_to_insn (targ
, insn
, match
->to_instr
);
2951 /* Return the maximum number of bytes this opcode can expand to. */
2954 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
2956 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
2958 int max_size
= xg_get_single_size (opcode
);
2960 assert (opcode
< table
->num_opcodes
);
2962 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
2964 TransitionRule
*rule
= l
->rule
;
2965 BuildInstr
*build_list
;
2970 build_list
= rule
->to_instr
;
2971 if (is_unique_insn_expansion (rule
))
2973 assert (build_list
->typ
== INSTR_INSTR
);
2974 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
2977 for (; build_list
!= NULL
; build_list
= build_list
->next
)
2979 switch (build_list
->typ
)
2982 this_size
+= xg_get_single_size (build_list
->opcode
);
2984 case INSTR_LITERAL_DEF
:
2985 case INSTR_LABEL_DEF
:
2990 if (this_size
> max_size
)
2991 max_size
= this_size
;
2997 /* Return the maximum number of literal bytes this opcode can generate. */
3000 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3002 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3006 assert (opcode
< table
->num_opcodes
);
3008 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3010 TransitionRule
*rule
= l
->rule
;
3011 BuildInstr
*build_list
;
3016 build_list
= rule
->to_instr
;
3017 if (is_unique_insn_expansion (rule
))
3019 assert (build_list
->typ
== INSTR_INSTR
);
3020 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3023 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3025 switch (build_list
->typ
)
3027 case INSTR_LITERAL_DEF
:
3028 /* Hard-coded 4-byte literal. */
3032 case INSTR_LABEL_DEF
:
3037 if (this_size
> max_size
)
3038 max_size
= this_size
;
3045 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3047 int steps_taken
= 0;
3048 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3051 assert (insn
->insn_type
== ITYPE_INSN
);
3052 assert (insn
->opcode
< table
->num_opcodes
);
3054 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3056 TransitionRule
*rule
= l
->rule
;
3058 if (xg_instruction_matches_rule (insn
, rule
))
3060 if (steps_taken
== lateral_steps
)
3070 get_special_literal_symbol (void)
3072 static symbolS
*sym
= NULL
;
3075 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3081 get_special_label_symbol (void)
3083 static symbolS
*sym
= NULL
;
3086 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3092 xg_valid_literal_expression (const expressionS
*exp
)
3109 /* This will check to see if the value can be converted into the
3110 operand type. It will return TRUE if it does not fit. */
3113 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3115 uint32 valbuf
= value
;
3116 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3122 /* Assumes: All immeds are constants. Check that all constants fit
3123 into their immeds; return FALSE if not. */
3126 xg_immeds_fit (const TInsn
*insn
)
3128 xtensa_isa isa
= xtensa_default_isa
;
3132 assert (insn
->insn_type
== ITYPE_INSN
);
3133 for (i
= 0; i
< n
; ++i
)
3135 const expressionS
*expr
= &insn
->tok
[i
];
3136 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3143 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3148 /* The symbol should have a fixup associated with it. */
3157 /* This should only be called after we have an initial
3158 estimate of the addresses. */
3161 xg_symbolic_immeds_fit (const TInsn
*insn
,
3167 xtensa_isa isa
= xtensa_default_isa
;
3175 assert (insn
->insn_type
== ITYPE_INSN
);
3177 for (i
= 0; i
< n
; ++i
)
3179 const expressionS
*expr
= &insn
->tok
[i
];
3180 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3187 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3193 /* Check for the worst case. */
3194 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3199 /* We only allow symbols for PC-relative references.
3200 If pc_frag == 0, then we don't have frag locations yet. */
3202 || xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0)
3205 /* If it is a weak symbol, then assume it won't reach. */
3206 if (S_IS_WEAK (expr
->X_add_symbol
))
3209 if (is_direct_call_opcode (insn
->opcode
)
3210 && ! pc_frag
->tc_frag_data
.use_longcalls
)
3212 /* If callee is undefined or in a different segment, be
3213 optimistic and assume it will be in range. */
3214 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3218 /* Only references within a segment can be known to fit in the
3219 operands at assembly time. */
3220 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3223 symbolP
= expr
->X_add_symbol
;
3224 sym_frag
= symbol_get_frag (symbolP
);
3225 target
= S_GET_VALUE (symbolP
) + expr
->X_add_number
;
3226 pc
= pc_frag
->fr_address
+ pc_offset
;
3228 /* If frag has yet to be reached on this pass, assume it
3229 will move by STRETCH just as we did. If this is not so,
3230 it will be because some frag between grows, and that will
3231 force another pass. Beware zero-length frags. There
3232 should be a faster way to do this. */
3235 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3236 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3241 new_offset
= target
;
3242 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3243 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3248 /* The symbol should have a fixup associated with it. */
3257 /* Return TRUE on success. */
3260 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3265 memset (targ
, 0, sizeof (TInsn
));
3266 targ
->linenum
= insn
->linenum
;
3271 targ
->opcode
= bi
->opcode
;
3272 targ
->insn_type
= ITYPE_INSN
;
3273 targ
->is_specific_opcode
= FALSE
;
3275 for (; op
!= NULL
; op
= op
->next
)
3277 int op_num
= op
->op_num
;
3278 int op_data
= op
->op_data
;
3280 assert (op
->op_num
< MAX_INSN_ARGS
);
3282 if (targ
->ntok
<= op_num
)
3283 targ
->ntok
= op_num
+ 1;
3288 set_expr_const (&targ
->tok
[op_num
], op_data
);
3291 assert (op_data
< insn
->ntok
);
3292 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3295 sym
= get_special_literal_symbol ();
3296 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3299 sym
= get_special_label_symbol ();
3300 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3302 case OP_OPERAND_HI16U
:
3303 case OP_OPERAND_LOW16U
:
3304 assert (op_data
< insn
->ntok
);
3305 if (expr_is_const (&insn
->tok
[op_data
]))
3308 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3309 val
= xg_apply_userdef_op_fn (op
->typ
,
3312 targ
->tok
[op_num
].X_add_number
= val
;
3316 /* For const16 we can create relocations for these. */
3317 if (targ
->opcode
== XTENSA_UNDEFINED
3318 || (targ
->opcode
!= xtensa_const16_opcode
))
3320 assert (op_data
< insn
->ntok
);
3321 /* Need to build a O_lo16 or O_hi16. */
3322 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3323 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3325 if (op
->typ
== OP_OPERAND_HI16U
)
3326 targ
->tok
[op_num
].X_op
= O_hi16
;
3327 else if (op
->typ
== OP_OPERAND_LOW16U
)
3328 targ
->tok
[op_num
].X_op
= O_lo16
;
3335 /* currently handles:
3338 OP_OPERAND_F32MINUS */
3339 if (xg_has_userdef_op_fn (op
->typ
))
3341 assert (op_data
< insn
->ntok
);
3342 if (expr_is_const (&insn
->tok
[op_data
]))
3345 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3346 val
= xg_apply_userdef_op_fn (op
->typ
,
3349 targ
->tok
[op_num
].X_add_number
= val
;
3352 return FALSE
; /* We cannot use a relocation for this. */
3361 case INSTR_LITERAL_DEF
:
3363 targ
->opcode
= XTENSA_UNDEFINED
;
3364 targ
->insn_type
= ITYPE_LITERAL
;
3365 targ
->is_specific_opcode
= FALSE
;
3366 for (; op
!= NULL
; op
= op
->next
)
3368 int op_num
= op
->op_num
;
3369 int op_data
= op
->op_data
;
3370 assert (op
->op_num
< MAX_INSN_ARGS
);
3372 if (targ
->ntok
<= op_num
)
3373 targ
->ntok
= op_num
+ 1;
3378 assert (op_data
< insn
->ntok
);
3379 /* We can only pass resolvable literals through. */
3380 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3382 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3394 case INSTR_LABEL_DEF
:
3396 targ
->opcode
= XTENSA_UNDEFINED
;
3397 targ
->insn_type
= ITYPE_LABEL
;
3398 targ
->is_specific_opcode
= FALSE
;
3399 /* Literal with no ops is a label? */
3400 assert (op
== NULL
);
3411 /* Return TRUE on success. */
3414 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3416 for (; bi
!= NULL
; bi
= bi
->next
)
3418 TInsn
*next_insn
= istack_push_space (istack
);
3420 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3427 /* Return TRUE on valid expansion. */
3430 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3432 int stack_size
= istack
->ninsn
;
3433 int steps_taken
= 0;
3434 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3437 assert (insn
->insn_type
== ITYPE_INSN
);
3438 assert (insn
->opcode
< table
->num_opcodes
);
3440 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3442 TransitionRule
*rule
= l
->rule
;
3444 if (xg_instruction_matches_rule (insn
, rule
))
3446 if (lateral_steps
== steps_taken
)
3450 /* This is it. Expand the rule to the stack. */
3451 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3454 /* Check to see if it fits. */
3455 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3457 TInsn
*insn
= &istack
->insn
[i
];
3459 if (insn
->insn_type
== ITYPE_INSN
3460 && !tinsn_has_symbolic_operands (insn
)
3461 && !xg_immeds_fit (insn
))
3463 istack
->ninsn
= stack_size
;
3476 /* Relax the assembly instruction at least "min_steps".
3477 Return the number of steps taken. */
3480 xg_assembly_relax (IStack
*istack
,
3483 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3484 offsetT pc_offset
, /* offset in fragment */
3485 int min_steps
, /* minimum conversion steps */
3486 long stretch
) /* number of bytes stretched so far */
3488 int steps_taken
= 0;
3490 /* assert (has no symbolic operands)
3491 Some of its immeds don't fit.
3492 Try to build a relaxed version.
3493 This may go through a couple of stages
3494 of single instruction transformations before
3497 TInsn single_target
;
3499 int lateral_steps
= 0;
3500 int istack_size
= istack
->ninsn
;
3502 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3503 && steps_taken
>= min_steps
)
3505 istack_push (istack
, insn
);
3508 current_insn
= *insn
;
3510 /* Walk through all of the single instruction expansions. */
3511 while (xg_is_single_relaxable_insn (¤t_insn
, &single_target
, FALSE
))
3514 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3517 if (steps_taken
>= min_steps
)
3519 istack_push (istack
, &single_target
);
3523 current_insn
= single_target
;
3526 /* Now check for a multi-instruction expansion. */
3527 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3529 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3532 if (steps_taken
>= min_steps
)
3534 istack_push (istack
, ¤t_insn
);
3539 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3541 if (steps_taken
>= min_steps
)
3545 istack
->ninsn
= istack_size
;
3548 /* It's not going to work -- use the original. */
3549 istack_push (istack
, insn
);
3555 xg_force_frag_space (int size
)
3557 /* This may have the side effect of creating a new fragment for the
3558 space to go into. I just do not like the name of the "frag"
3565 xg_finish_frag (char *last_insn
,
3566 enum xtensa_relax_statesE frag_state
,
3567 enum xtensa_relax_statesE slot0_state
,
3569 bfd_boolean is_insn
)
3571 /* Finish off this fragment so that it has at LEAST the desired
3572 max_growth. If it doesn't fit in this fragment, close this one
3573 and start a new one. In either case, return a pointer to the
3574 beginning of the growth area. */
3578 xg_force_frag_space (max_growth
);
3580 old_frag
= frag_now
;
3582 frag_now
->fr_opcode
= last_insn
;
3584 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3586 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3587 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3589 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3590 xtensa_set_frag_assembly_state (frag_now
);
3592 /* Just to make sure that we did not split it up. */
3593 assert (old_frag
->fr_next
== frag_now
);
3597 /* Return TRUE if the target frag is one of the next non-empty frags. */
3600 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3605 for (; fragP
; fragP
= fragP
->fr_next
)
3607 if (fragP
== target
)
3609 if (fragP
->fr_fix
!= 0)
3611 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3613 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3614 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3616 if (fragP
->fr_type
== rs_space
)
3624 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3626 xtensa_isa isa
= xtensa_default_isa
;
3628 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3633 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) != 1
3634 && xtensa_opcode_is_jump (isa
, insn
->opcode
) != 1)
3637 for (i
= 0; i
< num_ops
; i
++)
3639 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3645 if (target_op
== -1)
3648 if (insn
->ntok
<= target_op
)
3651 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3654 sym
= insn
->tok
[target_op
].X_add_symbol
;
3658 if (insn
->tok
[target_op
].X_add_number
!= 0)
3661 target_frag
= symbol_get_frag (sym
);
3662 if (target_frag
== NULL
)
3665 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3666 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3674 xg_add_branch_and_loop_targets (TInsn
*insn
)
3676 xtensa_isa isa
= xtensa_default_isa
;
3677 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3679 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3682 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3683 && insn
->tok
[i
].X_op
== O_symbol
)
3684 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3688 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3689 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3693 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3695 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3696 && insn
->tok
[i
].X_op
== O_symbol
)
3698 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3699 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3700 if (S_IS_DEFINED (sym
))
3701 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3708 /* Return FALSE if no error. */
3711 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3716 switch (instr_spec
->typ
)
3719 new_insn
->insn_type
= ITYPE_INSN
;
3720 new_insn
->opcode
= instr_spec
->opcode
;
3721 new_insn
->is_specific_opcode
= FALSE
;
3722 new_insn
->linenum
= old_insn
->linenum
;
3724 case INSTR_LITERAL_DEF
:
3725 new_insn
->insn_type
= ITYPE_LITERAL
;
3726 new_insn
->opcode
= XTENSA_UNDEFINED
;
3727 new_insn
->is_specific_opcode
= FALSE
;
3728 new_insn
->linenum
= old_insn
->linenum
;
3730 case INSTR_LABEL_DEF
:
3731 as_bad (_("INSTR_LABEL_DEF not supported yet"));
3735 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3738 const expressionS
*src_exp
;
3744 /* The expression must be the constant. */
3745 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3746 exp
= &new_insn
->tok
[b_op
->op_num
];
3747 set_expr_const (exp
, b_op
->op_data
);
3751 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3752 assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
3753 src_exp
= &old_insn
->tok
[b_op
->op_data
];
3754 exp
= &new_insn
->tok
[b_op
->op_num
];
3755 copy_expr (exp
, src_exp
);
3760 as_bad (_("can't handle generation of literal/labels yet"));
3764 as_bad (_("can't handle undefined OP TYPE"));
3769 new_insn
->ntok
= num_ops
;
3774 /* Return TRUE if it was simplified. */
3777 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
3779 TransitionRule
*rule
;
3780 BuildInstr
*insn_spec
;
3782 if (old_insn
->is_specific_opcode
|| !density_supported
)
3785 rule
= xg_instruction_match (old_insn
);
3789 insn_spec
= rule
->to_instr
;
3790 /* There should only be one. */
3791 assert (insn_spec
!= NULL
);
3792 assert (insn_spec
->next
== NULL
);
3793 if (insn_spec
->next
!= NULL
)
3796 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
3802 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3803 l32i.n. (2) Check the number of operands. (3) Place the instruction
3804 tokens into the stack or relax it and place multiple
3805 instructions/literals onto the stack. Return FALSE if no error. */
3808 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
3812 bfd_boolean do_expand
;
3814 memset (&new_insn
, 0, sizeof (TInsn
));
3816 /* Narrow it if we can. xg_simplify_insn now does all the
3817 appropriate checking (e.g., for the density option). */
3818 if (xg_simplify_insn (orig_insn
, &new_insn
))
3819 orig_insn
= &new_insn
;
3821 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
3823 if (orig_insn
->ntok
< noperands
)
3825 as_bad (_("found %d operands for '%s': Expected %d"),
3827 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3831 if (orig_insn
->ntok
> noperands
)
3832 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
3834 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3837 /* If there are not enough operands, we will assert above. If there
3838 are too many, just cut out the extras here. */
3839 orig_insn
->ntok
= noperands
;
3841 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
3844 /* If the instruction will definitely need to be relaxed, it is better
3845 to expand it now for better scheduling. Decide whether to expand
3847 do_expand
= (!orig_insn
->is_specific_opcode
&& use_transform ());
3849 /* Calls should be expanded to longcalls only in the backend relaxation
3850 so that the assembly scheduler will keep the L32R/CALLX instructions
3852 if (is_direct_call_opcode (orig_insn
->opcode
))
3855 if (tinsn_has_symbolic_operands (orig_insn
))
3857 /* The values of symbolic operands are not known yet, so only expand
3858 now if an operand is "complex" (e.g., difference of symbols) and
3859 will have to be stored as a literal regardless of the value. */
3860 if (!tinsn_has_complex_operands (orig_insn
))
3863 else if (xg_immeds_fit (orig_insn
))
3867 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
3869 istack_push (istack
, orig_insn
);
3875 /* Return TRUE if the section flags are marked linkonce
3876 or the name is .gnu.linkonce.*. */
3878 static int linkonce_len
= sizeof (".gnu.linkonce.") - 1;
3881 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
3883 flagword flags
, link_once_flags
;
3885 flags
= bfd_get_section_flags (abfd
, sec
);
3886 link_once_flags
= (flags
& SEC_LINK_ONCE
);
3888 /* Flags might not be set yet. */
3889 if (!link_once_flags
3890 && strncmp (segment_name (sec
), ".gnu.linkonce.", linkonce_len
) == 0)
3891 link_once_flags
= SEC_LINK_ONCE
;
3893 return (link_once_flags
!= 0);
3898 xtensa_add_literal_sym (symbolS
*sym
)
3902 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
3904 l
->next
= literal_syms
;
3910 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
3912 static int lit_num
= 0;
3913 static char name
[256];
3916 sprintf (name
, ".L_lit_sym%d", lit_num
);
3918 /* Create a local symbol. If it is in a linkonce section, we have to
3919 be careful to make sure that if it is used in a relocation that the
3920 symbol will be in the output file. */
3921 if (get_is_linkonce_section (stdoutput
, sec
))
3923 symbolP
= symbol_new (name
, sec
, 0, frag
);
3924 S_CLEAR_EXTERNAL (symbolP
);
3925 /* symbolP->local = 1; */
3928 symbolP
= symbol_new (name
, sec
, 0, frag
);
3930 xtensa_add_literal_sym (symbolP
);
3937 /* Currently all literals that are generated here are 32-bit L32R targets. */
3940 xg_assemble_literal (/* const */ TInsn
*insn
)
3943 symbolS
*lit_sym
= NULL
;
3945 /* size = 4 for L32R. It could easily be larger when we move to
3946 larger constants. Add a parameter later. */
3947 offsetT litsize
= 4;
3948 offsetT litalign
= 2; /* 2^2 = 4 */
3949 expressionS saved_loc
;
3950 expressionS
* emit_val
;
3952 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
3954 assert (insn
->insn_type
== ITYPE_LITERAL
);
3955 assert (insn
->ntok
== 1); /* must be only one token here */
3957 xtensa_switch_to_literal_fragment (&state
);
3959 emit_val
= &insn
->tok
[0];
3960 if (emit_val
->X_op
== O_big
)
3962 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
3965 /* This happens when someone writes a "movi a2, big_number". */
3966 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
3967 _("invalid immediate"));
3968 xtensa_restore_emit_state (&state
);
3973 /* Force a 4-byte align here. Note that this opens a new frag, so all
3974 literals done with this function have a frag to themselves. That's
3975 important for the way text section literals work. */
3976 frag_align (litalign
, 0, 0);
3977 record_alignment (now_seg
, litalign
);
3979 if (emit_val
->X_op
== O_pltrel
)
3981 char *p
= frag_more (litsize
);
3982 xtensa_set_frag_assembly_state (frag_now
);
3983 if (emit_val
->X_add_symbol
)
3984 emit_val
->X_op
= O_symbol
;
3986 emit_val
->X_op
= O_constant
;
3987 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
3988 litsize
, emit_val
, 0, BFD_RELOC_XTENSA_PLT
);
3991 emit_expr (emit_val
, litsize
);
3993 assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
3994 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
3995 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
3996 lit_sym
= frag_now
->fr_symbol
;
3999 xtensa_restore_emit_state (&state
);
4005 xg_assemble_literal_space (/* const */ int size
, int slot
)
4008 /* We might have to do something about this alignment. It only
4009 takes effect if something is placed here. */
4010 offsetT litalign
= 2; /* 2^2 = 4 */
4011 fragS
*lit_saved_frag
;
4013 assert (size
% 4 == 0);
4015 xtensa_switch_to_literal_fragment (&state
);
4017 /* Force a 4-byte align here. */
4018 frag_align (litalign
, 0, 0);
4019 record_alignment (now_seg
, litalign
);
4021 xg_force_frag_space (size
);
4023 lit_saved_frag
= frag_now
;
4024 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4025 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4026 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4029 xtensa_restore_emit_state (&state
);
4030 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4034 /* Put in a fixup record based on the opcode.
4035 Return TRUE on success. */
4038 xg_add_opcode_fix (TInsn
*tinsn
,
4046 xtensa_opcode opcode
= tinsn
->opcode
;
4047 bfd_reloc_code_real_type reloc
;
4048 reloc_howto_type
*howto
;
4052 reloc
= BFD_RELOC_NONE
;
4054 /* First try the special cases for "alternate" relocs. */
4055 if (opcode
== xtensa_l32r_opcode
)
4057 if (fragP
->tc_frag_data
.use_absolute_literals
)
4058 reloc
= encode_alt_reloc (slot
);
4060 else if (opcode
== xtensa_const16_opcode
)
4062 if (expr
->X_op
== O_lo16
)
4064 reloc
= encode_reloc (slot
);
4065 expr
->X_op
= O_symbol
;
4067 else if (expr
->X_op
== O_hi16
)
4069 reloc
= encode_alt_reloc (slot
);
4070 expr
->X_op
= O_symbol
;
4074 if (opnum
!= get_relaxable_immed (opcode
))
4076 as_bad (_("invalid relocation for operand %i of '%s'"),
4077 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4081 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4082 into the symbol table where the generic portions of the assembler
4083 won't know what to do with them. */
4084 if (expr
->X_op
== O_lo16
|| expr
->X_op
== O_hi16
)
4086 as_bad (_("invalid expression for operand %i of '%s'"),
4087 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4091 /* Next try the generic relocs. */
4092 if (reloc
== BFD_RELOC_NONE
)
4093 reloc
= encode_reloc (slot
);
4094 if (reloc
== BFD_RELOC_NONE
)
4096 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4100 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4103 as_bad (_("undefined symbol for opcode \"%s\""),
4104 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4108 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4109 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, expr
,
4110 howto
->pc_relative
, reloc
);
4111 the_fix
->fx_no_overflow
= 1;
4113 if (expr
->X_add_symbol
4114 && (S_IS_EXTERNAL (expr
->X_add_symbol
)
4115 || S_IS_WEAK (expr
->X_add_symbol
)))
4116 the_fix
->fx_plt
= TRUE
;
4118 the_fix
->tc_fix_data
.X_add_symbol
= expr
->X_add_symbol
;
4119 the_fix
->tc_fix_data
.X_add_number
= expr
->X_add_number
;
4120 the_fix
->tc_fix_data
.slot
= slot
;
4127 xg_emit_insn_to_buf (TInsn
*tinsn
,
4131 bfd_boolean build_fix
)
4133 static xtensa_insnbuf insnbuf
= NULL
;
4134 bfd_boolean has_symbolic_immed
= FALSE
;
4135 bfd_boolean ok
= TRUE
;
4138 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4140 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4141 if (has_symbolic_immed
&& build_fix
)
4144 xtensa_format fmt
= xg_get_single_format (tinsn
->opcode
);
4145 int slot
= xg_get_single_slot (tinsn
->opcode
);
4146 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4147 expressionS
*exp
= &tinsn
->tok
[opnum
];
4149 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, slot
, exp
, fragP
, offset
))
4152 fragP
->tc_frag_data
.is_insn
= TRUE
;
4153 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4154 (unsigned char *) buf
, 0);
4160 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4162 symbolS
*sym
= get_special_literal_symbol ();
4166 assert (insn
->insn_type
== ITYPE_INSN
);
4167 for (i
= 0; i
< insn
->ntok
; i
++)
4168 if (insn
->tok
[i
].X_add_symbol
== sym
)
4169 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4175 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4177 symbolS
*sym
= get_special_label_symbol ();
4179 for (i
= 0; i
< insn
->ntok
; i
++)
4180 if (insn
->tok
[i
].X_add_symbol
== sym
)
4181 insn
->tok
[i
].X_add_symbol
= label_sym
;
4186 /* Return TRUE if the instruction can write to the specified
4187 integer register. */
4190 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4194 xtensa_isa isa
= xtensa_default_isa
;
4196 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4198 for (i
= 0; i
< num_ops
; i
++)
4201 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4202 if ((inout
== 'o' || inout
== 'm')
4203 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4205 xtensa_regfile opnd_rf
=
4206 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4207 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4209 if ((insn
->tok
[i
].X_op
== O_register
)
4210 && (insn
->tok
[i
].X_add_number
== regnum
))
4220 is_bad_loopend_opcode (const TInsn
*tinsn
)
4222 xtensa_opcode opcode
= tinsn
->opcode
;
4224 if (opcode
== XTENSA_UNDEFINED
)
4227 if (opcode
== xtensa_call0_opcode
4228 || opcode
== xtensa_callx0_opcode
4229 || opcode
== xtensa_call4_opcode
4230 || opcode
== xtensa_callx4_opcode
4231 || opcode
== xtensa_call8_opcode
4232 || opcode
== xtensa_callx8_opcode
4233 || opcode
== xtensa_call12_opcode
4234 || opcode
== xtensa_callx12_opcode
4235 || opcode
== xtensa_isync_opcode
4236 || opcode
== xtensa_ret_opcode
4237 || opcode
== xtensa_ret_n_opcode
4238 || opcode
== xtensa_retw_opcode
4239 || opcode
== xtensa_retw_n_opcode
4240 || opcode
== xtensa_waiti_opcode
4241 || opcode
== xtensa_rsr_lcount_opcode
)
4248 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4249 This allows the debugger to add unaligned labels.
4250 Also, the assembler generates stabs labels that need
4251 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4254 is_unaligned_label (symbolS
*sym
)
4256 const char *name
= S_GET_NAME (sym
);
4257 static size_t fake_size
= 0;
4261 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4264 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4266 fake_size
= strlen (FAKE_LABEL_NAME
);
4269 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4270 && (name
[fake_size
] == 'F'
4271 || name
[fake_size
] == 'L'
4272 || (name
[fake_size
] == 'e'
4273 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4281 next_non_empty_frag (const fragS
*fragP
)
4283 fragS
*next_fragP
= fragP
->fr_next
;
4285 /* Sometimes an empty will end up here due storage allocation issues.
4286 So we have to skip until we find something legit. */
4287 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4288 next_fragP
= next_fragP
->fr_next
;
4290 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4298 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4300 xtensa_opcode out_opcode
;
4301 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4303 if (next_fragP
== NULL
)
4306 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4307 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4309 *opcode
= out_opcode
;
4317 frag_format_size (const fragS
*fragP
)
4319 static xtensa_insnbuf insnbuf
= NULL
;
4320 xtensa_isa isa
= xtensa_default_isa
;
4325 insnbuf
= xtensa_insnbuf_alloc (isa
);
4328 return XTENSA_UNDEFINED
;
4330 xtensa_insnbuf_from_chars (isa
, insnbuf
,
4331 (unsigned char *) fragP
->fr_literal
, 0);
4333 fmt
= xtensa_format_decode (isa
, insnbuf
);
4334 if (fmt
== XTENSA_UNDEFINED
)
4335 return XTENSA_UNDEFINED
;
4336 fmt_size
= xtensa_format_length (isa
, fmt
);
4338 /* If the next format won't be changing due to relaxation, just
4339 return the length of the first format. */
4340 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4343 /* If during relaxation we have to pull an instruction out of a
4344 multi-slot instruction, we will return the more conservative
4345 number. This works because alignment on bigger instructions
4346 is more restrictive than alignment on smaller instructions.
4347 This is more conservative than we would like, but it happens
4350 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4353 /* If we aren't doing one of our own relaxations or it isn't
4354 slot-based, then the insn size won't change. */
4355 if (fragP
->fr_type
!= rs_machine_dependent
)
4357 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4360 /* If an instruction is about to grow, return the longer size. */
4361 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4362 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
)
4365 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4366 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4373 next_frag_format_size (const fragS
*fragP
)
4375 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4376 return frag_format_size (next_fragP
);
4380 /* In early Xtensa Processors, for reasons that are unclear, the ISA
4381 required two-byte instructions to be treated as three-byte instructions
4382 for loop instruction alignment. This restriction was removed beginning
4383 with Xtensa LX. Now the only requirement on loop instruction alignment
4384 is that the first instruction of the loop must appear at an address that
4385 does not cross a fetch boundary. */
4388 get_loop_align_size (int insn_size
)
4390 if (insn_size
== XTENSA_UNDEFINED
)
4391 return xtensa_fetch_width
;
4393 if (enforce_three_byte_loop_align
&& insn_size
== 2)
4400 /* If the next legit fragment is an end-of-loop marker,
4401 switch its state so it will instantiate a NOP. */
4404 update_next_frag_state (fragS
*fragP
)
4406 fragS
*next_fragP
= fragP
->fr_next
;
4407 fragS
*new_target
= NULL
;
4411 /* We are guaranteed there will be one of these... */
4412 while (!(next_fragP
->fr_type
== rs_machine_dependent
4413 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4414 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4415 next_fragP
= next_fragP
->fr_next
;
4417 assert (next_fragP
->fr_type
== rs_machine_dependent
4418 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4419 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4421 /* ...and one of these. */
4422 new_target
= next_fragP
->fr_next
;
4423 while (!(new_target
->fr_type
== rs_machine_dependent
4424 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4425 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4426 new_target
= new_target
->fr_next
;
4428 assert (new_target
->fr_type
== rs_machine_dependent
4429 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4430 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4433 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4435 if (next_fragP
->fr_type
== rs_machine_dependent
4436 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4438 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4442 next_fragP
= next_fragP
->fr_next
;
4448 next_frag_is_branch_target (const fragS
*fragP
)
4450 /* Sometimes an empty will end up here due to storage allocation issues,
4451 so we have to skip until we find something legit. */
4452 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4454 if (fragP
->tc_frag_data
.is_branch_target
)
4456 if (fragP
->fr_fix
!= 0)
4464 next_frag_is_loop_target (const fragS
*fragP
)
4466 /* Sometimes an empty will end up here due storage allocation issues.
4467 So we have to skip until we find something legit. */
4468 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4470 if (fragP
->tc_frag_data
.is_loop_target
)
4472 if (fragP
->fr_fix
!= 0)
4480 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4482 const fragS
*next_fragp
= fragp
->fr_next
;
4483 xtensa_opcode next_opcode
;
4485 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4488 /* Sometimes an empty will end up here due to storage allocation issues,
4489 so we have to skip until we find something legit. */
4490 while (next_fragp
->fr_fix
== 0)
4491 next_fragp
= next_fragp
->fr_next
;
4493 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4496 /* There is some implicit knowledge encoded in here.
4497 The LOOP instructions that are NOT RELAX_IMMED have
4498 been relaxed. Note that we can assume that the LOOP
4499 instruction is in slot 0 because loops aren't bundleable. */
4500 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4501 return get_expanded_loop_offset (next_opcode
);
4507 /* Mark a location where we can later insert literal frags. Update
4508 the section's literal_pool_loc, so subsequent literals can be
4509 placed nearest to their use. */
4512 xtensa_mark_literal_pool_location (void)
4514 /* Any labels pointing to the current location need
4515 to be adjusted to after the literal pool. */
4517 fragS
*pool_location
;
4519 if (use_literal_section
)
4522 /* We stash info in these frags so we can later move the literal's
4523 fixes into this frchain's fix list. */
4524 pool_location
= frag_now
;
4525 frag_now
->tc_frag_data
.lit_frchain
= frchain_now
;
4526 frag_variant (rs_machine_dependent
, 0, 0,
4527 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4528 xtensa_set_frag_assembly_state (frag_now
);
4529 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
4530 frag_variant (rs_machine_dependent
, 0, 0,
4531 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4532 xtensa_set_frag_assembly_state (frag_now
);
4534 /* Now put a frag into the literal pool that points to this location. */
4535 set_literal_pool_location (now_seg
, pool_location
);
4536 xtensa_switch_to_non_abs_literal_fragment (&s
);
4537 frag_align (2, 0, 0);
4538 record_alignment (now_seg
, 2);
4540 /* Close whatever frag is there. */
4541 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4542 xtensa_set_frag_assembly_state (frag_now
);
4543 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
4544 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4545 xtensa_restore_emit_state (&s
);
4546 xtensa_set_frag_assembly_state (frag_now
);
4550 /* Build a nop of the correct size into tinsn. */
4553 build_nop (TInsn
*tinsn
, int size
)
4559 tinsn
->opcode
= xtensa_nop_n_opcode
;
4561 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4562 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4566 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4568 tinsn
->opcode
= xtensa_or_opcode
;
4569 set_expr_const (&tinsn
->tok
[0], 1);
4570 set_expr_const (&tinsn
->tok
[1], 1);
4571 set_expr_const (&tinsn
->tok
[2], 1);
4575 tinsn
->opcode
= xtensa_nop_opcode
;
4577 assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4582 /* Assemble a NOP of the requested size in the buffer. User must have
4583 allocated "buf" with at least "size" bytes. */
4586 assemble_nop (int size
, char *buf
)
4588 static xtensa_insnbuf insnbuf
= NULL
;
4591 build_nop (&tinsn
, size
);
4594 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4596 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4597 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4598 (unsigned char *) buf
, 0);
4602 /* Return the number of bytes for the offset of the expanded loop
4603 instruction. This should be incorporated into the relaxation
4604 specification but is hard-coded here. This is used to auto-align
4605 the loop instruction. It is invalid to call this function if the
4606 configuration does not have loops or if the opcode is not a loop
4610 get_expanded_loop_offset (xtensa_opcode opcode
)
4612 /* This is the OFFSET of the loop instruction in the expanded loop.
4613 This MUST correspond directly to the specification of the loop
4614 expansion. It will be validated on fragment conversion. */
4615 assert (opcode
!= XTENSA_UNDEFINED
);
4616 if (opcode
== xtensa_loop_opcode
)
4618 if (opcode
== xtensa_loopnez_opcode
)
4620 if (opcode
== xtensa_loopgtz_opcode
)
4622 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4628 get_literal_pool_location (segT seg
)
4630 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4635 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4637 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4641 /* Set frag assembly state should be called when a new frag is
4642 opened and after a frag has been closed. */
4645 xtensa_set_frag_assembly_state (fragS
*fragP
)
4647 if (!density_supported
)
4648 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4650 /* This function is called from subsegs_finish, which is called
4651 after xtensa_end, so we can't use "use_transform" or
4652 "use_schedule" here. */
4653 if (!directive_state
[directive_transform
])
4654 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4655 if (directive_state
[directive_longcalls
])
4656 fragP
->tc_frag_data
.use_longcalls
= TRUE
;
4657 fragP
->tc_frag_data
.use_absolute_literals
=
4658 directive_state
[directive_absolute_literals
];
4659 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4664 relaxable_section (asection
*sec
)
4666 return (sec
->flags
& SEC_DEBUGGING
) == 0;
4671 xtensa_find_unmarked_state_frags (void)
4675 /* Walk over each fragment of all of the current segments. For each
4676 unmarked fragment, mark it with the same info as the previous
4678 for (seclist
= &stdoutput
->sections
;
4679 seclist
&& *seclist
;
4680 seclist
= &(*seclist
)->next
)
4682 segT sec
= *seclist
;
4683 segment_info_type
*seginfo
;
4686 flags
= bfd_get_section_flags (stdoutput
, sec
);
4687 if (flags
& SEC_DEBUGGING
)
4689 if (!(flags
& SEC_ALLOC
))
4692 seginfo
= seg_info (sec
);
4693 if (seginfo
&& seginfo
->frchainP
)
4695 fragS
*last_fragP
= 0;
4696 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4697 fragP
= fragP
->fr_next
)
4699 if (fragP
->fr_fix
!= 0
4700 && !fragP
->tc_frag_data
.is_assembly_state_set
)
4702 if (last_fragP
== 0)
4704 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
4705 _("assembly state not set for first frag in section %s"),
4710 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4711 fragP
->tc_frag_data
.is_no_density
=
4712 last_fragP
->tc_frag_data
.is_no_density
;
4713 fragP
->tc_frag_data
.is_no_transform
=
4714 last_fragP
->tc_frag_data
.is_no_transform
;
4715 fragP
->tc_frag_data
.use_longcalls
=
4716 last_fragP
->tc_frag_data
.use_longcalls
;
4717 fragP
->tc_frag_data
.use_absolute_literals
=
4718 last_fragP
->tc_frag_data
.use_absolute_literals
;
4721 if (fragP
->tc_frag_data
.is_assembly_state_set
)
4730 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
4732 void *unused ATTRIBUTE_UNUSED
)
4734 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4735 segment_info_type
*seginfo
= seg_info (sec
);
4736 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4738 if (flags
& SEC_CODE
)
4740 xtensa_isa isa
= xtensa_default_isa
;
4741 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4742 while (frag
!= NULL
)
4744 if (frag
->tc_frag_data
.is_branch_target
)
4747 addressT branch_align
, frag_addr
;
4750 xtensa_insnbuf_from_chars
4751 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4752 fmt
= xtensa_format_decode (isa
, insnbuf
);
4753 op_size
= xtensa_format_length (isa
, fmt
);
4754 branch_align
= 1 << branch_align_power (sec
);
4755 frag_addr
= frag
->fr_address
% branch_align
;
4756 if (frag_addr
+ op_size
> branch_align
)
4757 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4758 _("unaligned branch target: %d bytes at 0x%lx"),
4759 op_size
, (long) frag
->fr_address
);
4761 frag
= frag
->fr_next
;
4763 xtensa_insnbuf_free (isa
, insnbuf
);
4769 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
4771 void *unused ATTRIBUTE_UNUSED
)
4773 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4774 segment_info_type
*seginfo
= seg_info (sec
);
4775 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4776 xtensa_isa isa
= xtensa_default_isa
;
4778 if (flags
& SEC_CODE
)
4780 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4781 while (frag
!= NULL
)
4783 if (frag
->tc_frag_data
.is_first_loop_insn
)
4789 xtensa_insnbuf_from_chars
4790 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4791 fmt
= xtensa_format_decode (isa
, insnbuf
);
4792 op_size
= xtensa_format_length (isa
, fmt
);
4793 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
4795 if (frag_addr
+ op_size
> xtensa_fetch_width
)
4796 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4797 _("unaligned loop: %d bytes at 0x%lx"),
4798 op_size
, (long) frag
->fr_address
);
4800 frag
= frag
->fr_next
;
4802 xtensa_insnbuf_free (isa
, insnbuf
);
4808 xg_apply_fix_value (fixS
*fixP
, valueT val
)
4810 xtensa_isa isa
= xtensa_default_isa
;
4811 static xtensa_insnbuf insnbuf
= NULL
;
4812 static xtensa_insnbuf slotbuf
= NULL
;
4815 bfd_boolean alt_reloc
;
4816 xtensa_opcode opcode
;
4817 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
4819 (void) decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
);
4821 as_fatal (_("unexpected fix"));
4825 insnbuf
= xtensa_insnbuf_alloc (isa
);
4826 slotbuf
= xtensa_insnbuf_alloc (isa
);
4829 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4830 fmt
= xtensa_format_decode (isa
, insnbuf
);
4831 if (fmt
== XTENSA_UNDEFINED
)
4832 as_fatal (_("undecodable fix"));
4833 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4834 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
4835 if (opcode
== XTENSA_UNDEFINED
)
4836 as_fatal (_("undecodable fix"));
4838 /* CONST16 immediates are not PC-relative, despite the fact that we
4839 reuse the normal PC-relative operand relocations for the low part
4840 of a CONST16 operand. */
4841 if (opcode
== xtensa_const16_opcode
)
4844 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
4845 get_relaxable_immed (opcode
), val
,
4846 fixP
->fx_file
, fixP
->fx_line
);
4848 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4849 xtensa_insnbuf_to_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4855 /* External Functions and Other GAS Hooks. */
4858 xtensa_target_format (void)
4860 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
4865 xtensa_file_arch_init (bfd
*abfd
)
4867 bfd_set_private_flags (abfd
, 0x100 | 0x200);
4872 md_number_to_chars (char *buf
, valueT val
, int n
)
4874 if (target_big_endian
)
4875 number_to_chars_bigendian (buf
, val
, n
);
4877 number_to_chars_littleendian (buf
, val
, n
);
4881 /* This function is called once, at assembler startup time. It should
4882 set up all the tables, etc. that the MD part of the assembler will
4888 segT current_section
= now_seg
;
4889 int current_subsec
= now_subseg
;
4892 xtensa_default_isa
= xtensa_isa_init (0, 0);
4893 isa
= xtensa_default_isa
;
4897 /* Set up the literal sections. */
4898 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
4900 subseg_set (current_section
, current_subsec
);
4902 xg_init_vinsn (&cur_vinsn
);
4904 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
4905 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
4906 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
4907 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
4908 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
4909 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
4910 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
4911 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
4912 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
4913 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
4914 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
4915 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
4916 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
4917 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
4918 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
4919 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
4920 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
4921 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
4922 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
4923 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
4924 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
4925 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
4926 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
4927 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
4928 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
4929 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
4930 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
4931 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
4932 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
4934 init_op_placement_info_table ();
4936 /* Set up the assembly state. */
4937 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
4938 xtensa_set_frag_assembly_state (frag_now
);
4942 /* TC_INIT_FIX_DATA hook */
4945 xtensa_init_fix_data (fixS
*x
)
4947 x
->tc_fix_data
.slot
= 0;
4948 x
->tc_fix_data
.X_add_symbol
= NULL
;
4949 x
->tc_fix_data
.X_add_number
= 0;
4953 /* tc_frob_label hook */
4956 xtensa_frob_label (symbolS
*sym
)
4960 if (cur_vinsn
.inside_bundle
)
4962 as_bad (_("labels are not valid inside bundles"));
4966 freq
= get_subseg_target_freq (now_seg
, now_subseg
);
4968 /* Since the label was already attached to a frag associated with the
4969 previous basic block, it now needs to be reset to the current frag. */
4970 symbol_set_frag (sym
, frag_now
);
4971 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
4973 if (generating_literals
)
4974 xtensa_add_literal_sym (sym
);
4976 xtensa_add_insn_label (sym
);
4978 if (symbol_get_tc (sym
)->is_loop_target
)
4980 if ((get_last_insn_flags (now_seg
, now_subseg
)
4981 & FLAG_IS_BAD_LOOPEND
) != 0)
4982 as_bad (_("invalid last instruction for a zero-overhead loop"));
4984 xtensa_set_frag_assembly_state (frag_now
);
4985 frag_var (rs_machine_dependent
, 4, 4, RELAX_LOOP_END
,
4986 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
4988 xtensa_set_frag_assembly_state (frag_now
);
4989 xtensa_move_labels (frag_now
, 0, TRUE
);
4992 /* No target aligning in the absolute section. */
4993 if (now_seg
!= absolute_section
4994 && do_align_targets ()
4995 && !is_unaligned_label (sym
)
4996 && !generating_literals
)
4998 xtensa_set_frag_assembly_state (frag_now
);
5000 frag_var (rs_machine_dependent
,
5002 RELAX_DESIRE_ALIGN_IF_TARGET
,
5003 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5004 xtensa_set_frag_assembly_state (frag_now
);
5005 xtensa_move_labels (frag_now
, 0, TRUE
);
5008 /* We need to mark the following properties even if we aren't aligning. */
5010 /* If the label is already known to be a branch target, i.e., a
5011 forward branch, mark the frag accordingly. Backward branches
5012 are handled by xg_add_branch_and_loop_targets. */
5013 if (symbol_get_tc (sym
)->is_branch_target
)
5014 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5016 /* Loops only go forward, so they can be identified here. */
5017 if (symbol_get_tc (sym
)->is_loop_target
)
5018 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5020 dwarf2_emit_label (sym
);
5024 /* tc_unrecognized_line hook */
5027 xtensa_unrecognized_line (int ch
)
5032 if (cur_vinsn
.inside_bundle
== 0)
5034 /* PR8110: Cannot emit line number info inside a FLIX bundle
5035 when using --gstabs. Temporarily disable debug info. */
5036 generate_lineno_debug ();
5037 if (debug_type
== DEBUG_STABS
)
5039 xt_saved_debug_type
= debug_type
;
5040 debug_type
= DEBUG_NONE
;
5043 cur_vinsn
.inside_bundle
= 1;
5047 as_bad (_("extra opening brace"));
5053 if (cur_vinsn
.inside_bundle
)
5054 finish_vinsn (&cur_vinsn
);
5057 as_bad (_("extra closing brace"));
5062 as_bad (_("syntax error"));
5069 /* md_flush_pending_output hook */
5072 xtensa_flush_pending_output (void)
5074 if (cur_vinsn
.inside_bundle
)
5075 as_bad (_("missing closing brace"));
5077 /* If there is a non-zero instruction fragment, close it. */
5078 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5080 frag_wane (frag_now
);
5082 xtensa_set_frag_assembly_state (frag_now
);
5084 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5086 xtensa_clear_insn_labels ();
5090 /* We had an error while parsing an instruction. The string might look
5091 like this: "insn arg1, arg2 }". If so, we need to see the closing
5092 brace and reset some fields. Otherwise, the vinsn never gets closed
5093 and the num_slots field will grow past the end of the array of slots,
5094 and bad things happen. */
5097 error_reset_cur_vinsn (void)
5099 if (cur_vinsn
.inside_bundle
)
5101 if (*input_line_pointer
== '}'
5102 || *(input_line_pointer
- 1) == '}'
5103 || *(input_line_pointer
- 2) == '}')
5104 xg_clear_vinsn (&cur_vinsn
);
5110 md_assemble (char *str
)
5112 xtensa_isa isa
= xtensa_default_isa
;
5113 char *opname
, *file_name
;
5115 bfd_boolean has_underbar
= FALSE
;
5116 char *arg_strings
[MAX_INSN_ARGS
];
5118 TInsn orig_insn
; /* Original instruction from the input. */
5120 tinsn_init (&orig_insn
);
5122 /* Split off the opcode. */
5123 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5124 opname
= xmalloc (opnamelen
+ 1);
5125 memcpy (opname
, str
, opnamelen
);
5126 opname
[opnamelen
] = '\0';
5128 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5131 as_bad (_("syntax error"));
5135 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5138 /* Check for an underbar prefix. */
5141 has_underbar
= TRUE
;
5145 orig_insn
.insn_type
= ITYPE_INSN
;
5147 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5149 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5150 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5152 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5153 if (fmt
== XTENSA_UNDEFINED
)
5155 as_bad (_("unknown opcode or format name '%s'"), opname
);
5156 error_reset_cur_vinsn ();
5159 if (!cur_vinsn
.inside_bundle
)
5161 as_bad (_("format names only valid inside bundles"));
5162 error_reset_cur_vinsn ();
5165 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5166 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5168 cur_vinsn
.format
= fmt
;
5169 free (has_underbar
? opname
- 1 : opname
);
5170 error_reset_cur_vinsn ();
5174 /* Parse the arguments. */
5175 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5177 as_bad (_("syntax error"));
5178 error_reset_cur_vinsn ();
5182 /* Free the opcode and argument strings, now that they've been parsed. */
5183 free (has_underbar
? opname
- 1 : opname
);
5185 while (num_args
-- > 0)
5186 free (arg_strings
[num_args
]);
5188 /* Get expressions for invisible operands. */
5189 if (get_invisible_operands (&orig_insn
))
5191 error_reset_cur_vinsn ();
5195 /* Check for the right number and type of arguments. */
5196 if (tinsn_check_arguments (&orig_insn
))
5198 error_reset_cur_vinsn ();
5202 /* A FLIX bundle may be spread across multiple input lines. We want to
5203 report the first such line in the debug information. Record the line
5204 number for each TInsn (assume the file name doesn't change), so the
5205 first line can be found later. */
5206 as_where (&file_name
, &orig_insn
.linenum
);
5208 xg_add_branch_and_loop_targets (&orig_insn
);
5210 /* Check that immediate value for ENTRY is >= 16. */
5211 if (orig_insn
.opcode
== xtensa_entry_opcode
&& orig_insn
.ntok
>= 3)
5213 expressionS
*exp
= &orig_insn
.tok
[2];
5214 if (exp
->X_op
== O_constant
&& exp
->X_add_number
< 16)
5215 as_warn (_("entry instruction with stack decrement < 16"));
5219 assemble_tokens (opcode, tok, ntok);
5220 expand the tokens from the orig_insn into the
5221 stack of instructions that will not expand
5222 unless required at relaxation time. */
5224 if (!cur_vinsn
.inside_bundle
)
5225 emit_single_op (&orig_insn
);
5226 else /* We are inside a bundle. */
5228 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5229 cur_vinsn
.num_slots
++;
5230 if (*input_line_pointer
== '}'
5231 || *(input_line_pointer
- 1) == '}'
5232 || *(input_line_pointer
- 2) == '}')
5233 finish_vinsn (&cur_vinsn
);
5236 /* We've just emitted a new instruction so clear the list of labels. */
5237 xtensa_clear_insn_labels ();
5241 /* HANDLE_ALIGN hook */
5243 /* For a .align directive, we mark the previous block with the alignment
5244 information. This will be placed in the object file in the
5245 property section corresponding to this section. */
5248 xtensa_handle_align (fragS
*fragP
)
5251 && ! fragP
->tc_frag_data
.is_literal
5252 && (fragP
->fr_type
== rs_align
5253 || fragP
->fr_type
== rs_align_code
)
5254 && fragP
->fr_address
+ fragP
->fr_fix
> 0
5255 && fragP
->fr_offset
> 0
5256 && now_seg
!= bss_section
)
5258 fragP
->tc_frag_data
.is_align
= TRUE
;
5259 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5262 if (fragP
->fr_type
== rs_align_test
)
5265 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5267 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5268 _("unaligned entry instruction"));
5273 /* TC_FRAG_INIT hook */
5276 xtensa_frag_init (fragS
*frag
)
5278 xtensa_set_frag_assembly_state (frag
);
5283 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5289 /* Round up a section size to the appropriate boundary. */
5292 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5294 return size
; /* Byte alignment is fine. */
5299 md_pcrel_from (fixS
*fixP
)
5302 static xtensa_insnbuf insnbuf
= NULL
;
5303 static xtensa_insnbuf slotbuf
= NULL
;
5306 xtensa_opcode opcode
;
5309 xtensa_isa isa
= xtensa_default_isa
;
5310 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5311 bfd_boolean alt_reloc
;
5313 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5318 insnbuf
= xtensa_insnbuf_alloc (isa
);
5319 slotbuf
= xtensa_insnbuf_alloc (isa
);
5322 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5323 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) insn_p
, 0);
5324 fmt
= xtensa_format_decode (isa
, insnbuf
);
5326 if (fmt
== XTENSA_UNDEFINED
)
5327 as_fatal (_("bad instruction format"));
5329 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5330 as_fatal (_("invalid relocation"));
5332 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5333 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5335 /* Check for "alternate" relocations (operand not specified). None
5336 of the current uses for these are really PC-relative. */
5337 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5339 if (opcode
!= xtensa_l32r_opcode
5340 && opcode
!= xtensa_const16_opcode
)
5341 as_fatal (_("invalid relocation for '%s' instruction"),
5342 xtensa_opcode_name (isa
, opcode
));
5346 opnum
= get_relaxable_immed (opcode
);
5348 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5349 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5351 as_bad_where (fixP
->fx_file
,
5353 _("invalid relocation for operand %d of '%s'"),
5354 opnum
, xtensa_opcode_name (isa
, opcode
));
5357 return 0 - opnd_value
;
5361 /* TC_FORCE_RELOCATION hook */
5364 xtensa_force_relocation (fixS
*fix
)
5366 switch (fix
->fx_r_type
)
5368 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5369 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5370 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5371 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5372 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5373 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5374 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5375 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5376 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5377 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5378 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5379 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5380 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5381 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5382 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5383 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5389 if (linkrelax
&& fix
->fx_addsy
5390 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5393 return generic_force_reloc (fix
);
5397 /* TC_VALIDATE_FIX_SUB hook */
5400 xtensa_validate_fix_sub (fixS
*fix
)
5402 segT add_symbol_segment
, sub_symbol_segment
;
5404 /* The difference of two symbols should be resolved by the assembler when
5405 linkrelax is not set. If the linker may relax the section containing
5406 the symbols, then an Xtensa DIFF relocation must be generated so that
5407 the linker knows to adjust the difference value. */
5408 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
5411 /* Make sure both symbols are in the same segment, and that segment is
5412 "normal" and relaxable. If the segment is not "normal", then the
5413 fix is not valid. If the segment is not "relaxable", then the fix
5414 should have been handled earlier. */
5415 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
5416 if (! SEG_NORMAL (add_symbol_segment
) ||
5417 ! relaxable_section (add_symbol_segment
))
5419 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
5420 return (sub_symbol_segment
== add_symbol_segment
);
5424 /* NO_PSEUDO_DOT hook */
5426 /* This function has nothing to do with pseudo dots, but this is the
5427 nearest macro to where the check needs to take place. FIXME: This
5431 xtensa_check_inside_bundle (void)
5433 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5434 as_bad (_("directives are not valid inside bundles"));
5436 /* This function must always return FALSE because it is called via a
5437 macro that has nothing to do with bundling. */
5442 /* md_elf_section_change_hook */
5445 xtensa_elf_section_change_hook (void)
5447 /* Set up the assembly state. */
5448 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5449 xtensa_set_frag_assembly_state (frag_now
);
5453 /* tc_fix_adjustable hook */
5456 xtensa_fix_adjustable (fixS
*fixP
)
5458 /* An offset is not allowed in combination with the difference of two
5459 symbols, but that cannot be easily detected after a local symbol
5460 has been adjusted to a (section+offset) form. Return 0 so that such
5461 an fix will not be adjusted. */
5462 if (fixP
->fx_subsy
&& fixP
->fx_addsy
&& fixP
->fx_offset
5463 && relaxable_section (S_GET_SEGMENT (fixP
->fx_subsy
)))
5466 /* We need the symbol name for the VTABLE entries. */
5467 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5468 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5476 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg
)
5478 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5481 /* Subtracted symbols are only allowed for a few relocation types, and
5482 unless linkrelax is enabled, they should not make it to this point. */
5483 if (fixP
->fx_subsy
&& !(linkrelax
&& (fixP
->fx_r_type
== BFD_RELOC_32
5484 || fixP
->fx_r_type
== BFD_RELOC_16
5485 || fixP
->fx_r_type
== BFD_RELOC_8
)))
5486 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("expression too complex"));
5488 switch (fixP
->fx_r_type
)
5495 switch (fixP
->fx_r_type
)
5498 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF8
;
5501 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF16
;
5504 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF32
;
5510 /* An offset is only allowed when it results from adjusting a
5511 local symbol into a section-relative offset. If the offset
5512 came from the original expression, tc_fix_adjustable will have
5513 prevented the fix from being converted to a section-relative
5514 form so that we can flag the error here. */
5515 if (fixP
->fx_offset
!= 0 && !symbol_section_p (fixP
->fx_addsy
))
5516 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5517 _("cannot represent subtraction with an offset"));
5519 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5520 - S_GET_VALUE (fixP
->fx_subsy
));
5522 /* The difference value gets written out, and the DIFF reloc
5523 identifies the address of the subtracted symbol (i.e., the one
5524 with the lowest address). */
5526 fixP
->fx_offset
-= val
;
5527 fixP
->fx_subsy
= NULL
;
5529 else if (! fixP
->fx_addsy
)
5536 case BFD_RELOC_XTENSA_PLT
:
5537 md_number_to_chars (fixpos
, val
, fixP
->fx_size
);
5538 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5541 case BFD_RELOC_XTENSA_SLOT0_OP
:
5542 case BFD_RELOC_XTENSA_SLOT1_OP
:
5543 case BFD_RELOC_XTENSA_SLOT2_OP
:
5544 case BFD_RELOC_XTENSA_SLOT3_OP
:
5545 case BFD_RELOC_XTENSA_SLOT4_OP
:
5546 case BFD_RELOC_XTENSA_SLOT5_OP
:
5547 case BFD_RELOC_XTENSA_SLOT6_OP
:
5548 case BFD_RELOC_XTENSA_SLOT7_OP
:
5549 case BFD_RELOC_XTENSA_SLOT8_OP
:
5550 case BFD_RELOC_XTENSA_SLOT9_OP
:
5551 case BFD_RELOC_XTENSA_SLOT10_OP
:
5552 case BFD_RELOC_XTENSA_SLOT11_OP
:
5553 case BFD_RELOC_XTENSA_SLOT12_OP
:
5554 case BFD_RELOC_XTENSA_SLOT13_OP
:
5555 case BFD_RELOC_XTENSA_SLOT14_OP
:
5558 /* Write the tentative value of a PC-relative relocation to a
5559 local symbol into the instruction. The value will be ignored
5560 by the linker, and it makes the object file disassembly
5561 readable when all branch targets are encoded in relocations. */
5563 assert (fixP
->fx_addsy
);
5564 if (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
&& !fixP
->fx_plt
5565 && !S_FORCE_RELOC (fixP
->fx_addsy
, 1))
5567 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5568 - md_pcrel_from (fixP
));
5569 (void) xg_apply_fix_value (fixP
, val
);
5572 else if (! fixP
->fx_addsy
)
5575 if (xg_apply_fix_value (fixP
, val
))
5580 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5581 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5582 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5583 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5584 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5585 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5586 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5587 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5588 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5589 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5590 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5591 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5592 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5593 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5594 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5595 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5596 /* These all need to be resolved at link-time. Do nothing now. */
5599 case BFD_RELOC_VTABLE_INHERIT
:
5600 case BFD_RELOC_VTABLE_ENTRY
:
5605 as_bad (_("unhandled local relocation fix %s"),
5606 bfd_get_reloc_code_name (fixP
->fx_r_type
));
5612 md_atof (int type
, char *litP
, int *sizeP
)
5615 LITTLENUM_TYPE words
[4];
5631 return "bad call to md_atof";
5634 t
= atof_ieee (input_line_pointer
, type
, words
);
5636 input_line_pointer
= t
;
5640 for (i
= prec
- 1; i
>= 0; i
--)
5643 if (target_big_endian
)
5644 idx
= (prec
- 1 - i
);
5646 md_number_to_chars (litP
, (valueT
) words
[idx
], 2);
5655 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
5657 return total_frag_text_expansion (fragP
);
5661 /* Translate internal representation of relocation info to BFD target
5665 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
5669 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
5670 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5671 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5672 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5674 /* Make sure none of our internal relocations make it this far.
5675 They'd better have been fully resolved by this point. */
5676 assert ((int) fixp
->fx_r_type
> 0);
5678 reloc
->addend
= fixp
->fx_offset
;
5680 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
5681 if (reloc
->howto
== NULL
)
5683 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5684 _("cannot represent `%s' relocation in object file"),
5685 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5686 free (reloc
->sym_ptr_ptr
);
5691 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
5692 as_fatal (_("internal error? cannot generate `%s' relocation"),
5693 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5699 /* Checks for resource conflicts between instructions. */
5701 /* The func unit stuff could be implemented as bit-vectors rather
5702 than the iterative approach here. If it ends up being too
5703 slow, we will switch it. */
5706 new_resource_table (void *data
,
5709 unit_num_copies_func uncf
,
5710 opcode_num_units_func onuf
,
5711 opcode_funcUnit_use_unit_func ouuf
,
5712 opcode_funcUnit_use_stage_func ousf
)
5715 resource_table
*rt
= (resource_table
*) xmalloc (sizeof (resource_table
));
5717 rt
->cycles
= cycles
;
5718 rt
->allocated_cycles
= cycles
;
5720 rt
->unit_num_copies
= uncf
;
5721 rt
->opcode_num_units
= onuf
;
5722 rt
->opcode_unit_use
= ouuf
;
5723 rt
->opcode_unit_stage
= ousf
;
5725 rt
->units
= (unsigned char **) xcalloc (cycles
, sizeof (unsigned char *));
5726 for (i
= 0; i
< cycles
; i
++)
5727 rt
->units
[i
] = (unsigned char *) xcalloc (nu
, sizeof (unsigned char));
5734 clear_resource_table (resource_table
*rt
)
5737 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
5738 for (j
= 0; j
< rt
->num_units
; j
++)
5739 rt
->units
[i
][j
] = 0;
5743 /* We never shrink it, just fake it into thinking so. */
5746 resize_resource_table (resource_table
*rt
, int cycles
)
5750 rt
->cycles
= cycles
;
5751 if (cycles
<= rt
->allocated_cycles
)
5754 old_cycles
= rt
->allocated_cycles
;
5755 rt
->allocated_cycles
= cycles
;
5757 rt
->units
= xrealloc (rt
->units
,
5758 rt
->allocated_cycles
* sizeof (unsigned char *));
5759 for (i
= 0; i
< old_cycles
; i
++)
5760 rt
->units
[i
] = xrealloc (rt
->units
[i
],
5761 rt
->num_units
* sizeof (unsigned char));
5762 for (i
= old_cycles
; i
< cycles
; i
++)
5763 rt
->units
[i
] = xcalloc (rt
->num_units
, sizeof (unsigned char));
5768 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5771 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5773 for (i
= 0; i
< uses
; i
++)
5775 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5776 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5777 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
5778 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
5779 if (copies_in_use
>= copies
)
5787 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5790 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5792 for (i
= 0; i
< uses
; i
++)
5794 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5795 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5796 /* Note that this allows resources to be oversubscribed. That's
5797 essential to the way the optional scheduler works.
5798 resources_available reports when a resource is over-subscribed,
5799 so it's easy to tell. */
5800 rt
->units
[stage
+ cycle
][unit
]++;
5806 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5809 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5811 for (i
= 0; i
< uses
; i
++)
5813 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5814 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5815 assert (rt
->units
[stage
+ cycle
][unit
] > 0);
5816 rt
->units
[stage
+ cycle
][unit
]--;
5821 /* Wrapper functions make parameterized resource reservation
5825 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
5827 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5833 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
5835 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5840 /* Note that this function does not check issue constraints, but
5841 solely whether the hardware is available to execute the given
5842 instructions together. It also doesn't check if the tinsns
5843 write the same state, or access the same tieports. That is
5844 checked by check_t1_t2_reads_and_writes. */
5847 resources_conflict (vliw_insn
*vinsn
)
5850 static resource_table
*rt
= NULL
;
5852 /* This is the most common case by far. Optimize it. */
5853 if (vinsn
->num_slots
== 1)
5858 xtensa_isa isa
= xtensa_default_isa
;
5859 rt
= new_resource_table
5860 (isa
, xtensa_isa_num_pipe_stages (isa
),
5861 xtensa_isa_num_funcUnits (isa
),
5862 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
5863 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
5864 opcode_funcUnit_use_unit
,
5865 opcode_funcUnit_use_stage
);
5868 clear_resource_table (rt
);
5870 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5872 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
5874 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
5881 /* finish_vinsn, emit_single_op and helper functions. */
5883 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
5884 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
5885 static void xg_assemble_vliw_tokens (vliw_insn
*);
5888 /* We have reached the end of a bundle; emit into the frag. */
5891 finish_vinsn (vliw_insn
*vinsn
)
5898 if (find_vinsn_conflicts (vinsn
))
5900 xg_clear_vinsn (vinsn
);
5904 /* First, find a format that works. */
5905 if (vinsn
->format
== XTENSA_UNDEFINED
)
5906 vinsn
->format
= xg_find_narrowest_format (vinsn
);
5908 if (vinsn
->format
== XTENSA_UNDEFINED
)
5910 as_where (&file_name
, &line
);
5911 as_bad_where (file_name
, line
,
5912 _("couldn't find a valid instruction format"));
5913 fprintf (stderr
, _(" ops were: "));
5914 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5915 fprintf (stderr
, _(" %s;"),
5916 xtensa_opcode_name (xtensa_default_isa
,
5917 vinsn
->slots
[i
].opcode
));
5918 fprintf (stderr
, _("\n"));
5919 xg_clear_vinsn (vinsn
);
5923 if (vinsn
->num_slots
5924 != xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
))
5926 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
5927 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
5928 xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
),
5930 xg_clear_vinsn (vinsn
);
5934 if (resources_conflict (vinsn
))
5936 as_where (&file_name
, &line
);
5937 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
5938 fprintf (stderr
, " ops were: ");
5939 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5940 fprintf (stderr
, " %s;",
5941 xtensa_opcode_name (xtensa_default_isa
,
5942 vinsn
->slots
[i
].opcode
));
5943 fprintf (stderr
, "\n");
5944 xg_clear_vinsn (vinsn
);
5948 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5950 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
5952 symbolS
*lit_sym
= NULL
;
5954 bfd_boolean e
= FALSE
;
5955 bfd_boolean saved_density
= density_supported
;
5957 /* We don't want to narrow ops inside multi-slot bundles. */
5958 if (vinsn
->num_slots
> 1)
5959 density_supported
= FALSE
;
5961 istack_init (&slotstack
);
5962 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
5964 vinsn
->slots
[i
].opcode
=
5965 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
5967 vinsn
->slots
[i
].ntok
= 0;
5970 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
5976 density_supported
= saved_density
;
5980 xg_clear_vinsn (vinsn
);
5984 for (j
= 0; j
< slotstack
.ninsn
; j
++)
5986 TInsn
*insn
= &slotstack
.insn
[j
];
5987 if (insn
->insn_type
== ITYPE_LITERAL
)
5989 assert (lit_sym
== NULL
);
5990 lit_sym
= xg_assemble_literal (insn
);
5994 assert (insn
->insn_type
== ITYPE_INSN
);
5996 xg_resolve_literals (insn
, lit_sym
);
5997 if (j
!= slotstack
.ninsn
- 1)
5998 emit_single_op (insn
);
6002 if (vinsn
->num_slots
> 1)
6004 if (opcode_fits_format_slot
6005 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6008 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6012 emit_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6013 if (vinsn
->format
== XTENSA_UNDEFINED
)
6014 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6016 vinsn
->slots
[i
].opcode
6017 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6020 vinsn
->slots
[i
].ntok
= 0;
6025 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6026 vinsn
->format
= XTENSA_UNDEFINED
;
6031 /* Now check resource conflicts on the modified bundle. */
6032 if (resources_conflict (vinsn
))
6034 as_where (&file_name
, &line
);
6035 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6036 fprintf (stderr
, " ops were: ");
6037 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6038 fprintf (stderr
, " %s;",
6039 xtensa_opcode_name (xtensa_default_isa
,
6040 vinsn
->slots
[i
].opcode
));
6041 fprintf (stderr
, "\n");
6042 xg_clear_vinsn (vinsn
);
6046 /* First, find a format that works. */
6047 if (vinsn
->format
== XTENSA_UNDEFINED
)
6048 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6050 xg_assemble_vliw_tokens (vinsn
);
6052 xg_clear_vinsn (vinsn
);
6056 /* Given an vliw instruction, what conflicts are there in register
6057 usage and in writes to states and queues?
6059 This function does two things:
6060 1. Reports an error when a vinsn contains illegal combinations
6061 of writes to registers states or queues.
6062 2. Marks individual tinsns as not relaxable if the combination
6063 contains antidependencies.
6065 Job 2 handles things like swap semantics in instructions that need
6066 to be relaxed. For example,
6070 normally would be relaxed to
6075 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6077 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6079 then we can't relax it into
6082 { add a0, a1, a0 ; add a2, a0, a4 ; }
6084 because the value of a0 is trashed before the second add can read it. */
6086 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6089 find_vinsn_conflicts (vliw_insn
*vinsn
)
6093 xtensa_isa isa
= xtensa_default_isa
;
6095 assert (!past_xtensa_end
);
6097 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6099 TInsn
*op1
= &vinsn
->slots
[i
];
6100 if (op1
->is_specific_opcode
)
6101 op1
->keep_wide
= TRUE
;
6103 op1
->keep_wide
= FALSE
;
6106 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6108 TInsn
*op1
= &vinsn
->slots
[i
];
6110 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6113 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6117 TInsn
*op2
= &vinsn
->slots
[j
];
6118 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6119 switch (conflict_type
)
6122 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6123 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6124 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6127 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6128 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6129 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6132 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"),
6133 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6134 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6137 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"),
6138 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6139 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6142 /* Everything is OK. */
6145 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6146 || conflict_type
== 'a');
6153 as_bad (_("multiple branches or jumps in the same bundle"));
6161 /* Check how the state used by t1 and t2 relate.
6164 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6165 case B: no relationship between what is read and written (both could
6166 read the same reg though)
6167 case C: t1 writes a register t2 writes (a register conflict within a
6169 case D: t1 writes a state that t2 also writes
6170 case E: t1 writes a tie queue that t2 also writes
6171 case F: two volatile queue accesses
6175 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6177 xtensa_isa isa
= xtensa_default_isa
;
6178 xtensa_regfile t1_regfile
, t2_regfile
;
6180 int t1_base_reg
, t1_last_reg
;
6181 int t2_base_reg
, t2_last_reg
;
6182 char t1_inout
, t2_inout
;
6184 char conflict
= 'b';
6189 bfd_boolean t1_volatile
= FALSE
;
6190 bfd_boolean t2_volatile
= FALSE
;
6192 /* Check registers. */
6193 for (j
= 0; j
< t2
->ntok
; j
++)
6195 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6198 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6199 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6200 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6202 for (i
= 0; i
< t1
->ntok
; i
++)
6204 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6207 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6209 if (t1_regfile
!= t2_regfile
)
6212 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6213 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6215 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6216 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6218 if (t1_inout
== 'm' || t1_inout
== 'o'
6219 || t2_inout
== 'm' || t2_inout
== 'o')
6226 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6227 t1_last_reg
= (t1_base_reg
6228 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6230 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6232 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6234 if (t1_reg
!= t2_reg
)
6237 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6243 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6249 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6257 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6258 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6259 for (j
= 0; j
< t2_states
; j
++)
6261 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6262 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6263 for (i
= 0; i
< t1_states
; i
++)
6265 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6266 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6270 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6276 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6282 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6287 /* Check tieports. */
6288 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6289 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6290 for (j
= 0; j
< t2_interfaces
; j
++)
6292 xtensa_interface t2_int
6293 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6294 int t2_class
= xtensa_interface_class_id (isa
, t2_int
);
6296 t2_inout
= xtensa_interface_inout (isa
, t2_int
);
6297 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1)
6300 for (i
= 0; i
< t1_interfaces
; i
++)
6302 xtensa_interface t1_int
6303 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6304 int t1_class
= xtensa_interface_class_id (isa
, t1_int
);
6306 t1_inout
= xtensa_interface_inout (isa
, t1_int
);
6307 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1)
6310 if (t1_volatile
&& t2_volatile
&& (t1_class
== t2_class
))
6313 if (t1_int
!= t2_int
)
6316 if (t2_inout
== 'i' && t1_inout
== 'o')
6322 if (t1_inout
== 'i' && t2_inout
== 'o')
6328 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6337 static xtensa_format
6338 xg_find_narrowest_format (vliw_insn
*vinsn
)
6340 /* Right now we assume that the ops within the vinsn are properly
6341 ordered for the slots that the programmer wanted them in. In
6342 other words, we don't rearrange the ops in hopes of finding a
6343 better format. The scheduler handles that. */
6345 xtensa_isa isa
= xtensa_default_isa
;
6346 xtensa_format format
;
6347 vliw_insn v_copy
= *vinsn
;
6348 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6350 if (vinsn
->num_slots
== 1)
6351 return xg_get_single_format (vinsn
->slots
[0].opcode
);
6353 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6356 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6360 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6362 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6364 v_copy
.slots
[slot
].opcode
=
6365 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6366 v_copy
.slots
[slot
].ntok
= 0;
6369 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6372 else if (v_copy
.num_slots
> 1)
6375 /* Try the widened version. */
6376 if (!v_copy
.slots
[slot
].keep_wide
6377 && !v_copy
.slots
[slot
].is_specific_opcode
6378 && xg_is_single_relaxable_insn (&v_copy
.slots
[slot
],
6380 && opcode_fits_format_slot (widened
.opcode
,
6383 v_copy
.slots
[slot
] = widened
;
6388 if (fit
== v_copy
.num_slots
)
6391 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6392 vinsn
->format
= format
;
6398 if (format
== xtensa_isa_num_formats (isa
))
6399 return XTENSA_UNDEFINED
;
6405 /* Return the additional space needed in a frag
6406 for possible relaxations of any ops in a VLIW insn.
6407 Also fill out the relaxations that might be required of
6408 each tinsn in the vinsn. */
6411 relaxation_requirements (vliw_insn
*vinsn
, bfd_boolean
*pfinish_frag
)
6413 bfd_boolean finish_frag
= FALSE
;
6414 int extra_space
= 0;
6417 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6419 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6420 if (!tinsn_has_symbolic_operands (tinsn
))
6422 /* A narrow instruction could be widened later to help
6423 alignment issues. */
6424 if (xg_is_single_relaxable_insn (tinsn
, 0, TRUE
)
6425 && !tinsn
->is_specific_opcode
6426 && vinsn
->num_slots
== 1)
6428 /* Difference in bytes between narrow and wide insns... */
6430 tinsn
->subtype
= RELAX_NARROW
;
6435 if (workaround_b_j_loop_end
6436 && tinsn
->opcode
== xtensa_jx_opcode
6437 && use_transform ())
6439 /* Add 2 of these. */
6440 extra_space
+= 3; /* for the nop size */
6441 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6444 /* Need to assemble it with space for the relocation. */
6445 if (xg_is_relaxable_insn (tinsn
, 0)
6446 && !tinsn
->is_specific_opcode
)
6448 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6449 int max_literal_size
=
6450 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6452 tinsn
->literal_space
= max_literal_size
;
6454 tinsn
->subtype
= RELAX_IMMED
;
6455 extra_space
+= max_size
;
6459 /* A fix record will be added for this instruction prior
6460 to relaxation, so make it end the frag. */
6465 *pfinish_frag
= finish_frag
;
6471 bundle_tinsn (TInsn
*tinsn
, vliw_insn
*vinsn
)
6473 xtensa_isa isa
= xtensa_default_isa
;
6474 int slot
, chosen_slot
;
6476 vinsn
->format
= xg_get_single_format (tinsn
->opcode
);
6477 assert (vinsn
->format
!= XTENSA_UNDEFINED
);
6478 vinsn
->num_slots
= xtensa_format_num_slots (isa
, vinsn
->format
);
6480 chosen_slot
= xg_get_single_slot (tinsn
->opcode
);
6481 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6483 if (slot
== chosen_slot
)
6484 vinsn
->slots
[slot
] = *tinsn
;
6487 vinsn
->slots
[slot
].opcode
=
6488 xtensa_format_slot_nop_opcode (isa
, vinsn
->format
, slot
);
6489 vinsn
->slots
[slot
].ntok
= 0;
6490 vinsn
->slots
[slot
].insn_type
= ITYPE_INSN
;
6497 emit_single_op (TInsn
*orig_insn
)
6500 IStack istack
; /* put instructions into here */
6501 symbolS
*lit_sym
= NULL
;
6502 symbolS
*label_sym
= NULL
;
6504 istack_init (&istack
);
6506 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6507 Because the scheduling and bundling characteristics of movi and
6508 l32r or const16 are so different, we can do much better if we relax
6509 it prior to scheduling and bundling, rather than after. */
6510 if ((orig_insn
->opcode
== xtensa_movi_opcode
6511 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
6512 && !cur_vinsn
.inside_bundle
6513 && (orig_insn
->tok
[1].X_op
== O_symbol
6514 || orig_insn
->tok
[1].X_op
== O_pltrel
)
6515 && !orig_insn
->is_specific_opcode
&& use_transform ())
6516 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
6518 if (xg_expand_assembly_insn (&istack
, orig_insn
))
6521 for (i
= 0; i
< istack
.ninsn
; i
++)
6523 TInsn
*insn
= &istack
.insn
[i
];
6524 switch (insn
->insn_type
)
6527 assert (lit_sym
== NULL
);
6528 lit_sym
= xg_assemble_literal (insn
);
6532 static int relaxed_sym_idx
= 0;
6533 char *label
= xmalloc (strlen (FAKE_LABEL_NAME
) + 12);
6534 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
6536 assert (label_sym
== NULL
);
6537 label_sym
= symbol_find_or_make (label
);
6546 xg_resolve_literals (insn
, lit_sym
);
6548 xg_resolve_labels (insn
, label_sym
);
6550 bundle_tinsn (insn
, &v
);
6565 total_frag_text_expansion (fragS
*fragP
)
6568 int total_expansion
= 0;
6570 for (slot
= 0; slot
< MAX_SLOTS
; slot
++)
6571 total_expansion
+= fragP
->tc_frag_data
.text_expansion
[slot
];
6573 return total_expansion
;
6577 /* Emit a vliw instruction to the current fragment. */
6580 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
6582 bfd_boolean finish_frag
;
6583 bfd_boolean is_jump
= FALSE
;
6584 bfd_boolean is_branch
= FALSE
;
6585 xtensa_isa isa
= xtensa_default_isa
;
6591 unsigned current_line
, best_linenum
;
6594 best_linenum
= UINT_MAX
;
6596 if (generating_literals
)
6598 static int reported
= 0;
6600 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
6601 _("cannot assemble into a literal fragment"));
6608 if (frag_now_fix () != 0
6609 && (! frag_now
->tc_frag_data
.is_insn
6610 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6611 || !use_transform () != frag_now
->tc_frag_data
.is_no_transform
6612 || (directive_state
[directive_longcalls
]
6613 != frag_now
->tc_frag_data
.use_longcalls
)
6614 || (directive_state
[directive_absolute_literals
]
6615 != frag_now
->tc_frag_data
.use_absolute_literals
)))
6617 frag_wane (frag_now
);
6619 xtensa_set_frag_assembly_state (frag_now
);
6622 if (workaround_a0_b_retw
6623 && vinsn
->num_slots
== 1
6624 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
6625 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
6626 && use_transform ())
6628 has_a0_b_retw
= TRUE
;
6630 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
6631 After the first assembly pass we will check all of them and
6632 add a nop if needed. */
6633 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6634 frag_var (rs_machine_dependent
, 4, 4,
6635 RELAX_ADD_NOP_IF_A0_B_RETW
,
6636 frag_now
->fr_symbol
,
6637 frag_now
->fr_offset
,
6639 xtensa_set_frag_assembly_state (frag_now
);
6640 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6641 frag_var (rs_machine_dependent
, 4, 4,
6642 RELAX_ADD_NOP_IF_A0_B_RETW
,
6643 frag_now
->fr_symbol
,
6644 frag_now
->fr_offset
,
6646 xtensa_set_frag_assembly_state (frag_now
);
6649 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6651 /* See if the instruction implies an aligned section. */
6652 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[i
].opcode
) == 1)
6653 record_alignment (now_seg
, 2);
6655 /* Also determine the best line number for debug info. */
6656 best_linenum
= vinsn
->slots
[i
].linenum
< best_linenum
6657 ? vinsn
->slots
[i
].linenum
: best_linenum
;
6660 /* Special cases for instructions that force an alignment... */
6661 /* None of these opcodes are bundle-able. */
6662 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
6666 /* Remember the symbol that marks the end of the loop in the frag
6667 that marks the start of the loop. This way we can easily find
6668 the end of the loop at the beginning, without adding special code
6669 to mark the loop instructions themselves. */
6670 symbolS
*target_sym
= NULL
;
6671 if (vinsn
->slots
[0].tok
[1].X_op
== O_symbol
)
6672 target_sym
= vinsn
->slots
[0].tok
[1].X_add_symbol
;
6674 xtensa_set_frag_assembly_state (frag_now
);
6675 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6677 max_fill
= get_text_align_max_fill_size
6678 (get_text_align_power (xtensa_fetch_width
),
6679 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
6681 if (use_transform ())
6682 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
6683 RELAX_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
6685 frag_var (rs_machine_dependent
, 0, 0,
6686 RELAX_CHECK_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
6687 xtensa_set_frag_assembly_state (frag_now
);
6689 xtensa_move_labels (frag_now
, 0, FALSE
);
6692 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
6693 && !vinsn
->slots
[0].is_specific_opcode
)
6695 xtensa_mark_literal_pool_location ();
6696 xtensa_move_labels (frag_now
, 0, TRUE
);
6697 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
6700 if (vinsn
->num_slots
== 1)
6702 if (workaround_a0_b_retw
&& use_transform ())
6703 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
6704 is_register_writer (&vinsn
->slots
[0], "a", 0));
6706 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
6707 is_bad_loopend_opcode (&vinsn
->slots
[0]));
6710 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
6712 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
6714 extra_space
= relaxation_requirements (vinsn
, &finish_frag
);
6716 /* vinsn_to_insnbuf will produce the error. */
6717 if (vinsn
->format
!= XTENSA_UNDEFINED
)
6719 f
= frag_more (insn_size
+ extra_space
);
6720 xtensa_set_frag_assembly_state (frag_now
);
6721 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6724 vinsn_to_insnbuf (vinsn
, f
, frag_now
, FALSE
);
6725 if (vinsn
->format
== XTENSA_UNDEFINED
)
6728 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, (unsigned char *) f
, 0);
6730 /* Temporarily set the logical line number to the one we want to appear
6731 in the debug information. */
6732 as_where (¤t_file
, ¤t_line
);
6733 new_logical_line (current_file
, best_linenum
);
6734 dwarf2_emit_insn (insn_size
+ extra_space
);
6735 new_logical_line (current_file
, current_line
);
6737 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6739 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6740 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
6741 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
6742 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
6743 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
6744 if (tinsn
->literal_space
!= 0)
6745 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
6747 if (tinsn
->subtype
== RELAX_NARROW
)
6748 assert (vinsn
->num_slots
== 1);
6749 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
6751 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
6754 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->offset
6755 || tinsn
->literal_frag
|| is_jump
|| is_branch
)
6759 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6760 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
6764 frag_variant (rs_machine_dependent
,
6765 extra_space
, extra_space
, RELAX_SLOTS
,
6766 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
6767 xtensa_set_frag_assembly_state (frag_now
);
6770 /* Special cases for loops:
6771 close_loop_end should be inserted AFTER short_loop.
6772 Make sure that CLOSE loops are processed BEFORE short_loops
6773 when converting them. */
6775 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
6776 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1
6777 && !vinsn
->slots
[0].is_specific_opcode
)
6779 if (workaround_short_loop
&& use_transform ())
6781 maybe_has_short_loop
= TRUE
;
6782 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6783 frag_var (rs_machine_dependent
, 4, 4,
6784 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6785 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6786 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6787 frag_var (rs_machine_dependent
, 4, 4,
6788 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6789 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6792 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
6793 loop at least 12 bytes away from another loop's end. */
6794 if (workaround_close_loop_end
&& use_transform ())
6796 maybe_has_close_loop_end
= TRUE
;
6797 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6798 frag_var (rs_machine_dependent
, 12, 12,
6799 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
6800 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6804 if (use_transform ())
6808 assert (finish_frag
);
6809 frag_var (rs_machine_dependent
,
6810 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6812 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6813 xtensa_set_frag_assembly_state (frag_now
);
6815 else if (is_branch
&& do_align_targets ())
6817 assert (finish_frag
);
6818 frag_var (rs_machine_dependent
,
6819 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6820 RELAX_MAYBE_UNREACHABLE
,
6821 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6822 xtensa_set_frag_assembly_state (frag_now
);
6823 frag_var (rs_machine_dependent
,
6825 RELAX_MAYBE_DESIRE_ALIGN
,
6826 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6827 xtensa_set_frag_assembly_state (frag_now
);
6831 /* Now, if the original opcode was a call... */
6832 if (do_align_targets ()
6833 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
6835 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
6836 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6837 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
6838 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6839 xtensa_set_frag_assembly_state (frag_now
);
6842 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6844 frag_wane (frag_now
);
6846 xtensa_set_frag_assembly_state (frag_now
);
6851 /* xtensa_end and helper functions. */
6853 static void xtensa_cleanup_align_frags (void);
6854 static void xtensa_fix_target_frags (void);
6855 static void xtensa_mark_narrow_branches (void);
6856 static void xtensa_mark_zcl_first_insns (void);
6857 static void xtensa_fix_a0_b_retw_frags (void);
6858 static void xtensa_fix_b_j_loop_end_frags (void);
6859 static void xtensa_fix_close_loop_end_frags (void);
6860 static void xtensa_fix_short_loop_frags (void);
6861 static void xtensa_sanity_check (void);
6866 directive_balance ();
6867 xtensa_flush_pending_output ();
6869 past_xtensa_end
= TRUE
;
6871 xtensa_move_literals ();
6873 xtensa_reorder_segments ();
6874 xtensa_cleanup_align_frags ();
6875 xtensa_fix_target_frags ();
6876 if (workaround_a0_b_retw
&& has_a0_b_retw
)
6877 xtensa_fix_a0_b_retw_frags ();
6878 if (workaround_b_j_loop_end
)
6879 xtensa_fix_b_j_loop_end_frags ();
6881 /* "close_loop_end" should be processed BEFORE "short_loop". */
6882 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
6883 xtensa_fix_close_loop_end_frags ();
6885 if (workaround_short_loop
&& maybe_has_short_loop
)
6886 xtensa_fix_short_loop_frags ();
6888 xtensa_mark_narrow_branches ();
6889 xtensa_mark_zcl_first_insns ();
6891 xtensa_sanity_check ();
6896 xtensa_cleanup_align_frags (void)
6901 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
6902 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
6905 /* Walk over all of the fragments in a subsection. */
6906 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
6908 if ((fragP
->fr_type
== rs_align
6909 || fragP
->fr_type
== rs_align_code
6910 || (fragP
->fr_type
== rs_machine_dependent
6911 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
6912 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
6913 && fragP
->fr_fix
== 0)
6915 fragS
*next
= fragP
->fr_next
;
6918 && next
->fr_fix
== 0
6919 && next
->fr_type
== rs_machine_dependent
6920 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
6923 next
= next
->fr_next
;
6926 /* If we don't widen branch targets, then they
6927 will be easier to align. */
6928 if (fragP
->tc_frag_data
.is_branch_target
6929 && fragP
->fr_opcode
== fragP
->fr_literal
6930 && fragP
->fr_type
== rs_machine_dependent
6931 && fragP
->fr_subtype
== RELAX_SLOTS
6932 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
6934 if (fragP
->fr_type
== rs_machine_dependent
6935 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
6936 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
6942 /* Re-process all of the fragments looking to convert all of the
6943 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
6944 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
6945 Otherwise, convert to a .fill 0. */
6948 xtensa_fix_target_frags (void)
6953 /* When this routine is called, all of the subsections are still intact
6954 so we walk over subsections instead of sections. */
6955 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
6956 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
6960 /* Walk over all of the fragments in a subsection. */
6961 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
6963 if (fragP
->fr_type
== rs_machine_dependent
6964 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
6966 if (next_frag_is_branch_target (fragP
))
6967 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
6976 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
6979 xtensa_mark_narrow_branches (void)
6984 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
6985 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
6988 /* Walk over all of the fragments in a subsection. */
6989 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
6991 if (fragP
->fr_type
== rs_machine_dependent
6992 && fragP
->fr_subtype
== RELAX_SLOTS
6993 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
6997 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
6998 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
7000 if (vinsn
.num_slots
== 1
7001 && xtensa_opcode_is_branch (xtensa_default_isa
,
7002 vinsn
.slots
[0].opcode
) == 1
7003 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
7004 && is_narrow_branch_guaranteed_in_range (fragP
,
7007 fragP
->fr_subtype
= RELAX_SLOTS
;
7008 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
7009 fragP
->tc_frag_data
.is_aligning_branch
= 1;
7017 /* A branch is typically widened only when its target is out of
7018 range. However, we would like to widen them to align a subsequent
7019 branch target when possible.
7021 Because the branch relaxation code is so convoluted, the optimal solution
7022 (combining the two cases) is difficult to get right in all circumstances.
7023 We therefore go with an "almost as good" solution, where we only
7024 use for alignment narrow branches that definitely will not expand to a
7025 jump and a branch. These functions find and mark these cases. */
7027 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
7028 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7029 We start counting beginning with the frag after the 2-byte branch, so the
7030 maximum offset is (4 - 2) + 63 = 65. */
7031 #define MAX_IMMED6 65
7033 static offsetT
unrelaxed_frag_max_size (fragS
*);
7036 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
7038 const expressionS
*expr
= &tinsn
->tok
[1];
7039 symbolS
*symbolP
= expr
->X_add_symbol
;
7040 offsetT max_distance
= expr
->X_add_number
;
7043 if (expr
->X_op
!= O_symbol
)
7046 target_frag
= symbol_get_frag (symbolP
);
7048 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
7049 if (is_branch_jmp_to_next (tinsn
, fragP
))
7052 /* The branch doesn't branch over it's own frag,
7053 but over the subsequent ones. */
7054 fragP
= fragP
->fr_next
;
7055 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
7057 max_distance
+= unrelaxed_frag_max_size (fragP
);
7058 fragP
= fragP
->fr_next
;
7060 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
7067 xtensa_mark_zcl_first_insns (void)
7072 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7073 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7076 /* Walk over all of the fragments in a subsection. */
7077 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7079 if (fragP
->fr_type
== rs_machine_dependent
7080 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7081 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7083 /* Find the loop frag. */
7084 fragS
*targ_frag
= next_non_empty_frag (fragP
);
7085 /* Find the first insn frag. */
7086 targ_frag
= next_non_empty_frag (targ_frag
);
7088 /* Of course, sometimes (mostly for toy test cases) a
7089 zero-cost loop instruction is the last in a section. */
7092 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
7093 /* Do not widen a frag that is the first instruction of a
7094 zero-cost loop. It makes that loop harder to align. */
7095 if (targ_frag
->fr_type
== rs_machine_dependent
7096 && targ_frag
->fr_subtype
== RELAX_SLOTS
7097 && (targ_frag
->tc_frag_data
.slot_subtypes
[0]
7100 if (targ_frag
->tc_frag_data
.is_aligning_branch
)
7101 targ_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
7104 frag_wane (targ_frag
);
7105 targ_frag
->tc_frag_data
.slot_subtypes
[0] = 0;
7109 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
7117 /* Re-process all of the fragments looking to convert all of the
7118 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7119 conditional branch or a retw/retw.n, convert this frag to one that
7120 will generate a NOP. In any case close it off with a .fill 0. */
7122 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
7125 xtensa_fix_a0_b_retw_frags (void)
7130 /* When this routine is called, all of the subsections are still intact
7131 so we walk over subsections instead of sections. */
7132 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7133 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7137 /* Walk over all of the fragments in a subsection. */
7138 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7140 if (fragP
->fr_type
== rs_machine_dependent
7141 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
7143 if (next_instrs_are_b_retw (fragP
))
7145 if (fragP
->tc_frag_data
.is_no_transform
)
7146 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7148 relax_frag_add_nop (fragP
);
7158 next_instrs_are_b_retw (fragS
*fragP
)
7160 xtensa_opcode opcode
;
7162 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
7163 static xtensa_insnbuf insnbuf
= NULL
;
7164 static xtensa_insnbuf slotbuf
= NULL
;
7165 xtensa_isa isa
= xtensa_default_isa
;
7168 bfd_boolean branch_seen
= FALSE
;
7172 insnbuf
= xtensa_insnbuf_alloc (isa
);
7173 slotbuf
= xtensa_insnbuf_alloc (isa
);
7176 if (next_fragP
== NULL
)
7179 /* Check for the conditional branch. */
7180 xtensa_insnbuf_from_chars
7181 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7182 fmt
= xtensa_format_decode (isa
, insnbuf
);
7183 if (fmt
== XTENSA_UNDEFINED
)
7186 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7188 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
7189 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
7191 branch_seen
= (branch_seen
7192 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
7198 offset
+= xtensa_format_length (isa
, fmt
);
7199 if (offset
== next_fragP
->fr_fix
)
7201 next_fragP
= next_non_empty_frag (next_fragP
);
7205 if (next_fragP
== NULL
)
7208 /* Check for the retw/retw.n. */
7209 xtensa_insnbuf_from_chars
7210 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7211 fmt
= xtensa_format_decode (isa
, insnbuf
);
7213 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
7214 have no problems. */
7215 if (fmt
== XTENSA_UNDEFINED
7216 || xtensa_format_num_slots (isa
, fmt
) != 1)
7219 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
7220 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
7222 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
7229 /* Re-process all of the fragments looking to convert all of the
7230 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
7231 loop end label, convert this frag to one that will generate a NOP.
7232 In any case close it off with a .fill 0. */
7234 static bfd_boolean
next_instr_is_loop_end (fragS
*);
7237 xtensa_fix_b_j_loop_end_frags (void)
7242 /* When this routine is called, all of the subsections are still intact
7243 so we walk over subsections instead of sections. */
7244 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7245 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7249 /* Walk over all of the fragments in a subsection. */
7250 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7252 if (fragP
->fr_type
== rs_machine_dependent
7253 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
7255 if (next_instr_is_loop_end (fragP
))
7257 if (fragP
->tc_frag_data
.is_no_transform
)
7258 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
7260 relax_frag_add_nop (fragP
);
7270 next_instr_is_loop_end (fragS
*fragP
)
7272 const fragS
*next_fragP
;
7274 if (next_frag_is_loop_target (fragP
))
7277 next_fragP
= next_non_empty_frag (fragP
);
7278 if (next_fragP
== NULL
)
7281 if (!next_frag_is_loop_target (next_fragP
))
7284 /* If the size is >= 3 then there is more than one instruction here.
7285 The hardware bug will not fire. */
7286 if (next_fragP
->fr_fix
> 3)
7293 /* Re-process all of the fragments looking to convert all of the
7294 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
7295 not MY loop's loop end within 12 bytes, add enough nops here to
7296 make it at least 12 bytes away. In any case close it off with a
7299 static offsetT min_bytes_to_other_loop_end
7300 (fragS
*, fragS
*, offsetT
);
7303 xtensa_fix_close_loop_end_frags (void)
7308 /* When this routine is called, all of the subsections are still intact
7309 so we walk over subsections instead of sections. */
7310 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7311 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7315 fragS
*current_target
= NULL
;
7317 /* Walk over all of the fragments in a subsection. */
7318 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7320 if (fragP
->fr_type
== rs_machine_dependent
7321 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7322 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7323 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7326 && fragP
->fr_type
== rs_machine_dependent
7327 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
7330 int bytes_added
= 0;
7332 #define REQUIRED_LOOP_DIVIDING_BYTES 12
7333 /* Max out at 12. */
7334 min_bytes
= min_bytes_to_other_loop_end
7335 (fragP
->fr_next
, current_target
, REQUIRED_LOOP_DIVIDING_BYTES
);
7337 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
7339 if (fragP
->tc_frag_data
.is_no_transform
)
7340 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
7343 while (min_bytes
+ bytes_added
7344 < REQUIRED_LOOP_DIVIDING_BYTES
)
7348 if (fragP
->fr_var
< length
)
7349 as_fatal (_("fr_var %lu < length %d"),
7350 (long) fragP
->fr_var
, length
);
7353 assemble_nop (length
,
7354 fragP
->fr_literal
+ fragP
->fr_fix
);
7355 fragP
->fr_fix
+= length
;
7356 fragP
->fr_var
-= length
;
7358 bytes_added
+= length
;
7364 assert (fragP
->fr_type
!= rs_machine_dependent
7365 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
7371 static offsetT
unrelaxed_frag_min_size (fragS
*);
7374 min_bytes_to_other_loop_end (fragS
*fragP
,
7375 fragS
*current_target
,
7379 fragS
*current_fragP
;
7381 for (current_fragP
= fragP
;
7383 current_fragP
= current_fragP
->fr_next
)
7385 if (current_fragP
->tc_frag_data
.is_loop_target
7386 && current_fragP
!= current_target
)
7389 offset
+= unrelaxed_frag_min_size (current_fragP
);
7391 if (offset
>= max_size
)
7399 unrelaxed_frag_min_size (fragS
*fragP
)
7401 offsetT size
= fragP
->fr_fix
;
7403 /* Add fill size. */
7404 if (fragP
->fr_type
== rs_fill
)
7405 size
+= fragP
->fr_offset
;
7412 unrelaxed_frag_max_size (fragS
*fragP
)
7414 offsetT size
= fragP
->fr_fix
;
7415 switch (fragP
->fr_type
)
7418 /* Empty frags created by the obstack allocation scheme
7419 end up with type 0. */
7424 size
+= fragP
->fr_offset
;
7432 /* No further adjustments needed. */
7434 case rs_machine_dependent
:
7435 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
7436 size
+= fragP
->fr_var
;
7439 /* We had darn well better know how big it is. */
7448 /* Re-process all of the fragments looking to convert all
7449 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
7452 1) the instruction size count to the loop end label
7453 is too short (<= 2 instructions),
7454 2) loop has a jump or branch in it
7457 1) workaround_all_short_loops is TRUE
7458 2) The generating loop was a 'loopgtz' or 'loopnez'
7459 3) the instruction size count to the loop end label is too short
7461 then convert this frag (and maybe the next one) to generate a NOP.
7462 In any case close it off with a .fill 0. */
7464 static int count_insns_to_loop_end (fragS
*, bfd_boolean
, int);
7465 static bfd_boolean
branch_before_loop_end (fragS
*);
7468 xtensa_fix_short_loop_frags (void)
7473 /* When this routine is called, all of the subsections are still intact
7474 so we walk over subsections instead of sections. */
7475 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7476 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7479 fragS
*current_target
= NULL
;
7480 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
7482 /* Walk over all of the fragments in a subsection. */
7483 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7485 if (fragP
->fr_type
== rs_machine_dependent
7486 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7487 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7490 fragS
*loop_frag
= next_non_empty_frag (fragP
);
7491 tinsn_from_chars (&t_insn
, loop_frag
->fr_opcode
, 0);
7492 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7493 current_opcode
= t_insn
.opcode
;
7494 assert (xtensa_opcode_is_loop (xtensa_default_isa
,
7495 current_opcode
) == 1);
7498 if (fragP
->fr_type
== rs_machine_dependent
7499 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7501 if (count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3) < 3
7502 && (branch_before_loop_end (fragP
->fr_next
)
7503 || (workaround_all_short_loops
7504 && current_opcode
!= XTENSA_UNDEFINED
7505 && current_opcode
!= xtensa_loop_opcode
)))
7507 if (fragP
->tc_frag_data
.is_no_transform
)
7508 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
7510 relax_frag_add_nop (fragP
);
7519 static int unrelaxed_frag_min_insn_count (fragS
*);
7522 count_insns_to_loop_end (fragS
*base_fragP
,
7523 bfd_boolean count_relax_add
,
7526 fragS
*fragP
= NULL
;
7531 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
7533 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
7534 if (insn_count
>= max_count
)
7537 if (count_relax_add
)
7539 if (fragP
->fr_type
== rs_machine_dependent
7540 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7542 /* In order to add the appropriate number of
7543 NOPs, we count an instruction for downstream
7546 if (insn_count
>= max_count
)
7556 unrelaxed_frag_min_insn_count (fragS
*fragP
)
7558 xtensa_isa isa
= xtensa_default_isa
;
7559 static xtensa_insnbuf insnbuf
= NULL
;
7563 if (!fragP
->tc_frag_data
.is_insn
)
7567 insnbuf
= xtensa_insnbuf_alloc (isa
);
7569 /* Decode the fixed instructions. */
7570 while (offset
< fragP
->fr_fix
)
7574 xtensa_insnbuf_from_chars
7575 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7576 fmt
= xtensa_format_decode (isa
, insnbuf
);
7578 if (fmt
== XTENSA_UNDEFINED
)
7580 as_fatal (_("undecodable instruction in instruction frag"));
7583 offset
+= xtensa_format_length (isa
, fmt
);
7591 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
7594 branch_before_loop_end (fragS
*base_fragP
)
7598 for (fragP
= base_fragP
;
7599 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
7600 fragP
= fragP
->fr_next
)
7602 if (unrelaxed_frag_has_b_j (fragP
))
7610 unrelaxed_frag_has_b_j (fragS
*fragP
)
7612 static xtensa_insnbuf insnbuf
= NULL
;
7613 xtensa_isa isa
= xtensa_default_isa
;
7616 if (!fragP
->tc_frag_data
.is_insn
)
7620 insnbuf
= xtensa_insnbuf_alloc (isa
);
7622 /* Decode the fixed instructions. */
7623 while (offset
< fragP
->fr_fix
)
7628 xtensa_insnbuf_from_chars
7629 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7630 fmt
= xtensa_format_decode (isa
, insnbuf
);
7631 if (fmt
== XTENSA_UNDEFINED
)
7634 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7636 xtensa_opcode opcode
=
7637 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
7638 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
7639 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
7642 offset
+= xtensa_format_length (isa
, fmt
);
7648 /* Checks to be made after initial assembly but before relaxation. */
7650 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
7651 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
7654 xtensa_sanity_check (void)
7661 as_where (&file_name
, &line
);
7662 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7663 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7667 /* Walk over all of the fragments in a subsection. */
7668 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7670 /* Currently we only check for empty loops here. */
7671 if (fragP
->fr_type
== rs_machine_dependent
7672 && fragP
->fr_subtype
== RELAX_IMMED
)
7674 static xtensa_insnbuf insnbuf
= NULL
;
7677 if (fragP
->fr_opcode
!= NULL
)
7680 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7681 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7682 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
7684 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7685 t_insn
.opcode
) == 1)
7687 if (is_empty_loop (&t_insn
, fragP
))
7689 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7690 as_bad (_("invalid empty loop"));
7692 if (!is_local_forward_loop (&t_insn
, fragP
))
7694 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7695 as_bad (_("loop target does not follow "
7696 "loop instruction in section"));
7703 new_logical_line (file_name
, line
);
7707 #define LOOP_IMMED_OPN 1
7709 /* Return TRUE if the loop target is the next non-zero fragment. */
7712 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
7714 const expressionS
*expr
;
7718 if (insn
->insn_type
!= ITYPE_INSN
)
7721 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
7724 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7727 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7729 if (expr
->X_op
!= O_symbol
)
7732 symbolP
= expr
->X_add_symbol
;
7736 if (symbol_get_frag (symbolP
) == NULL
)
7739 if (S_GET_VALUE (symbolP
) != 0)
7742 /* Walk through the zero-size fragments from this one. If we find
7743 the target fragment, then this is a zero-size loop. */
7745 for (next_fragP
= fragP
->fr_next
;
7747 next_fragP
= next_fragP
->fr_next
)
7749 if (next_fragP
== symbol_get_frag (symbolP
))
7751 if (next_fragP
->fr_fix
!= 0)
7759 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
7761 const expressionS
*expr
;
7765 if (insn
->insn_type
!= ITYPE_INSN
)
7768 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
7771 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7774 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7776 if (expr
->X_op
!= O_symbol
)
7779 symbolP
= expr
->X_add_symbol
;
7783 if (symbol_get_frag (symbolP
) == NULL
)
7786 /* Walk through fragments until we find the target.
7787 If we do not find the target, then this is an invalid loop. */
7789 for (next_fragP
= fragP
->fr_next
;
7791 next_fragP
= next_fragP
->fr_next
)
7793 if (next_fragP
== symbol_get_frag (symbolP
))
7801 /* Alignment Functions. */
7804 get_text_align_power (unsigned target_size
)
7806 if (target_size
<= 4)
7808 assert (target_size
== 8);
7814 get_text_align_max_fill_size (int align_pow
,
7815 bfd_boolean use_nops
,
7816 bfd_boolean use_no_density
)
7819 return (1 << align_pow
);
7821 return 3 * (1 << align_pow
);
7823 return 1 + (1 << align_pow
);
7827 /* Calculate the minimum bytes of fill needed at "address" to align a
7828 target instruction of size "target_size" so that it does not cross a
7829 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE,
7830 the fill can be an arbitrary number of bytes. Otherwise, the space must
7831 be filled by NOP instructions. */
7834 get_text_align_fill_size (addressT address
,
7837 bfd_boolean use_nops
,
7838 bfd_boolean use_no_density
)
7840 addressT alignment
, fill
, fill_limit
, fill_step
;
7841 bfd_boolean skip_one
= FALSE
;
7843 alignment
= (1 << align_pow
);
7844 assert (target_size
> 0 && alignment
>= (addressT
) target_size
);
7848 fill_limit
= alignment
;
7851 else if (!use_no_density
)
7853 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */
7854 fill_limit
= alignment
* 2;
7860 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */
7861 fill_limit
= alignment
* 3;
7865 /* Try all fill sizes until finding one that works. */
7866 for (fill
= 0; fill
< fill_limit
; fill
+= fill_step
)
7868 if (skip_one
&& fill
== 1)
7870 if ((address
+ fill
) >> align_pow
7871 == (address
+ fill
+ target_size
- 1) >> align_pow
)
7880 branch_align_power (segT sec
)
7882 /* If the Xtensa processor has a fetch width of 8 bytes, and the section
7883 is aligned to at least an 8-byte boundary, then a branch target need
7884 only fit within an 8-byte aligned block of memory to avoid a stall.
7885 Otherwise, try to fit branch targets within 4-byte aligned blocks
7886 (which may be insufficient, e.g., if the section has no alignment, but
7887 it's good enough). */
7888 if (xtensa_fetch_width
== 8)
7890 if (get_recorded_alignment (sec
) >= 3)
7894 assert (xtensa_fetch_width
== 4);
7900 /* This will assert if it is not possible. */
7903 get_text_align_nop_count (offsetT fill_size
, bfd_boolean use_no_density
)
7909 assert (fill_size
% 3 == 0);
7910 return (fill_size
/ 3);
7913 assert (fill_size
!= 1); /* Bad argument. */
7915 while (fill_size
> 1)
7918 if (fill_size
== 2 || fill_size
== 4)
7920 fill_size
-= insn_size
;
7923 assert (fill_size
!= 1); /* Bad algorithm. */
7929 get_text_align_nth_nop_size (offsetT fill_size
,
7931 bfd_boolean use_no_density
)
7938 assert (fill_size
!= 1); /* Bad argument. */
7940 while (fill_size
> 1)
7943 if (fill_size
== 2 || fill_size
== 4)
7945 fill_size
-= insn_size
;
7955 /* For the given fragment, find the appropriate address
7956 for it to begin at if we are using NOPs to align it. */
7959 get_noop_aligned_address (fragS
*fragP
, addressT address
)
7961 /* The rule is: get next fragment's FIRST instruction. Find
7962 the smallest number of bytes that need to be added to
7963 ensure that the next fragment's FIRST instruction will fit
7966 E.G., 2 bytes : 0, 1, 2 mod 4
7969 If the FIRST instruction MIGHT be relaxed,
7970 assume that it will become a 3-byte instruction.
7972 Note again here that LOOP instructions are not bundleable,
7973 and this relaxation only applies to LOOP opcodes. */
7976 int first_insn_size
;
7978 addressT pre_opcode_bytes
;
7981 xtensa_opcode opcode
;
7982 bfd_boolean is_loop
;
7984 assert (fragP
->fr_type
== rs_machine_dependent
);
7985 assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
7987 /* Find the loop frag. */
7988 first_insn
= next_non_empty_frag (fragP
);
7989 /* Now find the first insn frag. */
7990 first_insn
= next_non_empty_frag (first_insn
);
7992 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
7994 loop_insn_size
= xg_get_single_size (opcode
);
7996 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
7997 pre_opcode_bytes
+= loop_insn_size
;
7999 /* For loops, the alignment depends on the size of the
8000 instruction following the loop, not the LOOP instruction. */
8002 if (first_insn
== NULL
)
8003 first_insn_size
= xtensa_fetch_width
;
8005 first_insn_size
= get_loop_align_size (frag_format_size (first_insn
));
8007 /* If it was 8, then we'll need a larger alignment for the section. */
8008 align_power
= get_text_align_power (first_insn_size
);
8009 record_alignment (now_seg
, align_power
);
8011 fill_size
= get_text_align_fill_size
8012 (address
+ pre_opcode_bytes
, align_power
, first_insn_size
, TRUE
,
8013 fragP
->tc_frag_data
.is_no_density
);
8015 return address
+ fill_size
;
8019 /* 3 mechanisms for relaxing an alignment:
8021 Align to a power of 2.
8022 Align so the next fragment's instruction does not cross a word boundary.
8023 Align the current instruction so that if the next instruction
8024 were 3 bytes, it would not cross a word boundary.
8028 zeros - This is easy; always insert zeros.
8029 nops - 3-byte and 2-byte instructions
8033 >=5 : 3-byte instruction + fn (n-3)
8034 widening - widen previous instructions. */
8037 get_aligned_diff (fragS
*fragP
, addressT address
, offsetT
*max_diff
)
8039 addressT target_address
, loop_insn_offset
;
8041 xtensa_opcode loop_opcode
;
8042 bfd_boolean is_loop
;
8045 offsetT branch_align
;
8047 assert (fragP
->fr_type
== rs_machine_dependent
);
8048 switch (fragP
->fr_subtype
)
8050 case RELAX_DESIRE_ALIGN
:
8051 target_size
= next_frag_format_size (fragP
);
8052 if (target_size
== XTENSA_UNDEFINED
)
8054 align_power
= branch_align_power (now_seg
);
8055 branch_align
= 1 << align_power
;
8056 /* Don't count on the section alignment being as large as the target. */
8057 if (target_size
> branch_align
)
8058 target_size
= branch_align
;
8059 opt_diff
= get_text_align_fill_size (address
, align_power
,
8060 target_size
, FALSE
, FALSE
);
8062 *max_diff
= (opt_diff
+ branch_align
8063 - (target_size
+ ((address
+ opt_diff
) % branch_align
)));
8064 assert (*max_diff
>= opt_diff
);
8067 case RELAX_ALIGN_NEXT_OPCODE
:
8068 target_size
= get_loop_align_size (next_frag_format_size (fragP
));
8069 loop_insn_offset
= 0;
8070 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
8073 /* If the loop has been expanded then the LOOP instruction
8074 could be at an offset from this fragment. */
8075 if (next_non_empty_frag(fragP
)->tc_frag_data
.slot_subtypes
[0]
8077 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
8079 /* In an ideal world, which is what we are shooting for here,
8080 we wouldn't need to use any NOPs immediately prior to the
8081 LOOP instruction. If this approach fails, relax_frag_loop_align
8082 will call get_noop_aligned_address. */
8084 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
8085 align_power
= get_text_align_power (target_size
),
8086 opt_diff
= get_text_align_fill_size (target_address
, align_power
,
8087 target_size
, FALSE
, FALSE
);
8089 *max_diff
= xtensa_fetch_width
8090 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
8091 - target_size
+ opt_diff
;
8092 assert (*max_diff
>= opt_diff
);
8103 /* md_relax_frag Hook and Helper Functions. */
8105 static long relax_frag_loop_align (fragS
*, long);
8106 static long relax_frag_for_align (fragS
*, long);
8107 static long relax_frag_immed
8108 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
8111 /* Return the number of bytes added to this fragment, given that the
8112 input has been stretched already by "stretch". */
8115 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
8117 xtensa_isa isa
= xtensa_default_isa
;
8118 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
8119 long new_stretch
= 0;
8123 static xtensa_insnbuf vbuf
= NULL
;
8124 int slot
, num_slots
;
8127 as_where (&file_name
, &line
);
8128 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8130 fragP
->tc_frag_data
.unreported_expansion
= 0;
8132 switch (fragP
->fr_subtype
)
8134 case RELAX_ALIGN_NEXT_OPCODE
:
8135 /* Always convert. */
8136 if (fragP
->tc_frag_data
.relax_seen
)
8137 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
8140 case RELAX_LOOP_END
:
8144 case RELAX_LOOP_END_ADD_NOP
:
8145 /* Add a NOP and switch to .fill 0. */
8146 new_stretch
= relax_frag_add_nop (fragP
);
8150 case RELAX_DESIRE_ALIGN
:
8151 /* Do nothing. The narrowing before this frag will either align
8156 case RELAX_LITERAL_FINAL
:
8159 case RELAX_LITERAL_NR
:
8161 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
8162 assert (unreported
== lit_size
);
8163 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
8164 fragP
->fr_var
-= lit_size
;
8165 fragP
->fr_fix
+= lit_size
;
8171 vbuf
= xtensa_insnbuf_alloc (isa
);
8173 xtensa_insnbuf_from_chars
8174 (isa
, vbuf
, (unsigned char *) fragP
->fr_opcode
, 0);
8175 fmt
= xtensa_format_decode (isa
, vbuf
);
8176 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8178 for (slot
= 0; slot
< num_slots
; slot
++)
8180 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
8183 if (fragP
->tc_frag_data
.relax_seen
)
8184 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8188 case RELAX_IMMED_STEP1
:
8189 case RELAX_IMMED_STEP2
:
8190 /* Place the immediate. */
8191 new_stretch
+= relax_frag_immed
8192 (now_seg
, fragP
, stretch
,
8193 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8194 fmt
, slot
, stretched_p
, FALSE
);
8198 /* This is OK; see the note in xg_assemble_vliw_tokens. */
8204 case RELAX_LITERAL_POOL_BEGIN
:
8205 case RELAX_LITERAL_POOL_END
:
8206 case RELAX_MAYBE_UNREACHABLE
:
8207 case RELAX_MAYBE_DESIRE_ALIGN
:
8208 /* No relaxation required. */
8211 case RELAX_FILL_NOP
:
8212 case RELAX_UNREACHABLE
:
8213 if (fragP
->tc_frag_data
.relax_seen
)
8214 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8218 as_bad (_("bad relaxation state"));
8221 /* Tell gas we need another relaxation pass. */
8222 if (! fragP
->tc_frag_data
.relax_seen
)
8224 fragP
->tc_frag_data
.relax_seen
= TRUE
;
8228 new_logical_line (file_name
, line
);
8234 relax_frag_loop_align (fragS
*fragP
, long stretch
)
8236 addressT old_address
, old_next_address
, old_size
;
8237 addressT new_address
, new_next_address
, new_size
;
8240 /* All the frags with relax_frag_for_alignment prior to this one in the
8241 section have been done, hopefully eliminating the need for a NOP here.
8242 But, this will put it in if necessary. */
8244 /* Calculate the old address of this fragment and the next fragment. */
8245 old_address
= fragP
->fr_address
- stretch
;
8246 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
8247 fragP
->tc_frag_data
.text_expansion
[0]);
8248 old_size
= old_next_address
- old_address
;
8250 /* Calculate the new address of this fragment and the next fragment. */
8251 new_address
= fragP
->fr_address
;
8253 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
8254 new_size
= new_next_address
- new_address
;
8256 growth
= new_size
- old_size
;
8258 /* Fix up the text_expansion field and return the new growth. */
8259 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
8264 /* Add a NOP instruction. */
8267 relax_frag_add_nop (fragS
*fragP
)
8269 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
8270 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
8271 assemble_nop (length
, nop_buf
);
8272 fragP
->tc_frag_data
.is_insn
= TRUE
;
8274 if (fragP
->fr_var
< length
)
8276 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP
->fr_var
, length
);
8280 fragP
->fr_fix
+= length
;
8281 fragP
->fr_var
-= length
;
8286 static long future_alignment_required (fragS
*, long);
8289 relax_frag_for_align (fragS
*fragP
, long stretch
)
8291 /* Overview of the relaxation procedure for alignment:
8292 We can widen with NOPs or by widening instructions or by filling
8293 bytes after jump instructions. Find the opportune places and widen
8294 them if necessary. */
8299 assert (fragP
->fr_subtype
== RELAX_FILL_NOP
8300 || fragP
->fr_subtype
== RELAX_UNREACHABLE
8301 || (fragP
->fr_subtype
== RELAX_SLOTS
8302 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
8304 stretch_me
= future_alignment_required (fragP
, stretch
);
8305 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
8311 /* We expanded on a previous pass. Can we shrink now? */
8312 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
8313 if (shrink
<= stretch
&& stretch
> 0)
8315 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8321 /* Below here, diff > 0. */
8322 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8328 /* Return the address of the next frag that should be aligned.
8330 By "address" we mean the address it _would_ be at if there
8331 is no action taken to align it between here and the target frag.
8332 In other words, if no narrows and no fill nops are used between
8333 here and the frag to align, _even_if_ some of the frags we use
8334 to align targets have already expanded on a previous relaxation
8337 Also, count each frag that may be used to help align the target.
8339 Return 0 if there are no frags left in the chain that need to be
8343 find_address_of_next_align_frag (fragS
**fragPP
,
8347 bfd_boolean
*paddable
)
8349 fragS
*fragP
= *fragPP
;
8350 addressT address
= fragP
->fr_address
;
8352 /* Do not reset the counts to 0. */
8356 /* Limit this to a small search. */
8357 if (*widens
>= (int) xtensa_fetch_width
)
8362 address
+= fragP
->fr_fix
;
8364 if (fragP
->fr_type
== rs_fill
)
8365 address
+= fragP
->fr_offset
* fragP
->fr_var
;
8366 else if (fragP
->fr_type
== rs_machine_dependent
)
8368 switch (fragP
->fr_subtype
)
8370 case RELAX_UNREACHABLE
:
8374 case RELAX_FILL_NOP
:
8376 if (!fragP
->tc_frag_data
.is_no_density
)
8381 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8386 address
+= total_frag_text_expansion (fragP
);;
8390 address
+= fragP
->tc_frag_data
.text_expansion
[0];
8393 case RELAX_ALIGN_NEXT_OPCODE
:
8394 case RELAX_DESIRE_ALIGN
:
8398 case RELAX_MAYBE_UNREACHABLE
:
8399 case RELAX_MAYBE_DESIRE_ALIGN
:
8404 /* Just punt if we don't know the type. */
8411 /* Just punt if we don't know the type. */
8415 fragP
= fragP
->fr_next
;
8423 static long bytes_to_stretch (fragS
*, int, int, int, int);
8426 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
8428 fragS
*this_frag
= fragP
;
8432 int narrow_nops
= 0;
8433 bfd_boolean paddable
= FALSE
;
8434 offsetT local_opt_diff
;
8437 int stretch_amount
= 0;
8438 int local_stretch_amount
;
8439 int global_stretch_amount
;
8441 address
= find_address_of_next_align_frag
8442 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
8446 if (this_frag
->tc_frag_data
.is_aligning_branch
)
8447 this_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
8449 frag_wane (this_frag
);
8453 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
8454 opt_diff
= local_opt_diff
;
8455 assert (opt_diff
>= 0);
8456 assert (max_diff
>= opt_diff
);
8461 fragP
= fragP
->fr_next
;
8463 while (fragP
&& opt_diff
< max_diff
&& address
)
8465 /* We only use these to determine if we can exit early
8466 because there will be plenty of ways to align future
8468 int glob_widens
= 0;
8471 bfd_boolean glob_pad
= 0;
8472 address
= find_address_of_next_align_frag
8473 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
8474 /* If there is a padable portion, then skip. */
8475 if (glob_pad
|| glob_widens
>= (1 << branch_align_power (now_seg
)))
8480 offsetT next_m_diff
;
8481 offsetT next_o_diff
;
8483 /* Downrange frags haven't had stretch added to them yet. */
8486 /* The address also includes any text expansion from this
8487 frag in a previous pass, but we don't want that. */
8488 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
8490 /* Assume we are going to move at least opt_diff. In
8491 reality, we might not be able to, but assuming that
8492 we will helps catch cases where moving opt_diff pushes
8493 the next target from aligned to unaligned. */
8494 address
+= opt_diff
;
8496 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
8498 /* Now cleanup for the adjustments to address. */
8499 next_o_diff
+= opt_diff
;
8500 next_m_diff
+= opt_diff
;
8501 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
8502 opt_diff
= next_o_diff
;
8503 if (next_m_diff
< max_diff
)
8504 max_diff
= next_m_diff
;
8505 fragP
= fragP
->fr_next
;
8509 /* If there are enough wideners in between, do it. */
8512 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
8514 assert (opt_diff
<= UNREACHABLE_MAX_WIDTH
);
8519 local_stretch_amount
8520 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8521 num_widens
, local_opt_diff
);
8522 global_stretch_amount
8523 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8524 num_widens
, opt_diff
);
8525 /* If the condition below is true, then the frag couldn't
8526 stretch the correct amount for the global case, so we just
8527 optimize locally. We'll rely on the subsequent frags to get
8528 the correct alignment in the global case. */
8529 if (global_stretch_amount
< local_stretch_amount
)
8530 stretch_amount
= local_stretch_amount
;
8532 stretch_amount
= global_stretch_amount
;
8534 if (this_frag
->fr_subtype
== RELAX_SLOTS
8535 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8536 assert (stretch_amount
<= 1);
8537 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8539 if (this_frag
->tc_frag_data
.is_no_density
)
8540 assert (stretch_amount
== 3 || stretch_amount
== 0);
8542 assert (stretch_amount
<= 3);
8545 return stretch_amount
;
8549 /* The idea: widen everything you can to get a target or loop aligned,
8550 then start using NOPs.
8552 When we must have a NOP, here is a table of how we decide
8553 (so you don't have to fight through the control flow below):
8555 wide_nops = the number of wide NOPs available for aligning
8556 narrow_nops = the number of narrow NOPs available for aligning
8557 (a subset of wide_nops)
8558 widens = the number of narrow instructions that should be widened
8565 b 0 1 1 (case 3a makes this case unnecessary)
8568 c 0 1 2 (case 4a makes this case unnecessary)
8571 c 0 2 1 (case 5b makes this case unnecessary)
8574 c 0 1 4 (case 6b makes this case unnecessary)
8575 d 1 1 1 (case 6a makes this case unnecessary)
8576 e 0 2 2 (case 6a makes this case unnecessary)
8577 f 0 3 0 (case 6a makes this case unnecessary)
8580 c 1 1 2 (case 7b makes this case unnecessary)
8581 d 0 1 5 (case 7a makes this case unnecessary)
8582 e 0 2 3 (case 7b makes this case unnecessary)
8583 f 0 3 1 (case 7b makes this case unnecessary)
8584 g 1 2 1 (case 7b makes this case unnecessary)
8588 bytes_to_stretch (fragS
*this_frag
,
8594 int bytes_short
= desired_diff
- num_widens
;
8596 assert (desired_diff
>= 0 && desired_diff
< 8);
8597 if (desired_diff
== 0)
8600 assert (wide_nops
> 0 || num_widens
> 0);
8602 /* Always prefer widening to NOP-filling. */
8603 if (bytes_short
< 0)
8605 /* There are enough RELAX_NARROW frags after this one
8606 to align the target without widening this frag in any way. */
8610 if (bytes_short
== 0)
8612 /* Widen every narrow between here and the align target
8613 and the align target will be properly aligned. */
8614 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8620 /* From here we will need at least one NOP to get an alignment.
8621 However, we may not be able to align at all, in which case,
8623 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8625 switch (desired_diff
)
8630 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 1)
8631 return 2; /* case 2 */
8637 return 3; /* case 3a */
8639 if (num_widens
>= 1 && wide_nops
== 1)
8640 return 3; /* case 4a */
8641 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 2)
8642 return 2; /* case 4b */
8645 if (num_widens
>= 2 && wide_nops
== 1)
8646 return 3; /* case 5a */
8647 /* We will need two nops. Are there enough nops
8648 between here and the align target? */
8649 if (wide_nops
< 2 || narrow_nops
== 0)
8651 /* Are there other nops closer that can serve instead? */
8652 if (wide_nops
> 2 && narrow_nops
> 1)
8654 /* Take the density one first, because there might not be
8655 another density one available. */
8656 if (!this_frag
->tc_frag_data
.is_no_density
)
8657 return 2; /* case 5b narrow */
8659 return 3; /* case 5b wide */
8663 return 3; /* case 6a */
8664 else if (num_widens
>= 3 && wide_nops
== 1)
8665 return 3; /* case 6b */
8668 if (wide_nops
== 1 && num_widens
>= 4)
8669 return 3; /* case 7a */
8670 else if (wide_nops
== 2 && num_widens
>= 1)
8671 return 3; /* case 7b */
8679 /* We will need a NOP no matter what, but should we widen
8680 this instruction to help?
8682 This is a RELAX_NARROW frag. */
8683 switch (desired_diff
)
8692 if (wide_nops
>= 1 && num_widens
== 1)
8693 return 1; /* case 4a */
8696 if (wide_nops
>= 1 && num_widens
== 2)
8697 return 1; /* case 5a */
8701 return 0; /* case 6a */
8702 else if (wide_nops
>= 1 && num_widens
== 3)
8703 return 1; /* case 6b */
8706 if (wide_nops
>= 1 && num_widens
== 4)
8707 return 1; /* case 7a */
8708 else if (wide_nops
>= 2 && num_widens
== 1)
8709 return 1; /* case 7b */
8722 relax_frag_immed (segT segP
,
8729 bfd_boolean estimate_only
)
8733 bfd_boolean negatable_branch
= FALSE
;
8734 bfd_boolean branch_jmp_to_next
= FALSE
;
8735 bfd_boolean wide_insn
= FALSE
;
8736 xtensa_isa isa
= xtensa_default_isa
;
8738 offsetT frag_offset
;
8741 int num_text_bytes
, num_literal_bytes
;
8742 int literal_diff
, total_text_diff
, this_text_diff
, first
;
8744 assert (fragP
->fr_opcode
!= NULL
);
8746 xg_clear_vinsn (&cur_vinsn
);
8747 vinsn_from_chars (&cur_vinsn
, fragP
->fr_opcode
);
8748 if (cur_vinsn
.num_slots
> 1)
8751 tinsn
= cur_vinsn
.slots
[slot
];
8752 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
8754 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
) == 1)
8757 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
8758 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
8760 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
8762 old_size
= xtensa_format_length (isa
, fmt
);
8764 /* Special case: replace a branch to the next instruction with a NOP.
8765 This is required to work around a hardware bug in T1040.0 and also
8766 serves as an optimization. */
8768 if (branch_jmp_to_next
8769 && ((old_size
== 2) || (old_size
== 3))
8770 && !next_frag_is_loop_target (fragP
))
8773 /* Here is the fun stuff: Get the immediate field from this
8774 instruction. If it fits, we are done. If not, find the next
8775 instruction sequence that fits. */
8777 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
8778 istack_init (&istack
);
8779 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
8780 min_steps
, stretch
);
8781 if (num_steps
< min_steps
)
8783 as_fatal (_("internal error: relaxation failed"));
8787 if (num_steps
> RELAX_IMMED_MAXSTEPS
)
8789 as_fatal (_("internal error: relaxation requires too many steps"));
8793 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
8795 /* Figure out the number of bytes needed. */
8797 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
8799 num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
8801 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
8803 num_text_bytes
= get_num_stack_text_bytes (&istack
);
8806 num_text_bytes
+= old_size
;
8807 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
8808 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
8810 total_text_diff
= num_text_bytes
- old_size
;
8811 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
8813 /* It MUST get larger. If not, we could get an infinite loop. */
8814 assert (num_text_bytes
>= 0);
8815 assert (literal_diff
>= 0);
8816 assert (total_text_diff
>= 0);
8818 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
8819 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
8820 assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
8821 assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
8823 /* Find the associated expandable literal for this. */
8824 if (literal_diff
!= 0)
8826 lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
8829 assert (literal_diff
== 4);
8830 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
8832 /* We expect that the literal section state has NOT been
8834 assert (lit_fragP
->fr_type
== rs_machine_dependent
8835 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
8836 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
8838 /* We need to mark this section for another iteration
8844 if (negatable_branch
&& istack
.ninsn
> 1)
8845 update_next_frag_state (fragP
);
8847 return this_text_diff
;
8851 /* md_convert_frag Hook and Helper Functions. */
8853 static void convert_frag_align_next_opcode (fragS
*);
8854 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
8855 static void convert_frag_fill_nop (fragS
*);
8856 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
8859 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
8861 static xtensa_insnbuf vbuf
= NULL
;
8862 xtensa_isa isa
= xtensa_default_isa
;
8869 as_where (&file_name
, &line
);
8870 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
8872 switch (fragp
->fr_subtype
)
8874 case RELAX_ALIGN_NEXT_OPCODE
:
8875 /* Always convert. */
8876 convert_frag_align_next_opcode (fragp
);
8879 case RELAX_DESIRE_ALIGN
:
8880 /* Do nothing. If not aligned already, too bad. */
8884 case RELAX_LITERAL_FINAL
:
8889 vbuf
= xtensa_insnbuf_alloc (isa
);
8891 xtensa_insnbuf_from_chars
8892 (isa
, vbuf
, (unsigned char *) fragp
->fr_opcode
, 0);
8893 fmt
= xtensa_format_decode (isa
, vbuf
);
8894 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8896 for (slot
= 0; slot
< num_slots
; slot
++)
8898 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
8901 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
8905 case RELAX_IMMED_STEP1
:
8906 case RELAX_IMMED_STEP2
:
8907 /* Place the immediate. */
8910 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8915 /* This is OK because some slots could have
8916 relaxations and others have none. */
8922 case RELAX_UNREACHABLE
:
8923 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
8924 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
8925 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
8929 case RELAX_MAYBE_UNREACHABLE
:
8930 case RELAX_MAYBE_DESIRE_ALIGN
:
8934 case RELAX_FILL_NOP
:
8935 convert_frag_fill_nop (fragp
);
8938 case RELAX_LITERAL_NR
:
8939 if (use_literal_section
)
8941 /* This should have been handled during relaxation. When
8942 relaxing a code segment, literals sometimes need to be
8943 added to the corresponding literal segment. If that
8944 literal segment has already been relaxed, then we end up
8945 in this situation. Marking the literal segments as data
8946 would make this happen less often (since GAS always relaxes
8947 code before data), but we could still get into trouble if
8948 there are instructions in a segment that is not marked as
8949 containing code. Until we can implement a better solution,
8950 cheat and adjust the addresses of all the following frags.
8951 This could break subsequent alignments, but the linker's
8952 literal coalescing will do that anyway. */
8955 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
8956 assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
8957 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
8960 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
8964 as_bad (_("invalid relaxation fragment result"));
8969 new_logical_line (file_name
, line
);
8974 convert_frag_align_next_opcode (fragS
*fragp
)
8976 char *nop_buf
; /* Location for Writing. */
8977 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
8978 addressT aligned_address
;
8982 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
8984 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
8985 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
8986 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
8988 for (nop
= 0; nop
< nop_count
; nop
++)
8991 nop_size
= get_text_align_nth_nop_size (fill_size
, nop
, use_no_density
);
8993 assemble_nop (nop_size
, nop_buf
);
8994 nop_buf
+= nop_size
;
8997 fragp
->fr_fix
+= fill_size
;
8998 fragp
->fr_var
-= fill_size
;
9003 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
9005 TInsn tinsn
, single_target
;
9006 int size
, old_size
, diff
;
9007 offsetT frag_offset
;
9010 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
9012 if (fragP
->tc_frag_data
.is_aligning_branch
== 1)
9014 assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
9015 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
9016 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
9021 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
9023 /* No conversion. */
9028 assert (fragP
->fr_opcode
!= NULL
);
9030 /* Frags in this relaxation state should only contain
9031 single instruction bundles. */
9032 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
9034 /* Just convert it to a wide form.... */
9036 old_size
= xg_get_single_size (tinsn
.opcode
);
9038 tinsn_init (&single_target
);
9039 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9041 if (! xg_is_single_relaxable_insn (&tinsn
, &single_target
, FALSE
))
9043 as_bad (_("unable to widen instruction"));
9047 size
= xg_get_single_size (single_target
.opcode
);
9048 xg_emit_insn_to_buf (&single_target
, fragP
->fr_opcode
, fragP
,
9051 diff
= size
- old_size
;
9053 assert (diff
<= fragP
->fr_var
);
9054 fragP
->fr_var
-= diff
;
9055 fragP
->fr_fix
+= diff
;
9063 convert_frag_fill_nop (fragS
*fragP
)
9065 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
9066 int size
= fragP
->tc_frag_data
.text_expansion
[0];
9067 assert ((unsigned) size
== (fragP
->fr_next
->fr_address
9068 - fragP
->fr_address
- fragP
->fr_fix
));
9071 /* No conversion. */
9075 assemble_nop (size
, loc
);
9076 fragP
->tc_frag_data
.is_insn
= TRUE
;
9077 fragP
->fr_var
-= size
;
9078 fragP
->fr_fix
+= size
;
9083 static fixS
*fix_new_exp_in_seg
9084 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
9085 bfd_reloc_code_real_type
);
9086 static void convert_frag_immed_finish_loop (segT
, fragS
*, TInsn
*);
9089 convert_frag_immed (segT segP
,
9095 char *immed_instr
= fragP
->fr_opcode
;
9097 bfd_boolean expanded
= FALSE
;
9098 bfd_boolean branch_jmp_to_next
= FALSE
;
9099 char *fr_opcode
= fragP
->fr_opcode
;
9100 xtensa_isa isa
= xtensa_default_isa
;
9101 bfd_boolean wide_insn
= FALSE
;
9103 bfd_boolean is_loop
;
9105 assert (fr_opcode
!= NULL
);
9107 xg_clear_vinsn (&cur_vinsn
);
9109 vinsn_from_chars (&cur_vinsn
, fr_opcode
);
9110 if (cur_vinsn
.num_slots
> 1)
9113 orig_tinsn
= cur_vinsn
.slots
[slot
];
9114 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
9116 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
9118 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9119 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
9121 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
9123 /* Conversion just inserts a NOP and marks the fix as completed. */
9124 bytes
= xtensa_format_length (isa
, fmt
);
9127 cur_vinsn
.slots
[slot
].opcode
=
9128 xtensa_format_slot_nop_opcode (isa
, cur_vinsn
.format
, slot
);
9129 cur_vinsn
.slots
[slot
].ntok
= 0;
9133 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
9134 assert (bytes
== 2 || bytes
== 3);
9135 build_nop (&cur_vinsn
.slots
[0], bytes
);
9136 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
9138 vinsn_to_insnbuf (&cur_vinsn
, fr_opcode
, frag_now
, TRUE
);
9139 xtensa_insnbuf_to_chars
9140 (isa
, cur_vinsn
.insnbuf
, (unsigned char *) fr_opcode
, 0);
9145 /* Here is the fun stuff: Get the immediate field from this
9146 instruction. If it fits, we're done. If not, find the next
9147 instruction sequence that fits. */
9151 symbolS
*lit_sym
= NULL
;
9153 int target_offset
= 0;
9156 symbolS
*gen_label
= NULL
;
9157 offsetT frag_offset
;
9158 bfd_boolean first
= TRUE
;
9159 bfd_boolean last_is_jump
;
9161 /* It does not fit. Find something that does and
9162 convert immediately. */
9163 frag_offset
= fr_opcode
- fragP
->fr_literal
;
9164 istack_init (&istack
);
9165 xg_assembly_relax (&istack
, &orig_tinsn
,
9166 segP
, fragP
, frag_offset
, min_steps
, 0);
9168 old_size
= xtensa_format_length (isa
, fmt
);
9170 /* Assemble this right inline. */
9172 /* First, create the mapping from a label name to the REAL label. */
9174 for (i
= 0; i
< istack
.ninsn
; i
++)
9176 TInsn
*tinsn
= &istack
.insn
[i
];
9179 switch (tinsn
->insn_type
)
9182 if (lit_sym
!= NULL
)
9183 as_bad (_("multiple literals in expansion"));
9184 /* First find the appropriate space in the literal pool. */
9185 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9186 if (lit_frag
== NULL
)
9187 as_bad (_("no registered fragment for literal"));
9188 if (tinsn
->ntok
!= 1)
9189 as_bad (_("number of literal tokens != 1"));
9191 /* Set the literal symbol and add a fixup. */
9192 lit_sym
= lit_frag
->fr_symbol
;
9196 if (align_targets
&& !is_loop
)
9198 fragS
*unreach
= fragP
->fr_next
;
9199 while (!(unreach
->fr_type
== rs_machine_dependent
9200 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9201 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
9203 unreach
= unreach
->fr_next
;
9206 assert (unreach
->fr_type
== rs_machine_dependent
9207 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9208 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
9210 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
9212 assert (gen_label
== NULL
);
9213 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
9214 fr_opcode
- fragP
->fr_literal
9215 + target_offset
, fragP
);
9219 if (first
&& wide_insn
)
9221 target_offset
+= xtensa_format_length (isa
, fmt
);
9223 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9224 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9227 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9234 last_is_jump
= FALSE
;
9235 for (i
= 0; i
< istack
.ninsn
; i
++)
9237 TInsn
*tinsn
= &istack
.insn
[i
];
9241 bfd_reloc_code_real_type reloc_type
;
9243 switch (tinsn
->insn_type
)
9246 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9247 /* Already checked. */
9248 assert (lit_frag
!= NULL
);
9249 assert (lit_sym
!= NULL
);
9250 assert (tinsn
->ntok
== 1);
9252 target_seg
= S_GET_SEGMENT (lit_sym
);
9253 assert (target_seg
);
9254 if (tinsn
->tok
[0].X_op
== O_pltrel
)
9255 reloc_type
= BFD_RELOC_XTENSA_PLT
;
9257 reloc_type
= BFD_RELOC_32
;
9258 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
9259 &tinsn
->tok
[0], FALSE
, reloc_type
);
9266 xg_resolve_labels (tinsn
, gen_label
);
9267 xg_resolve_literals (tinsn
, lit_sym
);
9268 if (wide_insn
&& first
)
9271 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9273 cur_vinsn
.slots
[slot
] = *tinsn
;
9277 cur_vinsn
.slots
[slot
].opcode
=
9278 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
9279 cur_vinsn
.slots
[slot
].ntok
= 0;
9281 vinsn_to_insnbuf (&cur_vinsn
, immed_instr
, fragP
, TRUE
);
9282 xtensa_insnbuf_to_chars (isa
, cur_vinsn
.insnbuf
,
9283 (unsigned char *) immed_instr
, 0);
9284 fragP
->tc_frag_data
.is_insn
= TRUE
;
9285 size
= xtensa_format_length (isa
, fmt
);
9286 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9289 (tinsn
, immed_instr
+ size
, fragP
,
9290 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
9291 size
+= xg_get_single_size (tinsn
->opcode
);
9296 size
= xg_get_single_size (tinsn
->opcode
);
9297 xg_emit_insn_to_buf (tinsn
, immed_instr
, fragP
,
9298 immed_instr
- fragP
->fr_literal
, TRUE
);
9300 immed_instr
+= size
;
9306 diff
= total_size
- old_size
;
9310 assert (diff
<= fragP
->fr_var
);
9311 fragP
->fr_var
-= diff
;
9312 fragP
->fr_fix
+= diff
;
9315 /* Check for undefined immediates in LOOP instructions. */
9319 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
9320 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9322 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9325 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
9326 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9328 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9333 if (expanded
&& xtensa_opcode_is_loop (isa
, orig_tinsn
.opcode
) == 1)
9334 convert_frag_immed_finish_loop (segP
, fragP
, &orig_tinsn
);
9336 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
9338 /* Add an expansion note on the expanded instruction. */
9339 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
9340 &orig_tinsn
.tok
[0], TRUE
,
9341 BFD_RELOC_XTENSA_ASM_EXPAND
);
9346 /* Add a new fix expression into the desired segment. We have to
9347 switch to that segment to do this. */
9350 fix_new_exp_in_seg (segT new_seg
,
9357 bfd_reloc_code_real_type r_type
)
9361 subsegT subseg
= now_subseg
;
9363 assert (new_seg
!= 0);
9364 subseg_set (new_seg
, new_subseg
);
9366 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
9367 subseg_set (seg
, subseg
);
9372 /* Relax a loop instruction so that it can span loop >256 bytes.
9378 addi as, as, lo8 (label-.L1)
9379 addmi as, as, mid8 (label-.L1)
9390 convert_frag_immed_finish_loop (segT segP
, fragS
*fragP
, TInsn
*tinsn
)
9395 unsigned long target
;
9396 static xtensa_insnbuf insnbuf
= NULL
;
9397 unsigned int loop_length
, loop_length_hi
, loop_length_lo
;
9398 xtensa_isa isa
= xtensa_default_isa
;
9399 addressT loop_offset
;
9400 addressT addi_offset
= 9;
9401 addressT addmi_offset
= 12;
9406 insnbuf
= xtensa_insnbuf_alloc (isa
);
9408 /* Get the loop offset. */
9409 loop_offset
= get_expanded_loop_offset (tinsn
->opcode
);
9411 /* Validate that there really is a LOOP at the loop_offset. Because
9412 loops are not bundleable, we can assume that the instruction will be
9414 tinsn_from_chars (&loop_insn
, fragP
->fr_opcode
+ loop_offset
, 0);
9415 tinsn_immed_from_frag (&loop_insn
, fragP
, 0);
9417 assert (xtensa_opcode_is_loop (isa
, loop_insn
.opcode
) == 1);
9418 addi_offset
+= loop_offset
;
9419 addmi_offset
+= loop_offset
;
9421 assert (tinsn
->ntok
== 2);
9422 if (tinsn
->tok
[1].X_op
== O_constant
)
9423 target
= tinsn
->tok
[1].X_add_number
;
9424 else if (tinsn
->tok
[1].X_op
== O_symbol
)
9426 /* Find the fragment. */
9427 symbolS
*sym
= tinsn
->tok
[1].X_add_symbol
;
9428 assert (S_GET_SEGMENT (sym
) == segP
9429 || S_GET_SEGMENT (sym
) == absolute_section
);
9430 target
= (S_GET_VALUE (sym
) + tinsn
->tok
[1].X_add_number
);
9434 as_bad (_("invalid expression evaluation type %d"), tinsn
->tok
[1].X_op
);
9439 know (symbolP
->sy_frag
);
9440 know (!(S_GET_SEGMENT (symbolP
) == absolute_section
)
9441 || symbol_get_frag (symbolP
) == &zero_address_frag
);
9443 loop_length
= target
- (fragP
->fr_address
+ fragP
->fr_fix
);
9444 loop_length_hi
= loop_length
& ~0x0ff;
9445 loop_length_lo
= loop_length
& 0x0ff;
9446 if (loop_length_lo
>= 128)
9448 loop_length_lo
-= 256;
9449 loop_length_hi
+= 256;
9452 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
9453 32512. If the loop is larger than that, then we just fail. */
9454 if (loop_length_hi
> 32512)
9455 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9456 _("loop too long for LOOP instruction"));
9458 tinsn_from_chars (&addi_insn
, fragP
->fr_opcode
+ addi_offset
, 0);
9459 assert (addi_insn
.opcode
== xtensa_addi_opcode
);
9461 tinsn_from_chars (&addmi_insn
, fragP
->fr_opcode
+ addmi_offset
, 0);
9462 assert (addmi_insn
.opcode
== xtensa_addmi_opcode
);
9464 set_expr_const (&addi_insn
.tok
[2], loop_length_lo
);
9465 tinsn_to_insnbuf (&addi_insn
, insnbuf
);
9467 fragP
->tc_frag_data
.is_insn
= TRUE
;
9468 xtensa_insnbuf_to_chars
9469 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addi_offset
, 0);
9471 set_expr_const (&addmi_insn
.tok
[2], loop_length_hi
);
9472 tinsn_to_insnbuf (&addmi_insn
, insnbuf
);
9473 xtensa_insnbuf_to_chars
9474 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addmi_offset
, 0);
9476 /* Walk through all of the frags from here to the loop end
9477 and mark them as no_transform to keep them from being modified
9478 by the linker. If we ever have a relocation for the
9479 addi/addmi of the difference of two symbols we can remove this. */
9482 for (next_fragP
= fragP
; next_fragP
!= NULL
;
9483 next_fragP
= next_fragP
->fr_next
)
9485 next_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
9486 if (next_fragP
->tc_frag_data
.is_loop_target
)
9488 if (target_count
== 2)
9494 /* A map that keeps information on a per-subsegment basis. This is
9495 maintained during initial assembly, but is invalid once the
9496 subsegments are smashed together. I.E., it cannot be used during
9499 typedef struct subseg_map_struct
9507 float total_freq
; /* fall-through + branch target frequency */
9508 float target_freq
; /* branch target frequency alone */
9510 struct subseg_map_struct
*next
;
9514 static subseg_map
*sseg_map
= NULL
;
9517 get_subseg_info (segT seg
, subsegT subseg
)
9519 subseg_map
*subseg_e
;
9521 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
9523 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
9531 add_subseg_info (segT seg
, subsegT subseg
)
9533 subseg_map
*subseg_e
= (subseg_map
*) xmalloc (sizeof (subseg_map
));
9534 memset (subseg_e
, 0, sizeof (subseg_map
));
9535 subseg_e
->seg
= seg
;
9536 subseg_e
->subseg
= subseg
;
9537 subseg_e
->flags
= 0;
9538 /* Start off considering every branch target very important. */
9539 subseg_e
->target_freq
= 1.0;
9540 subseg_e
->total_freq
= 1.0;
9541 subseg_e
->next
= sseg_map
;
9542 sseg_map
= subseg_e
;
9548 get_last_insn_flags (segT seg
, subsegT subseg
)
9550 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9552 return subseg_e
->flags
;
9558 set_last_insn_flags (segT seg
,
9563 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9565 subseg_e
= add_subseg_info (seg
, subseg
);
9567 subseg_e
->flags
|= fl
;
9569 subseg_e
->flags
&= ~fl
;
9574 get_subseg_total_freq (segT seg
, subsegT subseg
)
9576 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9578 return subseg_e
->total_freq
;
9584 get_subseg_target_freq (segT seg
, subsegT subseg
)
9586 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9588 return subseg_e
->target_freq
;
9594 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
9596 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9598 subseg_e
= add_subseg_info (seg
, subseg
);
9599 subseg_e
->total_freq
= total_f
;
9600 subseg_e
->target_freq
= target_f
;
9604 /* Segment Lists and emit_state Stuff. */
9607 xtensa_move_seg_list_to_beginning (seg_list
*head
)
9612 segT literal_section
= head
->seg
;
9614 /* Move the literal section to the front of the section list. */
9615 assert (literal_section
);
9616 if (literal_section
!= stdoutput
->sections
)
9618 bfd_section_list_remove (stdoutput
, literal_section
);
9619 bfd_section_list_prepend (stdoutput
, literal_section
);
9626 static void mark_literal_frags (seg_list
*);
9629 xtensa_move_literals (void)
9632 frchainS
*frchain_from
, *frchain_to
;
9633 fragS
*search_frag
, *next_frag
, *last_frag
, *literal_pool
, *insert_after
;
9634 fragS
**frag_splice
;
9637 fixS
*fix
, *next_fix
, **fix_splice
;
9640 mark_literal_frags (literal_head
->next
);
9642 if (use_literal_section
)
9645 for (segment
= literal_head
->next
; segment
; segment
= segment
->next
)
9647 /* Keep the literals for .init and .fini in separate sections. */
9648 if (!strcmp (segment_name (segment
->seg
), INIT_SECTION_NAME
)
9649 || !strcmp (segment_name (segment
->seg
), FINI_SECTION_NAME
))
9652 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9653 search_frag
= frchain_from
->frch_root
;
9654 literal_pool
= NULL
;
9656 frag_splice
= &(frchain_from
->frch_root
);
9658 while (!search_frag
->tc_frag_data
.literal_frag
)
9660 assert (search_frag
->fr_fix
== 0
9661 || search_frag
->fr_type
== rs_align
);
9662 search_frag
= search_frag
->fr_next
;
9665 assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
9666 == RELAX_LITERAL_POOL_BEGIN
);
9667 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
9669 /* Make sure that all the frags in this series are closed, and
9670 that there is at least one left over of zero-size. This
9671 prevents us from making a segment with an frchain without any
9673 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9674 xtensa_set_frag_assembly_state (frag_now
);
9675 last_frag
= frag_now
;
9676 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9677 xtensa_set_frag_assembly_state (frag_now
);
9679 while (search_frag
!= frag_now
)
9681 next_frag
= search_frag
->fr_next
;
9683 /* First, move the frag out of the literal section and
9684 to the appropriate place. */
9685 if (search_frag
->tc_frag_data
.literal_frag
)
9687 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
9688 assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
9689 frchain_to
= literal_pool
->tc_frag_data
.lit_frchain
;
9690 assert (frchain_to
);
9692 insert_after
= literal_pool
;
9694 while (insert_after
->fr_next
->fr_subtype
!= RELAX_LITERAL_POOL_END
)
9695 insert_after
= insert_after
->fr_next
;
9697 dest_seg
= insert_after
->fr_next
->tc_frag_data
.lit_seg
;
9699 *frag_splice
= next_frag
;
9700 search_frag
->fr_next
= insert_after
->fr_next
;
9701 insert_after
->fr_next
= search_frag
;
9702 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
9704 /* Now move any fixups associated with this frag to the
9706 fix
= frchain_from
->fix_root
;
9707 fix_splice
= &(frchain_from
->fix_root
);
9710 next_fix
= fix
->fx_next
;
9711 if (fix
->fx_frag
== search_frag
)
9713 *fix_splice
= next_fix
;
9714 fix
->fx_next
= frchain_to
->fix_root
;
9715 frchain_to
->fix_root
= fix
;
9716 if (frchain_to
->fix_tail
== NULL
)
9717 frchain_to
->fix_tail
= fix
;
9720 fix_splice
= &(fix
->fx_next
);
9723 search_frag
= next_frag
;
9726 if (frchain_from
->fix_root
!= NULL
)
9728 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9729 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
9731 assert (frchain_from
->fix_root
== NULL
);
9733 frchain_from
->fix_tail
= NULL
;
9734 xtensa_restore_emit_state (&state
);
9737 /* Now fix up the SEGMENT value for all the literal symbols. */
9738 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
9740 symbolS
*lit_sym
= lit
->sym
;
9741 segT dest_seg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
9743 S_SET_SEGMENT (lit_sym
, dest_seg
);
9748 /* Walk over all the frags for segments in a list and mark them as
9749 containing literals. As clunky as this is, we can't rely on frag_var
9750 and frag_variant to get called in all situations. */
9753 mark_literal_frags (seg_list
*segment
)
9755 frchainS
*frchain_from
;
9760 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9761 search_frag
= frchain_from
->frch_root
;
9764 search_frag
->tc_frag_data
.is_literal
= TRUE
;
9765 search_frag
= search_frag
->fr_next
;
9767 segment
= segment
->next
;
9773 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
9775 /* Move all of the sections in the section list to come
9776 after "after" in the gnu segment list. */
9781 segT literal_section
= head
->seg
;
9783 /* Move the literal section after "after". */
9784 assert (literal_section
);
9785 if (literal_section
!= after
)
9787 bfd_section_list_remove (stdoutput
, literal_section
);
9788 bfd_section_list_insert_after (stdoutput
, after
, literal_section
);
9796 /* Push all the literal segments to the end of the gnu list. */
9799 xtensa_reorder_segments (void)
9806 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
9812 /* Now that we have the last section, push all the literal
9813 sections to the end. */
9814 xtensa_reorder_seg_list (literal_head
, last_sec
);
9816 /* Now perform the final error check. */
9817 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
9819 assert (new_count
== old_count
);
9823 /* Change the emit state (seg, subseg, and frag related stuff) to the
9824 correct location. Return a emit_state which can be passed to
9825 xtensa_restore_emit_state to return to current fragment. */
9828 xtensa_switch_to_literal_fragment (emit_state
*result
)
9830 if (directive_state
[directive_absolute_literals
])
9832 segT lit4_seg
= cache_literal_section (TRUE
);
9833 xtensa_switch_section_emit_state (result
, lit4_seg
, 0);
9836 xtensa_switch_to_non_abs_literal_fragment (result
);
9838 /* Do a 4-byte align here. */
9839 frag_align (2, 0, 0);
9840 record_alignment (now_seg
, 2);
9845 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
9847 static bfd_boolean recursive
= FALSE
;
9848 fragS
*pool_location
= get_literal_pool_location (now_seg
);
9850 bfd_boolean is_init
=
9851 (now_seg
&& !strcmp (segment_name (now_seg
), INIT_SECTION_NAME
));
9852 bfd_boolean is_fini
=
9853 (now_seg
&& !strcmp (segment_name (now_seg
), FINI_SECTION_NAME
));
9855 if (pool_location
== NULL
9856 && !use_literal_section
9858 && !is_init
&& ! is_fini
)
9860 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
9862 /* When we mark a literal pool location, we want to put a frag in
9863 the literal pool that points to it. But to do that, we want to
9864 switch_to_literal_fragment. But literal sections don't have
9865 literal pools, so their location is always null, so we would
9866 recurse forever. This is kind of hacky, but it works. */
9869 xtensa_mark_literal_pool_location ();
9873 lit_seg
= cache_literal_section (FALSE
);
9874 xtensa_switch_section_emit_state (result
, lit_seg
, 0);
9876 if (!use_literal_section
9877 && !is_init
&& !is_fini
9878 && get_literal_pool_location (now_seg
) != pool_location
)
9880 /* Close whatever frag is there. */
9881 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9882 xtensa_set_frag_assembly_state (frag_now
);
9883 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
9884 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9885 xtensa_set_frag_assembly_state (frag_now
);
9890 /* Call this function before emitting data into the literal section.
9891 This is a helper function for xtensa_switch_to_literal_fragment.
9892 This is similar to a .section new_now_seg subseg. */
9895 xtensa_switch_section_emit_state (emit_state
*state
,
9897 subsegT new_now_subseg
)
9899 state
->name
= now_seg
->name
;
9900 state
->now_seg
= now_seg
;
9901 state
->now_subseg
= now_subseg
;
9902 state
->generating_literals
= generating_literals
;
9903 generating_literals
++;
9904 subseg_set (new_now_seg
, new_now_subseg
);
9908 /* Use to restore the emitting into the normal place. */
9911 xtensa_restore_emit_state (emit_state
*state
)
9913 generating_literals
= state
->generating_literals
;
9914 subseg_set (state
->now_seg
, state
->now_subseg
);
9918 /* Predicate function used to look up a section in a particular group. */
9921 match_section_group (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
, void *inf
)
9923 const char *gname
= inf
;
9924 const char *group_name
= elf_group_name (sec
);
9926 return (group_name
== gname
9927 || (group_name
!= NULL
9929 && strcmp (group_name
, gname
) == 0));
9933 /* Get the literal section to be used for the current text section.
9934 The result may be cached in the default_lit_sections structure. */
9937 cache_literal_section (bfd_boolean use_abs_literals
)
9939 const char *text_name
, *group_name
= 0;
9940 char *base_name
, *name
, *suffix
;
9942 segT seg
, current_section
;
9944 bfd_boolean linkonce
= FALSE
;
9946 /* Save the current section/subsection. */
9947 current_section
= now_seg
;
9948 current_subsec
= now_subseg
;
9950 /* Clear the cached values if they are no longer valid. */
9951 if (now_seg
!= default_lit_sections
.current_text_seg
)
9953 default_lit_sections
.current_text_seg
= now_seg
;
9954 default_lit_sections
.lit_seg
= NULL
;
9955 default_lit_sections
.lit4_seg
= NULL
;
9958 /* Check if the literal section is already cached. */
9959 if (use_abs_literals
)
9960 pcached
= &default_lit_sections
.lit4_seg
;
9962 pcached
= &default_lit_sections
.lit_seg
;
9967 text_name
= default_lit_sections
.lit_prefix
;
9968 if (! text_name
|| ! *text_name
)
9970 text_name
= segment_name (current_section
);
9971 group_name
= elf_group_name (current_section
);
9972 linkonce
= (current_section
->flags
& SEC_LINK_ONCE
) != 0;
9975 base_name
= use_abs_literals
? ".lit4" : ".literal";
9978 name
= xmalloc (strlen (base_name
) + strlen (group_name
) + 2);
9979 sprintf (name
, "%s.%s", base_name
, group_name
);
9981 else if (strncmp (text_name
, ".gnu.linkonce.", linkonce_len
) == 0)
9983 suffix
= strchr (text_name
+ linkonce_len
, '.');
9985 name
= xmalloc (linkonce_len
+ strlen (base_name
) + 1
9986 + (suffix
? strlen (suffix
) : 0));
9987 strcpy (name
, ".gnu.linkonce");
9988 strcat (name
, base_name
);
9990 strcat (name
, suffix
);
9995 /* If the section name ends with ".text", then replace that suffix
9996 instead of appending an additional suffix. */
9997 size_t len
= strlen (text_name
);
9998 if (len
>= 5 && strcmp (text_name
+ len
- 5, ".text") == 0)
10001 name
= xmalloc (len
+ strlen (base_name
) + 1);
10002 strcpy (name
, text_name
);
10003 strcpy (name
+ len
, base_name
);
10006 /* Canonicalize section names to allow renaming literal sections.
10007 The group name, if any, came from the current text section and
10008 has already been canonicalized. */
10009 name
= tc_canonicalize_symbol_name (name
);
10011 seg
= bfd_get_section_by_name_if (stdoutput
, name
, match_section_group
,
10012 (void *) group_name
);
10017 seg
= subseg_force_new (name
, 0);
10019 if (! use_abs_literals
)
10021 /* Add the newly created literal segment to the list. */
10022 seg_list
*n
= (seg_list
*) xmalloc (sizeof (seg_list
));
10024 n
->next
= literal_head
->next
;
10025 literal_head
->next
= n
;
10028 flags
= (SEC_HAS_CONTENTS
| SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
10029 | (linkonce
? (SEC_LINK_ONCE
| SEC_LINK_DUPLICATES_DISCARD
) : 0)
10030 | (use_abs_literals
? SEC_DATA
: SEC_CODE
));
10032 elf_group_name (seg
) = group_name
;
10034 bfd_set_section_flags (stdoutput
, seg
, flags
);
10035 bfd_set_section_alignment (stdoutput
, seg
, 2);
10039 subseg_set (current_section
, current_subsec
);
10044 /* Property Tables Stuff. */
10046 #define XTENSA_INSN_SEC_NAME ".xt.insn"
10047 #define XTENSA_LIT_SEC_NAME ".xt.lit"
10048 #define XTENSA_PROP_SEC_NAME ".xt.prop"
10050 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
10051 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
10053 static bfd_boolean
get_frag_is_literal (const fragS
*);
10054 static void xtensa_create_property_segments
10055 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
10056 static void xtensa_create_xproperty_segments
10057 (frag_flags_fn
, const char *, xt_section_type
);
10058 static segment_info_type
*retrieve_segment_info (segT
);
10059 static bfd_boolean
section_has_property (segT
, frag_predicate
);
10060 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
10061 static void add_xt_block_frags
10062 (segT
, segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
10063 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
10064 static void xtensa_frag_flags_init (frag_flags
*);
10065 static void get_frag_property_flags (const fragS
*, frag_flags
*);
10066 static bfd_vma
frag_flags_to_number (const frag_flags
*);
10067 static void add_xt_prop_frags
10068 (segT
, segT
, xtensa_block_info
**, frag_flags_fn
);
10070 /* Set up property tables after relaxation. */
10073 xtensa_post_relax_hook (void)
10075 xtensa_move_seg_list_to_beginning (literal_head
);
10077 xtensa_find_unmarked_state_frags ();
10079 xtensa_create_property_segments (get_frag_is_literal
,
10081 XTENSA_LIT_SEC_NAME
,
10083 xtensa_create_xproperty_segments (get_frag_property_flags
,
10084 XTENSA_PROP_SEC_NAME
,
10087 if (warn_unaligned_branch_targets
)
10088 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
10089 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
10093 /* This function is only meaningful after xtensa_move_literals. */
10096 get_frag_is_literal (const fragS
*fragP
)
10098 assert (fragP
!= NULL
);
10099 return fragP
->tc_frag_data
.is_literal
;
10104 xtensa_create_property_segments (frag_predicate property_function
,
10105 frag_predicate end_property_function
,
10106 const char *section_name_base
,
10107 xt_section_type sec_type
)
10111 /* Walk over all of the current segments.
10112 Walk over each fragment
10113 For each non-empty fragment,
10114 Build a property record (append where possible). */
10116 for (seclist
= &stdoutput
->sections
;
10117 seclist
&& *seclist
;
10118 seclist
= &(*seclist
)->next
)
10120 segT sec
= *seclist
;
10123 flags
= bfd_get_section_flags (stdoutput
, sec
);
10124 if (flags
& SEC_DEBUGGING
)
10126 if (!(flags
& SEC_ALLOC
))
10129 if (section_has_property (sec
, property_function
))
10132 xtensa_get_property_section (sec
, section_name_base
);
10133 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10134 xtensa_block_info
**xt_blocks
=
10135 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10136 /* Walk over all of the frchains here and add new sections. */
10137 add_xt_block_frags (sec
, insn_sec
, xt_blocks
, property_function
,
10138 end_property_function
);
10142 /* Now we fill them out.... */
10144 for (seclist
= &stdoutput
->sections
;
10145 seclist
&& *seclist
;
10146 seclist
= &(*seclist
)->next
)
10148 segment_info_type
*seginfo
;
10149 xtensa_block_info
*block
;
10150 segT sec
= *seclist
;
10152 seginfo
= seg_info (sec
);
10153 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10157 xtensa_block_info
*cur_block
;
10158 /* This is a section with some data. */
10160 bfd_size_type rec_size
;
10162 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10165 rec_size
= num_recs
* 8;
10166 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10168 /* In order to make this work with the assembler, we have to
10169 build some frags and then build the "fixups" for it. It
10170 would be easier to just set the contents then set the
10175 /* Allocate a fragment and leak it. */
10177 bfd_size_type frag_size
;
10179 frchainS
*frchainP
;
10183 frag_size
= sizeof (fragS
) + rec_size
;
10184 fragP
= (fragS
*) xmalloc (frag_size
);
10186 memset (fragP
, 0, frag_size
);
10187 fragP
->fr_address
= 0;
10188 fragP
->fr_next
= NULL
;
10189 fragP
->fr_fix
= rec_size
;
10191 fragP
->fr_type
= rs_fill
;
10192 /* The rest are zeros. */
10194 frchainP
= seginfo
->frchainP
;
10195 frchainP
->frch_root
= fragP
;
10196 frchainP
->frch_last
= fragP
;
10198 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10199 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10201 seginfo
->fix_root
= fixes
;
10202 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10204 frag_data
= &fragP
->fr_literal
[0];
10205 for (i
= 0; i
< num_recs
; i
++)
10207 fixS
*fix
= &fixes
[i
];
10208 assert (cur_block
);
10210 /* Write the fixup. */
10211 if (i
!= num_recs
- 1)
10212 fix
->fx_next
= &fixes
[i
+ 1];
10214 fix
->fx_next
= NULL
;
10217 fix
->fx_frag
= fragP
;
10218 fix
->fx_where
= i
* 8;
10219 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10220 fix
->fx_offset
= cur_block
->offset
;
10221 fix
->fx_r_type
= BFD_RELOC_32
;
10222 fix
->fx_file
= "Internal Assembly";
10225 /* Write the length. */
10226 md_number_to_chars (&frag_data
[4 + 8 * i
],
10227 cur_block
->size
, 4);
10228 cur_block
= cur_block
->next
;
10237 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
10238 const char *section_name_base
,
10239 xt_section_type sec_type
)
10243 /* Walk over all of the current segments.
10244 Walk over each fragment.
10245 For each fragment that has instructions,
10246 build an instruction record (append where possible). */
10248 for (seclist
= &stdoutput
->sections
;
10249 seclist
&& *seclist
;
10250 seclist
= &(*seclist
)->next
)
10252 segT sec
= *seclist
;
10255 flags
= bfd_get_section_flags (stdoutput
, sec
);
10256 if ((flags
& SEC_DEBUGGING
)
10257 || !(flags
& SEC_ALLOC
)
10258 || (flags
& SEC_MERGE
))
10261 if (section_has_xproperty (sec
, flag_fn
))
10264 xtensa_get_property_section (sec
, section_name_base
);
10265 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10266 xtensa_block_info
**xt_blocks
=
10267 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10268 /* Walk over all of the frchains here and add new sections. */
10269 add_xt_prop_frags (sec
, insn_sec
, xt_blocks
, flag_fn
);
10273 /* Now we fill them out.... */
10275 for (seclist
= &stdoutput
->sections
;
10276 seclist
&& *seclist
;
10277 seclist
= &(*seclist
)->next
)
10279 segment_info_type
*seginfo
;
10280 xtensa_block_info
*block
;
10281 segT sec
= *seclist
;
10283 seginfo
= seg_info (sec
);
10284 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10288 xtensa_block_info
*cur_block
;
10289 /* This is a section with some data. */
10291 bfd_size_type rec_size
;
10293 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10296 rec_size
= num_recs
* (8 + 4);
10297 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10299 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
10301 /* In order to make this work with the assembler, we have to build
10302 some frags then build the "fixups" for it. It would be easier to
10303 just set the contents then set the arlents. */
10307 /* Allocate a fragment and (unfortunately) leak it. */
10309 bfd_size_type frag_size
;
10311 frchainS
*frchainP
;
10315 frag_size
= sizeof (fragS
) + rec_size
;
10316 fragP
= (fragS
*) xmalloc (frag_size
);
10318 memset (fragP
, 0, frag_size
);
10319 fragP
->fr_address
= 0;
10320 fragP
->fr_next
= NULL
;
10321 fragP
->fr_fix
= rec_size
;
10323 fragP
->fr_type
= rs_fill
;
10324 /* The rest are zeros. */
10326 frchainP
= seginfo
->frchainP
;
10327 frchainP
->frch_root
= fragP
;
10328 frchainP
->frch_last
= fragP
;
10330 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10331 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10333 seginfo
->fix_root
= fixes
;
10334 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10336 frag_data
= &fragP
->fr_literal
[0];
10337 for (i
= 0; i
< num_recs
; i
++)
10339 fixS
*fix
= &fixes
[i
];
10340 assert (cur_block
);
10342 /* Write the fixup. */
10343 if (i
!= num_recs
- 1)
10344 fix
->fx_next
= &fixes
[i
+ 1];
10346 fix
->fx_next
= NULL
;
10349 fix
->fx_frag
= fragP
;
10350 fix
->fx_where
= i
* (8 + 4);
10351 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10352 fix
->fx_offset
= cur_block
->offset
;
10353 fix
->fx_r_type
= BFD_RELOC_32
;
10354 fix
->fx_file
= "Internal Assembly";
10357 /* Write the length. */
10358 md_number_to_chars (&frag_data
[4 + (8+4) * i
],
10359 cur_block
->size
, 4);
10360 md_number_to_chars (&frag_data
[8 + (8+4) * i
],
10361 frag_flags_to_number (&cur_block
->flags
),
10363 cur_block
= cur_block
->next
;
10371 static segment_info_type
*
10372 retrieve_segment_info (segT seg
)
10374 segment_info_type
*seginfo
;
10375 seginfo
= (segment_info_type
*) bfd_get_section_userdata (stdoutput
, seg
);
10378 frchainS
*frchainP
;
10380 seginfo
= (segment_info_type
*) xmalloc (sizeof (*seginfo
));
10381 memset ((void *) seginfo
, 0, sizeof (*seginfo
));
10382 seginfo
->fix_root
= NULL
;
10383 seginfo
->fix_tail
= NULL
;
10384 seginfo
->bfd_section
= seg
;
10386 /* We will not be dealing with these, only our special ones. */
10387 bfd_set_section_userdata (stdoutput
, seg
, (void *) seginfo
);
10389 frchainP
= (frchainS
*) xmalloc (sizeof (frchainS
));
10390 frchainP
->frch_root
= NULL
;
10391 frchainP
->frch_last
= NULL
;
10392 frchainP
->frch_next
= NULL
;
10393 frchainP
->frch_subseg
= 0;
10394 frchainP
->fix_root
= NULL
;
10395 frchainP
->fix_tail
= NULL
;
10396 /* Do not init the objstack. */
10397 /* obstack_begin (&frchainP->frch_obstack, chunksize); */
10398 /* frchainP->frch_frag_now = fragP; */
10399 frchainP
->frch_frag_now
= NULL
;
10401 seginfo
->frchainP
= frchainP
;
10409 section_has_property (segT sec
, frag_predicate property_function
)
10411 segment_info_type
*seginfo
= seg_info (sec
);
10414 if (seginfo
&& seginfo
->frchainP
)
10416 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10418 if (property_function (fragP
)
10419 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10428 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
10430 segment_info_type
*seginfo
= seg_info (sec
);
10433 if (seginfo
&& seginfo
->frchainP
)
10435 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10437 frag_flags prop_flags
;
10438 property_function (fragP
, &prop_flags
);
10439 if (!xtensa_frag_flags_is_empty (&prop_flags
))
10447 /* Two types of block sections exist right now: literal and insns. */
10450 add_xt_block_frags (segT sec
,
10452 xtensa_block_info
**xt_block
,
10453 frag_predicate property_function
,
10454 frag_predicate end_property_function
)
10456 segment_info_type
*seg_info
;
10457 segment_info_type
*xt_seg_info
;
10458 bfd_vma seg_offset
;
10461 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
10462 seg_info
= retrieve_segment_info (sec
);
10464 /* Build it if needed. */
10465 while (*xt_block
!= NULL
)
10466 xt_block
= &(*xt_block
)->next
;
10467 /* We are either at NULL at the beginning or at the end. */
10469 /* Walk through the frags. */
10472 if (seg_info
->frchainP
)
10474 for (fragP
= seg_info
->frchainP
->frch_root
;
10476 fragP
= fragP
->fr_next
)
10478 if (property_function (fragP
)
10479 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10481 if (*xt_block
!= NULL
)
10483 if ((*xt_block
)->offset
+ (*xt_block
)->size
10484 == fragP
->fr_address
)
10485 (*xt_block
)->size
+= fragP
->fr_fix
;
10487 xt_block
= &((*xt_block
)->next
);
10489 if (*xt_block
== NULL
)
10491 xtensa_block_info
*new_block
= (xtensa_block_info
*)
10492 xmalloc (sizeof (xtensa_block_info
));
10493 new_block
->sec
= sec
;
10494 new_block
->offset
= fragP
->fr_address
;
10495 new_block
->size
= fragP
->fr_fix
;
10496 new_block
->next
= NULL
;
10497 xtensa_frag_flags_init (&new_block
->flags
);
10498 *xt_block
= new_block
;
10500 if (end_property_function
10501 && end_property_function (fragP
))
10503 xt_block
= &((*xt_block
)->next
);
10511 /* Break the encapsulation of add_xt_prop_frags here. */
10514 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
10516 if (prop_flags
->is_literal
10517 || prop_flags
->is_insn
10518 || prop_flags
->is_data
10519 || prop_flags
->is_unreachable
)
10526 xtensa_frag_flags_init (frag_flags
*prop_flags
)
10528 memset (prop_flags
, 0, sizeof (frag_flags
));
10533 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
10535 xtensa_frag_flags_init (prop_flags
);
10536 if (fragP
->tc_frag_data
.is_literal
)
10537 prop_flags
->is_literal
= TRUE
;
10538 if (fragP
->tc_frag_data
.is_unreachable
)
10539 prop_flags
->is_unreachable
= TRUE
;
10540 else if (fragP
->tc_frag_data
.is_insn
)
10542 prop_flags
->is_insn
= TRUE
;
10543 if (fragP
->tc_frag_data
.is_loop_target
)
10544 prop_flags
->insn
.is_loop_target
= TRUE
;
10545 if (fragP
->tc_frag_data
.is_branch_target
)
10546 prop_flags
->insn
.is_branch_target
= TRUE
;
10547 if (fragP
->tc_frag_data
.is_specific_opcode
10548 || fragP
->tc_frag_data
.is_no_transform
)
10549 prop_flags
->insn
.is_no_transform
= TRUE
;
10550 if (fragP
->tc_frag_data
.is_no_density
)
10551 prop_flags
->insn
.is_no_density
= TRUE
;
10552 if (fragP
->tc_frag_data
.use_absolute_literals
)
10553 prop_flags
->insn
.is_abslit
= TRUE
;
10555 if (fragP
->tc_frag_data
.is_align
)
10557 prop_flags
->is_align
= TRUE
;
10558 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
10559 if (xtensa_frag_flags_is_empty (prop_flags
))
10560 prop_flags
->is_data
= TRUE
;
10566 frag_flags_to_number (const frag_flags
*prop_flags
)
10569 if (prop_flags
->is_literal
)
10570 num
|= XTENSA_PROP_LITERAL
;
10571 if (prop_flags
->is_insn
)
10572 num
|= XTENSA_PROP_INSN
;
10573 if (prop_flags
->is_data
)
10574 num
|= XTENSA_PROP_DATA
;
10575 if (prop_flags
->is_unreachable
)
10576 num
|= XTENSA_PROP_UNREACHABLE
;
10577 if (prop_flags
->insn
.is_loop_target
)
10578 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
10579 if (prop_flags
->insn
.is_branch_target
)
10581 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
10582 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
10585 if (prop_flags
->insn
.is_no_density
)
10586 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
10587 if (prop_flags
->insn
.is_no_transform
)
10588 num
|= XTENSA_PROP_INSN_NO_TRANSFORM
;
10589 if (prop_flags
->insn
.is_no_reorder
)
10590 num
|= XTENSA_PROP_INSN_NO_REORDER
;
10591 if (prop_flags
->insn
.is_abslit
)
10592 num
|= XTENSA_PROP_INSN_ABSLIT
;
10594 if (prop_flags
->is_align
)
10596 num
|= XTENSA_PROP_ALIGN
;
10597 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
10605 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
10606 const frag_flags
*prop_flags_2
)
10608 /* Cannot combine with an end marker. */
10610 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
10612 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
10614 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
10617 if (prop_flags_1
->is_insn
)
10619 /* Properties of the beginning of the frag. */
10620 if (prop_flags_2
->insn
.is_loop_target
)
10622 if (prop_flags_2
->insn
.is_branch_target
)
10624 if (prop_flags_1
->insn
.is_no_density
!=
10625 prop_flags_2
->insn
.is_no_density
)
10627 if (prop_flags_1
->insn
.is_no_transform
!=
10628 prop_flags_2
->insn
.is_no_transform
)
10630 if (prop_flags_1
->insn
.is_no_reorder
!=
10631 prop_flags_2
->insn
.is_no_reorder
)
10633 if (prop_flags_1
->insn
.is_abslit
!=
10634 prop_flags_2
->insn
.is_abslit
)
10638 if (prop_flags_1
->is_align
)
10646 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
10649 unsigned align_bits
;
10651 if (!xt_block
->flags
.is_align
)
10652 return xt_block
->size
;
10654 end_addr
= xt_block
->offset
+ xt_block
->size
;
10655 align_bits
= xt_block
->flags
.alignment
;
10656 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
10657 return end_addr
- xt_block
->offset
;
10662 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
10663 const xtensa_block_info
*xt_block_2
)
10665 if (xt_block
->sec
!= xt_block_2
->sec
)
10667 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
10668 != xt_block_2
->offset
)
10671 if (xt_block_2
->size
== 0
10672 && (!xt_block_2
->flags
.is_unreachable
10673 || xt_block
->flags
.is_unreachable
))
10675 if (xt_block_2
->flags
.is_align
10676 && xt_block
->flags
.is_align
)
10678 /* Nothing needed. */
10679 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
10684 if (xt_block_2
->flags
.is_align
)
10686 /* Push alignment to previous entry. */
10687 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
10688 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10693 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
10694 &xt_block_2
->flags
))
10697 xt_block
->size
+= xt_block_2
->size
;
10699 if (xt_block_2
->flags
.is_align
)
10701 xt_block
->flags
.is_align
= TRUE
;
10702 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10710 add_xt_prop_frags (segT sec
,
10712 xtensa_block_info
**xt_block
,
10713 frag_flags_fn property_function
)
10715 segment_info_type
*seg_info
;
10716 segment_info_type
*xt_seg_info
;
10717 bfd_vma seg_offset
;
10720 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
10721 seg_info
= retrieve_segment_info (sec
);
10722 /* Build it if needed. */
10723 while (*xt_block
!= NULL
)
10725 xt_block
= &(*xt_block
)->next
;
10727 /* We are either at NULL at the beginning or at the end. */
10729 /* Walk through the frags. */
10732 if (seg_info
->frchainP
)
10734 for (fragP
= seg_info
->frchainP
->frch_root
; fragP
;
10735 fragP
= fragP
->fr_next
)
10737 xtensa_block_info tmp_block
;
10738 tmp_block
.sec
= sec
;
10739 tmp_block
.offset
= fragP
->fr_address
;
10740 tmp_block
.size
= fragP
->fr_fix
;
10741 tmp_block
.next
= NULL
;
10742 property_function (fragP
, &tmp_block
.flags
);
10744 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
10745 /* && fragP->fr_fix != 0) */
10747 if ((*xt_block
) == NULL
10748 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
10750 xtensa_block_info
*new_block
;
10751 if ((*xt_block
) != NULL
)
10752 xt_block
= &(*xt_block
)->next
;
10753 new_block
= (xtensa_block_info
*)
10754 xmalloc (sizeof (xtensa_block_info
));
10755 *new_block
= tmp_block
;
10756 *xt_block
= new_block
;
10764 /* op_placement_info_table */
10766 /* op_placement_info makes it easier to determine which
10767 ops can go in which slots. */
10770 init_op_placement_info_table (void)
10772 xtensa_isa isa
= xtensa_default_isa
;
10773 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
10774 xtensa_opcode opcode
;
10777 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
10779 op_placement_table
= (op_placement_info_table
)
10780 xmalloc (sizeof (op_placement_info
) * num_opcodes
);
10781 assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
10783 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
10785 op_placement_info
*opi
= &op_placement_table
[opcode
];
10786 /* FIXME: Make tinsn allocation dynamic. */
10787 if (xtensa_opcode_num_operands (isa
, opcode
) >= MAX_INSN_ARGS
)
10788 as_fatal (_("too many operands in instruction"));
10789 opi
->narrowest
= XTENSA_UNDEFINED
;
10790 opi
->narrowest_size
= 0x7F;
10791 opi
->narrowest_slot
= 0;
10793 opi
->num_formats
= 0;
10795 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
10797 opi
->slots
[fmt
] = 0;
10798 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
10800 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
10802 int fmt_length
= xtensa_format_length (isa
, fmt
);
10804 set_bit (fmt
, opi
->formats
);
10805 set_bit (slot
, opi
->slots
[fmt
]);
10806 if (fmt_length
< opi
->narrowest_size
10807 || (fmt_length
== opi
->narrowest_size
10808 && (xtensa_format_num_slots (isa
, fmt
)
10809 < xtensa_format_num_slots (isa
,
10812 opi
->narrowest
= fmt
;
10813 opi
->narrowest_size
= fmt_length
;
10814 opi
->narrowest_slot
= slot
;
10819 opi
->num_formats
++;
10822 xtensa_insnbuf_free (isa
, ibuf
);
10827 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
10829 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
10833 /* If the opcode is available in a single slot format, return its size. */
10836 xg_get_single_size (xtensa_opcode opcode
)
10838 return op_placement_table
[opcode
].narrowest_size
;
10842 static xtensa_format
10843 xg_get_single_format (xtensa_opcode opcode
)
10845 return op_placement_table
[opcode
].narrowest
;
10850 xg_get_single_slot (xtensa_opcode opcode
)
10852 return op_placement_table
[opcode
].narrowest_slot
;
10856 /* Instruction Stack Functions (from "xtensa-istack.h"). */
10859 istack_init (IStack
*stack
)
10861 memset (stack
, 0, sizeof (IStack
));
10867 istack_empty (IStack
*stack
)
10869 return (stack
->ninsn
== 0);
10874 istack_full (IStack
*stack
)
10876 return (stack
->ninsn
== MAX_ISTACK
);
10880 /* Return a pointer to the top IStack entry.
10881 It is an error to call this if istack_empty () is TRUE. */
10884 istack_top (IStack
*stack
)
10886 int rec
= stack
->ninsn
- 1;
10887 assert (!istack_empty (stack
));
10888 return &stack
->insn
[rec
];
10892 /* Add a new TInsn to an IStack.
10893 It is an error to call this if istack_full () is TRUE. */
10896 istack_push (IStack
*stack
, TInsn
*insn
)
10898 int rec
= stack
->ninsn
;
10899 assert (!istack_full (stack
));
10900 stack
->insn
[rec
] = *insn
;
10905 /* Clear space for the next TInsn on the IStack and return a pointer
10906 to it. It is an error to call this if istack_full () is TRUE. */
10909 istack_push_space (IStack
*stack
)
10911 int rec
= stack
->ninsn
;
10913 assert (!istack_full (stack
));
10914 insn
= &stack
->insn
[rec
];
10915 memset (insn
, 0, sizeof (TInsn
));
10921 /* Remove the last pushed instruction. It is an error to call this if
10922 istack_empty () returns TRUE. */
10925 istack_pop (IStack
*stack
)
10927 int rec
= stack
->ninsn
- 1;
10928 assert (!istack_empty (stack
));
10930 memset (&stack
->insn
[rec
], 0, sizeof (TInsn
));
10934 /* TInsn functions. */
10937 tinsn_init (TInsn
*dst
)
10939 memset (dst
, 0, sizeof (TInsn
));
10943 /* Get the ``num''th token of the TInsn.
10944 It is illegal to call this if num > insn->ntoks. */
10947 tinsn_get_tok (TInsn
*insn
, int num
)
10949 assert (num
< insn
->ntok
);
10950 return &insn
->tok
[num
];
10954 /* Return TRUE if ANY of the operands in the insn are symbolic. */
10957 tinsn_has_symbolic_operands (const TInsn
*insn
)
10960 int n
= insn
->ntok
;
10962 assert (insn
->insn_type
== ITYPE_INSN
);
10964 for (i
= 0; i
< n
; ++i
)
10966 switch (insn
->tok
[i
].X_op
)
10980 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
10982 xtensa_isa isa
= xtensa_default_isa
;
10984 int n
= insn
->ntok
;
10986 assert (insn
->insn_type
== ITYPE_INSN
);
10988 for (i
= 0; i
< n
; ++i
)
10990 switch (insn
->tok
[i
].X_op
)
10998 /* Errors for these types are caught later. */
11003 /* Symbolic immediates are only allowed on the last immediate
11004 operand. At this time, CONST16 is the only opcode where we
11005 support non-PC-relative relocations. */
11006 if (i
!= get_relaxable_immed (insn
->opcode
)
11007 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
11008 && insn
->opcode
!= xtensa_const16_opcode
))
11010 as_bad (_("invalid symbolic operand"));
11019 /* For assembly code with complex expressions (e.g. subtraction),
11020 we have to build them in the literal pool so that
11021 their results are calculated correctly after relaxation.
11022 The relaxation only handles expressions that
11023 boil down to SYMBOL + OFFSET. */
11026 tinsn_has_complex_operands (const TInsn
*insn
)
11029 int n
= insn
->ntok
;
11030 assert (insn
->insn_type
== ITYPE_INSN
);
11031 for (i
= 0; i
< n
; ++i
)
11033 switch (insn
->tok
[i
].X_op
)
11049 /* Encode a TInsn opcode and its constant operands into slotbuf.
11050 Return TRUE if there is a symbol in the immediate field. This
11051 function assumes that:
11052 1) The number of operands are correct.
11053 2) The insn_type is ITYPE_INSN.
11054 3) The opcode can be encoded in the specified format and slot.
11055 4) Operands are either O_constant or O_symbol, and all constants fit. */
11058 tinsn_to_slotbuf (xtensa_format fmt
,
11061 xtensa_insnbuf slotbuf
)
11063 xtensa_isa isa
= xtensa_default_isa
;
11064 xtensa_opcode opcode
= tinsn
->opcode
;
11065 bfd_boolean has_fixup
= FALSE
;
11066 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11069 assert (tinsn
->insn_type
== ITYPE_INSN
);
11070 if (noperands
!= tinsn
->ntok
)
11071 as_fatal (_("operand number mismatch"));
11073 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
11075 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
11076 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
11080 for (i
= 0; i
< noperands
; i
++)
11082 expressionS
*expr
= &tinsn
->tok
[i
];
11088 switch (expr
->X_op
)
11091 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11093 /* The register number has already been checked in
11094 expression_maybe_register, so we don't need to check here. */
11095 opnd_value
= expr
->X_add_number
;
11096 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11097 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
11100 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
11104 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11106 as_where (&file_name
, &line
);
11107 /* It is a constant and we called this function
11108 then we have to try to fit it. */
11109 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
11110 expr
->X_add_number
, file_name
, line
);
11123 /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded
11124 into a multi-slot instruction, fill the other slots with NOPs.
11125 Return TRUE if there is a symbol in the immediate field. See also the
11126 assumptions listed for tinsn_to_slotbuf. */
11129 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
11131 static xtensa_insnbuf slotbuf
= 0;
11132 static vliw_insn vinsn
;
11133 xtensa_isa isa
= xtensa_default_isa
;
11134 bfd_boolean has_fixup
= FALSE
;
11139 slotbuf
= xtensa_insnbuf_alloc (isa
);
11140 xg_init_vinsn (&vinsn
);
11143 xg_clear_vinsn (&vinsn
);
11145 bundle_tinsn (tinsn
, &vinsn
);
11147 xtensa_format_encode (isa
, vinsn
.format
, insnbuf
);
11149 for (i
= 0; i
< vinsn
.num_slots
; i
++)
11151 /* Only one slot may have a fix-up because the rest contains NOPs. */
11153 tinsn_to_slotbuf (vinsn
.format
, i
, &vinsn
.slots
[i
], vinsn
.slotbuf
[i
]);
11154 xtensa_format_set_slot (isa
, vinsn
.format
, i
, insnbuf
, vinsn
.slotbuf
[i
]);
11161 /* Check the instruction arguments. Return TRUE on failure. */
11164 tinsn_check_arguments (const TInsn
*insn
)
11166 xtensa_isa isa
= xtensa_default_isa
;
11167 xtensa_opcode opcode
= insn
->opcode
;
11169 if (opcode
== XTENSA_UNDEFINED
)
11171 as_bad (_("invalid opcode"));
11175 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
11177 as_bad (_("too few operands"));
11181 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
11183 as_bad (_("too many operands"));
11190 /* Load an instruction from its encoded form. */
11193 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
11197 xg_init_vinsn (&vinsn
);
11198 vinsn_from_chars (&vinsn
, f
);
11200 *tinsn
= vinsn
.slots
[slot
];
11201 xg_free_vinsn (&vinsn
);
11206 tinsn_from_insnbuf (TInsn
*tinsn
,
11207 xtensa_insnbuf slotbuf
,
11212 xtensa_isa isa
= xtensa_default_isa
;
11214 /* Find the immed. */
11215 tinsn_init (tinsn
);
11216 tinsn
->insn_type
= ITYPE_INSN
;
11217 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
11218 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
11219 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
11220 for (i
= 0; i
< tinsn
->ntok
; i
++)
11222 set_expr_const (&tinsn
->tok
[i
],
11223 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
11224 tinsn
->opcode
, i
));
11229 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
11232 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
11234 xtensa_opcode opcode
= tinsn
->opcode
;
11237 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
11239 opnum
= get_relaxable_immed (opcode
);
11240 assert (opnum
>= 0);
11241 set_expr_symbol_offset (&tinsn
->tok
[opnum
],
11242 fragP
->tc_frag_data
.slot_symbols
[slot
],
11243 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11249 get_num_stack_text_bytes (IStack
*istack
)
11252 int text_bytes
= 0;
11254 for (i
= 0; i
< istack
->ninsn
; i
++)
11256 TInsn
*tinsn
= &istack
->insn
[i
];
11257 if (tinsn
->insn_type
== ITYPE_INSN
)
11258 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
11265 get_num_stack_literal_bytes (IStack
*istack
)
11270 for (i
= 0; i
< istack
->ninsn
; i
++)
11272 TInsn
*tinsn
= &istack
->insn
[i
];
11273 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
11280 /* vliw_insn functions. */
11283 xg_init_vinsn (vliw_insn
*v
)
11286 xtensa_isa isa
= xtensa_default_isa
;
11288 xg_clear_vinsn (v
);
11290 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
11291 if (v
->insnbuf
== NULL
)
11292 as_fatal (_("out of memory"));
11294 for (i
= 0; i
< MAX_SLOTS
; i
++)
11296 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
11297 if (v
->slotbuf
[i
] == NULL
)
11298 as_fatal (_("out of memory"));
11304 xg_clear_vinsn (vliw_insn
*v
)
11308 memset (v
, 0, offsetof (vliw_insn
, insnbuf
));
11310 v
->format
= XTENSA_UNDEFINED
;
11312 v
->inside_bundle
= FALSE
;
11314 if (xt_saved_debug_type
!= DEBUG_NONE
)
11315 debug_type
= xt_saved_debug_type
;
11317 for (i
= 0; i
< MAX_SLOTS
; i
++)
11318 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
11323 vinsn_has_specific_opcodes (vliw_insn
*v
)
11327 for (i
= 0; i
< v
->num_slots
; i
++)
11329 if (v
->slots
[i
].is_specific_opcode
)
11337 xg_free_vinsn (vliw_insn
*v
)
11340 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
11341 for (i
= 0; i
< MAX_SLOTS
; i
++)
11342 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
11346 /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic
11347 operands. See also the assumptions listed for tinsn_to_slotbuf. */
11350 vinsn_to_insnbuf (vliw_insn
*vinsn
,
11353 bfd_boolean record_fixup
)
11355 xtensa_isa isa
= xtensa_default_isa
;
11356 xtensa_format fmt
= vinsn
->format
;
11357 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
11359 bfd_boolean has_fixup
= FALSE
;
11361 xtensa_format_encode (isa
, fmt
, insnbuf
);
11363 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
11365 TInsn
*tinsn
= &vinsn
->slots
[slot
];
11366 bfd_boolean tinsn_has_fixup
=
11367 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
11368 vinsn
->slotbuf
[slot
]);
11370 xtensa_format_set_slot (isa
, fmt
, slot
,
11371 insnbuf
, vinsn
->slotbuf
[slot
]);
11372 if (tinsn_has_fixup
)
11375 xtensa_opcode opcode
= tinsn
->opcode
;
11376 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11379 for (i
= 0; i
< noperands
; i
++)
11381 expressionS
* expr
= &tinsn
->tok
[i
];
11382 switch (expr
->X_op
)
11387 if (get_relaxable_immed (opcode
) == i
)
11389 /* Add a fix record for the instruction, except if this
11390 function is being called prior to relaxation, i.e.,
11391 if record_fixup is false, and the instruction might
11392 be relaxed later. */
11394 || tinsn
->is_specific_opcode
11395 || !xg_is_relaxable_insn (tinsn
, 0))
11397 xg_add_opcode_fix (tinsn
, i
, fmt
, slot
, expr
, fragP
,
11398 frag_offset
- fragP
->fr_literal
);
11402 if (expr
->X_op
!= O_symbol
)
11403 as_bad (_("invalid operand"));
11404 tinsn
->symbol
= expr
->X_add_symbol
;
11405 tinsn
->offset
= expr
->X_add_number
;
11409 as_bad (_("symbolic operand not allowed"));
11417 as_bad (_("expression too complex"));
11429 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
11431 static xtensa_insnbuf insnbuf
= NULL
;
11432 static xtensa_insnbuf slotbuf
= NULL
;
11435 xtensa_isa isa
= xtensa_default_isa
;
11439 insnbuf
= xtensa_insnbuf_alloc (isa
);
11440 slotbuf
= xtensa_insnbuf_alloc (isa
);
11443 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) f
, 0);
11444 fmt
= xtensa_format_decode (isa
, insnbuf
);
11445 if (fmt
== XTENSA_UNDEFINED
)
11446 as_fatal (_("cannot decode instruction format"));
11447 vinsn
->format
= fmt
;
11448 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
11450 for (i
= 0; i
< vinsn
->num_slots
; i
++)
11452 TInsn
*tinsn
= &vinsn
->slots
[i
];
11453 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
11454 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
11459 /* Expression utilities. */
11461 /* Return TRUE if the expression is an integer constant. */
11464 expr_is_const (const expressionS
*s
)
11466 return (s
->X_op
== O_constant
);
11470 /* Get the expression constant.
11471 Calling this is illegal if expr_is_const () returns TRUE. */
11474 get_expr_const (const expressionS
*s
)
11476 assert (expr_is_const (s
));
11477 return s
->X_add_number
;
11481 /* Set the expression to a constant value. */
11484 set_expr_const (expressionS
*s
, offsetT val
)
11486 s
->X_op
= O_constant
;
11487 s
->X_add_number
= val
;
11488 s
->X_add_symbol
= NULL
;
11489 s
->X_op_symbol
= NULL
;
11494 expr_is_register (const expressionS
*s
)
11496 return (s
->X_op
== O_register
);
11500 /* Get the expression constant.
11501 Calling this is illegal if expr_is_const () returns TRUE. */
11504 get_expr_register (const expressionS
*s
)
11506 assert (expr_is_register (s
));
11507 return s
->X_add_number
;
11511 /* Set the expression to a symbol + constant offset. */
11514 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
11516 s
->X_op
= O_symbol
;
11517 s
->X_add_symbol
= sym
;
11518 s
->X_op_symbol
= NULL
; /* unused */
11519 s
->X_add_number
= offset
;
11523 /* Return TRUE if the two expressions are equal. */
11526 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
11528 if (s1
->X_op
!= s2
->X_op
)
11530 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
11532 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
11534 if (s1
->X_add_number
!= s2
->X_add_number
)
11541 copy_expr (expressionS
*dst
, const expressionS
*src
)
11543 memcpy (dst
, src
, sizeof (expressionS
));
11547 /* Support for the "--rename-section" option. */
11549 struct rename_section_struct
11553 struct rename_section_struct
*next
;
11556 static struct rename_section_struct
*section_rename
;
11559 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
11560 entries to the section_rename list. Note: Specifying multiple
11561 renamings separated by colons is not documented and is retained only
11562 for backward compatibility. */
11565 build_section_rename (const char *arg
)
11567 struct rename_section_struct
*r
;
11568 char *this_arg
= NULL
;
11569 char *next_arg
= NULL
;
11571 for (this_arg
= xstrdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
11573 char *old_name
, *new_name
;
11577 next_arg
= strchr (this_arg
, ':');
11585 old_name
= this_arg
;
11586 new_name
= strchr (this_arg
, '=');
11588 if (*old_name
== '\0')
11590 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
11593 if (!new_name
|| new_name
[1] == '\0')
11595 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
11602 /* Check for invalid section renaming. */
11603 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11605 if (strcmp (r
->old_name
, old_name
) == 0)
11606 as_bad (_("section %s renamed multiple times"), old_name
);
11607 if (strcmp (r
->new_name
, new_name
) == 0)
11608 as_bad (_("multiple sections remapped to output section %s"),
11613 r
= (struct rename_section_struct
*)
11614 xmalloc (sizeof (struct rename_section_struct
));
11615 r
->old_name
= xstrdup (old_name
);
11616 r
->new_name
= xstrdup (new_name
);
11617 r
->next
= section_rename
;
11618 section_rename
= r
;
11624 xtensa_section_rename (char *name
)
11626 struct rename_section_struct
*r
= section_rename
;
11628 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11630 if (strcmp (r
->old_name
, name
) == 0)
11631 return r
->new_name
;