1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
24 #include "safe-ctype.h"
25 #include "tc-xtensa.h"
27 #include "xtensa-relax.h"
28 #include "dwarf2dbg.h"
29 #include "xtensa-istack.h"
30 #include "struc-symbol.h"
31 #include "xtensa-config.h"
33 /* Provide default values for new configuration settings. */
39 #define uint32 unsigned int
42 #define int32 signed int
47 Naming conventions (used somewhat inconsistently):
48 The xtensa_ functions are exported
49 The xg_ functions are internal
51 We also have a couple of different extensibility mechanisms.
52 1) The idiom replacement:
53 This is used when a line is first parsed to
54 replace an instruction pattern with another instruction
55 It is currently limited to replacements of instructions
56 with constant operands.
57 2) The xtensa-relax.c mechanism that has stronger instruction
58 replacement patterns. When an instruction's immediate field
59 does not fit the next instruction sequence is attempted.
60 In addition, "narrow" opcodes are supported this way. */
63 /* Define characters with special meanings to GAS. */
64 const char comment_chars
[] = "#";
65 const char line_comment_chars
[] = "#";
66 const char line_separator_chars
[] = ";";
67 const char EXP_CHARS
[] = "eE";
68 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
71 /* Flags to indicate whether the hardware supports the density and
72 absolute literals options. */
74 bfd_boolean density_supported
= XCHAL_HAVE_DENSITY
;
75 bfd_boolean absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
77 /* Maximum width we would pad an unreachable frag to get alignment. */
78 #define UNREACHABLE_MAX_WIDTH 8
80 static vliw_insn cur_vinsn
;
82 unsigned xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
84 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
86 /* Some functions are only valid in the front end. This variable
87 allows us to assert that we haven't crossed over into the
89 static bfd_boolean past_xtensa_end
= FALSE
;
91 /* Flags for properties of the last instruction in a segment. */
92 #define FLAG_IS_A0_WRITER 0x1
93 #define FLAG_IS_BAD_LOOPEND 0x2
96 /* We define a special segment names ".literal" to place literals
97 into. The .fini and .init sections are special because they
98 contain code that is moved together by the linker. We give them
99 their own special .fini.literal and .init.literal sections. */
101 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
102 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
103 #define INIT_SECTION_NAME xtensa_section_rename (".init")
104 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
107 /* This type is used for the directive_stack to keep track of the
108 state of the literal collection pools. If lit_prefix is set, it is
109 used to determine the literal section names; otherwise, the literal
110 sections are determined based on the current text section. The
111 lit_seg and lit4_seg fields cache these literal sections, with the
112 current_text_seg field used a tag to indicate whether the cached
115 typedef struct lit_state_struct
118 segT current_text_seg
;
123 static lit_state default_lit_sections
;
126 /* We keep a list of literal segments. The seg_list type is the node
127 for this list. The literal_head pointer is the head of the list,
128 with the literal_head_h dummy node at the start. */
130 typedef struct seg_list_struct
132 struct seg_list_struct
*next
;
136 static seg_list literal_head_h
;
137 static seg_list
*literal_head
= &literal_head_h
;
140 /* Lists of symbols. We keep a list of symbols that label the current
141 instruction, so that we can adjust the symbols when inserting alignment
142 for various instructions. We also keep a list of all the symbols on
143 literals, so that we can fix up those symbols when the literals are
144 later moved into the text sections. */
146 typedef struct sym_list_struct
148 struct sym_list_struct
*next
;
152 static sym_list
*insn_labels
= NULL
;
153 static sym_list
*free_insn_labels
= NULL
;
154 static sym_list
*saved_insn_labels
= NULL
;
156 static sym_list
*literal_syms
;
159 /* Flags to determine whether to prefer const16 or l32r
160 if both options are available. */
161 int prefer_const16
= 0;
164 /* Global flag to indicate when we are emitting literals. */
165 int generating_literals
= 0;
167 /* The following PROPERTY table definitions are copied from
168 <elf/xtensa.h> and must be kept in sync with the code there. */
170 /* Flags in the property tables to specify whether blocks of memory
171 are literals, instructions, data, or unreachable. For
172 instructions, blocks that begin loop targets and branch targets are
173 designated. Blocks that do not allow density, instruction
174 reordering or transformation are also specified. Finally, for
175 branch targets, branch target alignment priority is included.
176 Alignment of the next block is specified in the current block
177 and the size of the current block does not include any fill required
178 to align to the next block. */
180 #define XTENSA_PROP_LITERAL 0x00000001
181 #define XTENSA_PROP_INSN 0x00000002
182 #define XTENSA_PROP_DATA 0x00000004
183 #define XTENSA_PROP_UNREACHABLE 0x00000008
184 /* Instruction only properties at beginning of code. */
185 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
186 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
187 /* Instruction only properties about code. */
188 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
189 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
190 /* Historically, NO_TRANSFORM was a property of instructions,
191 but it should apply to literals under certain circumstances. */
192 #define XTENSA_PROP_NO_TRANSFORM 0x00000100
194 /* Branch target alignment information. This transmits information
195 to the linker optimization about the priority of aligning a
196 particular block for branch target alignment: None, low priority,
197 high priority, or required. These only need to be checked in
198 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
201 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
202 case XTENSA_PROP_BT_ALIGN_NONE:
203 case XTENSA_PROP_BT_ALIGN_LOW:
204 case XTENSA_PROP_BT_ALIGN_HIGH:
205 case XTENSA_PROP_BT_ALIGN_REQUIRE:
207 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
209 /* No branch target alignment. */
210 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
211 /* Low priority branch target alignment. */
212 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
213 /* High priority branch target alignment. */
214 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
215 /* Required branch target alignment. */
216 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
218 #define GET_XTENSA_PROP_BT_ALIGN(flag) \
219 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
220 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
221 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
222 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
225 /* Alignment is specified in the block BEFORE the one that needs
226 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
227 get the required alignment specified as a power of 2. Use
228 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
229 alignment. Be careful of side effects since the SET will evaluate
230 flags twice. Also, note that the SIZE of a block in the property
231 table does not include the alignment size, so the alignment fill
232 must be calculated to determine if two blocks are contiguous.
233 TEXT_ALIGN is not currently implemented but is a placeholder for a
234 possible future implementation. */
236 #define XTENSA_PROP_ALIGN 0x00000800
238 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
240 #define GET_XTENSA_PROP_ALIGNMENT(flag) \
241 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
242 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
243 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
244 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
246 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
249 /* Structure for saving instruction and alignment per-fragment data
250 that will be written to the object file. This structure is
251 equivalent to the actual data that will be written out to the file
252 but is easier to use. We provide a conversion to file flags
253 in frag_flags_to_number. */
255 typedef struct frag_flags_struct frag_flags
;
257 struct frag_flags_struct
259 /* is_literal should only be used after xtensa_move_literals.
260 If you need to check if you are generating a literal fragment,
261 then use the generating_literals global. */
263 unsigned is_literal
: 1;
264 unsigned is_insn
: 1;
265 unsigned is_data
: 1;
266 unsigned is_unreachable
: 1;
268 /* is_specific_opcode implies no_transform. */
269 unsigned is_no_transform
: 1;
273 unsigned is_loop_target
: 1;
274 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
275 unsigned bt_align_priority
: 2;
277 unsigned is_no_density
: 1;
278 /* no_longcalls flag does not need to be placed in the object file. */
280 unsigned is_no_reorder
: 1;
282 /* Uses absolute literal addressing for l32r. */
283 unsigned is_abslit
: 1;
285 unsigned is_align
: 1;
286 unsigned alignment
: 5;
290 /* Structure for saving information about a block of property data
291 for frags that have the same flags. */
292 struct xtensa_block_info_struct
298 struct xtensa_block_info_struct
*next
;
302 /* Structure for saving the current state before emitting literals. */
303 typedef struct emit_state_struct
308 int generating_literals
;
312 /* Opcode placement information */
314 typedef unsigned long long bitfield
;
315 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
316 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
317 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
319 #define MAX_FORMATS 32
321 typedef struct op_placement_info_struct
324 /* A number describing how restrictive the issue is for this
325 opcode. For example, an opcode that fits lots of different
326 formats has a high freedom, as does an opcode that fits
327 only one format but many slots in that format. The most
328 restrictive is the opcode that fits only one slot in one
331 xtensa_format narrowest
;
335 /* formats is a bitfield with the Nth bit set
336 if the opcode fits in the Nth xtensa_format. */
339 /* slots[N]'s Mth bit is set if the op fits in the
340 Mth slot of the Nth xtensa_format. */
341 bitfield slots
[MAX_FORMATS
];
343 /* A count of the number of slots in a given format
344 an op can fit (i.e., the bitcount of the slot field above). */
345 char slots_in_format
[MAX_FORMATS
];
347 } op_placement_info
, *op_placement_info_table
;
349 op_placement_info_table op_placement_table
;
352 /* Extra expression types. */
354 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
355 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
356 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
357 #define O_pcrel O_md4 /* value is a PC-relative offset */
359 struct suffix_reloc_map
363 bfd_reloc_code_real_type reloc
;
364 unsigned char operator;
367 #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op }
369 static struct suffix_reloc_map suffix_relocs
[] =
371 SUFFIX_MAP ("l", BFD_RELOC_LO16
, O_lo16
),
372 SUFFIX_MAP ("h", BFD_RELOC_HI16
, O_hi16
),
373 SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT
, O_pltrel
),
374 SUFFIX_MAP ("pcrel", BFD_RELOC_32_PCREL
, O_pcrel
),
375 { (char *) 0, 0, BFD_RELOC_UNUSED
, 0 }
389 directive_literal_prefix
,
391 directive_absolute_literals
,
392 directive_last_directive
398 bfd_boolean can_be_negated
;
401 const directive_infoS directive_info
[] =
404 { "literal", FALSE
},
406 { "transform", TRUE
},
407 { "freeregs", FALSE
},
408 { "longcalls", TRUE
},
409 { "literal_prefix", FALSE
},
410 { "schedule", TRUE
},
411 { "absolute-literals", TRUE
}
414 bfd_boolean directive_state
[] =
418 #if !XCHAL_HAVE_DENSITY
423 TRUE
, /* transform */
424 FALSE
, /* freeregs */
425 FALSE
, /* longcalls */
426 FALSE
, /* literal_prefix */
427 FALSE
, /* schedule */
428 #if XSHAL_USE_ABSOLUTE_LITERALS
429 TRUE
/* absolute_literals */
431 FALSE
/* absolute_literals */
436 /* Directive functions. */
438 static void xtensa_begin_directive (int);
439 static void xtensa_end_directive (int);
440 static void xtensa_literal_prefix (void);
441 static void xtensa_literal_position (int);
442 static void xtensa_literal_pseudo (int);
443 static void xtensa_frequency_pseudo (int);
444 static void xtensa_elf_cons (int);
446 /* Parsing and Idiom Translation. */
448 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
450 /* Various Other Internal Functions. */
452 extern bfd_boolean
xg_is_single_relaxable_insn (TInsn
*, TInsn
*, bfd_boolean
);
453 static bfd_boolean
xg_build_to_insn (TInsn
*, TInsn
*, BuildInstr
*);
454 static void xtensa_mark_literal_pool_location (void);
455 static addressT
get_expanded_loop_offset (xtensa_opcode
);
456 static fragS
*get_literal_pool_location (segT
);
457 static void set_literal_pool_location (segT
, fragS
*);
458 static void xtensa_set_frag_assembly_state (fragS
*);
459 static void finish_vinsn (vliw_insn
*);
460 static bfd_boolean
emit_single_op (TInsn
*);
461 static int total_frag_text_expansion (fragS
*);
463 /* Alignment Functions. */
465 static int get_text_align_power (unsigned);
466 static int get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
467 static int branch_align_power (segT
);
469 /* Helpers for xtensa_relax_frag(). */
471 static long relax_frag_add_nop (fragS
*);
473 /* Accessors for additional per-subsegment information. */
475 static unsigned get_last_insn_flags (segT
, subsegT
);
476 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
477 static float get_subseg_total_freq (segT
, subsegT
);
478 static float get_subseg_target_freq (segT
, subsegT
);
479 static void set_subseg_freq (segT
, subsegT
, float, float);
481 /* Segment list functions. */
483 static void xtensa_move_literals (void);
484 static void xtensa_reorder_segments (void);
485 static void xtensa_switch_to_literal_fragment (emit_state
*);
486 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
487 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
488 static void xtensa_restore_emit_state (emit_state
*);
489 static segT
cache_literal_section (bfd_boolean
);
491 /* Import from elf32-xtensa.c in BFD library. */
493 extern asection
*xtensa_get_property_section (asection
*, const char *);
495 /* op_placement_info functions. */
497 static void init_op_placement_info_table (void);
498 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
499 static int xg_get_single_size (xtensa_opcode
);
500 static xtensa_format
xg_get_single_format (xtensa_opcode
);
501 static int xg_get_single_slot (xtensa_opcode
);
503 /* TInsn and IStack functions. */
505 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
506 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
507 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
508 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
509 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
510 static void tinsn_from_chars (TInsn
*, char *, int);
511 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
512 static int get_num_stack_text_bytes (IStack
*);
513 static int get_num_stack_literal_bytes (IStack
*);
515 /* vliw_insn functions. */
517 static void xg_init_vinsn (vliw_insn
*);
518 static void xg_clear_vinsn (vliw_insn
*);
519 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
520 static void xg_free_vinsn (vliw_insn
*);
521 static bfd_boolean vinsn_to_insnbuf
522 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
523 static void vinsn_from_chars (vliw_insn
*, char *);
525 /* Expression Utilities. */
527 bfd_boolean
expr_is_const (const expressionS
*);
528 offsetT
get_expr_const (const expressionS
*);
529 void set_expr_const (expressionS
*, offsetT
);
530 bfd_boolean
expr_is_register (const expressionS
*);
531 offsetT
get_expr_register (const expressionS
*);
532 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
533 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
534 static void copy_expr (expressionS
*, const expressionS
*);
536 /* Section renaming. */
538 static void build_section_rename (const char *);
541 /* ISA imported from bfd. */
542 extern xtensa_isa xtensa_default_isa
;
544 extern int target_big_endian
;
546 static xtensa_opcode xtensa_addi_opcode
;
547 static xtensa_opcode xtensa_addmi_opcode
;
548 static xtensa_opcode xtensa_call0_opcode
;
549 static xtensa_opcode xtensa_call4_opcode
;
550 static xtensa_opcode xtensa_call8_opcode
;
551 static xtensa_opcode xtensa_call12_opcode
;
552 static xtensa_opcode xtensa_callx0_opcode
;
553 static xtensa_opcode xtensa_callx4_opcode
;
554 static xtensa_opcode xtensa_callx8_opcode
;
555 static xtensa_opcode xtensa_callx12_opcode
;
556 static xtensa_opcode xtensa_const16_opcode
;
557 static xtensa_opcode xtensa_entry_opcode
;
558 static xtensa_opcode xtensa_extui_opcode
;
559 static xtensa_opcode xtensa_movi_opcode
;
560 static xtensa_opcode xtensa_movi_n_opcode
;
561 static xtensa_opcode xtensa_isync_opcode
;
562 static xtensa_opcode xtensa_jx_opcode
;
563 static xtensa_opcode xtensa_l32r_opcode
;
564 static xtensa_opcode xtensa_loop_opcode
;
565 static xtensa_opcode xtensa_loopnez_opcode
;
566 static xtensa_opcode xtensa_loopgtz_opcode
;
567 static xtensa_opcode xtensa_nop_opcode
;
568 static xtensa_opcode xtensa_nop_n_opcode
;
569 static xtensa_opcode xtensa_or_opcode
;
570 static xtensa_opcode xtensa_ret_opcode
;
571 static xtensa_opcode xtensa_ret_n_opcode
;
572 static xtensa_opcode xtensa_retw_opcode
;
573 static xtensa_opcode xtensa_retw_n_opcode
;
574 static xtensa_opcode xtensa_rsr_lcount_opcode
;
575 static xtensa_opcode xtensa_waiti_opcode
;
578 /* Command-line Options. */
580 bfd_boolean use_literal_section
= TRUE
;
581 static bfd_boolean align_targets
= TRUE
;
582 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
583 static bfd_boolean has_a0_b_retw
= FALSE
;
584 static bfd_boolean workaround_a0_b_retw
= FALSE
;
585 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
586 static bfd_boolean workaround_short_loop
= FALSE
;
587 static bfd_boolean maybe_has_short_loop
= FALSE
;
588 static bfd_boolean workaround_close_loop_end
= FALSE
;
589 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
590 static bfd_boolean enforce_three_byte_loop_align
= FALSE
;
592 /* When workaround_short_loops is TRUE, all loops with early exits must
593 have at least 3 instructions. workaround_all_short_loops is a modifier
594 to the workaround_short_loop flag. In addition to the
595 workaround_short_loop actions, all straightline loopgtz and loopnez
596 must have at least 3 instructions. */
598 static bfd_boolean workaround_all_short_loops
= FALSE
;
602 xtensa_setup_hw_workarounds (int earliest
, int latest
)
604 if (earliest
> latest
)
605 as_fatal (_("illegal range of target hardware versions"));
607 /* Enable all workarounds for pre-T1050.0 hardware. */
608 if (earliest
< 105000 || latest
< 105000)
610 workaround_a0_b_retw
|= TRUE
;
611 workaround_b_j_loop_end
|= TRUE
;
612 workaround_short_loop
|= TRUE
;
613 workaround_close_loop_end
|= TRUE
;
614 workaround_all_short_loops
|= TRUE
;
615 enforce_three_byte_loop_align
= TRUE
;
622 option_density
= OPTION_MD_BASE
,
629 option_no_link_relax
,
637 option_text_section_literals
,
638 option_no_text_section_literals
,
640 option_absolute_literals
,
641 option_no_absolute_literals
,
643 option_align_targets
,
644 option_no_align_targets
,
646 option_warn_unaligned_targets
,
651 option_workaround_a0_b_retw
,
652 option_no_workaround_a0_b_retw
,
654 option_workaround_b_j_loop_end
,
655 option_no_workaround_b_j_loop_end
,
657 option_workaround_short_loop
,
658 option_no_workaround_short_loop
,
660 option_workaround_all_short_loops
,
661 option_no_workaround_all_short_loops
,
663 option_workaround_close_loop_end
,
664 option_no_workaround_close_loop_end
,
666 option_no_workarounds
,
668 option_rename_section_name
,
671 option_prefer_const16
,
673 option_target_hardware
676 const char *md_shortopts
= "";
678 struct option md_longopts
[] =
680 { "density", no_argument
, NULL
, option_density
},
681 { "no-density", no_argument
, NULL
, option_no_density
},
683 /* Both "relax" and "generics" are deprecated and treated as equivalent
684 to the "transform" option. */
685 { "relax", no_argument
, NULL
, option_relax
},
686 { "no-relax", no_argument
, NULL
, option_no_relax
},
687 { "generics", no_argument
, NULL
, option_generics
},
688 { "no-generics", no_argument
, NULL
, option_no_generics
},
690 { "transform", no_argument
, NULL
, option_transform
},
691 { "no-transform", no_argument
, NULL
, option_no_transform
},
692 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
693 { "no-text-section-literals", no_argument
, NULL
,
694 option_no_text_section_literals
},
695 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
696 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
697 /* This option was changed from -align-target to -target-align
698 because it conflicted with the "-al" option. */
699 { "target-align", no_argument
, NULL
, option_align_targets
},
700 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
701 { "warn-unaligned-targets", no_argument
, NULL
,
702 option_warn_unaligned_targets
},
703 { "longcalls", no_argument
, NULL
, option_longcalls
},
704 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
706 { "no-workaround-a0-b-retw", no_argument
, NULL
,
707 option_no_workaround_a0_b_retw
},
708 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
710 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
711 option_no_workaround_b_j_loop_end
},
712 { "workaround-b-j-loop-end", no_argument
, NULL
,
713 option_workaround_b_j_loop_end
},
715 { "no-workaround-short-loops", no_argument
, NULL
,
716 option_no_workaround_short_loop
},
717 { "workaround-short-loops", no_argument
, NULL
,
718 option_workaround_short_loop
},
720 { "no-workaround-all-short-loops", no_argument
, NULL
,
721 option_no_workaround_all_short_loops
},
722 { "workaround-all-short-loop", no_argument
, NULL
,
723 option_workaround_all_short_loops
},
725 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
726 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
728 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
730 { "no-workaround-close-loop-end", no_argument
, NULL
,
731 option_no_workaround_close_loop_end
},
732 { "workaround-close-loop-end", no_argument
, NULL
,
733 option_workaround_close_loop_end
},
735 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
737 { "link-relax", no_argument
, NULL
, option_link_relax
},
738 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
740 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
742 { NULL
, no_argument
, NULL
, 0 }
745 size_t md_longopts_size
= sizeof md_longopts
;
749 md_parse_option (int c
, char *arg
)
754 as_warn (_("--density option is ignored"));
756 case option_no_density
:
757 as_warn (_("--no-density option is ignored"));
759 case option_link_relax
:
762 case option_no_link_relax
:
765 case option_generics
:
766 as_warn (_("--generics is deprecated; use --transform instead"));
767 return md_parse_option (option_transform
, arg
);
768 case option_no_generics
:
769 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
770 return md_parse_option (option_no_transform
, arg
);
772 as_warn (_("--relax is deprecated; use --transform instead"));
773 return md_parse_option (option_transform
, arg
);
774 case option_no_relax
:
775 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
776 return md_parse_option (option_no_transform
, arg
);
777 case option_longcalls
:
778 directive_state
[directive_longcalls
] = TRUE
;
780 case option_no_longcalls
:
781 directive_state
[directive_longcalls
] = FALSE
;
783 case option_text_section_literals
:
784 use_literal_section
= FALSE
;
786 case option_no_text_section_literals
:
787 use_literal_section
= TRUE
;
789 case option_absolute_literals
:
790 if (!absolute_literals_supported
)
792 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
795 directive_state
[directive_absolute_literals
] = TRUE
;
797 case option_no_absolute_literals
:
798 directive_state
[directive_absolute_literals
] = FALSE
;
801 case option_workaround_a0_b_retw
:
802 workaround_a0_b_retw
= TRUE
;
804 case option_no_workaround_a0_b_retw
:
805 workaround_a0_b_retw
= FALSE
;
807 case option_workaround_b_j_loop_end
:
808 workaround_b_j_loop_end
= TRUE
;
810 case option_no_workaround_b_j_loop_end
:
811 workaround_b_j_loop_end
= FALSE
;
814 case option_workaround_short_loop
:
815 workaround_short_loop
= TRUE
;
817 case option_no_workaround_short_loop
:
818 workaround_short_loop
= FALSE
;
821 case option_workaround_all_short_loops
:
822 workaround_all_short_loops
= TRUE
;
824 case option_no_workaround_all_short_loops
:
825 workaround_all_short_loops
= FALSE
;
828 case option_workaround_close_loop_end
:
829 workaround_close_loop_end
= TRUE
;
831 case option_no_workaround_close_loop_end
:
832 workaround_close_loop_end
= FALSE
;
835 case option_no_workarounds
:
836 workaround_a0_b_retw
= FALSE
;
837 workaround_b_j_loop_end
= FALSE
;
838 workaround_short_loop
= FALSE
;
839 workaround_all_short_loops
= FALSE
;
840 workaround_close_loop_end
= FALSE
;
843 case option_align_targets
:
844 align_targets
= TRUE
;
846 case option_no_align_targets
:
847 align_targets
= FALSE
;
850 case option_warn_unaligned_targets
:
851 warn_unaligned_branch_targets
= TRUE
;
854 case option_rename_section_name
:
855 build_section_rename (arg
);
859 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
860 should be emitted or not. FIXME: Not implemented. */
863 case option_prefer_l32r
:
865 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
869 case option_prefer_const16
:
871 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
875 case option_target_hardware
:
877 int earliest
, latest
= 0;
878 if (*arg
== 0 || *arg
== '-')
879 as_fatal (_("invalid target hardware version"));
881 earliest
= strtol (arg
, &arg
, 0);
885 else if (*arg
== '-')
888 as_fatal (_("invalid target hardware version"));
889 latest
= strtol (arg
, &arg
, 0);
892 as_fatal (_("invalid target hardware version"));
894 xtensa_setup_hw_workarounds (earliest
, latest
);
898 case option_transform
:
899 /* This option has no affect other than to use the defaults,
900 which are already set. */
903 case option_no_transform
:
904 /* This option turns off all transformations of any kind.
905 However, because we want to preserve the state of other
906 directives, we only change its own field. Thus, before
907 you perform any transformation, always check if transform
908 is available. If you use the functions we provide for this
909 purpose, you will be ok. */
910 directive_state
[directive_transform
] = FALSE
;
920 md_show_usage (FILE *stream
)
924 --[no-]text-section-literals\n\
925 [Do not] put literals in the text section\n\
926 --[no-]absolute-literals\n\
927 [Do not] default to use non-PC-relative literals\n\
928 --[no-]target-align [Do not] try to align branch targets\n\
929 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
930 --[no-]transform [Do not] transform instructions\n\
931 --rename-section old=new Rename section 'old' to 'new'\n", stream
);
935 /* Functions related to the list of current label symbols. */
938 xtensa_add_insn_label (symbolS
*sym
)
942 if (!free_insn_labels
)
943 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
946 l
= free_insn_labels
;
947 free_insn_labels
= l
->next
;
951 l
->next
= insn_labels
;
957 xtensa_clear_insn_labels (void)
961 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
969 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
)
973 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
975 symbolS
*lit_sym
= lit
->sym
;
976 S_SET_VALUE (lit_sym
, new_offset
);
977 symbol_set_frag (lit_sym
, new_frag
);
982 /* Directive data and functions. */
984 typedef struct state_stackS_struct
986 directiveE directive
;
988 bfd_boolean old_state
;
992 struct state_stackS_struct
*prev
;
995 state_stackS
*directive_state_stack
;
997 const pseudo_typeS md_pseudo_table
[] =
999 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
1000 { "literal_position", xtensa_literal_position
, 0 },
1001 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
1002 { "long", xtensa_elf_cons
, 4 },
1003 { "word", xtensa_elf_cons
, 4 },
1004 { "4byte", xtensa_elf_cons
, 4 },
1005 { "short", xtensa_elf_cons
, 2 },
1006 { "2byte", xtensa_elf_cons
, 2 },
1007 { "begin", xtensa_begin_directive
, 0 },
1008 { "end", xtensa_end_directive
, 0 },
1009 { "literal", xtensa_literal_pseudo
, 0 },
1010 { "frequency", xtensa_frequency_pseudo
, 0 },
1016 use_transform (void)
1018 /* After md_end, you should be checking frag by frag, rather
1019 than state directives. */
1020 assert (!past_xtensa_end
);
1021 return directive_state
[directive_transform
];
1026 do_align_targets (void)
1028 /* Do not use this function after md_end; just look at align_targets
1029 instead. There is no target-align directive, so alignment is either
1030 enabled for all frags or not done at all. */
1031 assert (!past_xtensa_end
);
1032 return align_targets
&& use_transform ();
1037 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1041 state_stackS
*stack
= (state_stackS
*) xmalloc (sizeof (state_stackS
));
1043 as_where (&file
, &line
);
1045 stack
->directive
= directive
;
1046 stack
->negated
= negated
;
1047 stack
->old_state
= directive_state
[directive
];
1050 stack
->datum
= datum
;
1051 stack
->prev
= directive_state_stack
;
1052 directive_state_stack
= stack
;
1054 directive_state
[directive
] = !negated
;
1059 directive_pop (directiveE
*directive
,
1060 bfd_boolean
*negated
,
1065 state_stackS
*top
= directive_state_stack
;
1067 if (!directive_state_stack
)
1069 as_bad (_("unmatched end directive"));
1070 *directive
= directive_none
;
1074 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1075 *directive
= top
->directive
;
1076 *negated
= top
->negated
;
1079 *datum
= top
->datum
;
1080 directive_state_stack
= top
->prev
;
1086 directive_balance (void)
1088 while (directive_state_stack
)
1090 directiveE directive
;
1091 bfd_boolean negated
;
1096 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1097 as_warn_where ((char *) file
, line
,
1098 _(".begin directive with no matching .end directive"));
1104 inside_directive (directiveE dir
)
1106 state_stackS
*top
= directive_state_stack
;
1108 while (top
&& top
->directive
!= dir
)
1111 return (top
!= NULL
);
1116 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1120 char *directive_string
;
1122 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1127 input_line_pointer
+= 3;
1130 len
= strspn (input_line_pointer
,
1131 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1133 /* This code is a hack to make .begin [no-][generics|relax] exactly
1134 equivalent to .begin [no-]transform. We should remove it when
1135 we stop accepting those options. */
1137 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1139 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1140 directive_string
= "transform";
1142 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1144 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1145 directive_string
= "transform";
1148 directive_string
= input_line_pointer
;
1150 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1152 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1154 input_line_pointer
+= len
;
1155 *directive
= (directiveE
) i
;
1156 if (*negated
&& !directive_info
[i
].can_be_negated
)
1157 as_bad (_("directive %s cannot be negated"),
1158 directive_info
[i
].name
);
1163 as_bad (_("unknown directive"));
1164 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1169 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1171 directiveE directive
;
1172 bfd_boolean negated
;
1176 get_directive (&directive
, &negated
);
1177 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1179 discard_rest_of_line ();
1183 if (cur_vinsn
.inside_bundle
)
1184 as_bad (_("directives are not valid inside bundles"));
1188 case directive_literal
:
1189 if (!inside_directive (directive_literal
))
1191 /* Previous labels go with whatever follows this directive, not with
1192 the literal, so save them now. */
1193 saved_insn_labels
= insn_labels
;
1196 as_warn (_(".begin literal is deprecated; use .literal instead"));
1197 state
= (emit_state
*) xmalloc (sizeof (emit_state
));
1198 xtensa_switch_to_literal_fragment (state
);
1199 directive_push (directive_literal
, negated
, state
);
1202 case directive_literal_prefix
:
1203 /* Have to flush pending output because a movi relaxed to an l32r
1204 might produce a literal. */
1205 md_flush_pending_output ();
1206 /* Check to see if the current fragment is a literal
1207 fragment. If it is, then this operation is not allowed. */
1208 if (generating_literals
)
1210 as_bad (_("cannot set literal_prefix inside literal fragment"));
1214 /* Allocate the literal state for this section and push
1215 onto the directive stack. */
1216 ls
= xmalloc (sizeof (lit_state
));
1219 *ls
= default_lit_sections
;
1220 directive_push (directive_literal_prefix
, negated
, ls
);
1222 /* Process the new prefix. */
1223 xtensa_literal_prefix ();
1226 case directive_freeregs
:
1227 /* This information is currently unused, but we'll accept the statement
1228 and just discard the rest of the line. This won't check the syntax,
1229 but it will accept every correct freeregs directive. */
1230 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1231 directive_push (directive_freeregs
, negated
, 0);
1234 case directive_schedule
:
1235 md_flush_pending_output ();
1236 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1237 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1238 directive_push (directive_schedule
, negated
, 0);
1239 xtensa_set_frag_assembly_state (frag_now
);
1242 case directive_density
:
1243 as_warn (_(".begin [no-]density is ignored"));
1246 case directive_absolute_literals
:
1247 md_flush_pending_output ();
1248 if (!absolute_literals_supported
&& !negated
)
1250 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1253 xtensa_set_frag_assembly_state (frag_now
);
1254 directive_push (directive
, negated
, 0);
1258 md_flush_pending_output ();
1259 xtensa_set_frag_assembly_state (frag_now
);
1260 directive_push (directive
, negated
, 0);
1264 demand_empty_rest_of_line ();
1269 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1271 directiveE begin_directive
, end_directive
;
1272 bfd_boolean begin_negated
, end_negated
;
1276 emit_state
**state_ptr
;
1279 if (cur_vinsn
.inside_bundle
)
1280 as_bad (_("directives are not valid inside bundles"));
1282 get_directive (&end_directive
, &end_negated
);
1284 md_flush_pending_output ();
1286 switch (end_directive
)
1288 case (directiveE
) XTENSA_UNDEFINED
:
1289 discard_rest_of_line ();
1292 case directive_density
:
1293 as_warn (_(".end [no-]density is ignored"));
1294 demand_empty_rest_of_line ();
1297 case directive_absolute_literals
:
1298 if (!absolute_literals_supported
&& !end_negated
)
1300 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1301 demand_empty_rest_of_line ();
1310 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1311 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1312 (const void **) state_ptr
);
1314 if (begin_directive
!= directive_none
)
1316 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1318 as_bad (_("does not match begin %s%s at %s:%d"),
1319 begin_negated
? "no-" : "",
1320 directive_info
[begin_directive
].name
, file
, line
);
1324 switch (end_directive
)
1326 case directive_literal
:
1327 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1328 xtensa_restore_emit_state (state
);
1329 xtensa_set_frag_assembly_state (frag_now
);
1331 if (!inside_directive (directive_literal
))
1333 /* Restore the list of current labels. */
1334 xtensa_clear_insn_labels ();
1335 insn_labels
= saved_insn_labels
;
1339 case directive_literal_prefix
:
1340 /* Restore the default collection sections from saved state. */
1341 s
= (lit_state
*) state
;
1343 default_lit_sections
= *s
;
1345 /* Free the state storage. */
1346 free (s
->lit_prefix
);
1350 case directive_schedule
:
1351 case directive_freeregs
:
1355 xtensa_set_frag_assembly_state (frag_now
);
1361 demand_empty_rest_of_line ();
1365 /* Place an aligned literal fragment at the current location. */
1368 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1370 md_flush_pending_output ();
1372 if (inside_directive (directive_literal
))
1373 as_warn (_(".literal_position inside literal directive; ignoring"));
1374 xtensa_mark_literal_pool_location ();
1376 demand_empty_rest_of_line ();
1377 xtensa_clear_insn_labels ();
1381 /* Support .literal label, expr, ... */
1384 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1387 char *p
, *base_name
;
1391 if (inside_directive (directive_literal
))
1393 as_bad (_(".literal not allowed inside .begin literal region"));
1394 ignore_rest_of_line ();
1398 md_flush_pending_output ();
1400 /* Previous labels go with whatever follows this directive, not with
1401 the literal, so save them now. */
1402 saved_insn_labels
= insn_labels
;
1405 /* If we are using text-section literals, then this is the right value... */
1408 base_name
= input_line_pointer
;
1410 xtensa_switch_to_literal_fragment (&state
);
1412 /* ...but if we aren't using text-section-literals, then we
1413 need to put them in the section we just switched to. */
1414 if (use_literal_section
|| directive_state
[directive_absolute_literals
])
1417 /* All literals are aligned to four-byte boundaries. */
1418 frag_align (2, 0, 0);
1419 record_alignment (now_seg
, 2);
1421 c
= get_symbol_end ();
1422 /* Just after name is now '\0'. */
1423 p
= input_line_pointer
;
1427 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1429 as_bad (_("expected comma or colon after symbol name; "
1430 "rest of line ignored"));
1431 ignore_rest_of_line ();
1432 xtensa_restore_emit_state (&state
);
1440 input_line_pointer
++; /* skip ',' or ':' */
1442 xtensa_elf_cons (4);
1444 xtensa_restore_emit_state (&state
);
1446 /* Restore the list of current labels. */
1447 xtensa_clear_insn_labels ();
1448 insn_labels
= saved_insn_labels
;
1453 xtensa_literal_prefix (void)
1458 /* Parse the new prefix from the input_line_pointer. */
1460 len
= strspn (input_line_pointer
,
1461 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1462 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1464 /* Get a null-terminated copy of the name. */
1465 name
= xmalloc (len
+ 1);
1467 strncpy (name
, input_line_pointer
, len
);
1470 /* Skip the name in the input line. */
1471 input_line_pointer
+= len
;
1473 default_lit_sections
.lit_prefix
= name
;
1475 /* Clear cached literal sections, since the prefix has changed. */
1476 default_lit_sections
.lit_seg
= NULL
;
1477 default_lit_sections
.lit4_seg
= NULL
;
1481 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1484 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1486 float fall_through_f
, target_f
;
1488 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1489 if (fall_through_f
< 0)
1491 as_bad (_("fall through frequency must be greater than 0"));
1492 ignore_rest_of_line ();
1496 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1499 as_bad (_("branch target frequency must be greater than 0"));
1500 ignore_rest_of_line ();
1504 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1506 demand_empty_rest_of_line ();
1510 /* Like normal .long/.short/.word, except support @plt, etc.
1511 Clobbers input_line_pointer, checks end-of-line. */
1514 xtensa_elf_cons (int nbytes
)
1517 bfd_reloc_code_real_type reloc
;
1519 md_flush_pending_output ();
1521 if (cur_vinsn
.inside_bundle
)
1522 as_bad (_("directives are not valid inside bundles"));
1524 if (is_it_end_of_statement ())
1526 demand_empty_rest_of_line ();
1533 if (exp
.X_op
== O_symbol
1534 && *input_line_pointer
== '@'
1535 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1538 reloc_howto_type
*reloc_howto
=
1539 bfd_reloc_type_lookup (stdoutput
, reloc
);
1541 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1542 as_bad (_("unsupported relocation"));
1543 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1544 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1545 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1546 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1547 as_bad (_("opcode-specific %s relocation used outside "
1548 "an instruction"), reloc_howto
->name
);
1549 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1550 as_bad (_("%s relocations do not fit in %d bytes"),
1551 reloc_howto
->name
, nbytes
);
1554 char *p
= frag_more ((int) nbytes
);
1555 xtensa_set_frag_assembly_state (frag_now
);
1556 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1557 nbytes
, &exp
, reloc_howto
->pc_relative
, reloc
);
1561 emit_expr (&exp
, (unsigned int) nbytes
);
1563 while (*input_line_pointer
++ == ',');
1565 input_line_pointer
--; /* Put terminator back into stream. */
1566 demand_empty_rest_of_line ();
1570 /* Parsing and Idiom Translation. */
1572 /* Parse @plt, etc. and return the desired relocation. */
1573 static bfd_reloc_code_real_type
1574 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1581 struct suffix_reloc_map
*ptr
;
1584 return BFD_RELOC_NONE
;
1586 for (ch
= *str
, str2
= ident
;
1587 (str2
< ident
+ sizeof (ident
) - 1
1588 && (ISALNUM (ch
) || ch
== '@'));
1591 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1598 for (ptr
= &suffix_relocs
[0]; ptr
->length
> 0; ptr
++)
1599 if (ch
== ptr
->suffix
[0]
1600 && len
== ptr
->length
1601 && memcmp (ident
, ptr
->suffix
, ptr
->length
) == 0)
1603 /* Now check for "identifier@suffix+constant". */
1604 if (*str
== '-' || *str
== '+')
1606 char *orig_line
= input_line_pointer
;
1607 expressionS new_exp
;
1609 input_line_pointer
= str
;
1610 expression (&new_exp
);
1611 if (new_exp
.X_op
== O_constant
)
1613 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1614 str
= input_line_pointer
;
1617 if (&input_line_pointer
!= str_p
)
1618 input_line_pointer
= orig_line
;
1625 return BFD_RELOC_UNUSED
;
1629 /* Find the matching operator type. */
1630 static unsigned char
1631 map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc
)
1633 struct suffix_reloc_map
*sfx
;
1634 unsigned char operator = (unsigned char) -1;
1636 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1638 if (sfx
->reloc
== reloc
)
1640 operator = sfx
->operator;
1644 assert (operator != (unsigned char) -1);
1649 /* Find the matching reloc type. */
1650 static bfd_reloc_code_real_type
1651 map_operator_to_reloc (unsigned char operator)
1653 struct suffix_reloc_map
*sfx
;
1654 bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
1656 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1658 if (sfx
->operator == operator)
1665 if (reloc
== BFD_RELOC_UNUSED
)
1666 return BFD_RELOC_32
;
1673 expression_end (const char *name
)
1696 #define ERROR_REG_NUM ((unsigned) -1)
1699 tc_get_register (const char *prefix
)
1702 const char *next_expr
;
1703 const char *old_line_pointer
;
1706 old_line_pointer
= input_line_pointer
;
1708 if (*input_line_pointer
== '$')
1709 ++input_line_pointer
;
1711 /* Accept "sp" as a synonym for "a1". */
1712 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1713 && expression_end (input_line_pointer
+ 2))
1715 input_line_pointer
+= 2;
1716 return 1; /* AR[1] */
1719 while (*input_line_pointer
++ == *prefix
++)
1721 --input_line_pointer
;
1726 as_bad (_("bad register name: %s"), old_line_pointer
);
1727 return ERROR_REG_NUM
;
1730 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1732 as_bad (_("bad register number: %s"), input_line_pointer
);
1733 return ERROR_REG_NUM
;
1738 while (ISDIGIT ((int) *input_line_pointer
))
1739 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1741 if (!(next_expr
= expression_end (input_line_pointer
)))
1743 as_bad (_("bad register name: %s"), old_line_pointer
);
1744 return ERROR_REG_NUM
;
1747 input_line_pointer
= (char *) next_expr
;
1754 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1756 xtensa_isa isa
= xtensa_default_isa
;
1758 /* Check if this is an immediate operand. */
1759 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1761 bfd_reloc_code_real_type reloc
;
1762 segT t
= expression (tok
);
1763 if (t
== absolute_section
1764 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1766 assert (tok
->X_op
== O_constant
);
1767 tok
->X_op
= O_symbol
;
1768 tok
->X_add_symbol
= &abs_symbol
;
1771 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1772 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1777 case BFD_RELOC_LO16
:
1778 if (tok
->X_op
== O_constant
)
1780 tok
->X_add_number
&= 0xffff;
1784 case BFD_RELOC_HI16
:
1785 if (tok
->X_op
== O_constant
)
1787 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1791 case BFD_RELOC_UNUSED
:
1792 as_bad (_("unsupported relocation"));
1794 case BFD_RELOC_32_PCREL
:
1795 as_bad (_("pcrel relocation not allowed in an instruction"));
1800 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
1805 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1806 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1808 if (reg
!= ERROR_REG_NUM
) /* Already errored */
1811 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
1812 as_bad (_("register number out of range"));
1815 tok
->X_op
= O_register
;
1816 tok
->X_add_symbol
= 0;
1817 tok
->X_add_number
= reg
;
1822 /* Split up the arguments for an opcode or pseudo-op. */
1825 tokenize_arguments (char **args
, char *str
)
1827 char *old_input_line_pointer
;
1828 bfd_boolean saw_comma
= FALSE
;
1829 bfd_boolean saw_arg
= FALSE
;
1830 bfd_boolean saw_colon
= FALSE
;
1832 char *arg_end
, *arg
;
1835 /* Save and restore input_line_pointer around this function. */
1836 old_input_line_pointer
= input_line_pointer
;
1837 input_line_pointer
= str
;
1839 while (*input_line_pointer
)
1842 switch (*input_line_pointer
)
1849 input_line_pointer
++;
1850 if (saw_comma
|| saw_colon
|| !saw_arg
)
1856 input_line_pointer
++;
1857 if (saw_comma
|| saw_colon
|| !saw_arg
)
1863 if (!saw_comma
&& !saw_colon
&& saw_arg
)
1866 arg_end
= input_line_pointer
+ 1;
1867 while (!expression_end (arg_end
))
1870 arg_len
= arg_end
- input_line_pointer
;
1871 arg
= (char *) xmalloc ((saw_colon
? 1 : 0) + arg_len
+ 1);
1872 args
[num_args
] = arg
;
1876 strncpy (arg
, input_line_pointer
, arg_len
);
1877 arg
[arg_len
] = '\0';
1879 input_line_pointer
= arg_end
;
1889 if (saw_comma
|| saw_colon
)
1891 input_line_pointer
= old_input_line_pointer
;
1896 as_bad (_("extra comma"));
1898 as_bad (_("extra colon"));
1900 as_bad (_("missing argument"));
1902 as_bad (_("missing comma or colon"));
1903 input_line_pointer
= old_input_line_pointer
;
1908 /* Parse the arguments to an opcode. Return TRUE on error. */
1911 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
1913 expressionS
*tok
, *last_tok
;
1914 xtensa_opcode opcode
= insn
->opcode
;
1915 bfd_boolean had_error
= TRUE
;
1916 xtensa_isa isa
= xtensa_default_isa
;
1917 int n
, num_regs
= 0;
1918 int opcode_operand_count
;
1919 int opnd_cnt
, last_opnd_cnt
;
1920 unsigned int next_reg
= 0;
1921 char *old_input_line_pointer
;
1923 if (insn
->insn_type
== ITYPE_LITERAL
)
1924 opcode_operand_count
= 1;
1926 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
1929 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
1931 /* Save and restore input_line_pointer around this function. */
1932 old_input_line_pointer
= input_line_pointer
;
1938 /* Skip invisible operands. */
1939 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
1945 for (n
= 0; n
< num_args
; n
++)
1947 input_line_pointer
= arg_strings
[n
];
1948 if (*input_line_pointer
== ':')
1950 xtensa_regfile opnd_rf
;
1951 input_line_pointer
++;
1954 assert (opnd_cnt
> 0);
1956 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
1958 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
1959 as_warn (_("incorrect register number, ignoring"));
1964 if (opnd_cnt
>= opcode_operand_count
)
1966 as_warn (_("too many arguments"));
1969 assert (opnd_cnt
< MAX_INSN_ARGS
);
1971 expression_maybe_register (opcode
, opnd_cnt
, tok
);
1972 next_reg
= tok
->X_add_number
+ 1;
1974 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
1976 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
1978 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
1979 /* minus 1 because we are seeing one right now */
1985 last_opnd_cnt
= opnd_cnt
;
1992 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
1996 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
1999 insn
->ntok
= tok
- insn
->tok
;
2003 input_line_pointer
= old_input_line_pointer
;
2009 get_invisible_operands (TInsn
*insn
)
2011 xtensa_isa isa
= xtensa_default_isa
;
2012 static xtensa_insnbuf slotbuf
= NULL
;
2014 xtensa_opcode opc
= insn
->opcode
;
2015 int slot
, opnd
, fmt_found
;
2019 slotbuf
= xtensa_insnbuf_alloc (isa
);
2021 /* Find format/slot where this can be encoded. */
2024 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2026 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2028 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2034 if (fmt_found
) break;
2039 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2043 /* First encode all the visible operands
2044 (to deal with shared field operands). */
2045 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2047 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2048 && (insn
->tok
[opnd
].X_op
== O_register
2049 || insn
->tok
[opnd
].X_op
== O_constant
))
2051 val
= insn
->tok
[opnd
].X_add_number
;
2052 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2053 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2057 /* Then pull out the values for the invisible ones. */
2058 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2060 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2062 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2063 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2064 insn
->tok
[opnd
].X_add_number
= val
;
2065 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2066 insn
->tok
[opnd
].X_op
= O_register
;
2068 insn
->tok
[opnd
].X_op
= O_constant
;
2077 xg_reverse_shift_count (char **cnt_argp
)
2079 char *cnt_arg
, *new_arg
;
2080 cnt_arg
= *cnt_argp
;
2082 /* replace the argument with "31-(argument)" */
2083 new_arg
= (char *) xmalloc (strlen (cnt_arg
) + 6);
2084 sprintf (new_arg
, "31-(%s)", cnt_arg
);
2087 *cnt_argp
= new_arg
;
2091 /* If "arg" is a constant expression, return non-zero with the value
2095 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2098 char *save_ptr
= input_line_pointer
;
2100 input_line_pointer
= arg
;
2102 input_line_pointer
= save_ptr
;
2104 if (exp
.X_op
== O_constant
)
2106 *valp
= exp
.X_add_number
;
2115 xg_replace_opname (char **popname
, char *newop
)
2118 *popname
= (char *) xmalloc (strlen (newop
) + 1);
2119 strcpy (*popname
, newop
);
2124 xg_check_num_args (int *pnum_args
,
2129 int num_args
= *pnum_args
;
2131 if (num_args
< expected_num
)
2133 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2134 num_args
, opname
, expected_num
);
2138 if (num_args
> expected_num
)
2140 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2141 num_args
, opname
, expected_num
);
2142 while (num_args
-- > expected_num
)
2144 free (arg_strings
[num_args
]);
2145 arg_strings
[num_args
] = 0;
2147 *pnum_args
= expected_num
;
2155 /* If the register is not specified as part of the opcode,
2156 then get it from the operand and move it to the opcode. */
2159 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2161 xtensa_isa isa
= xtensa_default_isa
;
2163 char *opname
, *new_opname
;
2164 const char *sr_name
;
2165 int is_user
, is_write
;
2170 is_user
= (opname
[1] == 'u');
2171 is_write
= (opname
[0] == 'w');
2173 /* Opname == [rw]ur or [rwx]sr... */
2175 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2178 /* Check if the argument is a symbolic register name. */
2179 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2180 /* Handle WSR to "INTSET" as a special case. */
2181 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2182 && !strcasecmp (arg_strings
[1], "intset"))
2183 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2184 if (sr
== XTENSA_UNDEFINED
2185 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2187 /* Maybe it's a register number.... */
2189 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2191 as_bad (_("invalid register '%s' for '%s' instruction"),
2192 arg_strings
[1], opname
);
2195 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2196 if (sr
== XTENSA_UNDEFINED
)
2198 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2199 (long) val
, opname
);
2204 /* Remove the last argument, which is now part of the opcode. */
2205 free (arg_strings
[1]);
2209 /* Translate the opcode. */
2210 sr_name
= xtensa_sysreg_name (isa
, sr
);
2211 /* Another special case for "WSR.INTSET".... */
2212 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2214 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2215 sprintf (new_opname
, "%s.%s", *popname
, sr_name
);
2217 *popname
= new_opname
;
2224 xtensa_translate_old_userreg_ops (char **popname
)
2226 xtensa_isa isa
= xtensa_default_isa
;
2228 char *opname
, *new_opname
;
2229 const char *sr_name
;
2230 bfd_boolean has_underbar
= FALSE
;
2233 if (opname
[0] == '_')
2235 has_underbar
= TRUE
;
2239 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2240 if (sr
!= XTENSA_UNDEFINED
)
2242 /* The new default name ("nnn") is different from the old default
2243 name ("URnnn"). The old default is handled below, and we don't
2244 want to recognize [RW]nnn, so do nothing if the name is the (new)
2246 static char namebuf
[10];
2247 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2248 if (strcmp (namebuf
, opname
+ 1) == 0)
2256 /* Only continue if the reg name is "URnnn". */
2257 if (opname
[1] != 'u' || opname
[2] != 'r')
2259 val
= strtoul (opname
+ 3, &end
, 10);
2263 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2264 if (sr
== XTENSA_UNDEFINED
)
2266 as_bad (_("invalid register number (%ld) for '%s'"),
2267 (long) val
, opname
);
2272 /* Translate the opcode. */
2273 sr_name
= xtensa_sysreg_name (isa
, sr
);
2274 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2275 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2276 opname
[0], sr_name
);
2278 *popname
= new_opname
;
2285 xtensa_translate_zero_immed (char *old_op
,
2295 assert (opname
[0] != '_');
2297 if (strcmp (opname
, old_op
) != 0)
2300 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2302 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2304 xg_replace_opname (popname
, new_op
);
2305 free (arg_strings
[1]);
2306 arg_strings
[1] = arg_strings
[2];
2315 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2316 Returns non-zero if an error was found. */
2319 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2321 char *opname
= *popname
;
2322 bfd_boolean has_underbar
= FALSE
;
2326 has_underbar
= TRUE
;
2330 if (strcmp (opname
, "mov") == 0)
2332 if (use_transform () && !has_underbar
&& density_supported
)
2333 xg_replace_opname (popname
, "mov.n");
2336 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2338 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2339 arg_strings
[2] = (char *) xmalloc (strlen (arg_strings
[1]) + 1);
2340 strcpy (arg_strings
[2], arg_strings
[1]);
2346 if (strcmp (opname
, "bbsi.l") == 0)
2348 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2350 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2351 if (target_big_endian
)
2352 xg_reverse_shift_count (&arg_strings
[1]);
2356 if (strcmp (opname
, "bbci.l") == 0)
2358 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2360 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2361 if (target_big_endian
)
2362 xg_reverse_shift_count (&arg_strings
[1]);
2366 /* Don't do anything special with NOPs inside FLIX instructions. They
2367 are handled elsewhere. Real NOP instructions are always available
2368 in configurations with FLIX, so this should never be an issue but
2369 check for it anyway. */
2370 if (!cur_vinsn
.inside_bundle
&& xtensa_nop_opcode
== XTENSA_UNDEFINED
2371 && strcmp (opname
, "nop") == 0)
2373 if (use_transform () && !has_underbar
&& density_supported
)
2374 xg_replace_opname (popname
, "nop.n");
2377 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2379 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2380 arg_strings
[0] = (char *) xmalloc (3);
2381 arg_strings
[1] = (char *) xmalloc (3);
2382 arg_strings
[2] = (char *) xmalloc (3);
2383 strcpy (arg_strings
[0], "a1");
2384 strcpy (arg_strings
[1], "a1");
2385 strcpy (arg_strings
[2], "a1");
2391 /* Recognize [RW]UR and [RWX]SR. */
2392 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2393 && (opname
[1] == 'u' || opname
[1] == 's'))
2394 || (opname
[0] == 'x' && opname
[1] == 's'))
2396 && opname
[3] == '\0')
2397 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2399 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2400 [RW]<name> if <name> is the non-default name of a user register. */
2401 if ((opname
[0] == 'r' || opname
[0] == 'w')
2402 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2403 return xtensa_translate_old_userreg_ops (popname
);
2405 /* Relax branches that don't allow comparisons against an immediate value
2406 of zero to the corresponding branches with implicit zero immediates. */
2407 if (!has_underbar
&& use_transform ())
2409 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2410 pnum_args
, arg_strings
))
2413 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2414 pnum_args
, arg_strings
))
2417 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2418 pnum_args
, arg_strings
))
2421 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2422 pnum_args
, arg_strings
))
2430 /* Functions for dealing with the Xtensa ISA. */
2432 /* Currently the assembler only allows us to use a single target per
2433 fragment. Because of this, only one operand for a given
2434 instruction may be symbolic. If there is a PC-relative operand,
2435 the last one is chosen. Otherwise, the result is the number of the
2436 last immediate operand, and if there are none of those, we fail and
2440 get_relaxable_immed (xtensa_opcode opcode
)
2442 int last_immed
= -1;
2445 if (opcode
== XTENSA_UNDEFINED
)
2448 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2449 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2451 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2453 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2455 if (last_immed
== -1
2456 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2463 static xtensa_opcode
2464 get_opcode_from_buf (const char *buf
, int slot
)
2466 static xtensa_insnbuf insnbuf
= NULL
;
2467 static xtensa_insnbuf slotbuf
= NULL
;
2468 xtensa_isa isa
= xtensa_default_isa
;
2473 insnbuf
= xtensa_insnbuf_alloc (isa
);
2474 slotbuf
= xtensa_insnbuf_alloc (isa
);
2477 xtensa_insnbuf_from_chars (isa
, insnbuf
, (const unsigned char *) buf
, 0);
2478 fmt
= xtensa_format_decode (isa
, insnbuf
);
2479 if (fmt
== XTENSA_UNDEFINED
)
2480 return XTENSA_UNDEFINED
;
2482 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2483 return XTENSA_UNDEFINED
;
2485 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2486 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2490 #ifdef TENSILICA_DEBUG
2492 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2495 xtensa_print_insn_table (void)
2497 int num_opcodes
, num_operands
;
2498 xtensa_opcode opcode
;
2499 xtensa_isa isa
= xtensa_default_isa
;
2501 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2502 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2505 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2506 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2507 for (opn
= 0; opn
< num_operands
; opn
++)
2509 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2511 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2513 xtensa_regfile opnd_rf
=
2514 xtensa_operand_regfile (isa
, opcode
, opn
);
2515 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2517 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2518 fputs ("[lLr] ", stderr
);
2520 fputs ("i ", stderr
);
2522 fprintf (stderr
, "\n");
2528 print_vliw_insn (xtensa_insnbuf vbuf
)
2530 xtensa_isa isa
= xtensa_default_isa
;
2531 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2532 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2535 fprintf (stderr
, "format = %d\n", f
);
2537 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2539 xtensa_opcode opcode
;
2543 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2544 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2545 opname
= xtensa_opcode_name (isa
, opcode
);
2547 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2548 fprintf (stderr
, " operands = ");
2550 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2554 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2556 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2557 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2558 fprintf (stderr
, "%d ", val
);
2560 fprintf (stderr
, "\n");
2562 xtensa_insnbuf_free (isa
, sbuf
);
2565 #endif /* TENSILICA_DEBUG */
2569 is_direct_call_opcode (xtensa_opcode opcode
)
2571 xtensa_isa isa
= xtensa_default_isa
;
2572 int n
, num_operands
;
2574 if (xtensa_opcode_is_call (isa
, opcode
) != 1)
2577 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2578 for (n
= 0; n
< num_operands
; n
++)
2580 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2581 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2588 /* Convert from BFD relocation type code to slot and operand number.
2589 Returns non-zero on failure. */
2592 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2594 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2595 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2597 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2600 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2601 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2603 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2613 /* Convert from slot number to BFD relocation type code for the
2614 standard PC-relative relocations. Return BFD_RELOC_NONE on
2617 static bfd_reloc_code_real_type
2618 encode_reloc (int slot
)
2620 if (slot
< 0 || slot
> 14)
2621 return BFD_RELOC_NONE
;
2623 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2627 /* Convert from slot numbers to BFD relocation type code for the
2628 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2630 static bfd_reloc_code_real_type
2631 encode_alt_reloc (int slot
)
2633 if (slot
< 0 || slot
> 14)
2634 return BFD_RELOC_NONE
;
2636 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2641 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2644 xtensa_opcode opcode
,
2650 uint32 valbuf
= value
;
2652 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2654 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2656 as_bad_where ((char *) file
, line
,
2657 _("operand %d of '%s' has out of range value '%u'"),
2659 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2662 as_bad_where ((char *) file
, line
,
2663 _("operand %d of '%s' has invalid value '%u'"),
2665 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2670 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2676 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2679 xtensa_opcode opcode
,
2683 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2684 fmt
, slot
, slotbuf
, &val
);
2685 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2690 /* Checks for rules from xtensa-relax tables. */
2692 /* The routine xg_instruction_matches_option_term must return TRUE
2693 when a given option term is true. The meaning of all of the option
2694 terms is given interpretation by this function. This is needed when
2695 an option depends on the state of a directive, but there are no such
2696 options in use right now. */
2699 xg_instruction_matches_option_term (TInsn
*insn ATTRIBUTE_UNUSED
,
2700 const ReqOrOption
*option
)
2702 if (strcmp (option
->option_name
, "realnop") == 0
2703 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2705 /* These conditions were evaluated statically when building the
2706 relaxation table. There's no need to reevaluate them now. */
2711 as_fatal (_("internal error: unknown option name '%s'"),
2712 option
->option_name
);
2718 xg_instruction_matches_or_options (TInsn
*insn
,
2719 const ReqOrOptionList
*or_option
)
2721 const ReqOrOption
*option
;
2722 /* Must match each of the AND terms. */
2723 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2725 if (xg_instruction_matches_option_term (insn
, option
))
2733 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2735 const ReqOption
*req_options
;
2736 /* Must match each of the AND terms. */
2737 for (req_options
= options
;
2738 req_options
!= NULL
;
2739 req_options
= req_options
->next
)
2741 /* Must match one of the OR clauses. */
2742 if (!xg_instruction_matches_or_options (insn
,
2743 req_options
->or_option_terms
))
2750 /* Return the transition rule that matches or NULL if none matches. */
2753 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2755 PreconditionList
*condition_l
;
2757 if (rule
->opcode
!= insn
->opcode
)
2760 for (condition_l
= rule
->conditions
;
2761 condition_l
!= NULL
;
2762 condition_l
= condition_l
->next
)
2766 Precondition
*cond
= condition_l
->precond
;
2771 /* The expression must be the constant. */
2772 assert (cond
->op_num
< insn
->ntok
);
2773 exp1
= &insn
->tok
[cond
->op_num
];
2774 if (expr_is_const (exp1
))
2779 if (get_expr_const (exp1
) != cond
->op_data
)
2783 if (get_expr_const (exp1
) == cond
->op_data
)
2790 else if (expr_is_register (exp1
))
2795 if (get_expr_register (exp1
) != cond
->op_data
)
2799 if (get_expr_register (exp1
) == cond
->op_data
)
2811 assert (cond
->op_num
< insn
->ntok
);
2812 assert (cond
->op_data
< insn
->ntok
);
2813 exp1
= &insn
->tok
[cond
->op_num
];
2814 exp2
= &insn
->tok
[cond
->op_data
];
2819 if (!expr_is_equal (exp1
, exp2
))
2823 if (expr_is_equal (exp1
, exp2
))
2835 if (!xg_instruction_matches_options (insn
, rule
->options
))
2843 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
2845 bfd_boolean a_greater
= FALSE
;
2846 bfd_boolean b_greater
= FALSE
;
2848 ReqOptionList
*l_a
= a
->options
;
2849 ReqOptionList
*l_b
= b
->options
;
2851 /* We only care if they both are the same except for
2852 a const16 vs. an l32r. */
2854 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2856 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
2857 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
2858 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2860 if (l_or_a
->is_true
!= l_or_b
->is_true
)
2862 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
2864 /* This is the case we care about. */
2865 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
2866 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
2873 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
2874 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
2884 l_or_a
= l_or_a
->next
;
2885 l_or_b
= l_or_b
->next
;
2887 if (l_or_a
|| l_or_b
)
2896 /* Incomparable if the substitution was used differently in two cases. */
2897 if (a_greater
&& b_greater
)
2909 static TransitionRule
*
2910 xg_instruction_match (TInsn
*insn
)
2912 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
2914 assert (insn
->opcode
< table
->num_opcodes
);
2916 /* Walk through all of the possible transitions. */
2917 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2919 TransitionRule
*rule
= l
->rule
;
2920 if (xg_instruction_matches_rule (insn
, rule
))
2927 /* Various Other Internal Functions. */
2930 is_unique_insn_expansion (TransitionRule
*r
)
2932 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
2934 if (r
->to_instr
->typ
!= INSTR_INSTR
)
2940 /* Check if there is exactly one relaxation for INSN that converts it to
2941 another instruction of equal or larger size. If so, and if TARG is
2942 non-null, go ahead and generate the relaxed instruction into TARG. If
2943 NARROW_ONLY is true, then only consider relaxations that widen a narrow
2944 instruction, i.e., ignore relaxations that convert to an instruction of
2945 equal size. In some contexts where this function is used, only
2946 a single widening is allowed and the NARROW_ONLY argument is used to
2947 exclude cases like ADDI being "widened" to an ADDMI, which may
2948 later be relaxed to an ADDMI/ADDI pair. */
2951 xg_is_single_relaxable_insn (TInsn
*insn
, TInsn
*targ
, bfd_boolean narrow_only
)
2953 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
2955 TransitionRule
*match
= 0;
2957 assert (insn
->insn_type
== ITYPE_INSN
);
2958 assert (insn
->opcode
< table
->num_opcodes
);
2960 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2962 TransitionRule
*rule
= l
->rule
;
2964 if (xg_instruction_matches_rule (insn
, rule
)
2965 && is_unique_insn_expansion (rule
)
2966 && (xg_get_single_size (insn
->opcode
) + (narrow_only
? 1 : 0)
2967 <= xg_get_single_size (rule
->to_instr
->opcode
)))
2978 xg_build_to_insn (targ
, insn
, match
->to_instr
);
2983 /* Return the maximum number of bytes this opcode can expand to. */
2986 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
2988 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
2990 int max_size
= xg_get_single_size (opcode
);
2992 assert (opcode
< table
->num_opcodes
);
2994 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
2996 TransitionRule
*rule
= l
->rule
;
2997 BuildInstr
*build_list
;
3002 build_list
= rule
->to_instr
;
3003 if (is_unique_insn_expansion (rule
))
3005 assert (build_list
->typ
== INSTR_INSTR
);
3006 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
3009 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3011 switch (build_list
->typ
)
3014 this_size
+= xg_get_single_size (build_list
->opcode
);
3016 case INSTR_LITERAL_DEF
:
3017 case INSTR_LABEL_DEF
:
3022 if (this_size
> max_size
)
3023 max_size
= this_size
;
3029 /* Return the maximum number of literal bytes this opcode can generate. */
3032 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3034 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3038 assert (opcode
< table
->num_opcodes
);
3040 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3042 TransitionRule
*rule
= l
->rule
;
3043 BuildInstr
*build_list
;
3048 build_list
= rule
->to_instr
;
3049 if (is_unique_insn_expansion (rule
))
3051 assert (build_list
->typ
== INSTR_INSTR
);
3052 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3055 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3057 switch (build_list
->typ
)
3059 case INSTR_LITERAL_DEF
:
3060 /* Hard-coded 4-byte literal. */
3064 case INSTR_LABEL_DEF
:
3069 if (this_size
> max_size
)
3070 max_size
= this_size
;
3077 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3079 int steps_taken
= 0;
3080 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3083 assert (insn
->insn_type
== ITYPE_INSN
);
3084 assert (insn
->opcode
< table
->num_opcodes
);
3086 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3088 TransitionRule
*rule
= l
->rule
;
3090 if (xg_instruction_matches_rule (insn
, rule
))
3092 if (steps_taken
== lateral_steps
)
3102 get_special_literal_symbol (void)
3104 static symbolS
*sym
= NULL
;
3107 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3113 get_special_label_symbol (void)
3115 static symbolS
*sym
= NULL
;
3118 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3124 xg_valid_literal_expression (const expressionS
*exp
)
3142 /* This will check to see if the value can be converted into the
3143 operand type. It will return TRUE if it does not fit. */
3146 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3148 uint32 valbuf
= value
;
3149 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3155 /* Assumes: All immeds are constants. Check that all constants fit
3156 into their immeds; return FALSE if not. */
3159 xg_immeds_fit (const TInsn
*insn
)
3161 xtensa_isa isa
= xtensa_default_isa
;
3165 assert (insn
->insn_type
== ITYPE_INSN
);
3166 for (i
= 0; i
< n
; ++i
)
3168 const expressionS
*expr
= &insn
->tok
[i
];
3169 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3176 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3181 /* The symbol should have a fixup associated with it. */
3190 /* This should only be called after we have an initial
3191 estimate of the addresses. */
3194 xg_symbolic_immeds_fit (const TInsn
*insn
,
3200 xtensa_isa isa
= xtensa_default_isa
;
3208 assert (insn
->insn_type
== ITYPE_INSN
);
3210 for (i
= 0; i
< n
; ++i
)
3212 const expressionS
*expr
= &insn
->tok
[i
];
3213 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3220 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3226 /* Check for the worst case. */
3227 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3232 /* We only allow symbols for PC-relative references.
3233 If pc_frag == 0, then we don't have frag locations yet. */
3235 || xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0)
3238 /* If it is a weak symbol or a symbol in a different section,
3239 it cannot be known to fit at assembly time. */
3240 if (S_IS_WEAK (expr
->X_add_symbol
)
3241 || S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3243 /* For a direct call with --no-longcalls, be optimistic and
3244 assume it will be in range. If the symbol is weak and
3245 undefined, it may remain undefined at link-time, in which
3246 case it will have a zero value and almost certainly be out
3247 of range for a direct call; thus, relax for undefined weak
3248 symbols even if longcalls is not enabled. */
3249 if (is_direct_call_opcode (insn
->opcode
)
3250 && ! pc_frag
->tc_frag_data
.use_longcalls
3251 && (! S_IS_WEAK (expr
->X_add_symbol
)
3252 || S_IS_DEFINED (expr
->X_add_symbol
)))
3258 symbolP
= expr
->X_add_symbol
;
3259 sym_frag
= symbol_get_frag (symbolP
);
3260 target
= S_GET_VALUE (symbolP
) + expr
->X_add_number
;
3261 pc
= pc_frag
->fr_address
+ pc_offset
;
3263 /* If frag has yet to be reached on this pass, assume it
3264 will move by STRETCH just as we did. If this is not so,
3265 it will be because some frag between grows, and that will
3266 force another pass. Beware zero-length frags. There
3267 should be a faster way to do this. */
3270 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3271 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3276 new_offset
= target
;
3277 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3278 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3283 /* The symbol should have a fixup associated with it. */
3292 /* Return TRUE on success. */
3295 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3301 targ
->debug_line
= insn
->debug_line
;
3302 targ
->loc_directive_seen
= insn
->loc_directive_seen
;
3307 targ
->opcode
= bi
->opcode
;
3308 targ
->insn_type
= ITYPE_INSN
;
3309 targ
->is_specific_opcode
= FALSE
;
3311 for (; op
!= NULL
; op
= op
->next
)
3313 int op_num
= op
->op_num
;
3314 int op_data
= op
->op_data
;
3316 assert (op
->op_num
< MAX_INSN_ARGS
);
3318 if (targ
->ntok
<= op_num
)
3319 targ
->ntok
= op_num
+ 1;
3324 set_expr_const (&targ
->tok
[op_num
], op_data
);
3327 assert (op_data
< insn
->ntok
);
3328 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3331 sym
= get_special_literal_symbol ();
3332 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3335 sym
= get_special_label_symbol ();
3336 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3338 case OP_OPERAND_HI16U
:
3339 case OP_OPERAND_LOW16U
:
3340 assert (op_data
< insn
->ntok
);
3341 if (expr_is_const (&insn
->tok
[op_data
]))
3344 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3345 val
= xg_apply_userdef_op_fn (op
->typ
,
3348 targ
->tok
[op_num
].X_add_number
= val
;
3352 /* For const16 we can create relocations for these. */
3353 if (targ
->opcode
== XTENSA_UNDEFINED
3354 || (targ
->opcode
!= xtensa_const16_opcode
))
3356 assert (op_data
< insn
->ntok
);
3357 /* Need to build a O_lo16 or O_hi16. */
3358 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3359 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3361 if (op
->typ
== OP_OPERAND_HI16U
)
3362 targ
->tok
[op_num
].X_op
= O_hi16
;
3363 else if (op
->typ
== OP_OPERAND_LOW16U
)
3364 targ
->tok
[op_num
].X_op
= O_lo16
;
3371 /* currently handles:
3374 OP_OPERAND_F32MINUS */
3375 if (xg_has_userdef_op_fn (op
->typ
))
3377 assert (op_data
< insn
->ntok
);
3378 if (expr_is_const (&insn
->tok
[op_data
]))
3381 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3382 val
= xg_apply_userdef_op_fn (op
->typ
,
3385 targ
->tok
[op_num
].X_add_number
= val
;
3388 return FALSE
; /* We cannot use a relocation for this. */
3397 case INSTR_LITERAL_DEF
:
3399 targ
->opcode
= XTENSA_UNDEFINED
;
3400 targ
->insn_type
= ITYPE_LITERAL
;
3401 targ
->is_specific_opcode
= FALSE
;
3402 for (; op
!= NULL
; op
= op
->next
)
3404 int op_num
= op
->op_num
;
3405 int op_data
= op
->op_data
;
3406 assert (op
->op_num
< MAX_INSN_ARGS
);
3408 if (targ
->ntok
<= op_num
)
3409 targ
->ntok
= op_num
+ 1;
3414 assert (op_data
< insn
->ntok
);
3415 /* We can only pass resolvable literals through. */
3416 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3418 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3430 case INSTR_LABEL_DEF
:
3432 targ
->opcode
= XTENSA_UNDEFINED
;
3433 targ
->insn_type
= ITYPE_LABEL
;
3434 targ
->is_specific_opcode
= FALSE
;
3435 /* Literal with no ops is a label? */
3436 assert (op
== NULL
);
3447 /* Return TRUE on success. */
3450 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3452 for (; bi
!= NULL
; bi
= bi
->next
)
3454 TInsn
*next_insn
= istack_push_space (istack
);
3456 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3463 /* Return TRUE on valid expansion. */
3466 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3468 int stack_size
= istack
->ninsn
;
3469 int steps_taken
= 0;
3470 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3473 assert (insn
->insn_type
== ITYPE_INSN
);
3474 assert (insn
->opcode
< table
->num_opcodes
);
3476 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3478 TransitionRule
*rule
= l
->rule
;
3480 if (xg_instruction_matches_rule (insn
, rule
))
3482 if (lateral_steps
== steps_taken
)
3486 /* This is it. Expand the rule to the stack. */
3487 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3490 /* Check to see if it fits. */
3491 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3493 TInsn
*insn
= &istack
->insn
[i
];
3495 if (insn
->insn_type
== ITYPE_INSN
3496 && !tinsn_has_symbolic_operands (insn
)
3497 && !xg_immeds_fit (insn
))
3499 istack
->ninsn
= stack_size
;
3512 /* Relax the assembly instruction at least "min_steps".
3513 Return the number of steps taken.
3515 For relaxation to correctly terminate, every relaxation chain must
3516 terminate in one of two ways:
3518 1. If the chain from one instruction to the next consists entirely of
3519 single instructions, then the chain *must* handle all possible
3520 immediates without failing. It must not ever fail because an
3521 immediate is out of range. The MOVI.N -> MOVI -> L32R relaxation
3522 chain is one example. L32R loads 32 bits, and there cannot be an
3523 immediate larger than 32 bits, so it satisfies this condition.
3524 Single instruction relaxation chains are as defined by
3525 xg_is_single_relaxable_instruction.
3527 2. Otherwise, the chain must end in a multi-instruction expansion: e.g.,
3528 BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J
3530 Strictly speaking, in most cases you can violate condition 1 and be OK
3531 -- in particular when the last two instructions have the same single
3532 size. But nevertheless, you should guarantee the above two conditions.
3534 We could fix this so that single-instruction expansions correctly
3535 terminate when they can't handle the range, but the error messages are
3536 worse, and it actually turns out that in every case but one (18-bit wide
3537 branches), you need a multi-instruction expansion to get the full range
3538 anyway. And because 18-bit branches are handled identically to 15-bit
3539 branches, there isn't any point in changing it. */
3542 xg_assembly_relax (IStack
*istack
,
3545 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3546 offsetT pc_offset
, /* offset in fragment */
3547 int min_steps
, /* minimum conversion steps */
3548 long stretch
) /* number of bytes stretched so far */
3550 int steps_taken
= 0;
3552 /* Some of its immeds don't fit. Try to build a relaxed version.
3553 This may go through a couple of stages of single instruction
3554 transformations before we get there. */
3556 TInsn single_target
;
3558 int lateral_steps
= 0;
3559 int istack_size
= istack
->ninsn
;
3561 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3562 && steps_taken
>= min_steps
)
3564 istack_push (istack
, insn
);
3567 current_insn
= *insn
;
3569 /* Walk through all of the single instruction expansions. */
3570 while (xg_is_single_relaxable_insn (¤t_insn
, &single_target
, FALSE
))
3573 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3576 if (steps_taken
>= min_steps
)
3578 istack_push (istack
, &single_target
);
3582 current_insn
= single_target
;
3585 /* Now check for a multi-instruction expansion. */
3586 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3588 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3591 if (steps_taken
>= min_steps
)
3593 istack_push (istack
, ¤t_insn
);
3598 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3600 if (steps_taken
>= min_steps
)
3604 istack
->ninsn
= istack_size
;
3607 /* It's not going to work -- use the original. */
3608 istack_push (istack
, insn
);
3614 xg_finish_frag (char *last_insn
,
3615 enum xtensa_relax_statesE frag_state
,
3616 enum xtensa_relax_statesE slot0_state
,
3618 bfd_boolean is_insn
)
3620 /* Finish off this fragment so that it has at LEAST the desired
3621 max_growth. If it doesn't fit in this fragment, close this one
3622 and start a new one. In either case, return a pointer to the
3623 beginning of the growth area. */
3627 frag_grow (max_growth
);
3628 old_frag
= frag_now
;
3630 frag_now
->fr_opcode
= last_insn
;
3632 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3634 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3635 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3637 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3638 xtensa_set_frag_assembly_state (frag_now
);
3640 /* Just to make sure that we did not split it up. */
3641 assert (old_frag
->fr_next
== frag_now
);
3645 /* Return TRUE if the target frag is one of the next non-empty frags. */
3648 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3653 for (; fragP
; fragP
= fragP
->fr_next
)
3655 if (fragP
== target
)
3657 if (fragP
->fr_fix
!= 0)
3659 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3661 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3662 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3664 if (fragP
->fr_type
== rs_space
)
3672 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3674 xtensa_isa isa
= xtensa_default_isa
;
3676 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3681 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) != 1
3682 && xtensa_opcode_is_jump (isa
, insn
->opcode
) != 1)
3685 for (i
= 0; i
< num_ops
; i
++)
3687 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3693 if (target_op
== -1)
3696 if (insn
->ntok
<= target_op
)
3699 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3702 sym
= insn
->tok
[target_op
].X_add_symbol
;
3706 if (insn
->tok
[target_op
].X_add_number
!= 0)
3709 target_frag
= symbol_get_frag (sym
);
3710 if (target_frag
== NULL
)
3713 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3714 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3722 xg_add_branch_and_loop_targets (TInsn
*insn
)
3724 xtensa_isa isa
= xtensa_default_isa
;
3725 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3727 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3730 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3731 && insn
->tok
[i
].X_op
== O_symbol
)
3732 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3736 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3737 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3741 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3743 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3744 && insn
->tok
[i
].X_op
== O_symbol
)
3746 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3747 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3748 if (S_IS_DEFINED (sym
))
3749 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3756 /* Return FALSE if no error. */
3759 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3764 switch (instr_spec
->typ
)
3767 new_insn
->insn_type
= ITYPE_INSN
;
3768 new_insn
->opcode
= instr_spec
->opcode
;
3770 case INSTR_LITERAL_DEF
:
3771 new_insn
->insn_type
= ITYPE_LITERAL
;
3772 new_insn
->opcode
= XTENSA_UNDEFINED
;
3774 case INSTR_LABEL_DEF
:
3777 new_insn
->is_specific_opcode
= FALSE
;
3778 new_insn
->debug_line
= old_insn
->debug_line
;
3779 new_insn
->loc_directive_seen
= old_insn
->loc_directive_seen
;
3781 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3784 const expressionS
*src_exp
;
3790 /* The expression must be the constant. */
3791 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3792 exp
= &new_insn
->tok
[b_op
->op_num
];
3793 set_expr_const (exp
, b_op
->op_data
);
3797 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3798 assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
3799 src_exp
= &old_insn
->tok
[b_op
->op_data
];
3800 exp
= &new_insn
->tok
[b_op
->op_num
];
3801 copy_expr (exp
, src_exp
);
3806 as_bad (_("can't handle generation of literal/labels yet"));
3810 as_bad (_("can't handle undefined OP TYPE"));
3815 new_insn
->ntok
= num_ops
;
3820 /* Return TRUE if it was simplified. */
3823 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
3825 TransitionRule
*rule
;
3826 BuildInstr
*insn_spec
;
3828 if (old_insn
->is_specific_opcode
|| !density_supported
)
3831 rule
= xg_instruction_match (old_insn
);
3835 insn_spec
= rule
->to_instr
;
3836 /* There should only be one. */
3837 assert (insn_spec
!= NULL
);
3838 assert (insn_spec
->next
== NULL
);
3839 if (insn_spec
->next
!= NULL
)
3842 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
3848 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3849 l32i.n. (2) Check the number of operands. (3) Place the instruction
3850 tokens into the stack or relax it and place multiple
3851 instructions/literals onto the stack. Return FALSE if no error. */
3854 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
3858 bfd_boolean do_expand
;
3860 tinsn_init (&new_insn
);
3862 /* Narrow it if we can. xg_simplify_insn now does all the
3863 appropriate checking (e.g., for the density option). */
3864 if (xg_simplify_insn (orig_insn
, &new_insn
))
3865 orig_insn
= &new_insn
;
3867 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
3869 if (orig_insn
->ntok
< noperands
)
3871 as_bad (_("found %d operands for '%s': Expected %d"),
3873 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3877 if (orig_insn
->ntok
> noperands
)
3878 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
3880 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3883 /* If there are not enough operands, we will assert above. If there
3884 are too many, just cut out the extras here. */
3885 orig_insn
->ntok
= noperands
;
3887 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
3890 /* Special case for extui opcode which has constraints not handled
3891 by the ordinary operand encoding checks. The number of operands
3892 and related syntax issues have already been checked. */
3893 if (orig_insn
->opcode
== xtensa_extui_opcode
)
3895 int shiftimm
= orig_insn
->tok
[2].X_add_number
;
3896 int maskimm
= orig_insn
->tok
[3].X_add_number
;
3897 if (shiftimm
+ maskimm
> 32)
3899 as_bad (_("immediate operands sum to greater than 32"));
3904 /* If the instruction will definitely need to be relaxed, it is better
3905 to expand it now for better scheduling. Decide whether to expand
3907 do_expand
= (!orig_insn
->is_specific_opcode
&& use_transform ());
3909 /* Calls should be expanded to longcalls only in the backend relaxation
3910 so that the assembly scheduler will keep the L32R/CALLX instructions
3912 if (is_direct_call_opcode (orig_insn
->opcode
))
3915 if (tinsn_has_symbolic_operands (orig_insn
))
3917 /* The values of symbolic operands are not known yet, so only expand
3918 now if an operand is "complex" (e.g., difference of symbols) and
3919 will have to be stored as a literal regardless of the value. */
3920 if (!tinsn_has_complex_operands (orig_insn
))
3923 else if (xg_immeds_fit (orig_insn
))
3927 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
3929 istack_push (istack
, orig_insn
);
3935 /* Return TRUE if the section flags are marked linkonce
3936 or the name is .gnu.linkonce.*. */
3938 static int linkonce_len
= sizeof (".gnu.linkonce.") - 1;
3941 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
3943 flagword flags
, link_once_flags
;
3945 flags
= bfd_get_section_flags (abfd
, sec
);
3946 link_once_flags
= (flags
& SEC_LINK_ONCE
);
3948 /* Flags might not be set yet. */
3949 if (!link_once_flags
3950 && strncmp (segment_name (sec
), ".gnu.linkonce.", linkonce_len
) == 0)
3951 link_once_flags
= SEC_LINK_ONCE
;
3953 return (link_once_flags
!= 0);
3958 xtensa_add_literal_sym (symbolS
*sym
)
3962 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
3964 l
->next
= literal_syms
;
3970 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
3972 static int lit_num
= 0;
3973 static char name
[256];
3976 sprintf (name
, ".L_lit_sym%d", lit_num
);
3978 /* Create a local symbol. If it is in a linkonce section, we have to
3979 be careful to make sure that if it is used in a relocation that the
3980 symbol will be in the output file. */
3981 if (get_is_linkonce_section (stdoutput
, sec
))
3983 symbolP
= symbol_new (name
, sec
, 0, frag
);
3984 S_CLEAR_EXTERNAL (symbolP
);
3985 /* symbolP->local = 1; */
3988 symbolP
= symbol_new (name
, sec
, 0, frag
);
3990 xtensa_add_literal_sym (symbolP
);
3997 /* Currently all literals that are generated here are 32-bit L32R targets. */
4000 xg_assemble_literal (/* const */ TInsn
*insn
)
4003 symbolS
*lit_sym
= NULL
;
4004 bfd_reloc_code_real_type reloc
;
4005 bfd_boolean pcrel
= FALSE
;
4008 /* size = 4 for L32R. It could easily be larger when we move to
4009 larger constants. Add a parameter later. */
4010 offsetT litsize
= 4;
4011 offsetT litalign
= 2; /* 2^2 = 4 */
4012 expressionS saved_loc
;
4013 expressionS
* emit_val
;
4015 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
4017 assert (insn
->insn_type
== ITYPE_LITERAL
);
4018 assert (insn
->ntok
== 1); /* must be only one token here */
4020 xtensa_switch_to_literal_fragment (&state
);
4022 emit_val
= &insn
->tok
[0];
4023 if (emit_val
->X_op
== O_big
)
4025 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
4028 /* This happens when someone writes a "movi a2, big_number". */
4029 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4030 _("invalid immediate"));
4031 xtensa_restore_emit_state (&state
);
4036 /* Force a 4-byte align here. Note that this opens a new frag, so all
4037 literals done with this function have a frag to themselves. That's
4038 important for the way text section literals work. */
4039 frag_align (litalign
, 0, 0);
4040 record_alignment (now_seg
, litalign
);
4042 switch (emit_val
->X_op
)
4048 p
= frag_more (litsize
);
4049 xtensa_set_frag_assembly_state (frag_now
);
4050 reloc
= map_operator_to_reloc (emit_val
->X_op
);
4051 if (emit_val
->X_add_symbol
)
4052 emit_val
->X_op
= O_symbol
;
4054 emit_val
->X_op
= O_constant
;
4055 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
4056 litsize
, emit_val
, pcrel
, reloc
);
4060 emit_expr (emit_val
, litsize
);
4064 assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
4065 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4066 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4067 lit_sym
= frag_now
->fr_symbol
;
4070 xtensa_restore_emit_state (&state
);
4076 xg_assemble_literal_space (/* const */ int size
, int slot
)
4079 /* We might have to do something about this alignment. It only
4080 takes effect if something is placed here. */
4081 offsetT litalign
= 2; /* 2^2 = 4 */
4082 fragS
*lit_saved_frag
;
4084 assert (size
% 4 == 0);
4086 xtensa_switch_to_literal_fragment (&state
);
4088 /* Force a 4-byte align here. */
4089 frag_align (litalign
, 0, 0);
4090 record_alignment (now_seg
, litalign
);
4094 lit_saved_frag
= frag_now
;
4095 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4096 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4097 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4100 xtensa_restore_emit_state (&state
);
4101 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4105 /* Put in a fixup record based on the opcode.
4106 Return TRUE on success. */
4109 xg_add_opcode_fix (TInsn
*tinsn
,
4117 xtensa_opcode opcode
= tinsn
->opcode
;
4118 bfd_reloc_code_real_type reloc
;
4119 reloc_howto_type
*howto
;
4123 reloc
= BFD_RELOC_NONE
;
4125 /* First try the special cases for "alternate" relocs. */
4126 if (opcode
== xtensa_l32r_opcode
)
4128 if (fragP
->tc_frag_data
.use_absolute_literals
)
4129 reloc
= encode_alt_reloc (slot
);
4131 else if (opcode
== xtensa_const16_opcode
)
4133 if (expr
->X_op
== O_lo16
)
4135 reloc
= encode_reloc (slot
);
4136 expr
->X_op
= O_symbol
;
4138 else if (expr
->X_op
== O_hi16
)
4140 reloc
= encode_alt_reloc (slot
);
4141 expr
->X_op
= O_symbol
;
4145 if (opnum
!= get_relaxable_immed (opcode
))
4147 as_bad (_("invalid relocation for operand %i of '%s'"),
4148 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4152 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4153 into the symbol table where the generic portions of the assembler
4154 won't know what to do with them. */
4155 if (expr
->X_op
== O_lo16
|| expr
->X_op
== O_hi16
)
4157 as_bad (_("invalid expression for operand %i of '%s'"),
4158 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4162 /* Next try the generic relocs. */
4163 if (reloc
== BFD_RELOC_NONE
)
4164 reloc
= encode_reloc (slot
);
4165 if (reloc
== BFD_RELOC_NONE
)
4167 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4171 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4174 as_bad (_("undefined symbol for opcode \"%s\""),
4175 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4179 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4180 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, expr
,
4181 howto
->pc_relative
, reloc
);
4182 the_fix
->fx_no_overflow
= 1;
4183 the_fix
->tc_fix_data
.X_add_symbol
= expr
->X_add_symbol
;
4184 the_fix
->tc_fix_data
.X_add_number
= expr
->X_add_number
;
4185 the_fix
->tc_fix_data
.slot
= slot
;
4192 xg_emit_insn_to_buf (TInsn
*tinsn
,
4196 bfd_boolean build_fix
)
4198 static xtensa_insnbuf insnbuf
= NULL
;
4199 bfd_boolean has_symbolic_immed
= FALSE
;
4200 bfd_boolean ok
= TRUE
;
4203 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4205 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4206 if (has_symbolic_immed
&& build_fix
)
4209 xtensa_format fmt
= xg_get_single_format (tinsn
->opcode
);
4210 int slot
= xg_get_single_slot (tinsn
->opcode
);
4211 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4212 expressionS
*exp
= &tinsn
->tok
[opnum
];
4214 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, slot
, exp
, fragP
, offset
))
4217 fragP
->tc_frag_data
.is_insn
= TRUE
;
4218 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4219 (unsigned char *) buf
, 0);
4225 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4227 symbolS
*sym
= get_special_literal_symbol ();
4231 assert (insn
->insn_type
== ITYPE_INSN
);
4232 for (i
= 0; i
< insn
->ntok
; i
++)
4233 if (insn
->tok
[i
].X_add_symbol
== sym
)
4234 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4240 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4242 symbolS
*sym
= get_special_label_symbol ();
4244 for (i
= 0; i
< insn
->ntok
; i
++)
4245 if (insn
->tok
[i
].X_add_symbol
== sym
)
4246 insn
->tok
[i
].X_add_symbol
= label_sym
;
4251 /* Return TRUE if the instruction can write to the specified
4252 integer register. */
4255 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4259 xtensa_isa isa
= xtensa_default_isa
;
4261 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4263 for (i
= 0; i
< num_ops
; i
++)
4266 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4267 if ((inout
== 'o' || inout
== 'm')
4268 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4270 xtensa_regfile opnd_rf
=
4271 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4272 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4274 if ((insn
->tok
[i
].X_op
== O_register
)
4275 && (insn
->tok
[i
].X_add_number
== regnum
))
4285 is_bad_loopend_opcode (const TInsn
*tinsn
)
4287 xtensa_opcode opcode
= tinsn
->opcode
;
4289 if (opcode
== XTENSA_UNDEFINED
)
4292 if (opcode
== xtensa_call0_opcode
4293 || opcode
== xtensa_callx0_opcode
4294 || opcode
== xtensa_call4_opcode
4295 || opcode
== xtensa_callx4_opcode
4296 || opcode
== xtensa_call8_opcode
4297 || opcode
== xtensa_callx8_opcode
4298 || opcode
== xtensa_call12_opcode
4299 || opcode
== xtensa_callx12_opcode
4300 || opcode
== xtensa_isync_opcode
4301 || opcode
== xtensa_ret_opcode
4302 || opcode
== xtensa_ret_n_opcode
4303 || opcode
== xtensa_retw_opcode
4304 || opcode
== xtensa_retw_n_opcode
4305 || opcode
== xtensa_waiti_opcode
4306 || opcode
== xtensa_rsr_lcount_opcode
)
4313 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4314 This allows the debugger to add unaligned labels.
4315 Also, the assembler generates stabs labels that need
4316 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4319 is_unaligned_label (symbolS
*sym
)
4321 const char *name
= S_GET_NAME (sym
);
4322 static size_t fake_size
= 0;
4326 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4329 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4331 fake_size
= strlen (FAKE_LABEL_NAME
);
4334 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4335 && (name
[fake_size
] == 'F'
4336 || name
[fake_size
] == 'L'
4337 || (name
[fake_size
] == 'e'
4338 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4346 next_non_empty_frag (const fragS
*fragP
)
4348 fragS
*next_fragP
= fragP
->fr_next
;
4350 /* Sometimes an empty will end up here due storage allocation issues.
4351 So we have to skip until we find something legit. */
4352 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4353 next_fragP
= next_fragP
->fr_next
;
4355 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4363 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4365 xtensa_opcode out_opcode
;
4366 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4368 if (next_fragP
== NULL
)
4371 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4372 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4374 *opcode
= out_opcode
;
4382 frag_format_size (const fragS
*fragP
)
4384 static xtensa_insnbuf insnbuf
= NULL
;
4385 xtensa_isa isa
= xtensa_default_isa
;
4390 insnbuf
= xtensa_insnbuf_alloc (isa
);
4393 return XTENSA_UNDEFINED
;
4395 xtensa_insnbuf_from_chars (isa
, insnbuf
,
4396 (unsigned char *) fragP
->fr_literal
, 0);
4398 fmt
= xtensa_format_decode (isa
, insnbuf
);
4399 if (fmt
== XTENSA_UNDEFINED
)
4400 return XTENSA_UNDEFINED
;
4401 fmt_size
= xtensa_format_length (isa
, fmt
);
4403 /* If the next format won't be changing due to relaxation, just
4404 return the length of the first format. */
4405 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4408 /* If during relaxation we have to pull an instruction out of a
4409 multi-slot instruction, we will return the more conservative
4410 number. This works because alignment on bigger instructions
4411 is more restrictive than alignment on smaller instructions.
4412 This is more conservative than we would like, but it happens
4415 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4418 /* If we aren't doing one of our own relaxations or it isn't
4419 slot-based, then the insn size won't change. */
4420 if (fragP
->fr_type
!= rs_machine_dependent
)
4422 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4425 /* If an instruction is about to grow, return the longer size. */
4426 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4427 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
4428 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP3
)
4430 /* For most frags at RELAX_IMMED_STEPX, with X > 0, the first
4431 instruction in the relaxed version is of length 3. (The case
4432 where we have to pull the instruction out of a FLIX bundle
4433 is handled conservatively above.) However, frags with opcodes
4434 that are expanding to wide branches end up having formats that
4435 are not determinable by the RELAX_IMMED_STEPX enumeration, and
4436 we can't tell directly what format the relaxer picked. This
4437 is a wart in the design of the relaxer that should someday be
4438 fixed, but would require major changes, or at least should
4439 be accompanied by major changes to make use of that data.
4441 In any event, we can tell that we are expanding from a single-slot
4442 three-byte format to a wider one with the logic below. */
4444 if (fmt_size
<= 3 && fragP
->tc_frag_data
.text_expansion
[0] != 3)
4445 return 3 + fragP
->tc_frag_data
.text_expansion
[0];
4450 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4451 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4458 next_frag_format_size (const fragS
*fragP
)
4460 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4461 return frag_format_size (next_fragP
);
4465 /* In early Xtensa Processors, for reasons that are unclear, the ISA
4466 required two-byte instructions to be treated as three-byte instructions
4467 for loop instruction alignment. This restriction was removed beginning
4468 with Xtensa LX. Now the only requirement on loop instruction alignment
4469 is that the first instruction of the loop must appear at an address that
4470 does not cross a fetch boundary. */
4473 get_loop_align_size (int insn_size
)
4475 if (insn_size
== XTENSA_UNDEFINED
)
4476 return xtensa_fetch_width
;
4478 if (enforce_three_byte_loop_align
&& insn_size
== 2)
4485 /* If the next legit fragment is an end-of-loop marker,
4486 switch its state so it will instantiate a NOP. */
4489 update_next_frag_state (fragS
*fragP
)
4491 fragS
*next_fragP
= fragP
->fr_next
;
4492 fragS
*new_target
= NULL
;
4496 /* We are guaranteed there will be one of these... */
4497 while (!(next_fragP
->fr_type
== rs_machine_dependent
4498 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4499 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4500 next_fragP
= next_fragP
->fr_next
;
4502 assert (next_fragP
->fr_type
== rs_machine_dependent
4503 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4504 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4506 /* ...and one of these. */
4507 new_target
= next_fragP
->fr_next
;
4508 while (!(new_target
->fr_type
== rs_machine_dependent
4509 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4510 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4511 new_target
= new_target
->fr_next
;
4513 assert (new_target
->fr_type
== rs_machine_dependent
4514 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4515 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4518 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4520 if (next_fragP
->fr_type
== rs_machine_dependent
4521 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4523 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4527 next_fragP
= next_fragP
->fr_next
;
4533 next_frag_is_branch_target (const fragS
*fragP
)
4535 /* Sometimes an empty will end up here due to storage allocation issues,
4536 so we have to skip until we find something legit. */
4537 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4539 if (fragP
->tc_frag_data
.is_branch_target
)
4541 if (fragP
->fr_fix
!= 0)
4549 next_frag_is_loop_target (const fragS
*fragP
)
4551 /* Sometimes an empty will end up here due storage allocation issues.
4552 So we have to skip until we find something legit. */
4553 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4555 if (fragP
->tc_frag_data
.is_loop_target
)
4557 if (fragP
->fr_fix
!= 0)
4565 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4567 const fragS
*next_fragp
= fragp
->fr_next
;
4568 xtensa_opcode next_opcode
;
4570 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4573 /* Sometimes an empty will end up here due to storage allocation issues,
4574 so we have to skip until we find something legit. */
4575 while (next_fragp
->fr_fix
== 0)
4576 next_fragp
= next_fragp
->fr_next
;
4578 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4581 /* There is some implicit knowledge encoded in here.
4582 The LOOP instructions that are NOT RELAX_IMMED have
4583 been relaxed. Note that we can assume that the LOOP
4584 instruction is in slot 0 because loops aren't bundleable. */
4585 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4586 return get_expanded_loop_offset (next_opcode
);
4592 /* Mark a location where we can later insert literal frags. Update
4593 the section's literal_pool_loc, so subsequent literals can be
4594 placed nearest to their use. */
4597 xtensa_mark_literal_pool_location (void)
4599 /* Any labels pointing to the current location need
4600 to be adjusted to after the literal pool. */
4602 fragS
*pool_location
;
4604 if (use_literal_section
)
4607 /* We stash info in these frags so we can later move the literal's
4608 fixes into this frchain's fix list. */
4609 pool_location
= frag_now
;
4610 frag_now
->tc_frag_data
.lit_frchain
= frchain_now
;
4611 frag_now
->tc_frag_data
.literal_frag
= frag_now
;
4612 frag_variant (rs_machine_dependent
, 0, 0,
4613 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4614 xtensa_set_frag_assembly_state (frag_now
);
4615 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
4616 frag_variant (rs_machine_dependent
, 0, 0,
4617 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4618 xtensa_set_frag_assembly_state (frag_now
);
4620 /* Now put a frag into the literal pool that points to this location. */
4621 set_literal_pool_location (now_seg
, pool_location
);
4622 xtensa_switch_to_non_abs_literal_fragment (&s
);
4623 frag_align (2, 0, 0);
4624 record_alignment (now_seg
, 2);
4626 /* Close whatever frag is there. */
4627 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4628 xtensa_set_frag_assembly_state (frag_now
);
4629 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
4630 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4631 xtensa_restore_emit_state (&s
);
4632 xtensa_set_frag_assembly_state (frag_now
);
4636 /* Build a nop of the correct size into tinsn. */
4639 build_nop (TInsn
*tinsn
, int size
)
4645 tinsn
->opcode
= xtensa_nop_n_opcode
;
4647 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4648 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4652 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4654 tinsn
->opcode
= xtensa_or_opcode
;
4655 set_expr_const (&tinsn
->tok
[0], 1);
4656 set_expr_const (&tinsn
->tok
[1], 1);
4657 set_expr_const (&tinsn
->tok
[2], 1);
4661 tinsn
->opcode
= xtensa_nop_opcode
;
4663 assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4668 /* Assemble a NOP of the requested size in the buffer. User must have
4669 allocated "buf" with at least "size" bytes. */
4672 assemble_nop (int size
, char *buf
)
4674 static xtensa_insnbuf insnbuf
= NULL
;
4677 build_nop (&tinsn
, size
);
4680 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4682 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4683 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4684 (unsigned char *) buf
, 0);
4688 /* Return the number of bytes for the offset of the expanded loop
4689 instruction. This should be incorporated into the relaxation
4690 specification but is hard-coded here. This is used to auto-align
4691 the loop instruction. It is invalid to call this function if the
4692 configuration does not have loops or if the opcode is not a loop
4696 get_expanded_loop_offset (xtensa_opcode opcode
)
4698 /* This is the OFFSET of the loop instruction in the expanded loop.
4699 This MUST correspond directly to the specification of the loop
4700 expansion. It will be validated on fragment conversion. */
4701 assert (opcode
!= XTENSA_UNDEFINED
);
4702 if (opcode
== xtensa_loop_opcode
)
4704 if (opcode
== xtensa_loopnez_opcode
)
4706 if (opcode
== xtensa_loopgtz_opcode
)
4708 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4714 get_literal_pool_location (segT seg
)
4716 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4721 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4723 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4727 /* Set frag assembly state should be called when a new frag is
4728 opened and after a frag has been closed. */
4731 xtensa_set_frag_assembly_state (fragS
*fragP
)
4733 if (!density_supported
)
4734 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4736 /* This function is called from subsegs_finish, which is called
4737 after xtensa_end, so we can't use "use_transform" or
4738 "use_schedule" here. */
4739 if (!directive_state
[directive_transform
])
4740 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4741 if (directive_state
[directive_longcalls
])
4742 fragP
->tc_frag_data
.use_longcalls
= TRUE
;
4743 fragP
->tc_frag_data
.use_absolute_literals
=
4744 directive_state
[directive_absolute_literals
];
4745 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4750 relaxable_section (asection
*sec
)
4752 return ((sec
->flags
& SEC_DEBUGGING
) == 0
4753 && strcmp (sec
->name
, ".eh_frame") != 0);
4758 xtensa_mark_frags_for_org (void)
4762 /* Walk over each fragment of all of the current segments. If we find
4763 a .org frag in any of the segments, mark all frags prior to it as
4764 "no transform", which will prevent linker optimizations from messing
4765 up the .org distance. This should be done after
4766 xtensa_find_unmarked_state_frags, because we don't want to worry here
4767 about that function trashing the data we save here. */
4769 for (seclist
= &stdoutput
->sections
;
4770 seclist
&& *seclist
;
4771 seclist
= &(*seclist
)->next
)
4773 segT sec
= *seclist
;
4774 segment_info_type
*seginfo
;
4777 flags
= bfd_get_section_flags (stdoutput
, sec
);
4778 if (flags
& SEC_DEBUGGING
)
4780 if (!(flags
& SEC_ALLOC
))
4783 seginfo
= seg_info (sec
);
4784 if (seginfo
&& seginfo
->frchainP
)
4786 fragS
*last_fragP
= seginfo
->frchainP
->frch_root
;
4787 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4788 fragP
= fragP
->fr_next
)
4790 /* cvt_frag_to_fill has changed the fr_type of org frags to
4791 rs_fill, so use the value as cached in rs_subtype here. */
4792 if (fragP
->fr_subtype
== RELAX_ORG
)
4794 while (last_fragP
!= fragP
->fr_next
)
4796 last_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4797 last_fragP
= last_fragP
->fr_next
;
4807 xtensa_find_unmarked_state_frags (void)
4811 /* Walk over each fragment of all of the current segments. For each
4812 unmarked fragment, mark it with the same info as the previous
4814 for (seclist
= &stdoutput
->sections
;
4815 seclist
&& *seclist
;
4816 seclist
= &(*seclist
)->next
)
4818 segT sec
= *seclist
;
4819 segment_info_type
*seginfo
;
4822 flags
= bfd_get_section_flags (stdoutput
, sec
);
4823 if (flags
& SEC_DEBUGGING
)
4825 if (!(flags
& SEC_ALLOC
))
4828 seginfo
= seg_info (sec
);
4829 if (seginfo
&& seginfo
->frchainP
)
4831 fragS
*last_fragP
= 0;
4832 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4833 fragP
= fragP
->fr_next
)
4835 if (fragP
->fr_fix
!= 0
4836 && !fragP
->tc_frag_data
.is_assembly_state_set
)
4838 if (last_fragP
== 0)
4840 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
4841 _("assembly state not set for first frag in section %s"),
4846 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4847 fragP
->tc_frag_data
.is_no_density
=
4848 last_fragP
->tc_frag_data
.is_no_density
;
4849 fragP
->tc_frag_data
.is_no_transform
=
4850 last_fragP
->tc_frag_data
.is_no_transform
;
4851 fragP
->tc_frag_data
.use_longcalls
=
4852 last_fragP
->tc_frag_data
.use_longcalls
;
4853 fragP
->tc_frag_data
.use_absolute_literals
=
4854 last_fragP
->tc_frag_data
.use_absolute_literals
;
4857 if (fragP
->tc_frag_data
.is_assembly_state_set
)
4866 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
4868 void *unused ATTRIBUTE_UNUSED
)
4870 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4871 segment_info_type
*seginfo
= seg_info (sec
);
4872 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4874 if (flags
& SEC_CODE
)
4876 xtensa_isa isa
= xtensa_default_isa
;
4877 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4878 while (frag
!= NULL
)
4880 if (frag
->tc_frag_data
.is_branch_target
)
4883 addressT branch_align
, frag_addr
;
4886 xtensa_insnbuf_from_chars
4887 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4888 fmt
= xtensa_format_decode (isa
, insnbuf
);
4889 op_size
= xtensa_format_length (isa
, fmt
);
4890 branch_align
= 1 << branch_align_power (sec
);
4891 frag_addr
= frag
->fr_address
% branch_align
;
4892 if (frag_addr
+ op_size
> branch_align
)
4893 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4894 _("unaligned branch target: %d bytes at 0x%lx"),
4895 op_size
, (long) frag
->fr_address
);
4897 frag
= frag
->fr_next
;
4899 xtensa_insnbuf_free (isa
, insnbuf
);
4905 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
4907 void *unused ATTRIBUTE_UNUSED
)
4909 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4910 segment_info_type
*seginfo
= seg_info (sec
);
4911 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4912 xtensa_isa isa
= xtensa_default_isa
;
4914 if (flags
& SEC_CODE
)
4916 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4917 while (frag
!= NULL
)
4919 if (frag
->tc_frag_data
.is_first_loop_insn
)
4925 xtensa_insnbuf_from_chars
4926 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4927 fmt
= xtensa_format_decode (isa
, insnbuf
);
4928 op_size
= xtensa_format_length (isa
, fmt
);
4929 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
4931 if (frag_addr
+ op_size
> xtensa_fetch_width
)
4932 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4933 _("unaligned loop: %d bytes at 0x%lx"),
4934 op_size
, (long) frag
->fr_address
);
4936 frag
= frag
->fr_next
;
4938 xtensa_insnbuf_free (isa
, insnbuf
);
4944 xg_apply_fix_value (fixS
*fixP
, valueT val
)
4946 xtensa_isa isa
= xtensa_default_isa
;
4947 static xtensa_insnbuf insnbuf
= NULL
;
4948 static xtensa_insnbuf slotbuf
= NULL
;
4951 bfd_boolean alt_reloc
;
4952 xtensa_opcode opcode
;
4953 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
4955 (void) decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
);
4957 as_fatal (_("unexpected fix"));
4961 insnbuf
= xtensa_insnbuf_alloc (isa
);
4962 slotbuf
= xtensa_insnbuf_alloc (isa
);
4965 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4966 fmt
= xtensa_format_decode (isa
, insnbuf
);
4967 if (fmt
== XTENSA_UNDEFINED
)
4968 as_fatal (_("undecodable fix"));
4969 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4970 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
4971 if (opcode
== XTENSA_UNDEFINED
)
4972 as_fatal (_("undecodable fix"));
4974 /* CONST16 immediates are not PC-relative, despite the fact that we
4975 reuse the normal PC-relative operand relocations for the low part
4976 of a CONST16 operand. */
4977 if (opcode
== xtensa_const16_opcode
)
4980 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
4981 get_relaxable_immed (opcode
), val
,
4982 fixP
->fx_file
, fixP
->fx_line
);
4984 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4985 xtensa_insnbuf_to_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4991 /* External Functions and Other GAS Hooks. */
4994 xtensa_target_format (void)
4996 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
5001 xtensa_file_arch_init (bfd
*abfd
)
5003 bfd_set_private_flags (abfd
, 0x100 | 0x200);
5008 md_number_to_chars (char *buf
, valueT val
, int n
)
5010 if (target_big_endian
)
5011 number_to_chars_bigendian (buf
, val
, n
);
5013 number_to_chars_littleendian (buf
, val
, n
);
5017 /* This function is called once, at assembler startup time. It should
5018 set up all the tables, etc. that the MD part of the assembler will
5024 segT current_section
= now_seg
;
5025 int current_subsec
= now_subseg
;
5028 xtensa_default_isa
= xtensa_isa_init (0, 0);
5029 isa
= xtensa_default_isa
;
5033 /* Set up the literal sections. */
5034 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
5036 subseg_set (current_section
, current_subsec
);
5038 xg_init_vinsn (&cur_vinsn
);
5040 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
5041 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
5042 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
5043 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
5044 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
5045 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
5046 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
5047 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
5048 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
5049 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
5050 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
5051 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
5052 xtensa_extui_opcode
= xtensa_opcode_lookup (isa
, "extui");
5053 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
5054 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
5055 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
5056 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
5057 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
5058 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
5059 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
5060 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
5061 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
5062 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
5063 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
5064 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
5065 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
5066 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
5067 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
5068 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
5069 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
5071 init_op_placement_info_table ();
5073 /* Set up the assembly state. */
5074 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5075 xtensa_set_frag_assembly_state (frag_now
);
5079 /* TC_INIT_FIX_DATA hook */
5082 xtensa_init_fix_data (fixS
*x
)
5084 x
->tc_fix_data
.slot
= 0;
5085 x
->tc_fix_data
.X_add_symbol
= NULL
;
5086 x
->tc_fix_data
.X_add_number
= 0;
5090 /* tc_frob_label hook */
5093 xtensa_frob_label (symbolS
*sym
)
5097 if (cur_vinsn
.inside_bundle
)
5099 as_bad (_("labels are not valid inside bundles"));
5103 freq
= get_subseg_target_freq (now_seg
, now_subseg
);
5105 /* Since the label was already attached to a frag associated with the
5106 previous basic block, it now needs to be reset to the current frag. */
5107 symbol_set_frag (sym
, frag_now
);
5108 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5110 if (generating_literals
)
5111 xtensa_add_literal_sym (sym
);
5113 xtensa_add_insn_label (sym
);
5115 if (symbol_get_tc (sym
)->is_loop_target
)
5117 if ((get_last_insn_flags (now_seg
, now_subseg
)
5118 & FLAG_IS_BAD_LOOPEND
) != 0)
5119 as_bad (_("invalid last instruction for a zero-overhead loop"));
5121 xtensa_set_frag_assembly_state (frag_now
);
5122 frag_var (rs_machine_dependent
, 4, 4, RELAX_LOOP_END
,
5123 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5125 xtensa_set_frag_assembly_state (frag_now
);
5126 xtensa_move_labels (frag_now
, 0);
5129 /* No target aligning in the absolute section. */
5130 if (now_seg
!= absolute_section
5131 && do_align_targets ()
5132 && !is_unaligned_label (sym
)
5133 && !generating_literals
)
5135 xtensa_set_frag_assembly_state (frag_now
);
5137 frag_var (rs_machine_dependent
,
5139 RELAX_DESIRE_ALIGN_IF_TARGET
,
5140 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5141 xtensa_set_frag_assembly_state (frag_now
);
5142 xtensa_move_labels (frag_now
, 0);
5145 /* We need to mark the following properties even if we aren't aligning. */
5147 /* If the label is already known to be a branch target, i.e., a
5148 forward branch, mark the frag accordingly. Backward branches
5149 are handled by xg_add_branch_and_loop_targets. */
5150 if (symbol_get_tc (sym
)->is_branch_target
)
5151 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5153 /* Loops only go forward, so they can be identified here. */
5154 if (symbol_get_tc (sym
)->is_loop_target
)
5155 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5157 dwarf2_emit_label (sym
);
5161 /* tc_unrecognized_line hook */
5164 xtensa_unrecognized_line (int ch
)
5169 if (cur_vinsn
.inside_bundle
== 0)
5171 /* PR8110: Cannot emit line number info inside a FLIX bundle
5172 when using --gstabs. Temporarily disable debug info. */
5173 generate_lineno_debug ();
5174 if (debug_type
== DEBUG_STABS
)
5176 xt_saved_debug_type
= debug_type
;
5177 debug_type
= DEBUG_NONE
;
5180 cur_vinsn
.inside_bundle
= 1;
5184 as_bad (_("extra opening brace"));
5190 if (cur_vinsn
.inside_bundle
)
5191 finish_vinsn (&cur_vinsn
);
5194 as_bad (_("extra closing brace"));
5199 as_bad (_("syntax error"));
5206 /* md_flush_pending_output hook */
5209 xtensa_flush_pending_output (void)
5211 /* This line fixes a bug where automatically generated gstabs info
5212 separates a function label from its entry instruction, ending up
5213 with the literal position between the function label and the entry
5214 instruction and crashing code. It only happens with --gstabs and
5215 --text-section-literals, and when several other obscure relaxation
5216 conditions are met. */
5217 if (outputting_stabs_line_debug
)
5220 if (cur_vinsn
.inside_bundle
)
5221 as_bad (_("missing closing brace"));
5223 /* If there is a non-zero instruction fragment, close it. */
5224 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5226 frag_wane (frag_now
);
5228 xtensa_set_frag_assembly_state (frag_now
);
5230 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5232 xtensa_clear_insn_labels ();
5236 /* We had an error while parsing an instruction. The string might look
5237 like this: "insn arg1, arg2 }". If so, we need to see the closing
5238 brace and reset some fields. Otherwise, the vinsn never gets closed
5239 and the num_slots field will grow past the end of the array of slots,
5240 and bad things happen. */
5243 error_reset_cur_vinsn (void)
5245 if (cur_vinsn
.inside_bundle
)
5247 if (*input_line_pointer
== '}'
5248 || *(input_line_pointer
- 1) == '}'
5249 || *(input_line_pointer
- 2) == '}')
5250 xg_clear_vinsn (&cur_vinsn
);
5256 md_assemble (char *str
)
5258 xtensa_isa isa
= xtensa_default_isa
;
5261 bfd_boolean has_underbar
= FALSE
;
5262 char *arg_strings
[MAX_INSN_ARGS
];
5264 TInsn orig_insn
; /* Original instruction from the input. */
5266 tinsn_init (&orig_insn
);
5268 /* Split off the opcode. */
5269 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5270 opname
= xmalloc (opnamelen
+ 1);
5271 memcpy (opname
, str
, opnamelen
);
5272 opname
[opnamelen
] = '\0';
5274 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5277 as_bad (_("syntax error"));
5281 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5284 /* Check for an underbar prefix. */
5287 has_underbar
= TRUE
;
5291 orig_insn
.insn_type
= ITYPE_INSN
;
5293 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5295 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5296 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5298 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5299 if (fmt
== XTENSA_UNDEFINED
)
5301 as_bad (_("unknown opcode or format name '%s'"), opname
);
5302 error_reset_cur_vinsn ();
5305 if (!cur_vinsn
.inside_bundle
)
5307 as_bad (_("format names only valid inside bundles"));
5308 error_reset_cur_vinsn ();
5311 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5312 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5314 cur_vinsn
.format
= fmt
;
5315 free (has_underbar
? opname
- 1 : opname
);
5316 error_reset_cur_vinsn ();
5320 /* Parse the arguments. */
5321 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5323 as_bad (_("syntax error"));
5324 error_reset_cur_vinsn ();
5328 /* Free the opcode and argument strings, now that they've been parsed. */
5329 free (has_underbar
? opname
- 1 : opname
);
5331 while (num_args
-- > 0)
5332 free (arg_strings
[num_args
]);
5334 /* Get expressions for invisible operands. */
5335 if (get_invisible_operands (&orig_insn
))
5337 error_reset_cur_vinsn ();
5341 /* Check for the right number and type of arguments. */
5342 if (tinsn_check_arguments (&orig_insn
))
5344 error_reset_cur_vinsn ();
5348 /* Record the line number for each TInsn, because a FLIX bundle may be
5349 spread across multiple input lines and individual instructions may be
5350 moved around in some cases. */
5351 orig_insn
.loc_directive_seen
= dwarf2_loc_directive_seen
;
5352 dwarf2_where (&orig_insn
.debug_line
);
5353 dwarf2_consume_line_info ();
5355 xg_add_branch_and_loop_targets (&orig_insn
);
5357 /* Check that immediate value for ENTRY is >= 16. */
5358 if (orig_insn
.opcode
== xtensa_entry_opcode
&& orig_insn
.ntok
>= 3)
5360 expressionS
*exp
= &orig_insn
.tok
[2];
5361 if (exp
->X_op
== O_constant
&& exp
->X_add_number
< 16)
5362 as_warn (_("entry instruction with stack decrement < 16"));
5366 assemble_tokens (opcode, tok, ntok);
5367 expand the tokens from the orig_insn into the
5368 stack of instructions that will not expand
5369 unless required at relaxation time. */
5371 if (!cur_vinsn
.inside_bundle
)
5372 emit_single_op (&orig_insn
);
5373 else /* We are inside a bundle. */
5375 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5376 cur_vinsn
.num_slots
++;
5377 if (*input_line_pointer
== '}'
5378 || *(input_line_pointer
- 1) == '}'
5379 || *(input_line_pointer
- 2) == '}')
5380 finish_vinsn (&cur_vinsn
);
5383 /* We've just emitted a new instruction so clear the list of labels. */
5384 xtensa_clear_insn_labels ();
5388 /* HANDLE_ALIGN hook */
5390 /* For a .align directive, we mark the previous block with the alignment
5391 information. This will be placed in the object file in the
5392 property section corresponding to this section. */
5395 xtensa_handle_align (fragS
*fragP
)
5398 && ! fragP
->tc_frag_data
.is_literal
5399 && (fragP
->fr_type
== rs_align
5400 || fragP
->fr_type
== rs_align_code
)
5401 && fragP
->fr_address
+ fragP
->fr_fix
> 0
5402 && fragP
->fr_offset
> 0
5403 && now_seg
!= bss_section
)
5405 fragP
->tc_frag_data
.is_align
= TRUE
;
5406 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5409 if (fragP
->fr_type
== rs_align_test
)
5412 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5414 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5415 _("unaligned entry instruction"));
5418 if (linkrelax
&& fragP
->fr_type
== rs_org
)
5419 fragP
->fr_subtype
= RELAX_ORG
;
5423 /* TC_FRAG_INIT hook */
5426 xtensa_frag_init (fragS
*frag
)
5428 xtensa_set_frag_assembly_state (frag
);
5433 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5439 /* Round up a section size to the appropriate boundary. */
5442 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5444 return size
; /* Byte alignment is fine. */
5449 md_pcrel_from (fixS
*fixP
)
5452 static xtensa_insnbuf insnbuf
= NULL
;
5453 static xtensa_insnbuf slotbuf
= NULL
;
5456 xtensa_opcode opcode
;
5459 xtensa_isa isa
= xtensa_default_isa
;
5460 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5461 bfd_boolean alt_reloc
;
5463 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5466 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
5471 insnbuf
= xtensa_insnbuf_alloc (isa
);
5472 slotbuf
= xtensa_insnbuf_alloc (isa
);
5475 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5476 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) insn_p
, 0);
5477 fmt
= xtensa_format_decode (isa
, insnbuf
);
5479 if (fmt
== XTENSA_UNDEFINED
)
5480 as_fatal (_("bad instruction format"));
5482 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5483 as_fatal (_("invalid relocation"));
5485 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5486 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5488 /* Check for "alternate" relocations (operand not specified). None
5489 of the current uses for these are really PC-relative. */
5490 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5492 if (opcode
!= xtensa_l32r_opcode
5493 && opcode
!= xtensa_const16_opcode
)
5494 as_fatal (_("invalid relocation for '%s' instruction"),
5495 xtensa_opcode_name (isa
, opcode
));
5499 opnum
= get_relaxable_immed (opcode
);
5501 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5502 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5504 as_bad_where (fixP
->fx_file
,
5506 _("invalid relocation for operand %d of '%s'"),
5507 opnum
, xtensa_opcode_name (isa
, opcode
));
5510 return 0 - opnd_value
;
5514 /* TC_FORCE_RELOCATION hook */
5517 xtensa_force_relocation (fixS
*fix
)
5519 switch (fix
->fx_r_type
)
5521 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5522 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5523 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5524 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5525 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5526 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5527 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5528 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5529 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5530 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5531 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5532 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5533 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5534 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5535 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5536 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5542 if (linkrelax
&& fix
->fx_addsy
5543 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5546 return generic_force_reloc (fix
);
5550 /* TC_VALIDATE_FIX_SUB hook */
5553 xtensa_validate_fix_sub (fixS
*fix
)
5555 segT add_symbol_segment
, sub_symbol_segment
;
5557 /* The difference of two symbols should be resolved by the assembler when
5558 linkrelax is not set. If the linker may relax the section containing
5559 the symbols, then an Xtensa DIFF relocation must be generated so that
5560 the linker knows to adjust the difference value. */
5561 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
5564 /* Make sure both symbols are in the same segment, and that segment is
5565 "normal" and relaxable. If the segment is not "normal", then the
5566 fix is not valid. If the segment is not "relaxable", then the fix
5567 should have been handled earlier. */
5568 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
5569 if (! SEG_NORMAL (add_symbol_segment
) ||
5570 ! relaxable_section (add_symbol_segment
))
5572 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
5573 return (sub_symbol_segment
== add_symbol_segment
);
5577 /* NO_PSEUDO_DOT hook */
5579 /* This function has nothing to do with pseudo dots, but this is the
5580 nearest macro to where the check needs to take place. FIXME: This
5584 xtensa_check_inside_bundle (void)
5586 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5587 as_bad (_("directives are not valid inside bundles"));
5589 /* This function must always return FALSE because it is called via a
5590 macro that has nothing to do with bundling. */
5595 /* md_elf_section_change_hook */
5598 xtensa_elf_section_change_hook (void)
5600 /* Set up the assembly state. */
5601 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5602 xtensa_set_frag_assembly_state (frag_now
);
5606 /* tc_fix_adjustable hook */
5609 xtensa_fix_adjustable (fixS
*fixP
)
5611 /* An offset is not allowed in combination with the difference of two
5612 symbols, but that cannot be easily detected after a local symbol
5613 has been adjusted to a (section+offset) form. Return 0 so that such
5614 an fix will not be adjusted. */
5615 if (fixP
->fx_subsy
&& fixP
->fx_addsy
&& fixP
->fx_offset
5616 && relaxable_section (S_GET_SEGMENT (fixP
->fx_subsy
)))
5619 /* We need the symbol name for the VTABLE entries. */
5620 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5621 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5628 /* tc_symbol_new_hook */
5630 symbolS
*expr_symbols
= NULL
;
5633 xtensa_symbol_new_hook (symbolS
*sym
)
5635 if (S_GET_SEGMENT (sym
) == expr_section
)
5637 symbol_get_tc (sym
)->next_expr_symbol
= expr_symbols
;
5644 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg
)
5646 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5649 /* Subtracted symbols are only allowed for a few relocation types, and
5650 unless linkrelax is enabled, they should not make it to this point. */
5651 if (fixP
->fx_subsy
&& !(linkrelax
&& (fixP
->fx_r_type
== BFD_RELOC_32
5652 || fixP
->fx_r_type
== BFD_RELOC_16
5653 || fixP
->fx_r_type
== BFD_RELOC_8
)))
5654 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("expression too complex"));
5656 switch (fixP
->fx_r_type
)
5658 case BFD_RELOC_32_PCREL
:
5664 switch (fixP
->fx_r_type
)
5667 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF8
;
5670 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF16
;
5673 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF32
;
5679 /* An offset is only allowed when it results from adjusting a
5680 local symbol into a section-relative offset. If the offset
5681 came from the original expression, tc_fix_adjustable will have
5682 prevented the fix from being converted to a section-relative
5683 form so that we can flag the error here. */
5684 if (fixP
->fx_offset
!= 0 && !symbol_section_p (fixP
->fx_addsy
))
5685 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5686 _("cannot represent subtraction with an offset"));
5688 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5689 - S_GET_VALUE (fixP
->fx_subsy
));
5691 /* The difference value gets written out, and the DIFF reloc
5692 identifies the address of the subtracted symbol (i.e., the one
5693 with the lowest address). */
5695 fixP
->fx_offset
-= val
;
5696 fixP
->fx_subsy
= NULL
;
5698 else if (! fixP
->fx_addsy
)
5705 case BFD_RELOC_XTENSA_PLT
:
5706 md_number_to_chars (fixpos
, val
, fixP
->fx_size
);
5707 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5710 case BFD_RELOC_XTENSA_SLOT0_OP
:
5711 case BFD_RELOC_XTENSA_SLOT1_OP
:
5712 case BFD_RELOC_XTENSA_SLOT2_OP
:
5713 case BFD_RELOC_XTENSA_SLOT3_OP
:
5714 case BFD_RELOC_XTENSA_SLOT4_OP
:
5715 case BFD_RELOC_XTENSA_SLOT5_OP
:
5716 case BFD_RELOC_XTENSA_SLOT6_OP
:
5717 case BFD_RELOC_XTENSA_SLOT7_OP
:
5718 case BFD_RELOC_XTENSA_SLOT8_OP
:
5719 case BFD_RELOC_XTENSA_SLOT9_OP
:
5720 case BFD_RELOC_XTENSA_SLOT10_OP
:
5721 case BFD_RELOC_XTENSA_SLOT11_OP
:
5722 case BFD_RELOC_XTENSA_SLOT12_OP
:
5723 case BFD_RELOC_XTENSA_SLOT13_OP
:
5724 case BFD_RELOC_XTENSA_SLOT14_OP
:
5727 /* Write the tentative value of a PC-relative relocation to a
5728 local symbol into the instruction. The value will be ignored
5729 by the linker, and it makes the object file disassembly
5730 readable when all branch targets are encoded in relocations. */
5732 assert (fixP
->fx_addsy
);
5733 if (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
5734 && !S_FORCE_RELOC (fixP
->fx_addsy
, 1))
5736 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5737 - md_pcrel_from (fixP
));
5738 (void) xg_apply_fix_value (fixP
, val
);
5741 else if (! fixP
->fx_addsy
)
5744 if (xg_apply_fix_value (fixP
, val
))
5749 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5750 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5751 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5752 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5753 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5754 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5755 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5756 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5757 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5758 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5759 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5760 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5761 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5762 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5763 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5764 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5765 /* These all need to be resolved at link-time. Do nothing now. */
5768 case BFD_RELOC_VTABLE_INHERIT
:
5769 case BFD_RELOC_VTABLE_ENTRY
:
5774 as_bad (_("unhandled local relocation fix %s"),
5775 bfd_get_reloc_code_name (fixP
->fx_r_type
));
5781 md_atof (int type
, char *litP
, int *sizeP
)
5783 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
5788 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
5790 return total_frag_text_expansion (fragP
);
5794 /* Translate internal representation of relocation info to BFD target
5798 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
5802 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
5803 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5804 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5805 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5807 /* Make sure none of our internal relocations make it this far.
5808 They'd better have been fully resolved by this point. */
5809 assert ((int) fixp
->fx_r_type
> 0);
5811 reloc
->addend
= fixp
->fx_offset
;
5813 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
5814 if (reloc
->howto
== NULL
)
5816 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5817 _("cannot represent `%s' relocation in object file"),
5818 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5819 free (reloc
->sym_ptr_ptr
);
5824 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
5825 as_fatal (_("internal error; cannot generate `%s' relocation"),
5826 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5832 /* Checks for resource conflicts between instructions. */
5834 /* The func unit stuff could be implemented as bit-vectors rather
5835 than the iterative approach here. If it ends up being too
5836 slow, we will switch it. */
5839 new_resource_table (void *data
,
5842 unit_num_copies_func uncf
,
5843 opcode_num_units_func onuf
,
5844 opcode_funcUnit_use_unit_func ouuf
,
5845 opcode_funcUnit_use_stage_func ousf
)
5848 resource_table
*rt
= (resource_table
*) xmalloc (sizeof (resource_table
));
5850 rt
->cycles
= cycles
;
5851 rt
->allocated_cycles
= cycles
;
5853 rt
->unit_num_copies
= uncf
;
5854 rt
->opcode_num_units
= onuf
;
5855 rt
->opcode_unit_use
= ouuf
;
5856 rt
->opcode_unit_stage
= ousf
;
5858 rt
->units
= (unsigned char **) xcalloc (cycles
, sizeof (unsigned char *));
5859 for (i
= 0; i
< cycles
; i
++)
5860 rt
->units
[i
] = (unsigned char *) xcalloc (nu
, sizeof (unsigned char));
5867 clear_resource_table (resource_table
*rt
)
5870 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
5871 for (j
= 0; j
< rt
->num_units
; j
++)
5872 rt
->units
[i
][j
] = 0;
5876 /* We never shrink it, just fake it into thinking so. */
5879 resize_resource_table (resource_table
*rt
, int cycles
)
5883 rt
->cycles
= cycles
;
5884 if (cycles
<= rt
->allocated_cycles
)
5887 old_cycles
= rt
->allocated_cycles
;
5888 rt
->allocated_cycles
= cycles
;
5890 rt
->units
= xrealloc (rt
->units
,
5891 rt
->allocated_cycles
* sizeof (unsigned char *));
5892 for (i
= 0; i
< old_cycles
; i
++)
5893 rt
->units
[i
] = xrealloc (rt
->units
[i
],
5894 rt
->num_units
* sizeof (unsigned char));
5895 for (i
= old_cycles
; i
< cycles
; i
++)
5896 rt
->units
[i
] = xcalloc (rt
->num_units
, sizeof (unsigned char));
5901 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5904 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5906 for (i
= 0; i
< uses
; i
++)
5908 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5909 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5910 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
5911 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
5912 if (copies_in_use
>= copies
)
5920 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5923 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5925 for (i
= 0; i
< uses
; i
++)
5927 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5928 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5929 /* Note that this allows resources to be oversubscribed. That's
5930 essential to the way the optional scheduler works.
5931 resources_available reports when a resource is over-subscribed,
5932 so it's easy to tell. */
5933 rt
->units
[stage
+ cycle
][unit
]++;
5939 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5942 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5944 for (i
= 0; i
< uses
; i
++)
5946 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5947 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5948 assert (rt
->units
[stage
+ cycle
][unit
] > 0);
5949 rt
->units
[stage
+ cycle
][unit
]--;
5954 /* Wrapper functions make parameterized resource reservation
5958 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
5960 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5966 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
5968 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5973 /* Note that this function does not check issue constraints, but
5974 solely whether the hardware is available to execute the given
5975 instructions together. It also doesn't check if the tinsns
5976 write the same state, or access the same tieports. That is
5977 checked by check_t1_t2_reads_and_writes. */
5980 resources_conflict (vliw_insn
*vinsn
)
5983 static resource_table
*rt
= NULL
;
5985 /* This is the most common case by far. Optimize it. */
5986 if (vinsn
->num_slots
== 1)
5991 xtensa_isa isa
= xtensa_default_isa
;
5992 rt
= new_resource_table
5993 (isa
, xtensa_isa_num_pipe_stages (isa
),
5994 xtensa_isa_num_funcUnits (isa
),
5995 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
5996 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
5997 opcode_funcUnit_use_unit
,
5998 opcode_funcUnit_use_stage
);
6001 clear_resource_table (rt
);
6003 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6005 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
6007 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
6014 /* finish_vinsn, emit_single_op and helper functions. */
6016 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
6017 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
6018 static void xg_assemble_vliw_tokens (vliw_insn
*);
6021 /* We have reached the end of a bundle; emit into the frag. */
6024 finish_vinsn (vliw_insn
*vinsn
)
6031 if (find_vinsn_conflicts (vinsn
))
6033 xg_clear_vinsn (vinsn
);
6037 /* First, find a format that works. */
6038 if (vinsn
->format
== XTENSA_UNDEFINED
)
6039 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6041 if (vinsn
->format
== XTENSA_UNDEFINED
)
6043 as_where (&file_name
, &line
);
6044 as_bad_where (file_name
, line
,
6045 _("couldn't find a valid instruction format"));
6046 fprintf (stderr
, _(" ops were: "));
6047 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6048 fprintf (stderr
, _(" %s;"),
6049 xtensa_opcode_name (xtensa_default_isa
,
6050 vinsn
->slots
[i
].opcode
));
6051 fprintf (stderr
, _("\n"));
6052 xg_clear_vinsn (vinsn
);
6056 if (vinsn
->num_slots
6057 != xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
))
6059 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
6060 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
6061 xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
),
6063 xg_clear_vinsn (vinsn
);
6067 if (resources_conflict (vinsn
))
6069 as_where (&file_name
, &line
);
6070 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6071 fprintf (stderr
, " ops were: ");
6072 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6073 fprintf (stderr
, " %s;",
6074 xtensa_opcode_name (xtensa_default_isa
,
6075 vinsn
->slots
[i
].opcode
));
6076 fprintf (stderr
, "\n");
6077 xg_clear_vinsn (vinsn
);
6081 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6083 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
6085 symbolS
*lit_sym
= NULL
;
6087 bfd_boolean e
= FALSE
;
6088 bfd_boolean saved_density
= density_supported
;
6090 /* We don't want to narrow ops inside multi-slot bundles. */
6091 if (vinsn
->num_slots
> 1)
6092 density_supported
= FALSE
;
6094 istack_init (&slotstack
);
6095 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
6097 vinsn
->slots
[i
].opcode
=
6098 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6100 vinsn
->slots
[i
].ntok
= 0;
6103 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
6109 density_supported
= saved_density
;
6113 xg_clear_vinsn (vinsn
);
6117 for (j
= 0; j
< slotstack
.ninsn
; j
++)
6119 TInsn
*insn
= &slotstack
.insn
[j
];
6120 if (insn
->insn_type
== ITYPE_LITERAL
)
6122 assert (lit_sym
== NULL
);
6123 lit_sym
= xg_assemble_literal (insn
);
6127 assert (insn
->insn_type
== ITYPE_INSN
);
6129 xg_resolve_literals (insn
, lit_sym
);
6130 if (j
!= slotstack
.ninsn
- 1)
6131 emit_single_op (insn
);
6135 if (vinsn
->num_slots
> 1)
6137 if (opcode_fits_format_slot
6138 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6141 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6145 emit_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6146 if (vinsn
->format
== XTENSA_UNDEFINED
)
6147 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6149 vinsn
->slots
[i
].opcode
6150 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6153 vinsn
->slots
[i
].ntok
= 0;
6158 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6159 vinsn
->format
= XTENSA_UNDEFINED
;
6164 /* Now check resource conflicts on the modified bundle. */
6165 if (resources_conflict (vinsn
))
6167 as_where (&file_name
, &line
);
6168 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6169 fprintf (stderr
, " ops were: ");
6170 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6171 fprintf (stderr
, " %s;",
6172 xtensa_opcode_name (xtensa_default_isa
,
6173 vinsn
->slots
[i
].opcode
));
6174 fprintf (stderr
, "\n");
6175 xg_clear_vinsn (vinsn
);
6179 /* First, find a format that works. */
6180 if (vinsn
->format
== XTENSA_UNDEFINED
)
6181 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6183 xg_assemble_vliw_tokens (vinsn
);
6185 xg_clear_vinsn (vinsn
);
6189 /* Given an vliw instruction, what conflicts are there in register
6190 usage and in writes to states and queues?
6192 This function does two things:
6193 1. Reports an error when a vinsn contains illegal combinations
6194 of writes to registers states or queues.
6195 2. Marks individual tinsns as not relaxable if the combination
6196 contains antidependencies.
6198 Job 2 handles things like swap semantics in instructions that need
6199 to be relaxed. For example,
6203 normally would be relaxed to
6208 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6210 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6212 then we can't relax it into
6215 { add a0, a1, a0 ; add a2, a0, a4 ; }
6217 because the value of a0 is trashed before the second add can read it. */
6219 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6222 find_vinsn_conflicts (vliw_insn
*vinsn
)
6226 xtensa_isa isa
= xtensa_default_isa
;
6228 assert (!past_xtensa_end
);
6230 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6232 TInsn
*op1
= &vinsn
->slots
[i
];
6233 if (op1
->is_specific_opcode
)
6234 op1
->keep_wide
= TRUE
;
6236 op1
->keep_wide
= FALSE
;
6239 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6241 TInsn
*op1
= &vinsn
->slots
[i
];
6243 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6246 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6250 TInsn
*op2
= &vinsn
->slots
[j
];
6251 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6252 switch (conflict_type
)
6255 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6256 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6257 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6260 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6261 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6262 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6265 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"),
6266 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6267 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6270 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"),
6271 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6272 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6275 /* Everything is OK. */
6278 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6279 || conflict_type
== 'a');
6286 as_bad (_("multiple branches or jumps in the same bundle"));
6294 /* Check how the state used by t1 and t2 relate.
6297 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6298 case B: no relationship between what is read and written (both could
6299 read the same reg though)
6300 case C: t1 writes a register t2 writes (a register conflict within a
6302 case D: t1 writes a state that t2 also writes
6303 case E: t1 writes a tie queue that t2 also writes
6304 case F: two volatile queue accesses
6308 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6310 xtensa_isa isa
= xtensa_default_isa
;
6311 xtensa_regfile t1_regfile
, t2_regfile
;
6313 int t1_base_reg
, t1_last_reg
;
6314 int t2_base_reg
, t2_last_reg
;
6315 char t1_inout
, t2_inout
;
6317 char conflict
= 'b';
6322 bfd_boolean t1_volatile
= FALSE
;
6323 bfd_boolean t2_volatile
= FALSE
;
6325 /* Check registers. */
6326 for (j
= 0; j
< t2
->ntok
; j
++)
6328 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6331 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6332 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6333 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6335 for (i
= 0; i
< t1
->ntok
; i
++)
6337 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6340 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6342 if (t1_regfile
!= t2_regfile
)
6345 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6346 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6348 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6349 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6351 if (t1_inout
== 'm' || t1_inout
== 'o'
6352 || t2_inout
== 'm' || t2_inout
== 'o')
6359 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6360 t1_last_reg
= (t1_base_reg
6361 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6363 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6365 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6367 if (t1_reg
!= t2_reg
)
6370 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6376 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6382 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6390 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6391 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6392 for (j
= 0; j
< t2_states
; j
++)
6394 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6395 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6396 for (i
= 0; i
< t1_states
; i
++)
6398 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6399 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6403 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6409 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6415 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6420 /* Check tieports. */
6421 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6422 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6423 for (j
= 0; j
< t2_interfaces
; j
++)
6425 xtensa_interface t2_int
6426 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6427 int t2_class
= xtensa_interface_class_id (isa
, t2_int
);
6429 t2_inout
= xtensa_interface_inout (isa
, t2_int
);
6430 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1)
6433 for (i
= 0; i
< t1_interfaces
; i
++)
6435 xtensa_interface t1_int
6436 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6437 int t1_class
= xtensa_interface_class_id (isa
, t1_int
);
6439 t1_inout
= xtensa_interface_inout (isa
, t1_int
);
6440 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1)
6443 if (t1_volatile
&& t2_volatile
&& (t1_class
== t2_class
))
6446 if (t1_int
!= t2_int
)
6449 if (t2_inout
== 'i' && t1_inout
== 'o')
6455 if (t1_inout
== 'i' && t2_inout
== 'o')
6461 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6470 static xtensa_format
6471 xg_find_narrowest_format (vliw_insn
*vinsn
)
6473 /* Right now we assume that the ops within the vinsn are properly
6474 ordered for the slots that the programmer wanted them in. In
6475 other words, we don't rearrange the ops in hopes of finding a
6476 better format. The scheduler handles that. */
6478 xtensa_isa isa
= xtensa_default_isa
;
6479 xtensa_format format
;
6480 vliw_insn v_copy
= *vinsn
;
6481 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6483 if (vinsn
->num_slots
== 1)
6484 return xg_get_single_format (vinsn
->slots
[0].opcode
);
6486 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6489 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6493 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6495 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6497 v_copy
.slots
[slot
].opcode
=
6498 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6499 v_copy
.slots
[slot
].ntok
= 0;
6502 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6505 else if (v_copy
.num_slots
> 1)
6508 /* Try the widened version. */
6509 if (!v_copy
.slots
[slot
].keep_wide
6510 && !v_copy
.slots
[slot
].is_specific_opcode
6511 && xg_is_single_relaxable_insn (&v_copy
.slots
[slot
],
6513 && opcode_fits_format_slot (widened
.opcode
,
6516 v_copy
.slots
[slot
] = widened
;
6521 if (fit
== v_copy
.num_slots
)
6524 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6525 vinsn
->format
= format
;
6531 if (format
== xtensa_isa_num_formats (isa
))
6532 return XTENSA_UNDEFINED
;
6538 /* Return the additional space needed in a frag
6539 for possible relaxations of any ops in a VLIW insn.
6540 Also fill out the relaxations that might be required of
6541 each tinsn in the vinsn. */
6544 relaxation_requirements (vliw_insn
*vinsn
, bfd_boolean
*pfinish_frag
)
6546 bfd_boolean finish_frag
= FALSE
;
6547 int extra_space
= 0;
6550 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6552 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6553 if (!tinsn_has_symbolic_operands (tinsn
))
6555 /* A narrow instruction could be widened later to help
6556 alignment issues. */
6557 if (xg_is_single_relaxable_insn (tinsn
, 0, TRUE
)
6558 && !tinsn
->is_specific_opcode
6559 && vinsn
->num_slots
== 1)
6561 /* Difference in bytes between narrow and wide insns... */
6563 tinsn
->subtype
= RELAX_NARROW
;
6568 if (workaround_b_j_loop_end
6569 && tinsn
->opcode
== xtensa_jx_opcode
6570 && use_transform ())
6572 /* Add 2 of these. */
6573 extra_space
+= 3; /* for the nop size */
6574 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6577 /* Need to assemble it with space for the relocation. */
6578 if (xg_is_relaxable_insn (tinsn
, 0)
6579 && !tinsn
->is_specific_opcode
)
6581 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6582 int max_literal_size
=
6583 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6585 tinsn
->literal_space
= max_literal_size
;
6587 tinsn
->subtype
= RELAX_IMMED
;
6588 extra_space
+= max_size
;
6592 /* A fix record will be added for this instruction prior
6593 to relaxation, so make it end the frag. */
6598 *pfinish_frag
= finish_frag
;
6604 bundle_tinsn (TInsn
*tinsn
, vliw_insn
*vinsn
)
6606 xtensa_isa isa
= xtensa_default_isa
;
6607 int slot
, chosen_slot
;
6609 vinsn
->format
= xg_get_single_format (tinsn
->opcode
);
6610 assert (vinsn
->format
!= XTENSA_UNDEFINED
);
6611 vinsn
->num_slots
= xtensa_format_num_slots (isa
, vinsn
->format
);
6613 chosen_slot
= xg_get_single_slot (tinsn
->opcode
);
6614 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6616 if (slot
== chosen_slot
)
6617 vinsn
->slots
[slot
] = *tinsn
;
6620 vinsn
->slots
[slot
].opcode
=
6621 xtensa_format_slot_nop_opcode (isa
, vinsn
->format
, slot
);
6622 vinsn
->slots
[slot
].ntok
= 0;
6623 vinsn
->slots
[slot
].insn_type
= ITYPE_INSN
;
6630 emit_single_op (TInsn
*orig_insn
)
6633 IStack istack
; /* put instructions into here */
6634 symbolS
*lit_sym
= NULL
;
6635 symbolS
*label_sym
= NULL
;
6637 istack_init (&istack
);
6639 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6640 Because the scheduling and bundling characteristics of movi and
6641 l32r or const16 are so different, we can do much better if we relax
6642 it prior to scheduling and bundling, rather than after. */
6643 if ((orig_insn
->opcode
== xtensa_movi_opcode
6644 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
6645 && !cur_vinsn
.inside_bundle
6646 && (orig_insn
->tok
[1].X_op
== O_symbol
6647 || orig_insn
->tok
[1].X_op
== O_pltrel
)
6648 && !orig_insn
->is_specific_opcode
&& use_transform ())
6649 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
6651 if (xg_expand_assembly_insn (&istack
, orig_insn
))
6654 for (i
= 0; i
< istack
.ninsn
; i
++)
6656 TInsn
*insn
= &istack
.insn
[i
];
6657 switch (insn
->insn_type
)
6660 assert (lit_sym
== NULL
);
6661 lit_sym
= xg_assemble_literal (insn
);
6665 static int relaxed_sym_idx
= 0;
6666 char *label
= xmalloc (strlen (FAKE_LABEL_NAME
) + 12);
6667 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
6669 assert (label_sym
== NULL
);
6670 label_sym
= symbol_find_or_make (label
);
6679 xg_resolve_literals (insn
, lit_sym
);
6681 xg_resolve_labels (insn
, label_sym
);
6683 bundle_tinsn (insn
, &v
);
6698 total_frag_text_expansion (fragS
*fragP
)
6701 int total_expansion
= 0;
6703 for (slot
= 0; slot
< MAX_SLOTS
; slot
++)
6704 total_expansion
+= fragP
->tc_frag_data
.text_expansion
[slot
];
6706 return total_expansion
;
6710 /* Emit a vliw instruction to the current fragment. */
6713 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
6715 bfd_boolean finish_frag
;
6716 bfd_boolean is_jump
= FALSE
;
6717 bfd_boolean is_branch
= FALSE
;
6718 xtensa_isa isa
= xtensa_default_isa
;
6723 struct dwarf2_line_info debug_line
;
6724 bfd_boolean loc_directive_seen
= FALSE
;
6727 memset (&debug_line
, 0, sizeof (struct dwarf2_line_info
));
6729 if (generating_literals
)
6731 static int reported
= 0;
6733 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
6734 _("cannot assemble into a literal fragment"));
6741 if (frag_now_fix () != 0
6742 && (! frag_now
->tc_frag_data
.is_insn
6743 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6744 || !use_transform () != frag_now
->tc_frag_data
.is_no_transform
6745 || (directive_state
[directive_longcalls
]
6746 != frag_now
->tc_frag_data
.use_longcalls
)
6747 || (directive_state
[directive_absolute_literals
]
6748 != frag_now
->tc_frag_data
.use_absolute_literals
)))
6750 frag_wane (frag_now
);
6752 xtensa_set_frag_assembly_state (frag_now
);
6755 if (workaround_a0_b_retw
6756 && vinsn
->num_slots
== 1
6757 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
6758 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
6759 && use_transform ())
6761 has_a0_b_retw
= TRUE
;
6763 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
6764 After the first assembly pass we will check all of them and
6765 add a nop if needed. */
6766 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6767 frag_var (rs_machine_dependent
, 4, 4,
6768 RELAX_ADD_NOP_IF_A0_B_RETW
,
6769 frag_now
->fr_symbol
,
6770 frag_now
->fr_offset
,
6772 xtensa_set_frag_assembly_state (frag_now
);
6773 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6774 frag_var (rs_machine_dependent
, 4, 4,
6775 RELAX_ADD_NOP_IF_A0_B_RETW
,
6776 frag_now
->fr_symbol
,
6777 frag_now
->fr_offset
,
6779 xtensa_set_frag_assembly_state (frag_now
);
6782 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6784 tinsn
= &vinsn
->slots
[slot
];
6786 /* See if the instruction implies an aligned section. */
6787 if (xtensa_opcode_is_loop (isa
, tinsn
->opcode
) == 1)
6788 record_alignment (now_seg
, 2);
6790 /* Determine the best line number for debug info. */
6791 if ((tinsn
->loc_directive_seen
|| !loc_directive_seen
)
6792 && (tinsn
->debug_line
.filenum
!= debug_line
.filenum
6793 || tinsn
->debug_line
.line
< debug_line
.line
6794 || tinsn
->debug_line
.column
< debug_line
.column
))
6795 debug_line
= tinsn
->debug_line
;
6796 if (tinsn
->loc_directive_seen
)
6797 loc_directive_seen
= TRUE
;
6800 /* Special cases for instructions that force an alignment... */
6801 /* None of these opcodes are bundle-able. */
6802 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
6806 /* Remember the symbol that marks the end of the loop in the frag
6807 that marks the start of the loop. This way we can easily find
6808 the end of the loop at the beginning, without adding special code
6809 to mark the loop instructions themselves. */
6810 symbolS
*target_sym
= NULL
;
6811 if (vinsn
->slots
[0].tok
[1].X_op
== O_symbol
)
6812 target_sym
= vinsn
->slots
[0].tok
[1].X_add_symbol
;
6814 xtensa_set_frag_assembly_state (frag_now
);
6815 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6817 max_fill
= get_text_align_max_fill_size
6818 (get_text_align_power (xtensa_fetch_width
),
6819 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
6821 if (use_transform ())
6822 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
6823 RELAX_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
6825 frag_var (rs_machine_dependent
, 0, 0,
6826 RELAX_CHECK_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
6827 xtensa_set_frag_assembly_state (frag_now
);
6830 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
6831 && !vinsn
->slots
[0].is_specific_opcode
)
6833 xtensa_mark_literal_pool_location ();
6834 xtensa_move_labels (frag_now
, 0);
6835 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
6838 if (vinsn
->num_slots
== 1)
6840 if (workaround_a0_b_retw
&& use_transform ())
6841 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
6842 is_register_writer (&vinsn
->slots
[0], "a", 0));
6844 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
6845 is_bad_loopend_opcode (&vinsn
->slots
[0]));
6848 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
6850 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
6852 extra_space
= relaxation_requirements (vinsn
, &finish_frag
);
6854 /* vinsn_to_insnbuf will produce the error. */
6855 if (vinsn
->format
!= XTENSA_UNDEFINED
)
6857 f
= frag_more (insn_size
+ extra_space
);
6858 xtensa_set_frag_assembly_state (frag_now
);
6859 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6862 vinsn_to_insnbuf (vinsn
, f
, frag_now
, FALSE
);
6863 if (vinsn
->format
== XTENSA_UNDEFINED
)
6866 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, (unsigned char *) f
, 0);
6868 if (debug_type
== DEBUG_DWARF2
|| loc_directive_seen
)
6869 dwarf2_gen_line_info (frag_now_fix () - (insn_size
+ extra_space
),
6872 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6874 tinsn
= &vinsn
->slots
[slot
];
6875 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
6876 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
6877 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
6878 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
6879 if (tinsn
->literal_space
!= 0)
6880 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
6882 if (tinsn
->subtype
== RELAX_NARROW
)
6883 assert (vinsn
->num_slots
== 1);
6884 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
6886 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
6889 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->offset
6890 || tinsn
->literal_frag
|| is_jump
|| is_branch
)
6894 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6895 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
6899 frag_variant (rs_machine_dependent
,
6900 extra_space
, extra_space
, RELAX_SLOTS
,
6901 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
6902 xtensa_set_frag_assembly_state (frag_now
);
6905 /* Special cases for loops:
6906 close_loop_end should be inserted AFTER short_loop.
6907 Make sure that CLOSE loops are processed BEFORE short_loops
6908 when converting them. */
6910 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
6911 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1
6912 && !vinsn
->slots
[0].is_specific_opcode
)
6914 if (workaround_short_loop
&& use_transform ())
6916 maybe_has_short_loop
= TRUE
;
6917 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6918 frag_var (rs_machine_dependent
, 4, 4,
6919 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6920 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6921 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6922 frag_var (rs_machine_dependent
, 4, 4,
6923 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6924 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6927 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
6928 loop at least 12 bytes away from another loop's end. */
6929 if (workaround_close_loop_end
&& use_transform ())
6931 maybe_has_close_loop_end
= TRUE
;
6932 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6933 frag_var (rs_machine_dependent
, 12, 12,
6934 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
6935 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6939 if (use_transform ())
6943 assert (finish_frag
);
6944 frag_var (rs_machine_dependent
,
6945 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6947 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6948 xtensa_set_frag_assembly_state (frag_now
);
6950 else if (is_branch
&& do_align_targets ())
6952 assert (finish_frag
);
6953 frag_var (rs_machine_dependent
,
6954 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6955 RELAX_MAYBE_UNREACHABLE
,
6956 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6957 xtensa_set_frag_assembly_state (frag_now
);
6958 frag_var (rs_machine_dependent
,
6960 RELAX_MAYBE_DESIRE_ALIGN
,
6961 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6962 xtensa_set_frag_assembly_state (frag_now
);
6966 /* Now, if the original opcode was a call... */
6967 if (do_align_targets ()
6968 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
6970 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
6971 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6972 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
6973 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6974 xtensa_set_frag_assembly_state (frag_now
);
6977 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6979 frag_wane (frag_now
);
6981 xtensa_set_frag_assembly_state (frag_now
);
6986 /* xtensa_end and helper functions. */
6988 static void xtensa_cleanup_align_frags (void);
6989 static void xtensa_fix_target_frags (void);
6990 static void xtensa_mark_narrow_branches (void);
6991 static void xtensa_mark_zcl_first_insns (void);
6992 static void xtensa_mark_difference_of_two_symbols (void);
6993 static void xtensa_fix_a0_b_retw_frags (void);
6994 static void xtensa_fix_b_j_loop_end_frags (void);
6995 static void xtensa_fix_close_loop_end_frags (void);
6996 static void xtensa_fix_short_loop_frags (void);
6997 static void xtensa_sanity_check (void);
6998 static void xtensa_add_config_info (void);
7003 directive_balance ();
7004 xtensa_flush_pending_output ();
7006 past_xtensa_end
= TRUE
;
7008 xtensa_move_literals ();
7010 xtensa_reorder_segments ();
7011 xtensa_cleanup_align_frags ();
7012 xtensa_fix_target_frags ();
7013 if (workaround_a0_b_retw
&& has_a0_b_retw
)
7014 xtensa_fix_a0_b_retw_frags ();
7015 if (workaround_b_j_loop_end
)
7016 xtensa_fix_b_j_loop_end_frags ();
7018 /* "close_loop_end" should be processed BEFORE "short_loop". */
7019 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
7020 xtensa_fix_close_loop_end_frags ();
7022 if (workaround_short_loop
&& maybe_has_short_loop
)
7023 xtensa_fix_short_loop_frags ();
7025 xtensa_mark_narrow_branches ();
7026 xtensa_mark_zcl_first_insns ();
7028 xtensa_sanity_check ();
7030 xtensa_add_config_info ();
7035 xtensa_cleanup_align_frags (void)
7040 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7041 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7044 /* Walk over all of the fragments in a subsection. */
7045 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7047 if ((fragP
->fr_type
== rs_align
7048 || fragP
->fr_type
== rs_align_code
7049 || (fragP
->fr_type
== rs_machine_dependent
7050 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
7051 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
7052 && fragP
->fr_fix
== 0)
7054 fragS
*next
= fragP
->fr_next
;
7057 && next
->fr_fix
== 0
7058 && next
->fr_type
== rs_machine_dependent
7059 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7062 next
= next
->fr_next
;
7065 /* If we don't widen branch targets, then they
7066 will be easier to align. */
7067 if (fragP
->tc_frag_data
.is_branch_target
7068 && fragP
->fr_opcode
== fragP
->fr_literal
7069 && fragP
->fr_type
== rs_machine_dependent
7070 && fragP
->fr_subtype
== RELAX_SLOTS
7071 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
7073 if (fragP
->fr_type
== rs_machine_dependent
7074 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
7075 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
7081 /* Re-process all of the fragments looking to convert all of the
7082 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
7083 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7084 Otherwise, convert to a .fill 0. */
7087 xtensa_fix_target_frags (void)
7092 /* When this routine is called, all of the subsections are still intact
7093 so we walk over subsections instead of sections. */
7094 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7095 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7099 /* Walk over all of the fragments in a subsection. */
7100 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7102 if (fragP
->fr_type
== rs_machine_dependent
7103 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7105 if (next_frag_is_branch_target (fragP
))
7106 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7115 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
7118 xtensa_mark_narrow_branches (void)
7123 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7124 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7127 /* Walk over all of the fragments in a subsection. */
7128 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7130 if (fragP
->fr_type
== rs_machine_dependent
7131 && fragP
->fr_subtype
== RELAX_SLOTS
7132 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7136 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7137 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
7139 if (vinsn
.num_slots
== 1
7140 && xtensa_opcode_is_branch (xtensa_default_isa
,
7141 vinsn
.slots
[0].opcode
) == 1
7142 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
7143 && is_narrow_branch_guaranteed_in_range (fragP
,
7146 fragP
->fr_subtype
= RELAX_SLOTS
;
7147 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
7148 fragP
->tc_frag_data
.is_aligning_branch
= 1;
7156 /* A branch is typically widened only when its target is out of
7157 range. However, we would like to widen them to align a subsequent
7158 branch target when possible.
7160 Because the branch relaxation code is so convoluted, the optimal solution
7161 (combining the two cases) is difficult to get right in all circumstances.
7162 We therefore go with an "almost as good" solution, where we only
7163 use for alignment narrow branches that definitely will not expand to a
7164 jump and a branch. These functions find and mark these cases. */
7166 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
7167 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7168 We start counting beginning with the frag after the 2-byte branch, so the
7169 maximum offset is (4 - 2) + 63 = 65. */
7170 #define MAX_IMMED6 65
7172 static offsetT
unrelaxed_frag_max_size (fragS
*);
7175 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
7177 const expressionS
*expr
= &tinsn
->tok
[1];
7178 symbolS
*symbolP
= expr
->X_add_symbol
;
7179 offsetT max_distance
= expr
->X_add_number
;
7182 if (expr
->X_op
!= O_symbol
)
7185 target_frag
= symbol_get_frag (symbolP
);
7187 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
7188 if (is_branch_jmp_to_next (tinsn
, fragP
))
7191 /* The branch doesn't branch over it's own frag,
7192 but over the subsequent ones. */
7193 fragP
= fragP
->fr_next
;
7194 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
7196 max_distance
+= unrelaxed_frag_max_size (fragP
);
7197 fragP
= fragP
->fr_next
;
7199 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
7206 xtensa_mark_zcl_first_insns (void)
7211 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7212 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7215 /* Walk over all of the fragments in a subsection. */
7216 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7218 if (fragP
->fr_type
== rs_machine_dependent
7219 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7220 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7222 /* Find the loop frag. */
7223 fragS
*targ_frag
= next_non_empty_frag (fragP
);
7224 /* Find the first insn frag. */
7225 targ_frag
= next_non_empty_frag (targ_frag
);
7227 /* Of course, sometimes (mostly for toy test cases) a
7228 zero-cost loop instruction is the last in a section. */
7231 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
7232 /* Do not widen a frag that is the first instruction of a
7233 zero-cost loop. It makes that loop harder to align. */
7234 if (targ_frag
->fr_type
== rs_machine_dependent
7235 && targ_frag
->fr_subtype
== RELAX_SLOTS
7236 && (targ_frag
->tc_frag_data
.slot_subtypes
[0]
7239 if (targ_frag
->tc_frag_data
.is_aligning_branch
)
7240 targ_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
7243 frag_wane (targ_frag
);
7244 targ_frag
->tc_frag_data
.slot_subtypes
[0] = 0;
7248 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
7256 /* Some difference-of-symbols expressions make it out to the linker. Some
7257 don't. If one does, then the linker can optimize between the two labels.
7258 If it doesn't, then the linker shouldn't. */
7261 xtensa_mark_difference_of_two_symbols (void)
7265 for (expr_sym
= expr_symbols
; expr_sym
;
7266 expr_sym
= symbol_get_tc (expr_sym
)->next_expr_symbol
)
7268 expressionS
*expr
= symbol_get_value_expression (expr_sym
);
7270 if (expr
->X_op
== O_subtract
)
7272 symbolS
*left
= expr
->X_add_symbol
;
7273 symbolS
*right
= expr
->X_op_symbol
;
7275 /* Difference of two symbols not in the same section
7276 are handled with relocations in the linker. */
7277 if (S_GET_SEGMENT (left
) == S_GET_SEGMENT (right
))
7282 if (symbol_get_frag (left
)->fr_address
7283 <= symbol_get_frag (right
)->fr_address
)
7285 start
= symbol_get_frag (left
);
7286 end
= symbol_get_frag (right
);
7290 start
= symbol_get_frag (right
);
7291 end
= symbol_get_frag (left
);
7295 start
->tc_frag_data
.is_no_transform
= 1;
7296 start
= start
->fr_next
;
7298 while (start
&& start
->fr_address
< end
->fr_address
);
7305 /* Re-process all of the fragments looking to convert all of the
7306 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7307 conditional branch or a retw/retw.n, convert this frag to one that
7308 will generate a NOP. In any case close it off with a .fill 0. */
7310 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
7313 xtensa_fix_a0_b_retw_frags (void)
7318 /* When this routine is called, all of the subsections are still intact
7319 so we walk over subsections instead of sections. */
7320 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7321 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7325 /* Walk over all of the fragments in a subsection. */
7326 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7328 if (fragP
->fr_type
== rs_machine_dependent
7329 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
7331 if (next_instrs_are_b_retw (fragP
))
7333 if (fragP
->tc_frag_data
.is_no_transform
)
7334 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7336 relax_frag_add_nop (fragP
);
7346 next_instrs_are_b_retw (fragS
*fragP
)
7348 xtensa_opcode opcode
;
7350 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
7351 static xtensa_insnbuf insnbuf
= NULL
;
7352 static xtensa_insnbuf slotbuf
= NULL
;
7353 xtensa_isa isa
= xtensa_default_isa
;
7356 bfd_boolean branch_seen
= FALSE
;
7360 insnbuf
= xtensa_insnbuf_alloc (isa
);
7361 slotbuf
= xtensa_insnbuf_alloc (isa
);
7364 if (next_fragP
== NULL
)
7367 /* Check for the conditional branch. */
7368 xtensa_insnbuf_from_chars
7369 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7370 fmt
= xtensa_format_decode (isa
, insnbuf
);
7371 if (fmt
== XTENSA_UNDEFINED
)
7374 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7376 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
7377 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
7379 branch_seen
= (branch_seen
7380 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
7386 offset
+= xtensa_format_length (isa
, fmt
);
7387 if (offset
== next_fragP
->fr_fix
)
7389 next_fragP
= next_non_empty_frag (next_fragP
);
7393 if (next_fragP
== NULL
)
7396 /* Check for the retw/retw.n. */
7397 xtensa_insnbuf_from_chars
7398 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7399 fmt
= xtensa_format_decode (isa
, insnbuf
);
7401 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
7402 have no problems. */
7403 if (fmt
== XTENSA_UNDEFINED
7404 || xtensa_format_num_slots (isa
, fmt
) != 1)
7407 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
7408 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
7410 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
7417 /* Re-process all of the fragments looking to convert all of the
7418 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
7419 loop end label, convert this frag to one that will generate a NOP.
7420 In any case close it off with a .fill 0. */
7422 static bfd_boolean
next_instr_is_loop_end (fragS
*);
7425 xtensa_fix_b_j_loop_end_frags (void)
7430 /* When this routine is called, all of the subsections are still intact
7431 so we walk over subsections instead of sections. */
7432 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7433 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7437 /* Walk over all of the fragments in a subsection. */
7438 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7440 if (fragP
->fr_type
== rs_machine_dependent
7441 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
7443 if (next_instr_is_loop_end (fragP
))
7445 if (fragP
->tc_frag_data
.is_no_transform
)
7446 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
7448 relax_frag_add_nop (fragP
);
7458 next_instr_is_loop_end (fragS
*fragP
)
7460 const fragS
*next_fragP
;
7462 if (next_frag_is_loop_target (fragP
))
7465 next_fragP
= next_non_empty_frag (fragP
);
7466 if (next_fragP
== NULL
)
7469 if (!next_frag_is_loop_target (next_fragP
))
7472 /* If the size is >= 3 then there is more than one instruction here.
7473 The hardware bug will not fire. */
7474 if (next_fragP
->fr_fix
> 3)
7481 /* Re-process all of the fragments looking to convert all of the
7482 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
7483 not MY loop's loop end within 12 bytes, add enough nops here to
7484 make it at least 12 bytes away. In any case close it off with a
7487 static offsetT min_bytes_to_other_loop_end
7488 (fragS
*, fragS
*, offsetT
);
7491 xtensa_fix_close_loop_end_frags (void)
7496 /* When this routine is called, all of the subsections are still intact
7497 so we walk over subsections instead of sections. */
7498 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7499 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7503 fragS
*current_target
= NULL
;
7505 /* Walk over all of the fragments in a subsection. */
7506 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7508 if (fragP
->fr_type
== rs_machine_dependent
7509 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7510 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7511 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7514 && fragP
->fr_type
== rs_machine_dependent
7515 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
7518 int bytes_added
= 0;
7520 #define REQUIRED_LOOP_DIVIDING_BYTES 12
7521 /* Max out at 12. */
7522 min_bytes
= min_bytes_to_other_loop_end
7523 (fragP
->fr_next
, current_target
, REQUIRED_LOOP_DIVIDING_BYTES
);
7525 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
7527 if (fragP
->tc_frag_data
.is_no_transform
)
7528 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
7531 while (min_bytes
+ bytes_added
7532 < REQUIRED_LOOP_DIVIDING_BYTES
)
7536 if (fragP
->fr_var
< length
)
7537 as_fatal (_("fr_var %lu < length %d"),
7538 (long) fragP
->fr_var
, length
);
7541 assemble_nop (length
,
7542 fragP
->fr_literal
+ fragP
->fr_fix
);
7543 fragP
->fr_fix
+= length
;
7544 fragP
->fr_var
-= length
;
7546 bytes_added
+= length
;
7552 assert (fragP
->fr_type
!= rs_machine_dependent
7553 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
7559 static offsetT
unrelaxed_frag_min_size (fragS
*);
7562 min_bytes_to_other_loop_end (fragS
*fragP
,
7563 fragS
*current_target
,
7567 fragS
*current_fragP
;
7569 for (current_fragP
= fragP
;
7571 current_fragP
= current_fragP
->fr_next
)
7573 if (current_fragP
->tc_frag_data
.is_loop_target
7574 && current_fragP
!= current_target
)
7577 offset
+= unrelaxed_frag_min_size (current_fragP
);
7579 if (offset
>= max_size
)
7587 unrelaxed_frag_min_size (fragS
*fragP
)
7589 offsetT size
= fragP
->fr_fix
;
7591 /* Add fill size. */
7592 if (fragP
->fr_type
== rs_fill
)
7593 size
+= fragP
->fr_offset
;
7600 unrelaxed_frag_max_size (fragS
*fragP
)
7602 offsetT size
= fragP
->fr_fix
;
7603 switch (fragP
->fr_type
)
7606 /* Empty frags created by the obstack allocation scheme
7607 end up with type 0. */
7612 size
+= fragP
->fr_offset
;
7620 /* No further adjustments needed. */
7622 case rs_machine_dependent
:
7623 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
7624 size
+= fragP
->fr_var
;
7627 /* We had darn well better know how big it is. */
7636 /* Re-process all of the fragments looking to convert all
7637 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
7640 1) the instruction size count to the loop end label
7641 is too short (<= 2 instructions),
7642 2) loop has a jump or branch in it
7645 1) workaround_all_short_loops is TRUE
7646 2) The generating loop was a 'loopgtz' or 'loopnez'
7647 3) the instruction size count to the loop end label is too short
7649 then convert this frag (and maybe the next one) to generate a NOP.
7650 In any case close it off with a .fill 0. */
7652 static int count_insns_to_loop_end (fragS
*, bfd_boolean
, int);
7653 static bfd_boolean
branch_before_loop_end (fragS
*);
7656 xtensa_fix_short_loop_frags (void)
7661 /* When this routine is called, all of the subsections are still intact
7662 so we walk over subsections instead of sections. */
7663 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7664 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7667 fragS
*current_target
= NULL
;
7668 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
7670 /* Walk over all of the fragments in a subsection. */
7671 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7673 if (fragP
->fr_type
== rs_machine_dependent
7674 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7675 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7678 fragS
*loop_frag
= next_non_empty_frag (fragP
);
7679 tinsn_from_chars (&t_insn
, loop_frag
->fr_opcode
, 0);
7680 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7681 current_opcode
= t_insn
.opcode
;
7682 assert (xtensa_opcode_is_loop (xtensa_default_isa
,
7683 current_opcode
) == 1);
7686 if (fragP
->fr_type
== rs_machine_dependent
7687 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7689 if (count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3) < 3
7690 && (branch_before_loop_end (fragP
->fr_next
)
7691 || (workaround_all_short_loops
7692 && current_opcode
!= XTENSA_UNDEFINED
7693 && current_opcode
!= xtensa_loop_opcode
)))
7695 if (fragP
->tc_frag_data
.is_no_transform
)
7696 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
7698 relax_frag_add_nop (fragP
);
7707 static int unrelaxed_frag_min_insn_count (fragS
*);
7710 count_insns_to_loop_end (fragS
*base_fragP
,
7711 bfd_boolean count_relax_add
,
7714 fragS
*fragP
= NULL
;
7719 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
7721 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
7722 if (insn_count
>= max_count
)
7725 if (count_relax_add
)
7727 if (fragP
->fr_type
== rs_machine_dependent
7728 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7730 /* In order to add the appropriate number of
7731 NOPs, we count an instruction for downstream
7734 if (insn_count
>= max_count
)
7744 unrelaxed_frag_min_insn_count (fragS
*fragP
)
7746 xtensa_isa isa
= xtensa_default_isa
;
7747 static xtensa_insnbuf insnbuf
= NULL
;
7751 if (!fragP
->tc_frag_data
.is_insn
)
7755 insnbuf
= xtensa_insnbuf_alloc (isa
);
7757 /* Decode the fixed instructions. */
7758 while (offset
< fragP
->fr_fix
)
7762 xtensa_insnbuf_from_chars
7763 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7764 fmt
= xtensa_format_decode (isa
, insnbuf
);
7766 if (fmt
== XTENSA_UNDEFINED
)
7768 as_fatal (_("undecodable instruction in instruction frag"));
7771 offset
+= xtensa_format_length (isa
, fmt
);
7779 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
7782 branch_before_loop_end (fragS
*base_fragP
)
7786 for (fragP
= base_fragP
;
7787 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
7788 fragP
= fragP
->fr_next
)
7790 if (unrelaxed_frag_has_b_j (fragP
))
7798 unrelaxed_frag_has_b_j (fragS
*fragP
)
7800 static xtensa_insnbuf insnbuf
= NULL
;
7801 xtensa_isa isa
= xtensa_default_isa
;
7804 if (!fragP
->tc_frag_data
.is_insn
)
7808 insnbuf
= xtensa_insnbuf_alloc (isa
);
7810 /* Decode the fixed instructions. */
7811 while (offset
< fragP
->fr_fix
)
7816 xtensa_insnbuf_from_chars
7817 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7818 fmt
= xtensa_format_decode (isa
, insnbuf
);
7819 if (fmt
== XTENSA_UNDEFINED
)
7822 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7824 xtensa_opcode opcode
=
7825 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
7826 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
7827 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
7830 offset
+= xtensa_format_length (isa
, fmt
);
7836 /* Checks to be made after initial assembly but before relaxation. */
7838 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
7839 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
7842 xtensa_sanity_check (void)
7849 as_where (&file_name
, &line
);
7850 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7851 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7855 /* Walk over all of the fragments in a subsection. */
7856 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7858 if (fragP
->fr_type
== rs_machine_dependent
7859 && fragP
->fr_subtype
== RELAX_SLOTS
7860 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7862 static xtensa_insnbuf insnbuf
= NULL
;
7865 if (fragP
->fr_opcode
!= NULL
)
7868 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7869 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7870 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
7872 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7873 t_insn
.opcode
) == 1)
7875 if (is_empty_loop (&t_insn
, fragP
))
7877 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7878 as_bad (_("invalid empty loop"));
7880 if (!is_local_forward_loop (&t_insn
, fragP
))
7882 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7883 as_bad (_("loop target does not follow "
7884 "loop instruction in section"));
7891 new_logical_line (file_name
, line
);
7895 #define LOOP_IMMED_OPN 1
7897 /* Return TRUE if the loop target is the next non-zero fragment. */
7900 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
7902 const expressionS
*expr
;
7906 if (insn
->insn_type
!= ITYPE_INSN
)
7909 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
7912 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7915 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7917 if (expr
->X_op
!= O_symbol
)
7920 symbolP
= expr
->X_add_symbol
;
7924 if (symbol_get_frag (symbolP
) == NULL
)
7927 if (S_GET_VALUE (symbolP
) != 0)
7930 /* Walk through the zero-size fragments from this one. If we find
7931 the target fragment, then this is a zero-size loop. */
7933 for (next_fragP
= fragP
->fr_next
;
7935 next_fragP
= next_fragP
->fr_next
)
7937 if (next_fragP
== symbol_get_frag (symbolP
))
7939 if (next_fragP
->fr_fix
!= 0)
7947 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
7949 const expressionS
*expr
;
7953 if (insn
->insn_type
!= ITYPE_INSN
)
7956 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
7959 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7962 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7964 if (expr
->X_op
!= O_symbol
)
7967 symbolP
= expr
->X_add_symbol
;
7971 if (symbol_get_frag (symbolP
) == NULL
)
7974 /* Walk through fragments until we find the target.
7975 If we do not find the target, then this is an invalid loop. */
7977 for (next_fragP
= fragP
->fr_next
;
7979 next_fragP
= next_fragP
->fr_next
)
7981 if (next_fragP
== symbol_get_frag (symbolP
))
7989 #define XTINFO_NAME "Xtensa_Info"
7990 #define XTINFO_NAMESZ 12
7991 #define XTINFO_TYPE 1
7994 xtensa_add_config_info (void)
8000 info_sec
= subseg_new (".xtensa.info", 0);
8001 bfd_set_section_flags (stdoutput
, info_sec
, SEC_HAS_CONTENTS
| SEC_READONLY
);
8003 data
= xmalloc (100);
8004 sprintf (data
, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n",
8005 XSHAL_USE_ABSOLUTE_LITERALS
, XSHAL_ABI
);
8006 sz
= strlen (data
) + 1;
8008 /* Add enough null terminators to pad to a word boundary. */
8011 while ((sz
& 3) != 0);
8013 /* Follow the standard note section layout:
8014 First write the length of the name string. */
8016 md_number_to_chars (p
, (valueT
) XTINFO_NAMESZ
, 4);
8018 /* Next comes the length of the "descriptor", i.e., the actual data. */
8020 md_number_to_chars (p
, (valueT
) sz
, 4);
8022 /* Write the note type. */
8024 md_number_to_chars (p
, (valueT
) XTINFO_TYPE
, 4);
8026 /* Write the name field. */
8027 p
= frag_more (XTINFO_NAMESZ
);
8028 memcpy (p
, XTINFO_NAME
, XTINFO_NAMESZ
);
8030 /* Finally, write the descriptor. */
8032 memcpy (p
, data
, sz
);
8038 /* Alignment Functions. */
8041 get_text_align_power (unsigned target_size
)
8043 if (target_size
<= 4)
8045 assert (target_size
== 8);
8051 get_text_align_max_fill_size (int align_pow
,
8052 bfd_boolean use_nops
,
8053 bfd_boolean use_no_density
)
8056 return (1 << align_pow
);
8058 return 3 * (1 << align_pow
);
8060 return 1 + (1 << align_pow
);
8064 /* Calculate the minimum bytes of fill needed at "address" to align a
8065 target instruction of size "target_size" so that it does not cross a
8066 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE,
8067 the fill can be an arbitrary number of bytes. Otherwise, the space must
8068 be filled by NOP instructions. */
8071 get_text_align_fill_size (addressT address
,
8074 bfd_boolean use_nops
,
8075 bfd_boolean use_no_density
)
8077 addressT alignment
, fill
, fill_limit
, fill_step
;
8078 bfd_boolean skip_one
= FALSE
;
8080 alignment
= (1 << align_pow
);
8081 assert (target_size
> 0 && alignment
>= (addressT
) target_size
);
8085 fill_limit
= alignment
;
8088 else if (!use_no_density
)
8090 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */
8091 fill_limit
= alignment
* 2;
8097 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */
8098 fill_limit
= alignment
* 3;
8102 /* Try all fill sizes until finding one that works. */
8103 for (fill
= 0; fill
< fill_limit
; fill
+= fill_step
)
8105 if (skip_one
&& fill
== 1)
8107 if ((address
+ fill
) >> align_pow
8108 == (address
+ fill
+ target_size
- 1) >> align_pow
)
8117 branch_align_power (segT sec
)
8119 /* If the Xtensa processor has a fetch width of 8 bytes, and the section
8120 is aligned to at least an 8-byte boundary, then a branch target need
8121 only fit within an 8-byte aligned block of memory to avoid a stall.
8122 Otherwise, try to fit branch targets within 4-byte aligned blocks
8123 (which may be insufficient, e.g., if the section has no alignment, but
8124 it's good enough). */
8125 if (xtensa_fetch_width
== 8)
8127 if (get_recorded_alignment (sec
) >= 3)
8131 assert (xtensa_fetch_width
== 4);
8137 /* This will assert if it is not possible. */
8140 get_text_align_nop_count (offsetT fill_size
, bfd_boolean use_no_density
)
8146 assert (fill_size
% 3 == 0);
8147 return (fill_size
/ 3);
8150 assert (fill_size
!= 1); /* Bad argument. */
8152 while (fill_size
> 1)
8155 if (fill_size
== 2 || fill_size
== 4)
8157 fill_size
-= insn_size
;
8160 assert (fill_size
!= 1); /* Bad algorithm. */
8166 get_text_align_nth_nop_size (offsetT fill_size
,
8168 bfd_boolean use_no_density
)
8175 assert (fill_size
!= 1); /* Bad argument. */
8177 while (fill_size
> 1)
8180 if (fill_size
== 2 || fill_size
== 4)
8182 fill_size
-= insn_size
;
8192 /* For the given fragment, find the appropriate address
8193 for it to begin at if we are using NOPs to align it. */
8196 get_noop_aligned_address (fragS
*fragP
, addressT address
)
8198 /* The rule is: get next fragment's FIRST instruction. Find
8199 the smallest number of bytes that need to be added to
8200 ensure that the next fragment's FIRST instruction will fit
8203 E.G., 2 bytes : 0, 1, 2 mod 4
8206 If the FIRST instruction MIGHT be relaxed,
8207 assume that it will become a 3-byte instruction.
8209 Note again here that LOOP instructions are not bundleable,
8210 and this relaxation only applies to LOOP opcodes. */
8213 int first_insn_size
;
8215 addressT pre_opcode_bytes
;
8218 xtensa_opcode opcode
;
8219 bfd_boolean is_loop
;
8221 assert (fragP
->fr_type
== rs_machine_dependent
);
8222 assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
8224 /* Find the loop frag. */
8225 first_insn
= next_non_empty_frag (fragP
);
8226 /* Now find the first insn frag. */
8227 first_insn
= next_non_empty_frag (first_insn
);
8229 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
8231 loop_insn_size
= xg_get_single_size (opcode
);
8233 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
8234 pre_opcode_bytes
+= loop_insn_size
;
8236 /* For loops, the alignment depends on the size of the
8237 instruction following the loop, not the LOOP instruction. */
8239 if (first_insn
== NULL
)
8240 first_insn_size
= xtensa_fetch_width
;
8242 first_insn_size
= get_loop_align_size (frag_format_size (first_insn
));
8244 /* If it was 8, then we'll need a larger alignment for the section. */
8245 align_power
= get_text_align_power (first_insn_size
);
8246 record_alignment (now_seg
, align_power
);
8248 fill_size
= get_text_align_fill_size
8249 (address
+ pre_opcode_bytes
, align_power
, first_insn_size
, TRUE
,
8250 fragP
->tc_frag_data
.is_no_density
);
8252 return address
+ fill_size
;
8256 /* 3 mechanisms for relaxing an alignment:
8258 Align to a power of 2.
8259 Align so the next fragment's instruction does not cross a word boundary.
8260 Align the current instruction so that if the next instruction
8261 were 3 bytes, it would not cross a word boundary.
8265 zeros - This is easy; always insert zeros.
8266 nops - 3-byte and 2-byte instructions
8270 >=5 : 3-byte instruction + fn (n-3)
8271 widening - widen previous instructions. */
8274 get_aligned_diff (fragS
*fragP
, addressT address
, offsetT
*max_diff
)
8276 addressT target_address
, loop_insn_offset
;
8278 xtensa_opcode loop_opcode
;
8279 bfd_boolean is_loop
;
8282 offsetT branch_align
;
8285 assert (fragP
->fr_type
== rs_machine_dependent
);
8286 switch (fragP
->fr_subtype
)
8288 case RELAX_DESIRE_ALIGN
:
8289 target_size
= next_frag_format_size (fragP
);
8290 if (target_size
== XTENSA_UNDEFINED
)
8292 align_power
= branch_align_power (now_seg
);
8293 branch_align
= 1 << align_power
;
8294 /* Don't count on the section alignment being as large as the target. */
8295 if (target_size
> branch_align
)
8296 target_size
= branch_align
;
8297 opt_diff
= get_text_align_fill_size (address
, align_power
,
8298 target_size
, FALSE
, FALSE
);
8300 *max_diff
= (opt_diff
+ branch_align
8301 - (target_size
+ ((address
+ opt_diff
) % branch_align
)));
8302 assert (*max_diff
>= opt_diff
);
8305 case RELAX_ALIGN_NEXT_OPCODE
:
8306 /* The next non-empty frag after this one holds the LOOP instruction
8307 that needs to be aligned. The required alignment depends on the
8308 size of the next non-empty frag after the loop frag, i.e., the
8309 first instruction in the loop. */
8310 loop_frag
= next_non_empty_frag (fragP
);
8311 target_size
= get_loop_align_size (next_frag_format_size (loop_frag
));
8312 loop_insn_offset
= 0;
8313 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
8316 /* If the loop has been expanded then the LOOP instruction
8317 could be at an offset from this fragment. */
8318 if (loop_frag
->tc_frag_data
.slot_subtypes
[0] != RELAX_IMMED
)
8319 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
8321 /* In an ideal world, which is what we are shooting for here,
8322 we wouldn't need to use any NOPs immediately prior to the
8323 LOOP instruction. If this approach fails, relax_frag_loop_align
8324 will call get_noop_aligned_address. */
8326 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
8327 align_power
= get_text_align_power (target_size
);
8328 opt_diff
= get_text_align_fill_size (target_address
, align_power
,
8329 target_size
, FALSE
, FALSE
);
8331 *max_diff
= xtensa_fetch_width
8332 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
8333 - target_size
+ opt_diff
;
8334 assert (*max_diff
>= opt_diff
);
8345 /* md_relax_frag Hook and Helper Functions. */
8347 static long relax_frag_loop_align (fragS
*, long);
8348 static long relax_frag_for_align (fragS
*, long);
8349 static long relax_frag_immed
8350 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
8353 /* Return the number of bytes added to this fragment, given that the
8354 input has been stretched already by "stretch". */
8357 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
8359 xtensa_isa isa
= xtensa_default_isa
;
8360 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
8361 long new_stretch
= 0;
8365 static xtensa_insnbuf vbuf
= NULL
;
8366 int slot
, num_slots
;
8369 as_where (&file_name
, &line
);
8370 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8372 fragP
->tc_frag_data
.unreported_expansion
= 0;
8374 switch (fragP
->fr_subtype
)
8376 case RELAX_ALIGN_NEXT_OPCODE
:
8377 /* Always convert. */
8378 if (fragP
->tc_frag_data
.relax_seen
)
8379 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
8382 case RELAX_LOOP_END
:
8386 case RELAX_LOOP_END_ADD_NOP
:
8387 /* Add a NOP and switch to .fill 0. */
8388 new_stretch
= relax_frag_add_nop (fragP
);
8392 case RELAX_DESIRE_ALIGN
:
8393 /* Do nothing. The narrowing before this frag will either align
8398 case RELAX_LITERAL_FINAL
:
8401 case RELAX_LITERAL_NR
:
8403 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
8404 assert (unreported
== lit_size
);
8405 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
8406 fragP
->fr_var
-= lit_size
;
8407 fragP
->fr_fix
+= lit_size
;
8413 vbuf
= xtensa_insnbuf_alloc (isa
);
8415 xtensa_insnbuf_from_chars
8416 (isa
, vbuf
, (unsigned char *) fragP
->fr_opcode
, 0);
8417 fmt
= xtensa_format_decode (isa
, vbuf
);
8418 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8420 for (slot
= 0; slot
< num_slots
; slot
++)
8422 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
8425 if (fragP
->tc_frag_data
.relax_seen
)
8426 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8430 case RELAX_IMMED_STEP1
:
8431 case RELAX_IMMED_STEP2
:
8432 case RELAX_IMMED_STEP3
:
8433 /* Place the immediate. */
8434 new_stretch
+= relax_frag_immed
8435 (now_seg
, fragP
, stretch
,
8436 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8437 fmt
, slot
, stretched_p
, FALSE
);
8441 /* This is OK; see the note in xg_assemble_vliw_tokens. */
8447 case RELAX_LITERAL_POOL_BEGIN
:
8448 case RELAX_LITERAL_POOL_END
:
8449 case RELAX_MAYBE_UNREACHABLE
:
8450 case RELAX_MAYBE_DESIRE_ALIGN
:
8451 /* No relaxation required. */
8454 case RELAX_FILL_NOP
:
8455 case RELAX_UNREACHABLE
:
8456 if (fragP
->tc_frag_data
.relax_seen
)
8457 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8461 as_bad (_("bad relaxation state"));
8464 /* Tell gas we need another relaxation pass. */
8465 if (! fragP
->tc_frag_data
.relax_seen
)
8467 fragP
->tc_frag_data
.relax_seen
= TRUE
;
8471 new_logical_line (file_name
, line
);
8477 relax_frag_loop_align (fragS
*fragP
, long stretch
)
8479 addressT old_address
, old_next_address
, old_size
;
8480 addressT new_address
, new_next_address
, new_size
;
8483 /* All the frags with relax_frag_for_alignment prior to this one in the
8484 section have been done, hopefully eliminating the need for a NOP here.
8485 But, this will put it in if necessary. */
8487 /* Calculate the old address of this fragment and the next fragment. */
8488 old_address
= fragP
->fr_address
- stretch
;
8489 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
8490 fragP
->tc_frag_data
.text_expansion
[0]);
8491 old_size
= old_next_address
- old_address
;
8493 /* Calculate the new address of this fragment and the next fragment. */
8494 new_address
= fragP
->fr_address
;
8496 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
8497 new_size
= new_next_address
- new_address
;
8499 growth
= new_size
- old_size
;
8501 /* Fix up the text_expansion field and return the new growth. */
8502 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
8507 /* Add a NOP instruction. */
8510 relax_frag_add_nop (fragS
*fragP
)
8512 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
8513 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
8514 assemble_nop (length
, nop_buf
);
8515 fragP
->tc_frag_data
.is_insn
= TRUE
;
8517 if (fragP
->fr_var
< length
)
8519 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP
->fr_var
, length
);
8523 fragP
->fr_fix
+= length
;
8524 fragP
->fr_var
-= length
;
8529 static long future_alignment_required (fragS
*, long);
8532 relax_frag_for_align (fragS
*fragP
, long stretch
)
8534 /* Overview of the relaxation procedure for alignment:
8535 We can widen with NOPs or by widening instructions or by filling
8536 bytes after jump instructions. Find the opportune places and widen
8537 them if necessary. */
8542 assert (fragP
->fr_subtype
== RELAX_FILL_NOP
8543 || fragP
->fr_subtype
== RELAX_UNREACHABLE
8544 || (fragP
->fr_subtype
== RELAX_SLOTS
8545 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
8547 stretch_me
= future_alignment_required (fragP
, stretch
);
8548 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
8554 /* We expanded on a previous pass. Can we shrink now? */
8555 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
8556 if (shrink
<= stretch
&& stretch
> 0)
8558 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8564 /* Below here, diff > 0. */
8565 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8571 /* Return the address of the next frag that should be aligned.
8573 By "address" we mean the address it _would_ be at if there
8574 is no action taken to align it between here and the target frag.
8575 In other words, if no narrows and no fill nops are used between
8576 here and the frag to align, _even_if_ some of the frags we use
8577 to align targets have already expanded on a previous relaxation
8580 Also, count each frag that may be used to help align the target.
8582 Return 0 if there are no frags left in the chain that need to be
8586 find_address_of_next_align_frag (fragS
**fragPP
,
8590 bfd_boolean
*paddable
)
8592 fragS
*fragP
= *fragPP
;
8593 addressT address
= fragP
->fr_address
;
8595 /* Do not reset the counts to 0. */
8599 /* Limit this to a small search. */
8600 if (*widens
>= (int) xtensa_fetch_width
)
8605 address
+= fragP
->fr_fix
;
8607 if (fragP
->fr_type
== rs_fill
)
8608 address
+= fragP
->fr_offset
* fragP
->fr_var
;
8609 else if (fragP
->fr_type
== rs_machine_dependent
)
8611 switch (fragP
->fr_subtype
)
8613 case RELAX_UNREACHABLE
:
8617 case RELAX_FILL_NOP
:
8619 if (!fragP
->tc_frag_data
.is_no_density
)
8624 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8629 address
+= total_frag_text_expansion (fragP
);;
8633 address
+= fragP
->tc_frag_data
.text_expansion
[0];
8636 case RELAX_ALIGN_NEXT_OPCODE
:
8637 case RELAX_DESIRE_ALIGN
:
8641 case RELAX_MAYBE_UNREACHABLE
:
8642 case RELAX_MAYBE_DESIRE_ALIGN
:
8647 /* Just punt if we don't know the type. */
8654 /* Just punt if we don't know the type. */
8658 fragP
= fragP
->fr_next
;
8666 static long bytes_to_stretch (fragS
*, int, int, int, int);
8669 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
8671 fragS
*this_frag
= fragP
;
8675 int narrow_nops
= 0;
8676 bfd_boolean paddable
= FALSE
;
8677 offsetT local_opt_diff
;
8680 int stretch_amount
= 0;
8681 int local_stretch_amount
;
8682 int global_stretch_amount
;
8684 address
= find_address_of_next_align_frag
8685 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
8689 if (this_frag
->tc_frag_data
.is_aligning_branch
)
8690 this_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
8692 frag_wane (this_frag
);
8696 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
8697 opt_diff
= local_opt_diff
;
8698 assert (opt_diff
>= 0);
8699 assert (max_diff
>= opt_diff
);
8704 fragP
= fragP
->fr_next
;
8706 while (fragP
&& opt_diff
< max_diff
&& address
)
8708 /* We only use these to determine if we can exit early
8709 because there will be plenty of ways to align future
8711 int glob_widens
= 0;
8714 bfd_boolean glob_pad
= 0;
8715 address
= find_address_of_next_align_frag
8716 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
8717 /* If there is a padable portion, then skip. */
8718 if (glob_pad
|| glob_widens
>= (1 << branch_align_power (now_seg
)))
8723 offsetT next_m_diff
;
8724 offsetT next_o_diff
;
8726 /* Downrange frags haven't had stretch added to them yet. */
8729 /* The address also includes any text expansion from this
8730 frag in a previous pass, but we don't want that. */
8731 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
8733 /* Assume we are going to move at least opt_diff. In
8734 reality, we might not be able to, but assuming that
8735 we will helps catch cases where moving opt_diff pushes
8736 the next target from aligned to unaligned. */
8737 address
+= opt_diff
;
8739 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
8741 /* Now cleanup for the adjustments to address. */
8742 next_o_diff
+= opt_diff
;
8743 next_m_diff
+= opt_diff
;
8744 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
8745 opt_diff
= next_o_diff
;
8746 if (next_m_diff
< max_diff
)
8747 max_diff
= next_m_diff
;
8748 fragP
= fragP
->fr_next
;
8752 /* If there are enough wideners in between, do it. */
8755 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
8757 assert (opt_diff
<= UNREACHABLE_MAX_WIDTH
);
8762 local_stretch_amount
8763 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8764 num_widens
, local_opt_diff
);
8765 global_stretch_amount
8766 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8767 num_widens
, opt_diff
);
8768 /* If the condition below is true, then the frag couldn't
8769 stretch the correct amount for the global case, so we just
8770 optimize locally. We'll rely on the subsequent frags to get
8771 the correct alignment in the global case. */
8772 if (global_stretch_amount
< local_stretch_amount
)
8773 stretch_amount
= local_stretch_amount
;
8775 stretch_amount
= global_stretch_amount
;
8777 if (this_frag
->fr_subtype
== RELAX_SLOTS
8778 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8779 assert (stretch_amount
<= 1);
8780 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8782 if (this_frag
->tc_frag_data
.is_no_density
)
8783 assert (stretch_amount
== 3 || stretch_amount
== 0);
8785 assert (stretch_amount
<= 3);
8788 return stretch_amount
;
8792 /* The idea: widen everything you can to get a target or loop aligned,
8793 then start using NOPs.
8795 When we must have a NOP, here is a table of how we decide
8796 (so you don't have to fight through the control flow below):
8798 wide_nops = the number of wide NOPs available for aligning
8799 narrow_nops = the number of narrow NOPs available for aligning
8800 (a subset of wide_nops)
8801 widens = the number of narrow instructions that should be widened
8808 b 0 1 1 (case 3a makes this case unnecessary)
8811 c 0 1 2 (case 4a makes this case unnecessary)
8814 c 0 2 1 (case 5b makes this case unnecessary)
8817 c 0 1 4 (case 6b makes this case unnecessary)
8818 d 1 1 1 (case 6a makes this case unnecessary)
8819 e 0 2 2 (case 6a makes this case unnecessary)
8820 f 0 3 0 (case 6a makes this case unnecessary)
8823 c 1 1 2 (case 7b makes this case unnecessary)
8824 d 0 1 5 (case 7a makes this case unnecessary)
8825 e 0 2 3 (case 7b makes this case unnecessary)
8826 f 0 3 1 (case 7b makes this case unnecessary)
8827 g 1 2 1 (case 7b makes this case unnecessary)
8831 bytes_to_stretch (fragS
*this_frag
,
8837 int bytes_short
= desired_diff
- num_widens
;
8839 assert (desired_diff
>= 0 && desired_diff
< 8);
8840 if (desired_diff
== 0)
8843 assert (wide_nops
> 0 || num_widens
> 0);
8845 /* Always prefer widening to NOP-filling. */
8846 if (bytes_short
< 0)
8848 /* There are enough RELAX_NARROW frags after this one
8849 to align the target without widening this frag in any way. */
8853 if (bytes_short
== 0)
8855 /* Widen every narrow between here and the align target
8856 and the align target will be properly aligned. */
8857 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8863 /* From here we will need at least one NOP to get an alignment.
8864 However, we may not be able to align at all, in which case,
8866 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8868 switch (desired_diff
)
8873 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 1)
8874 return 2; /* case 2 */
8880 return 3; /* case 3a */
8882 if (num_widens
>= 1 && wide_nops
== 1)
8883 return 3; /* case 4a */
8884 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 2)
8885 return 2; /* case 4b */
8888 if (num_widens
>= 2 && wide_nops
== 1)
8889 return 3; /* case 5a */
8890 /* We will need two nops. Are there enough nops
8891 between here and the align target? */
8892 if (wide_nops
< 2 || narrow_nops
== 0)
8894 /* Are there other nops closer that can serve instead? */
8895 if (wide_nops
> 2 && narrow_nops
> 1)
8897 /* Take the density one first, because there might not be
8898 another density one available. */
8899 if (!this_frag
->tc_frag_data
.is_no_density
)
8900 return 2; /* case 5b narrow */
8902 return 3; /* case 5b wide */
8906 return 3; /* case 6a */
8907 else if (num_widens
>= 3 && wide_nops
== 1)
8908 return 3; /* case 6b */
8911 if (wide_nops
== 1 && num_widens
>= 4)
8912 return 3; /* case 7a */
8913 else if (wide_nops
== 2 && num_widens
>= 1)
8914 return 3; /* case 7b */
8922 /* We will need a NOP no matter what, but should we widen
8923 this instruction to help?
8925 This is a RELAX_NARROW frag. */
8926 switch (desired_diff
)
8935 if (wide_nops
>= 1 && num_widens
== 1)
8936 return 1; /* case 4a */
8939 if (wide_nops
>= 1 && num_widens
== 2)
8940 return 1; /* case 5a */
8944 return 0; /* case 6a */
8945 else if (wide_nops
>= 1 && num_widens
== 3)
8946 return 1; /* case 6b */
8949 if (wide_nops
>= 1 && num_widens
== 4)
8950 return 1; /* case 7a */
8951 else if (wide_nops
>= 2 && num_widens
== 1)
8952 return 1; /* case 7b */
8965 relax_frag_immed (segT segP
,
8972 bfd_boolean estimate_only
)
8976 bfd_boolean negatable_branch
= FALSE
;
8977 bfd_boolean branch_jmp_to_next
= FALSE
;
8978 bfd_boolean from_wide_insn
= FALSE
;
8979 xtensa_isa isa
= xtensa_default_isa
;
8981 offsetT frag_offset
;
8984 int num_text_bytes
, num_literal_bytes
;
8985 int literal_diff
, total_text_diff
, this_text_diff
, first
;
8987 assert (fragP
->fr_opcode
!= NULL
);
8989 xg_clear_vinsn (&cur_vinsn
);
8990 vinsn_from_chars (&cur_vinsn
, fragP
->fr_opcode
);
8991 if (cur_vinsn
.num_slots
> 1)
8992 from_wide_insn
= TRUE
;
8994 tinsn
= cur_vinsn
.slots
[slot
];
8995 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
8997 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
) == 1)
9000 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9001 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
9003 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
9005 old_size
= xtensa_format_length (isa
, fmt
);
9007 /* Special case: replace a branch to the next instruction with a NOP.
9008 This is required to work around a hardware bug in T1040.0 and also
9009 serves as an optimization. */
9011 if (branch_jmp_to_next
9012 && ((old_size
== 2) || (old_size
== 3))
9013 && !next_frag_is_loop_target (fragP
))
9016 /* Here is the fun stuff: Get the immediate field from this
9017 instruction. If it fits, we are done. If not, find the next
9018 instruction sequence that fits. */
9020 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9021 istack_init (&istack
);
9022 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
9023 min_steps
, stretch
);
9024 if (num_steps
< min_steps
)
9026 as_fatal (_("internal error: relaxation failed"));
9030 if (num_steps
> RELAX_IMMED_MAXSTEPS
)
9032 as_fatal (_("internal error: relaxation requires too many steps"));
9036 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
9038 /* Figure out the number of bytes needed. */
9040 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
9042 num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
9044 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
9047 num_text_bytes
= get_num_stack_text_bytes (&istack
);
9051 num_text_bytes
+= old_size
;
9052 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
9053 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
9056 total_text_diff
= num_text_bytes
- old_size
;
9057 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
9059 /* It MUST get larger. If not, we could get an infinite loop. */
9060 assert (num_text_bytes
>= 0);
9061 assert (literal_diff
>= 0);
9062 assert (total_text_diff
>= 0);
9064 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
9065 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
9066 assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
9067 assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
9069 /* Find the associated expandable literal for this. */
9070 if (literal_diff
!= 0)
9072 lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
9075 assert (literal_diff
== 4);
9076 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
9078 /* We expect that the literal section state has NOT been
9080 assert (lit_fragP
->fr_type
== rs_machine_dependent
9081 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
9082 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
9084 /* We need to mark this section for another iteration
9090 if (negatable_branch
&& istack
.ninsn
> 1)
9091 update_next_frag_state (fragP
);
9093 return this_text_diff
;
9097 /* md_convert_frag Hook and Helper Functions. */
9099 static void convert_frag_align_next_opcode (fragS
*);
9100 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
9101 static void convert_frag_fill_nop (fragS
*);
9102 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
9105 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
9107 static xtensa_insnbuf vbuf
= NULL
;
9108 xtensa_isa isa
= xtensa_default_isa
;
9115 as_where (&file_name
, &line
);
9116 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
9118 switch (fragp
->fr_subtype
)
9120 case RELAX_ALIGN_NEXT_OPCODE
:
9121 /* Always convert. */
9122 convert_frag_align_next_opcode (fragp
);
9125 case RELAX_DESIRE_ALIGN
:
9126 /* Do nothing. If not aligned already, too bad. */
9130 case RELAX_LITERAL_FINAL
:
9135 vbuf
= xtensa_insnbuf_alloc (isa
);
9137 xtensa_insnbuf_from_chars
9138 (isa
, vbuf
, (unsigned char *) fragp
->fr_opcode
, 0);
9139 fmt
= xtensa_format_decode (isa
, vbuf
);
9140 num_slots
= xtensa_format_num_slots (isa
, fmt
);
9142 for (slot
= 0; slot
< num_slots
; slot
++)
9144 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
9147 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
9151 case RELAX_IMMED_STEP1
:
9152 case RELAX_IMMED_STEP2
:
9153 case RELAX_IMMED_STEP3
:
9154 /* Place the immediate. */
9157 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
9162 /* This is OK because some slots could have
9163 relaxations and others have none. */
9169 case RELAX_UNREACHABLE
:
9170 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
9171 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
9172 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
9176 case RELAX_MAYBE_UNREACHABLE
:
9177 case RELAX_MAYBE_DESIRE_ALIGN
:
9181 case RELAX_FILL_NOP
:
9182 convert_frag_fill_nop (fragp
);
9185 case RELAX_LITERAL_NR
:
9186 if (use_literal_section
)
9188 /* This should have been handled during relaxation. When
9189 relaxing a code segment, literals sometimes need to be
9190 added to the corresponding literal segment. If that
9191 literal segment has already been relaxed, then we end up
9192 in this situation. Marking the literal segments as data
9193 would make this happen less often (since GAS always relaxes
9194 code before data), but we could still get into trouble if
9195 there are instructions in a segment that is not marked as
9196 containing code. Until we can implement a better solution,
9197 cheat and adjust the addresses of all the following frags.
9198 This could break subsequent alignments, but the linker's
9199 literal coalescing will do that anyway. */
9202 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
9203 assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
9204 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
9207 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
9211 as_bad (_("invalid relaxation fragment result"));
9216 new_logical_line (file_name
, line
);
9221 convert_frag_align_next_opcode (fragS
*fragp
)
9223 char *nop_buf
; /* Location for Writing. */
9224 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
9225 addressT aligned_address
;
9229 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
9231 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
9232 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
9233 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
9235 for (nop
= 0; nop
< nop_count
; nop
++)
9238 nop_size
= get_text_align_nth_nop_size (fill_size
, nop
, use_no_density
);
9240 assemble_nop (nop_size
, nop_buf
);
9241 nop_buf
+= nop_size
;
9244 fragp
->fr_fix
+= fill_size
;
9245 fragp
->fr_var
-= fill_size
;
9250 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
9252 TInsn tinsn
, single_target
;
9253 int size
, old_size
, diff
;
9254 offsetT frag_offset
;
9257 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
9259 if (fragP
->tc_frag_data
.is_aligning_branch
== 1)
9261 assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
9262 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
9263 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
9268 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
9270 /* No conversion. */
9275 assert (fragP
->fr_opcode
!= NULL
);
9277 /* Frags in this relaxation state should only contain
9278 single instruction bundles. */
9279 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
9281 /* Just convert it to a wide form.... */
9283 old_size
= xg_get_single_size (tinsn
.opcode
);
9285 tinsn_init (&single_target
);
9286 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9288 if (! xg_is_single_relaxable_insn (&tinsn
, &single_target
, FALSE
))
9290 as_bad (_("unable to widen instruction"));
9294 size
= xg_get_single_size (single_target
.opcode
);
9295 xg_emit_insn_to_buf (&single_target
, fragP
->fr_opcode
, fragP
,
9298 diff
= size
- old_size
;
9300 assert (diff
<= fragP
->fr_var
);
9301 fragP
->fr_var
-= diff
;
9302 fragP
->fr_fix
+= diff
;
9310 convert_frag_fill_nop (fragS
*fragP
)
9312 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
9313 int size
= fragP
->tc_frag_data
.text_expansion
[0];
9314 assert ((unsigned) size
== (fragP
->fr_next
->fr_address
9315 - fragP
->fr_address
- fragP
->fr_fix
));
9318 /* No conversion. */
9322 assemble_nop (size
, loc
);
9323 fragP
->tc_frag_data
.is_insn
= TRUE
;
9324 fragP
->fr_var
-= size
;
9325 fragP
->fr_fix
+= size
;
9330 static fixS
*fix_new_exp_in_seg
9331 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
9332 bfd_reloc_code_real_type
);
9333 static void convert_frag_immed_finish_loop (segT
, fragS
*, TInsn
*);
9336 convert_frag_immed (segT segP
,
9342 char *immed_instr
= fragP
->fr_opcode
;
9344 bfd_boolean expanded
= FALSE
;
9345 bfd_boolean branch_jmp_to_next
= FALSE
;
9346 char *fr_opcode
= fragP
->fr_opcode
;
9347 xtensa_isa isa
= xtensa_default_isa
;
9348 bfd_boolean from_wide_insn
= FALSE
;
9350 bfd_boolean is_loop
;
9352 assert (fr_opcode
!= NULL
);
9354 xg_clear_vinsn (&cur_vinsn
);
9356 vinsn_from_chars (&cur_vinsn
, fr_opcode
);
9357 if (cur_vinsn
.num_slots
> 1)
9358 from_wide_insn
= TRUE
;
9360 orig_tinsn
= cur_vinsn
.slots
[slot
];
9361 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
9363 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
9365 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9366 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
9368 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
9370 /* Conversion just inserts a NOP and marks the fix as completed. */
9371 bytes
= xtensa_format_length (isa
, fmt
);
9374 cur_vinsn
.slots
[slot
].opcode
=
9375 xtensa_format_slot_nop_opcode (isa
, cur_vinsn
.format
, slot
);
9376 cur_vinsn
.slots
[slot
].ntok
= 0;
9380 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
9381 assert (bytes
== 2 || bytes
== 3);
9382 build_nop (&cur_vinsn
.slots
[0], bytes
);
9383 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
9385 vinsn_to_insnbuf (&cur_vinsn
, fr_opcode
, frag_now
, TRUE
);
9386 xtensa_insnbuf_to_chars
9387 (isa
, cur_vinsn
.insnbuf
, (unsigned char *) fr_opcode
, 0);
9392 /* Here is the fun stuff: Get the immediate field from this
9393 instruction. If it fits, we're done. If not, find the next
9394 instruction sequence that fits. */
9398 symbolS
*lit_sym
= NULL
;
9400 int target_offset
= 0;
9403 symbolS
*gen_label
= NULL
;
9404 offsetT frag_offset
;
9405 bfd_boolean first
= TRUE
;
9406 bfd_boolean last_is_jump
;
9408 /* It does not fit. Find something that does and
9409 convert immediately. */
9410 frag_offset
= fr_opcode
- fragP
->fr_literal
;
9411 istack_init (&istack
);
9412 xg_assembly_relax (&istack
, &orig_tinsn
,
9413 segP
, fragP
, frag_offset
, min_steps
, 0);
9415 old_size
= xtensa_format_length (isa
, fmt
);
9417 /* Assemble this right inline. */
9419 /* First, create the mapping from a label name to the REAL label. */
9421 for (i
= 0; i
< istack
.ninsn
; i
++)
9423 TInsn
*tinsn
= &istack
.insn
[i
];
9426 switch (tinsn
->insn_type
)
9429 if (lit_sym
!= NULL
)
9430 as_bad (_("multiple literals in expansion"));
9431 /* First find the appropriate space in the literal pool. */
9432 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9433 if (lit_frag
== NULL
)
9434 as_bad (_("no registered fragment for literal"));
9435 if (tinsn
->ntok
!= 1)
9436 as_bad (_("number of literal tokens != 1"));
9438 /* Set the literal symbol and add a fixup. */
9439 lit_sym
= lit_frag
->fr_symbol
;
9443 if (align_targets
&& !is_loop
)
9445 fragS
*unreach
= fragP
->fr_next
;
9446 while (!(unreach
->fr_type
== rs_machine_dependent
9447 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9448 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
9450 unreach
= unreach
->fr_next
;
9453 assert (unreach
->fr_type
== rs_machine_dependent
9454 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9455 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
9457 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
9459 assert (gen_label
== NULL
);
9460 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
9461 fr_opcode
- fragP
->fr_literal
9462 + target_offset
, fragP
);
9466 if (first
&& from_wide_insn
)
9468 target_offset
+= xtensa_format_length (isa
, fmt
);
9470 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9471 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9474 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9481 last_is_jump
= FALSE
;
9482 for (i
= 0; i
< istack
.ninsn
; i
++)
9484 TInsn
*tinsn
= &istack
.insn
[i
];
9488 bfd_reloc_code_real_type reloc_type
;
9490 switch (tinsn
->insn_type
)
9493 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9494 /* Already checked. */
9495 assert (lit_frag
!= NULL
);
9496 assert (lit_sym
!= NULL
);
9497 assert (tinsn
->ntok
== 1);
9499 target_seg
= S_GET_SEGMENT (lit_sym
);
9500 assert (target_seg
);
9501 reloc_type
= map_operator_to_reloc (tinsn
->tok
[0].X_op
);
9502 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
9503 &tinsn
->tok
[0], FALSE
, reloc_type
);
9510 xg_resolve_labels (tinsn
, gen_label
);
9511 xg_resolve_literals (tinsn
, lit_sym
);
9512 if (from_wide_insn
&& first
)
9515 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9517 cur_vinsn
.slots
[slot
] = *tinsn
;
9521 cur_vinsn
.slots
[slot
].opcode
=
9522 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
9523 cur_vinsn
.slots
[slot
].ntok
= 0;
9525 vinsn_to_insnbuf (&cur_vinsn
, immed_instr
, fragP
, TRUE
);
9526 xtensa_insnbuf_to_chars (isa
, cur_vinsn
.insnbuf
,
9527 (unsigned char *) immed_instr
, 0);
9528 fragP
->tc_frag_data
.is_insn
= TRUE
;
9529 size
= xtensa_format_length (isa
, fmt
);
9530 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9533 (tinsn
, immed_instr
+ size
, fragP
,
9534 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
9535 size
+= xg_get_single_size (tinsn
->opcode
);
9540 size
= xg_get_single_size (tinsn
->opcode
);
9541 xg_emit_insn_to_buf (tinsn
, immed_instr
, fragP
,
9542 immed_instr
- fragP
->fr_literal
, TRUE
);
9544 immed_instr
+= size
;
9550 diff
= total_size
- old_size
;
9554 assert (diff
<= fragP
->fr_var
);
9555 fragP
->fr_var
-= diff
;
9556 fragP
->fr_fix
+= diff
;
9559 /* Check for undefined immediates in LOOP instructions. */
9563 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
9564 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9566 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9569 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
9570 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9572 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9577 if (expanded
&& xtensa_opcode_is_loop (isa
, orig_tinsn
.opcode
) == 1)
9578 convert_frag_immed_finish_loop (segP
, fragP
, &orig_tinsn
);
9580 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
9582 /* Add an expansion note on the expanded instruction. */
9583 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
9584 &orig_tinsn
.tok
[0], TRUE
,
9585 BFD_RELOC_XTENSA_ASM_EXPAND
);
9590 /* Add a new fix expression into the desired segment. We have to
9591 switch to that segment to do this. */
9594 fix_new_exp_in_seg (segT new_seg
,
9601 bfd_reloc_code_real_type r_type
)
9605 subsegT subseg
= now_subseg
;
9607 assert (new_seg
!= 0);
9608 subseg_set (new_seg
, new_subseg
);
9610 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
9611 subseg_set (seg
, subseg
);
9616 /* Relax a loop instruction so that it can span loop >256 bytes.
9622 addi as, as, lo8 (label-.L1)
9623 addmi as, as, mid8 (label-.L1)
9634 convert_frag_immed_finish_loop (segT segP
, fragS
*fragP
, TInsn
*tinsn
)
9639 unsigned long target
;
9640 static xtensa_insnbuf insnbuf
= NULL
;
9641 unsigned int loop_length
, loop_length_hi
, loop_length_lo
;
9642 xtensa_isa isa
= xtensa_default_isa
;
9643 addressT loop_offset
;
9644 addressT addi_offset
= 9;
9645 addressT addmi_offset
= 12;
9650 insnbuf
= xtensa_insnbuf_alloc (isa
);
9652 /* Get the loop offset. */
9653 loop_offset
= get_expanded_loop_offset (tinsn
->opcode
);
9655 /* Validate that there really is a LOOP at the loop_offset. Because
9656 loops are not bundleable, we can assume that the instruction will be
9658 tinsn_from_chars (&loop_insn
, fragP
->fr_opcode
+ loop_offset
, 0);
9659 tinsn_immed_from_frag (&loop_insn
, fragP
, 0);
9661 assert (xtensa_opcode_is_loop (isa
, loop_insn
.opcode
) == 1);
9662 addi_offset
+= loop_offset
;
9663 addmi_offset
+= loop_offset
;
9665 assert (tinsn
->ntok
== 2);
9666 if (tinsn
->tok
[1].X_op
== O_constant
)
9667 target
= tinsn
->tok
[1].X_add_number
;
9668 else if (tinsn
->tok
[1].X_op
== O_symbol
)
9670 /* Find the fragment. */
9671 symbolS
*sym
= tinsn
->tok
[1].X_add_symbol
;
9672 assert (S_GET_SEGMENT (sym
) == segP
9673 || S_GET_SEGMENT (sym
) == absolute_section
);
9674 target
= (S_GET_VALUE (sym
) + tinsn
->tok
[1].X_add_number
);
9678 as_bad (_("invalid expression evaluation type %d"), tinsn
->tok
[1].X_op
);
9682 loop_length
= target
- (fragP
->fr_address
+ fragP
->fr_fix
);
9683 loop_length_hi
= loop_length
& ~0x0ff;
9684 loop_length_lo
= loop_length
& 0x0ff;
9685 if (loop_length_lo
>= 128)
9687 loop_length_lo
-= 256;
9688 loop_length_hi
+= 256;
9691 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
9692 32512. If the loop is larger than that, then we just fail. */
9693 if (loop_length_hi
> 32512)
9694 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9695 _("loop too long for LOOP instruction"));
9697 tinsn_from_chars (&addi_insn
, fragP
->fr_opcode
+ addi_offset
, 0);
9698 assert (addi_insn
.opcode
== xtensa_addi_opcode
);
9700 tinsn_from_chars (&addmi_insn
, fragP
->fr_opcode
+ addmi_offset
, 0);
9701 assert (addmi_insn
.opcode
== xtensa_addmi_opcode
);
9703 set_expr_const (&addi_insn
.tok
[2], loop_length_lo
);
9704 tinsn_to_insnbuf (&addi_insn
, insnbuf
);
9706 fragP
->tc_frag_data
.is_insn
= TRUE
;
9707 xtensa_insnbuf_to_chars
9708 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addi_offset
, 0);
9710 set_expr_const (&addmi_insn
.tok
[2], loop_length_hi
);
9711 tinsn_to_insnbuf (&addmi_insn
, insnbuf
);
9712 xtensa_insnbuf_to_chars
9713 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addmi_offset
, 0);
9715 /* Walk through all of the frags from here to the loop end
9716 and mark them as no_transform to keep them from being modified
9717 by the linker. If we ever have a relocation for the
9718 addi/addmi of the difference of two symbols we can remove this. */
9721 for (next_fragP
= fragP
; next_fragP
!= NULL
;
9722 next_fragP
= next_fragP
->fr_next
)
9724 next_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
9725 if (next_fragP
->tc_frag_data
.is_loop_target
)
9727 if (target_count
== 2)
9733 /* A map that keeps information on a per-subsegment basis. This is
9734 maintained during initial assembly, but is invalid once the
9735 subsegments are smashed together. I.E., it cannot be used during
9738 typedef struct subseg_map_struct
9746 float total_freq
; /* fall-through + branch target frequency */
9747 float target_freq
; /* branch target frequency alone */
9749 struct subseg_map_struct
*next
;
9753 static subseg_map
*sseg_map
= NULL
;
9756 get_subseg_info (segT seg
, subsegT subseg
)
9758 subseg_map
*subseg_e
;
9760 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
9762 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
9770 add_subseg_info (segT seg
, subsegT subseg
)
9772 subseg_map
*subseg_e
= (subseg_map
*) xmalloc (sizeof (subseg_map
));
9773 memset (subseg_e
, 0, sizeof (subseg_map
));
9774 subseg_e
->seg
= seg
;
9775 subseg_e
->subseg
= subseg
;
9776 subseg_e
->flags
= 0;
9777 /* Start off considering every branch target very important. */
9778 subseg_e
->target_freq
= 1.0;
9779 subseg_e
->total_freq
= 1.0;
9780 subseg_e
->next
= sseg_map
;
9781 sseg_map
= subseg_e
;
9787 get_last_insn_flags (segT seg
, subsegT subseg
)
9789 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9791 return subseg_e
->flags
;
9797 set_last_insn_flags (segT seg
,
9802 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9804 subseg_e
= add_subseg_info (seg
, subseg
);
9806 subseg_e
->flags
|= fl
;
9808 subseg_e
->flags
&= ~fl
;
9813 get_subseg_total_freq (segT seg
, subsegT subseg
)
9815 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9817 return subseg_e
->total_freq
;
9823 get_subseg_target_freq (segT seg
, subsegT subseg
)
9825 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9827 return subseg_e
->target_freq
;
9833 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
9835 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9837 subseg_e
= add_subseg_info (seg
, subseg
);
9838 subseg_e
->total_freq
= total_f
;
9839 subseg_e
->target_freq
= target_f
;
9843 /* Segment Lists and emit_state Stuff. */
9846 xtensa_move_seg_list_to_beginning (seg_list
*head
)
9851 segT literal_section
= head
->seg
;
9853 /* Move the literal section to the front of the section list. */
9854 assert (literal_section
);
9855 if (literal_section
!= stdoutput
->sections
)
9857 bfd_section_list_remove (stdoutput
, literal_section
);
9858 bfd_section_list_prepend (stdoutput
, literal_section
);
9865 static void mark_literal_frags (seg_list
*);
9868 xtensa_move_literals (void)
9871 frchainS
*frchain_from
, *frchain_to
;
9872 fragS
*search_frag
, *next_frag
, *last_frag
, *literal_pool
, *insert_after
;
9873 fragS
**frag_splice
;
9876 fixS
*fix
, *next_fix
, **fix_splice
;
9879 mark_literal_frags (literal_head
->next
);
9881 if (use_literal_section
)
9884 for (segment
= literal_head
->next
; segment
; segment
= segment
->next
)
9886 /* Keep the literals for .init and .fini in separate sections. */
9887 if (!strcmp (segment_name (segment
->seg
), INIT_SECTION_NAME
)
9888 || !strcmp (segment_name (segment
->seg
), FINI_SECTION_NAME
))
9891 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9892 search_frag
= frchain_from
->frch_root
;
9893 literal_pool
= NULL
;
9895 frag_splice
= &(frchain_from
->frch_root
);
9897 while (!search_frag
->tc_frag_data
.literal_frag
)
9899 assert (search_frag
->fr_fix
== 0
9900 || search_frag
->fr_type
== rs_align
);
9901 search_frag
= search_frag
->fr_next
;
9904 assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
9905 == RELAX_LITERAL_POOL_BEGIN
);
9906 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
9908 /* Make sure that all the frags in this series are closed, and
9909 that there is at least one left over of zero-size. This
9910 prevents us from making a segment with an frchain without any
9912 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9913 xtensa_set_frag_assembly_state (frag_now
);
9914 last_frag
= frag_now
;
9915 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9916 xtensa_set_frag_assembly_state (frag_now
);
9918 while (search_frag
!= frag_now
)
9920 next_frag
= search_frag
->fr_next
;
9922 /* First, move the frag out of the literal section and
9923 to the appropriate place. */
9924 if (search_frag
->tc_frag_data
.literal_frag
)
9926 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
9927 assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
9928 frchain_to
= literal_pool
->tc_frag_data
.lit_frchain
;
9929 assert (frchain_to
);
9931 insert_after
= literal_pool
->tc_frag_data
.literal_frag
;
9932 dest_seg
= insert_after
->fr_next
->tc_frag_data
.lit_seg
;
9934 *frag_splice
= next_frag
;
9935 search_frag
->fr_next
= insert_after
->fr_next
;
9936 insert_after
->fr_next
= search_frag
;
9937 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
9938 literal_pool
->tc_frag_data
.literal_frag
= search_frag
;
9940 /* Now move any fixups associated with this frag to the
9942 fix
= frchain_from
->fix_root
;
9943 fix_splice
= &(frchain_from
->fix_root
);
9946 next_fix
= fix
->fx_next
;
9947 if (fix
->fx_frag
== search_frag
)
9949 *fix_splice
= next_fix
;
9950 fix
->fx_next
= frchain_to
->fix_root
;
9951 frchain_to
->fix_root
= fix
;
9952 if (frchain_to
->fix_tail
== NULL
)
9953 frchain_to
->fix_tail
= fix
;
9956 fix_splice
= &(fix
->fx_next
);
9959 search_frag
= next_frag
;
9962 if (frchain_from
->fix_root
!= NULL
)
9964 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9965 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
9967 assert (frchain_from
->fix_root
== NULL
);
9969 frchain_from
->fix_tail
= NULL
;
9970 xtensa_restore_emit_state (&state
);
9973 /* Now fix up the SEGMENT value for all the literal symbols. */
9974 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
9976 symbolS
*lit_sym
= lit
->sym
;
9977 segT dest_seg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
9979 S_SET_SEGMENT (lit_sym
, dest_seg
);
9984 /* Walk over all the frags for segments in a list and mark them as
9985 containing literals. As clunky as this is, we can't rely on frag_var
9986 and frag_variant to get called in all situations. */
9989 mark_literal_frags (seg_list
*segment
)
9991 frchainS
*frchain_from
;
9996 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9997 search_frag
= frchain_from
->frch_root
;
10000 search_frag
->tc_frag_data
.is_literal
= TRUE
;
10001 search_frag
= search_frag
->fr_next
;
10003 segment
= segment
->next
;
10009 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
10011 /* Move all of the sections in the section list to come
10012 after "after" in the gnu segment list. */
10017 segT literal_section
= head
->seg
;
10019 /* Move the literal section after "after". */
10020 assert (literal_section
);
10021 if (literal_section
!= after
)
10023 bfd_section_list_remove (stdoutput
, literal_section
);
10024 bfd_section_list_insert_after (stdoutput
, after
, literal_section
);
10032 /* Push all the literal segments to the end of the gnu list. */
10035 xtensa_reorder_segments (void)
10042 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
10048 /* Now that we have the last section, push all the literal
10049 sections to the end. */
10050 xtensa_reorder_seg_list (literal_head
, last_sec
);
10052 /* Now perform the final error check. */
10053 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
10055 assert (new_count
== old_count
);
10059 /* Change the emit state (seg, subseg, and frag related stuff) to the
10060 correct location. Return a emit_state which can be passed to
10061 xtensa_restore_emit_state to return to current fragment. */
10064 xtensa_switch_to_literal_fragment (emit_state
*result
)
10066 if (directive_state
[directive_absolute_literals
])
10068 segT lit4_seg
= cache_literal_section (TRUE
);
10069 xtensa_switch_section_emit_state (result
, lit4_seg
, 0);
10072 xtensa_switch_to_non_abs_literal_fragment (result
);
10074 /* Do a 4-byte align here. */
10075 frag_align (2, 0, 0);
10076 record_alignment (now_seg
, 2);
10081 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
10083 static bfd_boolean recursive
= FALSE
;
10084 fragS
*pool_location
= get_literal_pool_location (now_seg
);
10086 bfd_boolean is_init
=
10087 (now_seg
&& !strcmp (segment_name (now_seg
), INIT_SECTION_NAME
));
10088 bfd_boolean is_fini
=
10089 (now_seg
&& !strcmp (segment_name (now_seg
), FINI_SECTION_NAME
));
10091 if (pool_location
== NULL
10092 && !use_literal_section
10094 && !is_init
&& ! is_fini
)
10096 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
10098 /* When we mark a literal pool location, we want to put a frag in
10099 the literal pool that points to it. But to do that, we want to
10100 switch_to_literal_fragment. But literal sections don't have
10101 literal pools, so their location is always null, so we would
10102 recurse forever. This is kind of hacky, but it works. */
10105 xtensa_mark_literal_pool_location ();
10109 lit_seg
= cache_literal_section (FALSE
);
10110 xtensa_switch_section_emit_state (result
, lit_seg
, 0);
10112 if (!use_literal_section
10113 && !is_init
&& !is_fini
10114 && get_literal_pool_location (now_seg
) != pool_location
)
10116 /* Close whatever frag is there. */
10117 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10118 xtensa_set_frag_assembly_state (frag_now
);
10119 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
10120 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10121 xtensa_set_frag_assembly_state (frag_now
);
10126 /* Call this function before emitting data into the literal section.
10127 This is a helper function for xtensa_switch_to_literal_fragment.
10128 This is similar to a .section new_now_seg subseg. */
10131 xtensa_switch_section_emit_state (emit_state
*state
,
10133 subsegT new_now_subseg
)
10135 state
->name
= now_seg
->name
;
10136 state
->now_seg
= now_seg
;
10137 state
->now_subseg
= now_subseg
;
10138 state
->generating_literals
= generating_literals
;
10139 generating_literals
++;
10140 subseg_set (new_now_seg
, new_now_subseg
);
10144 /* Use to restore the emitting into the normal place. */
10147 xtensa_restore_emit_state (emit_state
*state
)
10149 generating_literals
= state
->generating_literals
;
10150 subseg_set (state
->now_seg
, state
->now_subseg
);
10154 /* Predicate function used to look up a section in a particular group. */
10157 match_section_group (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
, void *inf
)
10159 const char *gname
= inf
;
10160 const char *group_name
= elf_group_name (sec
);
10162 return (group_name
== gname
10163 || (group_name
!= NULL
10165 && strcmp (group_name
, gname
) == 0));
10169 /* Get the literal section to be used for the current text section.
10170 The result may be cached in the default_lit_sections structure. */
10173 cache_literal_section (bfd_boolean use_abs_literals
)
10175 const char *text_name
, *group_name
= 0;
10176 char *base_name
, *name
, *suffix
;
10178 segT seg
, current_section
;
10179 int current_subsec
;
10180 bfd_boolean linkonce
= FALSE
;
10182 /* Save the current section/subsection. */
10183 current_section
= now_seg
;
10184 current_subsec
= now_subseg
;
10186 /* Clear the cached values if they are no longer valid. */
10187 if (now_seg
!= default_lit_sections
.current_text_seg
)
10189 default_lit_sections
.current_text_seg
= now_seg
;
10190 default_lit_sections
.lit_seg
= NULL
;
10191 default_lit_sections
.lit4_seg
= NULL
;
10194 /* Check if the literal section is already cached. */
10195 if (use_abs_literals
)
10196 pcached
= &default_lit_sections
.lit4_seg
;
10198 pcached
= &default_lit_sections
.lit_seg
;
10203 text_name
= default_lit_sections
.lit_prefix
;
10204 if (! text_name
|| ! *text_name
)
10206 text_name
= segment_name (current_section
);
10207 group_name
= elf_group_name (current_section
);
10208 linkonce
= (current_section
->flags
& SEC_LINK_ONCE
) != 0;
10211 base_name
= use_abs_literals
? ".lit4" : ".literal";
10214 name
= xmalloc (strlen (base_name
) + strlen (group_name
) + 2);
10215 sprintf (name
, "%s.%s", base_name
, group_name
);
10217 else if (strncmp (text_name
, ".gnu.linkonce.", linkonce_len
) == 0)
10219 suffix
= strchr (text_name
+ linkonce_len
, '.');
10221 name
= xmalloc (linkonce_len
+ strlen (base_name
) + 1
10222 + (suffix
? strlen (suffix
) : 0));
10223 strcpy (name
, ".gnu.linkonce");
10224 strcat (name
, base_name
);
10226 strcat (name
, suffix
);
10231 /* If the section name ends with ".text", then replace that suffix
10232 instead of appending an additional suffix. */
10233 size_t len
= strlen (text_name
);
10234 if (len
>= 5 && strcmp (text_name
+ len
- 5, ".text") == 0)
10237 name
= xmalloc (len
+ strlen (base_name
) + 1);
10238 strcpy (name
, text_name
);
10239 strcpy (name
+ len
, base_name
);
10242 /* Canonicalize section names to allow renaming literal sections.
10243 The group name, if any, came from the current text section and
10244 has already been canonicalized. */
10245 name
= tc_canonicalize_symbol_name (name
);
10247 seg
= bfd_get_section_by_name_if (stdoutput
, name
, match_section_group
,
10248 (void *) group_name
);
10253 seg
= subseg_force_new (name
, 0);
10255 if (! use_abs_literals
)
10257 /* Add the newly created literal segment to the list. */
10258 seg_list
*n
= (seg_list
*) xmalloc (sizeof (seg_list
));
10260 n
->next
= literal_head
->next
;
10261 literal_head
->next
= n
;
10264 flags
= (SEC_HAS_CONTENTS
| SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
10265 | (linkonce
? (SEC_LINK_ONCE
| SEC_LINK_DUPLICATES_DISCARD
) : 0)
10266 | (use_abs_literals
? SEC_DATA
: SEC_CODE
));
10268 elf_group_name (seg
) = group_name
;
10270 bfd_set_section_flags (stdoutput
, seg
, flags
);
10271 bfd_set_section_alignment (stdoutput
, seg
, 2);
10275 subseg_set (current_section
, current_subsec
);
10280 /* Property Tables Stuff. */
10282 #define XTENSA_INSN_SEC_NAME ".xt.insn"
10283 #define XTENSA_LIT_SEC_NAME ".xt.lit"
10284 #define XTENSA_PROP_SEC_NAME ".xt.prop"
10286 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
10287 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
10289 static bfd_boolean
get_frag_is_literal (const fragS
*);
10290 static void xtensa_create_property_segments
10291 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
10292 static void xtensa_create_xproperty_segments
10293 (frag_flags_fn
, const char *, xt_section_type
);
10294 static bfd_boolean
section_has_property (segT
, frag_predicate
);
10295 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
10296 static void add_xt_block_frags
10297 (segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
10298 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
10299 static void xtensa_frag_flags_init (frag_flags
*);
10300 static void get_frag_property_flags (const fragS
*, frag_flags
*);
10301 static bfd_vma
frag_flags_to_number (const frag_flags
*);
10302 static void add_xt_prop_frags (segT
, xtensa_block_info
**, frag_flags_fn
);
10304 /* Set up property tables after relaxation. */
10307 xtensa_post_relax_hook (void)
10309 xtensa_move_seg_list_to_beginning (literal_head
);
10311 xtensa_find_unmarked_state_frags ();
10312 xtensa_mark_frags_for_org ();
10313 xtensa_mark_difference_of_two_symbols ();
10315 xtensa_create_property_segments (get_frag_is_literal
,
10317 XTENSA_LIT_SEC_NAME
,
10319 xtensa_create_xproperty_segments (get_frag_property_flags
,
10320 XTENSA_PROP_SEC_NAME
,
10323 if (warn_unaligned_branch_targets
)
10324 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
10325 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
10329 /* This function is only meaningful after xtensa_move_literals. */
10332 get_frag_is_literal (const fragS
*fragP
)
10334 assert (fragP
!= NULL
);
10335 return fragP
->tc_frag_data
.is_literal
;
10340 xtensa_create_property_segments (frag_predicate property_function
,
10341 frag_predicate end_property_function
,
10342 const char *section_name_base
,
10343 xt_section_type sec_type
)
10347 /* Walk over all of the current segments.
10348 Walk over each fragment
10349 For each non-empty fragment,
10350 Build a property record (append where possible). */
10352 for (seclist
= &stdoutput
->sections
;
10353 seclist
&& *seclist
;
10354 seclist
= &(*seclist
)->next
)
10356 segT sec
= *seclist
;
10359 flags
= bfd_get_section_flags (stdoutput
, sec
);
10360 if (flags
& SEC_DEBUGGING
)
10362 if (!(flags
& SEC_ALLOC
))
10365 if (section_has_property (sec
, property_function
))
10367 segment_info_type
*xt_seg_info
;
10368 xtensa_block_info
**xt_blocks
;
10369 segT prop_sec
= xtensa_get_property_section (sec
, section_name_base
);
10371 prop_sec
->output_section
= prop_sec
;
10372 subseg_set (prop_sec
, 0);
10373 xt_seg_info
= seg_info (prop_sec
);
10374 xt_blocks
= &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10376 /* Walk over all of the frchains here and add new sections. */
10377 add_xt_block_frags (sec
, xt_blocks
, property_function
,
10378 end_property_function
);
10382 /* Now we fill them out.... */
10384 for (seclist
= &stdoutput
->sections
;
10385 seclist
&& *seclist
;
10386 seclist
= &(*seclist
)->next
)
10388 segment_info_type
*seginfo
;
10389 xtensa_block_info
*block
;
10390 segT sec
= *seclist
;
10392 seginfo
= seg_info (sec
);
10393 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10397 xtensa_block_info
*cur_block
;
10399 bfd_size_type rec_size
;
10401 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10404 rec_size
= num_recs
* 8;
10405 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10412 subseg_set (sec
, 0);
10413 frag_data
= frag_more (rec_size
);
10415 for (i
= 0; i
< num_recs
; i
++)
10419 /* Write the fixup. */
10420 assert (cur_block
);
10421 fix
= fix_new (frag_now
, i
* 8, 4,
10422 section_symbol (cur_block
->sec
),
10424 FALSE
, BFD_RELOC_32
);
10425 fix
->fx_file
= "<internal>";
10428 /* Write the length. */
10429 md_number_to_chars (&frag_data
[4 + i
* 8],
10430 cur_block
->size
, 4);
10431 cur_block
= cur_block
->next
;
10433 frag_wane (frag_now
);
10435 frag_wane (frag_now
);
10443 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
10444 const char *section_name_base
,
10445 xt_section_type sec_type
)
10449 /* Walk over all of the current segments.
10450 Walk over each fragment.
10451 For each fragment that has instructions,
10452 build an instruction record (append where possible). */
10454 for (seclist
= &stdoutput
->sections
;
10455 seclist
&& *seclist
;
10456 seclist
= &(*seclist
)->next
)
10458 segT sec
= *seclist
;
10461 flags
= bfd_get_section_flags (stdoutput
, sec
);
10462 if ((flags
& SEC_DEBUGGING
)
10463 || !(flags
& SEC_ALLOC
)
10464 || (flags
& SEC_MERGE
))
10467 if (section_has_xproperty (sec
, flag_fn
))
10469 segment_info_type
*xt_seg_info
;
10470 xtensa_block_info
**xt_blocks
;
10471 segT prop_sec
= xtensa_get_property_section (sec
, section_name_base
);
10473 prop_sec
->output_section
= prop_sec
;
10474 subseg_set (prop_sec
, 0);
10475 xt_seg_info
= seg_info (prop_sec
);
10476 xt_blocks
= &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10478 /* Walk over all of the frchains here and add new sections. */
10479 add_xt_prop_frags (sec
, xt_blocks
, flag_fn
);
10483 /* Now we fill them out.... */
10485 for (seclist
= &stdoutput
->sections
;
10486 seclist
&& *seclist
;
10487 seclist
= &(*seclist
)->next
)
10489 segment_info_type
*seginfo
;
10490 xtensa_block_info
*block
;
10491 segT sec
= *seclist
;
10493 seginfo
= seg_info (sec
);
10494 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10498 xtensa_block_info
*cur_block
;
10500 bfd_size_type rec_size
;
10502 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10505 rec_size
= num_recs
* (8 + 4);
10506 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10507 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
10514 subseg_set (sec
, 0);
10515 frag_data
= frag_more (rec_size
);
10517 for (i
= 0; i
< num_recs
; i
++)
10521 /* Write the fixup. */
10522 assert (cur_block
);
10523 fix
= fix_new (frag_now
, i
* 12, 4,
10524 section_symbol (cur_block
->sec
),
10526 FALSE
, BFD_RELOC_32
);
10527 fix
->fx_file
= "<internal>";
10530 /* Write the length. */
10531 md_number_to_chars (&frag_data
[4 + i
* 12],
10532 cur_block
->size
, 4);
10533 md_number_to_chars (&frag_data
[8 + i
* 12],
10534 frag_flags_to_number (&cur_block
->flags
),
10536 cur_block
= cur_block
->next
;
10538 frag_wane (frag_now
);
10540 frag_wane (frag_now
);
10548 section_has_property (segT sec
, frag_predicate property_function
)
10550 segment_info_type
*seginfo
= seg_info (sec
);
10553 if (seginfo
&& seginfo
->frchainP
)
10555 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10557 if (property_function (fragP
)
10558 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10567 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
10569 segment_info_type
*seginfo
= seg_info (sec
);
10572 if (seginfo
&& seginfo
->frchainP
)
10574 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10576 frag_flags prop_flags
;
10577 property_function (fragP
, &prop_flags
);
10578 if (!xtensa_frag_flags_is_empty (&prop_flags
))
10586 /* Two types of block sections exist right now: literal and insns. */
10589 add_xt_block_frags (segT sec
,
10590 xtensa_block_info
**xt_block
,
10591 frag_predicate property_function
,
10592 frag_predicate end_property_function
)
10594 bfd_vma seg_offset
;
10597 /* Build it if needed. */
10598 while (*xt_block
!= NULL
)
10599 xt_block
= &(*xt_block
)->next
;
10600 /* We are either at NULL at the beginning or at the end. */
10602 /* Walk through the frags. */
10605 if (seg_info (sec
)->frchainP
)
10607 for (fragP
= seg_info (sec
)->frchainP
->frch_root
;
10609 fragP
= fragP
->fr_next
)
10611 if (property_function (fragP
)
10612 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10614 if (*xt_block
!= NULL
)
10616 if ((*xt_block
)->offset
+ (*xt_block
)->size
10617 == fragP
->fr_address
)
10618 (*xt_block
)->size
+= fragP
->fr_fix
;
10620 xt_block
= &((*xt_block
)->next
);
10622 if (*xt_block
== NULL
)
10624 xtensa_block_info
*new_block
= (xtensa_block_info
*)
10625 xmalloc (sizeof (xtensa_block_info
));
10626 new_block
->sec
= sec
;
10627 new_block
->offset
= fragP
->fr_address
;
10628 new_block
->size
= fragP
->fr_fix
;
10629 new_block
->next
= NULL
;
10630 xtensa_frag_flags_init (&new_block
->flags
);
10631 *xt_block
= new_block
;
10633 if (end_property_function
10634 && end_property_function (fragP
))
10636 xt_block
= &((*xt_block
)->next
);
10644 /* Break the encapsulation of add_xt_prop_frags here. */
10647 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
10649 if (prop_flags
->is_literal
10650 || prop_flags
->is_insn
10651 || prop_flags
->is_data
10652 || prop_flags
->is_unreachable
)
10659 xtensa_frag_flags_init (frag_flags
*prop_flags
)
10661 memset (prop_flags
, 0, sizeof (frag_flags
));
10666 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
10668 xtensa_frag_flags_init (prop_flags
);
10669 if (fragP
->tc_frag_data
.is_literal
)
10670 prop_flags
->is_literal
= TRUE
;
10671 if (fragP
->tc_frag_data
.is_specific_opcode
10672 || fragP
->tc_frag_data
.is_no_transform
)
10673 prop_flags
->is_no_transform
= TRUE
;
10674 if (fragP
->tc_frag_data
.is_unreachable
)
10675 prop_flags
->is_unreachable
= TRUE
;
10676 else if (fragP
->tc_frag_data
.is_insn
)
10678 prop_flags
->is_insn
= TRUE
;
10679 if (fragP
->tc_frag_data
.is_loop_target
)
10680 prop_flags
->insn
.is_loop_target
= TRUE
;
10681 if (fragP
->tc_frag_data
.is_branch_target
)
10682 prop_flags
->insn
.is_branch_target
= TRUE
;
10683 if (fragP
->tc_frag_data
.is_no_density
)
10684 prop_flags
->insn
.is_no_density
= TRUE
;
10685 if (fragP
->tc_frag_data
.use_absolute_literals
)
10686 prop_flags
->insn
.is_abslit
= TRUE
;
10688 if (fragP
->tc_frag_data
.is_align
)
10690 prop_flags
->is_align
= TRUE
;
10691 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
10692 if (xtensa_frag_flags_is_empty (prop_flags
))
10693 prop_flags
->is_data
= TRUE
;
10699 frag_flags_to_number (const frag_flags
*prop_flags
)
10702 if (prop_flags
->is_literal
)
10703 num
|= XTENSA_PROP_LITERAL
;
10704 if (prop_flags
->is_insn
)
10705 num
|= XTENSA_PROP_INSN
;
10706 if (prop_flags
->is_data
)
10707 num
|= XTENSA_PROP_DATA
;
10708 if (prop_flags
->is_unreachable
)
10709 num
|= XTENSA_PROP_UNREACHABLE
;
10710 if (prop_flags
->insn
.is_loop_target
)
10711 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
10712 if (prop_flags
->insn
.is_branch_target
)
10714 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
10715 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
10718 if (prop_flags
->insn
.is_no_density
)
10719 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
10720 if (prop_flags
->is_no_transform
)
10721 num
|= XTENSA_PROP_NO_TRANSFORM
;
10722 if (prop_flags
->insn
.is_no_reorder
)
10723 num
|= XTENSA_PROP_INSN_NO_REORDER
;
10724 if (prop_flags
->insn
.is_abslit
)
10725 num
|= XTENSA_PROP_INSN_ABSLIT
;
10727 if (prop_flags
->is_align
)
10729 num
|= XTENSA_PROP_ALIGN
;
10730 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
10738 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
10739 const frag_flags
*prop_flags_2
)
10741 /* Cannot combine with an end marker. */
10743 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
10745 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
10747 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
10750 if (prop_flags_1
->is_insn
)
10752 /* Properties of the beginning of the frag. */
10753 if (prop_flags_2
->insn
.is_loop_target
)
10755 if (prop_flags_2
->insn
.is_branch_target
)
10757 if (prop_flags_1
->insn
.is_no_density
!=
10758 prop_flags_2
->insn
.is_no_density
)
10760 if (prop_flags_1
->is_no_transform
!=
10761 prop_flags_2
->is_no_transform
)
10763 if (prop_flags_1
->insn
.is_no_reorder
!=
10764 prop_flags_2
->insn
.is_no_reorder
)
10766 if (prop_flags_1
->insn
.is_abslit
!=
10767 prop_flags_2
->insn
.is_abslit
)
10771 if (prop_flags_1
->is_align
)
10779 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
10782 unsigned align_bits
;
10784 if (!xt_block
->flags
.is_align
)
10785 return xt_block
->size
;
10787 end_addr
= xt_block
->offset
+ xt_block
->size
;
10788 align_bits
= xt_block
->flags
.alignment
;
10789 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
10790 return end_addr
- xt_block
->offset
;
10795 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
10796 const xtensa_block_info
*xt_block_2
)
10798 if (xt_block
->sec
!= xt_block_2
->sec
)
10800 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
10801 != xt_block_2
->offset
)
10804 if (xt_block_2
->size
== 0
10805 && (!xt_block_2
->flags
.is_unreachable
10806 || xt_block
->flags
.is_unreachable
))
10808 if (xt_block_2
->flags
.is_align
10809 && xt_block
->flags
.is_align
)
10811 /* Nothing needed. */
10812 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
10817 if (xt_block_2
->flags
.is_align
)
10819 /* Push alignment to previous entry. */
10820 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
10821 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10826 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
10827 &xt_block_2
->flags
))
10830 xt_block
->size
+= xt_block_2
->size
;
10832 if (xt_block_2
->flags
.is_align
)
10834 xt_block
->flags
.is_align
= TRUE
;
10835 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10843 add_xt_prop_frags (segT sec
,
10844 xtensa_block_info
**xt_block
,
10845 frag_flags_fn property_function
)
10847 bfd_vma seg_offset
;
10850 /* Build it if needed. */
10851 while (*xt_block
!= NULL
)
10853 xt_block
= &(*xt_block
)->next
;
10855 /* We are either at NULL at the beginning or at the end. */
10857 /* Walk through the frags. */
10860 if (seg_info (sec
)->frchainP
)
10862 for (fragP
= seg_info (sec
)->frchainP
->frch_root
; fragP
;
10863 fragP
= fragP
->fr_next
)
10865 xtensa_block_info tmp_block
;
10866 tmp_block
.sec
= sec
;
10867 tmp_block
.offset
= fragP
->fr_address
;
10868 tmp_block
.size
= fragP
->fr_fix
;
10869 tmp_block
.next
= NULL
;
10870 property_function (fragP
, &tmp_block
.flags
);
10872 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
10873 /* && fragP->fr_fix != 0) */
10875 if ((*xt_block
) == NULL
10876 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
10878 xtensa_block_info
*new_block
;
10879 if ((*xt_block
) != NULL
)
10880 xt_block
= &(*xt_block
)->next
;
10881 new_block
= (xtensa_block_info
*)
10882 xmalloc (sizeof (xtensa_block_info
));
10883 *new_block
= tmp_block
;
10884 *xt_block
= new_block
;
10892 /* op_placement_info_table */
10894 /* op_placement_info makes it easier to determine which
10895 ops can go in which slots. */
10898 init_op_placement_info_table (void)
10900 xtensa_isa isa
= xtensa_default_isa
;
10901 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
10902 xtensa_opcode opcode
;
10905 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
10907 op_placement_table
= (op_placement_info_table
)
10908 xmalloc (sizeof (op_placement_info
) * num_opcodes
);
10909 assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
10911 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
10913 op_placement_info
*opi
= &op_placement_table
[opcode
];
10914 /* FIXME: Make tinsn allocation dynamic. */
10915 if (xtensa_opcode_num_operands (isa
, opcode
) >= MAX_INSN_ARGS
)
10916 as_fatal (_("too many operands in instruction"));
10917 opi
->narrowest
= XTENSA_UNDEFINED
;
10918 opi
->narrowest_size
= 0x7F;
10919 opi
->narrowest_slot
= 0;
10921 opi
->num_formats
= 0;
10923 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
10925 opi
->slots
[fmt
] = 0;
10926 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
10928 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
10930 int fmt_length
= xtensa_format_length (isa
, fmt
);
10932 set_bit (fmt
, opi
->formats
);
10933 set_bit (slot
, opi
->slots
[fmt
]);
10934 if (fmt_length
< opi
->narrowest_size
10935 || (fmt_length
== opi
->narrowest_size
10936 && (xtensa_format_num_slots (isa
, fmt
)
10937 < xtensa_format_num_slots (isa
,
10940 opi
->narrowest
= fmt
;
10941 opi
->narrowest_size
= fmt_length
;
10942 opi
->narrowest_slot
= slot
;
10947 opi
->num_formats
++;
10950 xtensa_insnbuf_free (isa
, ibuf
);
10955 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
10957 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
10961 /* If the opcode is available in a single slot format, return its size. */
10964 xg_get_single_size (xtensa_opcode opcode
)
10966 return op_placement_table
[opcode
].narrowest_size
;
10970 static xtensa_format
10971 xg_get_single_format (xtensa_opcode opcode
)
10973 return op_placement_table
[opcode
].narrowest
;
10978 xg_get_single_slot (xtensa_opcode opcode
)
10980 return op_placement_table
[opcode
].narrowest_slot
;
10984 /* Instruction Stack Functions (from "xtensa-istack.h"). */
10987 istack_init (IStack
*stack
)
10989 memset (stack
, 0, sizeof (IStack
));
10995 istack_empty (IStack
*stack
)
10997 return (stack
->ninsn
== 0);
11002 istack_full (IStack
*stack
)
11004 return (stack
->ninsn
== MAX_ISTACK
);
11008 /* Return a pointer to the top IStack entry.
11009 It is an error to call this if istack_empty () is TRUE. */
11012 istack_top (IStack
*stack
)
11014 int rec
= stack
->ninsn
- 1;
11015 assert (!istack_empty (stack
));
11016 return &stack
->insn
[rec
];
11020 /* Add a new TInsn to an IStack.
11021 It is an error to call this if istack_full () is TRUE. */
11024 istack_push (IStack
*stack
, TInsn
*insn
)
11026 int rec
= stack
->ninsn
;
11027 assert (!istack_full (stack
));
11028 stack
->insn
[rec
] = *insn
;
11033 /* Clear space for the next TInsn on the IStack and return a pointer
11034 to it. It is an error to call this if istack_full () is TRUE. */
11037 istack_push_space (IStack
*stack
)
11039 int rec
= stack
->ninsn
;
11041 assert (!istack_full (stack
));
11042 insn
= &stack
->insn
[rec
];
11049 /* Remove the last pushed instruction. It is an error to call this if
11050 istack_empty () returns TRUE. */
11053 istack_pop (IStack
*stack
)
11055 int rec
= stack
->ninsn
- 1;
11056 assert (!istack_empty (stack
));
11058 tinsn_init (&stack
->insn
[rec
]);
11062 /* TInsn functions. */
11065 tinsn_init (TInsn
*dst
)
11067 memset (dst
, 0, sizeof (TInsn
));
11071 /* Return TRUE if ANY of the operands in the insn are symbolic. */
11074 tinsn_has_symbolic_operands (const TInsn
*insn
)
11077 int n
= insn
->ntok
;
11079 assert (insn
->insn_type
== ITYPE_INSN
);
11081 for (i
= 0; i
< n
; ++i
)
11083 switch (insn
->tok
[i
].X_op
)
11097 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
11099 xtensa_isa isa
= xtensa_default_isa
;
11101 int n
= insn
->ntok
;
11103 assert (insn
->insn_type
== ITYPE_INSN
);
11105 for (i
= 0; i
< n
; ++i
)
11107 switch (insn
->tok
[i
].X_op
)
11115 /* Errors for these types are caught later. */
11120 /* Symbolic immediates are only allowed on the last immediate
11121 operand. At this time, CONST16 is the only opcode where we
11122 support non-PC-relative relocations. */
11123 if (i
!= get_relaxable_immed (insn
->opcode
)
11124 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
11125 && insn
->opcode
!= xtensa_const16_opcode
))
11127 as_bad (_("invalid symbolic operand"));
11136 /* For assembly code with complex expressions (e.g. subtraction),
11137 we have to build them in the literal pool so that
11138 their results are calculated correctly after relaxation.
11139 The relaxation only handles expressions that
11140 boil down to SYMBOL + OFFSET. */
11143 tinsn_has_complex_operands (const TInsn
*insn
)
11146 int n
= insn
->ntok
;
11147 assert (insn
->insn_type
== ITYPE_INSN
);
11148 for (i
= 0; i
< n
; ++i
)
11150 switch (insn
->tok
[i
].X_op
)
11166 /* Encode a TInsn opcode and its constant operands into slotbuf.
11167 Return TRUE if there is a symbol in the immediate field. This
11168 function assumes that:
11169 1) The number of operands are correct.
11170 2) The insn_type is ITYPE_INSN.
11171 3) The opcode can be encoded in the specified format and slot.
11172 4) Operands are either O_constant or O_symbol, and all constants fit. */
11175 tinsn_to_slotbuf (xtensa_format fmt
,
11178 xtensa_insnbuf slotbuf
)
11180 xtensa_isa isa
= xtensa_default_isa
;
11181 xtensa_opcode opcode
= tinsn
->opcode
;
11182 bfd_boolean has_fixup
= FALSE
;
11183 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11186 assert (tinsn
->insn_type
== ITYPE_INSN
);
11187 if (noperands
!= tinsn
->ntok
)
11188 as_fatal (_("operand number mismatch"));
11190 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
11192 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
11193 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
11197 for (i
= 0; i
< noperands
; i
++)
11199 expressionS
*expr
= &tinsn
->tok
[i
];
11205 switch (expr
->X_op
)
11208 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11210 /* The register number has already been checked in
11211 expression_maybe_register, so we don't need to check here. */
11212 opnd_value
= expr
->X_add_number
;
11213 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11214 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
11217 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
11221 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11223 as_where (&file_name
, &line
);
11224 /* It is a constant and we called this function
11225 then we have to try to fit it. */
11226 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
11227 expr
->X_add_number
, file_name
, line
);
11240 /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded
11241 into a multi-slot instruction, fill the other slots with NOPs.
11242 Return TRUE if there is a symbol in the immediate field. See also the
11243 assumptions listed for tinsn_to_slotbuf. */
11246 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
11248 static xtensa_insnbuf slotbuf
= 0;
11249 static vliw_insn vinsn
;
11250 xtensa_isa isa
= xtensa_default_isa
;
11251 bfd_boolean has_fixup
= FALSE
;
11256 slotbuf
= xtensa_insnbuf_alloc (isa
);
11257 xg_init_vinsn (&vinsn
);
11260 xg_clear_vinsn (&vinsn
);
11262 bundle_tinsn (tinsn
, &vinsn
);
11264 xtensa_format_encode (isa
, vinsn
.format
, insnbuf
);
11266 for (i
= 0; i
< vinsn
.num_slots
; i
++)
11268 /* Only one slot may have a fix-up because the rest contains NOPs. */
11270 tinsn_to_slotbuf (vinsn
.format
, i
, &vinsn
.slots
[i
], vinsn
.slotbuf
[i
]);
11271 xtensa_format_set_slot (isa
, vinsn
.format
, i
, insnbuf
, vinsn
.slotbuf
[i
]);
11278 /* Check the instruction arguments. Return TRUE on failure. */
11281 tinsn_check_arguments (const TInsn
*insn
)
11283 xtensa_isa isa
= xtensa_default_isa
;
11284 xtensa_opcode opcode
= insn
->opcode
;
11286 if (opcode
== XTENSA_UNDEFINED
)
11288 as_bad (_("invalid opcode"));
11292 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
11294 as_bad (_("too few operands"));
11298 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
11300 as_bad (_("too many operands"));
11307 /* Load an instruction from its encoded form. */
11310 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
11314 xg_init_vinsn (&vinsn
);
11315 vinsn_from_chars (&vinsn
, f
);
11317 *tinsn
= vinsn
.slots
[slot
];
11318 xg_free_vinsn (&vinsn
);
11323 tinsn_from_insnbuf (TInsn
*tinsn
,
11324 xtensa_insnbuf slotbuf
,
11329 xtensa_isa isa
= xtensa_default_isa
;
11331 /* Find the immed. */
11332 tinsn_init (tinsn
);
11333 tinsn
->insn_type
= ITYPE_INSN
;
11334 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
11335 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
11336 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
11337 for (i
= 0; i
< tinsn
->ntok
; i
++)
11339 set_expr_const (&tinsn
->tok
[i
],
11340 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
11341 tinsn
->opcode
, i
));
11346 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
11349 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
11351 xtensa_opcode opcode
= tinsn
->opcode
;
11354 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
11356 opnum
= get_relaxable_immed (opcode
);
11357 assert (opnum
>= 0);
11358 set_expr_symbol_offset (&tinsn
->tok
[opnum
],
11359 fragP
->tc_frag_data
.slot_symbols
[slot
],
11360 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11366 get_num_stack_text_bytes (IStack
*istack
)
11369 int text_bytes
= 0;
11371 for (i
= 0; i
< istack
->ninsn
; i
++)
11373 TInsn
*tinsn
= &istack
->insn
[i
];
11374 if (tinsn
->insn_type
== ITYPE_INSN
)
11375 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
11382 get_num_stack_literal_bytes (IStack
*istack
)
11387 for (i
= 0; i
< istack
->ninsn
; i
++)
11389 TInsn
*tinsn
= &istack
->insn
[i
];
11390 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
11397 /* vliw_insn functions. */
11400 xg_init_vinsn (vliw_insn
*v
)
11403 xtensa_isa isa
= xtensa_default_isa
;
11405 xg_clear_vinsn (v
);
11407 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
11408 if (v
->insnbuf
== NULL
)
11409 as_fatal (_("out of memory"));
11411 for (i
= 0; i
< MAX_SLOTS
; i
++)
11413 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
11414 if (v
->slotbuf
[i
] == NULL
)
11415 as_fatal (_("out of memory"));
11421 xg_clear_vinsn (vliw_insn
*v
)
11425 memset (v
, 0, offsetof (vliw_insn
, insnbuf
));
11427 v
->format
= XTENSA_UNDEFINED
;
11429 v
->inside_bundle
= FALSE
;
11431 if (xt_saved_debug_type
!= DEBUG_NONE
)
11432 debug_type
= xt_saved_debug_type
;
11434 for (i
= 0; i
< MAX_SLOTS
; i
++)
11435 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
11440 vinsn_has_specific_opcodes (vliw_insn
*v
)
11444 for (i
= 0; i
< v
->num_slots
; i
++)
11446 if (v
->slots
[i
].is_specific_opcode
)
11454 xg_free_vinsn (vliw_insn
*v
)
11457 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
11458 for (i
= 0; i
< MAX_SLOTS
; i
++)
11459 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
11463 /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic
11464 operands. See also the assumptions listed for tinsn_to_slotbuf. */
11467 vinsn_to_insnbuf (vliw_insn
*vinsn
,
11470 bfd_boolean record_fixup
)
11472 xtensa_isa isa
= xtensa_default_isa
;
11473 xtensa_format fmt
= vinsn
->format
;
11474 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
11476 bfd_boolean has_fixup
= FALSE
;
11478 xtensa_format_encode (isa
, fmt
, insnbuf
);
11480 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
11482 TInsn
*tinsn
= &vinsn
->slots
[slot
];
11483 bfd_boolean tinsn_has_fixup
=
11484 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
11485 vinsn
->slotbuf
[slot
]);
11487 xtensa_format_set_slot (isa
, fmt
, slot
,
11488 insnbuf
, vinsn
->slotbuf
[slot
]);
11489 if (tinsn_has_fixup
)
11492 xtensa_opcode opcode
= tinsn
->opcode
;
11493 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11496 for (i
= 0; i
< noperands
; i
++)
11498 expressionS
* expr
= &tinsn
->tok
[i
];
11499 switch (expr
->X_op
)
11504 if (get_relaxable_immed (opcode
) == i
)
11506 /* Add a fix record for the instruction, except if this
11507 function is being called prior to relaxation, i.e.,
11508 if record_fixup is false, and the instruction might
11509 be relaxed later. */
11511 || tinsn
->is_specific_opcode
11512 || !xg_is_relaxable_insn (tinsn
, 0))
11514 xg_add_opcode_fix (tinsn
, i
, fmt
, slot
, expr
, fragP
,
11515 frag_offset
- fragP
->fr_literal
);
11519 if (expr
->X_op
!= O_symbol
)
11520 as_bad (_("invalid operand"));
11521 tinsn
->symbol
= expr
->X_add_symbol
;
11522 tinsn
->offset
= expr
->X_add_number
;
11526 as_bad (_("symbolic operand not allowed"));
11534 as_bad (_("expression too complex"));
11546 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
11548 static xtensa_insnbuf insnbuf
= NULL
;
11549 static xtensa_insnbuf slotbuf
= NULL
;
11552 xtensa_isa isa
= xtensa_default_isa
;
11556 insnbuf
= xtensa_insnbuf_alloc (isa
);
11557 slotbuf
= xtensa_insnbuf_alloc (isa
);
11560 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) f
, 0);
11561 fmt
= xtensa_format_decode (isa
, insnbuf
);
11562 if (fmt
== XTENSA_UNDEFINED
)
11563 as_fatal (_("cannot decode instruction format"));
11564 vinsn
->format
= fmt
;
11565 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
11567 for (i
= 0; i
< vinsn
->num_slots
; i
++)
11569 TInsn
*tinsn
= &vinsn
->slots
[i
];
11570 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
11571 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
11576 /* Expression utilities. */
11578 /* Return TRUE if the expression is an integer constant. */
11581 expr_is_const (const expressionS
*s
)
11583 return (s
->X_op
== O_constant
);
11587 /* Get the expression constant.
11588 Calling this is illegal if expr_is_const () returns TRUE. */
11591 get_expr_const (const expressionS
*s
)
11593 assert (expr_is_const (s
));
11594 return s
->X_add_number
;
11598 /* Set the expression to a constant value. */
11601 set_expr_const (expressionS
*s
, offsetT val
)
11603 s
->X_op
= O_constant
;
11604 s
->X_add_number
= val
;
11605 s
->X_add_symbol
= NULL
;
11606 s
->X_op_symbol
= NULL
;
11611 expr_is_register (const expressionS
*s
)
11613 return (s
->X_op
== O_register
);
11617 /* Get the expression constant.
11618 Calling this is illegal if expr_is_const () returns TRUE. */
11621 get_expr_register (const expressionS
*s
)
11623 assert (expr_is_register (s
));
11624 return s
->X_add_number
;
11628 /* Set the expression to a symbol + constant offset. */
11631 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
11633 s
->X_op
= O_symbol
;
11634 s
->X_add_symbol
= sym
;
11635 s
->X_op_symbol
= NULL
; /* unused */
11636 s
->X_add_number
= offset
;
11640 /* Return TRUE if the two expressions are equal. */
11643 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
11645 if (s1
->X_op
!= s2
->X_op
)
11647 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
11649 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
11651 if (s1
->X_add_number
!= s2
->X_add_number
)
11658 copy_expr (expressionS
*dst
, const expressionS
*src
)
11660 memcpy (dst
, src
, sizeof (expressionS
));
11664 /* Support for the "--rename-section" option. */
11666 struct rename_section_struct
11670 struct rename_section_struct
*next
;
11673 static struct rename_section_struct
*section_rename
;
11676 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
11677 entries to the section_rename list. Note: Specifying multiple
11678 renamings separated by colons is not documented and is retained only
11679 for backward compatibility. */
11682 build_section_rename (const char *arg
)
11684 struct rename_section_struct
*r
;
11685 char *this_arg
= NULL
;
11686 char *next_arg
= NULL
;
11688 for (this_arg
= xstrdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
11690 char *old_name
, *new_name
;
11694 next_arg
= strchr (this_arg
, ':');
11702 old_name
= this_arg
;
11703 new_name
= strchr (this_arg
, '=');
11705 if (*old_name
== '\0')
11707 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
11710 if (!new_name
|| new_name
[1] == '\0')
11712 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
11719 /* Check for invalid section renaming. */
11720 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11722 if (strcmp (r
->old_name
, old_name
) == 0)
11723 as_bad (_("section %s renamed multiple times"), old_name
);
11724 if (strcmp (r
->new_name
, new_name
) == 0)
11725 as_bad (_("multiple sections remapped to output section %s"),
11730 r
= (struct rename_section_struct
*)
11731 xmalloc (sizeof (struct rename_section_struct
));
11732 r
->old_name
= xstrdup (old_name
);
11733 r
->new_name
= xstrdup (new_name
);
11734 r
->next
= section_rename
;
11735 section_rename
= r
;
11741 xtensa_section_rename (char *name
)
11743 struct rename_section_struct
*r
= section_rename
;
11745 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11747 if (strcmp (r
->old_name
, name
) == 0)
11748 return r
->new_name
;