1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright 2003, 2004, 2005, 2006, 2007, 2008, 2009
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
25 #include "safe-ctype.h"
26 #include "tc-xtensa.h"
28 #include "xtensa-relax.h"
29 #include "dwarf2dbg.h"
30 #include "xtensa-istack.h"
31 #include "struc-symbol.h"
32 #include "xtensa-config.h"
34 /* Provide default values for new configuration settings. */
40 #define uint32 unsigned int
43 #define int32 signed int
48 Naming conventions (used somewhat inconsistently):
49 The xtensa_ functions are exported
50 The xg_ functions are internal
52 We also have a couple of different extensibility mechanisms.
53 1) The idiom replacement:
54 This is used when a line is first parsed to
55 replace an instruction pattern with another instruction
56 It is currently limited to replacements of instructions
57 with constant operands.
58 2) The xtensa-relax.c mechanism that has stronger instruction
59 replacement patterns. When an instruction's immediate field
60 does not fit the next instruction sequence is attempted.
61 In addition, "narrow" opcodes are supported this way. */
64 /* Define characters with special meanings to GAS. */
65 const char comment_chars
[] = "#";
66 const char line_comment_chars
[] = "#";
67 const char line_separator_chars
[] = ";";
68 const char EXP_CHARS
[] = "eE";
69 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
72 /* Flags to indicate whether the hardware supports the density and
73 absolute literals options. */
75 bfd_boolean density_supported
= XCHAL_HAVE_DENSITY
;
76 bfd_boolean absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
78 static vliw_insn cur_vinsn
;
80 unsigned xtensa_num_pipe_stages
;
81 unsigned xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
83 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
85 /* Some functions are only valid in the front end. This variable
86 allows us to assert that we haven't crossed over into the
88 static bfd_boolean past_xtensa_end
= FALSE
;
90 /* Flags for properties of the last instruction in a segment. */
91 #define FLAG_IS_A0_WRITER 0x1
92 #define FLAG_IS_BAD_LOOPEND 0x2
95 /* We define a special segment names ".literal" to place literals
96 into. The .fini and .init sections are special because they
97 contain code that is moved together by the linker. We give them
98 their own special .fini.literal and .init.literal sections. */
100 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
101 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
102 #define INIT_SECTION_NAME xtensa_section_rename (".init")
103 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
106 /* This type is used for the directive_stack to keep track of the
107 state of the literal collection pools. If lit_prefix is set, it is
108 used to determine the literal section names; otherwise, the literal
109 sections are determined based on the current text section. The
110 lit_seg and lit4_seg fields cache these literal sections, with the
111 current_text_seg field used a tag to indicate whether the cached
114 typedef struct lit_state_struct
117 segT current_text_seg
;
122 static lit_state default_lit_sections
;
125 /* We keep a list of literal segments. The seg_list type is the node
126 for this list. The literal_head pointer is the head of the list,
127 with the literal_head_h dummy node at the start. */
129 typedef struct seg_list_struct
131 struct seg_list_struct
*next
;
135 static seg_list literal_head_h
;
136 static seg_list
*literal_head
= &literal_head_h
;
139 /* Lists of symbols. We keep a list of symbols that label the current
140 instruction, so that we can adjust the symbols when inserting alignment
141 for various instructions. We also keep a list of all the symbols on
142 literals, so that we can fix up those symbols when the literals are
143 later moved into the text sections. */
145 typedef struct sym_list_struct
147 struct sym_list_struct
*next
;
151 static sym_list
*insn_labels
= NULL
;
152 static sym_list
*free_insn_labels
= NULL
;
153 static sym_list
*saved_insn_labels
= NULL
;
155 static sym_list
*literal_syms
;
158 /* Flags to determine whether to prefer const16 or l32r
159 if both options are available. */
160 int prefer_const16
= 0;
163 /* Global flag to indicate when we are emitting literals. */
164 int generating_literals
= 0;
166 /* The following PROPERTY table definitions are copied from
167 <elf/xtensa.h> and must be kept in sync with the code there. */
169 /* Flags in the property tables to specify whether blocks of memory
170 are literals, instructions, data, or unreachable. For
171 instructions, blocks that begin loop targets and branch targets are
172 designated. Blocks that do not allow density, instruction
173 reordering or transformation are also specified. Finally, for
174 branch targets, branch target alignment priority is included.
175 Alignment of the next block is specified in the current block
176 and the size of the current block does not include any fill required
177 to align to the next block. */
179 #define XTENSA_PROP_LITERAL 0x00000001
180 #define XTENSA_PROP_INSN 0x00000002
181 #define XTENSA_PROP_DATA 0x00000004
182 #define XTENSA_PROP_UNREACHABLE 0x00000008
183 /* Instruction only properties at beginning of code. */
184 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
185 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
186 /* Instruction only properties about code. */
187 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
188 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
189 /* Historically, NO_TRANSFORM was a property of instructions,
190 but it should apply to literals under certain circumstances. */
191 #define XTENSA_PROP_NO_TRANSFORM 0x00000100
193 /* Branch target alignment information. This transmits information
194 to the linker optimization about the priority of aligning a
195 particular block for branch target alignment: None, low priority,
196 high priority, or required. These only need to be checked in
197 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
200 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
201 case XTENSA_PROP_BT_ALIGN_NONE:
202 case XTENSA_PROP_BT_ALIGN_LOW:
203 case XTENSA_PROP_BT_ALIGN_HIGH:
204 case XTENSA_PROP_BT_ALIGN_REQUIRE:
206 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
208 /* No branch target alignment. */
209 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
210 /* Low priority branch target alignment. */
211 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
212 /* High priority branch target alignment. */
213 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
214 /* Required branch target alignment. */
215 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
217 #define GET_XTENSA_PROP_BT_ALIGN(flag) \
218 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
219 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
220 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
221 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
224 /* Alignment is specified in the block BEFORE the one that needs
225 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
226 get the required alignment specified as a power of 2. Use
227 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
228 alignment. Be careful of side effects since the SET will evaluate
229 flags twice. Also, note that the SIZE of a block in the property
230 table does not include the alignment size, so the alignment fill
231 must be calculated to determine if two blocks are contiguous.
232 TEXT_ALIGN is not currently implemented but is a placeholder for a
233 possible future implementation. */
235 #define XTENSA_PROP_ALIGN 0x00000800
237 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
239 #define GET_XTENSA_PROP_ALIGNMENT(flag) \
240 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
241 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
242 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
243 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
245 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
248 /* Structure for saving instruction and alignment per-fragment data
249 that will be written to the object file. This structure is
250 equivalent to the actual data that will be written out to the file
251 but is easier to use. We provide a conversion to file flags
252 in frag_flags_to_number. */
254 typedef struct frag_flags_struct frag_flags
;
256 struct frag_flags_struct
258 /* is_literal should only be used after xtensa_move_literals.
259 If you need to check if you are generating a literal fragment,
260 then use the generating_literals global. */
262 unsigned is_literal
: 1;
263 unsigned is_insn
: 1;
264 unsigned is_data
: 1;
265 unsigned is_unreachable
: 1;
267 /* is_specific_opcode implies no_transform. */
268 unsigned is_no_transform
: 1;
272 unsigned is_loop_target
: 1;
273 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
274 unsigned bt_align_priority
: 2;
276 unsigned is_no_density
: 1;
277 /* no_longcalls flag does not need to be placed in the object file. */
279 unsigned is_no_reorder
: 1;
281 /* Uses absolute literal addressing for l32r. */
282 unsigned is_abslit
: 1;
284 unsigned is_align
: 1;
285 unsigned alignment
: 5;
289 /* Structure for saving information about a block of property data
290 for frags that have the same flags. */
291 struct xtensa_block_info_struct
297 struct xtensa_block_info_struct
*next
;
301 /* Structure for saving the current state before emitting literals. */
302 typedef struct emit_state_struct
307 int generating_literals
;
311 /* Opcode placement information */
313 typedef unsigned long long bitfield
;
314 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
315 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
316 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
318 #define MAX_FORMATS 32
320 typedef struct op_placement_info_struct
323 /* A number describing how restrictive the issue is for this
324 opcode. For example, an opcode that fits lots of different
325 formats has a high freedom, as does an opcode that fits
326 only one format but many slots in that format. The most
327 restrictive is the opcode that fits only one slot in one
330 xtensa_format narrowest
;
334 /* formats is a bitfield with the Nth bit set
335 if the opcode fits in the Nth xtensa_format. */
338 /* slots[N]'s Mth bit is set if the op fits in the
339 Mth slot of the Nth xtensa_format. */
340 bitfield slots
[MAX_FORMATS
];
342 /* A count of the number of slots in a given format
343 an op can fit (i.e., the bitcount of the slot field above). */
344 char slots_in_format
[MAX_FORMATS
];
346 } op_placement_info
, *op_placement_info_table
;
348 op_placement_info_table op_placement_table
;
351 /* Extra expression types. */
353 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
354 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
355 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
356 #define O_pcrel O_md4 /* value is a PC-relative offset */
357 #define O_tlsfunc O_md5 /* TLS_FUNC/TLSDESC_FN relocation */
358 #define O_tlsarg O_md6 /* TLS_ARG/TLSDESC_ARG relocation */
359 #define O_tlscall O_md7 /* TLS_CALL relocation */
360 #define O_tpoff O_md8 /* TPOFF relocation */
361 #define O_dtpoff O_md9 /* DTPOFF relocation */
363 struct suffix_reloc_map
367 bfd_reloc_code_real_type reloc
;
368 unsigned char operator;
371 #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op }
373 static struct suffix_reloc_map suffix_relocs
[] =
375 SUFFIX_MAP ("l", BFD_RELOC_LO16
, O_lo16
),
376 SUFFIX_MAP ("h", BFD_RELOC_HI16
, O_hi16
),
377 SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT
, O_pltrel
),
378 SUFFIX_MAP ("pcrel", BFD_RELOC_32_PCREL
, O_pcrel
),
379 SUFFIX_MAP ("tlsfunc", BFD_RELOC_XTENSA_TLS_FUNC
, O_tlsfunc
),
380 SUFFIX_MAP ("tlsarg", BFD_RELOC_XTENSA_TLS_ARG
, O_tlsarg
),
381 SUFFIX_MAP ("tlscall", BFD_RELOC_XTENSA_TLS_CALL
, O_tlscall
),
382 SUFFIX_MAP ("tpoff", BFD_RELOC_XTENSA_TLS_TPOFF
, O_tpoff
),
383 SUFFIX_MAP ("dtpoff", BFD_RELOC_XTENSA_TLS_DTPOFF
, O_dtpoff
),
384 { (char *) 0, 0, BFD_RELOC_UNUSED
, 0 }
398 directive_literal_prefix
,
400 directive_absolute_literals
,
401 directive_last_directive
407 bfd_boolean can_be_negated
;
410 const directive_infoS directive_info
[] =
413 { "literal", FALSE
},
415 { "transform", TRUE
},
416 { "freeregs", FALSE
},
417 { "longcalls", TRUE
},
418 { "literal_prefix", FALSE
},
419 { "schedule", TRUE
},
420 { "absolute-literals", TRUE
}
423 bfd_boolean directive_state
[] =
427 #if !XCHAL_HAVE_DENSITY
432 TRUE
, /* transform */
433 FALSE
, /* freeregs */
434 FALSE
, /* longcalls */
435 FALSE
, /* literal_prefix */
436 FALSE
, /* schedule */
437 #if XSHAL_USE_ABSOLUTE_LITERALS
438 TRUE
/* absolute_literals */
440 FALSE
/* absolute_literals */
445 /* Directive functions. */
447 static void xtensa_begin_directive (int);
448 static void xtensa_end_directive (int);
449 static void xtensa_literal_prefix (void);
450 static void xtensa_literal_position (int);
451 static void xtensa_literal_pseudo (int);
452 static void xtensa_frequency_pseudo (int);
453 static void xtensa_elf_cons (int);
454 static void xtensa_leb128 (int);
456 /* Parsing and Idiom Translation. */
458 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
460 /* Various Other Internal Functions. */
462 extern bfd_boolean
xg_is_single_relaxable_insn (TInsn
*, TInsn
*, bfd_boolean
);
463 static bfd_boolean
xg_build_to_insn (TInsn
*, TInsn
*, BuildInstr
*);
464 static void xtensa_mark_literal_pool_location (void);
465 static addressT
get_expanded_loop_offset (xtensa_opcode
);
466 static fragS
*get_literal_pool_location (segT
);
467 static void set_literal_pool_location (segT
, fragS
*);
468 static void xtensa_set_frag_assembly_state (fragS
*);
469 static void finish_vinsn (vliw_insn
*);
470 static bfd_boolean
emit_single_op (TInsn
*);
471 static int total_frag_text_expansion (fragS
*);
473 /* Alignment Functions. */
475 static int get_text_align_power (unsigned);
476 static int get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
477 static int branch_align_power (segT
);
479 /* Helpers for xtensa_relax_frag(). */
481 static long relax_frag_add_nop (fragS
*);
483 /* Accessors for additional per-subsegment information. */
485 static unsigned get_last_insn_flags (segT
, subsegT
);
486 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
487 static float get_subseg_total_freq (segT
, subsegT
);
488 static float get_subseg_target_freq (segT
, subsegT
);
489 static void set_subseg_freq (segT
, subsegT
, float, float);
491 /* Segment list functions. */
493 static void xtensa_move_literals (void);
494 static void xtensa_reorder_segments (void);
495 static void xtensa_switch_to_literal_fragment (emit_state
*);
496 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
497 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
498 static void xtensa_restore_emit_state (emit_state
*);
499 static segT
cache_literal_section (bfd_boolean
);
501 /* Import from elf32-xtensa.c in BFD library. */
503 extern asection
*xtensa_make_property_section (asection
*, const char *);
505 /* op_placement_info functions. */
507 static void init_op_placement_info_table (void);
508 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
509 static int xg_get_single_size (xtensa_opcode
);
510 static xtensa_format
xg_get_single_format (xtensa_opcode
);
511 static int xg_get_single_slot (xtensa_opcode
);
513 /* TInsn and IStack functions. */
515 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
516 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
517 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
518 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
519 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
520 static void tinsn_from_chars (TInsn
*, char *, int);
521 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
522 static int get_num_stack_text_bytes (IStack
*);
523 static int get_num_stack_literal_bytes (IStack
*);
525 /* vliw_insn functions. */
527 static void xg_init_vinsn (vliw_insn
*);
528 static void xg_copy_vinsn (vliw_insn
*, vliw_insn
*);
529 static void xg_clear_vinsn (vliw_insn
*);
530 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
531 static void xg_free_vinsn (vliw_insn
*);
532 static bfd_boolean vinsn_to_insnbuf
533 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
534 static void vinsn_from_chars (vliw_insn
*, char *);
536 /* Expression Utilities. */
538 bfd_boolean
expr_is_const (const expressionS
*);
539 offsetT
get_expr_const (const expressionS
*);
540 void set_expr_const (expressionS
*, offsetT
);
541 bfd_boolean
expr_is_register (const expressionS
*);
542 offsetT
get_expr_register (const expressionS
*);
543 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
544 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
545 static void copy_expr (expressionS
*, const expressionS
*);
547 /* Section renaming. */
549 static void build_section_rename (const char *);
552 /* ISA imported from bfd. */
553 extern xtensa_isa xtensa_default_isa
;
555 extern int target_big_endian
;
557 static xtensa_opcode xtensa_addi_opcode
;
558 static xtensa_opcode xtensa_addmi_opcode
;
559 static xtensa_opcode xtensa_call0_opcode
;
560 static xtensa_opcode xtensa_call4_opcode
;
561 static xtensa_opcode xtensa_call8_opcode
;
562 static xtensa_opcode xtensa_call12_opcode
;
563 static xtensa_opcode xtensa_callx0_opcode
;
564 static xtensa_opcode xtensa_callx4_opcode
;
565 static xtensa_opcode xtensa_callx8_opcode
;
566 static xtensa_opcode xtensa_callx12_opcode
;
567 static xtensa_opcode xtensa_const16_opcode
;
568 static xtensa_opcode xtensa_entry_opcode
;
569 static xtensa_opcode xtensa_extui_opcode
;
570 static xtensa_opcode xtensa_movi_opcode
;
571 static xtensa_opcode xtensa_movi_n_opcode
;
572 static xtensa_opcode xtensa_isync_opcode
;
573 static xtensa_opcode xtensa_j_opcode
;
574 static xtensa_opcode xtensa_jx_opcode
;
575 static xtensa_opcode xtensa_l32r_opcode
;
576 static xtensa_opcode xtensa_loop_opcode
;
577 static xtensa_opcode xtensa_loopnez_opcode
;
578 static xtensa_opcode xtensa_loopgtz_opcode
;
579 static xtensa_opcode xtensa_nop_opcode
;
580 static xtensa_opcode xtensa_nop_n_opcode
;
581 static xtensa_opcode xtensa_or_opcode
;
582 static xtensa_opcode xtensa_ret_opcode
;
583 static xtensa_opcode xtensa_ret_n_opcode
;
584 static xtensa_opcode xtensa_retw_opcode
;
585 static xtensa_opcode xtensa_retw_n_opcode
;
586 static xtensa_opcode xtensa_rsr_lcount_opcode
;
587 static xtensa_opcode xtensa_waiti_opcode
;
588 static int config_max_slots
= 0;
591 /* Command-line Options. */
593 bfd_boolean use_literal_section
= TRUE
;
594 enum flix_level produce_flix
= FLIX_ALL
;
595 static bfd_boolean align_targets
= TRUE
;
596 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
597 static bfd_boolean has_a0_b_retw
= FALSE
;
598 static bfd_boolean workaround_a0_b_retw
= FALSE
;
599 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
600 static bfd_boolean workaround_short_loop
= FALSE
;
601 static bfd_boolean maybe_has_short_loop
= FALSE
;
602 static bfd_boolean workaround_close_loop_end
= FALSE
;
603 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
604 static bfd_boolean enforce_three_byte_loop_align
= FALSE
;
606 /* When workaround_short_loops is TRUE, all loops with early exits must
607 have at least 3 instructions. workaround_all_short_loops is a modifier
608 to the workaround_short_loop flag. In addition to the
609 workaround_short_loop actions, all straightline loopgtz and loopnez
610 must have at least 3 instructions. */
612 static bfd_boolean workaround_all_short_loops
= FALSE
;
616 xtensa_setup_hw_workarounds (int earliest
, int latest
)
618 if (earliest
> latest
)
619 as_fatal (_("illegal range of target hardware versions"));
621 /* Enable all workarounds for pre-T1050.0 hardware. */
622 if (earliest
< 105000 || latest
< 105000)
624 workaround_a0_b_retw
|= TRUE
;
625 workaround_b_j_loop_end
|= TRUE
;
626 workaround_short_loop
|= TRUE
;
627 workaround_close_loop_end
|= TRUE
;
628 workaround_all_short_loops
|= TRUE
;
629 enforce_three_byte_loop_align
= TRUE
;
636 option_density
= OPTION_MD_BASE
,
640 option_no_generate_flix
,
647 option_no_link_relax
,
655 option_text_section_literals
,
656 option_no_text_section_literals
,
658 option_absolute_literals
,
659 option_no_absolute_literals
,
661 option_align_targets
,
662 option_no_align_targets
,
664 option_warn_unaligned_targets
,
669 option_workaround_a0_b_retw
,
670 option_no_workaround_a0_b_retw
,
672 option_workaround_b_j_loop_end
,
673 option_no_workaround_b_j_loop_end
,
675 option_workaround_short_loop
,
676 option_no_workaround_short_loop
,
678 option_workaround_all_short_loops
,
679 option_no_workaround_all_short_loops
,
681 option_workaround_close_loop_end
,
682 option_no_workaround_close_loop_end
,
684 option_no_workarounds
,
686 option_rename_section_name
,
689 option_prefer_const16
,
691 option_target_hardware
694 const char *md_shortopts
= "";
696 struct option md_longopts
[] =
698 { "density", no_argument
, NULL
, option_density
},
699 { "no-density", no_argument
, NULL
, option_no_density
},
701 { "flix", no_argument
, NULL
, option_flix
},
702 { "no-generate-flix", no_argument
, NULL
, option_no_generate_flix
},
703 { "no-allow-flix", no_argument
, NULL
, option_no_flix
},
705 /* Both "relax" and "generics" are deprecated and treated as equivalent
706 to the "transform" option. */
707 { "relax", no_argument
, NULL
, option_relax
},
708 { "no-relax", no_argument
, NULL
, option_no_relax
},
709 { "generics", no_argument
, NULL
, option_generics
},
710 { "no-generics", no_argument
, NULL
, option_no_generics
},
712 { "transform", no_argument
, NULL
, option_transform
},
713 { "no-transform", no_argument
, NULL
, option_no_transform
},
714 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
715 { "no-text-section-literals", no_argument
, NULL
,
716 option_no_text_section_literals
},
717 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
718 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
719 /* This option was changed from -align-target to -target-align
720 because it conflicted with the "-al" option. */
721 { "target-align", no_argument
, NULL
, option_align_targets
},
722 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
723 { "warn-unaligned-targets", no_argument
, NULL
,
724 option_warn_unaligned_targets
},
725 { "longcalls", no_argument
, NULL
, option_longcalls
},
726 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
728 { "no-workaround-a0-b-retw", no_argument
, NULL
,
729 option_no_workaround_a0_b_retw
},
730 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
732 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
733 option_no_workaround_b_j_loop_end
},
734 { "workaround-b-j-loop-end", no_argument
, NULL
,
735 option_workaround_b_j_loop_end
},
737 { "no-workaround-short-loops", no_argument
, NULL
,
738 option_no_workaround_short_loop
},
739 { "workaround-short-loops", no_argument
, NULL
,
740 option_workaround_short_loop
},
742 { "no-workaround-all-short-loops", no_argument
, NULL
,
743 option_no_workaround_all_short_loops
},
744 { "workaround-all-short-loop", no_argument
, NULL
,
745 option_workaround_all_short_loops
},
747 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
748 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
750 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
752 { "no-workaround-close-loop-end", no_argument
, NULL
,
753 option_no_workaround_close_loop_end
},
754 { "workaround-close-loop-end", no_argument
, NULL
,
755 option_workaround_close_loop_end
},
757 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
759 { "link-relax", no_argument
, NULL
, option_link_relax
},
760 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
762 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
764 { NULL
, no_argument
, NULL
, 0 }
767 size_t md_longopts_size
= sizeof md_longopts
;
771 md_parse_option (int c
, char *arg
)
776 as_warn (_("--density option is ignored"));
778 case option_no_density
:
779 as_warn (_("--no-density option is ignored"));
781 case option_link_relax
:
784 case option_no_link_relax
:
788 produce_flix
= FLIX_ALL
;
790 case option_no_generate_flix
:
791 produce_flix
= FLIX_NO_GENERATE
;
794 produce_flix
= FLIX_NONE
;
796 case option_generics
:
797 as_warn (_("--generics is deprecated; use --transform instead"));
798 return md_parse_option (option_transform
, arg
);
799 case option_no_generics
:
800 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
801 return md_parse_option (option_no_transform
, arg
);
803 as_warn (_("--relax is deprecated; use --transform instead"));
804 return md_parse_option (option_transform
, arg
);
805 case option_no_relax
:
806 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
807 return md_parse_option (option_no_transform
, arg
);
808 case option_longcalls
:
809 directive_state
[directive_longcalls
] = TRUE
;
811 case option_no_longcalls
:
812 directive_state
[directive_longcalls
] = FALSE
;
814 case option_text_section_literals
:
815 use_literal_section
= FALSE
;
817 case option_no_text_section_literals
:
818 use_literal_section
= TRUE
;
820 case option_absolute_literals
:
821 if (!absolute_literals_supported
)
823 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
826 directive_state
[directive_absolute_literals
] = TRUE
;
828 case option_no_absolute_literals
:
829 directive_state
[directive_absolute_literals
] = FALSE
;
832 case option_workaround_a0_b_retw
:
833 workaround_a0_b_retw
= TRUE
;
835 case option_no_workaround_a0_b_retw
:
836 workaround_a0_b_retw
= FALSE
;
838 case option_workaround_b_j_loop_end
:
839 workaround_b_j_loop_end
= TRUE
;
841 case option_no_workaround_b_j_loop_end
:
842 workaround_b_j_loop_end
= FALSE
;
845 case option_workaround_short_loop
:
846 workaround_short_loop
= TRUE
;
848 case option_no_workaround_short_loop
:
849 workaround_short_loop
= FALSE
;
852 case option_workaround_all_short_loops
:
853 workaround_all_short_loops
= TRUE
;
855 case option_no_workaround_all_short_loops
:
856 workaround_all_short_loops
= FALSE
;
859 case option_workaround_close_loop_end
:
860 workaround_close_loop_end
= TRUE
;
862 case option_no_workaround_close_loop_end
:
863 workaround_close_loop_end
= FALSE
;
866 case option_no_workarounds
:
867 workaround_a0_b_retw
= FALSE
;
868 workaround_b_j_loop_end
= FALSE
;
869 workaround_short_loop
= FALSE
;
870 workaround_all_short_loops
= FALSE
;
871 workaround_close_loop_end
= FALSE
;
874 case option_align_targets
:
875 align_targets
= TRUE
;
877 case option_no_align_targets
:
878 align_targets
= FALSE
;
881 case option_warn_unaligned_targets
:
882 warn_unaligned_branch_targets
= TRUE
;
885 case option_rename_section_name
:
886 build_section_rename (arg
);
890 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
891 should be emitted or not. FIXME: Not implemented. */
894 case option_prefer_l32r
:
896 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
900 case option_prefer_const16
:
902 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
906 case option_target_hardware
:
908 int earliest
, latest
= 0;
909 if (*arg
== 0 || *arg
== '-')
910 as_fatal (_("invalid target hardware version"));
912 earliest
= strtol (arg
, &arg
, 0);
916 else if (*arg
== '-')
919 as_fatal (_("invalid target hardware version"));
920 latest
= strtol (arg
, &arg
, 0);
923 as_fatal (_("invalid target hardware version"));
925 xtensa_setup_hw_workarounds (earliest
, latest
);
929 case option_transform
:
930 /* This option has no affect other than to use the defaults,
931 which are already set. */
934 case option_no_transform
:
935 /* This option turns off all transformations of any kind.
936 However, because we want to preserve the state of other
937 directives, we only change its own field. Thus, before
938 you perform any transformation, always check if transform
939 is available. If you use the functions we provide for this
940 purpose, you will be ok. */
941 directive_state
[directive_transform
] = FALSE
;
951 md_show_usage (FILE *stream
)
955 --[no-]text-section-literals\n\
956 [Do not] put literals in the text section\n\
957 --[no-]absolute-literals\n\
958 [Do not] default to use non-PC-relative literals\n\
959 --[no-]target-align [Do not] try to align branch targets\n\
960 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
961 --[no-]transform [Do not] transform instructions\n\
962 --flix both allow hand-written and generate flix bundles\n\
963 --no-generate-flix allow hand-written but do not generate\n\
965 --no-allow-flix neither allow hand-written nor generate\n\
967 --rename-section old=new Rename section 'old' to 'new'\n", stream
);
971 /* Functions related to the list of current label symbols. */
974 xtensa_add_insn_label (symbolS
*sym
)
978 if (!free_insn_labels
)
979 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
982 l
= free_insn_labels
;
983 free_insn_labels
= l
->next
;
987 l
->next
= insn_labels
;
993 xtensa_clear_insn_labels (void)
997 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1005 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
)
1009 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
1011 symbolS
*lit_sym
= lit
->sym
;
1012 S_SET_VALUE (lit_sym
, new_offset
);
1013 symbol_set_frag (lit_sym
, new_frag
);
1018 /* Directive data and functions. */
1020 typedef struct state_stackS_struct
1022 directiveE directive
;
1023 bfd_boolean negated
;
1024 bfd_boolean old_state
;
1028 struct state_stackS_struct
*prev
;
1031 state_stackS
*directive_state_stack
;
1033 const pseudo_typeS md_pseudo_table
[] =
1035 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
1036 { "literal_position", xtensa_literal_position
, 0 },
1037 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
1038 { "long", xtensa_elf_cons
, 4 },
1039 { "word", xtensa_elf_cons
, 4 },
1040 { "4byte", xtensa_elf_cons
, 4 },
1041 { "short", xtensa_elf_cons
, 2 },
1042 { "2byte", xtensa_elf_cons
, 2 },
1043 { "sleb128", xtensa_leb128
, 1},
1044 { "uleb128", xtensa_leb128
, 0},
1045 { "begin", xtensa_begin_directive
, 0 },
1046 { "end", xtensa_end_directive
, 0 },
1047 { "literal", xtensa_literal_pseudo
, 0 },
1048 { "frequency", xtensa_frequency_pseudo
, 0 },
1054 use_transform (void)
1056 /* After md_end, you should be checking frag by frag, rather
1057 than state directives. */
1058 gas_assert (!past_xtensa_end
);
1059 return directive_state
[directive_transform
];
1064 do_align_targets (void)
1066 /* Do not use this function after md_end; just look at align_targets
1067 instead. There is no target-align directive, so alignment is either
1068 enabled for all frags or not done at all. */
1069 gas_assert (!past_xtensa_end
);
1070 return align_targets
&& use_transform ();
1075 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1079 state_stackS
*stack
= (state_stackS
*) xmalloc (sizeof (state_stackS
));
1081 as_where (&file
, &line
);
1083 stack
->directive
= directive
;
1084 stack
->negated
= negated
;
1085 stack
->old_state
= directive_state
[directive
];
1088 stack
->datum
= datum
;
1089 stack
->prev
= directive_state_stack
;
1090 directive_state_stack
= stack
;
1092 directive_state
[directive
] = !negated
;
1097 directive_pop (directiveE
*directive
,
1098 bfd_boolean
*negated
,
1103 state_stackS
*top
= directive_state_stack
;
1105 if (!directive_state_stack
)
1107 as_bad (_("unmatched end directive"));
1108 *directive
= directive_none
;
1112 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1113 *directive
= top
->directive
;
1114 *negated
= top
->negated
;
1117 *datum
= top
->datum
;
1118 directive_state_stack
= top
->prev
;
1124 directive_balance (void)
1126 while (directive_state_stack
)
1128 directiveE directive
;
1129 bfd_boolean negated
;
1134 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1135 as_warn_where ((char *) file
, line
,
1136 _(".begin directive with no matching .end directive"));
1142 inside_directive (directiveE dir
)
1144 state_stackS
*top
= directive_state_stack
;
1146 while (top
&& top
->directive
!= dir
)
1149 return (top
!= NULL
);
1154 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1158 char *directive_string
;
1160 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1165 input_line_pointer
+= 3;
1168 len
= strspn (input_line_pointer
,
1169 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1171 /* This code is a hack to make .begin [no-][generics|relax] exactly
1172 equivalent to .begin [no-]transform. We should remove it when
1173 we stop accepting those options. */
1175 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1177 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1178 directive_string
= "transform";
1180 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1182 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1183 directive_string
= "transform";
1186 directive_string
= input_line_pointer
;
1188 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1190 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1192 input_line_pointer
+= len
;
1193 *directive
= (directiveE
) i
;
1194 if (*negated
&& !directive_info
[i
].can_be_negated
)
1195 as_bad (_("directive %s cannot be negated"),
1196 directive_info
[i
].name
);
1201 as_bad (_("unknown directive"));
1202 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1207 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1209 directiveE directive
;
1210 bfd_boolean negated
;
1214 get_directive (&directive
, &negated
);
1215 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1217 discard_rest_of_line ();
1221 if (cur_vinsn
.inside_bundle
)
1222 as_bad (_("directives are not valid inside bundles"));
1226 case directive_literal
:
1227 if (!inside_directive (directive_literal
))
1229 /* Previous labels go with whatever follows this directive, not with
1230 the literal, so save them now. */
1231 saved_insn_labels
= insn_labels
;
1234 as_warn (_(".begin literal is deprecated; use .literal instead"));
1235 state
= (emit_state
*) xmalloc (sizeof (emit_state
));
1236 xtensa_switch_to_literal_fragment (state
);
1237 directive_push (directive_literal
, negated
, state
);
1240 case directive_literal_prefix
:
1241 /* Have to flush pending output because a movi relaxed to an l32r
1242 might produce a literal. */
1243 md_flush_pending_output ();
1244 /* Check to see if the current fragment is a literal
1245 fragment. If it is, then this operation is not allowed. */
1246 if (generating_literals
)
1248 as_bad (_("cannot set literal_prefix inside literal fragment"));
1252 /* Allocate the literal state for this section and push
1253 onto the directive stack. */
1254 ls
= xmalloc (sizeof (lit_state
));
1257 *ls
= default_lit_sections
;
1258 directive_push (directive_literal_prefix
, negated
, ls
);
1260 /* Process the new prefix. */
1261 xtensa_literal_prefix ();
1264 case directive_freeregs
:
1265 /* This information is currently unused, but we'll accept the statement
1266 and just discard the rest of the line. This won't check the syntax,
1267 but it will accept every correct freeregs directive. */
1268 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1269 directive_push (directive_freeregs
, negated
, 0);
1272 case directive_schedule
:
1273 md_flush_pending_output ();
1274 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1275 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1276 directive_push (directive_schedule
, negated
, 0);
1277 xtensa_set_frag_assembly_state (frag_now
);
1280 case directive_density
:
1281 as_warn (_(".begin [no-]density is ignored"));
1284 case directive_absolute_literals
:
1285 md_flush_pending_output ();
1286 if (!absolute_literals_supported
&& !negated
)
1288 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1291 xtensa_set_frag_assembly_state (frag_now
);
1292 directive_push (directive
, negated
, 0);
1296 md_flush_pending_output ();
1297 xtensa_set_frag_assembly_state (frag_now
);
1298 directive_push (directive
, negated
, 0);
1302 demand_empty_rest_of_line ();
1307 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1309 directiveE begin_directive
, end_directive
;
1310 bfd_boolean begin_negated
, end_negated
;
1314 emit_state
**state_ptr
;
1317 if (cur_vinsn
.inside_bundle
)
1318 as_bad (_("directives are not valid inside bundles"));
1320 get_directive (&end_directive
, &end_negated
);
1322 md_flush_pending_output ();
1324 switch (end_directive
)
1326 case (directiveE
) XTENSA_UNDEFINED
:
1327 discard_rest_of_line ();
1330 case directive_density
:
1331 as_warn (_(".end [no-]density is ignored"));
1332 demand_empty_rest_of_line ();
1335 case directive_absolute_literals
:
1336 if (!absolute_literals_supported
&& !end_negated
)
1338 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1339 demand_empty_rest_of_line ();
1348 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1349 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1350 (const void **) state_ptr
);
1352 if (begin_directive
!= directive_none
)
1354 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1356 as_bad (_("does not match begin %s%s at %s:%d"),
1357 begin_negated
? "no-" : "",
1358 directive_info
[begin_directive
].name
, file
, line
);
1362 switch (end_directive
)
1364 case directive_literal
:
1365 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1366 xtensa_restore_emit_state (state
);
1367 xtensa_set_frag_assembly_state (frag_now
);
1369 if (!inside_directive (directive_literal
))
1371 /* Restore the list of current labels. */
1372 xtensa_clear_insn_labels ();
1373 insn_labels
= saved_insn_labels
;
1377 case directive_literal_prefix
:
1378 /* Restore the default collection sections from saved state. */
1379 s
= (lit_state
*) state
;
1381 default_lit_sections
= *s
;
1383 /* Free the state storage. */
1384 free (s
->lit_prefix
);
1388 case directive_schedule
:
1389 case directive_freeregs
:
1393 xtensa_set_frag_assembly_state (frag_now
);
1399 demand_empty_rest_of_line ();
1403 /* Place an aligned literal fragment at the current location. */
1406 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1408 md_flush_pending_output ();
1410 if (inside_directive (directive_literal
))
1411 as_warn (_(".literal_position inside literal directive; ignoring"));
1412 xtensa_mark_literal_pool_location ();
1414 demand_empty_rest_of_line ();
1415 xtensa_clear_insn_labels ();
1419 /* Support .literal label, expr, ... */
1422 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1425 char *p
, *base_name
;
1429 if (inside_directive (directive_literal
))
1431 as_bad (_(".literal not allowed inside .begin literal region"));
1432 ignore_rest_of_line ();
1436 md_flush_pending_output ();
1438 /* Previous labels go with whatever follows this directive, not with
1439 the literal, so save them now. */
1440 saved_insn_labels
= insn_labels
;
1443 /* If we are using text-section literals, then this is the right value... */
1446 base_name
= input_line_pointer
;
1448 xtensa_switch_to_literal_fragment (&state
);
1450 /* ...but if we aren't using text-section-literals, then we
1451 need to put them in the section we just switched to. */
1452 if (use_literal_section
|| directive_state
[directive_absolute_literals
])
1455 /* All literals are aligned to four-byte boundaries. */
1456 frag_align (2, 0, 0);
1457 record_alignment (now_seg
, 2);
1459 c
= get_symbol_end ();
1460 /* Just after name is now '\0'. */
1461 p
= input_line_pointer
;
1465 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1467 as_bad (_("expected comma or colon after symbol name; "
1468 "rest of line ignored"));
1469 ignore_rest_of_line ();
1470 xtensa_restore_emit_state (&state
);
1478 input_line_pointer
++; /* skip ',' or ':' */
1480 xtensa_elf_cons (4);
1482 xtensa_restore_emit_state (&state
);
1484 /* Restore the list of current labels. */
1485 xtensa_clear_insn_labels ();
1486 insn_labels
= saved_insn_labels
;
1491 xtensa_literal_prefix (void)
1496 /* Parse the new prefix from the input_line_pointer. */
1498 len
= strspn (input_line_pointer
,
1499 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1500 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1502 /* Get a null-terminated copy of the name. */
1503 name
= xmalloc (len
+ 1);
1505 strncpy (name
, input_line_pointer
, len
);
1508 /* Skip the name in the input line. */
1509 input_line_pointer
+= len
;
1511 default_lit_sections
.lit_prefix
= name
;
1513 /* Clear cached literal sections, since the prefix has changed. */
1514 default_lit_sections
.lit_seg
= NULL
;
1515 default_lit_sections
.lit4_seg
= NULL
;
1519 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1522 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1524 float fall_through_f
, target_f
;
1526 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1527 if (fall_through_f
< 0)
1529 as_bad (_("fall through frequency must be greater than 0"));
1530 ignore_rest_of_line ();
1534 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1537 as_bad (_("branch target frequency must be greater than 0"));
1538 ignore_rest_of_line ();
1542 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1544 demand_empty_rest_of_line ();
1548 /* Like normal .long/.short/.word, except support @plt, etc.
1549 Clobbers input_line_pointer, checks end-of-line. */
1552 xtensa_elf_cons (int nbytes
)
1555 bfd_reloc_code_real_type reloc
;
1557 md_flush_pending_output ();
1559 if (cur_vinsn
.inside_bundle
)
1560 as_bad (_("directives are not valid inside bundles"));
1562 if (is_it_end_of_statement ())
1564 demand_empty_rest_of_line ();
1571 if (exp
.X_op
== O_symbol
1572 && *input_line_pointer
== '@'
1573 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1576 reloc_howto_type
*reloc_howto
=
1577 bfd_reloc_type_lookup (stdoutput
, reloc
);
1579 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1580 as_bad (_("unsupported relocation"));
1581 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1582 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1583 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1584 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1585 as_bad (_("opcode-specific %s relocation used outside "
1586 "an instruction"), reloc_howto
->name
);
1587 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1588 as_bad (_("%s relocations do not fit in %d bytes"),
1589 reloc_howto
->name
, nbytes
);
1590 else if (reloc
== BFD_RELOC_XTENSA_TLS_FUNC
1591 || reloc
== BFD_RELOC_XTENSA_TLS_ARG
1592 || reloc
== BFD_RELOC_XTENSA_TLS_CALL
)
1593 as_bad (_("invalid use of %s relocation"), reloc_howto
->name
);
1596 char *p
= frag_more ((int) nbytes
);
1597 xtensa_set_frag_assembly_state (frag_now
);
1598 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1599 nbytes
, &exp
, reloc_howto
->pc_relative
, reloc
);
1604 xtensa_set_frag_assembly_state (frag_now
);
1605 emit_expr (&exp
, (unsigned int) nbytes
);
1608 while (*input_line_pointer
++ == ',');
1610 input_line_pointer
--; /* Put terminator back into stream. */
1611 demand_empty_rest_of_line ();
1614 static bfd_boolean is_leb128_expr
;
1617 xtensa_leb128 (int sign
)
1619 is_leb128_expr
= TRUE
;
1621 is_leb128_expr
= FALSE
;
1625 /* Parsing and Idiom Translation. */
1627 /* Parse @plt, etc. and return the desired relocation. */
1628 static bfd_reloc_code_real_type
1629 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1636 struct suffix_reloc_map
*ptr
;
1639 return BFD_RELOC_NONE
;
1641 for (ch
= *str
, str2
= ident
;
1642 (str2
< ident
+ sizeof (ident
) - 1
1643 && (ISALNUM (ch
) || ch
== '@'));
1646 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1653 for (ptr
= &suffix_relocs
[0]; ptr
->length
> 0; ptr
++)
1654 if (ch
== ptr
->suffix
[0]
1655 && len
== ptr
->length
1656 && memcmp (ident
, ptr
->suffix
, ptr
->length
) == 0)
1658 /* Now check for "identifier@suffix+constant". */
1659 if (*str
== '-' || *str
== '+')
1661 char *orig_line
= input_line_pointer
;
1662 expressionS new_exp
;
1664 input_line_pointer
= str
;
1665 expression (&new_exp
);
1666 if (new_exp
.X_op
== O_constant
)
1668 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1669 str
= input_line_pointer
;
1672 if (&input_line_pointer
!= str_p
)
1673 input_line_pointer
= orig_line
;
1680 return BFD_RELOC_UNUSED
;
1684 /* Find the matching operator type. */
1685 static unsigned char
1686 map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc
)
1688 struct suffix_reloc_map
*sfx
;
1689 unsigned char operator = (unsigned char) -1;
1691 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1693 if (sfx
->reloc
== reloc
)
1695 operator = sfx
->operator;
1699 gas_assert (operator != (unsigned char) -1);
1704 /* Find the matching reloc type. */
1705 static bfd_reloc_code_real_type
1706 map_operator_to_reloc (unsigned char operator, bfd_boolean is_literal
)
1708 struct suffix_reloc_map
*sfx
;
1709 bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
1711 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1713 if (sfx
->operator == operator)
1722 if (reloc
== BFD_RELOC_XTENSA_TLS_FUNC
)
1723 return BFD_RELOC_XTENSA_TLSDESC_FN
;
1724 else if (reloc
== BFD_RELOC_XTENSA_TLS_ARG
)
1725 return BFD_RELOC_XTENSA_TLSDESC_ARG
;
1728 if (reloc
== BFD_RELOC_UNUSED
)
1729 return BFD_RELOC_32
;
1736 expression_end (const char *name
)
1759 #define ERROR_REG_NUM ((unsigned) -1)
1762 tc_get_register (const char *prefix
)
1765 const char *next_expr
;
1766 const char *old_line_pointer
;
1769 old_line_pointer
= input_line_pointer
;
1771 if (*input_line_pointer
== '$')
1772 ++input_line_pointer
;
1774 /* Accept "sp" as a synonym for "a1". */
1775 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1776 && expression_end (input_line_pointer
+ 2))
1778 input_line_pointer
+= 2;
1779 return 1; /* AR[1] */
1782 while (*input_line_pointer
++ == *prefix
++)
1784 --input_line_pointer
;
1789 as_bad (_("bad register name: %s"), old_line_pointer
);
1790 return ERROR_REG_NUM
;
1793 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1795 as_bad (_("bad register number: %s"), input_line_pointer
);
1796 return ERROR_REG_NUM
;
1801 while (ISDIGIT ((int) *input_line_pointer
))
1802 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1804 if (!(next_expr
= expression_end (input_line_pointer
)))
1806 as_bad (_("bad register name: %s"), old_line_pointer
);
1807 return ERROR_REG_NUM
;
1810 input_line_pointer
= (char *) next_expr
;
1817 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1819 xtensa_isa isa
= xtensa_default_isa
;
1821 /* Check if this is an immediate operand. */
1822 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1824 bfd_reloc_code_real_type reloc
;
1825 segT t
= expression (tok
);
1827 if (t
== absolute_section
1828 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1830 gas_assert (tok
->X_op
== O_constant
);
1831 tok
->X_op
= O_symbol
;
1832 tok
->X_add_symbol
= &abs_symbol
;
1835 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1836 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1841 case BFD_RELOC_LO16
:
1842 if (tok
->X_op
== O_constant
)
1844 tok
->X_add_number
&= 0xffff;
1848 case BFD_RELOC_HI16
:
1849 if (tok
->X_op
== O_constant
)
1851 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1855 case BFD_RELOC_UNUSED
:
1856 as_bad (_("unsupported relocation"));
1858 case BFD_RELOC_32_PCREL
:
1859 as_bad (_("pcrel relocation not allowed in an instruction"));
1864 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
1869 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1870 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1872 if (reg
!= ERROR_REG_NUM
) /* Already errored */
1875 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
1876 as_bad (_("register number out of range"));
1879 tok
->X_op
= O_register
;
1880 tok
->X_add_symbol
= 0;
1881 tok
->X_add_number
= reg
;
1886 /* Split up the arguments for an opcode or pseudo-op. */
1889 tokenize_arguments (char **args
, char *str
)
1891 char *old_input_line_pointer
;
1892 bfd_boolean saw_comma
= FALSE
;
1893 bfd_boolean saw_arg
= FALSE
;
1894 bfd_boolean saw_colon
= FALSE
;
1896 char *arg_end
, *arg
;
1899 /* Save and restore input_line_pointer around this function. */
1900 old_input_line_pointer
= input_line_pointer
;
1901 input_line_pointer
= str
;
1903 while (*input_line_pointer
)
1906 switch (*input_line_pointer
)
1913 input_line_pointer
++;
1914 if (saw_comma
|| saw_colon
|| !saw_arg
)
1920 input_line_pointer
++;
1921 if (saw_comma
|| saw_colon
|| !saw_arg
)
1927 if (!saw_comma
&& !saw_colon
&& saw_arg
)
1930 arg_end
= input_line_pointer
+ 1;
1931 while (!expression_end (arg_end
))
1934 arg_len
= arg_end
- input_line_pointer
;
1935 arg
= (char *) xmalloc ((saw_colon
? 1 : 0) + arg_len
+ 1);
1936 args
[num_args
] = arg
;
1940 strncpy (arg
, input_line_pointer
, arg_len
);
1941 arg
[arg_len
] = '\0';
1943 input_line_pointer
= arg_end
;
1953 if (saw_comma
|| saw_colon
)
1955 input_line_pointer
= old_input_line_pointer
;
1960 as_bad (_("extra comma"));
1962 as_bad (_("extra colon"));
1964 as_bad (_("missing argument"));
1966 as_bad (_("missing comma or colon"));
1967 input_line_pointer
= old_input_line_pointer
;
1972 /* Parse the arguments to an opcode. Return TRUE on error. */
1975 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
1977 expressionS
*tok
, *last_tok
;
1978 xtensa_opcode opcode
= insn
->opcode
;
1979 bfd_boolean had_error
= TRUE
;
1980 xtensa_isa isa
= xtensa_default_isa
;
1981 int n
, num_regs
= 0;
1982 int opcode_operand_count
;
1983 int opnd_cnt
, last_opnd_cnt
;
1984 unsigned int next_reg
= 0;
1985 char *old_input_line_pointer
;
1987 if (insn
->insn_type
== ITYPE_LITERAL
)
1988 opcode_operand_count
= 1;
1990 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
1993 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
1995 /* Save and restore input_line_pointer around this function. */
1996 old_input_line_pointer
= input_line_pointer
;
2002 /* Skip invisible operands. */
2003 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
2009 for (n
= 0; n
< num_args
; n
++)
2011 input_line_pointer
= arg_strings
[n
];
2012 if (*input_line_pointer
== ':')
2014 xtensa_regfile opnd_rf
;
2015 input_line_pointer
++;
2018 gas_assert (opnd_cnt
> 0);
2020 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
2022 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
2023 as_warn (_("incorrect register number, ignoring"));
2028 if (opnd_cnt
>= opcode_operand_count
)
2030 as_warn (_("too many arguments"));
2033 gas_assert (opnd_cnt
< MAX_INSN_ARGS
);
2035 expression_maybe_register (opcode
, opnd_cnt
, tok
);
2036 next_reg
= tok
->X_add_number
+ 1;
2038 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
2040 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
2042 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
2043 /* minus 1 because we are seeing one right now */
2049 last_opnd_cnt
= opnd_cnt
;
2050 demand_empty_rest_of_line ();
2057 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
2061 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
2064 insn
->ntok
= tok
- insn
->tok
;
2068 input_line_pointer
= old_input_line_pointer
;
2074 get_invisible_operands (TInsn
*insn
)
2076 xtensa_isa isa
= xtensa_default_isa
;
2077 static xtensa_insnbuf slotbuf
= NULL
;
2079 xtensa_opcode opc
= insn
->opcode
;
2080 int slot
, opnd
, fmt_found
;
2084 slotbuf
= xtensa_insnbuf_alloc (isa
);
2086 /* Find format/slot where this can be encoded. */
2089 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2091 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2093 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2099 if (fmt_found
) break;
2104 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2108 /* First encode all the visible operands
2109 (to deal with shared field operands). */
2110 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2112 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2113 && (insn
->tok
[opnd
].X_op
== O_register
2114 || insn
->tok
[opnd
].X_op
== O_constant
))
2116 val
= insn
->tok
[opnd
].X_add_number
;
2117 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2118 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2122 /* Then pull out the values for the invisible ones. */
2123 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2125 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2127 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2128 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2129 insn
->tok
[opnd
].X_add_number
= val
;
2130 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2131 insn
->tok
[opnd
].X_op
= O_register
;
2133 insn
->tok
[opnd
].X_op
= O_constant
;
2142 xg_reverse_shift_count (char **cnt_argp
)
2144 char *cnt_arg
, *new_arg
;
2145 cnt_arg
= *cnt_argp
;
2147 /* replace the argument with "31-(argument)" */
2148 new_arg
= (char *) xmalloc (strlen (cnt_arg
) + 6);
2149 sprintf (new_arg
, "31-(%s)", cnt_arg
);
2152 *cnt_argp
= new_arg
;
2156 /* If "arg" is a constant expression, return non-zero with the value
2160 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2163 char *save_ptr
= input_line_pointer
;
2165 input_line_pointer
= arg
;
2167 input_line_pointer
= save_ptr
;
2169 if (exp
.X_op
== O_constant
)
2171 *valp
= exp
.X_add_number
;
2180 xg_replace_opname (char **popname
, char *newop
)
2183 *popname
= (char *) xmalloc (strlen (newop
) + 1);
2184 strcpy (*popname
, newop
);
2189 xg_check_num_args (int *pnum_args
,
2194 int num_args
= *pnum_args
;
2196 if (num_args
< expected_num
)
2198 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2199 num_args
, opname
, expected_num
);
2203 if (num_args
> expected_num
)
2205 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2206 num_args
, opname
, expected_num
);
2207 while (num_args
-- > expected_num
)
2209 free (arg_strings
[num_args
]);
2210 arg_strings
[num_args
] = 0;
2212 *pnum_args
= expected_num
;
2220 /* If the register is not specified as part of the opcode,
2221 then get it from the operand and move it to the opcode. */
2224 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2226 xtensa_isa isa
= xtensa_default_isa
;
2228 char *opname
, *new_opname
;
2229 const char *sr_name
;
2230 int is_user
, is_write
;
2235 is_user
= (opname
[1] == 'u');
2236 is_write
= (opname
[0] == 'w');
2238 /* Opname == [rw]ur or [rwx]sr... */
2240 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2243 /* Check if the argument is a symbolic register name. */
2244 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2245 /* Handle WSR to "INTSET" as a special case. */
2246 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2247 && !strcasecmp (arg_strings
[1], "intset"))
2248 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2249 if (sr
== XTENSA_UNDEFINED
2250 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2252 /* Maybe it's a register number.... */
2254 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2256 as_bad (_("invalid register '%s' for '%s' instruction"),
2257 arg_strings
[1], opname
);
2260 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2261 if (sr
== XTENSA_UNDEFINED
)
2263 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2264 (long) val
, opname
);
2269 /* Remove the last argument, which is now part of the opcode. */
2270 free (arg_strings
[1]);
2274 /* Translate the opcode. */
2275 sr_name
= xtensa_sysreg_name (isa
, sr
);
2276 /* Another special case for "WSR.INTSET".... */
2277 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2279 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2280 sprintf (new_opname
, "%s.%s", *popname
, sr_name
);
2282 *popname
= new_opname
;
2289 xtensa_translate_old_userreg_ops (char **popname
)
2291 xtensa_isa isa
= xtensa_default_isa
;
2293 char *opname
, *new_opname
;
2294 const char *sr_name
;
2295 bfd_boolean has_underbar
= FALSE
;
2298 if (opname
[0] == '_')
2300 has_underbar
= TRUE
;
2304 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2305 if (sr
!= XTENSA_UNDEFINED
)
2307 /* The new default name ("nnn") is different from the old default
2308 name ("URnnn"). The old default is handled below, and we don't
2309 want to recognize [RW]nnn, so do nothing if the name is the (new)
2311 static char namebuf
[10];
2312 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2313 if (strcmp (namebuf
, opname
+ 1) == 0)
2321 /* Only continue if the reg name is "URnnn". */
2322 if (opname
[1] != 'u' || opname
[2] != 'r')
2324 val
= strtoul (opname
+ 3, &end
, 10);
2328 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2329 if (sr
== XTENSA_UNDEFINED
)
2331 as_bad (_("invalid register number (%ld) for '%s'"),
2332 (long) val
, opname
);
2337 /* Translate the opcode. */
2338 sr_name
= xtensa_sysreg_name (isa
, sr
);
2339 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2340 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2341 opname
[0], sr_name
);
2343 *popname
= new_opname
;
2350 xtensa_translate_zero_immed (char *old_op
,
2360 gas_assert (opname
[0] != '_');
2362 if (strcmp (opname
, old_op
) != 0)
2365 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2367 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2369 xg_replace_opname (popname
, new_op
);
2370 free (arg_strings
[1]);
2371 arg_strings
[1] = arg_strings
[2];
2380 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2381 Returns non-zero if an error was found. */
2384 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2386 char *opname
= *popname
;
2387 bfd_boolean has_underbar
= FALSE
;
2391 has_underbar
= TRUE
;
2395 if (strcmp (opname
, "mov") == 0)
2397 if (use_transform () && !has_underbar
&& density_supported
)
2398 xg_replace_opname (popname
, "mov.n");
2401 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2403 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2404 arg_strings
[2] = (char *) xmalloc (strlen (arg_strings
[1]) + 1);
2405 strcpy (arg_strings
[2], arg_strings
[1]);
2411 if (strcmp (opname
, "bbsi.l") == 0)
2413 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2415 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2416 if (target_big_endian
)
2417 xg_reverse_shift_count (&arg_strings
[1]);
2421 if (strcmp (opname
, "bbci.l") == 0)
2423 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2425 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2426 if (target_big_endian
)
2427 xg_reverse_shift_count (&arg_strings
[1]);
2431 /* Don't do anything special with NOPs inside FLIX instructions. They
2432 are handled elsewhere. Real NOP instructions are always available
2433 in configurations with FLIX, so this should never be an issue but
2434 check for it anyway. */
2435 if (!cur_vinsn
.inside_bundle
&& xtensa_nop_opcode
== XTENSA_UNDEFINED
2436 && strcmp (opname
, "nop") == 0)
2438 if (use_transform () && !has_underbar
&& density_supported
)
2439 xg_replace_opname (popname
, "nop.n");
2442 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2444 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2445 arg_strings
[0] = (char *) xmalloc (3);
2446 arg_strings
[1] = (char *) xmalloc (3);
2447 arg_strings
[2] = (char *) xmalloc (3);
2448 strcpy (arg_strings
[0], "a1");
2449 strcpy (arg_strings
[1], "a1");
2450 strcpy (arg_strings
[2], "a1");
2456 /* Recognize [RW]UR and [RWX]SR. */
2457 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2458 && (opname
[1] == 'u' || opname
[1] == 's'))
2459 || (opname
[0] == 'x' && opname
[1] == 's'))
2461 && opname
[3] == '\0')
2462 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2464 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2465 [RW]<name> if <name> is the non-default name of a user register. */
2466 if ((opname
[0] == 'r' || opname
[0] == 'w')
2467 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2468 return xtensa_translate_old_userreg_ops (popname
);
2470 /* Relax branches that don't allow comparisons against an immediate value
2471 of zero to the corresponding branches with implicit zero immediates. */
2472 if (!has_underbar
&& use_transform ())
2474 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2475 pnum_args
, arg_strings
))
2478 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2479 pnum_args
, arg_strings
))
2482 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2483 pnum_args
, arg_strings
))
2486 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2487 pnum_args
, arg_strings
))
2495 /* Functions for dealing with the Xtensa ISA. */
2497 /* Currently the assembler only allows us to use a single target per
2498 fragment. Because of this, only one operand for a given
2499 instruction may be symbolic. If there is a PC-relative operand,
2500 the last one is chosen. Otherwise, the result is the number of the
2501 last immediate operand, and if there are none of those, we fail and
2505 get_relaxable_immed (xtensa_opcode opcode
)
2507 int last_immed
= -1;
2510 if (opcode
== XTENSA_UNDEFINED
)
2513 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2514 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2516 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2518 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2520 if (last_immed
== -1
2521 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2528 static xtensa_opcode
2529 get_opcode_from_buf (const char *buf
, int slot
)
2531 static xtensa_insnbuf insnbuf
= NULL
;
2532 static xtensa_insnbuf slotbuf
= NULL
;
2533 xtensa_isa isa
= xtensa_default_isa
;
2538 insnbuf
= xtensa_insnbuf_alloc (isa
);
2539 slotbuf
= xtensa_insnbuf_alloc (isa
);
2542 xtensa_insnbuf_from_chars (isa
, insnbuf
, (const unsigned char *) buf
, 0);
2543 fmt
= xtensa_format_decode (isa
, insnbuf
);
2544 if (fmt
== XTENSA_UNDEFINED
)
2545 return XTENSA_UNDEFINED
;
2547 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2548 return XTENSA_UNDEFINED
;
2550 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2551 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2555 #ifdef TENSILICA_DEBUG
2557 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2560 xtensa_print_insn_table (void)
2562 int num_opcodes
, num_operands
;
2563 xtensa_opcode opcode
;
2564 xtensa_isa isa
= xtensa_default_isa
;
2566 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2567 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2570 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2571 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2572 for (opn
= 0; opn
< num_operands
; opn
++)
2574 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2576 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2578 xtensa_regfile opnd_rf
=
2579 xtensa_operand_regfile (isa
, opcode
, opn
);
2580 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2582 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2583 fputs ("[lLr] ", stderr
);
2585 fputs ("i ", stderr
);
2587 fprintf (stderr
, "\n");
2593 print_vliw_insn (xtensa_insnbuf vbuf
)
2595 xtensa_isa isa
= xtensa_default_isa
;
2596 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2597 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2600 fprintf (stderr
, "format = %d\n", f
);
2602 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2604 xtensa_opcode opcode
;
2608 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2609 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2610 opname
= xtensa_opcode_name (isa
, opcode
);
2612 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2613 fprintf (stderr
, " operands = ");
2615 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2619 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2621 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2622 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2623 fprintf (stderr
, "%d ", val
);
2625 fprintf (stderr
, "\n");
2627 xtensa_insnbuf_free (isa
, sbuf
);
2630 #endif /* TENSILICA_DEBUG */
2634 is_direct_call_opcode (xtensa_opcode opcode
)
2636 xtensa_isa isa
= xtensa_default_isa
;
2637 int n
, num_operands
;
2639 if (xtensa_opcode_is_call (isa
, opcode
) != 1)
2642 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2643 for (n
= 0; n
< num_operands
; n
++)
2645 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2646 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2653 /* Convert from BFD relocation type code to slot and operand number.
2654 Returns non-zero on failure. */
2657 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2659 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2660 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2662 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2665 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2666 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2668 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2678 /* Convert from slot number to BFD relocation type code for the
2679 standard PC-relative relocations. Return BFD_RELOC_NONE on
2682 static bfd_reloc_code_real_type
2683 encode_reloc (int slot
)
2685 if (slot
< 0 || slot
> 14)
2686 return BFD_RELOC_NONE
;
2688 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2692 /* Convert from slot numbers to BFD relocation type code for the
2693 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2695 static bfd_reloc_code_real_type
2696 encode_alt_reloc (int slot
)
2698 if (slot
< 0 || slot
> 14)
2699 return BFD_RELOC_NONE
;
2701 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2706 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2709 xtensa_opcode opcode
,
2715 uint32 valbuf
= value
;
2717 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2719 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2721 as_bad_where ((char *) file
, line
,
2722 _("operand %d of '%s' has out of range value '%u'"),
2724 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2727 as_bad_where ((char *) file
, line
,
2728 _("operand %d of '%s' has invalid value '%u'"),
2730 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2735 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2741 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2744 xtensa_opcode opcode
,
2748 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2749 fmt
, slot
, slotbuf
, &val
);
2750 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2755 /* Checks for rules from xtensa-relax tables. */
2757 /* The routine xg_instruction_matches_option_term must return TRUE
2758 when a given option term is true. The meaning of all of the option
2759 terms is given interpretation by this function. */
2762 xg_instruction_matches_option_term (TInsn
*insn
, const ReqOrOption
*option
)
2764 if (strcmp (option
->option_name
, "realnop") == 0
2765 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2767 /* These conditions were evaluated statically when building the
2768 relaxation table. There's no need to reevaluate them now. */
2771 else if (strcmp (option
->option_name
, "FREEREG") == 0)
2772 return insn
->extra_arg
.X_op
== O_register
;
2775 as_fatal (_("internal error: unknown option name '%s'"),
2776 option
->option_name
);
2782 xg_instruction_matches_or_options (TInsn
*insn
,
2783 const ReqOrOptionList
*or_option
)
2785 const ReqOrOption
*option
;
2786 /* Must match each of the AND terms. */
2787 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2789 if (xg_instruction_matches_option_term (insn
, option
))
2797 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2799 const ReqOption
*req_options
;
2800 /* Must match each of the AND terms. */
2801 for (req_options
= options
;
2802 req_options
!= NULL
;
2803 req_options
= req_options
->next
)
2805 /* Must match one of the OR clauses. */
2806 if (!xg_instruction_matches_or_options (insn
,
2807 req_options
->or_option_terms
))
2814 /* Return the transition rule that matches or NULL if none matches. */
2817 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2819 PreconditionList
*condition_l
;
2821 if (rule
->opcode
!= insn
->opcode
)
2824 for (condition_l
= rule
->conditions
;
2825 condition_l
!= NULL
;
2826 condition_l
= condition_l
->next
)
2830 Precondition
*cond
= condition_l
->precond
;
2835 /* The expression must be the constant. */
2836 gas_assert (cond
->op_num
< insn
->ntok
);
2837 exp1
= &insn
->tok
[cond
->op_num
];
2838 if (expr_is_const (exp1
))
2843 if (get_expr_const (exp1
) != cond
->op_data
)
2847 if (get_expr_const (exp1
) == cond
->op_data
)
2854 else if (expr_is_register (exp1
))
2859 if (get_expr_register (exp1
) != cond
->op_data
)
2863 if (get_expr_register (exp1
) == cond
->op_data
)
2875 gas_assert (cond
->op_num
< insn
->ntok
);
2876 gas_assert (cond
->op_data
< insn
->ntok
);
2877 exp1
= &insn
->tok
[cond
->op_num
];
2878 exp2
= &insn
->tok
[cond
->op_data
];
2883 if (!expr_is_equal (exp1
, exp2
))
2887 if (expr_is_equal (exp1
, exp2
))
2899 if (!xg_instruction_matches_options (insn
, rule
->options
))
2907 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
2909 bfd_boolean a_greater
= FALSE
;
2910 bfd_boolean b_greater
= FALSE
;
2912 ReqOptionList
*l_a
= a
->options
;
2913 ReqOptionList
*l_b
= b
->options
;
2915 /* We only care if they both are the same except for
2916 a const16 vs. an l32r. */
2918 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2920 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
2921 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
2922 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2924 if (l_or_a
->is_true
!= l_or_b
->is_true
)
2926 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
2928 /* This is the case we care about. */
2929 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
2930 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
2937 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
2938 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
2948 l_or_a
= l_or_a
->next
;
2949 l_or_b
= l_or_b
->next
;
2951 if (l_or_a
|| l_or_b
)
2960 /* Incomparable if the substitution was used differently in two cases. */
2961 if (a_greater
&& b_greater
)
2973 static TransitionRule
*
2974 xg_instruction_match (TInsn
*insn
)
2976 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
2978 gas_assert (insn
->opcode
< table
->num_opcodes
);
2980 /* Walk through all of the possible transitions. */
2981 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2983 TransitionRule
*rule
= l
->rule
;
2984 if (xg_instruction_matches_rule (insn
, rule
))
2991 /* Various Other Internal Functions. */
2994 is_unique_insn_expansion (TransitionRule
*r
)
2996 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
2998 if (r
->to_instr
->typ
!= INSTR_INSTR
)
3004 /* Check if there is exactly one relaxation for INSN that converts it to
3005 another instruction of equal or larger size. If so, and if TARG is
3006 non-null, go ahead and generate the relaxed instruction into TARG. If
3007 NARROW_ONLY is true, then only consider relaxations that widen a narrow
3008 instruction, i.e., ignore relaxations that convert to an instruction of
3009 equal size. In some contexts where this function is used, only
3010 a single widening is allowed and the NARROW_ONLY argument is used to
3011 exclude cases like ADDI being "widened" to an ADDMI, which may
3012 later be relaxed to an ADDMI/ADDI pair. */
3015 xg_is_single_relaxable_insn (TInsn
*insn
, TInsn
*targ
, bfd_boolean narrow_only
)
3017 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3019 TransitionRule
*match
= 0;
3021 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3022 gas_assert (insn
->opcode
< table
->num_opcodes
);
3024 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3026 TransitionRule
*rule
= l
->rule
;
3028 if (xg_instruction_matches_rule (insn
, rule
)
3029 && is_unique_insn_expansion (rule
)
3030 && (xg_get_single_size (insn
->opcode
) + (narrow_only
? 1 : 0)
3031 <= xg_get_single_size (rule
->to_instr
->opcode
)))
3042 xg_build_to_insn (targ
, insn
, match
->to_instr
);
3047 /* Return the maximum number of bytes this opcode can expand to. */
3050 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
3052 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3054 int max_size
= xg_get_single_size (opcode
);
3056 gas_assert (opcode
< table
->num_opcodes
);
3058 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3060 TransitionRule
*rule
= l
->rule
;
3061 BuildInstr
*build_list
;
3066 build_list
= rule
->to_instr
;
3067 if (is_unique_insn_expansion (rule
))
3069 gas_assert (build_list
->typ
== INSTR_INSTR
);
3070 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
3073 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3075 switch (build_list
->typ
)
3078 this_size
+= xg_get_single_size (build_list
->opcode
);
3080 case INSTR_LITERAL_DEF
:
3081 case INSTR_LABEL_DEF
:
3086 if (this_size
> max_size
)
3087 max_size
= this_size
;
3093 /* Return the maximum number of literal bytes this opcode can generate. */
3096 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3098 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3102 gas_assert (opcode
< table
->num_opcodes
);
3104 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3106 TransitionRule
*rule
= l
->rule
;
3107 BuildInstr
*build_list
;
3112 build_list
= rule
->to_instr
;
3113 if (is_unique_insn_expansion (rule
))
3115 gas_assert (build_list
->typ
== INSTR_INSTR
);
3116 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3119 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3121 switch (build_list
->typ
)
3123 case INSTR_LITERAL_DEF
:
3124 /* Hard-coded 4-byte literal. */
3128 case INSTR_LABEL_DEF
:
3133 if (this_size
> max_size
)
3134 max_size
= this_size
;
3141 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3143 int steps_taken
= 0;
3144 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3147 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3148 gas_assert (insn
->opcode
< table
->num_opcodes
);
3150 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3152 TransitionRule
*rule
= l
->rule
;
3154 if (xg_instruction_matches_rule (insn
, rule
))
3156 if (steps_taken
== lateral_steps
)
3166 get_special_literal_symbol (void)
3168 static symbolS
*sym
= NULL
;
3171 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3177 get_special_label_symbol (void)
3179 static symbolS
*sym
= NULL
;
3182 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3188 xg_valid_literal_expression (const expressionS
*exp
)
3210 /* This will check to see if the value can be converted into the
3211 operand type. It will return TRUE if it does not fit. */
3214 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3216 uint32 valbuf
= value
;
3217 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3223 /* Assumes: All immeds are constants. Check that all constants fit
3224 into their immeds; return FALSE if not. */
3227 xg_immeds_fit (const TInsn
*insn
)
3229 xtensa_isa isa
= xtensa_default_isa
;
3233 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3234 for (i
= 0; i
< n
; ++i
)
3236 const expressionS
*exp
= &insn
->tok
[i
];
3238 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3245 if (xg_check_operand (exp
->X_add_number
, insn
->opcode
, i
))
3250 /* The symbol should have a fixup associated with it. */
3259 /* This should only be called after we have an initial
3260 estimate of the addresses. */
3263 xg_symbolic_immeds_fit (const TInsn
*insn
,
3269 xtensa_isa isa
= xtensa_default_isa
;
3277 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3279 for (i
= 0; i
< n
; ++i
)
3281 const expressionS
*exp
= &insn
->tok
[i
];
3283 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3290 if (xg_check_operand (exp
->X_add_number
, insn
->opcode
, i
))
3296 /* Check for the worst case. */
3297 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3302 /* We only allow symbols for PC-relative references.
3303 If pc_frag == 0, then we don't have frag locations yet. */
3305 || xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0)
3308 /* If it is a weak symbol or a symbol in a different section,
3309 it cannot be known to fit at assembly time. */
3310 if (S_IS_WEAK (exp
->X_add_symbol
)
3311 || S_GET_SEGMENT (exp
->X_add_symbol
) != pc_seg
)
3313 /* For a direct call with --no-longcalls, be optimistic and
3314 assume it will be in range. If the symbol is weak and
3315 undefined, it may remain undefined at link-time, in which
3316 case it will have a zero value and almost certainly be out
3317 of range for a direct call; thus, relax for undefined weak
3318 symbols even if longcalls is not enabled. */
3319 if (is_direct_call_opcode (insn
->opcode
)
3320 && ! pc_frag
->tc_frag_data
.use_longcalls
3321 && (! S_IS_WEAK (exp
->X_add_symbol
)
3322 || S_IS_DEFINED (exp
->X_add_symbol
)))
3328 symbolP
= exp
->X_add_symbol
;
3329 sym_frag
= symbol_get_frag (symbolP
);
3330 target
= S_GET_VALUE (symbolP
) + exp
->X_add_number
;
3331 pc
= pc_frag
->fr_address
+ pc_offset
;
3333 /* If frag has yet to be reached on this pass, assume it
3334 will move by STRETCH just as we did. If this is not so,
3335 it will be because some frag between grows, and that will
3336 force another pass. Beware zero-length frags. There
3337 should be a faster way to do this. */
3340 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3341 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3346 new_offset
= target
;
3347 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3348 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3353 /* The symbol should have a fixup associated with it. */
3362 /* Return TRUE on success. */
3365 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3371 targ
->debug_line
= insn
->debug_line
;
3372 targ
->loc_directive_seen
= insn
->loc_directive_seen
;
3377 targ
->opcode
= bi
->opcode
;
3378 targ
->insn_type
= ITYPE_INSN
;
3379 targ
->is_specific_opcode
= FALSE
;
3381 for (; op
!= NULL
; op
= op
->next
)
3383 int op_num
= op
->op_num
;
3384 int op_data
= op
->op_data
;
3386 gas_assert (op
->op_num
< MAX_INSN_ARGS
);
3388 if (targ
->ntok
<= op_num
)
3389 targ
->ntok
= op_num
+ 1;
3394 set_expr_const (&targ
->tok
[op_num
], op_data
);
3397 gas_assert (op_data
< insn
->ntok
);
3398 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3401 if (insn
->extra_arg
.X_op
!= O_register
)
3403 copy_expr (&targ
->tok
[op_num
], &insn
->extra_arg
);
3406 sym
= get_special_literal_symbol ();
3407 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3408 if (insn
->tok
[op_data
].X_op
== O_tlsfunc
3409 || insn
->tok
[op_data
].X_op
== O_tlsarg
)
3410 copy_expr (&targ
->extra_arg
, &insn
->tok
[op_data
]);
3413 sym
= get_special_label_symbol ();
3414 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3416 case OP_OPERAND_HI16U
:
3417 case OP_OPERAND_LOW16U
:
3418 gas_assert (op_data
< insn
->ntok
);
3419 if (expr_is_const (&insn
->tok
[op_data
]))
3422 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3423 val
= xg_apply_userdef_op_fn (op
->typ
,
3426 targ
->tok
[op_num
].X_add_number
= val
;
3430 /* For const16 we can create relocations for these. */
3431 if (targ
->opcode
== XTENSA_UNDEFINED
3432 || (targ
->opcode
!= xtensa_const16_opcode
))
3434 gas_assert (op_data
< insn
->ntok
);
3435 /* Need to build a O_lo16 or O_hi16. */
3436 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3437 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3439 if (op
->typ
== OP_OPERAND_HI16U
)
3440 targ
->tok
[op_num
].X_op
= O_hi16
;
3441 else if (op
->typ
== OP_OPERAND_LOW16U
)
3442 targ
->tok
[op_num
].X_op
= O_lo16
;
3449 /* currently handles:
3452 OP_OPERAND_F32MINUS */
3453 if (xg_has_userdef_op_fn (op
->typ
))
3455 gas_assert (op_data
< insn
->ntok
);
3456 if (expr_is_const (&insn
->tok
[op_data
]))
3459 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3460 val
= xg_apply_userdef_op_fn (op
->typ
,
3463 targ
->tok
[op_num
].X_add_number
= val
;
3466 return FALSE
; /* We cannot use a relocation for this. */
3475 case INSTR_LITERAL_DEF
:
3477 targ
->opcode
= XTENSA_UNDEFINED
;
3478 targ
->insn_type
= ITYPE_LITERAL
;
3479 targ
->is_specific_opcode
= FALSE
;
3480 for (; op
!= NULL
; op
= op
->next
)
3482 int op_num
= op
->op_num
;
3483 int op_data
= op
->op_data
;
3484 gas_assert (op
->op_num
< MAX_INSN_ARGS
);
3486 if (targ
->ntok
<= op_num
)
3487 targ
->ntok
= op_num
+ 1;
3492 gas_assert (op_data
< insn
->ntok
);
3493 /* We can only pass resolvable literals through. */
3494 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3496 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3508 case INSTR_LABEL_DEF
:
3510 targ
->opcode
= XTENSA_UNDEFINED
;
3511 targ
->insn_type
= ITYPE_LABEL
;
3512 targ
->is_specific_opcode
= FALSE
;
3513 /* Literal with no ops is a label? */
3514 gas_assert (op
== NULL
);
3525 /* Return TRUE on success. */
3528 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3530 for (; bi
!= NULL
; bi
= bi
->next
)
3532 TInsn
*next_insn
= istack_push_space (istack
);
3534 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3541 /* Return TRUE on valid expansion. */
3544 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3546 int stack_size
= istack
->ninsn
;
3547 int steps_taken
= 0;
3548 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3551 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3552 gas_assert (insn
->opcode
< table
->num_opcodes
);
3554 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3556 TransitionRule
*rule
= l
->rule
;
3558 if (xg_instruction_matches_rule (insn
, rule
))
3560 if (lateral_steps
== steps_taken
)
3564 /* This is it. Expand the rule to the stack. */
3565 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3568 /* Check to see if it fits. */
3569 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3571 TInsn
*tinsn
= &istack
->insn
[i
];
3573 if (tinsn
->insn_type
== ITYPE_INSN
3574 && !tinsn_has_symbolic_operands (tinsn
)
3575 && !xg_immeds_fit (tinsn
))
3577 istack
->ninsn
= stack_size
;
3590 /* Relax the assembly instruction at least "min_steps".
3591 Return the number of steps taken.
3593 For relaxation to correctly terminate, every relaxation chain must
3594 terminate in one of two ways:
3596 1. If the chain from one instruction to the next consists entirely of
3597 single instructions, then the chain *must* handle all possible
3598 immediates without failing. It must not ever fail because an
3599 immediate is out of range. The MOVI.N -> MOVI -> L32R relaxation
3600 chain is one example. L32R loads 32 bits, and there cannot be an
3601 immediate larger than 32 bits, so it satisfies this condition.
3602 Single instruction relaxation chains are as defined by
3603 xg_is_single_relaxable_instruction.
3605 2. Otherwise, the chain must end in a multi-instruction expansion: e.g.,
3606 BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J
3608 Strictly speaking, in most cases you can violate condition 1 and be OK
3609 -- in particular when the last two instructions have the same single
3610 size. But nevertheless, you should guarantee the above two conditions.
3612 We could fix this so that single-instruction expansions correctly
3613 terminate when they can't handle the range, but the error messages are
3614 worse, and it actually turns out that in every case but one (18-bit wide
3615 branches), you need a multi-instruction expansion to get the full range
3616 anyway. And because 18-bit branches are handled identically to 15-bit
3617 branches, there isn't any point in changing it. */
3620 xg_assembly_relax (IStack
*istack
,
3623 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3624 offsetT pc_offset
, /* offset in fragment */
3625 int min_steps
, /* minimum conversion steps */
3626 long stretch
) /* number of bytes stretched so far */
3628 int steps_taken
= 0;
3630 /* Some of its immeds don't fit. Try to build a relaxed version.
3631 This may go through a couple of stages of single instruction
3632 transformations before we get there. */
3634 TInsn single_target
;
3636 int lateral_steps
= 0;
3637 int istack_size
= istack
->ninsn
;
3639 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3640 && steps_taken
>= min_steps
)
3642 istack_push (istack
, insn
);
3645 current_insn
= *insn
;
3647 /* Walk through all of the single instruction expansions. */
3648 while (xg_is_single_relaxable_insn (¤t_insn
, &single_target
, FALSE
))
3651 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3654 if (steps_taken
>= min_steps
)
3656 istack_push (istack
, &single_target
);
3660 current_insn
= single_target
;
3663 /* Now check for a multi-instruction expansion. */
3664 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3666 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3669 if (steps_taken
>= min_steps
)
3671 istack_push (istack
, ¤t_insn
);
3676 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3678 if (steps_taken
>= min_steps
)
3682 istack
->ninsn
= istack_size
;
3685 /* It's not going to work -- use the original. */
3686 istack_push (istack
, insn
);
3692 xg_finish_frag (char *last_insn
,
3693 enum xtensa_relax_statesE frag_state
,
3694 enum xtensa_relax_statesE slot0_state
,
3696 bfd_boolean is_insn
)
3698 /* Finish off this fragment so that it has at LEAST the desired
3699 max_growth. If it doesn't fit in this fragment, close this one
3700 and start a new one. In either case, return a pointer to the
3701 beginning of the growth area. */
3705 frag_grow (max_growth
);
3706 old_frag
= frag_now
;
3708 frag_now
->fr_opcode
= last_insn
;
3710 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3712 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3713 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3715 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3716 xtensa_set_frag_assembly_state (frag_now
);
3718 /* Just to make sure that we did not split it up. */
3719 gas_assert (old_frag
->fr_next
== frag_now
);
3723 /* Return TRUE if the target frag is one of the next non-empty frags. */
3726 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3731 for (; fragP
; fragP
= fragP
->fr_next
)
3733 if (fragP
== target
)
3735 if (fragP
->fr_fix
!= 0)
3737 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3739 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3740 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3742 if (fragP
->fr_type
== rs_space
)
3750 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3752 xtensa_isa isa
= xtensa_default_isa
;
3754 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3759 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) != 1
3760 && xtensa_opcode_is_jump (isa
, insn
->opcode
) != 1)
3763 for (i
= 0; i
< num_ops
; i
++)
3765 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3771 if (target_op
== -1)
3774 if (insn
->ntok
<= target_op
)
3777 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3780 sym
= insn
->tok
[target_op
].X_add_symbol
;
3784 if (insn
->tok
[target_op
].X_add_number
!= 0)
3787 target_frag
= symbol_get_frag (sym
);
3788 if (target_frag
== NULL
)
3791 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3792 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3800 xg_add_branch_and_loop_targets (TInsn
*insn
)
3802 xtensa_isa isa
= xtensa_default_isa
;
3803 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3805 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3808 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3809 && insn
->tok
[i
].X_op
== O_symbol
)
3810 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3814 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3815 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3819 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3821 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3822 && insn
->tok
[i
].X_op
== O_symbol
)
3824 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3825 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3826 if (S_IS_DEFINED (sym
))
3827 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3834 /* Return FALSE if no error. */
3837 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3842 switch (instr_spec
->typ
)
3845 new_insn
->insn_type
= ITYPE_INSN
;
3846 new_insn
->opcode
= instr_spec
->opcode
;
3848 case INSTR_LITERAL_DEF
:
3849 new_insn
->insn_type
= ITYPE_LITERAL
;
3850 new_insn
->opcode
= XTENSA_UNDEFINED
;
3852 case INSTR_LABEL_DEF
:
3855 new_insn
->is_specific_opcode
= FALSE
;
3856 new_insn
->debug_line
= old_insn
->debug_line
;
3857 new_insn
->loc_directive_seen
= old_insn
->loc_directive_seen
;
3859 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3862 const expressionS
*src_exp
;
3868 /* The expression must be the constant. */
3869 gas_assert (b_op
->op_num
< MAX_INSN_ARGS
);
3870 exp
= &new_insn
->tok
[b_op
->op_num
];
3871 set_expr_const (exp
, b_op
->op_data
);
3875 gas_assert (b_op
->op_num
< MAX_INSN_ARGS
);
3876 gas_assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
3877 src_exp
= &old_insn
->tok
[b_op
->op_data
];
3878 exp
= &new_insn
->tok
[b_op
->op_num
];
3879 copy_expr (exp
, src_exp
);
3884 as_bad (_("can't handle generation of literal/labels yet"));
3888 as_bad (_("can't handle undefined OP TYPE"));
3893 new_insn
->ntok
= num_ops
;
3898 /* Return TRUE if it was simplified. */
3901 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
3903 TransitionRule
*rule
;
3904 BuildInstr
*insn_spec
;
3906 if (old_insn
->is_specific_opcode
|| !density_supported
)
3909 rule
= xg_instruction_match (old_insn
);
3913 insn_spec
= rule
->to_instr
;
3914 /* There should only be one. */
3915 gas_assert (insn_spec
!= NULL
);
3916 gas_assert (insn_spec
->next
== NULL
);
3917 if (insn_spec
->next
!= NULL
)
3920 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
3926 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3927 l32i.n. (2) Check the number of operands. (3) Place the instruction
3928 tokens into the stack or relax it and place multiple
3929 instructions/literals onto the stack. Return FALSE if no error. */
3932 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
3936 bfd_boolean do_expand
;
3938 tinsn_init (&new_insn
);
3940 /* Narrow it if we can. xg_simplify_insn now does all the
3941 appropriate checking (e.g., for the density option). */
3942 if (xg_simplify_insn (orig_insn
, &new_insn
))
3943 orig_insn
= &new_insn
;
3945 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
3947 if (orig_insn
->ntok
< noperands
)
3949 as_bad (_("found %d operands for '%s': Expected %d"),
3951 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3955 if (orig_insn
->ntok
> noperands
)
3956 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
3958 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3961 /* If there are not enough operands, we will assert above. If there
3962 are too many, just cut out the extras here. */
3963 orig_insn
->ntok
= noperands
;
3965 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
3968 /* Special case for extui opcode which has constraints not handled
3969 by the ordinary operand encoding checks. The number of operands
3970 and related syntax issues have already been checked. */
3971 if (orig_insn
->opcode
== xtensa_extui_opcode
)
3973 int shiftimm
= orig_insn
->tok
[2].X_add_number
;
3974 int maskimm
= orig_insn
->tok
[3].X_add_number
;
3975 if (shiftimm
+ maskimm
> 32)
3977 as_bad (_("immediate operands sum to greater than 32"));
3982 /* If the instruction will definitely need to be relaxed, it is better
3983 to expand it now for better scheduling. Decide whether to expand
3985 do_expand
= (!orig_insn
->is_specific_opcode
&& use_transform ());
3987 /* Calls should be expanded to longcalls only in the backend relaxation
3988 so that the assembly scheduler will keep the L32R/CALLX instructions
3990 if (is_direct_call_opcode (orig_insn
->opcode
))
3993 if (tinsn_has_symbolic_operands (orig_insn
))
3995 /* The values of symbolic operands are not known yet, so only expand
3996 now if an operand is "complex" (e.g., difference of symbols) and
3997 will have to be stored as a literal regardless of the value. */
3998 if (!tinsn_has_complex_operands (orig_insn
))
4001 else if (xg_immeds_fit (orig_insn
))
4005 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
4007 istack_push (istack
, orig_insn
);
4013 /* Return TRUE if the section flags are marked linkonce
4014 or the name is .gnu.linkonce.*. */
4016 static int linkonce_len
= sizeof (".gnu.linkonce.") - 1;
4019 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
4021 flagword flags
, link_once_flags
;
4023 flags
= bfd_get_section_flags (abfd
, sec
);
4024 link_once_flags
= (flags
& SEC_LINK_ONCE
);
4026 /* Flags might not be set yet. */
4027 if (!link_once_flags
4028 && strncmp (segment_name (sec
), ".gnu.linkonce.", linkonce_len
) == 0)
4029 link_once_flags
= SEC_LINK_ONCE
;
4031 return (link_once_flags
!= 0);
4036 xtensa_add_literal_sym (symbolS
*sym
)
4040 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
4042 l
->next
= literal_syms
;
4048 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
4050 static int lit_num
= 0;
4051 static char name
[256];
4054 sprintf (name
, ".L_lit_sym%d", lit_num
);
4056 /* Create a local symbol. If it is in a linkonce section, we have to
4057 be careful to make sure that if it is used in a relocation that the
4058 symbol will be in the output file. */
4059 if (get_is_linkonce_section (stdoutput
, sec
))
4061 symbolP
= symbol_new (name
, sec
, 0, frag
);
4062 S_CLEAR_EXTERNAL (symbolP
);
4063 /* symbolP->local = 1; */
4066 symbolP
= symbol_new (name
, sec
, 0, frag
);
4068 xtensa_add_literal_sym (symbolP
);
4075 /* Currently all literals that are generated here are 32-bit L32R targets. */
4078 xg_assemble_literal (/* const */ TInsn
*insn
)
4081 symbolS
*lit_sym
= NULL
;
4082 bfd_reloc_code_real_type reloc
;
4083 bfd_boolean pcrel
= FALSE
;
4086 /* size = 4 for L32R. It could easily be larger when we move to
4087 larger constants. Add a parameter later. */
4088 offsetT litsize
= 4;
4089 offsetT litalign
= 2; /* 2^2 = 4 */
4090 expressionS saved_loc
;
4091 expressionS
* emit_val
;
4093 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
4095 gas_assert (insn
->insn_type
== ITYPE_LITERAL
);
4096 gas_assert (insn
->ntok
== 1); /* must be only one token here */
4098 xtensa_switch_to_literal_fragment (&state
);
4100 emit_val
= &insn
->tok
[0];
4101 if (emit_val
->X_op
== O_big
)
4103 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
4106 /* This happens when someone writes a "movi a2, big_number". */
4107 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4108 _("invalid immediate"));
4109 xtensa_restore_emit_state (&state
);
4114 /* Force a 4-byte align here. Note that this opens a new frag, so all
4115 literals done with this function have a frag to themselves. That's
4116 important for the way text section literals work. */
4117 frag_align (litalign
, 0, 0);
4118 record_alignment (now_seg
, litalign
);
4120 switch (emit_val
->X_op
)
4130 p
= frag_more (litsize
);
4131 xtensa_set_frag_assembly_state (frag_now
);
4132 reloc
= map_operator_to_reloc (emit_val
->X_op
, TRUE
);
4133 if (emit_val
->X_add_symbol
)
4134 emit_val
->X_op
= O_symbol
;
4136 emit_val
->X_op
= O_constant
;
4137 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
4138 litsize
, emit_val
, pcrel
, reloc
);
4142 emit_expr (emit_val
, litsize
);
4146 gas_assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
4147 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4148 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4149 lit_sym
= frag_now
->fr_symbol
;
4152 xtensa_restore_emit_state (&state
);
4158 xg_assemble_literal_space (/* const */ int size
, int slot
)
4161 /* We might have to do something about this alignment. It only
4162 takes effect if something is placed here. */
4163 offsetT litalign
= 2; /* 2^2 = 4 */
4164 fragS
*lit_saved_frag
;
4166 gas_assert (size
% 4 == 0);
4168 xtensa_switch_to_literal_fragment (&state
);
4170 /* Force a 4-byte align here. */
4171 frag_align (litalign
, 0, 0);
4172 record_alignment (now_seg
, litalign
);
4176 lit_saved_frag
= frag_now
;
4177 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4178 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4179 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4182 xtensa_restore_emit_state (&state
);
4183 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4187 /* Put in a fixup record based on the opcode.
4188 Return TRUE on success. */
4191 xg_add_opcode_fix (TInsn
*tinsn
,
4199 xtensa_opcode opcode
= tinsn
->opcode
;
4200 bfd_reloc_code_real_type reloc
;
4201 reloc_howto_type
*howto
;
4205 reloc
= BFD_RELOC_NONE
;
4207 /* First try the special cases for "alternate" relocs. */
4208 if (opcode
== xtensa_l32r_opcode
)
4210 if (fragP
->tc_frag_data
.use_absolute_literals
)
4211 reloc
= encode_alt_reloc (slot
);
4213 else if (opcode
== xtensa_const16_opcode
)
4215 if (exp
->X_op
== O_lo16
)
4217 reloc
= encode_reloc (slot
);
4218 exp
->X_op
= O_symbol
;
4220 else if (exp
->X_op
== O_hi16
)
4222 reloc
= encode_alt_reloc (slot
);
4223 exp
->X_op
= O_symbol
;
4227 if (opnum
!= get_relaxable_immed (opcode
))
4229 as_bad (_("invalid relocation for operand %i of '%s'"),
4230 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4234 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4235 into the symbol table where the generic portions of the assembler
4236 won't know what to do with them. */
4237 if (exp
->X_op
== O_lo16
|| exp
->X_op
== O_hi16
)
4239 as_bad (_("invalid expression for operand %i of '%s'"),
4240 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4244 /* Next try the generic relocs. */
4245 if (reloc
== BFD_RELOC_NONE
)
4246 reloc
= encode_reloc (slot
);
4247 if (reloc
== BFD_RELOC_NONE
)
4249 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4253 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4256 as_bad (_("undefined symbol for opcode \"%s\""),
4257 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4261 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4262 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, exp
,
4263 howto
->pc_relative
, reloc
);
4264 the_fix
->fx_no_overflow
= 1;
4265 the_fix
->tc_fix_data
.X_add_symbol
= exp
->X_add_symbol
;
4266 the_fix
->tc_fix_data
.X_add_number
= exp
->X_add_number
;
4267 the_fix
->tc_fix_data
.slot
= slot
;
4274 xg_emit_insn_to_buf (TInsn
*tinsn
,
4278 bfd_boolean build_fix
)
4280 static xtensa_insnbuf insnbuf
= NULL
;
4281 bfd_boolean has_symbolic_immed
= FALSE
;
4282 bfd_boolean ok
= TRUE
;
4285 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4287 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4288 if (has_symbolic_immed
&& build_fix
)
4291 xtensa_format fmt
= xg_get_single_format (tinsn
->opcode
);
4292 int slot
= xg_get_single_slot (tinsn
->opcode
);
4293 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4294 expressionS
*exp
= &tinsn
->tok
[opnum
];
4296 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, slot
, exp
, fragP
, offset
))
4299 fragP
->tc_frag_data
.is_insn
= TRUE
;
4300 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4301 (unsigned char *) buf
, 0);
4307 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4309 symbolS
*sym
= get_special_literal_symbol ();
4313 gas_assert (insn
->insn_type
== ITYPE_INSN
);
4314 for (i
= 0; i
< insn
->ntok
; i
++)
4315 if (insn
->tok
[i
].X_add_symbol
== sym
)
4316 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4322 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4324 symbolS
*sym
= get_special_label_symbol ();
4326 for (i
= 0; i
< insn
->ntok
; i
++)
4327 if (insn
->tok
[i
].X_add_symbol
== sym
)
4328 insn
->tok
[i
].X_add_symbol
= label_sym
;
4333 /* Return TRUE if the instruction can write to the specified
4334 integer register. */
4337 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4341 xtensa_isa isa
= xtensa_default_isa
;
4343 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4345 for (i
= 0; i
< num_ops
; i
++)
4348 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4349 if ((inout
== 'o' || inout
== 'm')
4350 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4352 xtensa_regfile opnd_rf
=
4353 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4354 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4356 if ((insn
->tok
[i
].X_op
== O_register
)
4357 && (insn
->tok
[i
].X_add_number
== regnum
))
4367 is_bad_loopend_opcode (const TInsn
*tinsn
)
4369 xtensa_opcode opcode
= tinsn
->opcode
;
4371 if (opcode
== XTENSA_UNDEFINED
)
4374 if (opcode
== xtensa_call0_opcode
4375 || opcode
== xtensa_callx0_opcode
4376 || opcode
== xtensa_call4_opcode
4377 || opcode
== xtensa_callx4_opcode
4378 || opcode
== xtensa_call8_opcode
4379 || opcode
== xtensa_callx8_opcode
4380 || opcode
== xtensa_call12_opcode
4381 || opcode
== xtensa_callx12_opcode
4382 || opcode
== xtensa_isync_opcode
4383 || opcode
== xtensa_ret_opcode
4384 || opcode
== xtensa_ret_n_opcode
4385 || opcode
== xtensa_retw_opcode
4386 || opcode
== xtensa_retw_n_opcode
4387 || opcode
== xtensa_waiti_opcode
4388 || opcode
== xtensa_rsr_lcount_opcode
)
4395 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4396 This allows the debugger to add unaligned labels.
4397 Also, the assembler generates stabs labels that need
4398 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4401 is_unaligned_label (symbolS
*sym
)
4403 const char *name
= S_GET_NAME (sym
);
4404 static size_t fake_size
= 0;
4408 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4411 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4413 fake_size
= strlen (FAKE_LABEL_NAME
);
4416 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4417 && (name
[fake_size
] == 'F'
4418 || name
[fake_size
] == 'L'
4419 || (name
[fake_size
] == 'e'
4420 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4428 next_non_empty_frag (const fragS
*fragP
)
4430 fragS
*next_fragP
= fragP
->fr_next
;
4432 /* Sometimes an empty will end up here due storage allocation issues.
4433 So we have to skip until we find something legit. */
4434 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4435 next_fragP
= next_fragP
->fr_next
;
4437 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4445 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4447 xtensa_opcode out_opcode
;
4448 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4450 if (next_fragP
== NULL
)
4453 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4454 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4456 *opcode
= out_opcode
;
4464 frag_format_size (const fragS
*fragP
)
4466 static xtensa_insnbuf insnbuf
= NULL
;
4467 xtensa_isa isa
= xtensa_default_isa
;
4472 insnbuf
= xtensa_insnbuf_alloc (isa
);
4475 return XTENSA_UNDEFINED
;
4477 xtensa_insnbuf_from_chars (isa
, insnbuf
,
4478 (unsigned char *) fragP
->fr_literal
, 0);
4480 fmt
= xtensa_format_decode (isa
, insnbuf
);
4481 if (fmt
== XTENSA_UNDEFINED
)
4482 return XTENSA_UNDEFINED
;
4483 fmt_size
= xtensa_format_length (isa
, fmt
);
4485 /* If the next format won't be changing due to relaxation, just
4486 return the length of the first format. */
4487 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4490 /* If during relaxation we have to pull an instruction out of a
4491 multi-slot instruction, we will return the more conservative
4492 number. This works because alignment on bigger instructions
4493 is more restrictive than alignment on smaller instructions.
4494 This is more conservative than we would like, but it happens
4497 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4500 /* If we aren't doing one of our own relaxations or it isn't
4501 slot-based, then the insn size won't change. */
4502 if (fragP
->fr_type
!= rs_machine_dependent
)
4504 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4507 /* If an instruction is about to grow, return the longer size. */
4508 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4509 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
4510 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP3
)
4512 /* For most frags at RELAX_IMMED_STEPX, with X > 0, the first
4513 instruction in the relaxed version is of length 3. (The case
4514 where we have to pull the instruction out of a FLIX bundle
4515 is handled conservatively above.) However, frags with opcodes
4516 that are expanding to wide branches end up having formats that
4517 are not determinable by the RELAX_IMMED_STEPX enumeration, and
4518 we can't tell directly what format the relaxer picked. This
4519 is a wart in the design of the relaxer that should someday be
4520 fixed, but would require major changes, or at least should
4521 be accompanied by major changes to make use of that data.
4523 In any event, we can tell that we are expanding from a single-slot
4524 format to a wider one with the logic below. */
4527 int relaxed_size
= fmt_size
+ fragP
->tc_frag_data
.text_expansion
[0];
4529 for (i
= 0; i
< xtensa_isa_num_formats (isa
); i
++)
4531 if (relaxed_size
== xtensa_format_length (isa
, i
))
4532 return relaxed_size
;
4538 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4539 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4546 next_frag_format_size (const fragS
*fragP
)
4548 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4549 return frag_format_size (next_fragP
);
4553 /* In early Xtensa Processors, for reasons that are unclear, the ISA
4554 required two-byte instructions to be treated as three-byte instructions
4555 for loop instruction alignment. This restriction was removed beginning
4556 with Xtensa LX. Now the only requirement on loop instruction alignment
4557 is that the first instruction of the loop must appear at an address that
4558 does not cross a fetch boundary. */
4561 get_loop_align_size (int insn_size
)
4563 if (insn_size
== XTENSA_UNDEFINED
)
4564 return xtensa_fetch_width
;
4566 if (enforce_three_byte_loop_align
&& insn_size
== 2)
4573 /* If the next legit fragment is an end-of-loop marker,
4574 switch its state so it will instantiate a NOP. */
4577 update_next_frag_state (fragS
*fragP
)
4579 fragS
*next_fragP
= fragP
->fr_next
;
4580 fragS
*new_target
= NULL
;
4584 /* We are guaranteed there will be one of these... */
4585 while (!(next_fragP
->fr_type
== rs_machine_dependent
4586 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4587 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4588 next_fragP
= next_fragP
->fr_next
;
4590 gas_assert (next_fragP
->fr_type
== rs_machine_dependent
4591 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4592 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4594 /* ...and one of these. */
4595 new_target
= next_fragP
->fr_next
;
4596 while (!(new_target
->fr_type
== rs_machine_dependent
4597 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4598 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4599 new_target
= new_target
->fr_next
;
4601 gas_assert (new_target
->fr_type
== rs_machine_dependent
4602 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4603 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4606 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4608 if (next_fragP
->fr_type
== rs_machine_dependent
4609 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4611 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4615 next_fragP
= next_fragP
->fr_next
;
4621 next_frag_is_branch_target (const fragS
*fragP
)
4623 /* Sometimes an empty will end up here due to storage allocation issues,
4624 so we have to skip until we find something legit. */
4625 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4627 if (fragP
->tc_frag_data
.is_branch_target
)
4629 if (fragP
->fr_fix
!= 0)
4637 next_frag_is_loop_target (const fragS
*fragP
)
4639 /* Sometimes an empty will end up here due storage allocation issues.
4640 So we have to skip until we find something legit. */
4641 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4643 if (fragP
->tc_frag_data
.is_loop_target
)
4645 if (fragP
->fr_fix
!= 0)
4652 /* As specified in the relaxation table, when a loop instruction is
4653 relaxed, there are 24 bytes between the loop instruction itself and
4654 the first instruction in the loop. */
4656 #define RELAXED_LOOP_INSN_BYTES 24
4659 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4661 const fragS
*next_fragp
= fragp
->fr_next
;
4662 xtensa_opcode next_opcode
;
4664 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4667 /* Sometimes an empty will end up here due to storage allocation issues,
4668 so we have to skip until we find something legit. */
4669 while (next_fragp
->fr_fix
== 0)
4670 next_fragp
= next_fragp
->fr_next
;
4672 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4675 /* There is some implicit knowledge encoded in here.
4676 The LOOP instructions that are NOT RELAX_IMMED have
4677 been relaxed. Note that we can assume that the LOOP
4678 instruction is in slot 0 because loops aren't bundleable. */
4679 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4680 return get_expanded_loop_offset (next_opcode
) + RELAXED_LOOP_INSN_BYTES
;
4686 /* Mark a location where we can later insert literal frags. Update
4687 the section's literal_pool_loc, so subsequent literals can be
4688 placed nearest to their use. */
4691 xtensa_mark_literal_pool_location (void)
4693 /* Any labels pointing to the current location need
4694 to be adjusted to after the literal pool. */
4696 fragS
*pool_location
;
4698 if (use_literal_section
)
4701 /* We stash info in these frags so we can later move the literal's
4702 fixes into this frchain's fix list. */
4703 pool_location
= frag_now
;
4704 frag_now
->tc_frag_data
.lit_frchain
= frchain_now
;
4705 frag_now
->tc_frag_data
.literal_frag
= frag_now
;
4706 frag_variant (rs_machine_dependent
, 0, 0,
4707 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4708 xtensa_set_frag_assembly_state (frag_now
);
4709 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
4710 frag_variant (rs_machine_dependent
, 0, 0,
4711 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4712 xtensa_set_frag_assembly_state (frag_now
);
4714 /* Now put a frag into the literal pool that points to this location. */
4715 set_literal_pool_location (now_seg
, pool_location
);
4716 xtensa_switch_to_non_abs_literal_fragment (&s
);
4717 frag_align (2, 0, 0);
4718 record_alignment (now_seg
, 2);
4720 /* Close whatever frag is there. */
4721 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4722 xtensa_set_frag_assembly_state (frag_now
);
4723 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
4724 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4725 xtensa_restore_emit_state (&s
);
4726 xtensa_set_frag_assembly_state (frag_now
);
4730 /* Build a nop of the correct size into tinsn. */
4733 build_nop (TInsn
*tinsn
, int size
)
4739 tinsn
->opcode
= xtensa_nop_n_opcode
;
4741 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4742 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4746 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4748 tinsn
->opcode
= xtensa_or_opcode
;
4749 set_expr_const (&tinsn
->tok
[0], 1);
4750 set_expr_const (&tinsn
->tok
[1], 1);
4751 set_expr_const (&tinsn
->tok
[2], 1);
4755 tinsn
->opcode
= xtensa_nop_opcode
;
4757 gas_assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4762 /* Assemble a NOP of the requested size in the buffer. User must have
4763 allocated "buf" with at least "size" bytes. */
4766 assemble_nop (int size
, char *buf
)
4768 static xtensa_insnbuf insnbuf
= NULL
;
4771 build_nop (&tinsn
, size
);
4774 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4776 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4777 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4778 (unsigned char *) buf
, 0);
4782 /* Return the number of bytes for the offset of the expanded loop
4783 instruction. This should be incorporated into the relaxation
4784 specification but is hard-coded here. This is used to auto-align
4785 the loop instruction. It is invalid to call this function if the
4786 configuration does not have loops or if the opcode is not a loop
4790 get_expanded_loop_offset (xtensa_opcode opcode
)
4792 /* This is the OFFSET of the loop instruction in the expanded loop.
4793 This MUST correspond directly to the specification of the loop
4794 expansion. It will be validated on fragment conversion. */
4795 gas_assert (opcode
!= XTENSA_UNDEFINED
);
4796 if (opcode
== xtensa_loop_opcode
)
4798 if (opcode
== xtensa_loopnez_opcode
)
4800 if (opcode
== xtensa_loopgtz_opcode
)
4802 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4808 get_literal_pool_location (segT seg
)
4810 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4815 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4817 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4821 /* Set frag assembly state should be called when a new frag is
4822 opened and after a frag has been closed. */
4825 xtensa_set_frag_assembly_state (fragS
*fragP
)
4827 if (!density_supported
)
4828 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4830 /* This function is called from subsegs_finish, which is called
4831 after xtensa_end, so we can't use "use_transform" or
4832 "use_schedule" here. */
4833 if (!directive_state
[directive_transform
])
4834 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4835 if (directive_state
[directive_longcalls
])
4836 fragP
->tc_frag_data
.use_longcalls
= TRUE
;
4837 fragP
->tc_frag_data
.use_absolute_literals
=
4838 directive_state
[directive_absolute_literals
];
4839 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4844 relaxable_section (asection
*sec
)
4846 return ((sec
->flags
& SEC_DEBUGGING
) == 0
4847 && strcmp (sec
->name
, ".eh_frame") != 0);
4852 xtensa_mark_frags_for_org (void)
4856 /* Walk over each fragment of all of the current segments. If we find
4857 a .org frag in any of the segments, mark all frags prior to it as
4858 "no transform", which will prevent linker optimizations from messing
4859 up the .org distance. This should be done after
4860 xtensa_find_unmarked_state_frags, because we don't want to worry here
4861 about that function trashing the data we save here. */
4863 for (seclist
= &stdoutput
->sections
;
4864 seclist
&& *seclist
;
4865 seclist
= &(*seclist
)->next
)
4867 segT sec
= *seclist
;
4868 segment_info_type
*seginfo
;
4871 flags
= bfd_get_section_flags (stdoutput
, sec
);
4872 if (flags
& SEC_DEBUGGING
)
4874 if (!(flags
& SEC_ALLOC
))
4877 seginfo
= seg_info (sec
);
4878 if (seginfo
&& seginfo
->frchainP
)
4880 fragS
*last_fragP
= seginfo
->frchainP
->frch_root
;
4881 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4882 fragP
= fragP
->fr_next
)
4884 /* cvt_frag_to_fill has changed the fr_type of org frags to
4885 rs_fill, so use the value as cached in rs_subtype here. */
4886 if (fragP
->fr_subtype
== RELAX_ORG
)
4888 while (last_fragP
!= fragP
->fr_next
)
4890 last_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4891 last_fragP
= last_fragP
->fr_next
;
4901 xtensa_find_unmarked_state_frags (void)
4905 /* Walk over each fragment of all of the current segments. For each
4906 unmarked fragment, mark it with the same info as the previous
4908 for (seclist
= &stdoutput
->sections
;
4909 seclist
&& *seclist
;
4910 seclist
= &(*seclist
)->next
)
4912 segT sec
= *seclist
;
4913 segment_info_type
*seginfo
;
4916 flags
= bfd_get_section_flags (stdoutput
, sec
);
4917 if (flags
& SEC_DEBUGGING
)
4919 if (!(flags
& SEC_ALLOC
))
4922 seginfo
= seg_info (sec
);
4923 if (seginfo
&& seginfo
->frchainP
)
4925 fragS
*last_fragP
= 0;
4926 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4927 fragP
= fragP
->fr_next
)
4929 if (fragP
->fr_fix
!= 0
4930 && !fragP
->tc_frag_data
.is_assembly_state_set
)
4932 if (last_fragP
== 0)
4934 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
4935 _("assembly state not set for first frag in section %s"),
4940 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4941 fragP
->tc_frag_data
.is_no_density
=
4942 last_fragP
->tc_frag_data
.is_no_density
;
4943 fragP
->tc_frag_data
.is_no_transform
=
4944 last_fragP
->tc_frag_data
.is_no_transform
;
4945 fragP
->tc_frag_data
.use_longcalls
=
4946 last_fragP
->tc_frag_data
.use_longcalls
;
4947 fragP
->tc_frag_data
.use_absolute_literals
=
4948 last_fragP
->tc_frag_data
.use_absolute_literals
;
4951 if (fragP
->tc_frag_data
.is_assembly_state_set
)
4960 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
4962 void *unused ATTRIBUTE_UNUSED
)
4964 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4965 segment_info_type
*seginfo
= seg_info (sec
);
4966 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4968 if (flags
& SEC_CODE
)
4970 xtensa_isa isa
= xtensa_default_isa
;
4971 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4972 while (frag
!= NULL
)
4974 if (frag
->tc_frag_data
.is_branch_target
)
4977 addressT branch_align
, frag_addr
;
4980 xtensa_insnbuf_from_chars
4981 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4982 fmt
= xtensa_format_decode (isa
, insnbuf
);
4983 op_size
= xtensa_format_length (isa
, fmt
);
4984 branch_align
= 1 << branch_align_power (sec
);
4985 frag_addr
= frag
->fr_address
% branch_align
;
4986 if (frag_addr
+ op_size
> branch_align
)
4987 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4988 _("unaligned branch target: %d bytes at 0x%lx"),
4989 op_size
, (long) frag
->fr_address
);
4991 frag
= frag
->fr_next
;
4993 xtensa_insnbuf_free (isa
, insnbuf
);
4999 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
5001 void *unused ATTRIBUTE_UNUSED
)
5003 flagword flags
= bfd_get_section_flags (abfd
, sec
);
5004 segment_info_type
*seginfo
= seg_info (sec
);
5005 fragS
*frag
= seginfo
->frchainP
->frch_root
;
5006 xtensa_isa isa
= xtensa_default_isa
;
5008 if (flags
& SEC_CODE
)
5010 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
5011 while (frag
!= NULL
)
5013 if (frag
->tc_frag_data
.is_first_loop_insn
)
5019 xtensa_insnbuf_from_chars
5020 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
5021 fmt
= xtensa_format_decode (isa
, insnbuf
);
5022 op_size
= xtensa_format_length (isa
, fmt
);
5023 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
5025 if (frag_addr
+ op_size
> xtensa_fetch_width
)
5026 as_warn_where (frag
->fr_file
, frag
->fr_line
,
5027 _("unaligned loop: %d bytes at 0x%lx"),
5028 op_size
, (long) frag
->fr_address
);
5030 frag
= frag
->fr_next
;
5032 xtensa_insnbuf_free (isa
, insnbuf
);
5038 xg_apply_fix_value (fixS
*fixP
, valueT val
)
5040 xtensa_isa isa
= xtensa_default_isa
;
5041 static xtensa_insnbuf insnbuf
= NULL
;
5042 static xtensa_insnbuf slotbuf
= NULL
;
5045 bfd_boolean alt_reloc
;
5046 xtensa_opcode opcode
;
5047 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5049 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
)
5051 as_fatal (_("unexpected fix"));
5055 insnbuf
= xtensa_insnbuf_alloc (isa
);
5056 slotbuf
= xtensa_insnbuf_alloc (isa
);
5059 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
5060 fmt
= xtensa_format_decode (isa
, insnbuf
);
5061 if (fmt
== XTENSA_UNDEFINED
)
5062 as_fatal (_("undecodable fix"));
5063 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5064 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5065 if (opcode
== XTENSA_UNDEFINED
)
5066 as_fatal (_("undecodable fix"));
5068 /* CONST16 immediates are not PC-relative, despite the fact that we
5069 reuse the normal PC-relative operand relocations for the low part
5070 of a CONST16 operand. */
5071 if (opcode
== xtensa_const16_opcode
)
5074 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
5075 get_relaxable_immed (opcode
), val
,
5076 fixP
->fx_file
, fixP
->fx_line
);
5078 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5079 xtensa_insnbuf_to_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
5085 /* External Functions and Other GAS Hooks. */
5088 xtensa_target_format (void)
5090 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
5095 xtensa_file_arch_init (bfd
*abfd
)
5097 bfd_set_private_flags (abfd
, 0x100 | 0x200);
5102 md_number_to_chars (char *buf
, valueT val
, int n
)
5104 if (target_big_endian
)
5105 number_to_chars_bigendian (buf
, val
, n
);
5107 number_to_chars_littleendian (buf
, val
, n
);
5111 /* This function is called once, at assembler startup time. It should
5112 set up all the tables, etc. that the MD part of the assembler will
5118 segT current_section
= now_seg
;
5119 int current_subsec
= now_subseg
;
5123 xtensa_default_isa
= xtensa_isa_init (0, 0);
5124 isa
= xtensa_default_isa
;
5128 /* Set up the literal sections. */
5129 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
5131 subseg_set (current_section
, current_subsec
);
5133 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
5134 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
5135 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
5136 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
5137 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
5138 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
5139 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
5140 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
5141 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
5142 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
5143 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
5144 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
5145 xtensa_extui_opcode
= xtensa_opcode_lookup (isa
, "extui");
5146 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
5147 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
5148 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
5149 xtensa_j_opcode
= xtensa_opcode_lookup (isa
, "j");
5150 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
5151 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
5152 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
5153 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
5154 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
5155 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
5156 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
5157 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
5158 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
5159 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
5160 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
5161 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
5162 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
5163 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
5165 for (i
= 0; i
< xtensa_isa_num_formats (isa
); i
++)
5167 int format_slots
= xtensa_format_num_slots (isa
, i
);
5168 if (format_slots
> config_max_slots
)
5169 config_max_slots
= format_slots
;
5172 xg_init_vinsn (&cur_vinsn
);
5174 xtensa_num_pipe_stages
= xtensa_isa_num_pipe_stages (isa
);
5176 init_op_placement_info_table ();
5178 /* Set up the assembly state. */
5179 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5180 xtensa_set_frag_assembly_state (frag_now
);
5184 /* TC_INIT_FIX_DATA hook */
5187 xtensa_init_fix_data (fixS
*x
)
5189 x
->tc_fix_data
.slot
= 0;
5190 x
->tc_fix_data
.X_add_symbol
= NULL
;
5191 x
->tc_fix_data
.X_add_number
= 0;
5195 /* tc_frob_label hook */
5198 xtensa_frob_label (symbolS
*sym
)
5202 if (cur_vinsn
.inside_bundle
)
5204 as_bad (_("labels are not valid inside bundles"));
5208 freq
= get_subseg_target_freq (now_seg
, now_subseg
);
5210 /* Since the label was already attached to a frag associated with the
5211 previous basic block, it now needs to be reset to the current frag. */
5212 symbol_set_frag (sym
, frag_now
);
5213 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5215 if (generating_literals
)
5216 xtensa_add_literal_sym (sym
);
5218 xtensa_add_insn_label (sym
);
5220 if (symbol_get_tc (sym
)->is_loop_target
)
5222 if ((get_last_insn_flags (now_seg
, now_subseg
)
5223 & FLAG_IS_BAD_LOOPEND
) != 0)
5224 as_bad (_("invalid last instruction for a zero-overhead loop"));
5226 xtensa_set_frag_assembly_state (frag_now
);
5227 frag_var (rs_machine_dependent
, 4, 4, RELAX_LOOP_END
,
5228 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5230 xtensa_set_frag_assembly_state (frag_now
);
5231 xtensa_move_labels (frag_now
, 0);
5234 /* No target aligning in the absolute section. */
5235 if (now_seg
!= absolute_section
5236 && !is_unaligned_label (sym
)
5237 && !generating_literals
)
5239 xtensa_set_frag_assembly_state (frag_now
);
5241 if (do_align_targets ())
5242 frag_var (rs_machine_dependent
, 0, (int) freq
,
5243 RELAX_DESIRE_ALIGN_IF_TARGET
, frag_now
->fr_symbol
,
5244 frag_now
->fr_offset
, NULL
);
5246 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
5247 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5248 xtensa_set_frag_assembly_state (frag_now
);
5249 xtensa_move_labels (frag_now
, 0);
5252 /* We need to mark the following properties even if we aren't aligning. */
5254 /* If the label is already known to be a branch target, i.e., a
5255 forward branch, mark the frag accordingly. Backward branches
5256 are handled by xg_add_branch_and_loop_targets. */
5257 if (symbol_get_tc (sym
)->is_branch_target
)
5258 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5260 /* Loops only go forward, so they can be identified here. */
5261 if (symbol_get_tc (sym
)->is_loop_target
)
5262 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5264 dwarf2_emit_label (sym
);
5268 /* tc_unrecognized_line hook */
5271 xtensa_unrecognized_line (int ch
)
5276 if (cur_vinsn
.inside_bundle
== 0)
5278 /* PR8110: Cannot emit line number info inside a FLIX bundle
5279 when using --gstabs. Temporarily disable debug info. */
5280 generate_lineno_debug ();
5281 if (debug_type
== DEBUG_STABS
)
5283 xt_saved_debug_type
= debug_type
;
5284 debug_type
= DEBUG_NONE
;
5287 cur_vinsn
.inside_bundle
= 1;
5291 as_bad (_("extra opening brace"));
5297 if (cur_vinsn
.inside_bundle
)
5298 finish_vinsn (&cur_vinsn
);
5301 as_bad (_("extra closing brace"));
5306 as_bad (_("syntax error"));
5313 /* md_flush_pending_output hook */
5316 xtensa_flush_pending_output (void)
5318 /* This line fixes a bug where automatically generated gstabs info
5319 separates a function label from its entry instruction, ending up
5320 with the literal position between the function label and the entry
5321 instruction and crashing code. It only happens with --gstabs and
5322 --text-section-literals, and when several other obscure relaxation
5323 conditions are met. */
5324 if (outputting_stabs_line_debug
)
5327 if (cur_vinsn
.inside_bundle
)
5328 as_bad (_("missing closing brace"));
5330 /* If there is a non-zero instruction fragment, close it. */
5331 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5333 frag_wane (frag_now
);
5335 xtensa_set_frag_assembly_state (frag_now
);
5337 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5339 xtensa_clear_insn_labels ();
5343 /* We had an error while parsing an instruction. The string might look
5344 like this: "insn arg1, arg2 }". If so, we need to see the closing
5345 brace and reset some fields. Otherwise, the vinsn never gets closed
5346 and the num_slots field will grow past the end of the array of slots,
5347 and bad things happen. */
5350 error_reset_cur_vinsn (void)
5352 if (cur_vinsn
.inside_bundle
)
5354 if (*input_line_pointer
== '}'
5355 || *(input_line_pointer
- 1) == '}'
5356 || *(input_line_pointer
- 2) == '}')
5357 xg_clear_vinsn (&cur_vinsn
);
5363 md_assemble (char *str
)
5365 xtensa_isa isa
= xtensa_default_isa
;
5368 bfd_boolean has_underbar
= FALSE
;
5369 char *arg_strings
[MAX_INSN_ARGS
];
5371 TInsn orig_insn
; /* Original instruction from the input. */
5373 tinsn_init (&orig_insn
);
5375 /* Split off the opcode. */
5376 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5377 opname
= xmalloc (opnamelen
+ 1);
5378 memcpy (opname
, str
, opnamelen
);
5379 opname
[opnamelen
] = '\0';
5381 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5384 as_bad (_("syntax error"));
5388 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5391 /* Check for an underbar prefix. */
5394 has_underbar
= TRUE
;
5398 orig_insn
.insn_type
= ITYPE_INSN
;
5400 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5401 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5403 /* Special case: Check for "CALLXn.TLS" psuedo op. If found, grab its
5404 extra argument and set the opcode to "CALLXn". */
5405 if (orig_insn
.opcode
== XTENSA_UNDEFINED
5406 && strncasecmp (opname
, "callx", 5) == 0)
5408 unsigned long window_size
;
5411 window_size
= strtoul (opname
+ 5, &suffix
, 10);
5412 if (suffix
!= opname
+ 5
5413 && (window_size
== 0
5416 || window_size
== 12)
5417 && strcasecmp (suffix
, ".tls") == 0)
5419 switch (window_size
)
5421 case 0: orig_insn
.opcode
= xtensa_callx0_opcode
; break;
5422 case 4: orig_insn
.opcode
= xtensa_callx4_opcode
; break;
5423 case 8: orig_insn
.opcode
= xtensa_callx8_opcode
; break;
5424 case 12: orig_insn
.opcode
= xtensa_callx12_opcode
; break;
5428 as_bad (_("wrong number of operands for '%s'"), opname
);
5431 bfd_reloc_code_real_type reloc
;
5432 char *old_input_line_pointer
;
5433 expressionS
*tok
= &orig_insn
.extra_arg
;
5436 old_input_line_pointer
= input_line_pointer
;
5437 input_line_pointer
= arg_strings
[num_args
- 1];
5439 t
= expression (tok
);
5440 if (tok
->X_op
== O_symbol
5441 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
5442 == BFD_RELOC_XTENSA_TLS_CALL
))
5443 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
5445 as_bad (_("bad relocation expression for '%s'"), opname
);
5447 input_line_pointer
= old_input_line_pointer
;
5453 /* Special case: Check for "j.l" psuedo op. */
5454 if (orig_insn
.opcode
== XTENSA_UNDEFINED
5455 && strncasecmp (opname
, "j.l", 3) == 0)
5458 as_bad (_("wrong number of operands for '%s'"), opname
);
5461 char *old_input_line_pointer
;
5462 expressionS
*tok
= &orig_insn
.extra_arg
;
5464 old_input_line_pointer
= input_line_pointer
;
5465 input_line_pointer
= arg_strings
[num_args
- 1];
5467 expression_maybe_register (xtensa_jx_opcode
, 0, tok
);
5468 input_line_pointer
= old_input_line_pointer
;
5471 orig_insn
.opcode
= xtensa_j_opcode
;
5475 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5477 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5478 if (fmt
== XTENSA_UNDEFINED
)
5480 as_bad (_("unknown opcode or format name '%s'"), opname
);
5481 error_reset_cur_vinsn ();
5484 if (!cur_vinsn
.inside_bundle
)
5486 as_bad (_("format names only valid inside bundles"));
5487 error_reset_cur_vinsn ();
5490 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5491 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5493 cur_vinsn
.format
= fmt
;
5494 free (has_underbar
? opname
- 1 : opname
);
5495 error_reset_cur_vinsn ();
5499 /* Parse the arguments. */
5500 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5502 as_bad (_("syntax error"));
5503 error_reset_cur_vinsn ();
5507 /* Free the opcode and argument strings, now that they've been parsed. */
5508 free (has_underbar
? opname
- 1 : opname
);
5510 while (num_args
-- > 0)
5511 free (arg_strings
[num_args
]);
5513 /* Get expressions for invisible operands. */
5514 if (get_invisible_operands (&orig_insn
))
5516 error_reset_cur_vinsn ();
5520 /* Check for the right number and type of arguments. */
5521 if (tinsn_check_arguments (&orig_insn
))
5523 error_reset_cur_vinsn ();
5527 /* Record the line number for each TInsn, because a FLIX bundle may be
5528 spread across multiple input lines and individual instructions may be
5529 moved around in some cases. */
5530 orig_insn
.loc_directive_seen
= dwarf2_loc_directive_seen
;
5531 dwarf2_where (&orig_insn
.debug_line
);
5532 dwarf2_consume_line_info ();
5534 xg_add_branch_and_loop_targets (&orig_insn
);
5536 /* Check that immediate value for ENTRY is >= 16. */
5537 if (orig_insn
.opcode
== xtensa_entry_opcode
&& orig_insn
.ntok
>= 3)
5539 expressionS
*exp
= &orig_insn
.tok
[2];
5540 if (exp
->X_op
== O_constant
&& exp
->X_add_number
< 16)
5541 as_warn (_("entry instruction with stack decrement < 16"));
5545 assemble_tokens (opcode, tok, ntok);
5546 expand the tokens from the orig_insn into the
5547 stack of instructions that will not expand
5548 unless required at relaxation time. */
5550 if (!cur_vinsn
.inside_bundle
)
5551 emit_single_op (&orig_insn
);
5552 else /* We are inside a bundle. */
5554 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5555 cur_vinsn
.num_slots
++;
5556 if (*input_line_pointer
== '}'
5557 || *(input_line_pointer
- 1) == '}'
5558 || *(input_line_pointer
- 2) == '}')
5559 finish_vinsn (&cur_vinsn
);
5562 /* We've just emitted a new instruction so clear the list of labels. */
5563 xtensa_clear_insn_labels ();
5567 /* HANDLE_ALIGN hook */
5569 /* For a .align directive, we mark the previous block with the alignment
5570 information. This will be placed in the object file in the
5571 property section corresponding to this section. */
5574 xtensa_handle_align (fragS
*fragP
)
5577 && ! fragP
->tc_frag_data
.is_literal
5578 && (fragP
->fr_type
== rs_align
5579 || fragP
->fr_type
== rs_align_code
)
5580 && fragP
->fr_address
+ fragP
->fr_fix
> 0
5581 && fragP
->fr_offset
> 0
5582 && now_seg
!= bss_section
)
5584 fragP
->tc_frag_data
.is_align
= TRUE
;
5585 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5588 if (fragP
->fr_type
== rs_align_test
)
5591 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5593 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5594 _("unaligned entry instruction"));
5597 if (linkrelax
&& fragP
->fr_type
== rs_org
)
5598 fragP
->fr_subtype
= RELAX_ORG
;
5602 /* TC_FRAG_INIT hook */
5605 xtensa_frag_init (fragS
*frag
)
5607 xtensa_set_frag_assembly_state (frag
);
5612 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5618 /* Round up a section size to the appropriate boundary. */
5621 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5623 return size
; /* Byte alignment is fine. */
5628 md_pcrel_from (fixS
*fixP
)
5631 static xtensa_insnbuf insnbuf
= NULL
;
5632 static xtensa_insnbuf slotbuf
= NULL
;
5635 xtensa_opcode opcode
;
5638 xtensa_isa isa
= xtensa_default_isa
;
5639 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5640 bfd_boolean alt_reloc
;
5642 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5645 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
5650 insnbuf
= xtensa_insnbuf_alloc (isa
);
5651 slotbuf
= xtensa_insnbuf_alloc (isa
);
5654 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5655 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) insn_p
, 0);
5656 fmt
= xtensa_format_decode (isa
, insnbuf
);
5658 if (fmt
== XTENSA_UNDEFINED
)
5659 as_fatal (_("bad instruction format"));
5661 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5662 as_fatal (_("invalid relocation"));
5664 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5665 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5667 /* Check for "alternate" relocations (operand not specified). None
5668 of the current uses for these are really PC-relative. */
5669 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5671 if (opcode
!= xtensa_l32r_opcode
5672 && opcode
!= xtensa_const16_opcode
)
5673 as_fatal (_("invalid relocation for '%s' instruction"),
5674 xtensa_opcode_name (isa
, opcode
));
5678 opnum
= get_relaxable_immed (opcode
);
5680 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5681 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5683 as_bad_where (fixP
->fx_file
,
5685 _("invalid relocation for operand %d of '%s'"),
5686 opnum
, xtensa_opcode_name (isa
, opcode
));
5689 return 0 - opnd_value
;
5693 /* TC_FORCE_RELOCATION hook */
5696 xtensa_force_relocation (fixS
*fix
)
5698 switch (fix
->fx_r_type
)
5700 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5701 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5702 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5703 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5704 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5705 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5706 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5707 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5708 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5709 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5710 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5711 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5712 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5713 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5714 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5715 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5721 if (linkrelax
&& fix
->fx_addsy
5722 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5725 return generic_force_reloc (fix
);
5729 /* TC_VALIDATE_FIX_SUB hook */
5732 xtensa_validate_fix_sub (fixS
*fix
)
5734 segT add_symbol_segment
, sub_symbol_segment
;
5736 /* The difference of two symbols should be resolved by the assembler when
5737 linkrelax is not set. If the linker may relax the section containing
5738 the symbols, then an Xtensa DIFF relocation must be generated so that
5739 the linker knows to adjust the difference value. */
5740 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
5743 /* Make sure both symbols are in the same segment, and that segment is
5744 "normal" and relaxable. If the segment is not "normal", then the
5745 fix is not valid. If the segment is not "relaxable", then the fix
5746 should have been handled earlier. */
5747 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
5748 if (! SEG_NORMAL (add_symbol_segment
) ||
5749 ! relaxable_section (add_symbol_segment
))
5751 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
5752 return (sub_symbol_segment
== add_symbol_segment
);
5756 /* NO_PSEUDO_DOT hook */
5758 /* This function has nothing to do with pseudo dots, but this is the
5759 nearest macro to where the check needs to take place. FIXME: This
5763 xtensa_check_inside_bundle (void)
5765 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5766 as_bad (_("directives are not valid inside bundles"));
5768 /* This function must always return FALSE because it is called via a
5769 macro that has nothing to do with bundling. */
5774 /* md_elf_section_change_hook */
5777 xtensa_elf_section_change_hook (void)
5779 /* Set up the assembly state. */
5780 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5781 xtensa_set_frag_assembly_state (frag_now
);
5785 /* tc_fix_adjustable hook */
5788 xtensa_fix_adjustable (fixS
*fixP
)
5790 /* We need the symbol name for the VTABLE entries. */
5791 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5792 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5799 /* tc_symbol_new_hook */
5801 symbolS
*expr_symbols
= NULL
;
5804 xtensa_symbol_new_hook (symbolS
*sym
)
5806 if (is_leb128_expr
&& S_GET_SEGMENT (sym
) == expr_section
)
5808 symbol_get_tc (sym
)->next_expr_symbol
= expr_symbols
;
5815 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg
)
5817 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5820 /* Subtracted symbols are only allowed for a few relocation types, and
5821 unless linkrelax is enabled, they should not make it to this point. */
5822 if (fixP
->fx_subsy
&& !(linkrelax
&& (fixP
->fx_r_type
== BFD_RELOC_32
5823 || fixP
->fx_r_type
== BFD_RELOC_16
5824 || fixP
->fx_r_type
== BFD_RELOC_8
)))
5825 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("expression too complex"));
5827 switch (fixP
->fx_r_type
)
5829 case BFD_RELOC_32_PCREL
:
5835 switch (fixP
->fx_r_type
)
5838 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF8
;
5841 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF16
;
5844 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF32
;
5850 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5851 - S_GET_VALUE (fixP
->fx_subsy
));
5853 /* The difference value gets written out, and the DIFF reloc
5854 identifies the address of the subtracted symbol (i.e., the one
5855 with the lowest address). */
5857 fixP
->fx_offset
-= val
;
5858 fixP
->fx_subsy
= NULL
;
5860 else if (! fixP
->fx_addsy
)
5867 case BFD_RELOC_XTENSA_PLT
:
5868 md_number_to_chars (fixpos
, val
, fixP
->fx_size
);
5869 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5872 case BFD_RELOC_XTENSA_TLSDESC_FN
:
5873 case BFD_RELOC_XTENSA_TLSDESC_ARG
:
5874 case BFD_RELOC_XTENSA_TLS_TPOFF
:
5875 case BFD_RELOC_XTENSA_TLS_DTPOFF
:
5876 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
5877 md_number_to_chars (fixpos
, 0, fixP
->fx_size
);
5878 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5881 case BFD_RELOC_XTENSA_SLOT0_OP
:
5882 case BFD_RELOC_XTENSA_SLOT1_OP
:
5883 case BFD_RELOC_XTENSA_SLOT2_OP
:
5884 case BFD_RELOC_XTENSA_SLOT3_OP
:
5885 case BFD_RELOC_XTENSA_SLOT4_OP
:
5886 case BFD_RELOC_XTENSA_SLOT5_OP
:
5887 case BFD_RELOC_XTENSA_SLOT6_OP
:
5888 case BFD_RELOC_XTENSA_SLOT7_OP
:
5889 case BFD_RELOC_XTENSA_SLOT8_OP
:
5890 case BFD_RELOC_XTENSA_SLOT9_OP
:
5891 case BFD_RELOC_XTENSA_SLOT10_OP
:
5892 case BFD_RELOC_XTENSA_SLOT11_OP
:
5893 case BFD_RELOC_XTENSA_SLOT12_OP
:
5894 case BFD_RELOC_XTENSA_SLOT13_OP
:
5895 case BFD_RELOC_XTENSA_SLOT14_OP
:
5898 /* Write the tentative value of a PC-relative relocation to a
5899 local symbol into the instruction. The value will be ignored
5900 by the linker, and it makes the object file disassembly
5901 readable when all branch targets are encoded in relocations. */
5903 gas_assert (fixP
->fx_addsy
);
5904 if (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
5905 && !S_FORCE_RELOC (fixP
->fx_addsy
, 1))
5907 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5908 - md_pcrel_from (fixP
));
5909 (void) xg_apply_fix_value (fixP
, val
);
5912 else if (! fixP
->fx_addsy
)
5915 if (xg_apply_fix_value (fixP
, val
))
5920 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5921 case BFD_RELOC_XTENSA_TLS_FUNC
:
5922 case BFD_RELOC_XTENSA_TLS_ARG
:
5923 case BFD_RELOC_XTENSA_TLS_CALL
:
5924 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5925 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5926 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5927 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5928 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5929 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5930 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5931 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5932 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5933 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5934 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5935 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5936 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5937 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5938 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5939 /* These all need to be resolved at link-time. Do nothing now. */
5942 case BFD_RELOC_VTABLE_INHERIT
:
5943 case BFD_RELOC_VTABLE_ENTRY
:
5948 as_bad (_("unhandled local relocation fix %s"),
5949 bfd_get_reloc_code_name (fixP
->fx_r_type
));
5955 md_atof (int type
, char *litP
, int *sizeP
)
5957 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
5962 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
5964 return total_frag_text_expansion (fragP
);
5968 /* Translate internal representation of relocation info to BFD target
5972 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
5976 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
5977 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5978 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5979 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5981 /* Make sure none of our internal relocations make it this far.
5982 They'd better have been fully resolved by this point. */
5983 gas_assert ((int) fixp
->fx_r_type
> 0);
5985 reloc
->addend
= fixp
->fx_offset
;
5987 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
5988 if (reloc
->howto
== NULL
)
5990 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5991 _("cannot represent `%s' relocation in object file"),
5992 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5993 free (reloc
->sym_ptr_ptr
);
5998 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
5999 as_fatal (_("internal error; cannot generate `%s' relocation"),
6000 bfd_get_reloc_code_name (fixp
->fx_r_type
));
6006 /* Checks for resource conflicts between instructions. */
6008 /* The func unit stuff could be implemented as bit-vectors rather
6009 than the iterative approach here. If it ends up being too
6010 slow, we will switch it. */
6013 new_resource_table (void *data
,
6016 unit_num_copies_func uncf
,
6017 opcode_num_units_func onuf
,
6018 opcode_funcUnit_use_unit_func ouuf
,
6019 opcode_funcUnit_use_stage_func ousf
)
6022 resource_table
*rt
= (resource_table
*) xmalloc (sizeof (resource_table
));
6024 rt
->cycles
= cycles
;
6025 rt
->allocated_cycles
= cycles
;
6027 rt
->unit_num_copies
= uncf
;
6028 rt
->opcode_num_units
= onuf
;
6029 rt
->opcode_unit_use
= ouuf
;
6030 rt
->opcode_unit_stage
= ousf
;
6032 rt
->units
= (unsigned char **) xcalloc (cycles
, sizeof (unsigned char *));
6033 for (i
= 0; i
< cycles
; i
++)
6034 rt
->units
[i
] = (unsigned char *) xcalloc (nu
, sizeof (unsigned char));
6041 clear_resource_table (resource_table
*rt
)
6044 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
6045 for (j
= 0; j
< rt
->num_units
; j
++)
6046 rt
->units
[i
][j
] = 0;
6050 /* We never shrink it, just fake it into thinking so. */
6053 resize_resource_table (resource_table
*rt
, int cycles
)
6057 rt
->cycles
= cycles
;
6058 if (cycles
<= rt
->allocated_cycles
)
6061 old_cycles
= rt
->allocated_cycles
;
6062 rt
->allocated_cycles
= cycles
;
6064 rt
->units
= xrealloc (rt
->units
,
6065 rt
->allocated_cycles
* sizeof (unsigned char *));
6066 for (i
= 0; i
< old_cycles
; i
++)
6067 rt
->units
[i
] = xrealloc (rt
->units
[i
],
6068 rt
->num_units
* sizeof (unsigned char));
6069 for (i
= old_cycles
; i
< cycles
; i
++)
6070 rt
->units
[i
] = xcalloc (rt
->num_units
, sizeof (unsigned char));
6075 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6078 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6080 for (i
= 0; i
< uses
; i
++)
6082 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6083 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6084 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
6085 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
6086 if (copies_in_use
>= copies
)
6094 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6097 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6099 for (i
= 0; i
< uses
; i
++)
6101 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6102 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6103 /* Note that this allows resources to be oversubscribed. That's
6104 essential to the way the optional scheduler works.
6105 resources_available reports when a resource is over-subscribed,
6106 so it's easy to tell. */
6107 rt
->units
[stage
+ cycle
][unit
]++;
6113 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6116 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6118 for (i
= 0; i
< uses
; i
++)
6120 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6121 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6122 gas_assert (rt
->units
[stage
+ cycle
][unit
] > 0);
6123 rt
->units
[stage
+ cycle
][unit
]--;
6128 /* Wrapper functions make parameterized resource reservation
6132 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
6134 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
6140 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
6142 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
6147 /* Note that this function does not check issue constraints, but
6148 solely whether the hardware is available to execute the given
6149 instructions together. It also doesn't check if the tinsns
6150 write the same state, or access the same tieports. That is
6151 checked by check_t1_t2_reads_and_writes. */
6154 resources_conflict (vliw_insn
*vinsn
)
6157 static resource_table
*rt
= NULL
;
6159 /* This is the most common case by far. Optimize it. */
6160 if (vinsn
->num_slots
== 1)
6165 xtensa_isa isa
= xtensa_default_isa
;
6166 rt
= new_resource_table
6167 (isa
, xtensa_num_pipe_stages
,
6168 xtensa_isa_num_funcUnits (isa
),
6169 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
6170 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
6171 opcode_funcUnit_use_unit
,
6172 opcode_funcUnit_use_stage
);
6175 clear_resource_table (rt
);
6177 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6179 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
6181 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
6188 /* finish_vinsn, emit_single_op and helper functions. */
6190 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
6191 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
6192 static void xg_assemble_vliw_tokens (vliw_insn
*);
6195 /* We have reached the end of a bundle; emit into the frag. */
6198 finish_vinsn (vliw_insn
*vinsn
)
6205 if (find_vinsn_conflicts (vinsn
))
6207 xg_clear_vinsn (vinsn
);
6211 /* First, find a format that works. */
6212 if (vinsn
->format
== XTENSA_UNDEFINED
)
6213 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6215 if (xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
) > 1
6216 && produce_flix
== FLIX_NONE
)
6218 as_bad (_("The option \"--no-allow-flix\" prohibits multi-slot flix."));
6219 xg_clear_vinsn (vinsn
);
6223 if (vinsn
->format
== XTENSA_UNDEFINED
)
6225 as_where (&file_name
, &line
);
6226 as_bad_where (file_name
, line
,
6227 _("couldn't find a valid instruction format"));
6228 fprintf (stderr
, _(" ops were: "));
6229 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6230 fprintf (stderr
, _(" %s;"),
6231 xtensa_opcode_name (xtensa_default_isa
,
6232 vinsn
->slots
[i
].opcode
));
6233 fprintf (stderr
, _("\n"));
6234 xg_clear_vinsn (vinsn
);
6238 if (vinsn
->num_slots
6239 != xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
))
6241 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
6242 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
6243 xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
),
6245 xg_clear_vinsn (vinsn
);
6249 if (resources_conflict (vinsn
))
6251 as_where (&file_name
, &line
);
6252 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6253 fprintf (stderr
, " ops were: ");
6254 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6255 fprintf (stderr
, " %s;",
6256 xtensa_opcode_name (xtensa_default_isa
,
6257 vinsn
->slots
[i
].opcode
));
6258 fprintf (stderr
, "\n");
6259 xg_clear_vinsn (vinsn
);
6263 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6265 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
6267 symbolS
*lit_sym
= NULL
;
6269 bfd_boolean e
= FALSE
;
6270 bfd_boolean saved_density
= density_supported
;
6272 /* We don't want to narrow ops inside multi-slot bundles. */
6273 if (vinsn
->num_slots
> 1)
6274 density_supported
= FALSE
;
6276 istack_init (&slotstack
);
6277 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
6279 vinsn
->slots
[i
].opcode
=
6280 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6282 vinsn
->slots
[i
].ntok
= 0;
6285 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
6291 density_supported
= saved_density
;
6295 xg_clear_vinsn (vinsn
);
6299 for (j
= 0; j
< slotstack
.ninsn
; j
++)
6301 TInsn
*insn
= &slotstack
.insn
[j
];
6302 if (insn
->insn_type
== ITYPE_LITERAL
)
6304 gas_assert (lit_sym
== NULL
);
6305 lit_sym
= xg_assemble_literal (insn
);
6309 gas_assert (insn
->insn_type
== ITYPE_INSN
);
6311 xg_resolve_literals (insn
, lit_sym
);
6312 if (j
!= slotstack
.ninsn
- 1)
6313 emit_single_op (insn
);
6317 if (vinsn
->num_slots
> 1)
6319 if (opcode_fits_format_slot
6320 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6323 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6327 emit_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6328 if (vinsn
->format
== XTENSA_UNDEFINED
)
6329 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6331 vinsn
->slots
[i
].opcode
6332 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6335 vinsn
->slots
[i
].ntok
= 0;
6340 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6341 vinsn
->format
= XTENSA_UNDEFINED
;
6346 /* Now check resource conflicts on the modified bundle. */
6347 if (resources_conflict (vinsn
))
6349 as_where (&file_name
, &line
);
6350 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6351 fprintf (stderr
, " ops were: ");
6352 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6353 fprintf (stderr
, " %s;",
6354 xtensa_opcode_name (xtensa_default_isa
,
6355 vinsn
->slots
[i
].opcode
));
6356 fprintf (stderr
, "\n");
6357 xg_clear_vinsn (vinsn
);
6361 /* First, find a format that works. */
6362 if (vinsn
->format
== XTENSA_UNDEFINED
)
6363 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6365 xg_assemble_vliw_tokens (vinsn
);
6367 xg_clear_vinsn (vinsn
);
6371 /* Given an vliw instruction, what conflicts are there in register
6372 usage and in writes to states and queues?
6374 This function does two things:
6375 1. Reports an error when a vinsn contains illegal combinations
6376 of writes to registers states or queues.
6377 2. Marks individual tinsns as not relaxable if the combination
6378 contains antidependencies.
6380 Job 2 handles things like swap semantics in instructions that need
6381 to be relaxed. For example,
6385 normally would be relaxed to
6390 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6392 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6394 then we can't relax it into
6397 { add a0, a1, a0 ; add a2, a0, a4 ; }
6399 because the value of a0 is trashed before the second add can read it. */
6401 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6404 find_vinsn_conflicts (vliw_insn
*vinsn
)
6408 xtensa_isa isa
= xtensa_default_isa
;
6410 gas_assert (!past_xtensa_end
);
6412 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6414 TInsn
*op1
= &vinsn
->slots
[i
];
6415 if (op1
->is_specific_opcode
)
6416 op1
->keep_wide
= TRUE
;
6418 op1
->keep_wide
= FALSE
;
6421 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6423 TInsn
*op1
= &vinsn
->slots
[i
];
6425 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6428 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6432 TInsn
*op2
= &vinsn
->slots
[j
];
6433 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6434 switch (conflict_type
)
6437 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6438 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6439 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6442 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6443 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6444 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6447 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"),
6448 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6449 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6452 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"),
6453 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6454 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6457 /* Everything is OK. */
6460 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6461 || conflict_type
== 'a');
6468 as_bad (_("multiple branches or jumps in the same bundle"));
6476 /* Check how the state used by t1 and t2 relate.
6479 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6480 case B: no relationship between what is read and written (both could
6481 read the same reg though)
6482 case C: t1 writes a register t2 writes (a register conflict within a
6484 case D: t1 writes a state that t2 also writes
6485 case E: t1 writes a tie queue that t2 also writes
6486 case F: two volatile queue accesses
6490 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6492 xtensa_isa isa
= xtensa_default_isa
;
6493 xtensa_regfile t1_regfile
, t2_regfile
;
6495 int t1_base_reg
, t1_last_reg
;
6496 int t2_base_reg
, t2_last_reg
;
6497 char t1_inout
, t2_inout
;
6499 char conflict
= 'b';
6504 bfd_boolean t1_volatile
= FALSE
;
6505 bfd_boolean t2_volatile
= FALSE
;
6507 /* Check registers. */
6508 for (j
= 0; j
< t2
->ntok
; j
++)
6510 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6513 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6514 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6515 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6517 for (i
= 0; i
< t1
->ntok
; i
++)
6519 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6522 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6524 if (t1_regfile
!= t2_regfile
)
6527 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6528 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6530 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6531 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6533 if (t1_inout
== 'm' || t1_inout
== 'o'
6534 || t2_inout
== 'm' || t2_inout
== 'o')
6541 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6542 t1_last_reg
= (t1_base_reg
6543 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6545 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6547 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6549 if (t1_reg
!= t2_reg
)
6552 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6558 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6564 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6572 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6573 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6574 for (j
= 0; j
< t2_states
; j
++)
6576 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6577 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6578 for (i
= 0; i
< t1_states
; i
++)
6580 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6581 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6582 if (t1_so
!= t2_so
|| xtensa_state_is_shared_or (isa
, t1_so
) == 1)
6585 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6591 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6597 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6602 /* Check tieports. */
6603 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6604 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6605 for (j
= 0; j
< t2_interfaces
; j
++)
6607 xtensa_interface t2_int
6608 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6609 int t2_class
= xtensa_interface_class_id (isa
, t2_int
);
6611 t2_inout
= xtensa_interface_inout (isa
, t2_int
);
6612 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1)
6615 for (i
= 0; i
< t1_interfaces
; i
++)
6617 xtensa_interface t1_int
6618 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6619 int t1_class
= xtensa_interface_class_id (isa
, t1_int
);
6621 t1_inout
= xtensa_interface_inout (isa
, t1_int
);
6622 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1)
6625 if (t1_volatile
&& t2_volatile
&& (t1_class
== t2_class
))
6628 if (t1_int
!= t2_int
)
6631 if (t2_inout
== 'i' && t1_inout
== 'o')
6637 if (t1_inout
== 'i' && t2_inout
== 'o')
6643 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6652 static xtensa_format
6653 xg_find_narrowest_format (vliw_insn
*vinsn
)
6655 /* Right now we assume that the ops within the vinsn are properly
6656 ordered for the slots that the programmer wanted them in. In
6657 other words, we don't rearrange the ops in hopes of finding a
6658 better format. The scheduler handles that. */
6660 xtensa_isa isa
= xtensa_default_isa
;
6661 xtensa_format format
;
6662 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6664 if (vinsn
->num_slots
== 1)
6665 return xg_get_single_format (vinsn
->slots
[0].opcode
);
6667 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6670 xg_copy_vinsn (&v_copy
, vinsn
);
6671 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6675 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6677 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6679 v_copy
.slots
[slot
].opcode
=
6680 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6681 v_copy
.slots
[slot
].ntok
= 0;
6684 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6687 else if (v_copy
.num_slots
> 1)
6690 /* Try the widened version. */
6691 if (!v_copy
.slots
[slot
].keep_wide
6692 && !v_copy
.slots
[slot
].is_specific_opcode
6693 && xg_is_single_relaxable_insn (&v_copy
.slots
[slot
],
6695 && opcode_fits_format_slot (widened
.opcode
,
6698 v_copy
.slots
[slot
] = widened
;
6703 if (fit
== v_copy
.num_slots
)
6705 xg_copy_vinsn (vinsn
, &v_copy
);
6706 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6707 vinsn
->format
= format
;
6713 if (format
== xtensa_isa_num_formats (isa
))
6714 return XTENSA_UNDEFINED
;
6720 /* Return the additional space needed in a frag
6721 for possible relaxations of any ops in a VLIW insn.
6722 Also fill out the relaxations that might be required of
6723 each tinsn in the vinsn. */
6726 relaxation_requirements (vliw_insn
*vinsn
, bfd_boolean
*pfinish_frag
)
6728 bfd_boolean finish_frag
= FALSE
;
6729 int extra_space
= 0;
6732 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6734 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6735 if (!tinsn_has_symbolic_operands (tinsn
))
6737 /* A narrow instruction could be widened later to help
6738 alignment issues. */
6739 if (xg_is_single_relaxable_insn (tinsn
, 0, TRUE
)
6740 && !tinsn
->is_specific_opcode
6741 && vinsn
->num_slots
== 1)
6743 /* Difference in bytes between narrow and wide insns... */
6745 tinsn
->subtype
= RELAX_NARROW
;
6750 if (workaround_b_j_loop_end
6751 && tinsn
->opcode
== xtensa_jx_opcode
6752 && use_transform ())
6754 /* Add 2 of these. */
6755 extra_space
+= 3; /* for the nop size */
6756 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6759 /* Need to assemble it with space for the relocation. */
6760 if (xg_is_relaxable_insn (tinsn
, 0)
6761 && !tinsn
->is_specific_opcode
)
6763 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6764 int max_literal_size
=
6765 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6767 tinsn
->literal_space
= max_literal_size
;
6769 tinsn
->subtype
= RELAX_IMMED
;
6770 extra_space
+= max_size
;
6774 /* A fix record will be added for this instruction prior
6775 to relaxation, so make it end the frag. */
6780 *pfinish_frag
= finish_frag
;
6786 bundle_tinsn (TInsn
*tinsn
, vliw_insn
*vinsn
)
6788 xtensa_isa isa
= xtensa_default_isa
;
6789 int slot
, chosen_slot
;
6791 vinsn
->format
= xg_get_single_format (tinsn
->opcode
);
6792 gas_assert (vinsn
->format
!= XTENSA_UNDEFINED
);
6793 vinsn
->num_slots
= xtensa_format_num_slots (isa
, vinsn
->format
);
6795 chosen_slot
= xg_get_single_slot (tinsn
->opcode
);
6796 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6798 if (slot
== chosen_slot
)
6799 vinsn
->slots
[slot
] = *tinsn
;
6802 vinsn
->slots
[slot
].opcode
=
6803 xtensa_format_slot_nop_opcode (isa
, vinsn
->format
, slot
);
6804 vinsn
->slots
[slot
].ntok
= 0;
6805 vinsn
->slots
[slot
].insn_type
= ITYPE_INSN
;
6812 emit_single_op (TInsn
*orig_insn
)
6815 IStack istack
; /* put instructions into here */
6816 symbolS
*lit_sym
= NULL
;
6817 symbolS
*label_sym
= NULL
;
6819 istack_init (&istack
);
6821 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6822 Because the scheduling and bundling characteristics of movi and
6823 l32r or const16 are so different, we can do much better if we relax
6824 it prior to scheduling and bundling, rather than after. */
6825 if ((orig_insn
->opcode
== xtensa_movi_opcode
6826 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
6827 && !cur_vinsn
.inside_bundle
6828 && (orig_insn
->tok
[1].X_op
== O_symbol
6829 || orig_insn
->tok
[1].X_op
== O_pltrel
6830 || orig_insn
->tok
[1].X_op
== O_tlsfunc
6831 || orig_insn
->tok
[1].X_op
== O_tlsarg
6832 || orig_insn
->tok
[1].X_op
== O_tpoff
6833 || orig_insn
->tok
[1].X_op
== O_dtpoff
)
6834 && !orig_insn
->is_specific_opcode
&& use_transform ())
6835 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
6837 if (xg_expand_assembly_insn (&istack
, orig_insn
))
6840 for (i
= 0; i
< istack
.ninsn
; i
++)
6842 TInsn
*insn
= &istack
.insn
[i
];
6843 switch (insn
->insn_type
)
6846 gas_assert (lit_sym
== NULL
);
6847 lit_sym
= xg_assemble_literal (insn
);
6851 static int relaxed_sym_idx
= 0;
6852 char *label
= xmalloc (strlen (FAKE_LABEL_NAME
) + 12);
6853 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
6855 gas_assert (label_sym
== NULL
);
6856 label_sym
= symbol_find_or_make (label
);
6857 gas_assert (label_sym
);
6865 xg_resolve_literals (insn
, lit_sym
);
6867 xg_resolve_labels (insn
, label_sym
);
6869 bundle_tinsn (insn
, &v
);
6884 total_frag_text_expansion (fragS
*fragP
)
6887 int total_expansion
= 0;
6889 for (slot
= 0; slot
< config_max_slots
; slot
++)
6890 total_expansion
+= fragP
->tc_frag_data
.text_expansion
[slot
];
6892 return total_expansion
;
6896 /* Emit a vliw instruction to the current fragment. */
6899 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
6901 bfd_boolean finish_frag
;
6902 bfd_boolean is_jump
= FALSE
;
6903 bfd_boolean is_branch
= FALSE
;
6904 xtensa_isa isa
= xtensa_default_isa
;
6909 struct dwarf2_line_info debug_line
;
6910 bfd_boolean loc_directive_seen
= FALSE
;
6913 memset (&debug_line
, 0, sizeof (struct dwarf2_line_info
));
6915 if (generating_literals
)
6917 static int reported
= 0;
6919 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
6920 _("cannot assemble into a literal fragment"));
6927 if (frag_now_fix () != 0
6928 && (! frag_now
->tc_frag_data
.is_insn
6929 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6930 || !use_transform () != frag_now
->tc_frag_data
.is_no_transform
6931 || (directive_state
[directive_longcalls
]
6932 != frag_now
->tc_frag_data
.use_longcalls
)
6933 || (directive_state
[directive_absolute_literals
]
6934 != frag_now
->tc_frag_data
.use_absolute_literals
)))
6936 frag_wane (frag_now
);
6938 xtensa_set_frag_assembly_state (frag_now
);
6941 if (workaround_a0_b_retw
6942 && vinsn
->num_slots
== 1
6943 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
6944 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
6945 && use_transform ())
6947 has_a0_b_retw
= TRUE
;
6949 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
6950 After the first assembly pass we will check all of them and
6951 add a nop if needed. */
6952 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6953 frag_var (rs_machine_dependent
, 4, 4,
6954 RELAX_ADD_NOP_IF_A0_B_RETW
,
6955 frag_now
->fr_symbol
,
6956 frag_now
->fr_offset
,
6958 xtensa_set_frag_assembly_state (frag_now
);
6959 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6960 frag_var (rs_machine_dependent
, 4, 4,
6961 RELAX_ADD_NOP_IF_A0_B_RETW
,
6962 frag_now
->fr_symbol
,
6963 frag_now
->fr_offset
,
6965 xtensa_set_frag_assembly_state (frag_now
);
6968 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6970 tinsn
= &vinsn
->slots
[slot
];
6972 /* See if the instruction implies an aligned section. */
6973 if (xtensa_opcode_is_loop (isa
, tinsn
->opcode
) == 1)
6974 record_alignment (now_seg
, 2);
6976 /* Determine the best line number for debug info. */
6977 if ((tinsn
->loc_directive_seen
|| !loc_directive_seen
)
6978 && (tinsn
->debug_line
.filenum
!= debug_line
.filenum
6979 || tinsn
->debug_line
.line
< debug_line
.line
6980 || tinsn
->debug_line
.column
< debug_line
.column
))
6981 debug_line
= tinsn
->debug_line
;
6982 if (tinsn
->loc_directive_seen
)
6983 loc_directive_seen
= TRUE
;
6986 /* Special cases for instructions that force an alignment... */
6987 /* None of these opcodes are bundle-able. */
6988 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
6992 /* Remember the symbol that marks the end of the loop in the frag
6993 that marks the start of the loop. This way we can easily find
6994 the end of the loop at the beginning, without adding special code
6995 to mark the loop instructions themselves. */
6996 symbolS
*target_sym
= NULL
;
6997 if (vinsn
->slots
[0].tok
[1].X_op
== O_symbol
)
6998 target_sym
= vinsn
->slots
[0].tok
[1].X_add_symbol
;
7000 xtensa_set_frag_assembly_state (frag_now
);
7001 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7003 max_fill
= get_text_align_max_fill_size
7004 (get_text_align_power (xtensa_fetch_width
),
7005 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
7007 if (use_transform ())
7008 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
7009 RELAX_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
7011 frag_var (rs_machine_dependent
, 0, 0,
7012 RELAX_CHECK_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
7013 xtensa_set_frag_assembly_state (frag_now
);
7016 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
7017 && !vinsn
->slots
[0].is_specific_opcode
)
7019 xtensa_mark_literal_pool_location ();
7020 xtensa_move_labels (frag_now
, 0);
7021 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
7024 if (vinsn
->num_slots
== 1)
7026 if (workaround_a0_b_retw
&& use_transform ())
7027 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
7028 is_register_writer (&vinsn
->slots
[0], "a", 0));
7030 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
7031 is_bad_loopend_opcode (&vinsn
->slots
[0]));
7034 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
7036 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
7038 extra_space
= relaxation_requirements (vinsn
, &finish_frag
);
7040 /* vinsn_to_insnbuf will produce the error. */
7041 if (vinsn
->format
!= XTENSA_UNDEFINED
)
7043 f
= frag_more (insn_size
+ extra_space
);
7044 xtensa_set_frag_assembly_state (frag_now
);
7045 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7048 vinsn_to_insnbuf (vinsn
, f
, frag_now
, FALSE
);
7049 if (vinsn
->format
== XTENSA_UNDEFINED
)
7052 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, (unsigned char *) f
, 0);
7054 if (debug_type
== DEBUG_DWARF2
|| loc_directive_seen
)
7055 dwarf2_gen_line_info (frag_now_fix () - (insn_size
+ extra_space
),
7058 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
7060 tinsn
= &vinsn
->slots
[slot
];
7061 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
7062 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
7063 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
7064 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
7065 if (tinsn
->literal_space
!= 0)
7066 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
7067 frag_now
->tc_frag_data
.free_reg
[slot
] = tinsn
->extra_arg
;
7069 if (tinsn
->subtype
== RELAX_NARROW
)
7070 gas_assert (vinsn
->num_slots
== 1);
7071 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
7073 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
7076 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->offset
7077 || tinsn
->literal_frag
|| is_jump
|| is_branch
)
7081 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7082 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
7086 frag_variant (rs_machine_dependent
,
7087 extra_space
, extra_space
, RELAX_SLOTS
,
7088 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
7089 xtensa_set_frag_assembly_state (frag_now
);
7092 /* Special cases for loops:
7093 close_loop_end should be inserted AFTER short_loop.
7094 Make sure that CLOSE loops are processed BEFORE short_loops
7095 when converting them. */
7097 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
7098 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1
7099 && !vinsn
->slots
[0].is_specific_opcode
)
7101 if (workaround_short_loop
&& use_transform ())
7103 maybe_has_short_loop
= TRUE
;
7104 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7105 frag_var (rs_machine_dependent
, 4, 4,
7106 RELAX_ADD_NOP_IF_SHORT_LOOP
,
7107 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7108 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7109 frag_var (rs_machine_dependent
, 4, 4,
7110 RELAX_ADD_NOP_IF_SHORT_LOOP
,
7111 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7114 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
7115 loop at least 12 bytes away from another loop's end. */
7116 if (workaround_close_loop_end
&& use_transform ())
7118 maybe_has_close_loop_end
= TRUE
;
7119 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7120 frag_var (rs_machine_dependent
, 12, 12,
7121 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
7122 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7126 if (use_transform ())
7130 gas_assert (finish_frag
);
7131 frag_var (rs_machine_dependent
,
7132 xtensa_fetch_width
, xtensa_fetch_width
,
7134 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7135 xtensa_set_frag_assembly_state (frag_now
);
7137 else if (is_branch
&& do_align_targets ())
7139 gas_assert (finish_frag
);
7140 frag_var (rs_machine_dependent
,
7141 xtensa_fetch_width
, xtensa_fetch_width
,
7142 RELAX_MAYBE_UNREACHABLE
,
7143 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7144 xtensa_set_frag_assembly_state (frag_now
);
7145 frag_var (rs_machine_dependent
,
7147 RELAX_MAYBE_DESIRE_ALIGN
,
7148 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7149 xtensa_set_frag_assembly_state (frag_now
);
7153 /* Now, if the original opcode was a call... */
7154 if (do_align_targets ()
7155 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
7157 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
7158 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7159 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
7160 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7161 xtensa_set_frag_assembly_state (frag_now
);
7164 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7166 frag_wane (frag_now
);
7168 xtensa_set_frag_assembly_state (frag_now
);
7173 /* xtensa_end and helper functions. */
7175 static void xtensa_cleanup_align_frags (void);
7176 static void xtensa_fix_target_frags (void);
7177 static void xtensa_mark_narrow_branches (void);
7178 static void xtensa_mark_zcl_first_insns (void);
7179 static void xtensa_mark_difference_of_two_symbols (void);
7180 static void xtensa_fix_a0_b_retw_frags (void);
7181 static void xtensa_fix_b_j_loop_end_frags (void);
7182 static void xtensa_fix_close_loop_end_frags (void);
7183 static void xtensa_fix_short_loop_frags (void);
7184 static void xtensa_sanity_check (void);
7185 static void xtensa_add_config_info (void);
7190 directive_balance ();
7191 xtensa_flush_pending_output ();
7193 past_xtensa_end
= TRUE
;
7195 xtensa_move_literals ();
7197 xtensa_reorder_segments ();
7198 xtensa_cleanup_align_frags ();
7199 xtensa_fix_target_frags ();
7200 if (workaround_a0_b_retw
&& has_a0_b_retw
)
7201 xtensa_fix_a0_b_retw_frags ();
7202 if (workaround_b_j_loop_end
)
7203 xtensa_fix_b_j_loop_end_frags ();
7205 /* "close_loop_end" should be processed BEFORE "short_loop". */
7206 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
7207 xtensa_fix_close_loop_end_frags ();
7209 if (workaround_short_loop
&& maybe_has_short_loop
)
7210 xtensa_fix_short_loop_frags ();
7212 xtensa_mark_narrow_branches ();
7213 xtensa_mark_zcl_first_insns ();
7215 xtensa_sanity_check ();
7217 xtensa_add_config_info ();
7222 xtensa_cleanup_align_frags (void)
7227 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7228 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7231 /* Walk over all of the fragments in a subsection. */
7232 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7234 if ((fragP
->fr_type
== rs_align
7235 || fragP
->fr_type
== rs_align_code
7236 || (fragP
->fr_type
== rs_machine_dependent
7237 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
7238 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
7239 && fragP
->fr_fix
== 0)
7241 fragS
*next
= fragP
->fr_next
;
7244 && next
->fr_fix
== 0
7245 && next
->fr_type
== rs_machine_dependent
7246 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7249 next
= next
->fr_next
;
7252 /* If we don't widen branch targets, then they
7253 will be easier to align. */
7254 if (fragP
->tc_frag_data
.is_branch_target
7255 && fragP
->fr_opcode
== fragP
->fr_literal
7256 && fragP
->fr_type
== rs_machine_dependent
7257 && fragP
->fr_subtype
== RELAX_SLOTS
7258 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
7260 if (fragP
->fr_type
== rs_machine_dependent
7261 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
7262 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
7268 /* Re-process all of the fragments looking to convert all of the
7269 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
7270 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7271 Otherwise, convert to a .fill 0. */
7274 xtensa_fix_target_frags (void)
7279 /* When this routine is called, all of the subsections are still intact
7280 so we walk over subsections instead of sections. */
7281 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7282 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7286 /* Walk over all of the fragments in a subsection. */
7287 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7289 if (fragP
->fr_type
== rs_machine_dependent
7290 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7292 if (next_frag_is_branch_target (fragP
))
7293 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7302 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
7305 xtensa_mark_narrow_branches (void)
7310 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7311 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7314 /* Walk over all of the fragments in a subsection. */
7315 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7317 if (fragP
->fr_type
== rs_machine_dependent
7318 && fragP
->fr_subtype
== RELAX_SLOTS
7319 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7323 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7324 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
7326 if (vinsn
.num_slots
== 1
7327 && xtensa_opcode_is_branch (xtensa_default_isa
,
7328 vinsn
.slots
[0].opcode
) == 1
7329 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
7330 && is_narrow_branch_guaranteed_in_range (fragP
,
7333 fragP
->fr_subtype
= RELAX_SLOTS
;
7334 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
7335 fragP
->tc_frag_data
.is_aligning_branch
= 1;
7343 /* A branch is typically widened only when its target is out of
7344 range. However, we would like to widen them to align a subsequent
7345 branch target when possible.
7347 Because the branch relaxation code is so convoluted, the optimal solution
7348 (combining the two cases) is difficult to get right in all circumstances.
7349 We therefore go with an "almost as good" solution, where we only
7350 use for alignment narrow branches that definitely will not expand to a
7351 jump and a branch. These functions find and mark these cases. */
7353 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
7354 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7355 We start counting beginning with the frag after the 2-byte branch, so the
7356 maximum offset is (4 - 2) + 63 = 65. */
7357 #define MAX_IMMED6 65
7359 static offsetT
unrelaxed_frag_max_size (fragS
*);
7362 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
7364 const expressionS
*exp
= &tinsn
->tok
[1];
7365 symbolS
*symbolP
= exp
->X_add_symbol
;
7366 offsetT max_distance
= exp
->X_add_number
;
7369 if (exp
->X_op
!= O_symbol
)
7372 target_frag
= symbol_get_frag (symbolP
);
7374 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
7375 if (is_branch_jmp_to_next (tinsn
, fragP
))
7378 /* The branch doesn't branch over it's own frag,
7379 but over the subsequent ones. */
7380 fragP
= fragP
->fr_next
;
7381 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
7383 max_distance
+= unrelaxed_frag_max_size (fragP
);
7384 fragP
= fragP
->fr_next
;
7386 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
7393 xtensa_mark_zcl_first_insns (void)
7398 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7399 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7402 /* Walk over all of the fragments in a subsection. */
7403 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7405 if (fragP
->fr_type
== rs_machine_dependent
7406 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7407 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7409 /* Find the loop frag. */
7410 fragS
*loop_frag
= next_non_empty_frag (fragP
);
7411 /* Find the first insn frag. */
7412 fragS
*targ_frag
= next_non_empty_frag (loop_frag
);
7414 /* Handle a corner case that comes up in hardware
7415 diagnostics. The original assembly looks like this:
7418 <empty_frag>--not found by next_non_empty_frag
7421 Depending on the start address, the assembler may or
7422 may not change it to look something like this:
7425 nop--frag isn't empty anymore
7428 So set up to check the alignment of the nop if it
7430 while (loop_frag
!= targ_frag
)
7432 if (loop_frag
->fr_type
== rs_machine_dependent
7433 && (loop_frag
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7434 || loop_frag
->fr_subtype
7435 == RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7436 targ_frag
= loop_frag
;
7438 loop_frag
= loop_frag
->fr_next
;
7441 /* Of course, sometimes (mostly for toy test cases) a
7442 zero-cost loop instruction is the last in a section. */
7445 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
7446 /* Do not widen a frag that is the first instruction of a
7447 zero-cost loop. It makes that loop harder to align. */
7448 if (targ_frag
->fr_type
== rs_machine_dependent
7449 && targ_frag
->fr_subtype
== RELAX_SLOTS
7450 && (targ_frag
->tc_frag_data
.slot_subtypes
[0]
7453 if (targ_frag
->tc_frag_data
.is_aligning_branch
)
7454 targ_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
7457 frag_wane (targ_frag
);
7458 targ_frag
->tc_frag_data
.slot_subtypes
[0] = 0;
7462 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
7470 /* When a difference-of-symbols expression is encoded as a uleb128 or
7471 sleb128 value, the linker is unable to adjust that value to account for
7472 link-time relaxation. Mark all the code between such symbols so that
7473 its size cannot be changed by linker relaxation. */
7476 xtensa_mark_difference_of_two_symbols (void)
7480 for (expr_sym
= expr_symbols
; expr_sym
;
7481 expr_sym
= symbol_get_tc (expr_sym
)->next_expr_symbol
)
7483 expressionS
*exp
= symbol_get_value_expression (expr_sym
);
7485 if (exp
->X_op
== O_subtract
)
7487 symbolS
*left
= exp
->X_add_symbol
;
7488 symbolS
*right
= exp
->X_op_symbol
;
7490 /* Difference of two symbols not in the same section
7491 are handled with relocations in the linker. */
7492 if (S_GET_SEGMENT (left
) == S_GET_SEGMENT (right
))
7498 if (symbol_get_frag (left
)->fr_address
7499 <= symbol_get_frag (right
)->fr_address
)
7501 start
= symbol_get_frag (left
);
7502 end
= symbol_get_frag (right
);
7506 start
= symbol_get_frag (right
);
7507 end
= symbol_get_frag (left
);
7510 if (start
->tc_frag_data
.no_transform_end
!= NULL
)
7511 walk
= start
->tc_frag_data
.no_transform_end
;
7516 walk
->tc_frag_data
.is_no_transform
= 1;
7517 walk
= walk
->fr_next
;
7519 while (walk
&& walk
->fr_address
< end
->fr_address
);
7521 start
->tc_frag_data
.no_transform_end
= walk
;
7528 /* Re-process all of the fragments looking to convert all of the
7529 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7530 conditional branch or a retw/retw.n, convert this frag to one that
7531 will generate a NOP. In any case close it off with a .fill 0. */
7533 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
7536 xtensa_fix_a0_b_retw_frags (void)
7541 /* When this routine is called, all of the subsections are still intact
7542 so we walk over subsections instead of sections. */
7543 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7544 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7548 /* Walk over all of the fragments in a subsection. */
7549 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7551 if (fragP
->fr_type
== rs_machine_dependent
7552 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
7554 if (next_instrs_are_b_retw (fragP
))
7556 if (fragP
->tc_frag_data
.is_no_transform
)
7557 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7559 relax_frag_add_nop (fragP
);
7569 next_instrs_are_b_retw (fragS
*fragP
)
7571 xtensa_opcode opcode
;
7573 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
7574 static xtensa_insnbuf insnbuf
= NULL
;
7575 static xtensa_insnbuf slotbuf
= NULL
;
7576 xtensa_isa isa
= xtensa_default_isa
;
7579 bfd_boolean branch_seen
= FALSE
;
7583 insnbuf
= xtensa_insnbuf_alloc (isa
);
7584 slotbuf
= xtensa_insnbuf_alloc (isa
);
7587 if (next_fragP
== NULL
)
7590 /* Check for the conditional branch. */
7591 xtensa_insnbuf_from_chars
7592 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7593 fmt
= xtensa_format_decode (isa
, insnbuf
);
7594 if (fmt
== XTENSA_UNDEFINED
)
7597 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7599 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
7600 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
7602 branch_seen
= (branch_seen
7603 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
7609 offset
+= xtensa_format_length (isa
, fmt
);
7610 if (offset
== next_fragP
->fr_fix
)
7612 next_fragP
= next_non_empty_frag (next_fragP
);
7616 if (next_fragP
== NULL
)
7619 /* Check for the retw/retw.n. */
7620 xtensa_insnbuf_from_chars
7621 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7622 fmt
= xtensa_format_decode (isa
, insnbuf
);
7624 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
7625 have no problems. */
7626 if (fmt
== XTENSA_UNDEFINED
7627 || xtensa_format_num_slots (isa
, fmt
) != 1)
7630 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
7631 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
7633 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
7640 /* Re-process all of the fragments looking to convert all of the
7641 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
7642 loop end label, convert this frag to one that will generate a NOP.
7643 In any case close it off with a .fill 0. */
7645 static bfd_boolean
next_instr_is_loop_end (fragS
*);
7648 xtensa_fix_b_j_loop_end_frags (void)
7653 /* When this routine is called, all of the subsections are still intact
7654 so we walk over subsections instead of sections. */
7655 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7656 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7660 /* Walk over all of the fragments in a subsection. */
7661 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7663 if (fragP
->fr_type
== rs_machine_dependent
7664 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
7666 if (next_instr_is_loop_end (fragP
))
7668 if (fragP
->tc_frag_data
.is_no_transform
)
7669 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
7671 relax_frag_add_nop (fragP
);
7681 next_instr_is_loop_end (fragS
*fragP
)
7683 const fragS
*next_fragP
;
7685 if (next_frag_is_loop_target (fragP
))
7688 next_fragP
= next_non_empty_frag (fragP
);
7689 if (next_fragP
== NULL
)
7692 if (!next_frag_is_loop_target (next_fragP
))
7695 /* If the size is >= 3 then there is more than one instruction here.
7696 The hardware bug will not fire. */
7697 if (next_fragP
->fr_fix
> 3)
7704 /* Re-process all of the fragments looking to convert all of the
7705 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
7706 not MY loop's loop end within 12 bytes, add enough nops here to
7707 make it at least 12 bytes away. In any case close it off with a
7710 static offsetT min_bytes_to_other_loop_end
7711 (fragS
*, fragS
*, offsetT
);
7714 xtensa_fix_close_loop_end_frags (void)
7719 /* When this routine is called, all of the subsections are still intact
7720 so we walk over subsections instead of sections. */
7721 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7722 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7726 fragS
*current_target
= NULL
;
7728 /* Walk over all of the fragments in a subsection. */
7729 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7731 if (fragP
->fr_type
== rs_machine_dependent
7732 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7733 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7734 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7737 && fragP
->fr_type
== rs_machine_dependent
7738 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
7741 int bytes_added
= 0;
7743 #define REQUIRED_LOOP_DIVIDING_BYTES 12
7744 /* Max out at 12. */
7745 min_bytes
= min_bytes_to_other_loop_end
7746 (fragP
->fr_next
, current_target
, REQUIRED_LOOP_DIVIDING_BYTES
);
7748 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
7750 if (fragP
->tc_frag_data
.is_no_transform
)
7751 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
7754 while (min_bytes
+ bytes_added
7755 < REQUIRED_LOOP_DIVIDING_BYTES
)
7759 if (fragP
->fr_var
< length
)
7760 as_fatal (_("fr_var %lu < length %d"),
7761 (long) fragP
->fr_var
, length
);
7764 assemble_nop (length
,
7765 fragP
->fr_literal
+ fragP
->fr_fix
);
7766 fragP
->fr_fix
+= length
;
7767 fragP
->fr_var
-= length
;
7769 bytes_added
+= length
;
7775 gas_assert (fragP
->fr_type
!= rs_machine_dependent
7776 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
7782 static offsetT
unrelaxed_frag_min_size (fragS
*);
7785 min_bytes_to_other_loop_end (fragS
*fragP
,
7786 fragS
*current_target
,
7790 fragS
*current_fragP
;
7792 for (current_fragP
= fragP
;
7794 current_fragP
= current_fragP
->fr_next
)
7796 if (current_fragP
->tc_frag_data
.is_loop_target
7797 && current_fragP
!= current_target
)
7800 offset
+= unrelaxed_frag_min_size (current_fragP
);
7802 if (offset
>= max_size
)
7810 unrelaxed_frag_min_size (fragS
*fragP
)
7812 offsetT size
= fragP
->fr_fix
;
7814 /* Add fill size. */
7815 if (fragP
->fr_type
== rs_fill
)
7816 size
+= fragP
->fr_offset
;
7823 unrelaxed_frag_max_size (fragS
*fragP
)
7825 offsetT size
= fragP
->fr_fix
;
7826 switch (fragP
->fr_type
)
7829 /* Empty frags created by the obstack allocation scheme
7830 end up with type 0. */
7835 size
+= fragP
->fr_offset
;
7843 /* No further adjustments needed. */
7845 case rs_machine_dependent
:
7846 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
7847 size
+= fragP
->fr_var
;
7850 /* We had darn well better know how big it is. */
7859 /* Re-process all of the fragments looking to convert all
7860 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
7863 1) the instruction size count to the loop end label
7864 is too short (<= 2 instructions),
7865 2) loop has a jump or branch in it
7868 1) workaround_all_short_loops is TRUE
7869 2) The generating loop was a 'loopgtz' or 'loopnez'
7870 3) the instruction size count to the loop end label is too short
7872 then convert this frag (and maybe the next one) to generate a NOP.
7873 In any case close it off with a .fill 0. */
7875 static int count_insns_to_loop_end (fragS
*, bfd_boolean
, int);
7876 static bfd_boolean
branch_before_loop_end (fragS
*);
7879 xtensa_fix_short_loop_frags (void)
7884 /* When this routine is called, all of the subsections are still intact
7885 so we walk over subsections instead of sections. */
7886 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7887 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7890 fragS
*current_target
= NULL
;
7891 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
7893 /* Walk over all of the fragments in a subsection. */
7894 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7896 if (fragP
->fr_type
== rs_machine_dependent
7897 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7898 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7901 fragS
*loop_frag
= next_non_empty_frag (fragP
);
7902 tinsn_from_chars (&t_insn
, loop_frag
->fr_opcode
, 0);
7903 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7904 current_opcode
= t_insn
.opcode
;
7905 gas_assert (xtensa_opcode_is_loop (xtensa_default_isa
,
7906 current_opcode
) == 1);
7909 if (fragP
->fr_type
== rs_machine_dependent
7910 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7912 if (count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3) < 3
7913 && (branch_before_loop_end (fragP
->fr_next
)
7914 || (workaround_all_short_loops
7915 && current_opcode
!= XTENSA_UNDEFINED
7916 && current_opcode
!= xtensa_loop_opcode
)))
7918 if (fragP
->tc_frag_data
.is_no_transform
)
7919 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
7921 relax_frag_add_nop (fragP
);
7930 static int unrelaxed_frag_min_insn_count (fragS
*);
7933 count_insns_to_loop_end (fragS
*base_fragP
,
7934 bfd_boolean count_relax_add
,
7937 fragS
*fragP
= NULL
;
7942 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
7944 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
7945 if (insn_count
>= max_count
)
7948 if (count_relax_add
)
7950 if (fragP
->fr_type
== rs_machine_dependent
7951 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7953 /* In order to add the appropriate number of
7954 NOPs, we count an instruction for downstream
7957 if (insn_count
>= max_count
)
7967 unrelaxed_frag_min_insn_count (fragS
*fragP
)
7969 xtensa_isa isa
= xtensa_default_isa
;
7970 static xtensa_insnbuf insnbuf
= NULL
;
7974 if (!fragP
->tc_frag_data
.is_insn
)
7978 insnbuf
= xtensa_insnbuf_alloc (isa
);
7980 /* Decode the fixed instructions. */
7981 while (offset
< fragP
->fr_fix
)
7985 xtensa_insnbuf_from_chars
7986 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7987 fmt
= xtensa_format_decode (isa
, insnbuf
);
7989 if (fmt
== XTENSA_UNDEFINED
)
7991 as_fatal (_("undecodable instruction in instruction frag"));
7994 offset
+= xtensa_format_length (isa
, fmt
);
8002 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
8005 branch_before_loop_end (fragS
*base_fragP
)
8009 for (fragP
= base_fragP
;
8010 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
8011 fragP
= fragP
->fr_next
)
8013 if (unrelaxed_frag_has_b_j (fragP
))
8021 unrelaxed_frag_has_b_j (fragS
*fragP
)
8023 static xtensa_insnbuf insnbuf
= NULL
;
8024 xtensa_isa isa
= xtensa_default_isa
;
8027 if (!fragP
->tc_frag_data
.is_insn
)
8031 insnbuf
= xtensa_insnbuf_alloc (isa
);
8033 /* Decode the fixed instructions. */
8034 while (offset
< fragP
->fr_fix
)
8039 xtensa_insnbuf_from_chars
8040 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
8041 fmt
= xtensa_format_decode (isa
, insnbuf
);
8042 if (fmt
== XTENSA_UNDEFINED
)
8045 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
8047 xtensa_opcode opcode
=
8048 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
8049 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
8050 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
8053 offset
+= xtensa_format_length (isa
, fmt
);
8059 /* Checks to be made after initial assembly but before relaxation. */
8061 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
8062 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
8065 xtensa_sanity_check (void)
8072 as_where (&file_name
, &line
);
8073 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8074 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8078 /* Walk over all of the fragments in a subsection. */
8079 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8081 if (fragP
->fr_type
== rs_machine_dependent
8082 && fragP
->fr_subtype
== RELAX_SLOTS
8083 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
8085 static xtensa_insnbuf insnbuf
= NULL
;
8088 if (fragP
->fr_opcode
!= NULL
)
8091 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
8092 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
8093 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
8095 if (xtensa_opcode_is_loop (xtensa_default_isa
,
8096 t_insn
.opcode
) == 1)
8098 if (is_empty_loop (&t_insn
, fragP
))
8100 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8101 as_bad (_("invalid empty loop"));
8103 if (!is_local_forward_loop (&t_insn
, fragP
))
8105 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8106 as_bad (_("loop target does not follow "
8107 "loop instruction in section"));
8114 new_logical_line (file_name
, line
);
8118 #define LOOP_IMMED_OPN 1
8120 /* Return TRUE if the loop target is the next non-zero fragment. */
8123 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
8125 const expressionS
*exp
;
8129 if (insn
->insn_type
!= ITYPE_INSN
)
8132 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
8135 if (insn
->ntok
<= LOOP_IMMED_OPN
)
8138 exp
= &insn
->tok
[LOOP_IMMED_OPN
];
8140 if (exp
->X_op
!= O_symbol
)
8143 symbolP
= exp
->X_add_symbol
;
8147 if (symbol_get_frag (symbolP
) == NULL
)
8150 if (S_GET_VALUE (symbolP
) != 0)
8153 /* Walk through the zero-size fragments from this one. If we find
8154 the target fragment, then this is a zero-size loop. */
8156 for (next_fragP
= fragP
->fr_next
;
8158 next_fragP
= next_fragP
->fr_next
)
8160 if (next_fragP
== symbol_get_frag (symbolP
))
8162 if (next_fragP
->fr_fix
!= 0)
8170 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
8172 const expressionS
*exp
;
8176 if (insn
->insn_type
!= ITYPE_INSN
)
8179 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
8182 if (insn
->ntok
<= LOOP_IMMED_OPN
)
8185 exp
= &insn
->tok
[LOOP_IMMED_OPN
];
8187 if (exp
->X_op
!= O_symbol
)
8190 symbolP
= exp
->X_add_symbol
;
8194 if (symbol_get_frag (symbolP
) == NULL
)
8197 /* Walk through fragments until we find the target.
8198 If we do not find the target, then this is an invalid loop. */
8200 for (next_fragP
= fragP
->fr_next
;
8202 next_fragP
= next_fragP
->fr_next
)
8204 if (next_fragP
== symbol_get_frag (symbolP
))
8212 #define XTINFO_NAME "Xtensa_Info"
8213 #define XTINFO_NAMESZ 12
8214 #define XTINFO_TYPE 1
8217 xtensa_add_config_info (void)
8223 info_sec
= subseg_new (".xtensa.info", 0);
8224 bfd_set_section_flags (stdoutput
, info_sec
, SEC_HAS_CONTENTS
| SEC_READONLY
);
8226 data
= xmalloc (100);
8227 sprintf (data
, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n",
8228 XSHAL_USE_ABSOLUTE_LITERALS
, XSHAL_ABI
);
8229 sz
= strlen (data
) + 1;
8231 /* Add enough null terminators to pad to a word boundary. */
8234 while ((sz
& 3) != 0);
8236 /* Follow the standard note section layout:
8237 First write the length of the name string. */
8239 md_number_to_chars (p
, (valueT
) XTINFO_NAMESZ
, 4);
8241 /* Next comes the length of the "descriptor", i.e., the actual data. */
8243 md_number_to_chars (p
, (valueT
) sz
, 4);
8245 /* Write the note type. */
8247 md_number_to_chars (p
, (valueT
) XTINFO_TYPE
, 4);
8249 /* Write the name field. */
8250 p
= frag_more (XTINFO_NAMESZ
);
8251 memcpy (p
, XTINFO_NAME
, XTINFO_NAMESZ
);
8253 /* Finally, write the descriptor. */
8255 memcpy (p
, data
, sz
);
8261 /* Alignment Functions. */
8264 get_text_align_power (unsigned target_size
)
8266 if (target_size
<= 4)
8269 if (target_size
<= 8)
8272 if (target_size
<= 16)
8275 if (target_size
<= 32)
8278 if (target_size
<= 64)
8281 if (target_size
<= 128)
8284 if (target_size
<= 256)
8287 if (target_size
<= 512)
8290 if (target_size
<= 1024)
8299 get_text_align_max_fill_size (int align_pow
,
8300 bfd_boolean use_nops
,
8301 bfd_boolean use_no_density
)
8304 return (1 << align_pow
);
8306 return 3 * (1 << align_pow
);
8308 return 1 + (1 << align_pow
);
8312 /* Calculate the minimum bytes of fill needed at "address" to align a
8313 target instruction of size "target_size" so that it does not cross a
8314 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE,
8315 the fill can be an arbitrary number of bytes. Otherwise, the space must
8316 be filled by NOP instructions. */
8319 get_text_align_fill_size (addressT address
,
8322 bfd_boolean use_nops
,
8323 bfd_boolean use_no_density
)
8325 addressT alignment
, fill
, fill_limit
, fill_step
;
8326 bfd_boolean skip_one
= FALSE
;
8328 alignment
= (1 << align_pow
);
8329 gas_assert (target_size
> 0 && alignment
>= (addressT
) target_size
);
8333 fill_limit
= alignment
;
8336 else if (!use_no_density
)
8338 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */
8339 fill_limit
= alignment
* 2;
8345 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */
8346 fill_limit
= alignment
* 3;
8350 /* Try all fill sizes until finding one that works. */
8351 for (fill
= 0; fill
< fill_limit
; fill
+= fill_step
)
8353 if (skip_one
&& fill
== 1)
8355 if ((address
+ fill
) >> align_pow
8356 == (address
+ fill
+ target_size
- 1) >> align_pow
)
8365 branch_align_power (segT sec
)
8367 /* If the Xtensa processor has a fetch width of X, and
8368 the section is aligned to at least that boundary, then a branch
8369 target need only fit within that aligned block of memory to avoid
8370 a stall. Otherwise, try to fit branch targets within 4-byte
8371 aligned blocks (which may be insufficient, e.g., if the section
8372 has no alignment, but it's good enough). */
8373 int fetch_align
= get_text_align_power(xtensa_fetch_width
);
8374 int sec_align
= get_recorded_alignment (sec
);
8376 if (sec_align
>= fetch_align
)
8383 /* This will assert if it is not possible. */
8386 get_text_align_nop_count (offsetT fill_size
, bfd_boolean use_no_density
)
8392 gas_assert (fill_size
% 3 == 0);
8393 return (fill_size
/ 3);
8396 gas_assert (fill_size
!= 1); /* Bad argument. */
8398 while (fill_size
> 1)
8401 if (fill_size
== 2 || fill_size
== 4)
8403 fill_size
-= insn_size
;
8406 gas_assert (fill_size
!= 1); /* Bad algorithm. */
8412 get_text_align_nth_nop_size (offsetT fill_size
,
8414 bfd_boolean use_no_density
)
8421 gas_assert (fill_size
!= 1); /* Bad argument. */
8423 while (fill_size
> 1)
8426 if (fill_size
== 2 || fill_size
== 4)
8428 fill_size
-= insn_size
;
8438 /* For the given fragment, find the appropriate address
8439 for it to begin at if we are using NOPs to align it. */
8442 get_noop_aligned_address (fragS
*fragP
, addressT address
)
8444 /* The rule is: get next fragment's FIRST instruction. Find
8445 the smallest number of bytes that need to be added to
8446 ensure that the next fragment's FIRST instruction will fit
8449 E.G., 2 bytes : 0, 1, 2 mod 4
8452 If the FIRST instruction MIGHT be relaxed,
8453 assume that it will become a 3-byte instruction.
8455 Note again here that LOOP instructions are not bundleable,
8456 and this relaxation only applies to LOOP opcodes. */
8459 int first_insn_size
;
8461 addressT pre_opcode_bytes
;
8464 xtensa_opcode opcode
;
8465 bfd_boolean is_loop
;
8467 gas_assert (fragP
->fr_type
== rs_machine_dependent
);
8468 gas_assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
8470 /* Find the loop frag. */
8471 first_insn
= next_non_empty_frag (fragP
);
8472 /* Now find the first insn frag. */
8473 first_insn
= next_non_empty_frag (first_insn
);
8475 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
8476 gas_assert (is_loop
);
8477 loop_insn_size
= xg_get_single_size (opcode
);
8479 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
8480 pre_opcode_bytes
+= loop_insn_size
;
8482 /* For loops, the alignment depends on the size of the
8483 instruction following the loop, not the LOOP instruction. */
8485 if (first_insn
== NULL
)
8486 first_insn_size
= xtensa_fetch_width
;
8488 first_insn_size
= get_loop_align_size (frag_format_size (first_insn
));
8490 /* If it was 8, then we'll need a larger alignment for the section. */
8491 align_power
= get_text_align_power (first_insn_size
);
8492 record_alignment (now_seg
, align_power
);
8494 fill_size
= get_text_align_fill_size
8495 (address
+ pre_opcode_bytes
, align_power
, first_insn_size
, TRUE
,
8496 fragP
->tc_frag_data
.is_no_density
);
8498 return address
+ fill_size
;
8502 /* 3 mechanisms for relaxing an alignment:
8504 Align to a power of 2.
8505 Align so the next fragment's instruction does not cross a word boundary.
8506 Align the current instruction so that if the next instruction
8507 were 3 bytes, it would not cross a word boundary.
8511 zeros - This is easy; always insert zeros.
8512 nops - 3-byte and 2-byte instructions
8516 >=5 : 3-byte instruction + fn (n-3)
8517 widening - widen previous instructions. */
8520 get_aligned_diff (fragS
*fragP
, addressT address
, offsetT
*max_diff
)
8522 addressT target_address
, loop_insn_offset
;
8524 xtensa_opcode loop_opcode
;
8525 bfd_boolean is_loop
;
8528 offsetT branch_align
;
8531 gas_assert (fragP
->fr_type
== rs_machine_dependent
);
8532 switch (fragP
->fr_subtype
)
8534 case RELAX_DESIRE_ALIGN
:
8535 target_size
= next_frag_format_size (fragP
);
8536 if (target_size
== XTENSA_UNDEFINED
)
8538 align_power
= branch_align_power (now_seg
);
8539 branch_align
= 1 << align_power
;
8540 /* Don't count on the section alignment being as large as the target. */
8541 if (target_size
> branch_align
)
8542 target_size
= branch_align
;
8543 opt_diff
= get_text_align_fill_size (address
, align_power
,
8544 target_size
, FALSE
, FALSE
);
8546 *max_diff
= (opt_diff
+ branch_align
8547 - (target_size
+ ((address
+ opt_diff
) % branch_align
)));
8548 gas_assert (*max_diff
>= opt_diff
);
8551 case RELAX_ALIGN_NEXT_OPCODE
:
8552 /* The next non-empty frag after this one holds the LOOP instruction
8553 that needs to be aligned. The required alignment depends on the
8554 size of the next non-empty frag after the loop frag, i.e., the
8555 first instruction in the loop. */
8556 loop_frag
= next_non_empty_frag (fragP
);
8557 target_size
= get_loop_align_size (next_frag_format_size (loop_frag
));
8558 loop_insn_offset
= 0;
8559 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
8560 gas_assert (is_loop
);
8562 /* If the loop has been expanded then the LOOP instruction
8563 could be at an offset from this fragment. */
8564 if (loop_frag
->tc_frag_data
.slot_subtypes
[0] != RELAX_IMMED
)
8565 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
8567 /* In an ideal world, which is what we are shooting for here,
8568 we wouldn't need to use any NOPs immediately prior to the
8569 LOOP instruction. If this approach fails, relax_frag_loop_align
8570 will call get_noop_aligned_address. */
8572 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
8573 align_power
= get_text_align_power (target_size
);
8574 opt_diff
= get_text_align_fill_size (target_address
, align_power
,
8575 target_size
, FALSE
, FALSE
);
8577 *max_diff
= xtensa_fetch_width
8578 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
8579 - target_size
+ opt_diff
;
8580 gas_assert (*max_diff
>= opt_diff
);
8591 /* md_relax_frag Hook and Helper Functions. */
8593 static long relax_frag_loop_align (fragS
*, long);
8594 static long relax_frag_for_align (fragS
*, long);
8595 static long relax_frag_immed
8596 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
8599 /* Return the number of bytes added to this fragment, given that the
8600 input has been stretched already by "stretch". */
8603 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
8605 xtensa_isa isa
= xtensa_default_isa
;
8606 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
8607 long new_stretch
= 0;
8611 static xtensa_insnbuf vbuf
= NULL
;
8612 int slot
, num_slots
;
8615 as_where (&file_name
, &line
);
8616 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8618 fragP
->tc_frag_data
.unreported_expansion
= 0;
8620 switch (fragP
->fr_subtype
)
8622 case RELAX_ALIGN_NEXT_OPCODE
:
8623 /* Always convert. */
8624 if (fragP
->tc_frag_data
.relax_seen
)
8625 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
8628 case RELAX_LOOP_END
:
8632 case RELAX_LOOP_END_ADD_NOP
:
8633 /* Add a NOP and switch to .fill 0. */
8634 new_stretch
= relax_frag_add_nop (fragP
);
8638 case RELAX_DESIRE_ALIGN
:
8639 /* Do nothing. The narrowing before this frag will either align
8644 case RELAX_LITERAL_FINAL
:
8647 case RELAX_LITERAL_NR
:
8649 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
8650 gas_assert (unreported
== lit_size
);
8651 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
8652 fragP
->fr_var
-= lit_size
;
8653 fragP
->fr_fix
+= lit_size
;
8659 vbuf
= xtensa_insnbuf_alloc (isa
);
8661 xtensa_insnbuf_from_chars
8662 (isa
, vbuf
, (unsigned char *) fragP
->fr_opcode
, 0);
8663 fmt
= xtensa_format_decode (isa
, vbuf
);
8664 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8666 for (slot
= 0; slot
< num_slots
; slot
++)
8668 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
8671 if (fragP
->tc_frag_data
.relax_seen
)
8672 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8676 case RELAX_IMMED_STEP1
:
8677 case RELAX_IMMED_STEP2
:
8678 case RELAX_IMMED_STEP3
:
8679 /* Place the immediate. */
8680 new_stretch
+= relax_frag_immed
8681 (now_seg
, fragP
, stretch
,
8682 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8683 fmt
, slot
, stretched_p
, FALSE
);
8687 /* This is OK; see the note in xg_assemble_vliw_tokens. */
8693 case RELAX_LITERAL_POOL_BEGIN
:
8694 case RELAX_LITERAL_POOL_END
:
8695 case RELAX_MAYBE_UNREACHABLE
:
8696 case RELAX_MAYBE_DESIRE_ALIGN
:
8697 /* No relaxation required. */
8700 case RELAX_FILL_NOP
:
8701 case RELAX_UNREACHABLE
:
8702 if (fragP
->tc_frag_data
.relax_seen
)
8703 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8707 as_bad (_("bad relaxation state"));
8710 /* Tell gas we need another relaxation pass. */
8711 if (! fragP
->tc_frag_data
.relax_seen
)
8713 fragP
->tc_frag_data
.relax_seen
= TRUE
;
8717 new_logical_line (file_name
, line
);
8723 relax_frag_loop_align (fragS
*fragP
, long stretch
)
8725 addressT old_address
, old_next_address
, old_size
;
8726 addressT new_address
, new_next_address
, new_size
;
8729 /* All the frags with relax_frag_for_alignment prior to this one in the
8730 section have been done, hopefully eliminating the need for a NOP here.
8731 But, this will put it in if necessary. */
8733 /* Calculate the old address of this fragment and the next fragment. */
8734 old_address
= fragP
->fr_address
- stretch
;
8735 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
8736 fragP
->tc_frag_data
.text_expansion
[0]);
8737 old_size
= old_next_address
- old_address
;
8739 /* Calculate the new address of this fragment and the next fragment. */
8740 new_address
= fragP
->fr_address
;
8742 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
8743 new_size
= new_next_address
- new_address
;
8745 growth
= new_size
- old_size
;
8747 /* Fix up the text_expansion field and return the new growth. */
8748 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
8753 /* Add a NOP instruction. */
8756 relax_frag_add_nop (fragS
*fragP
)
8758 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
8759 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
8760 assemble_nop (length
, nop_buf
);
8761 fragP
->tc_frag_data
.is_insn
= TRUE
;
8763 if (fragP
->fr_var
< length
)
8765 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP
->fr_var
, length
);
8769 fragP
->fr_fix
+= length
;
8770 fragP
->fr_var
-= length
;
8775 static long future_alignment_required (fragS
*, long);
8778 relax_frag_for_align (fragS
*fragP
, long stretch
)
8780 /* Overview of the relaxation procedure for alignment:
8781 We can widen with NOPs or by widening instructions or by filling
8782 bytes after jump instructions. Find the opportune places and widen
8783 them if necessary. */
8788 gas_assert (fragP
->fr_subtype
== RELAX_FILL_NOP
8789 || fragP
->fr_subtype
== RELAX_UNREACHABLE
8790 || (fragP
->fr_subtype
== RELAX_SLOTS
8791 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
8793 stretch_me
= future_alignment_required (fragP
, stretch
);
8794 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
8800 /* We expanded on a previous pass. Can we shrink now? */
8801 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
8802 if (shrink
<= stretch
&& stretch
> 0)
8804 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8810 /* Below here, diff > 0. */
8811 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8817 /* Return the address of the next frag that should be aligned.
8819 By "address" we mean the address it _would_ be at if there
8820 is no action taken to align it between here and the target frag.
8821 In other words, if no narrows and no fill nops are used between
8822 here and the frag to align, _even_if_ some of the frags we use
8823 to align targets have already expanded on a previous relaxation
8826 Also, count each frag that may be used to help align the target.
8828 Return 0 if there are no frags left in the chain that need to be
8832 find_address_of_next_align_frag (fragS
**fragPP
,
8836 bfd_boolean
*paddable
)
8838 fragS
*fragP
= *fragPP
;
8839 addressT address
= fragP
->fr_address
;
8841 /* Do not reset the counts to 0. */
8845 /* Limit this to a small search. */
8846 if (*widens
>= (int) xtensa_fetch_width
)
8851 address
+= fragP
->fr_fix
;
8853 if (fragP
->fr_type
== rs_fill
)
8854 address
+= fragP
->fr_offset
* fragP
->fr_var
;
8855 else if (fragP
->fr_type
== rs_machine_dependent
)
8857 switch (fragP
->fr_subtype
)
8859 case RELAX_UNREACHABLE
:
8863 case RELAX_FILL_NOP
:
8865 if (!fragP
->tc_frag_data
.is_no_density
)
8870 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8875 address
+= total_frag_text_expansion (fragP
);;
8879 address
+= fragP
->tc_frag_data
.text_expansion
[0];
8882 case RELAX_ALIGN_NEXT_OPCODE
:
8883 case RELAX_DESIRE_ALIGN
:
8887 case RELAX_MAYBE_UNREACHABLE
:
8888 case RELAX_MAYBE_DESIRE_ALIGN
:
8893 /* Just punt if we don't know the type. */
8900 /* Just punt if we don't know the type. */
8904 fragP
= fragP
->fr_next
;
8912 static long bytes_to_stretch (fragS
*, int, int, int, int);
8915 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
8917 fragS
*this_frag
= fragP
;
8921 int narrow_nops
= 0;
8922 bfd_boolean paddable
= FALSE
;
8923 offsetT local_opt_diff
;
8926 int stretch_amount
= 0;
8927 int local_stretch_amount
;
8928 int global_stretch_amount
;
8930 address
= find_address_of_next_align_frag
8931 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
8935 if (this_frag
->tc_frag_data
.is_aligning_branch
)
8936 this_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
8938 frag_wane (this_frag
);
8942 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
8943 opt_diff
= local_opt_diff
;
8944 gas_assert (opt_diff
>= 0);
8945 gas_assert (max_diff
>= opt_diff
);
8950 fragP
= fragP
->fr_next
;
8952 while (fragP
&& opt_diff
< max_diff
&& address
)
8954 /* We only use these to determine if we can exit early
8955 because there will be plenty of ways to align future
8957 int glob_widens
= 0;
8960 bfd_boolean glob_pad
= 0;
8961 address
= find_address_of_next_align_frag
8962 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
8963 /* If there is a padable portion, then skip. */
8964 if (glob_pad
|| glob_widens
>= (1 << branch_align_power (now_seg
)))
8969 offsetT next_m_diff
;
8970 offsetT next_o_diff
;
8972 /* Downrange frags haven't had stretch added to them yet. */
8975 /* The address also includes any text expansion from this
8976 frag in a previous pass, but we don't want that. */
8977 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
8979 /* Assume we are going to move at least opt_diff. In
8980 reality, we might not be able to, but assuming that
8981 we will helps catch cases where moving opt_diff pushes
8982 the next target from aligned to unaligned. */
8983 address
+= opt_diff
;
8985 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
8987 /* Now cleanup for the adjustments to address. */
8988 next_o_diff
+= opt_diff
;
8989 next_m_diff
+= opt_diff
;
8990 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
8991 opt_diff
= next_o_diff
;
8992 if (next_m_diff
< max_diff
)
8993 max_diff
= next_m_diff
;
8994 fragP
= fragP
->fr_next
;
8998 /* If there are enough wideners in between, do it. */
9001 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
9003 gas_assert (opt_diff
<= (signed) xtensa_fetch_width
);
9008 local_stretch_amount
9009 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
9010 num_widens
, local_opt_diff
);
9011 global_stretch_amount
9012 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
9013 num_widens
, opt_diff
);
9014 /* If the condition below is true, then the frag couldn't
9015 stretch the correct amount for the global case, so we just
9016 optimize locally. We'll rely on the subsequent frags to get
9017 the correct alignment in the global case. */
9018 if (global_stretch_amount
< local_stretch_amount
)
9019 stretch_amount
= local_stretch_amount
;
9021 stretch_amount
= global_stretch_amount
;
9023 if (this_frag
->fr_subtype
== RELAX_SLOTS
9024 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
9025 gas_assert (stretch_amount
<= 1);
9026 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9028 if (this_frag
->tc_frag_data
.is_no_density
)
9029 gas_assert (stretch_amount
== 3 || stretch_amount
== 0);
9031 gas_assert (stretch_amount
<= 3);
9034 return stretch_amount
;
9038 /* The idea: widen everything you can to get a target or loop aligned,
9039 then start using NOPs.
9041 wide_nops = the number of wide NOPs available for aligning
9042 narrow_nops = the number of narrow NOPs available for aligning
9043 (a subset of wide_nops)
9044 widens = the number of narrow instructions that should be widened
9049 bytes_to_stretch (fragS
*this_frag
,
9058 int bytes_short
= desired_diff
- num_widens
;
9060 gas_assert (desired_diff
>= 0
9061 && desired_diff
< (signed) xtensa_fetch_width
);
9062 if (desired_diff
== 0)
9065 gas_assert (wide_nops
> 0 || num_widens
> 0);
9067 /* Always prefer widening to NOP-filling. */
9068 if (bytes_short
< 0)
9070 /* There are enough RELAX_NARROW frags after this one
9071 to align the target without widening this frag in any way. */
9075 if (bytes_short
== 0)
9077 /* Widen every narrow between here and the align target
9078 and the align target will be properly aligned. */
9079 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9085 /* From here we will need at least one NOP to get an alignment.
9086 However, we may not be able to align at all, in which case,
9088 nops_needed
= desired_diff
/ 3;
9090 /* If there aren't enough nops, don't widen. */
9091 if (nops_needed
> wide_nops
)
9094 /* First try it with all wide nops. */
9095 nop_bytes
= nops_needed
* 3;
9096 extra_bytes
= desired_diff
- nop_bytes
;
9098 if (nop_bytes
+ num_widens
>= desired_diff
)
9100 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9102 else if (num_widens
== extra_bytes
)
9107 /* Add a narrow nop. */
9111 if (narrow_nops
== 0 || nops_needed
> wide_nops
)
9114 if (nop_bytes
+ num_widens
>= desired_diff
&& extra_bytes
>= 0)
9116 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9117 return !this_frag
->tc_frag_data
.is_no_density
? 2 : 3;
9118 else if (num_widens
== extra_bytes
)
9123 /* Replace a wide nop with a narrow nop--we can get here if
9124 extra_bytes was negative in the previous conditional. */
9125 if (narrow_nops
== 1)
9129 if (nop_bytes
+ num_widens
>= desired_diff
)
9131 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9132 return !this_frag
->tc_frag_data
.is_no_density
? 2 : 3;
9133 else if (num_widens
== extra_bytes
)
9138 /* If we can't satisfy any of the above cases, then we can't align
9139 using padding or fill nops. */
9145 relax_frag_immed (segT segP
,
9152 bfd_boolean estimate_only
)
9156 bfd_boolean negatable_branch
= FALSE
;
9157 bfd_boolean branch_jmp_to_next
= FALSE
;
9158 bfd_boolean from_wide_insn
= FALSE
;
9159 xtensa_isa isa
= xtensa_default_isa
;
9161 offsetT frag_offset
;
9163 int num_text_bytes
, num_literal_bytes
;
9164 int literal_diff
, total_text_diff
, this_text_diff
;
9166 gas_assert (fragP
->fr_opcode
!= NULL
);
9168 xg_clear_vinsn (&cur_vinsn
);
9169 vinsn_from_chars (&cur_vinsn
, fragP
->fr_opcode
);
9170 if (cur_vinsn
.num_slots
> 1)
9171 from_wide_insn
= TRUE
;
9173 tinsn
= cur_vinsn
.slots
[slot
];
9174 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
9176 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
) == 1)
9179 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9180 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
9182 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
9184 old_size
= xtensa_format_length (isa
, fmt
);
9186 /* Special case: replace a branch to the next instruction with a NOP.
9187 This is required to work around a hardware bug in T1040.0 and also
9188 serves as an optimization. */
9190 if (branch_jmp_to_next
9191 && ((old_size
== 2) || (old_size
== 3))
9192 && !next_frag_is_loop_target (fragP
))
9195 /* Here is the fun stuff: Get the immediate field from this
9196 instruction. If it fits, we are done. If not, find the next
9197 instruction sequence that fits. */
9199 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9200 istack_init (&istack
);
9201 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
9202 min_steps
, stretch
);
9203 gas_assert (num_steps
>= min_steps
&& num_steps
<= RELAX_IMMED_MAXSTEPS
);
9205 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
9207 /* Figure out the number of bytes needed. */
9208 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
9210 = num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
9211 num_text_bytes
= get_num_stack_text_bytes (&istack
);
9216 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
9219 num_text_bytes
+= old_size
;
9220 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
9221 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
9224 /* The first instruction in the relaxed sequence will go after
9225 the current wide instruction, and thus its symbolic immediates
9228 istack_init (&istack
);
9229 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
,
9230 frag_offset
+ old_size
,
9231 min_steps
, stretch
+ old_size
);
9232 gas_assert (num_steps
>= min_steps
&& num_steps
<= RELAX_IMMED_MAXSTEPS
);
9234 fragP
->tc_frag_data
.slot_subtypes
[slot
]
9235 = (int) RELAX_IMMED
+ num_steps
;
9237 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
9239 = num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
9241 num_text_bytes
= get_num_stack_text_bytes (&istack
) + old_size
;
9245 total_text_diff
= num_text_bytes
- old_size
;
9246 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
9248 /* It MUST get larger. If not, we could get an infinite loop. */
9249 gas_assert (num_text_bytes
>= 0);
9250 gas_assert (literal_diff
>= 0);
9251 gas_assert (total_text_diff
>= 0);
9253 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
9254 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
9255 gas_assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
9256 gas_assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
9258 /* Find the associated expandable literal for this. */
9259 if (literal_diff
!= 0)
9261 fragS
*lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
9264 gas_assert (literal_diff
== 4);
9265 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
9267 /* We expect that the literal section state has NOT been
9269 gas_assert (lit_fragP
->fr_type
== rs_machine_dependent
9270 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
9271 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
9273 /* We need to mark this section for another iteration
9279 if (negatable_branch
&& istack
.ninsn
> 1)
9280 update_next_frag_state (fragP
);
9282 return this_text_diff
;
9286 /* md_convert_frag Hook and Helper Functions. */
9288 static void convert_frag_align_next_opcode (fragS
*);
9289 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
9290 static void convert_frag_fill_nop (fragS
*);
9291 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
9294 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
9296 static xtensa_insnbuf vbuf
= NULL
;
9297 xtensa_isa isa
= xtensa_default_isa
;
9304 as_where (&file_name
, &line
);
9305 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
9307 switch (fragp
->fr_subtype
)
9309 case RELAX_ALIGN_NEXT_OPCODE
:
9310 /* Always convert. */
9311 convert_frag_align_next_opcode (fragp
);
9314 case RELAX_DESIRE_ALIGN
:
9315 /* Do nothing. If not aligned already, too bad. */
9319 case RELAX_LITERAL_FINAL
:
9324 vbuf
= xtensa_insnbuf_alloc (isa
);
9326 xtensa_insnbuf_from_chars
9327 (isa
, vbuf
, (unsigned char *) fragp
->fr_opcode
, 0);
9328 fmt
= xtensa_format_decode (isa
, vbuf
);
9329 num_slots
= xtensa_format_num_slots (isa
, fmt
);
9331 for (slot
= 0; slot
< num_slots
; slot
++)
9333 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
9336 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
9340 case RELAX_IMMED_STEP1
:
9341 case RELAX_IMMED_STEP2
:
9342 case RELAX_IMMED_STEP3
:
9343 /* Place the immediate. */
9346 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
9351 /* This is OK because some slots could have
9352 relaxations and others have none. */
9358 case RELAX_UNREACHABLE
:
9359 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
9360 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
9361 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
9365 case RELAX_MAYBE_UNREACHABLE
:
9366 case RELAX_MAYBE_DESIRE_ALIGN
:
9370 case RELAX_FILL_NOP
:
9371 convert_frag_fill_nop (fragp
);
9374 case RELAX_LITERAL_NR
:
9375 if (use_literal_section
)
9377 /* This should have been handled during relaxation. When
9378 relaxing a code segment, literals sometimes need to be
9379 added to the corresponding literal segment. If that
9380 literal segment has already been relaxed, then we end up
9381 in this situation. Marking the literal segments as data
9382 would make this happen less often (since GAS always relaxes
9383 code before data), but we could still get into trouble if
9384 there are instructions in a segment that is not marked as
9385 containing code. Until we can implement a better solution,
9386 cheat and adjust the addresses of all the following frags.
9387 This could break subsequent alignments, but the linker's
9388 literal coalescing will do that anyway. */
9391 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
9392 gas_assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
9393 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
9396 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
9400 as_bad (_("invalid relaxation fragment result"));
9405 new_logical_line (file_name
, line
);
9410 convert_frag_align_next_opcode (fragS
*fragp
)
9412 char *nop_buf
; /* Location for Writing. */
9413 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
9414 addressT aligned_address
;
9418 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
9420 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
9421 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
9422 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
9424 for (nop
= 0; nop
< nop_count
; nop
++)
9427 nop_size
= get_text_align_nth_nop_size (fill_size
, nop
, use_no_density
);
9429 assemble_nop (nop_size
, nop_buf
);
9430 nop_buf
+= nop_size
;
9433 fragp
->fr_fix
+= fill_size
;
9434 fragp
->fr_var
-= fill_size
;
9439 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
9441 TInsn tinsn
, single_target
;
9442 int size
, old_size
, diff
;
9443 offsetT frag_offset
;
9445 gas_assert (slot
== 0);
9446 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
9448 if (fragP
->tc_frag_data
.is_aligning_branch
== 1)
9450 gas_assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
9451 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
9452 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
9457 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
9459 /* No conversion. */
9464 gas_assert (fragP
->fr_opcode
!= NULL
);
9466 /* Frags in this relaxation state should only contain
9467 single instruction bundles. */
9468 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
9470 /* Just convert it to a wide form.... */
9472 old_size
= xg_get_single_size (tinsn
.opcode
);
9474 tinsn_init (&single_target
);
9475 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9477 if (! xg_is_single_relaxable_insn (&tinsn
, &single_target
, FALSE
))
9479 as_bad (_("unable to widen instruction"));
9483 size
= xg_get_single_size (single_target
.opcode
);
9484 xg_emit_insn_to_buf (&single_target
, fragP
->fr_opcode
, fragP
,
9487 diff
= size
- old_size
;
9488 gas_assert (diff
>= 0);
9489 gas_assert (diff
<= fragP
->fr_var
);
9490 fragP
->fr_var
-= diff
;
9491 fragP
->fr_fix
+= diff
;
9499 convert_frag_fill_nop (fragS
*fragP
)
9501 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
9502 int size
= fragP
->tc_frag_data
.text_expansion
[0];
9503 gas_assert ((unsigned) size
== (fragP
->fr_next
->fr_address
9504 - fragP
->fr_address
- fragP
->fr_fix
));
9507 /* No conversion. */
9511 assemble_nop (size
, loc
);
9512 fragP
->tc_frag_data
.is_insn
= TRUE
;
9513 fragP
->fr_var
-= size
;
9514 fragP
->fr_fix
+= size
;
9519 static fixS
*fix_new_exp_in_seg
9520 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
9521 bfd_reloc_code_real_type
);
9522 static void convert_frag_immed_finish_loop (segT
, fragS
*, TInsn
*);
9525 convert_frag_immed (segT segP
,
9531 char *immed_instr
= fragP
->fr_opcode
;
9533 bfd_boolean expanded
= FALSE
;
9534 bfd_boolean branch_jmp_to_next
= FALSE
;
9535 char *fr_opcode
= fragP
->fr_opcode
;
9536 xtensa_isa isa
= xtensa_default_isa
;
9537 bfd_boolean from_wide_insn
= FALSE
;
9539 bfd_boolean is_loop
;
9541 gas_assert (fr_opcode
!= NULL
);
9543 xg_clear_vinsn (&cur_vinsn
);
9545 vinsn_from_chars (&cur_vinsn
, fr_opcode
);
9546 if (cur_vinsn
.num_slots
> 1)
9547 from_wide_insn
= TRUE
;
9549 orig_tinsn
= cur_vinsn
.slots
[slot
];
9550 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
9552 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
9554 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9555 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
9557 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
9559 /* Conversion just inserts a NOP and marks the fix as completed. */
9560 bytes
= xtensa_format_length (isa
, fmt
);
9563 cur_vinsn
.slots
[slot
].opcode
=
9564 xtensa_format_slot_nop_opcode (isa
, cur_vinsn
.format
, slot
);
9565 cur_vinsn
.slots
[slot
].ntok
= 0;
9569 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
9570 gas_assert (bytes
== 2 || bytes
== 3);
9571 build_nop (&cur_vinsn
.slots
[0], bytes
);
9572 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
9574 vinsn_to_insnbuf (&cur_vinsn
, fr_opcode
, frag_now
, TRUE
);
9575 xtensa_insnbuf_to_chars
9576 (isa
, cur_vinsn
.insnbuf
, (unsigned char *) fr_opcode
, 0);
9581 /* Here is the fun stuff: Get the immediate field from this
9582 instruction. If it fits, we're done. If not, find the next
9583 instruction sequence that fits. */
9587 symbolS
*lit_sym
= NULL
;
9589 int target_offset
= 0;
9592 symbolS
*gen_label
= NULL
;
9593 offsetT frag_offset
;
9594 bfd_boolean first
= TRUE
;
9595 bfd_boolean last_is_jump
;
9597 /* It does not fit. Find something that does and
9598 convert immediately. */
9599 frag_offset
= fr_opcode
- fragP
->fr_literal
;
9600 istack_init (&istack
);
9601 xg_assembly_relax (&istack
, &orig_tinsn
,
9602 segP
, fragP
, frag_offset
, min_steps
, 0);
9604 old_size
= xtensa_format_length (isa
, fmt
);
9606 /* Assemble this right inline. */
9608 /* First, create the mapping from a label name to the REAL label. */
9610 for (i
= 0; i
< istack
.ninsn
; i
++)
9612 TInsn
*tinsn
= &istack
.insn
[i
];
9615 switch (tinsn
->insn_type
)
9618 if (lit_sym
!= NULL
)
9619 as_bad (_("multiple literals in expansion"));
9620 /* First find the appropriate space in the literal pool. */
9621 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9622 if (lit_frag
== NULL
)
9623 as_bad (_("no registered fragment for literal"));
9624 if (tinsn
->ntok
!= 1)
9625 as_bad (_("number of literal tokens != 1"));
9627 /* Set the literal symbol and add a fixup. */
9628 lit_sym
= lit_frag
->fr_symbol
;
9632 if (align_targets
&& !is_loop
)
9634 fragS
*unreach
= fragP
->fr_next
;
9635 while (!(unreach
->fr_type
== rs_machine_dependent
9636 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9637 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
9639 unreach
= unreach
->fr_next
;
9642 gas_assert (unreach
->fr_type
== rs_machine_dependent
9643 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9644 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
9646 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
9648 gas_assert (gen_label
== NULL
);
9649 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
9650 fr_opcode
- fragP
->fr_literal
9651 + target_offset
, fragP
);
9655 if (first
&& from_wide_insn
)
9657 target_offset
+= xtensa_format_length (isa
, fmt
);
9659 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9660 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9663 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9670 last_is_jump
= FALSE
;
9671 for (i
= 0; i
< istack
.ninsn
; i
++)
9673 TInsn
*tinsn
= &istack
.insn
[i
];
9677 bfd_reloc_code_real_type reloc_type
;
9679 switch (tinsn
->insn_type
)
9682 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9683 /* Already checked. */
9684 gas_assert (lit_frag
!= NULL
);
9685 gas_assert (lit_sym
!= NULL
);
9686 gas_assert (tinsn
->ntok
== 1);
9688 target_seg
= S_GET_SEGMENT (lit_sym
);
9689 gas_assert (target_seg
);
9690 reloc_type
= map_operator_to_reloc (tinsn
->tok
[0].X_op
, TRUE
);
9691 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
9692 &tinsn
->tok
[0], FALSE
, reloc_type
);
9699 xg_resolve_labels (tinsn
, gen_label
);
9700 xg_resolve_literals (tinsn
, lit_sym
);
9701 if (from_wide_insn
&& first
)
9704 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9706 cur_vinsn
.slots
[slot
] = *tinsn
;
9710 cur_vinsn
.slots
[slot
].opcode
=
9711 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
9712 cur_vinsn
.slots
[slot
].ntok
= 0;
9714 vinsn_to_insnbuf (&cur_vinsn
, immed_instr
, fragP
, TRUE
);
9715 xtensa_insnbuf_to_chars (isa
, cur_vinsn
.insnbuf
,
9716 (unsigned char *) immed_instr
, 0);
9717 fragP
->tc_frag_data
.is_insn
= TRUE
;
9718 size
= xtensa_format_length (isa
, fmt
);
9719 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9722 (tinsn
, immed_instr
+ size
, fragP
,
9723 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
9724 size
+= xg_get_single_size (tinsn
->opcode
);
9729 size
= xg_get_single_size (tinsn
->opcode
);
9730 xg_emit_insn_to_buf (tinsn
, immed_instr
, fragP
,
9731 immed_instr
- fragP
->fr_literal
, TRUE
);
9733 immed_instr
+= size
;
9739 diff
= total_size
- old_size
;
9740 gas_assert (diff
>= 0);
9743 gas_assert (diff
<= fragP
->fr_var
);
9744 fragP
->fr_var
-= diff
;
9745 fragP
->fr_fix
+= diff
;
9748 /* Check for undefined immediates in LOOP instructions. */
9752 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
9753 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9755 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9758 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
9759 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9761 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9766 if (expanded
&& xtensa_opcode_is_loop (isa
, orig_tinsn
.opcode
) == 1)
9767 convert_frag_immed_finish_loop (segP
, fragP
, &orig_tinsn
);
9769 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
9771 /* Add an expansion note on the expanded instruction. */
9772 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
9773 &orig_tinsn
.tok
[0], TRUE
,
9774 BFD_RELOC_XTENSA_ASM_EXPAND
);
9779 /* Add a new fix expression into the desired segment. We have to
9780 switch to that segment to do this. */
9783 fix_new_exp_in_seg (segT new_seg
,
9790 bfd_reloc_code_real_type r_type
)
9794 subsegT subseg
= now_subseg
;
9796 gas_assert (new_seg
!= 0);
9797 subseg_set (new_seg
, new_subseg
);
9799 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
9800 subseg_set (seg
, subseg
);
9805 /* Relax a loop instruction so that it can span loop >256 bytes.
9811 addi as, as, lo8 (label-.L1)
9812 addmi as, as, mid8 (label-.L1)
9823 convert_frag_immed_finish_loop (segT segP
, fragS
*fragP
, TInsn
*tinsn
)
9828 unsigned long target
;
9829 static xtensa_insnbuf insnbuf
= NULL
;
9830 unsigned int loop_length
, loop_length_hi
, loop_length_lo
;
9831 xtensa_isa isa
= xtensa_default_isa
;
9832 addressT loop_offset
;
9833 addressT addi_offset
= 9;
9834 addressT addmi_offset
= 12;
9839 insnbuf
= xtensa_insnbuf_alloc (isa
);
9841 /* Get the loop offset. */
9842 loop_offset
= get_expanded_loop_offset (tinsn
->opcode
);
9844 /* Validate that there really is a LOOP at the loop_offset. Because
9845 loops are not bundleable, we can assume that the instruction will be
9847 tinsn_from_chars (&loop_insn
, fragP
->fr_opcode
+ loop_offset
, 0);
9848 tinsn_immed_from_frag (&loop_insn
, fragP
, 0);
9850 gas_assert (xtensa_opcode_is_loop (isa
, loop_insn
.opcode
) == 1);
9851 addi_offset
+= loop_offset
;
9852 addmi_offset
+= loop_offset
;
9854 gas_assert (tinsn
->ntok
== 2);
9855 if (tinsn
->tok
[1].X_op
== O_constant
)
9856 target
= tinsn
->tok
[1].X_add_number
;
9857 else if (tinsn
->tok
[1].X_op
== O_symbol
)
9859 /* Find the fragment. */
9860 symbolS
*sym
= tinsn
->tok
[1].X_add_symbol
;
9861 gas_assert (S_GET_SEGMENT (sym
) == segP
9862 || S_GET_SEGMENT (sym
) == absolute_section
);
9863 target
= (S_GET_VALUE (sym
) + tinsn
->tok
[1].X_add_number
);
9867 as_bad (_("invalid expression evaluation type %d"), tinsn
->tok
[1].X_op
);
9871 loop_length
= target
- (fragP
->fr_address
+ fragP
->fr_fix
);
9872 loop_length_hi
= loop_length
& ~0x0ff;
9873 loop_length_lo
= loop_length
& 0x0ff;
9874 if (loop_length_lo
>= 128)
9876 loop_length_lo
-= 256;
9877 loop_length_hi
+= 256;
9880 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
9881 32512. If the loop is larger than that, then we just fail. */
9882 if (loop_length_hi
> 32512)
9883 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9884 _("loop too long for LOOP instruction"));
9886 tinsn_from_chars (&addi_insn
, fragP
->fr_opcode
+ addi_offset
, 0);
9887 gas_assert (addi_insn
.opcode
== xtensa_addi_opcode
);
9889 tinsn_from_chars (&addmi_insn
, fragP
->fr_opcode
+ addmi_offset
, 0);
9890 gas_assert (addmi_insn
.opcode
== xtensa_addmi_opcode
);
9892 set_expr_const (&addi_insn
.tok
[2], loop_length_lo
);
9893 tinsn_to_insnbuf (&addi_insn
, insnbuf
);
9895 fragP
->tc_frag_data
.is_insn
= TRUE
;
9896 xtensa_insnbuf_to_chars
9897 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addi_offset
, 0);
9899 set_expr_const (&addmi_insn
.tok
[2], loop_length_hi
);
9900 tinsn_to_insnbuf (&addmi_insn
, insnbuf
);
9901 xtensa_insnbuf_to_chars
9902 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addmi_offset
, 0);
9904 /* Walk through all of the frags from here to the loop end
9905 and mark them as no_transform to keep them from being modified
9906 by the linker. If we ever have a relocation for the
9907 addi/addmi of the difference of two symbols we can remove this. */
9910 for (next_fragP
= fragP
; next_fragP
!= NULL
;
9911 next_fragP
= next_fragP
->fr_next
)
9913 next_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
9914 if (next_fragP
->tc_frag_data
.is_loop_target
)
9916 if (target_count
== 2)
9922 /* A map that keeps information on a per-subsegment basis. This is
9923 maintained during initial assembly, but is invalid once the
9924 subsegments are smashed together. I.E., it cannot be used during
9927 typedef struct subseg_map_struct
9935 float total_freq
; /* fall-through + branch target frequency */
9936 float target_freq
; /* branch target frequency alone */
9938 struct subseg_map_struct
*next
;
9942 static subseg_map
*sseg_map
= NULL
;
9945 get_subseg_info (segT seg
, subsegT subseg
)
9947 subseg_map
*subseg_e
;
9949 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
9951 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
9959 add_subseg_info (segT seg
, subsegT subseg
)
9961 subseg_map
*subseg_e
= (subseg_map
*) xmalloc (sizeof (subseg_map
));
9962 memset (subseg_e
, 0, sizeof (subseg_map
));
9963 subseg_e
->seg
= seg
;
9964 subseg_e
->subseg
= subseg
;
9965 subseg_e
->flags
= 0;
9966 /* Start off considering every branch target very important. */
9967 subseg_e
->target_freq
= 1.0;
9968 subseg_e
->total_freq
= 1.0;
9969 subseg_e
->next
= sseg_map
;
9970 sseg_map
= subseg_e
;
9976 get_last_insn_flags (segT seg
, subsegT subseg
)
9978 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9980 return subseg_e
->flags
;
9986 set_last_insn_flags (segT seg
,
9991 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9993 subseg_e
= add_subseg_info (seg
, subseg
);
9995 subseg_e
->flags
|= fl
;
9997 subseg_e
->flags
&= ~fl
;
10002 get_subseg_total_freq (segT seg
, subsegT subseg
)
10004 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
10006 return subseg_e
->total_freq
;
10012 get_subseg_target_freq (segT seg
, subsegT subseg
)
10014 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
10016 return subseg_e
->target_freq
;
10022 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
10024 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
10026 subseg_e
= add_subseg_info (seg
, subseg
);
10027 subseg_e
->total_freq
= total_f
;
10028 subseg_e
->target_freq
= target_f
;
10032 /* Segment Lists and emit_state Stuff. */
10035 xtensa_move_seg_list_to_beginning (seg_list
*head
)
10040 segT literal_section
= head
->seg
;
10042 /* Move the literal section to the front of the section list. */
10043 gas_assert (literal_section
);
10044 if (literal_section
!= stdoutput
->sections
)
10046 bfd_section_list_remove (stdoutput
, literal_section
);
10047 bfd_section_list_prepend (stdoutput
, literal_section
);
10054 static void mark_literal_frags (seg_list
*);
10057 xtensa_move_literals (void)
10060 frchainS
*frchain_from
, *frchain_to
;
10061 fragS
*search_frag
, *next_frag
, *last_frag
, *literal_pool
, *insert_after
;
10062 fragS
**frag_splice
;
10065 fixS
*fix
, *next_fix
, **fix_splice
;
10068 mark_literal_frags (literal_head
->next
);
10070 if (use_literal_section
)
10073 for (segment
= literal_head
->next
; segment
; segment
= segment
->next
)
10075 /* Keep the literals for .init and .fini in separate sections. */
10076 if (!strcmp (segment_name (segment
->seg
), INIT_SECTION_NAME
)
10077 || !strcmp (segment_name (segment
->seg
), FINI_SECTION_NAME
))
10080 frchain_from
= seg_info (segment
->seg
)->frchainP
;
10081 search_frag
= frchain_from
->frch_root
;
10082 literal_pool
= NULL
;
10084 frag_splice
= &(frchain_from
->frch_root
);
10086 while (!search_frag
->tc_frag_data
.literal_frag
)
10088 gas_assert (search_frag
->fr_fix
== 0
10089 || search_frag
->fr_type
== rs_align
);
10090 search_frag
= search_frag
->fr_next
;
10093 gas_assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
10094 == RELAX_LITERAL_POOL_BEGIN
);
10095 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
10097 /* Make sure that all the frags in this series are closed, and
10098 that there is at least one left over of zero-size. This
10099 prevents us from making a segment with an frchain without any
10101 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10102 xtensa_set_frag_assembly_state (frag_now
);
10103 last_frag
= frag_now
;
10104 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10105 xtensa_set_frag_assembly_state (frag_now
);
10107 while (search_frag
!= frag_now
)
10109 next_frag
= search_frag
->fr_next
;
10111 /* First, move the frag out of the literal section and
10112 to the appropriate place. */
10113 if (search_frag
->tc_frag_data
.literal_frag
)
10115 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
10116 gas_assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
10117 frchain_to
= literal_pool
->tc_frag_data
.lit_frchain
;
10118 gas_assert (frchain_to
);
10120 insert_after
= literal_pool
->tc_frag_data
.literal_frag
;
10121 dest_seg
= insert_after
->fr_next
->tc_frag_data
.lit_seg
;
10123 *frag_splice
= next_frag
;
10124 search_frag
->fr_next
= insert_after
->fr_next
;
10125 insert_after
->fr_next
= search_frag
;
10126 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
10127 literal_pool
->tc_frag_data
.literal_frag
= search_frag
;
10129 /* Now move any fixups associated with this frag to the
10131 fix
= frchain_from
->fix_root
;
10132 fix_splice
= &(frchain_from
->fix_root
);
10135 next_fix
= fix
->fx_next
;
10136 if (fix
->fx_frag
== search_frag
)
10138 *fix_splice
= next_fix
;
10139 fix
->fx_next
= frchain_to
->fix_root
;
10140 frchain_to
->fix_root
= fix
;
10141 if (frchain_to
->fix_tail
== NULL
)
10142 frchain_to
->fix_tail
= fix
;
10145 fix_splice
= &(fix
->fx_next
);
10148 search_frag
= next_frag
;
10151 if (frchain_from
->fix_root
!= NULL
)
10153 frchain_from
= seg_info (segment
->seg
)->frchainP
;
10154 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
10156 gas_assert (frchain_from
->fix_root
== NULL
);
10158 frchain_from
->fix_tail
= NULL
;
10159 xtensa_restore_emit_state (&state
);
10162 /* Now fix up the SEGMENT value for all the literal symbols. */
10163 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
10165 symbolS
*lit_sym
= lit
->sym
;
10166 segT dseg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
10168 S_SET_SEGMENT (lit_sym
, dseg
);
10173 /* Walk over all the frags for segments in a list and mark them as
10174 containing literals. As clunky as this is, we can't rely on frag_var
10175 and frag_variant to get called in all situations. */
10178 mark_literal_frags (seg_list
*segment
)
10180 frchainS
*frchain_from
;
10181 fragS
*search_frag
;
10185 frchain_from
= seg_info (segment
->seg
)->frchainP
;
10186 search_frag
= frchain_from
->frch_root
;
10187 while (search_frag
)
10189 search_frag
->tc_frag_data
.is_literal
= TRUE
;
10190 search_frag
= search_frag
->fr_next
;
10192 segment
= segment
->next
;
10198 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
10200 /* Move all of the sections in the section list to come
10201 after "after" in the gnu segment list. */
10206 segT literal_section
= head
->seg
;
10208 /* Move the literal section after "after". */
10209 gas_assert (literal_section
);
10210 if (literal_section
!= after
)
10212 bfd_section_list_remove (stdoutput
, literal_section
);
10213 bfd_section_list_insert_after (stdoutput
, after
, literal_section
);
10221 /* Push all the literal segments to the end of the gnu list. */
10224 xtensa_reorder_segments (void)
10231 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
10237 /* Now that we have the last section, push all the literal
10238 sections to the end. */
10239 xtensa_reorder_seg_list (literal_head
, last_sec
);
10241 /* Now perform the final error check. */
10242 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
10244 gas_assert (new_count
== old_count
);
10248 /* Change the emit state (seg, subseg, and frag related stuff) to the
10249 correct location. Return a emit_state which can be passed to
10250 xtensa_restore_emit_state to return to current fragment. */
10253 xtensa_switch_to_literal_fragment (emit_state
*result
)
10255 if (directive_state
[directive_absolute_literals
])
10257 segT lit4_seg
= cache_literal_section (TRUE
);
10258 xtensa_switch_section_emit_state (result
, lit4_seg
, 0);
10261 xtensa_switch_to_non_abs_literal_fragment (result
);
10263 /* Do a 4-byte align here. */
10264 frag_align (2, 0, 0);
10265 record_alignment (now_seg
, 2);
10270 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
10272 static bfd_boolean recursive
= FALSE
;
10273 fragS
*pool_location
= get_literal_pool_location (now_seg
);
10275 bfd_boolean is_init
=
10276 (now_seg
&& !strcmp (segment_name (now_seg
), INIT_SECTION_NAME
));
10277 bfd_boolean is_fini
=
10278 (now_seg
&& !strcmp (segment_name (now_seg
), FINI_SECTION_NAME
));
10280 if (pool_location
== NULL
10281 && !use_literal_section
10283 && !is_init
&& ! is_fini
)
10285 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
10287 /* When we mark a literal pool location, we want to put a frag in
10288 the literal pool that points to it. But to do that, we want to
10289 switch_to_literal_fragment. But literal sections don't have
10290 literal pools, so their location is always null, so we would
10291 recurse forever. This is kind of hacky, but it works. */
10294 xtensa_mark_literal_pool_location ();
10298 lit_seg
= cache_literal_section (FALSE
);
10299 xtensa_switch_section_emit_state (result
, lit_seg
, 0);
10301 if (!use_literal_section
10302 && !is_init
&& !is_fini
10303 && get_literal_pool_location (now_seg
) != pool_location
)
10305 /* Close whatever frag is there. */
10306 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10307 xtensa_set_frag_assembly_state (frag_now
);
10308 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
10309 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10310 xtensa_set_frag_assembly_state (frag_now
);
10315 /* Call this function before emitting data into the literal section.
10316 This is a helper function for xtensa_switch_to_literal_fragment.
10317 This is similar to a .section new_now_seg subseg. */
10320 xtensa_switch_section_emit_state (emit_state
*state
,
10322 subsegT new_now_subseg
)
10324 state
->name
= now_seg
->name
;
10325 state
->now_seg
= now_seg
;
10326 state
->now_subseg
= now_subseg
;
10327 state
->generating_literals
= generating_literals
;
10328 generating_literals
++;
10329 subseg_set (new_now_seg
, new_now_subseg
);
10333 /* Use to restore the emitting into the normal place. */
10336 xtensa_restore_emit_state (emit_state
*state
)
10338 generating_literals
= state
->generating_literals
;
10339 subseg_set (state
->now_seg
, state
->now_subseg
);
10343 /* Predicate function used to look up a section in a particular group. */
10346 match_section_group (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
, void *inf
)
10348 const char *gname
= inf
;
10349 const char *group_name
= elf_group_name (sec
);
10351 return (group_name
== gname
10352 || (group_name
!= NULL
10354 && strcmp (group_name
, gname
) == 0));
10358 /* Get the literal section to be used for the current text section.
10359 The result may be cached in the default_lit_sections structure. */
10362 cache_literal_section (bfd_boolean use_abs_literals
)
10364 const char *text_name
, *group_name
= 0;
10365 char *base_name
, *name
, *suffix
;
10367 segT seg
, current_section
;
10368 int current_subsec
;
10369 bfd_boolean linkonce
= FALSE
;
10371 /* Save the current section/subsection. */
10372 current_section
= now_seg
;
10373 current_subsec
= now_subseg
;
10375 /* Clear the cached values if they are no longer valid. */
10376 if (now_seg
!= default_lit_sections
.current_text_seg
)
10378 default_lit_sections
.current_text_seg
= now_seg
;
10379 default_lit_sections
.lit_seg
= NULL
;
10380 default_lit_sections
.lit4_seg
= NULL
;
10383 /* Check if the literal section is already cached. */
10384 if (use_abs_literals
)
10385 pcached
= &default_lit_sections
.lit4_seg
;
10387 pcached
= &default_lit_sections
.lit_seg
;
10392 text_name
= default_lit_sections
.lit_prefix
;
10393 if (! text_name
|| ! *text_name
)
10395 text_name
= segment_name (current_section
);
10396 group_name
= elf_group_name (current_section
);
10397 linkonce
= (current_section
->flags
& SEC_LINK_ONCE
) != 0;
10400 base_name
= use_abs_literals
? ".lit4" : ".literal";
10403 name
= xmalloc (strlen (base_name
) + strlen (group_name
) + 2);
10404 sprintf (name
, "%s.%s", base_name
, group_name
);
10406 else if (strncmp (text_name
, ".gnu.linkonce.", linkonce_len
) == 0)
10408 suffix
= strchr (text_name
+ linkonce_len
, '.');
10410 name
= xmalloc (linkonce_len
+ strlen (base_name
) + 1
10411 + (suffix
? strlen (suffix
) : 0));
10412 strcpy (name
, ".gnu.linkonce");
10413 strcat (name
, base_name
);
10415 strcat (name
, suffix
);
10420 /* If the section name ends with ".text", then replace that suffix
10421 instead of appending an additional suffix. */
10422 size_t len
= strlen (text_name
);
10423 if (len
>= 5 && strcmp (text_name
+ len
- 5, ".text") == 0)
10426 name
= xmalloc (len
+ strlen (base_name
) + 1);
10427 strcpy (name
, text_name
);
10428 strcpy (name
+ len
, base_name
);
10431 /* Canonicalize section names to allow renaming literal sections.
10432 The group name, if any, came from the current text section and
10433 has already been canonicalized. */
10434 name
= tc_canonicalize_symbol_name (name
);
10436 seg
= bfd_get_section_by_name_if (stdoutput
, name
, match_section_group
,
10437 (void *) group_name
);
10442 seg
= subseg_force_new (name
, 0);
10444 if (! use_abs_literals
)
10446 /* Add the newly created literal segment to the list. */
10447 seg_list
*n
= (seg_list
*) xmalloc (sizeof (seg_list
));
10449 n
->next
= literal_head
->next
;
10450 literal_head
->next
= n
;
10453 flags
= (SEC_HAS_CONTENTS
| SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
10454 | (linkonce
? (SEC_LINK_ONCE
| SEC_LINK_DUPLICATES_DISCARD
) : 0)
10455 | (use_abs_literals
? SEC_DATA
: SEC_CODE
));
10457 elf_group_name (seg
) = group_name
;
10459 bfd_set_section_flags (stdoutput
, seg
, flags
);
10460 bfd_set_section_alignment (stdoutput
, seg
, 2);
10464 subseg_set (current_section
, current_subsec
);
10469 /* Property Tables Stuff. */
10471 #define XTENSA_INSN_SEC_NAME ".xt.insn"
10472 #define XTENSA_LIT_SEC_NAME ".xt.lit"
10473 #define XTENSA_PROP_SEC_NAME ".xt.prop"
10475 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
10476 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
10478 static bfd_boolean
get_frag_is_literal (const fragS
*);
10479 static void xtensa_create_property_segments
10480 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
10481 static void xtensa_create_xproperty_segments
10482 (frag_flags_fn
, const char *, xt_section_type
);
10483 static bfd_boolean
exclude_section_from_property_tables (segT
);
10484 static bfd_boolean
section_has_property (segT
, frag_predicate
);
10485 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
10486 static void add_xt_block_frags
10487 (segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
10488 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
10489 static void xtensa_frag_flags_init (frag_flags
*);
10490 static void get_frag_property_flags (const fragS
*, frag_flags
*);
10491 static flagword
frag_flags_to_number (const frag_flags
*);
10492 static void add_xt_prop_frags (segT
, xtensa_block_info
**, frag_flags_fn
);
10494 /* Set up property tables after relaxation. */
10497 xtensa_post_relax_hook (void)
10499 xtensa_move_seg_list_to_beginning (literal_head
);
10501 xtensa_find_unmarked_state_frags ();
10502 xtensa_mark_frags_for_org ();
10503 xtensa_mark_difference_of_two_symbols ();
10505 xtensa_create_property_segments (get_frag_is_literal
,
10507 XTENSA_LIT_SEC_NAME
,
10509 xtensa_create_xproperty_segments (get_frag_property_flags
,
10510 XTENSA_PROP_SEC_NAME
,
10513 if (warn_unaligned_branch_targets
)
10514 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
10515 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
10519 /* This function is only meaningful after xtensa_move_literals. */
10522 get_frag_is_literal (const fragS
*fragP
)
10524 gas_assert (fragP
!= NULL
);
10525 return fragP
->tc_frag_data
.is_literal
;
10530 xtensa_create_property_segments (frag_predicate property_function
,
10531 frag_predicate end_property_function
,
10532 const char *section_name_base
,
10533 xt_section_type sec_type
)
10537 /* Walk over all of the current segments.
10538 Walk over each fragment
10539 For each non-empty fragment,
10540 Build a property record (append where possible). */
10542 for (seclist
= &stdoutput
->sections
;
10543 seclist
&& *seclist
;
10544 seclist
= &(*seclist
)->next
)
10546 segT sec
= *seclist
;
10548 if (exclude_section_from_property_tables (sec
))
10551 if (section_has_property (sec
, property_function
))
10553 segment_info_type
*xt_seg_info
;
10554 xtensa_block_info
**xt_blocks
;
10555 segT prop_sec
= xtensa_make_property_section (sec
, section_name_base
);
10557 prop_sec
->output_section
= prop_sec
;
10558 subseg_set (prop_sec
, 0);
10559 xt_seg_info
= seg_info (prop_sec
);
10560 xt_blocks
= &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10562 /* Walk over all of the frchains here and add new sections. */
10563 add_xt_block_frags (sec
, xt_blocks
, property_function
,
10564 end_property_function
);
10568 /* Now we fill them out.... */
10570 for (seclist
= &stdoutput
->sections
;
10571 seclist
&& *seclist
;
10572 seclist
= &(*seclist
)->next
)
10574 segment_info_type
*seginfo
;
10575 xtensa_block_info
*block
;
10576 segT sec
= *seclist
;
10578 seginfo
= seg_info (sec
);
10579 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10583 xtensa_block_info
*cur_block
;
10585 bfd_size_type rec_size
;
10587 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10590 rec_size
= num_recs
* 8;
10591 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10598 subseg_set (sec
, 0);
10599 frag_data
= frag_more (rec_size
);
10601 for (i
= 0; i
< num_recs
; i
++)
10605 /* Write the fixup. */
10606 gas_assert (cur_block
);
10607 fix
= fix_new (frag_now
, i
* 8, 4,
10608 section_symbol (cur_block
->sec
),
10610 FALSE
, BFD_RELOC_32
);
10611 fix
->fx_file
= "<internal>";
10614 /* Write the length. */
10615 md_number_to_chars (&frag_data
[4 + i
* 8],
10616 cur_block
->size
, 4);
10617 cur_block
= cur_block
->next
;
10619 frag_wane (frag_now
);
10621 frag_wane (frag_now
);
10629 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
10630 const char *section_name_base
,
10631 xt_section_type sec_type
)
10635 /* Walk over all of the current segments.
10636 Walk over each fragment.
10637 For each fragment that has instructions,
10638 build an instruction record (append where possible). */
10640 for (seclist
= &stdoutput
->sections
;
10641 seclist
&& *seclist
;
10642 seclist
= &(*seclist
)->next
)
10644 segT sec
= *seclist
;
10646 if (exclude_section_from_property_tables (sec
))
10649 if (section_has_xproperty (sec
, flag_fn
))
10651 segment_info_type
*xt_seg_info
;
10652 xtensa_block_info
**xt_blocks
;
10653 segT prop_sec
= xtensa_make_property_section (sec
, section_name_base
);
10655 prop_sec
->output_section
= prop_sec
;
10656 subseg_set (prop_sec
, 0);
10657 xt_seg_info
= seg_info (prop_sec
);
10658 xt_blocks
= &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10660 /* Walk over all of the frchains here and add new sections. */
10661 add_xt_prop_frags (sec
, xt_blocks
, flag_fn
);
10665 /* Now we fill them out.... */
10667 for (seclist
= &stdoutput
->sections
;
10668 seclist
&& *seclist
;
10669 seclist
= &(*seclist
)->next
)
10671 segment_info_type
*seginfo
;
10672 xtensa_block_info
*block
;
10673 segT sec
= *seclist
;
10675 seginfo
= seg_info (sec
);
10676 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10680 xtensa_block_info
*cur_block
;
10682 bfd_size_type rec_size
;
10684 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10687 rec_size
= num_recs
* (8 + 4);
10688 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10689 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
10696 subseg_set (sec
, 0);
10697 frag_data
= frag_more (rec_size
);
10699 for (i
= 0; i
< num_recs
; i
++)
10703 /* Write the fixup. */
10704 gas_assert (cur_block
);
10705 fix
= fix_new (frag_now
, i
* 12, 4,
10706 section_symbol (cur_block
->sec
),
10708 FALSE
, BFD_RELOC_32
);
10709 fix
->fx_file
= "<internal>";
10712 /* Write the length. */
10713 md_number_to_chars (&frag_data
[4 + i
* 12],
10714 cur_block
->size
, 4);
10715 md_number_to_chars (&frag_data
[8 + i
* 12],
10716 frag_flags_to_number (&cur_block
->flags
),
10717 sizeof (flagword
));
10718 cur_block
= cur_block
->next
;
10720 frag_wane (frag_now
);
10722 frag_wane (frag_now
);
10730 exclude_section_from_property_tables (segT sec
)
10732 flagword flags
= bfd_get_section_flags (stdoutput
, sec
);
10734 /* Sections that don't contribute to the memory footprint are excluded. */
10735 if ((flags
& SEC_DEBUGGING
)
10736 || !(flags
& SEC_ALLOC
)
10737 || (flags
& SEC_MERGE
))
10740 /* Linker cie and fde optimizations mess up property entries for
10741 eh_frame sections, but there is nothing inside them relevant to
10742 property tables anyway. */
10743 if (strcmp (sec
->name
, ".eh_frame") == 0)
10751 section_has_property (segT sec
, frag_predicate property_function
)
10753 segment_info_type
*seginfo
= seg_info (sec
);
10756 if (seginfo
&& seginfo
->frchainP
)
10758 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10760 if (property_function (fragP
)
10761 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10770 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
10772 segment_info_type
*seginfo
= seg_info (sec
);
10775 if (seginfo
&& seginfo
->frchainP
)
10777 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10779 frag_flags prop_flags
;
10780 property_function (fragP
, &prop_flags
);
10781 if (!xtensa_frag_flags_is_empty (&prop_flags
))
10789 /* Two types of block sections exist right now: literal and insns. */
10792 add_xt_block_frags (segT sec
,
10793 xtensa_block_info
**xt_block
,
10794 frag_predicate property_function
,
10795 frag_predicate end_property_function
)
10799 /* Build it if needed. */
10800 while (*xt_block
!= NULL
)
10801 xt_block
= &(*xt_block
)->next
;
10802 /* We are either at NULL at the beginning or at the end. */
10804 /* Walk through the frags. */
10805 if (seg_info (sec
)->frchainP
)
10807 for (fragP
= seg_info (sec
)->frchainP
->frch_root
;
10809 fragP
= fragP
->fr_next
)
10811 if (property_function (fragP
)
10812 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10814 if (*xt_block
!= NULL
)
10816 if ((*xt_block
)->offset
+ (*xt_block
)->size
10817 == fragP
->fr_address
)
10818 (*xt_block
)->size
+= fragP
->fr_fix
;
10820 xt_block
= &((*xt_block
)->next
);
10822 if (*xt_block
== NULL
)
10824 xtensa_block_info
*new_block
= (xtensa_block_info
*)
10825 xmalloc (sizeof (xtensa_block_info
));
10826 new_block
->sec
= sec
;
10827 new_block
->offset
= fragP
->fr_address
;
10828 new_block
->size
= fragP
->fr_fix
;
10829 new_block
->next
= NULL
;
10830 xtensa_frag_flags_init (&new_block
->flags
);
10831 *xt_block
= new_block
;
10833 if (end_property_function
10834 && end_property_function (fragP
))
10836 xt_block
= &((*xt_block
)->next
);
10844 /* Break the encapsulation of add_xt_prop_frags here. */
10847 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
10849 if (prop_flags
->is_literal
10850 || prop_flags
->is_insn
10851 || prop_flags
->is_data
10852 || prop_flags
->is_unreachable
)
10859 xtensa_frag_flags_init (frag_flags
*prop_flags
)
10861 memset (prop_flags
, 0, sizeof (frag_flags
));
10866 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
10868 xtensa_frag_flags_init (prop_flags
);
10869 if (fragP
->tc_frag_data
.is_literal
)
10870 prop_flags
->is_literal
= TRUE
;
10871 if (fragP
->tc_frag_data
.is_specific_opcode
10872 || fragP
->tc_frag_data
.is_no_transform
)
10874 prop_flags
->is_no_transform
= TRUE
;
10875 if (xtensa_frag_flags_is_empty (prop_flags
))
10876 prop_flags
->is_data
= TRUE
;
10878 if (fragP
->tc_frag_data
.is_unreachable
)
10879 prop_flags
->is_unreachable
= TRUE
;
10880 else if (fragP
->tc_frag_data
.is_insn
)
10882 prop_flags
->is_insn
= TRUE
;
10883 if (fragP
->tc_frag_data
.is_loop_target
)
10884 prop_flags
->insn
.is_loop_target
= TRUE
;
10885 if (fragP
->tc_frag_data
.is_branch_target
)
10886 prop_flags
->insn
.is_branch_target
= TRUE
;
10887 if (fragP
->tc_frag_data
.is_no_density
)
10888 prop_flags
->insn
.is_no_density
= TRUE
;
10889 if (fragP
->tc_frag_data
.use_absolute_literals
)
10890 prop_flags
->insn
.is_abslit
= TRUE
;
10892 if (fragP
->tc_frag_data
.is_align
)
10894 prop_flags
->is_align
= TRUE
;
10895 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
10896 if (xtensa_frag_flags_is_empty (prop_flags
))
10897 prop_flags
->is_data
= TRUE
;
10903 frag_flags_to_number (const frag_flags
*prop_flags
)
10906 if (prop_flags
->is_literal
)
10907 num
|= XTENSA_PROP_LITERAL
;
10908 if (prop_flags
->is_insn
)
10909 num
|= XTENSA_PROP_INSN
;
10910 if (prop_flags
->is_data
)
10911 num
|= XTENSA_PROP_DATA
;
10912 if (prop_flags
->is_unreachable
)
10913 num
|= XTENSA_PROP_UNREACHABLE
;
10914 if (prop_flags
->insn
.is_loop_target
)
10915 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
10916 if (prop_flags
->insn
.is_branch_target
)
10918 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
10919 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
10922 if (prop_flags
->insn
.is_no_density
)
10923 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
10924 if (prop_flags
->is_no_transform
)
10925 num
|= XTENSA_PROP_NO_TRANSFORM
;
10926 if (prop_flags
->insn
.is_no_reorder
)
10927 num
|= XTENSA_PROP_INSN_NO_REORDER
;
10928 if (prop_flags
->insn
.is_abslit
)
10929 num
|= XTENSA_PROP_INSN_ABSLIT
;
10931 if (prop_flags
->is_align
)
10933 num
|= XTENSA_PROP_ALIGN
;
10934 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
10942 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
10943 const frag_flags
*prop_flags_2
)
10945 /* Cannot combine with an end marker. */
10947 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
10949 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
10951 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
10954 if (prop_flags_1
->is_insn
)
10956 /* Properties of the beginning of the frag. */
10957 if (prop_flags_2
->insn
.is_loop_target
)
10959 if (prop_flags_2
->insn
.is_branch_target
)
10961 if (prop_flags_1
->insn
.is_no_density
!=
10962 prop_flags_2
->insn
.is_no_density
)
10964 if (prop_flags_1
->is_no_transform
!=
10965 prop_flags_2
->is_no_transform
)
10967 if (prop_flags_1
->insn
.is_no_reorder
!=
10968 prop_flags_2
->insn
.is_no_reorder
)
10970 if (prop_flags_1
->insn
.is_abslit
!=
10971 prop_flags_2
->insn
.is_abslit
)
10975 if (prop_flags_1
->is_align
)
10983 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
10986 unsigned align_bits
;
10988 if (!xt_block
->flags
.is_align
)
10989 return xt_block
->size
;
10991 end_addr
= xt_block
->offset
+ xt_block
->size
;
10992 align_bits
= xt_block
->flags
.alignment
;
10993 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
10994 return end_addr
- xt_block
->offset
;
10999 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
11000 const xtensa_block_info
*xt_block_2
)
11002 if (xt_block
->sec
!= xt_block_2
->sec
)
11004 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
11005 != xt_block_2
->offset
)
11008 if (xt_block_2
->size
== 0
11009 && (!xt_block_2
->flags
.is_unreachable
11010 || xt_block
->flags
.is_unreachable
))
11012 if (xt_block_2
->flags
.is_align
11013 && xt_block
->flags
.is_align
)
11015 /* Nothing needed. */
11016 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
11021 if (xt_block_2
->flags
.is_align
)
11023 /* Push alignment to previous entry. */
11024 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
11025 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
11030 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
11031 &xt_block_2
->flags
))
11034 xt_block
->size
+= xt_block_2
->size
;
11036 if (xt_block_2
->flags
.is_align
)
11038 xt_block
->flags
.is_align
= TRUE
;
11039 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
11047 add_xt_prop_frags (segT sec
,
11048 xtensa_block_info
**xt_block
,
11049 frag_flags_fn property_function
)
11053 /* Build it if needed. */
11054 while (*xt_block
!= NULL
)
11056 xt_block
= &(*xt_block
)->next
;
11058 /* We are either at NULL at the beginning or at the end. */
11060 /* Walk through the frags. */
11061 if (seg_info (sec
)->frchainP
)
11063 for (fragP
= seg_info (sec
)->frchainP
->frch_root
; fragP
;
11064 fragP
= fragP
->fr_next
)
11066 xtensa_block_info tmp_block
;
11067 tmp_block
.sec
= sec
;
11068 tmp_block
.offset
= fragP
->fr_address
;
11069 tmp_block
.size
= fragP
->fr_fix
;
11070 tmp_block
.next
= NULL
;
11071 property_function (fragP
, &tmp_block
.flags
);
11073 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
11074 /* && fragP->fr_fix != 0) */
11076 if ((*xt_block
) == NULL
11077 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
11079 xtensa_block_info
*new_block
;
11080 if ((*xt_block
) != NULL
)
11081 xt_block
= &(*xt_block
)->next
;
11082 new_block
= (xtensa_block_info
*)
11083 xmalloc (sizeof (xtensa_block_info
));
11084 *new_block
= tmp_block
;
11085 *xt_block
= new_block
;
11093 /* op_placement_info_table */
11095 /* op_placement_info makes it easier to determine which
11096 ops can go in which slots. */
11099 init_op_placement_info_table (void)
11101 xtensa_isa isa
= xtensa_default_isa
;
11102 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
11103 xtensa_opcode opcode
;
11106 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
11108 op_placement_table
= (op_placement_info_table
)
11109 xmalloc (sizeof (op_placement_info
) * num_opcodes
);
11110 gas_assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
11112 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
11114 op_placement_info
*opi
= &op_placement_table
[opcode
];
11115 /* FIXME: Make tinsn allocation dynamic. */
11116 if (xtensa_opcode_num_operands (isa
, opcode
) > MAX_INSN_ARGS
)
11117 as_fatal (_("too many operands in instruction"));
11118 opi
->narrowest
= XTENSA_UNDEFINED
;
11119 opi
->narrowest_size
= 0x7F;
11120 opi
->narrowest_slot
= 0;
11122 opi
->num_formats
= 0;
11124 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
11126 opi
->slots
[fmt
] = 0;
11127 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
11129 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
11131 int fmt_length
= xtensa_format_length (isa
, fmt
);
11133 set_bit (fmt
, opi
->formats
);
11134 set_bit (slot
, opi
->slots
[fmt
]);
11135 if (fmt_length
< opi
->narrowest_size
11136 || (fmt_length
== opi
->narrowest_size
11137 && (xtensa_format_num_slots (isa
, fmt
)
11138 < xtensa_format_num_slots (isa
,
11141 opi
->narrowest
= fmt
;
11142 opi
->narrowest_size
= fmt_length
;
11143 opi
->narrowest_slot
= slot
;
11148 opi
->num_formats
++;
11151 xtensa_insnbuf_free (isa
, ibuf
);
11156 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
11158 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
11162 /* If the opcode is available in a single slot format, return its size. */
11165 xg_get_single_size (xtensa_opcode opcode
)
11167 return op_placement_table
[opcode
].narrowest_size
;
11171 static xtensa_format
11172 xg_get_single_format (xtensa_opcode opcode
)
11174 return op_placement_table
[opcode
].narrowest
;
11179 xg_get_single_slot (xtensa_opcode opcode
)
11181 return op_placement_table
[opcode
].narrowest_slot
;
11185 /* Instruction Stack Functions (from "xtensa-istack.h"). */
11188 istack_init (IStack
*stack
)
11190 memset (stack
, 0, sizeof (IStack
));
11196 istack_empty (IStack
*stack
)
11198 return (stack
->ninsn
== 0);
11203 istack_full (IStack
*stack
)
11205 return (stack
->ninsn
== MAX_ISTACK
);
11209 /* Return a pointer to the top IStack entry.
11210 It is an error to call this if istack_empty () is TRUE. */
11213 istack_top (IStack
*stack
)
11215 int rec
= stack
->ninsn
- 1;
11216 gas_assert (!istack_empty (stack
));
11217 return &stack
->insn
[rec
];
11221 /* Add a new TInsn to an IStack.
11222 It is an error to call this if istack_full () is TRUE. */
11225 istack_push (IStack
*stack
, TInsn
*insn
)
11227 int rec
= stack
->ninsn
;
11228 gas_assert (!istack_full (stack
));
11229 stack
->insn
[rec
] = *insn
;
11234 /* Clear space for the next TInsn on the IStack and return a pointer
11235 to it. It is an error to call this if istack_full () is TRUE. */
11238 istack_push_space (IStack
*stack
)
11240 int rec
= stack
->ninsn
;
11242 gas_assert (!istack_full (stack
));
11243 insn
= &stack
->insn
[rec
];
11250 /* Remove the last pushed instruction. It is an error to call this if
11251 istack_empty () returns TRUE. */
11254 istack_pop (IStack
*stack
)
11256 int rec
= stack
->ninsn
- 1;
11257 gas_assert (!istack_empty (stack
));
11259 tinsn_init (&stack
->insn
[rec
]);
11263 /* TInsn functions. */
11266 tinsn_init (TInsn
*dst
)
11268 memset (dst
, 0, sizeof (TInsn
));
11272 /* Return TRUE if ANY of the operands in the insn are symbolic. */
11275 tinsn_has_symbolic_operands (const TInsn
*insn
)
11278 int n
= insn
->ntok
;
11280 gas_assert (insn
->insn_type
== ITYPE_INSN
);
11282 for (i
= 0; i
< n
; ++i
)
11284 switch (insn
->tok
[i
].X_op
)
11298 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
11300 xtensa_isa isa
= xtensa_default_isa
;
11302 int n
= insn
->ntok
;
11304 gas_assert (insn
->insn_type
== ITYPE_INSN
);
11306 for (i
= 0; i
< n
; ++i
)
11308 switch (insn
->tok
[i
].X_op
)
11316 /* Errors for these types are caught later. */
11321 /* Symbolic immediates are only allowed on the last immediate
11322 operand. At this time, CONST16 is the only opcode where we
11323 support non-PC-relative relocations. */
11324 if (i
!= get_relaxable_immed (insn
->opcode
)
11325 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
11326 && insn
->opcode
!= xtensa_const16_opcode
))
11328 as_bad (_("invalid symbolic operand"));
11337 /* For assembly code with complex expressions (e.g. subtraction),
11338 we have to build them in the literal pool so that
11339 their results are calculated correctly after relaxation.
11340 The relaxation only handles expressions that
11341 boil down to SYMBOL + OFFSET. */
11344 tinsn_has_complex_operands (const TInsn
*insn
)
11347 int n
= insn
->ntok
;
11348 gas_assert (insn
->insn_type
== ITYPE_INSN
);
11349 for (i
= 0; i
< n
; ++i
)
11351 switch (insn
->tok
[i
].X_op
)
11367 /* Encode a TInsn opcode and its constant operands into slotbuf.
11368 Return TRUE if there is a symbol in the immediate field. This
11369 function assumes that:
11370 1) The number of operands are correct.
11371 2) The insn_type is ITYPE_INSN.
11372 3) The opcode can be encoded in the specified format and slot.
11373 4) Operands are either O_constant or O_symbol, and all constants fit. */
11376 tinsn_to_slotbuf (xtensa_format fmt
,
11379 xtensa_insnbuf slotbuf
)
11381 xtensa_isa isa
= xtensa_default_isa
;
11382 xtensa_opcode opcode
= tinsn
->opcode
;
11383 bfd_boolean has_fixup
= FALSE
;
11384 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11387 gas_assert (tinsn
->insn_type
== ITYPE_INSN
);
11388 if (noperands
!= tinsn
->ntok
)
11389 as_fatal (_("operand number mismatch"));
11391 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
11393 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
11394 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
11398 for (i
= 0; i
< noperands
; i
++)
11400 expressionS
*exp
= &tinsn
->tok
[i
];
11409 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11411 /* The register number has already been checked in
11412 expression_maybe_register, so we don't need to check here. */
11413 opnd_value
= exp
->X_add_number
;
11414 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11415 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
11418 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
11422 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11424 as_where (&file_name
, &line
);
11425 /* It is a constant and we called this function
11426 then we have to try to fit it. */
11427 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
11428 exp
->X_add_number
, file_name
, line
);
11441 /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded
11442 into a multi-slot instruction, fill the other slots with NOPs.
11443 Return TRUE if there is a symbol in the immediate field. See also the
11444 assumptions listed for tinsn_to_slotbuf. */
11447 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
11449 static xtensa_insnbuf slotbuf
= 0;
11450 static vliw_insn vinsn
;
11451 xtensa_isa isa
= xtensa_default_isa
;
11452 bfd_boolean has_fixup
= FALSE
;
11457 slotbuf
= xtensa_insnbuf_alloc (isa
);
11458 xg_init_vinsn (&vinsn
);
11461 xg_clear_vinsn (&vinsn
);
11463 bundle_tinsn (tinsn
, &vinsn
);
11465 xtensa_format_encode (isa
, vinsn
.format
, insnbuf
);
11467 for (i
= 0; i
< vinsn
.num_slots
; i
++)
11469 /* Only one slot may have a fix-up because the rest contains NOPs. */
11471 tinsn_to_slotbuf (vinsn
.format
, i
, &vinsn
.slots
[i
], vinsn
.slotbuf
[i
]);
11472 xtensa_format_set_slot (isa
, vinsn
.format
, i
, insnbuf
, vinsn
.slotbuf
[i
]);
11479 /* Check the instruction arguments. Return TRUE on failure. */
11482 tinsn_check_arguments (const TInsn
*insn
)
11484 xtensa_isa isa
= xtensa_default_isa
;
11485 xtensa_opcode opcode
= insn
->opcode
;
11486 xtensa_regfile t1_regfile
, t2_regfile
;
11487 int t1_reg
, t2_reg
;
11488 int t1_base_reg
, t1_last_reg
;
11489 int t2_base_reg
, t2_last_reg
;
11490 char t1_inout
, t2_inout
;
11493 if (opcode
== XTENSA_UNDEFINED
)
11495 as_bad (_("invalid opcode"));
11499 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
11501 as_bad (_("too few operands"));
11505 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
11507 as_bad (_("too many operands"));
11511 /* Check registers. */
11512 for (j
= 0; j
< insn
->ntok
; j
++)
11514 if (xtensa_operand_is_register (isa
, insn
->opcode
, j
) != 1)
11517 t2_regfile
= xtensa_operand_regfile (isa
, insn
->opcode
, j
);
11518 t2_base_reg
= insn
->tok
[j
].X_add_number
;
11520 = t2_base_reg
+ xtensa_operand_num_regs (isa
, insn
->opcode
, j
);
11522 for (i
= 0; i
< insn
->ntok
; i
++)
11527 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) != 1)
11530 t1_regfile
= xtensa_operand_regfile (isa
, insn
->opcode
, i
);
11532 if (t1_regfile
!= t2_regfile
)
11535 t1_inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
11536 t2_inout
= xtensa_operand_inout (isa
, insn
->opcode
, j
);
11538 t1_base_reg
= insn
->tok
[i
].X_add_number
;
11539 t1_last_reg
= (t1_base_reg
11540 + xtensa_operand_num_regs (isa
, insn
->opcode
, i
));
11542 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
11544 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
11546 if (t1_reg
!= t2_reg
)
11549 if (t1_inout
!= 'i' && t2_inout
!= 'i')
11551 as_bad (_("multiple writes to the same register"));
11562 /* Load an instruction from its encoded form. */
11565 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
11569 xg_init_vinsn (&vinsn
);
11570 vinsn_from_chars (&vinsn
, f
);
11572 *tinsn
= vinsn
.slots
[slot
];
11573 xg_free_vinsn (&vinsn
);
11578 tinsn_from_insnbuf (TInsn
*tinsn
,
11579 xtensa_insnbuf slotbuf
,
11584 xtensa_isa isa
= xtensa_default_isa
;
11586 /* Find the immed. */
11587 tinsn_init (tinsn
);
11588 tinsn
->insn_type
= ITYPE_INSN
;
11589 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
11590 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
11591 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
11592 for (i
= 0; i
< tinsn
->ntok
; i
++)
11594 set_expr_const (&tinsn
->tok
[i
],
11595 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
11596 tinsn
->opcode
, i
));
11601 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
11604 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
11606 xtensa_opcode opcode
= tinsn
->opcode
;
11609 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
11611 opnum
= get_relaxable_immed (opcode
);
11612 gas_assert (opnum
>= 0);
11613 set_expr_symbol_offset (&tinsn
->tok
[opnum
],
11614 fragP
->tc_frag_data
.slot_symbols
[slot
],
11615 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11617 tinsn
->extra_arg
= fragP
->tc_frag_data
.free_reg
[slot
];
11622 get_num_stack_text_bytes (IStack
*istack
)
11625 int text_bytes
= 0;
11627 for (i
= 0; i
< istack
->ninsn
; i
++)
11629 TInsn
*tinsn
= &istack
->insn
[i
];
11630 if (tinsn
->insn_type
== ITYPE_INSN
)
11631 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
11638 get_num_stack_literal_bytes (IStack
*istack
)
11643 for (i
= 0; i
< istack
->ninsn
; i
++)
11645 TInsn
*tinsn
= &istack
->insn
[i
];
11646 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
11653 /* vliw_insn functions. */
11656 xg_init_vinsn (vliw_insn
*v
)
11659 xtensa_isa isa
= xtensa_default_isa
;
11661 xg_clear_vinsn (v
);
11663 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
11664 if (v
->insnbuf
== NULL
)
11665 as_fatal (_("out of memory"));
11667 for (i
= 0; i
< config_max_slots
; i
++)
11669 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
11670 if (v
->slotbuf
[i
] == NULL
)
11671 as_fatal (_("out of memory"));
11677 xg_clear_vinsn (vliw_insn
*v
)
11681 memset (v
, 0, offsetof (vliw_insn
, slots
)
11682 + sizeof(TInsn
) * config_max_slots
);
11684 v
->format
= XTENSA_UNDEFINED
;
11686 v
->inside_bundle
= FALSE
;
11688 if (xt_saved_debug_type
!= DEBUG_NONE
)
11689 debug_type
= xt_saved_debug_type
;
11691 for (i
= 0; i
< config_max_slots
; i
++)
11692 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
11697 xg_copy_vinsn (vliw_insn
*dst
, vliw_insn
*src
)
11700 offsetof(vliw_insn
, slots
) + src
->num_slots
* sizeof(TInsn
));
11701 dst
->insnbuf
= src
->insnbuf
;
11702 memcpy (dst
->slotbuf
, src
->slotbuf
, src
->num_slots
* sizeof(xtensa_insnbuf
));
11707 vinsn_has_specific_opcodes (vliw_insn
*v
)
11711 for (i
= 0; i
< v
->num_slots
; i
++)
11713 if (v
->slots
[i
].is_specific_opcode
)
11721 xg_free_vinsn (vliw_insn
*v
)
11724 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
11725 for (i
= 0; i
< config_max_slots
; i
++)
11726 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
11730 /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic
11731 operands. See also the assumptions listed for tinsn_to_slotbuf. */
11734 vinsn_to_insnbuf (vliw_insn
*vinsn
,
11737 bfd_boolean record_fixup
)
11739 xtensa_isa isa
= xtensa_default_isa
;
11740 xtensa_format fmt
= vinsn
->format
;
11741 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
11743 bfd_boolean has_fixup
= FALSE
;
11745 xtensa_format_encode (isa
, fmt
, insnbuf
);
11747 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
11749 TInsn
*tinsn
= &vinsn
->slots
[slot
];
11750 expressionS
*extra_arg
= &tinsn
->extra_arg
;
11751 bfd_boolean tinsn_has_fixup
=
11752 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
11753 vinsn
->slotbuf
[slot
]);
11755 xtensa_format_set_slot (isa
, fmt
, slot
,
11756 insnbuf
, vinsn
->slotbuf
[slot
]);
11757 if (extra_arg
->X_op
!= O_illegal
&& extra_arg
->X_op
!= O_register
)
11759 if (vinsn
->num_slots
!= 1)
11760 as_bad (_("TLS relocation not allowed in FLIX bundle"));
11761 else if (record_fixup
)
11762 /* Instructions that generate TLS relocations should always be
11763 relaxed in the front-end. If "record_fixup" is set, then this
11764 function is being called during back-end relaxation, so flag
11765 the unexpected behavior as an error. */
11766 as_bad (_("unexpected TLS relocation"));
11768 fix_new (fragP
, frag_offset
- fragP
->fr_literal
,
11769 xtensa_format_length (isa
, fmt
),
11770 extra_arg
->X_add_symbol
, extra_arg
->X_add_number
,
11771 FALSE
, map_operator_to_reloc (extra_arg
->X_op
, FALSE
));
11773 if (tinsn_has_fixup
)
11776 xtensa_opcode opcode
= tinsn
->opcode
;
11777 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11780 for (i
= 0; i
< noperands
; i
++)
11782 expressionS
* exp
= &tinsn
->tok
[i
];
11788 if (get_relaxable_immed (opcode
) == i
)
11790 /* Add a fix record for the instruction, except if this
11791 function is being called prior to relaxation, i.e.,
11792 if record_fixup is false, and the instruction might
11793 be relaxed later. */
11795 || tinsn
->is_specific_opcode
11796 || !xg_is_relaxable_insn (tinsn
, 0))
11798 xg_add_opcode_fix (tinsn
, i
, fmt
, slot
, exp
, fragP
,
11799 frag_offset
- fragP
->fr_literal
);
11803 if (exp
->X_op
!= O_symbol
)
11804 as_bad (_("invalid operand"));
11805 tinsn
->symbol
= exp
->X_add_symbol
;
11806 tinsn
->offset
= exp
->X_add_number
;
11810 as_bad (_("symbolic operand not allowed"));
11818 as_bad (_("expression too complex"));
11830 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
11832 static xtensa_insnbuf insnbuf
= NULL
;
11833 static xtensa_insnbuf slotbuf
= NULL
;
11836 xtensa_isa isa
= xtensa_default_isa
;
11840 insnbuf
= xtensa_insnbuf_alloc (isa
);
11841 slotbuf
= xtensa_insnbuf_alloc (isa
);
11844 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) f
, 0);
11845 fmt
= xtensa_format_decode (isa
, insnbuf
);
11846 if (fmt
== XTENSA_UNDEFINED
)
11847 as_fatal (_("cannot decode instruction format"));
11848 vinsn
->format
= fmt
;
11849 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
11851 for (i
= 0; i
< vinsn
->num_slots
; i
++)
11853 TInsn
*tinsn
= &vinsn
->slots
[i
];
11854 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
11855 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
11860 /* Expression utilities. */
11862 /* Return TRUE if the expression is an integer constant. */
11865 expr_is_const (const expressionS
*s
)
11867 return (s
->X_op
== O_constant
);
11871 /* Get the expression constant.
11872 Calling this is illegal if expr_is_const () returns TRUE. */
11875 get_expr_const (const expressionS
*s
)
11877 gas_assert (expr_is_const (s
));
11878 return s
->X_add_number
;
11882 /* Set the expression to a constant value. */
11885 set_expr_const (expressionS
*s
, offsetT val
)
11887 s
->X_op
= O_constant
;
11888 s
->X_add_number
= val
;
11889 s
->X_add_symbol
= NULL
;
11890 s
->X_op_symbol
= NULL
;
11895 expr_is_register (const expressionS
*s
)
11897 return (s
->X_op
== O_register
);
11901 /* Get the expression constant.
11902 Calling this is illegal if expr_is_const () returns TRUE. */
11905 get_expr_register (const expressionS
*s
)
11907 gas_assert (expr_is_register (s
));
11908 return s
->X_add_number
;
11912 /* Set the expression to a symbol + constant offset. */
11915 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
11917 s
->X_op
= O_symbol
;
11918 s
->X_add_symbol
= sym
;
11919 s
->X_op_symbol
= NULL
; /* unused */
11920 s
->X_add_number
= offset
;
11924 /* Return TRUE if the two expressions are equal. */
11927 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
11929 if (s1
->X_op
!= s2
->X_op
)
11931 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
11933 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
11935 if (s1
->X_add_number
!= s2
->X_add_number
)
11942 copy_expr (expressionS
*dst
, const expressionS
*src
)
11944 memcpy (dst
, src
, sizeof (expressionS
));
11948 /* Support for the "--rename-section" option. */
11950 struct rename_section_struct
11954 struct rename_section_struct
*next
;
11957 static struct rename_section_struct
*section_rename
;
11960 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
11961 entries to the section_rename list. Note: Specifying multiple
11962 renamings separated by colons is not documented and is retained only
11963 for backward compatibility. */
11966 build_section_rename (const char *arg
)
11968 struct rename_section_struct
*r
;
11969 char *this_arg
= NULL
;
11970 char *next_arg
= NULL
;
11972 for (this_arg
= xstrdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
11974 char *old_name
, *new_name
;
11978 next_arg
= strchr (this_arg
, ':');
11986 old_name
= this_arg
;
11987 new_name
= strchr (this_arg
, '=');
11989 if (*old_name
== '\0')
11991 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
11994 if (!new_name
|| new_name
[1] == '\0')
11996 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
12003 /* Check for invalid section renaming. */
12004 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
12006 if (strcmp (r
->old_name
, old_name
) == 0)
12007 as_bad (_("section %s renamed multiple times"), old_name
);
12008 if (strcmp (r
->new_name
, new_name
) == 0)
12009 as_bad (_("multiple sections remapped to output section %s"),
12014 r
= (struct rename_section_struct
*)
12015 xmalloc (sizeof (struct rename_section_struct
));
12016 r
->old_name
= xstrdup (old_name
);
12017 r
->new_name
= xstrdup (new_name
);
12018 r
->next
= section_rename
;
12019 section_rename
= r
;
12025 xtensa_section_rename (char *name
)
12027 struct rename_section_struct
*r
= section_rename
;
12029 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
12031 if (strcmp (r
->old_name
, name
) == 0)
12032 return r
->new_name
;