1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
24 #include "safe-ctype.h"
25 #include "tc-xtensa.h"
27 #include "xtensa-relax.h"
28 #include "xtensa-istack.h"
29 #include "dwarf2dbg.h"
30 #include "struc-symbol.h"
31 #include "xtensa-config.h"
33 /* Provide default values for new configuration settings. */
39 #define uint32 unsigned int
42 #define int32 signed int
47 Naming conventions (used somewhat inconsistently):
48 The xtensa_ functions are exported
49 The xg_ functions are internal
51 We also have a couple of different extensibility mechanisms.
52 1) The idiom replacement:
53 This is used when a line is first parsed to
54 replace an instruction pattern with another instruction
55 It is currently limited to replacements of instructions
56 with constant operands.
57 2) The xtensa-relax.c mechanism that has stronger instruction
58 replacement patterns. When an instruction's immediate field
59 does not fit the next instruction sequence is attempted.
60 In addition, "narrow" opcodes are supported this way. */
63 /* Define characters with special meanings to GAS. */
64 const char comment_chars
[] = "#";
65 const char line_comment_chars
[] = "#";
66 const char line_separator_chars
[] = ";";
67 const char EXP_CHARS
[] = "eE";
68 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
71 /* Flags to indicate whether the hardware supports the density and
72 absolute literals options. */
74 bfd_boolean density_supported
= XCHAL_HAVE_DENSITY
;
75 bfd_boolean absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
77 /* Maximum width we would pad an unreachable frag to get alignment. */
78 #define UNREACHABLE_MAX_WIDTH 8
80 static vliw_insn cur_vinsn
;
82 unsigned xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
84 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
86 /* Some functions are only valid in the front end. This variable
87 allows us to assert that we haven't crossed over into the
89 static bfd_boolean past_xtensa_end
= FALSE
;
91 /* Flags for properties of the last instruction in a segment. */
92 #define FLAG_IS_A0_WRITER 0x1
93 #define FLAG_IS_BAD_LOOPEND 0x2
96 /* We define a special segment names ".literal" to place literals
97 into. The .fini and .init sections are special because they
98 contain code that is moved together by the linker. We give them
99 their own special .fini.literal and .init.literal sections. */
101 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
102 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
103 #define INIT_SECTION_NAME xtensa_section_rename (".init")
104 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
107 /* This type is used for the directive_stack to keep track of the
108 state of the literal collection pools. If lit_prefix is set, it is
109 used to determine the literal section names; otherwise, the literal
110 sections are determined based on the current text section. The
111 lit_seg and lit4_seg fields cache these literal sections, with the
112 current_text_seg field used a tag to indicate whether the cached
115 typedef struct lit_state_struct
118 segT current_text_seg
;
123 static lit_state default_lit_sections
;
126 /* We keep a list of literal segments. The seg_list type is the node
127 for this list. The literal_head pointer is the head of the list,
128 with the literal_head_h dummy node at the start. */
130 typedef struct seg_list_struct
132 struct seg_list_struct
*next
;
136 static seg_list literal_head_h
;
137 static seg_list
*literal_head
= &literal_head_h
;
140 /* Lists of symbols. We keep a list of symbols that label the current
141 instruction, so that we can adjust the symbols when inserting alignment
142 for various instructions. We also keep a list of all the symbols on
143 literals, so that we can fix up those symbols when the literals are
144 later moved into the text sections. */
146 typedef struct sym_list_struct
148 struct sym_list_struct
*next
;
152 static sym_list
*insn_labels
= NULL
;
153 static sym_list
*free_insn_labels
= NULL
;
154 static sym_list
*saved_insn_labels
= NULL
;
156 static sym_list
*literal_syms
;
159 /* Flags to determine whether to prefer const16 or l32r
160 if both options are available. */
161 int prefer_const16
= 0;
164 /* Global flag to indicate when we are emitting literals. */
165 int generating_literals
= 0;
167 /* The following PROPERTY table definitions are copied from
168 <elf/xtensa.h> and must be kept in sync with the code there. */
170 /* Flags in the property tables to specify whether blocks of memory
171 are literals, instructions, data, or unreachable. For
172 instructions, blocks that begin loop targets and branch targets are
173 designated. Blocks that do not allow density, instruction
174 reordering or transformation are also specified. Finally, for
175 branch targets, branch target alignment priority is included.
176 Alignment of the next block is specified in the current block
177 and the size of the current block does not include any fill required
178 to align to the next block. */
180 #define XTENSA_PROP_LITERAL 0x00000001
181 #define XTENSA_PROP_INSN 0x00000002
182 #define XTENSA_PROP_DATA 0x00000004
183 #define XTENSA_PROP_UNREACHABLE 0x00000008
184 /* Instruction only properties at beginning of code. */
185 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
186 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
187 /* Instruction only properties about code. */
188 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
189 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
190 /* Historically, NO_TRANSFORM was a property of instructions,
191 but it should apply to literals under certain circumstances. */
192 #define XTENSA_PROP_NO_TRANSFORM 0x00000100
194 /* Branch target alignment information. This transmits information
195 to the linker optimization about the priority of aligning a
196 particular block for branch target alignment: None, low priority,
197 high priority, or required. These only need to be checked in
198 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
201 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
202 case XTENSA_PROP_BT_ALIGN_NONE:
203 case XTENSA_PROP_BT_ALIGN_LOW:
204 case XTENSA_PROP_BT_ALIGN_HIGH:
205 case XTENSA_PROP_BT_ALIGN_REQUIRE:
207 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
209 /* No branch target alignment. */
210 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
211 /* Low priority branch target alignment. */
212 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
213 /* High priority branch target alignment. */
214 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
215 /* Required branch target alignment. */
216 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
218 #define GET_XTENSA_PROP_BT_ALIGN(flag) \
219 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
220 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
221 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
222 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
225 /* Alignment is specified in the block BEFORE the one that needs
226 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
227 get the required alignment specified as a power of 2. Use
228 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
229 alignment. Be careful of side effects since the SET will evaluate
230 flags twice. Also, note that the SIZE of a block in the property
231 table does not include the alignment size, so the alignment fill
232 must be calculated to determine if two blocks are contiguous.
233 TEXT_ALIGN is not currently implemented but is a placeholder for a
234 possible future implementation. */
236 #define XTENSA_PROP_ALIGN 0x00000800
238 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
240 #define GET_XTENSA_PROP_ALIGNMENT(flag) \
241 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
242 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
243 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
244 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
246 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
249 /* Structure for saving instruction and alignment per-fragment data
250 that will be written to the object file. This structure is
251 equivalent to the actual data that will be written out to the file
252 but is easier to use. We provide a conversion to file flags
253 in frag_flags_to_number. */
255 typedef struct frag_flags_struct frag_flags
;
257 struct frag_flags_struct
259 /* is_literal should only be used after xtensa_move_literals.
260 If you need to check if you are generating a literal fragment,
261 then use the generating_literals global. */
263 unsigned is_literal
: 1;
264 unsigned is_insn
: 1;
265 unsigned is_data
: 1;
266 unsigned is_unreachable
: 1;
268 /* is_specific_opcode implies no_transform. */
269 unsigned is_no_transform
: 1;
273 unsigned is_loop_target
: 1;
274 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
275 unsigned bt_align_priority
: 2;
277 unsigned is_no_density
: 1;
278 /* no_longcalls flag does not need to be placed in the object file. */
280 unsigned is_no_reorder
: 1;
282 /* Uses absolute literal addressing for l32r. */
283 unsigned is_abslit
: 1;
285 unsigned is_align
: 1;
286 unsigned alignment
: 5;
290 /* Structure for saving information about a block of property data
291 for frags that have the same flags. */
292 struct xtensa_block_info_struct
298 struct xtensa_block_info_struct
*next
;
302 /* Structure for saving the current state before emitting literals. */
303 typedef struct emit_state_struct
308 int generating_literals
;
312 /* Opcode placement information */
314 typedef unsigned long long bitfield
;
315 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
316 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
317 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
319 #define MAX_FORMATS 32
321 typedef struct op_placement_info_struct
324 /* A number describing how restrictive the issue is for this
325 opcode. For example, an opcode that fits lots of different
326 formats has a high freedom, as does an opcode that fits
327 only one format but many slots in that format. The most
328 restrictive is the opcode that fits only one slot in one
331 xtensa_format narrowest
;
335 /* formats is a bitfield with the Nth bit set
336 if the opcode fits in the Nth xtensa_format. */
339 /* slots[N]'s Mth bit is set if the op fits in the
340 Mth slot of the Nth xtensa_format. */
341 bitfield slots
[MAX_FORMATS
];
343 /* A count of the number of slots in a given format
344 an op can fit (i.e., the bitcount of the slot field above). */
345 char slots_in_format
[MAX_FORMATS
];
347 } op_placement_info
, *op_placement_info_table
;
349 op_placement_info_table op_placement_table
;
352 /* Extra expression types. */
354 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
355 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
356 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
358 struct suffix_reloc_map
362 bfd_reloc_code_real_type reloc
;
363 unsigned char operator;
366 #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op }
368 static struct suffix_reloc_map suffix_relocs
[] =
370 SUFFIX_MAP ("l", BFD_RELOC_LO16
, O_lo16
),
371 SUFFIX_MAP ("h", BFD_RELOC_HI16
, O_hi16
),
372 SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT
, O_pltrel
),
373 { (char *) 0, 0, BFD_RELOC_UNUSED
, 0 }
387 directive_literal_prefix
,
389 directive_absolute_literals
,
390 directive_last_directive
396 bfd_boolean can_be_negated
;
399 const directive_infoS directive_info
[] =
402 { "literal", FALSE
},
404 { "transform", TRUE
},
405 { "freeregs", FALSE
},
406 { "longcalls", TRUE
},
407 { "literal_prefix", FALSE
},
408 { "schedule", TRUE
},
409 { "absolute-literals", TRUE
}
412 bfd_boolean directive_state
[] =
416 #if !XCHAL_HAVE_DENSITY
421 TRUE
, /* transform */
422 FALSE
, /* freeregs */
423 FALSE
, /* longcalls */
424 FALSE
, /* literal_prefix */
425 FALSE
, /* schedule */
426 #if XSHAL_USE_ABSOLUTE_LITERALS
427 TRUE
/* absolute_literals */
429 FALSE
/* absolute_literals */
434 /* Directive functions. */
436 static void xtensa_begin_directive (int);
437 static void xtensa_end_directive (int);
438 static void xtensa_literal_prefix (void);
439 static void xtensa_literal_position (int);
440 static void xtensa_literal_pseudo (int);
441 static void xtensa_frequency_pseudo (int);
442 static void xtensa_elf_cons (int);
444 /* Parsing and Idiom Translation. */
446 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
448 /* Various Other Internal Functions. */
450 extern bfd_boolean
xg_is_single_relaxable_insn (TInsn
*, TInsn
*, bfd_boolean
);
451 static bfd_boolean
xg_build_to_insn (TInsn
*, TInsn
*, BuildInstr
*);
452 static void xtensa_mark_literal_pool_location (void);
453 static addressT
get_expanded_loop_offset (xtensa_opcode
);
454 static fragS
*get_literal_pool_location (segT
);
455 static void set_literal_pool_location (segT
, fragS
*);
456 static void xtensa_set_frag_assembly_state (fragS
*);
457 static void finish_vinsn (vliw_insn
*);
458 static bfd_boolean
emit_single_op (TInsn
*);
459 static int total_frag_text_expansion (fragS
*);
461 /* Alignment Functions. */
463 static int get_text_align_power (unsigned);
464 static int get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
465 static int branch_align_power (segT
);
467 /* Helpers for xtensa_relax_frag(). */
469 static long relax_frag_add_nop (fragS
*);
471 /* Accessors for additional per-subsegment information. */
473 static unsigned get_last_insn_flags (segT
, subsegT
);
474 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
475 static float get_subseg_total_freq (segT
, subsegT
);
476 static float get_subseg_target_freq (segT
, subsegT
);
477 static void set_subseg_freq (segT
, subsegT
, float, float);
479 /* Segment list functions. */
481 static void xtensa_move_literals (void);
482 static void xtensa_reorder_segments (void);
483 static void xtensa_switch_to_literal_fragment (emit_state
*);
484 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
485 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
486 static void xtensa_restore_emit_state (emit_state
*);
487 static segT
cache_literal_section (bfd_boolean
);
489 /* Import from elf32-xtensa.c in BFD library. */
491 extern asection
*xtensa_get_property_section (asection
*, const char *);
493 /* op_placement_info functions. */
495 static void init_op_placement_info_table (void);
496 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
497 static int xg_get_single_size (xtensa_opcode
);
498 static xtensa_format
xg_get_single_format (xtensa_opcode
);
499 static int xg_get_single_slot (xtensa_opcode
);
501 /* TInsn and IStack functions. */
503 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
504 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
505 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
506 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
507 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
508 static void tinsn_from_chars (TInsn
*, char *, int);
509 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
510 static int get_num_stack_text_bytes (IStack
*);
511 static int get_num_stack_literal_bytes (IStack
*);
513 /* vliw_insn functions. */
515 static void xg_init_vinsn (vliw_insn
*);
516 static void xg_clear_vinsn (vliw_insn
*);
517 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
518 static void xg_free_vinsn (vliw_insn
*);
519 static bfd_boolean vinsn_to_insnbuf
520 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
521 static void vinsn_from_chars (vliw_insn
*, char *);
523 /* Expression Utilities. */
525 bfd_boolean
expr_is_const (const expressionS
*);
526 offsetT
get_expr_const (const expressionS
*);
527 void set_expr_const (expressionS
*, offsetT
);
528 bfd_boolean
expr_is_register (const expressionS
*);
529 offsetT
get_expr_register (const expressionS
*);
530 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
531 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
532 static void copy_expr (expressionS
*, const expressionS
*);
534 /* Section renaming. */
536 static void build_section_rename (const char *);
539 /* ISA imported from bfd. */
540 extern xtensa_isa xtensa_default_isa
;
542 extern int target_big_endian
;
544 static xtensa_opcode xtensa_addi_opcode
;
545 static xtensa_opcode xtensa_addmi_opcode
;
546 static xtensa_opcode xtensa_call0_opcode
;
547 static xtensa_opcode xtensa_call4_opcode
;
548 static xtensa_opcode xtensa_call8_opcode
;
549 static xtensa_opcode xtensa_call12_opcode
;
550 static xtensa_opcode xtensa_callx0_opcode
;
551 static xtensa_opcode xtensa_callx4_opcode
;
552 static xtensa_opcode xtensa_callx8_opcode
;
553 static xtensa_opcode xtensa_callx12_opcode
;
554 static xtensa_opcode xtensa_const16_opcode
;
555 static xtensa_opcode xtensa_entry_opcode
;
556 static xtensa_opcode xtensa_extui_opcode
;
557 static xtensa_opcode xtensa_movi_opcode
;
558 static xtensa_opcode xtensa_movi_n_opcode
;
559 static xtensa_opcode xtensa_isync_opcode
;
560 static xtensa_opcode xtensa_jx_opcode
;
561 static xtensa_opcode xtensa_l32r_opcode
;
562 static xtensa_opcode xtensa_loop_opcode
;
563 static xtensa_opcode xtensa_loopnez_opcode
;
564 static xtensa_opcode xtensa_loopgtz_opcode
;
565 static xtensa_opcode xtensa_nop_opcode
;
566 static xtensa_opcode xtensa_nop_n_opcode
;
567 static xtensa_opcode xtensa_or_opcode
;
568 static xtensa_opcode xtensa_ret_opcode
;
569 static xtensa_opcode xtensa_ret_n_opcode
;
570 static xtensa_opcode xtensa_retw_opcode
;
571 static xtensa_opcode xtensa_retw_n_opcode
;
572 static xtensa_opcode xtensa_rsr_lcount_opcode
;
573 static xtensa_opcode xtensa_waiti_opcode
;
576 /* Command-line Options. */
578 bfd_boolean use_literal_section
= TRUE
;
579 static bfd_boolean align_targets
= TRUE
;
580 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
581 static bfd_boolean has_a0_b_retw
= FALSE
;
582 static bfd_boolean workaround_a0_b_retw
= FALSE
;
583 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
584 static bfd_boolean workaround_short_loop
= FALSE
;
585 static bfd_boolean maybe_has_short_loop
= FALSE
;
586 static bfd_boolean workaround_close_loop_end
= FALSE
;
587 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
588 static bfd_boolean enforce_three_byte_loop_align
= FALSE
;
590 /* When workaround_short_loops is TRUE, all loops with early exits must
591 have at least 3 instructions. workaround_all_short_loops is a modifier
592 to the workaround_short_loop flag. In addition to the
593 workaround_short_loop actions, all straightline loopgtz and loopnez
594 must have at least 3 instructions. */
596 static bfd_boolean workaround_all_short_loops
= FALSE
;
600 xtensa_setup_hw_workarounds (int earliest
, int latest
)
602 if (earliest
> latest
)
603 as_fatal (_("illegal range of target hardware versions"));
605 /* Enable all workarounds for pre-T1050.0 hardware. */
606 if (earliest
< 105000 || latest
< 105000)
608 workaround_a0_b_retw
|= TRUE
;
609 workaround_b_j_loop_end
|= TRUE
;
610 workaround_short_loop
|= TRUE
;
611 workaround_close_loop_end
|= TRUE
;
612 workaround_all_short_loops
|= TRUE
;
613 enforce_three_byte_loop_align
= TRUE
;
620 option_density
= OPTION_MD_BASE
,
627 option_no_link_relax
,
635 option_text_section_literals
,
636 option_no_text_section_literals
,
638 option_absolute_literals
,
639 option_no_absolute_literals
,
641 option_align_targets
,
642 option_no_align_targets
,
644 option_warn_unaligned_targets
,
649 option_workaround_a0_b_retw
,
650 option_no_workaround_a0_b_retw
,
652 option_workaround_b_j_loop_end
,
653 option_no_workaround_b_j_loop_end
,
655 option_workaround_short_loop
,
656 option_no_workaround_short_loop
,
658 option_workaround_all_short_loops
,
659 option_no_workaround_all_short_loops
,
661 option_workaround_close_loop_end
,
662 option_no_workaround_close_loop_end
,
664 option_no_workarounds
,
666 option_rename_section_name
,
669 option_prefer_const16
,
671 option_target_hardware
674 const char *md_shortopts
= "";
676 struct option md_longopts
[] =
678 { "density", no_argument
, NULL
, option_density
},
679 { "no-density", no_argument
, NULL
, option_no_density
},
681 /* Both "relax" and "generics" are deprecated and treated as equivalent
682 to the "transform" option. */
683 { "relax", no_argument
, NULL
, option_relax
},
684 { "no-relax", no_argument
, NULL
, option_no_relax
},
685 { "generics", no_argument
, NULL
, option_generics
},
686 { "no-generics", no_argument
, NULL
, option_no_generics
},
688 { "transform", no_argument
, NULL
, option_transform
},
689 { "no-transform", no_argument
, NULL
, option_no_transform
},
690 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
691 { "no-text-section-literals", no_argument
, NULL
,
692 option_no_text_section_literals
},
693 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
694 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
695 /* This option was changed from -align-target to -target-align
696 because it conflicted with the "-al" option. */
697 { "target-align", no_argument
, NULL
, option_align_targets
},
698 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
699 { "warn-unaligned-targets", no_argument
, NULL
,
700 option_warn_unaligned_targets
},
701 { "longcalls", no_argument
, NULL
, option_longcalls
},
702 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
704 { "no-workaround-a0-b-retw", no_argument
, NULL
,
705 option_no_workaround_a0_b_retw
},
706 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
708 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
709 option_no_workaround_b_j_loop_end
},
710 { "workaround-b-j-loop-end", no_argument
, NULL
,
711 option_workaround_b_j_loop_end
},
713 { "no-workaround-short-loops", no_argument
, NULL
,
714 option_no_workaround_short_loop
},
715 { "workaround-short-loops", no_argument
, NULL
,
716 option_workaround_short_loop
},
718 { "no-workaround-all-short-loops", no_argument
, NULL
,
719 option_no_workaround_all_short_loops
},
720 { "workaround-all-short-loop", no_argument
, NULL
,
721 option_workaround_all_short_loops
},
723 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
724 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
726 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
728 { "no-workaround-close-loop-end", no_argument
, NULL
,
729 option_no_workaround_close_loop_end
},
730 { "workaround-close-loop-end", no_argument
, NULL
,
731 option_workaround_close_loop_end
},
733 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
735 { "link-relax", no_argument
, NULL
, option_link_relax
},
736 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
738 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
740 { NULL
, no_argument
, NULL
, 0 }
743 size_t md_longopts_size
= sizeof md_longopts
;
747 md_parse_option (int c
, char *arg
)
752 as_warn (_("--density option is ignored"));
754 case option_no_density
:
755 as_warn (_("--no-density option is ignored"));
757 case option_link_relax
:
760 case option_no_link_relax
:
763 case option_generics
:
764 as_warn (_("--generics is deprecated; use --transform instead"));
765 return md_parse_option (option_transform
, arg
);
766 case option_no_generics
:
767 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
768 return md_parse_option (option_no_transform
, arg
);
770 as_warn (_("--relax is deprecated; use --transform instead"));
771 return md_parse_option (option_transform
, arg
);
772 case option_no_relax
:
773 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
774 return md_parse_option (option_no_transform
, arg
);
775 case option_longcalls
:
776 directive_state
[directive_longcalls
] = TRUE
;
778 case option_no_longcalls
:
779 directive_state
[directive_longcalls
] = FALSE
;
781 case option_text_section_literals
:
782 use_literal_section
= FALSE
;
784 case option_no_text_section_literals
:
785 use_literal_section
= TRUE
;
787 case option_absolute_literals
:
788 if (!absolute_literals_supported
)
790 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
793 directive_state
[directive_absolute_literals
] = TRUE
;
795 case option_no_absolute_literals
:
796 directive_state
[directive_absolute_literals
] = FALSE
;
799 case option_workaround_a0_b_retw
:
800 workaround_a0_b_retw
= TRUE
;
802 case option_no_workaround_a0_b_retw
:
803 workaround_a0_b_retw
= FALSE
;
805 case option_workaround_b_j_loop_end
:
806 workaround_b_j_loop_end
= TRUE
;
808 case option_no_workaround_b_j_loop_end
:
809 workaround_b_j_loop_end
= FALSE
;
812 case option_workaround_short_loop
:
813 workaround_short_loop
= TRUE
;
815 case option_no_workaround_short_loop
:
816 workaround_short_loop
= FALSE
;
819 case option_workaround_all_short_loops
:
820 workaround_all_short_loops
= TRUE
;
822 case option_no_workaround_all_short_loops
:
823 workaround_all_short_loops
= FALSE
;
826 case option_workaround_close_loop_end
:
827 workaround_close_loop_end
= TRUE
;
829 case option_no_workaround_close_loop_end
:
830 workaround_close_loop_end
= FALSE
;
833 case option_no_workarounds
:
834 workaround_a0_b_retw
= FALSE
;
835 workaround_b_j_loop_end
= FALSE
;
836 workaround_short_loop
= FALSE
;
837 workaround_all_short_loops
= FALSE
;
838 workaround_close_loop_end
= FALSE
;
841 case option_align_targets
:
842 align_targets
= TRUE
;
844 case option_no_align_targets
:
845 align_targets
= FALSE
;
848 case option_warn_unaligned_targets
:
849 warn_unaligned_branch_targets
= TRUE
;
852 case option_rename_section_name
:
853 build_section_rename (arg
);
857 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
858 should be emitted or not. FIXME: Not implemented. */
861 case option_prefer_l32r
:
863 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
867 case option_prefer_const16
:
869 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
873 case option_target_hardware
:
875 int earliest
, latest
= 0;
876 if (*arg
== 0 || *arg
== '-')
877 as_fatal (_("invalid target hardware version"));
879 earliest
= strtol (arg
, &arg
, 0);
883 else if (*arg
== '-')
886 as_fatal (_("invalid target hardware version"));
887 latest
= strtol (arg
, &arg
, 0);
890 as_fatal (_("invalid target hardware version"));
892 xtensa_setup_hw_workarounds (earliest
, latest
);
896 case option_transform
:
897 /* This option has no affect other than to use the defaults,
898 which are already set. */
901 case option_no_transform
:
902 /* This option turns off all transformations of any kind.
903 However, because we want to preserve the state of other
904 directives, we only change its own field. Thus, before
905 you perform any transformation, always check if transform
906 is available. If you use the functions we provide for this
907 purpose, you will be ok. */
908 directive_state
[directive_transform
] = FALSE
;
918 md_show_usage (FILE *stream
)
922 --[no-]text-section-literals\n\
923 [Do not] put literals in the text section\n\
924 --[no-]absolute-literals\n\
925 [Do not] default to use non-PC-relative literals\n\
926 --[no-]target-align [Do not] try to align branch targets\n\
927 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
928 --[no-]transform [Do not] transform instructions\n\
929 --rename-section old=new Rename section 'old' to 'new'\n", stream
);
933 /* Functions related to the list of current label symbols. */
936 xtensa_add_insn_label (symbolS
*sym
)
940 if (!free_insn_labels
)
941 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
944 l
= free_insn_labels
;
945 free_insn_labels
= l
->next
;
949 l
->next
= insn_labels
;
955 xtensa_clear_insn_labels (void)
959 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
967 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
)
971 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
973 symbolS
*lit_sym
= lit
->sym
;
974 S_SET_VALUE (lit_sym
, new_offset
);
975 symbol_set_frag (lit_sym
, new_frag
);
980 /* Directive data and functions. */
982 typedef struct state_stackS_struct
984 directiveE directive
;
986 bfd_boolean old_state
;
990 struct state_stackS_struct
*prev
;
993 state_stackS
*directive_state_stack
;
995 const pseudo_typeS md_pseudo_table
[] =
997 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
998 { "literal_position", xtensa_literal_position
, 0 },
999 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
1000 { "long", xtensa_elf_cons
, 4 },
1001 { "word", xtensa_elf_cons
, 4 },
1002 { "short", xtensa_elf_cons
, 2 },
1003 { "begin", xtensa_begin_directive
, 0 },
1004 { "end", xtensa_end_directive
, 0 },
1005 { "literal", xtensa_literal_pseudo
, 0 },
1006 { "frequency", xtensa_frequency_pseudo
, 0 },
1012 use_transform (void)
1014 /* After md_end, you should be checking frag by frag, rather
1015 than state directives. */
1016 assert (!past_xtensa_end
);
1017 return directive_state
[directive_transform
];
1022 do_align_targets (void)
1024 /* Do not use this function after md_end; just look at align_targets
1025 instead. There is no target-align directive, so alignment is either
1026 enabled for all frags or not done at all. */
1027 assert (!past_xtensa_end
);
1028 return align_targets
&& use_transform ();
1033 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1037 state_stackS
*stack
= (state_stackS
*) xmalloc (sizeof (state_stackS
));
1039 as_where (&file
, &line
);
1041 stack
->directive
= directive
;
1042 stack
->negated
= negated
;
1043 stack
->old_state
= directive_state
[directive
];
1046 stack
->datum
= datum
;
1047 stack
->prev
= directive_state_stack
;
1048 directive_state_stack
= stack
;
1050 directive_state
[directive
] = !negated
;
1055 directive_pop (directiveE
*directive
,
1056 bfd_boolean
*negated
,
1061 state_stackS
*top
= directive_state_stack
;
1063 if (!directive_state_stack
)
1065 as_bad (_("unmatched end directive"));
1066 *directive
= directive_none
;
1070 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1071 *directive
= top
->directive
;
1072 *negated
= top
->negated
;
1075 *datum
= top
->datum
;
1076 directive_state_stack
= top
->prev
;
1082 directive_balance (void)
1084 while (directive_state_stack
)
1086 directiveE directive
;
1087 bfd_boolean negated
;
1092 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1093 as_warn_where ((char *) file
, line
,
1094 _(".begin directive with no matching .end directive"));
1100 inside_directive (directiveE dir
)
1102 state_stackS
*top
= directive_state_stack
;
1104 while (top
&& top
->directive
!= dir
)
1107 return (top
!= NULL
);
1112 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1116 char *directive_string
;
1118 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1123 input_line_pointer
+= 3;
1126 len
= strspn (input_line_pointer
,
1127 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1129 /* This code is a hack to make .begin [no-][generics|relax] exactly
1130 equivalent to .begin [no-]transform. We should remove it when
1131 we stop accepting those options. */
1133 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1135 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1136 directive_string
= "transform";
1138 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1140 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1141 directive_string
= "transform";
1144 directive_string
= input_line_pointer
;
1146 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1148 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1150 input_line_pointer
+= len
;
1151 *directive
= (directiveE
) i
;
1152 if (*negated
&& !directive_info
[i
].can_be_negated
)
1153 as_bad (_("directive %s cannot be negated"),
1154 directive_info
[i
].name
);
1159 as_bad (_("unknown directive"));
1160 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1165 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1167 directiveE directive
;
1168 bfd_boolean negated
;
1172 get_directive (&directive
, &negated
);
1173 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1175 discard_rest_of_line ();
1179 if (cur_vinsn
.inside_bundle
)
1180 as_bad (_("directives are not valid inside bundles"));
1184 case directive_literal
:
1185 if (!inside_directive (directive_literal
))
1187 /* Previous labels go with whatever follows this directive, not with
1188 the literal, so save them now. */
1189 saved_insn_labels
= insn_labels
;
1192 as_warn (_(".begin literal is deprecated; use .literal instead"));
1193 state
= (emit_state
*) xmalloc (sizeof (emit_state
));
1194 xtensa_switch_to_literal_fragment (state
);
1195 directive_push (directive_literal
, negated
, state
);
1198 case directive_literal_prefix
:
1199 /* Have to flush pending output because a movi relaxed to an l32r
1200 might produce a literal. */
1201 md_flush_pending_output ();
1202 /* Check to see if the current fragment is a literal
1203 fragment. If it is, then this operation is not allowed. */
1204 if (generating_literals
)
1206 as_bad (_("cannot set literal_prefix inside literal fragment"));
1210 /* Allocate the literal state for this section and push
1211 onto the directive stack. */
1212 ls
= xmalloc (sizeof (lit_state
));
1215 *ls
= default_lit_sections
;
1216 directive_push (directive_literal_prefix
, negated
, ls
);
1218 /* Process the new prefix. */
1219 xtensa_literal_prefix ();
1222 case directive_freeregs
:
1223 /* This information is currently unused, but we'll accept the statement
1224 and just discard the rest of the line. This won't check the syntax,
1225 but it will accept every correct freeregs directive. */
1226 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1227 directive_push (directive_freeregs
, negated
, 0);
1230 case directive_schedule
:
1231 md_flush_pending_output ();
1232 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1233 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1234 directive_push (directive_schedule
, negated
, 0);
1235 xtensa_set_frag_assembly_state (frag_now
);
1238 case directive_density
:
1239 as_warn (_(".begin [no-]density is ignored"));
1242 case directive_absolute_literals
:
1243 md_flush_pending_output ();
1244 if (!absolute_literals_supported
&& !negated
)
1246 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1249 xtensa_set_frag_assembly_state (frag_now
);
1250 directive_push (directive
, negated
, 0);
1254 md_flush_pending_output ();
1255 xtensa_set_frag_assembly_state (frag_now
);
1256 directive_push (directive
, negated
, 0);
1260 demand_empty_rest_of_line ();
1265 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1267 directiveE begin_directive
, end_directive
;
1268 bfd_boolean begin_negated
, end_negated
;
1272 emit_state
**state_ptr
;
1275 if (cur_vinsn
.inside_bundle
)
1276 as_bad (_("directives are not valid inside bundles"));
1278 get_directive (&end_directive
, &end_negated
);
1280 md_flush_pending_output ();
1282 switch (end_directive
)
1284 case (directiveE
) XTENSA_UNDEFINED
:
1285 discard_rest_of_line ();
1288 case directive_density
:
1289 as_warn (_(".end [no-]density is ignored"));
1290 demand_empty_rest_of_line ();
1293 case directive_absolute_literals
:
1294 if (!absolute_literals_supported
&& !end_negated
)
1296 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1297 demand_empty_rest_of_line ();
1306 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1307 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1308 (const void **) state_ptr
);
1310 if (begin_directive
!= directive_none
)
1312 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1314 as_bad (_("does not match begin %s%s at %s:%d"),
1315 begin_negated
? "no-" : "",
1316 directive_info
[begin_directive
].name
, file
, line
);
1320 switch (end_directive
)
1322 case directive_literal
:
1323 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1324 xtensa_restore_emit_state (state
);
1325 xtensa_set_frag_assembly_state (frag_now
);
1327 if (!inside_directive (directive_literal
))
1329 /* Restore the list of current labels. */
1330 xtensa_clear_insn_labels ();
1331 insn_labels
= saved_insn_labels
;
1335 case directive_literal_prefix
:
1336 /* Restore the default collection sections from saved state. */
1337 s
= (lit_state
*) state
;
1339 default_lit_sections
= *s
;
1341 /* Free the state storage. */
1342 free (s
->lit_prefix
);
1346 case directive_schedule
:
1347 case directive_freeregs
:
1351 xtensa_set_frag_assembly_state (frag_now
);
1357 demand_empty_rest_of_line ();
1361 /* Place an aligned literal fragment at the current location. */
1364 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1366 md_flush_pending_output ();
1368 if (inside_directive (directive_literal
))
1369 as_warn (_(".literal_position inside literal directive; ignoring"));
1370 xtensa_mark_literal_pool_location ();
1372 demand_empty_rest_of_line ();
1373 xtensa_clear_insn_labels ();
1377 /* Support .literal label, expr, ... */
1380 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1383 char *p
, *base_name
;
1387 if (inside_directive (directive_literal
))
1389 as_bad (_(".literal not allowed inside .begin literal region"));
1390 ignore_rest_of_line ();
1394 md_flush_pending_output ();
1396 /* Previous labels go with whatever follows this directive, not with
1397 the literal, so save them now. */
1398 saved_insn_labels
= insn_labels
;
1401 /* If we are using text-section literals, then this is the right value... */
1404 base_name
= input_line_pointer
;
1406 xtensa_switch_to_literal_fragment (&state
);
1408 /* ...but if we aren't using text-section-literals, then we
1409 need to put them in the section we just switched to. */
1410 if (use_literal_section
|| directive_state
[directive_absolute_literals
])
1413 /* All literals are aligned to four-byte boundaries. */
1414 frag_align (2, 0, 0);
1415 record_alignment (now_seg
, 2);
1417 c
= get_symbol_end ();
1418 /* Just after name is now '\0'. */
1419 p
= input_line_pointer
;
1423 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1425 as_bad (_("expected comma or colon after symbol name; "
1426 "rest of line ignored"));
1427 ignore_rest_of_line ();
1428 xtensa_restore_emit_state (&state
);
1436 input_line_pointer
++; /* skip ',' or ':' */
1438 xtensa_elf_cons (4);
1440 xtensa_restore_emit_state (&state
);
1442 /* Restore the list of current labels. */
1443 xtensa_clear_insn_labels ();
1444 insn_labels
= saved_insn_labels
;
1449 xtensa_literal_prefix (void)
1454 /* Parse the new prefix from the input_line_pointer. */
1456 len
= strspn (input_line_pointer
,
1457 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1458 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1460 /* Get a null-terminated copy of the name. */
1461 name
= xmalloc (len
+ 1);
1463 strncpy (name
, input_line_pointer
, len
);
1466 /* Skip the name in the input line. */
1467 input_line_pointer
+= len
;
1469 default_lit_sections
.lit_prefix
= name
;
1471 /* Clear cached literal sections, since the prefix has changed. */
1472 default_lit_sections
.lit_seg
= NULL
;
1473 default_lit_sections
.lit4_seg
= NULL
;
1477 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1480 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1482 float fall_through_f
, target_f
;
1484 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1485 if (fall_through_f
< 0)
1487 as_bad (_("fall through frequency must be greater than 0"));
1488 ignore_rest_of_line ();
1492 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1495 as_bad (_("branch target frequency must be greater than 0"));
1496 ignore_rest_of_line ();
1500 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1502 demand_empty_rest_of_line ();
1506 /* Like normal .long/.short/.word, except support @plt, etc.
1507 Clobbers input_line_pointer, checks end-of-line. */
1510 xtensa_elf_cons (int nbytes
)
1513 bfd_reloc_code_real_type reloc
;
1515 md_flush_pending_output ();
1517 if (cur_vinsn
.inside_bundle
)
1518 as_bad (_("directives are not valid inside bundles"));
1520 if (is_it_end_of_statement ())
1522 demand_empty_rest_of_line ();
1529 if (exp
.X_op
== O_symbol
1530 && *input_line_pointer
== '@'
1531 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1534 reloc_howto_type
*reloc_howto
=
1535 bfd_reloc_type_lookup (stdoutput
, reloc
);
1537 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1538 as_bad (_("unsupported relocation"));
1539 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1540 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1541 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1542 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1543 as_bad (_("opcode-specific %s relocation used outside "
1544 "an instruction"), reloc_howto
->name
);
1545 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1546 as_bad (_("%s relocations do not fit in %d bytes"),
1547 reloc_howto
->name
, nbytes
);
1550 char *p
= frag_more ((int) nbytes
);
1551 xtensa_set_frag_assembly_state (frag_now
);
1552 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1553 nbytes
, &exp
, 0, reloc
);
1557 emit_expr (&exp
, (unsigned int) nbytes
);
1559 while (*input_line_pointer
++ == ',');
1561 input_line_pointer
--; /* Put terminator back into stream. */
1562 demand_empty_rest_of_line ();
1566 /* Parsing and Idiom Translation. */
1568 /* Parse @plt, etc. and return the desired relocation. */
1569 static bfd_reloc_code_real_type
1570 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1577 struct suffix_reloc_map
*ptr
;
1580 return BFD_RELOC_NONE
;
1582 for (ch
= *str
, str2
= ident
;
1583 (str2
< ident
+ sizeof (ident
) - 1
1584 && (ISALNUM (ch
) || ch
== '@'));
1587 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1594 for (ptr
= &suffix_relocs
[0]; ptr
->length
> 0; ptr
++)
1595 if (ch
== ptr
->suffix
[0]
1596 && len
== ptr
->length
1597 && memcmp (ident
, ptr
->suffix
, ptr
->length
) == 0)
1599 /* Now check for "identifier@suffix+constant". */
1600 if (*str
== '-' || *str
== '+')
1602 char *orig_line
= input_line_pointer
;
1603 expressionS new_exp
;
1605 input_line_pointer
= str
;
1606 expression (&new_exp
);
1607 if (new_exp
.X_op
== O_constant
)
1609 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1610 str
= input_line_pointer
;
1613 if (&input_line_pointer
!= str_p
)
1614 input_line_pointer
= orig_line
;
1621 return BFD_RELOC_UNUSED
;
1625 /* Find the matching operator type. */
1626 static unsigned char
1627 map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc
)
1629 struct suffix_reloc_map
*sfx
;
1630 unsigned char operator = (unsigned char) -1;
1632 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1634 if (sfx
->reloc
== reloc
)
1636 operator = sfx
->operator;
1640 assert (operator != (unsigned char) -1);
1645 /* Find the matching reloc type. */
1646 static bfd_reloc_code_real_type
1647 map_operator_to_reloc (unsigned char operator)
1649 struct suffix_reloc_map
*sfx
;
1650 bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
1652 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1654 if (sfx
->operator == operator)
1661 if (reloc
== BFD_RELOC_UNUSED
)
1662 return BFD_RELOC_32
;
1669 expression_end (const char *name
)
1692 #define ERROR_REG_NUM ((unsigned) -1)
1695 tc_get_register (const char *prefix
)
1698 const char *next_expr
;
1699 const char *old_line_pointer
;
1702 old_line_pointer
= input_line_pointer
;
1704 if (*input_line_pointer
== '$')
1705 ++input_line_pointer
;
1707 /* Accept "sp" as a synonym for "a1". */
1708 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1709 && expression_end (input_line_pointer
+ 2))
1711 input_line_pointer
+= 2;
1712 return 1; /* AR[1] */
1715 while (*input_line_pointer
++ == *prefix
++)
1717 --input_line_pointer
;
1722 as_bad (_("bad register name: %s"), old_line_pointer
);
1723 return ERROR_REG_NUM
;
1726 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1728 as_bad (_("bad register number: %s"), input_line_pointer
);
1729 return ERROR_REG_NUM
;
1734 while (ISDIGIT ((int) *input_line_pointer
))
1735 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1737 if (!(next_expr
= expression_end (input_line_pointer
)))
1739 as_bad (_("bad register name: %s"), old_line_pointer
);
1740 return ERROR_REG_NUM
;
1743 input_line_pointer
= (char *) next_expr
;
1750 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1752 xtensa_isa isa
= xtensa_default_isa
;
1754 /* Check if this is an immediate operand. */
1755 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1757 bfd_reloc_code_real_type reloc
;
1758 segT t
= expression (tok
);
1759 if (t
== absolute_section
1760 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1762 assert (tok
->X_op
== O_constant
);
1763 tok
->X_op
= O_symbol
;
1764 tok
->X_add_symbol
= &abs_symbol
;
1767 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1768 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1771 if (reloc
== BFD_RELOC_UNUSED
)
1773 as_bad (_("unsupported relocation"));
1777 if (tok
->X_op
== O_constant
)
1781 case BFD_RELOC_LO16
:
1782 tok
->X_add_number
&= 0xffff;
1785 case BFD_RELOC_HI16
:
1786 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1793 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
1798 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1799 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1801 if (reg
!= ERROR_REG_NUM
) /* Already errored */
1804 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
1805 as_bad (_("register number out of range"));
1808 tok
->X_op
= O_register
;
1809 tok
->X_add_symbol
= 0;
1810 tok
->X_add_number
= reg
;
1815 /* Split up the arguments for an opcode or pseudo-op. */
1818 tokenize_arguments (char **args
, char *str
)
1820 char *old_input_line_pointer
;
1821 bfd_boolean saw_comma
= FALSE
;
1822 bfd_boolean saw_arg
= FALSE
;
1823 bfd_boolean saw_colon
= FALSE
;
1825 char *arg_end
, *arg
;
1828 /* Save and restore input_line_pointer around this function. */
1829 old_input_line_pointer
= input_line_pointer
;
1830 input_line_pointer
= str
;
1832 while (*input_line_pointer
)
1835 switch (*input_line_pointer
)
1842 input_line_pointer
++;
1843 if (saw_comma
|| saw_colon
|| !saw_arg
)
1849 input_line_pointer
++;
1850 if (saw_comma
|| saw_colon
|| !saw_arg
)
1856 if (!saw_comma
&& !saw_colon
&& saw_arg
)
1859 arg_end
= input_line_pointer
+ 1;
1860 while (!expression_end (arg_end
))
1863 arg_len
= arg_end
- input_line_pointer
;
1864 arg
= (char *) xmalloc ((saw_colon
? 1 : 0) + arg_len
+ 1);
1865 args
[num_args
] = arg
;
1869 strncpy (arg
, input_line_pointer
, arg_len
);
1870 arg
[arg_len
] = '\0';
1872 input_line_pointer
= arg_end
;
1882 if (saw_comma
|| saw_colon
)
1884 input_line_pointer
= old_input_line_pointer
;
1889 as_bad (_("extra comma"));
1891 as_bad (_("extra colon"));
1893 as_bad (_("missing argument"));
1895 as_bad (_("missing comma or colon"));
1896 input_line_pointer
= old_input_line_pointer
;
1901 /* Parse the arguments to an opcode. Return TRUE on error. */
1904 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
1906 expressionS
*tok
, *last_tok
;
1907 xtensa_opcode opcode
= insn
->opcode
;
1908 bfd_boolean had_error
= TRUE
;
1909 xtensa_isa isa
= xtensa_default_isa
;
1910 int n
, num_regs
= 0;
1911 int opcode_operand_count
;
1912 int opnd_cnt
, last_opnd_cnt
;
1913 unsigned int next_reg
= 0;
1914 char *old_input_line_pointer
;
1916 if (insn
->insn_type
== ITYPE_LITERAL
)
1917 opcode_operand_count
= 1;
1919 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
1922 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
1924 /* Save and restore input_line_pointer around this function. */
1925 old_input_line_pointer
= input_line_pointer
;
1931 /* Skip invisible operands. */
1932 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
1938 for (n
= 0; n
< num_args
; n
++)
1940 input_line_pointer
= arg_strings
[n
];
1941 if (*input_line_pointer
== ':')
1943 xtensa_regfile opnd_rf
;
1944 input_line_pointer
++;
1947 assert (opnd_cnt
> 0);
1949 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
1951 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
1952 as_warn (_("incorrect register number, ignoring"));
1957 if (opnd_cnt
>= opcode_operand_count
)
1959 as_warn (_("too many arguments"));
1962 assert (opnd_cnt
< MAX_INSN_ARGS
);
1964 expression_maybe_register (opcode
, opnd_cnt
, tok
);
1965 next_reg
= tok
->X_add_number
+ 1;
1967 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
1969 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
1971 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
1972 /* minus 1 because we are seeing one right now */
1978 last_opnd_cnt
= opnd_cnt
;
1985 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
1989 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
1992 insn
->ntok
= tok
- insn
->tok
;
1996 input_line_pointer
= old_input_line_pointer
;
2002 get_invisible_operands (TInsn
*insn
)
2004 xtensa_isa isa
= xtensa_default_isa
;
2005 static xtensa_insnbuf slotbuf
= NULL
;
2007 xtensa_opcode opc
= insn
->opcode
;
2008 int slot
, opnd
, fmt_found
;
2012 slotbuf
= xtensa_insnbuf_alloc (isa
);
2014 /* Find format/slot where this can be encoded. */
2017 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2019 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2021 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2027 if (fmt_found
) break;
2032 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2036 /* First encode all the visible operands
2037 (to deal with shared field operands). */
2038 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2040 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2041 && (insn
->tok
[opnd
].X_op
== O_register
2042 || insn
->tok
[opnd
].X_op
== O_constant
))
2044 val
= insn
->tok
[opnd
].X_add_number
;
2045 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2046 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2050 /* Then pull out the values for the invisible ones. */
2051 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2053 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2055 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2056 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2057 insn
->tok
[opnd
].X_add_number
= val
;
2058 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2059 insn
->tok
[opnd
].X_op
= O_register
;
2061 insn
->tok
[opnd
].X_op
= O_constant
;
2070 xg_reverse_shift_count (char **cnt_argp
)
2072 char *cnt_arg
, *new_arg
;
2073 cnt_arg
= *cnt_argp
;
2075 /* replace the argument with "31-(argument)" */
2076 new_arg
= (char *) xmalloc (strlen (cnt_arg
) + 6);
2077 sprintf (new_arg
, "31-(%s)", cnt_arg
);
2080 *cnt_argp
= new_arg
;
2084 /* If "arg" is a constant expression, return non-zero with the value
2088 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2091 char *save_ptr
= input_line_pointer
;
2093 input_line_pointer
= arg
;
2095 input_line_pointer
= save_ptr
;
2097 if (exp
.X_op
== O_constant
)
2099 *valp
= exp
.X_add_number
;
2108 xg_replace_opname (char **popname
, char *newop
)
2111 *popname
= (char *) xmalloc (strlen (newop
) + 1);
2112 strcpy (*popname
, newop
);
2117 xg_check_num_args (int *pnum_args
,
2122 int num_args
= *pnum_args
;
2124 if (num_args
< expected_num
)
2126 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2127 num_args
, opname
, expected_num
);
2131 if (num_args
> expected_num
)
2133 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2134 num_args
, opname
, expected_num
);
2135 while (num_args
-- > expected_num
)
2137 free (arg_strings
[num_args
]);
2138 arg_strings
[num_args
] = 0;
2140 *pnum_args
= expected_num
;
2148 /* If the register is not specified as part of the opcode,
2149 then get it from the operand and move it to the opcode. */
2152 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2154 xtensa_isa isa
= xtensa_default_isa
;
2156 char *opname
, *new_opname
;
2157 const char *sr_name
;
2158 int is_user
, is_write
;
2163 is_user
= (opname
[1] == 'u');
2164 is_write
= (opname
[0] == 'w');
2166 /* Opname == [rw]ur or [rwx]sr... */
2168 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2171 /* Check if the argument is a symbolic register name. */
2172 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2173 /* Handle WSR to "INTSET" as a special case. */
2174 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2175 && !strcasecmp (arg_strings
[1], "intset"))
2176 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2177 if (sr
== XTENSA_UNDEFINED
2178 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2180 /* Maybe it's a register number.... */
2182 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2184 as_bad (_("invalid register '%s' for '%s' instruction"),
2185 arg_strings
[1], opname
);
2188 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2189 if (sr
== XTENSA_UNDEFINED
)
2191 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2192 (long) val
, opname
);
2197 /* Remove the last argument, which is now part of the opcode. */
2198 free (arg_strings
[1]);
2202 /* Translate the opcode. */
2203 sr_name
= xtensa_sysreg_name (isa
, sr
);
2204 /* Another special case for "WSR.INTSET".... */
2205 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2207 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2208 sprintf (new_opname
, "%s.%s", *popname
, sr_name
);
2210 *popname
= new_opname
;
2217 xtensa_translate_old_userreg_ops (char **popname
)
2219 xtensa_isa isa
= xtensa_default_isa
;
2221 char *opname
, *new_opname
;
2222 const char *sr_name
;
2223 bfd_boolean has_underbar
= FALSE
;
2226 if (opname
[0] == '_')
2228 has_underbar
= TRUE
;
2232 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2233 if (sr
!= XTENSA_UNDEFINED
)
2235 /* The new default name ("nnn") is different from the old default
2236 name ("URnnn"). The old default is handled below, and we don't
2237 want to recognize [RW]nnn, so do nothing if the name is the (new)
2239 static char namebuf
[10];
2240 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2241 if (strcmp (namebuf
, opname
+ 1) == 0)
2249 /* Only continue if the reg name is "URnnn". */
2250 if (opname
[1] != 'u' || opname
[2] != 'r')
2252 val
= strtoul (opname
+ 3, &end
, 10);
2256 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2257 if (sr
== XTENSA_UNDEFINED
)
2259 as_bad (_("invalid register number (%ld) for '%s'"),
2260 (long) val
, opname
);
2265 /* Translate the opcode. */
2266 sr_name
= xtensa_sysreg_name (isa
, sr
);
2267 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2268 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2269 opname
[0], sr_name
);
2271 *popname
= new_opname
;
2278 xtensa_translate_zero_immed (char *old_op
,
2288 assert (opname
[0] != '_');
2290 if (strcmp (opname
, old_op
) != 0)
2293 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2295 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2297 xg_replace_opname (popname
, new_op
);
2298 free (arg_strings
[1]);
2299 arg_strings
[1] = arg_strings
[2];
2308 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2309 Returns non-zero if an error was found. */
2312 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2314 char *opname
= *popname
;
2315 bfd_boolean has_underbar
= FALSE
;
2319 has_underbar
= TRUE
;
2323 if (strcmp (opname
, "mov") == 0)
2325 if (use_transform () && !has_underbar
&& density_supported
)
2326 xg_replace_opname (popname
, "mov.n");
2329 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2331 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2332 arg_strings
[2] = (char *) xmalloc (strlen (arg_strings
[1]) + 1);
2333 strcpy (arg_strings
[2], arg_strings
[1]);
2339 if (strcmp (opname
, "bbsi.l") == 0)
2341 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2343 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2344 if (target_big_endian
)
2345 xg_reverse_shift_count (&arg_strings
[1]);
2349 if (strcmp (opname
, "bbci.l") == 0)
2351 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2353 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2354 if (target_big_endian
)
2355 xg_reverse_shift_count (&arg_strings
[1]);
2359 /* Don't do anything special with NOPs inside FLIX instructions. They
2360 are handled elsewhere. Real NOP instructions are always available
2361 in configurations with FLIX, so this should never be an issue but
2362 check for it anyway. */
2363 if (!cur_vinsn
.inside_bundle
&& xtensa_nop_opcode
== XTENSA_UNDEFINED
2364 && strcmp (opname
, "nop") == 0)
2366 if (use_transform () && !has_underbar
&& density_supported
)
2367 xg_replace_opname (popname
, "nop.n");
2370 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2372 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2373 arg_strings
[0] = (char *) xmalloc (3);
2374 arg_strings
[1] = (char *) xmalloc (3);
2375 arg_strings
[2] = (char *) xmalloc (3);
2376 strcpy (arg_strings
[0], "a1");
2377 strcpy (arg_strings
[1], "a1");
2378 strcpy (arg_strings
[2], "a1");
2384 /* Recognize [RW]UR and [RWX]SR. */
2385 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2386 && (opname
[1] == 'u' || opname
[1] == 's'))
2387 || (opname
[0] == 'x' && opname
[1] == 's'))
2389 && opname
[3] == '\0')
2390 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2392 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2393 [RW]<name> if <name> is the non-default name of a user register. */
2394 if ((opname
[0] == 'r' || opname
[0] == 'w')
2395 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2396 return xtensa_translate_old_userreg_ops (popname
);
2398 /* Relax branches that don't allow comparisons against an immediate value
2399 of zero to the corresponding branches with implicit zero immediates. */
2400 if (!has_underbar
&& use_transform ())
2402 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2403 pnum_args
, arg_strings
))
2406 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2407 pnum_args
, arg_strings
))
2410 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2411 pnum_args
, arg_strings
))
2414 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2415 pnum_args
, arg_strings
))
2423 /* Functions for dealing with the Xtensa ISA. */
2425 /* Currently the assembler only allows us to use a single target per
2426 fragment. Because of this, only one operand for a given
2427 instruction may be symbolic. If there is a PC-relative operand,
2428 the last one is chosen. Otherwise, the result is the number of the
2429 last immediate operand, and if there are none of those, we fail and
2433 get_relaxable_immed (xtensa_opcode opcode
)
2435 int last_immed
= -1;
2438 if (opcode
== XTENSA_UNDEFINED
)
2441 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2442 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2444 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2446 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2448 if (last_immed
== -1
2449 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2456 static xtensa_opcode
2457 get_opcode_from_buf (const char *buf
, int slot
)
2459 static xtensa_insnbuf insnbuf
= NULL
;
2460 static xtensa_insnbuf slotbuf
= NULL
;
2461 xtensa_isa isa
= xtensa_default_isa
;
2466 insnbuf
= xtensa_insnbuf_alloc (isa
);
2467 slotbuf
= xtensa_insnbuf_alloc (isa
);
2470 xtensa_insnbuf_from_chars (isa
, insnbuf
, (const unsigned char *) buf
, 0);
2471 fmt
= xtensa_format_decode (isa
, insnbuf
);
2472 if (fmt
== XTENSA_UNDEFINED
)
2473 return XTENSA_UNDEFINED
;
2475 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2476 return XTENSA_UNDEFINED
;
2478 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2479 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2483 #ifdef TENSILICA_DEBUG
2485 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2488 xtensa_print_insn_table (void)
2490 int num_opcodes
, num_operands
;
2491 xtensa_opcode opcode
;
2492 xtensa_isa isa
= xtensa_default_isa
;
2494 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2495 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2498 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2499 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2500 for (opn
= 0; opn
< num_operands
; opn
++)
2502 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2504 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2506 xtensa_regfile opnd_rf
=
2507 xtensa_operand_regfile (isa
, opcode
, opn
);
2508 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2510 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2511 fputs ("[lLr] ", stderr
);
2513 fputs ("i ", stderr
);
2515 fprintf (stderr
, "\n");
2521 print_vliw_insn (xtensa_insnbuf vbuf
)
2523 xtensa_isa isa
= xtensa_default_isa
;
2524 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2525 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2528 fprintf (stderr
, "format = %d\n", f
);
2530 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2532 xtensa_opcode opcode
;
2536 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2537 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2538 opname
= xtensa_opcode_name (isa
, opcode
);
2540 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2541 fprintf (stderr
, " operands = ");
2543 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2547 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2549 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2550 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2551 fprintf (stderr
, "%d ", val
);
2553 fprintf (stderr
, "\n");
2555 xtensa_insnbuf_free (isa
, sbuf
);
2558 #endif /* TENSILICA_DEBUG */
2562 is_direct_call_opcode (xtensa_opcode opcode
)
2564 xtensa_isa isa
= xtensa_default_isa
;
2565 int n
, num_operands
;
2567 if (xtensa_opcode_is_call (isa
, opcode
) != 1)
2570 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2571 for (n
= 0; n
< num_operands
; n
++)
2573 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2574 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2581 /* Convert from BFD relocation type code to slot and operand number.
2582 Returns non-zero on failure. */
2585 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2587 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2588 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2590 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2593 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2594 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2596 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2606 /* Convert from slot number to BFD relocation type code for the
2607 standard PC-relative relocations. Return BFD_RELOC_NONE on
2610 static bfd_reloc_code_real_type
2611 encode_reloc (int slot
)
2613 if (slot
< 0 || slot
> 14)
2614 return BFD_RELOC_NONE
;
2616 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2620 /* Convert from slot numbers to BFD relocation type code for the
2621 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2623 static bfd_reloc_code_real_type
2624 encode_alt_reloc (int slot
)
2626 if (slot
< 0 || slot
> 14)
2627 return BFD_RELOC_NONE
;
2629 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2634 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2637 xtensa_opcode opcode
,
2643 uint32 valbuf
= value
;
2645 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2647 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2649 as_bad_where ((char *) file
, line
,
2650 _("operand %d of '%s' has out of range value '%u'"),
2652 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2655 as_bad_where ((char *) file
, line
,
2656 _("operand %d of '%s' has invalid value '%u'"),
2658 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2663 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2669 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2672 xtensa_opcode opcode
,
2676 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2677 fmt
, slot
, slotbuf
, &val
);
2678 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2683 /* Checks for rules from xtensa-relax tables. */
2685 /* The routine xg_instruction_matches_option_term must return TRUE
2686 when a given option term is true. The meaning of all of the option
2687 terms is given interpretation by this function. This is needed when
2688 an option depends on the state of a directive, but there are no such
2689 options in use right now. */
2692 xg_instruction_matches_option_term (TInsn
*insn ATTRIBUTE_UNUSED
,
2693 const ReqOrOption
*option
)
2695 if (strcmp (option
->option_name
, "realnop") == 0
2696 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2698 /* These conditions were evaluated statically when building the
2699 relaxation table. There's no need to reevaluate them now. */
2704 as_fatal (_("internal error: unknown option name '%s'"),
2705 option
->option_name
);
2711 xg_instruction_matches_or_options (TInsn
*insn
,
2712 const ReqOrOptionList
*or_option
)
2714 const ReqOrOption
*option
;
2715 /* Must match each of the AND terms. */
2716 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2718 if (xg_instruction_matches_option_term (insn
, option
))
2726 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2728 const ReqOption
*req_options
;
2729 /* Must match each of the AND terms. */
2730 for (req_options
= options
;
2731 req_options
!= NULL
;
2732 req_options
= req_options
->next
)
2734 /* Must match one of the OR clauses. */
2735 if (!xg_instruction_matches_or_options (insn
,
2736 req_options
->or_option_terms
))
2743 /* Return the transition rule that matches or NULL if none matches. */
2746 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2748 PreconditionList
*condition_l
;
2750 if (rule
->opcode
!= insn
->opcode
)
2753 for (condition_l
= rule
->conditions
;
2754 condition_l
!= NULL
;
2755 condition_l
= condition_l
->next
)
2759 Precondition
*cond
= condition_l
->precond
;
2764 /* The expression must be the constant. */
2765 assert (cond
->op_num
< insn
->ntok
);
2766 exp1
= &insn
->tok
[cond
->op_num
];
2767 if (expr_is_const (exp1
))
2772 if (get_expr_const (exp1
) != cond
->op_data
)
2776 if (get_expr_const (exp1
) == cond
->op_data
)
2783 else if (expr_is_register (exp1
))
2788 if (get_expr_register (exp1
) != cond
->op_data
)
2792 if (get_expr_register (exp1
) == cond
->op_data
)
2804 assert (cond
->op_num
< insn
->ntok
);
2805 assert (cond
->op_data
< insn
->ntok
);
2806 exp1
= &insn
->tok
[cond
->op_num
];
2807 exp2
= &insn
->tok
[cond
->op_data
];
2812 if (!expr_is_equal (exp1
, exp2
))
2816 if (expr_is_equal (exp1
, exp2
))
2828 if (!xg_instruction_matches_options (insn
, rule
->options
))
2836 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
2838 bfd_boolean a_greater
= FALSE
;
2839 bfd_boolean b_greater
= FALSE
;
2841 ReqOptionList
*l_a
= a
->options
;
2842 ReqOptionList
*l_b
= b
->options
;
2844 /* We only care if they both are the same except for
2845 a const16 vs. an l32r. */
2847 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2849 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
2850 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
2851 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2853 if (l_or_a
->is_true
!= l_or_b
->is_true
)
2855 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
2857 /* This is the case we care about. */
2858 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
2859 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
2866 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
2867 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
2877 l_or_a
= l_or_a
->next
;
2878 l_or_b
= l_or_b
->next
;
2880 if (l_or_a
|| l_or_b
)
2889 /* Incomparable if the substitution was used differently in two cases. */
2890 if (a_greater
&& b_greater
)
2902 static TransitionRule
*
2903 xg_instruction_match (TInsn
*insn
)
2905 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
2907 assert (insn
->opcode
< table
->num_opcodes
);
2909 /* Walk through all of the possible transitions. */
2910 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2912 TransitionRule
*rule
= l
->rule
;
2913 if (xg_instruction_matches_rule (insn
, rule
))
2920 /* Various Other Internal Functions. */
2923 is_unique_insn_expansion (TransitionRule
*r
)
2925 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
2927 if (r
->to_instr
->typ
!= INSTR_INSTR
)
2933 /* Check if there is exactly one relaxation for INSN that converts it to
2934 another instruction of equal or larger size. If so, and if TARG is
2935 non-null, go ahead and generate the relaxed instruction into TARG. If
2936 NARROW_ONLY is true, then only consider relaxations that widen a narrow
2937 instruction, i.e., ignore relaxations that convert to an instruction of
2938 equal size. In some contexts where this function is used, only
2939 a single widening is allowed and the NARROW_ONLY argument is used to
2940 exclude cases like ADDI being "widened" to an ADDMI, which may
2941 later be relaxed to an ADDMI/ADDI pair. */
2944 xg_is_single_relaxable_insn (TInsn
*insn
, TInsn
*targ
, bfd_boolean narrow_only
)
2946 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
2948 TransitionRule
*match
= 0;
2950 assert (insn
->insn_type
== ITYPE_INSN
);
2951 assert (insn
->opcode
< table
->num_opcodes
);
2953 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2955 TransitionRule
*rule
= l
->rule
;
2957 if (xg_instruction_matches_rule (insn
, rule
)
2958 && is_unique_insn_expansion (rule
)
2959 && (xg_get_single_size (insn
->opcode
) + (narrow_only
? 1 : 0)
2960 <= xg_get_single_size (rule
->to_instr
->opcode
)))
2971 xg_build_to_insn (targ
, insn
, match
->to_instr
);
2976 /* Return the maximum number of bytes this opcode can expand to. */
2979 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
2981 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
2983 int max_size
= xg_get_single_size (opcode
);
2985 assert (opcode
< table
->num_opcodes
);
2987 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
2989 TransitionRule
*rule
= l
->rule
;
2990 BuildInstr
*build_list
;
2995 build_list
= rule
->to_instr
;
2996 if (is_unique_insn_expansion (rule
))
2998 assert (build_list
->typ
== INSTR_INSTR
);
2999 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
3002 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3004 switch (build_list
->typ
)
3007 this_size
+= xg_get_single_size (build_list
->opcode
);
3009 case INSTR_LITERAL_DEF
:
3010 case INSTR_LABEL_DEF
:
3015 if (this_size
> max_size
)
3016 max_size
= this_size
;
3022 /* Return the maximum number of literal bytes this opcode can generate. */
3025 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3027 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3031 assert (opcode
< table
->num_opcodes
);
3033 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3035 TransitionRule
*rule
= l
->rule
;
3036 BuildInstr
*build_list
;
3041 build_list
= rule
->to_instr
;
3042 if (is_unique_insn_expansion (rule
))
3044 assert (build_list
->typ
== INSTR_INSTR
);
3045 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3048 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3050 switch (build_list
->typ
)
3052 case INSTR_LITERAL_DEF
:
3053 /* Hard-coded 4-byte literal. */
3057 case INSTR_LABEL_DEF
:
3062 if (this_size
> max_size
)
3063 max_size
= this_size
;
3070 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3072 int steps_taken
= 0;
3073 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3076 assert (insn
->insn_type
== ITYPE_INSN
);
3077 assert (insn
->opcode
< table
->num_opcodes
);
3079 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3081 TransitionRule
*rule
= l
->rule
;
3083 if (xg_instruction_matches_rule (insn
, rule
))
3085 if (steps_taken
== lateral_steps
)
3095 get_special_literal_symbol (void)
3097 static symbolS
*sym
= NULL
;
3100 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3106 get_special_label_symbol (void)
3108 static symbolS
*sym
= NULL
;
3111 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3117 xg_valid_literal_expression (const expressionS
*exp
)
3134 /* This will check to see if the value can be converted into the
3135 operand type. It will return TRUE if it does not fit. */
3138 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3140 uint32 valbuf
= value
;
3141 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3147 /* Assumes: All immeds are constants. Check that all constants fit
3148 into their immeds; return FALSE if not. */
3151 xg_immeds_fit (const TInsn
*insn
)
3153 xtensa_isa isa
= xtensa_default_isa
;
3157 assert (insn
->insn_type
== ITYPE_INSN
);
3158 for (i
= 0; i
< n
; ++i
)
3160 const expressionS
*expr
= &insn
->tok
[i
];
3161 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3168 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3173 /* The symbol should have a fixup associated with it. */
3182 /* This should only be called after we have an initial
3183 estimate of the addresses. */
3186 xg_symbolic_immeds_fit (const TInsn
*insn
,
3192 xtensa_isa isa
= xtensa_default_isa
;
3200 assert (insn
->insn_type
== ITYPE_INSN
);
3202 for (i
= 0; i
< n
; ++i
)
3204 const expressionS
*expr
= &insn
->tok
[i
];
3205 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3212 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3218 /* Check for the worst case. */
3219 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3224 /* We only allow symbols for PC-relative references.
3225 If pc_frag == 0, then we don't have frag locations yet. */
3227 || xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0)
3230 /* If it is a weak symbol, then assume it won't reach. */
3231 if (S_IS_WEAK (expr
->X_add_symbol
))
3234 if (is_direct_call_opcode (insn
->opcode
)
3235 && ! pc_frag
->tc_frag_data
.use_longcalls
)
3237 /* If callee is undefined or in a different segment, be
3238 optimistic and assume it will be in range. */
3239 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3243 /* Only references within a segment can be known to fit in the
3244 operands at assembly time. */
3245 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3248 symbolP
= expr
->X_add_symbol
;
3249 sym_frag
= symbol_get_frag (symbolP
);
3250 target
= S_GET_VALUE (symbolP
) + expr
->X_add_number
;
3251 pc
= pc_frag
->fr_address
+ pc_offset
;
3253 /* If frag has yet to be reached on this pass, assume it
3254 will move by STRETCH just as we did. If this is not so,
3255 it will be because some frag between grows, and that will
3256 force another pass. Beware zero-length frags. There
3257 should be a faster way to do this. */
3260 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3261 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3266 new_offset
= target
;
3267 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3268 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3273 /* The symbol should have a fixup associated with it. */
3282 /* Return TRUE on success. */
3285 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3291 targ
->linenum
= insn
->linenum
;
3296 targ
->opcode
= bi
->opcode
;
3297 targ
->insn_type
= ITYPE_INSN
;
3298 targ
->is_specific_opcode
= FALSE
;
3300 for (; op
!= NULL
; op
= op
->next
)
3302 int op_num
= op
->op_num
;
3303 int op_data
= op
->op_data
;
3305 assert (op
->op_num
< MAX_INSN_ARGS
);
3307 if (targ
->ntok
<= op_num
)
3308 targ
->ntok
= op_num
+ 1;
3313 set_expr_const (&targ
->tok
[op_num
], op_data
);
3316 assert (op_data
< insn
->ntok
);
3317 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3320 sym
= get_special_literal_symbol ();
3321 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3324 sym
= get_special_label_symbol ();
3325 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3327 case OP_OPERAND_HI16U
:
3328 case OP_OPERAND_LOW16U
:
3329 assert (op_data
< insn
->ntok
);
3330 if (expr_is_const (&insn
->tok
[op_data
]))
3333 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3334 val
= xg_apply_userdef_op_fn (op
->typ
,
3337 targ
->tok
[op_num
].X_add_number
= val
;
3341 /* For const16 we can create relocations for these. */
3342 if (targ
->opcode
== XTENSA_UNDEFINED
3343 || (targ
->opcode
!= xtensa_const16_opcode
))
3345 assert (op_data
< insn
->ntok
);
3346 /* Need to build a O_lo16 or O_hi16. */
3347 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3348 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3350 if (op
->typ
== OP_OPERAND_HI16U
)
3351 targ
->tok
[op_num
].X_op
= O_hi16
;
3352 else if (op
->typ
== OP_OPERAND_LOW16U
)
3353 targ
->tok
[op_num
].X_op
= O_lo16
;
3360 /* currently handles:
3363 OP_OPERAND_F32MINUS */
3364 if (xg_has_userdef_op_fn (op
->typ
))
3366 assert (op_data
< insn
->ntok
);
3367 if (expr_is_const (&insn
->tok
[op_data
]))
3370 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3371 val
= xg_apply_userdef_op_fn (op
->typ
,
3374 targ
->tok
[op_num
].X_add_number
= val
;
3377 return FALSE
; /* We cannot use a relocation for this. */
3386 case INSTR_LITERAL_DEF
:
3388 targ
->opcode
= XTENSA_UNDEFINED
;
3389 targ
->insn_type
= ITYPE_LITERAL
;
3390 targ
->is_specific_opcode
= FALSE
;
3391 for (; op
!= NULL
; op
= op
->next
)
3393 int op_num
= op
->op_num
;
3394 int op_data
= op
->op_data
;
3395 assert (op
->op_num
< MAX_INSN_ARGS
);
3397 if (targ
->ntok
<= op_num
)
3398 targ
->ntok
= op_num
+ 1;
3403 assert (op_data
< insn
->ntok
);
3404 /* We can only pass resolvable literals through. */
3405 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3407 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3419 case INSTR_LABEL_DEF
:
3421 targ
->opcode
= XTENSA_UNDEFINED
;
3422 targ
->insn_type
= ITYPE_LABEL
;
3423 targ
->is_specific_opcode
= FALSE
;
3424 /* Literal with no ops is a label? */
3425 assert (op
== NULL
);
3436 /* Return TRUE on success. */
3439 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3441 for (; bi
!= NULL
; bi
= bi
->next
)
3443 TInsn
*next_insn
= istack_push_space (istack
);
3445 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3452 /* Return TRUE on valid expansion. */
3455 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3457 int stack_size
= istack
->ninsn
;
3458 int steps_taken
= 0;
3459 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3462 assert (insn
->insn_type
== ITYPE_INSN
);
3463 assert (insn
->opcode
< table
->num_opcodes
);
3465 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3467 TransitionRule
*rule
= l
->rule
;
3469 if (xg_instruction_matches_rule (insn
, rule
))
3471 if (lateral_steps
== steps_taken
)
3475 /* This is it. Expand the rule to the stack. */
3476 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3479 /* Check to see if it fits. */
3480 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3482 TInsn
*insn
= &istack
->insn
[i
];
3484 if (insn
->insn_type
== ITYPE_INSN
3485 && !tinsn_has_symbolic_operands (insn
)
3486 && !xg_immeds_fit (insn
))
3488 istack
->ninsn
= stack_size
;
3501 /* Relax the assembly instruction at least "min_steps".
3502 Return the number of steps taken.
3504 For relaxation to correctly terminate, every relaxation chain must
3505 terminate in one of two ways:
3507 1. If the chain from one instruction to the next consists entirely of
3508 single instructions, then the chain *must* handle all possible
3509 immediates without failing. It must not ever fail because an
3510 immediate is out of range. The MOVI.N -> MOVI -> L32R relaxation
3511 chain is one example. L32R loads 32 bits, and there cannot be an
3512 immediate larger than 32 bits, so it satisfies this condition.
3513 Single instruction relaxation chains are as defined by
3514 xg_is_single_relaxable_instruction.
3516 2. Otherwise, the chain must end in a multi-instruction expansion: e.g.,
3517 BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J
3519 Strictly speaking, in most cases you can violate condition 1 and be OK
3520 -- in particular when the last two instructions have the same single
3521 size. But nevertheless, you should guarantee the above two conditions.
3523 We could fix this so that single-instruction expansions correctly
3524 terminate when they can't handle the range, but the error messages are
3525 worse, and it actually turns out that in every case but one (18-bit wide
3526 branches), you need a multi-instruction expansion to get the full range
3527 anyway. And because 18-bit branches are handled identically to 15-bit
3528 branches, there isn't any point in changing it. */
3531 xg_assembly_relax (IStack
*istack
,
3534 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3535 offsetT pc_offset
, /* offset in fragment */
3536 int min_steps
, /* minimum conversion steps */
3537 long stretch
) /* number of bytes stretched so far */
3539 int steps_taken
= 0;
3541 /* Some of its immeds don't fit. Try to build a relaxed version.
3542 This may go through a couple of stages of single instruction
3543 transformations before we get there. */
3545 TInsn single_target
;
3547 int lateral_steps
= 0;
3548 int istack_size
= istack
->ninsn
;
3550 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3551 && steps_taken
>= min_steps
)
3553 istack_push (istack
, insn
);
3556 current_insn
= *insn
;
3558 /* Walk through all of the single instruction expansions. */
3559 while (xg_is_single_relaxable_insn (¤t_insn
, &single_target
, FALSE
))
3562 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3565 if (steps_taken
>= min_steps
)
3567 istack_push (istack
, &single_target
);
3571 current_insn
= single_target
;
3574 /* Now check for a multi-instruction expansion. */
3575 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3577 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3580 if (steps_taken
>= min_steps
)
3582 istack_push (istack
, ¤t_insn
);
3587 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3589 if (steps_taken
>= min_steps
)
3593 istack
->ninsn
= istack_size
;
3596 /* It's not going to work -- use the original. */
3597 istack_push (istack
, insn
);
3603 xg_force_frag_space (int size
)
3605 /* This may have the side effect of creating a new fragment for the
3606 space to go into. I just do not like the name of the "frag"
3613 xg_finish_frag (char *last_insn
,
3614 enum xtensa_relax_statesE frag_state
,
3615 enum xtensa_relax_statesE slot0_state
,
3617 bfd_boolean is_insn
)
3619 /* Finish off this fragment so that it has at LEAST the desired
3620 max_growth. If it doesn't fit in this fragment, close this one
3621 and start a new one. In either case, return a pointer to the
3622 beginning of the growth area. */
3626 xg_force_frag_space (max_growth
);
3628 old_frag
= frag_now
;
3630 frag_now
->fr_opcode
= last_insn
;
3632 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3634 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3635 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3637 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3638 xtensa_set_frag_assembly_state (frag_now
);
3640 /* Just to make sure that we did not split it up. */
3641 assert (old_frag
->fr_next
== frag_now
);
3645 /* Return TRUE if the target frag is one of the next non-empty frags. */
3648 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3653 for (; fragP
; fragP
= fragP
->fr_next
)
3655 if (fragP
== target
)
3657 if (fragP
->fr_fix
!= 0)
3659 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3661 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3662 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3664 if (fragP
->fr_type
== rs_space
)
3672 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3674 xtensa_isa isa
= xtensa_default_isa
;
3676 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3681 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) != 1
3682 && xtensa_opcode_is_jump (isa
, insn
->opcode
) != 1)
3685 for (i
= 0; i
< num_ops
; i
++)
3687 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3693 if (target_op
== -1)
3696 if (insn
->ntok
<= target_op
)
3699 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3702 sym
= insn
->tok
[target_op
].X_add_symbol
;
3706 if (insn
->tok
[target_op
].X_add_number
!= 0)
3709 target_frag
= symbol_get_frag (sym
);
3710 if (target_frag
== NULL
)
3713 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3714 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3722 xg_add_branch_and_loop_targets (TInsn
*insn
)
3724 xtensa_isa isa
= xtensa_default_isa
;
3725 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3727 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3730 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3731 && insn
->tok
[i
].X_op
== O_symbol
)
3732 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3736 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3737 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3741 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3743 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3744 && insn
->tok
[i
].X_op
== O_symbol
)
3746 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3747 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3748 if (S_IS_DEFINED (sym
))
3749 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3756 /* Return FALSE if no error. */
3759 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3764 switch (instr_spec
->typ
)
3767 new_insn
->insn_type
= ITYPE_INSN
;
3768 new_insn
->opcode
= instr_spec
->opcode
;
3769 new_insn
->is_specific_opcode
= FALSE
;
3770 new_insn
->linenum
= old_insn
->linenum
;
3772 case INSTR_LITERAL_DEF
:
3773 new_insn
->insn_type
= ITYPE_LITERAL
;
3774 new_insn
->opcode
= XTENSA_UNDEFINED
;
3775 new_insn
->is_specific_opcode
= FALSE
;
3776 new_insn
->linenum
= old_insn
->linenum
;
3778 case INSTR_LABEL_DEF
:
3779 as_bad (_("INSTR_LABEL_DEF not supported yet"));
3783 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3786 const expressionS
*src_exp
;
3792 /* The expression must be the constant. */
3793 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3794 exp
= &new_insn
->tok
[b_op
->op_num
];
3795 set_expr_const (exp
, b_op
->op_data
);
3799 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3800 assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
3801 src_exp
= &old_insn
->tok
[b_op
->op_data
];
3802 exp
= &new_insn
->tok
[b_op
->op_num
];
3803 copy_expr (exp
, src_exp
);
3808 as_bad (_("can't handle generation of literal/labels yet"));
3812 as_bad (_("can't handle undefined OP TYPE"));
3817 new_insn
->ntok
= num_ops
;
3822 /* Return TRUE if it was simplified. */
3825 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
3827 TransitionRule
*rule
;
3828 BuildInstr
*insn_spec
;
3830 if (old_insn
->is_specific_opcode
|| !density_supported
)
3833 rule
= xg_instruction_match (old_insn
);
3837 insn_spec
= rule
->to_instr
;
3838 /* There should only be one. */
3839 assert (insn_spec
!= NULL
);
3840 assert (insn_spec
->next
== NULL
);
3841 if (insn_spec
->next
!= NULL
)
3844 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
3850 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3851 l32i.n. (2) Check the number of operands. (3) Place the instruction
3852 tokens into the stack or relax it and place multiple
3853 instructions/literals onto the stack. Return FALSE if no error. */
3856 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
3860 bfd_boolean do_expand
;
3862 tinsn_init (&new_insn
);
3864 /* Narrow it if we can. xg_simplify_insn now does all the
3865 appropriate checking (e.g., for the density option). */
3866 if (xg_simplify_insn (orig_insn
, &new_insn
))
3867 orig_insn
= &new_insn
;
3869 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
3871 if (orig_insn
->ntok
< noperands
)
3873 as_bad (_("found %d operands for '%s': Expected %d"),
3875 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3879 if (orig_insn
->ntok
> noperands
)
3880 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
3882 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3885 /* If there are not enough operands, we will assert above. If there
3886 are too many, just cut out the extras here. */
3887 orig_insn
->ntok
= noperands
;
3889 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
3892 /* Special case for extui opcode which has constraints not handled
3893 by the ordinary operand encoding checks. The number of operands
3894 and related syntax issues have already been checked. */
3895 if (orig_insn
->opcode
== xtensa_extui_opcode
)
3897 int shiftimm
= orig_insn
->tok
[2].X_add_number
;
3898 int maskimm
= orig_insn
->tok
[3].X_add_number
;
3899 if (shiftimm
+ maskimm
> 32)
3901 as_bad (_("immediate operands sum to greater than 32"));
3906 /* If the instruction will definitely need to be relaxed, it is better
3907 to expand it now for better scheduling. Decide whether to expand
3909 do_expand
= (!orig_insn
->is_specific_opcode
&& use_transform ());
3911 /* Calls should be expanded to longcalls only in the backend relaxation
3912 so that the assembly scheduler will keep the L32R/CALLX instructions
3914 if (is_direct_call_opcode (orig_insn
->opcode
))
3917 if (tinsn_has_symbolic_operands (orig_insn
))
3919 /* The values of symbolic operands are not known yet, so only expand
3920 now if an operand is "complex" (e.g., difference of symbols) and
3921 will have to be stored as a literal regardless of the value. */
3922 if (!tinsn_has_complex_operands (orig_insn
))
3925 else if (xg_immeds_fit (orig_insn
))
3929 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
3931 istack_push (istack
, orig_insn
);
3937 /* Return TRUE if the section flags are marked linkonce
3938 or the name is .gnu.linkonce.*. */
3940 static int linkonce_len
= sizeof (".gnu.linkonce.") - 1;
3943 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
3945 flagword flags
, link_once_flags
;
3947 flags
= bfd_get_section_flags (abfd
, sec
);
3948 link_once_flags
= (flags
& SEC_LINK_ONCE
);
3950 /* Flags might not be set yet. */
3951 if (!link_once_flags
3952 && strncmp (segment_name (sec
), ".gnu.linkonce.", linkonce_len
) == 0)
3953 link_once_flags
= SEC_LINK_ONCE
;
3955 return (link_once_flags
!= 0);
3960 xtensa_add_literal_sym (symbolS
*sym
)
3964 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
3966 l
->next
= literal_syms
;
3972 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
3974 static int lit_num
= 0;
3975 static char name
[256];
3978 sprintf (name
, ".L_lit_sym%d", lit_num
);
3980 /* Create a local symbol. If it is in a linkonce section, we have to
3981 be careful to make sure that if it is used in a relocation that the
3982 symbol will be in the output file. */
3983 if (get_is_linkonce_section (stdoutput
, sec
))
3985 symbolP
= symbol_new (name
, sec
, 0, frag
);
3986 S_CLEAR_EXTERNAL (symbolP
);
3987 /* symbolP->local = 1; */
3990 symbolP
= symbol_new (name
, sec
, 0, frag
);
3992 xtensa_add_literal_sym (symbolP
);
3999 /* Currently all literals that are generated here are 32-bit L32R targets. */
4002 xg_assemble_literal (/* const */ TInsn
*insn
)
4005 symbolS
*lit_sym
= NULL
;
4006 bfd_reloc_code_real_type reloc
;
4009 /* size = 4 for L32R. It could easily be larger when we move to
4010 larger constants. Add a parameter later. */
4011 offsetT litsize
= 4;
4012 offsetT litalign
= 2; /* 2^2 = 4 */
4013 expressionS saved_loc
;
4014 expressionS
* emit_val
;
4016 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
4018 assert (insn
->insn_type
== ITYPE_LITERAL
);
4019 assert (insn
->ntok
== 1); /* must be only one token here */
4021 xtensa_switch_to_literal_fragment (&state
);
4023 emit_val
= &insn
->tok
[0];
4024 if (emit_val
->X_op
== O_big
)
4026 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
4029 /* This happens when someone writes a "movi a2, big_number". */
4030 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4031 _("invalid immediate"));
4032 xtensa_restore_emit_state (&state
);
4037 /* Force a 4-byte align here. Note that this opens a new frag, so all
4038 literals done with this function have a frag to themselves. That's
4039 important for the way text section literals work. */
4040 frag_align (litalign
, 0, 0);
4041 record_alignment (now_seg
, litalign
);
4043 switch (emit_val
->X_op
)
4046 p
= frag_more (litsize
);
4047 xtensa_set_frag_assembly_state (frag_now
);
4048 reloc
= map_operator_to_reloc (emit_val
->X_op
);
4049 if (emit_val
->X_add_symbol
)
4050 emit_val
->X_op
= O_symbol
;
4052 emit_val
->X_op
= O_constant
;
4053 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
4054 litsize
, emit_val
, 0, reloc
);
4058 emit_expr (emit_val
, litsize
);
4062 assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
4063 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4064 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4065 lit_sym
= frag_now
->fr_symbol
;
4068 xtensa_restore_emit_state (&state
);
4074 xg_assemble_literal_space (/* const */ int size
, int slot
)
4077 /* We might have to do something about this alignment. It only
4078 takes effect if something is placed here. */
4079 offsetT litalign
= 2; /* 2^2 = 4 */
4080 fragS
*lit_saved_frag
;
4082 assert (size
% 4 == 0);
4084 xtensa_switch_to_literal_fragment (&state
);
4086 /* Force a 4-byte align here. */
4087 frag_align (litalign
, 0, 0);
4088 record_alignment (now_seg
, litalign
);
4090 xg_force_frag_space (size
);
4092 lit_saved_frag
= frag_now
;
4093 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4094 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4095 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4098 xtensa_restore_emit_state (&state
);
4099 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4103 /* Put in a fixup record based on the opcode.
4104 Return TRUE on success. */
4107 xg_add_opcode_fix (TInsn
*tinsn
,
4115 xtensa_opcode opcode
= tinsn
->opcode
;
4116 bfd_reloc_code_real_type reloc
;
4117 reloc_howto_type
*howto
;
4121 reloc
= BFD_RELOC_NONE
;
4123 /* First try the special cases for "alternate" relocs. */
4124 if (opcode
== xtensa_l32r_opcode
)
4126 if (fragP
->tc_frag_data
.use_absolute_literals
)
4127 reloc
= encode_alt_reloc (slot
);
4129 else if (opcode
== xtensa_const16_opcode
)
4131 if (expr
->X_op
== O_lo16
)
4133 reloc
= encode_reloc (slot
);
4134 expr
->X_op
= O_symbol
;
4136 else if (expr
->X_op
== O_hi16
)
4138 reloc
= encode_alt_reloc (slot
);
4139 expr
->X_op
= O_symbol
;
4143 if (opnum
!= get_relaxable_immed (opcode
))
4145 as_bad (_("invalid relocation for operand %i of '%s'"),
4146 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4150 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4151 into the symbol table where the generic portions of the assembler
4152 won't know what to do with them. */
4153 if (expr
->X_op
== O_lo16
|| expr
->X_op
== O_hi16
)
4155 as_bad (_("invalid expression for operand %i of '%s'"),
4156 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4160 /* Next try the generic relocs. */
4161 if (reloc
== BFD_RELOC_NONE
)
4162 reloc
= encode_reloc (slot
);
4163 if (reloc
== BFD_RELOC_NONE
)
4165 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4169 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4172 as_bad (_("undefined symbol for opcode \"%s\""),
4173 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4177 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4178 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, expr
,
4179 howto
->pc_relative
, reloc
);
4180 the_fix
->fx_no_overflow
= 1;
4181 the_fix
->tc_fix_data
.X_add_symbol
= expr
->X_add_symbol
;
4182 the_fix
->tc_fix_data
.X_add_number
= expr
->X_add_number
;
4183 the_fix
->tc_fix_data
.slot
= slot
;
4190 xg_emit_insn_to_buf (TInsn
*tinsn
,
4194 bfd_boolean build_fix
)
4196 static xtensa_insnbuf insnbuf
= NULL
;
4197 bfd_boolean has_symbolic_immed
= FALSE
;
4198 bfd_boolean ok
= TRUE
;
4201 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4203 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4204 if (has_symbolic_immed
&& build_fix
)
4207 xtensa_format fmt
= xg_get_single_format (tinsn
->opcode
);
4208 int slot
= xg_get_single_slot (tinsn
->opcode
);
4209 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4210 expressionS
*exp
= &tinsn
->tok
[opnum
];
4212 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, slot
, exp
, fragP
, offset
))
4215 fragP
->tc_frag_data
.is_insn
= TRUE
;
4216 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4217 (unsigned char *) buf
, 0);
4223 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4225 symbolS
*sym
= get_special_literal_symbol ();
4229 assert (insn
->insn_type
== ITYPE_INSN
);
4230 for (i
= 0; i
< insn
->ntok
; i
++)
4231 if (insn
->tok
[i
].X_add_symbol
== sym
)
4232 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4238 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4240 symbolS
*sym
= get_special_label_symbol ();
4242 for (i
= 0; i
< insn
->ntok
; i
++)
4243 if (insn
->tok
[i
].X_add_symbol
== sym
)
4244 insn
->tok
[i
].X_add_symbol
= label_sym
;
4249 /* Return TRUE if the instruction can write to the specified
4250 integer register. */
4253 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4257 xtensa_isa isa
= xtensa_default_isa
;
4259 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4261 for (i
= 0; i
< num_ops
; i
++)
4264 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4265 if ((inout
== 'o' || inout
== 'm')
4266 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4268 xtensa_regfile opnd_rf
=
4269 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4270 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4272 if ((insn
->tok
[i
].X_op
== O_register
)
4273 && (insn
->tok
[i
].X_add_number
== regnum
))
4283 is_bad_loopend_opcode (const TInsn
*tinsn
)
4285 xtensa_opcode opcode
= tinsn
->opcode
;
4287 if (opcode
== XTENSA_UNDEFINED
)
4290 if (opcode
== xtensa_call0_opcode
4291 || opcode
== xtensa_callx0_opcode
4292 || opcode
== xtensa_call4_opcode
4293 || opcode
== xtensa_callx4_opcode
4294 || opcode
== xtensa_call8_opcode
4295 || opcode
== xtensa_callx8_opcode
4296 || opcode
== xtensa_call12_opcode
4297 || opcode
== xtensa_callx12_opcode
4298 || opcode
== xtensa_isync_opcode
4299 || opcode
== xtensa_ret_opcode
4300 || opcode
== xtensa_ret_n_opcode
4301 || opcode
== xtensa_retw_opcode
4302 || opcode
== xtensa_retw_n_opcode
4303 || opcode
== xtensa_waiti_opcode
4304 || opcode
== xtensa_rsr_lcount_opcode
)
4311 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4312 This allows the debugger to add unaligned labels.
4313 Also, the assembler generates stabs labels that need
4314 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4317 is_unaligned_label (symbolS
*sym
)
4319 const char *name
= S_GET_NAME (sym
);
4320 static size_t fake_size
= 0;
4324 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4327 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4329 fake_size
= strlen (FAKE_LABEL_NAME
);
4332 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4333 && (name
[fake_size
] == 'F'
4334 || name
[fake_size
] == 'L'
4335 || (name
[fake_size
] == 'e'
4336 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4344 next_non_empty_frag (const fragS
*fragP
)
4346 fragS
*next_fragP
= fragP
->fr_next
;
4348 /* Sometimes an empty will end up here due storage allocation issues.
4349 So we have to skip until we find something legit. */
4350 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4351 next_fragP
= next_fragP
->fr_next
;
4353 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4361 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4363 xtensa_opcode out_opcode
;
4364 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4366 if (next_fragP
== NULL
)
4369 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4370 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4372 *opcode
= out_opcode
;
4380 frag_format_size (const fragS
*fragP
)
4382 static xtensa_insnbuf insnbuf
= NULL
;
4383 xtensa_isa isa
= xtensa_default_isa
;
4388 insnbuf
= xtensa_insnbuf_alloc (isa
);
4391 return XTENSA_UNDEFINED
;
4393 xtensa_insnbuf_from_chars (isa
, insnbuf
,
4394 (unsigned char *) fragP
->fr_literal
, 0);
4396 fmt
= xtensa_format_decode (isa
, insnbuf
);
4397 if (fmt
== XTENSA_UNDEFINED
)
4398 return XTENSA_UNDEFINED
;
4399 fmt_size
= xtensa_format_length (isa
, fmt
);
4401 /* If the next format won't be changing due to relaxation, just
4402 return the length of the first format. */
4403 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4406 /* If during relaxation we have to pull an instruction out of a
4407 multi-slot instruction, we will return the more conservative
4408 number. This works because alignment on bigger instructions
4409 is more restrictive than alignment on smaller instructions.
4410 This is more conservative than we would like, but it happens
4413 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4416 /* If we aren't doing one of our own relaxations or it isn't
4417 slot-based, then the insn size won't change. */
4418 if (fragP
->fr_type
!= rs_machine_dependent
)
4420 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4423 /* If an instruction is about to grow, return the longer size. */
4424 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4425 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
4426 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP3
)
4429 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4430 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4437 next_frag_format_size (const fragS
*fragP
)
4439 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4440 return frag_format_size (next_fragP
);
4444 /* In early Xtensa Processors, for reasons that are unclear, the ISA
4445 required two-byte instructions to be treated as three-byte instructions
4446 for loop instruction alignment. This restriction was removed beginning
4447 with Xtensa LX. Now the only requirement on loop instruction alignment
4448 is that the first instruction of the loop must appear at an address that
4449 does not cross a fetch boundary. */
4452 get_loop_align_size (int insn_size
)
4454 if (insn_size
== XTENSA_UNDEFINED
)
4455 return xtensa_fetch_width
;
4457 if (enforce_three_byte_loop_align
&& insn_size
== 2)
4464 /* If the next legit fragment is an end-of-loop marker,
4465 switch its state so it will instantiate a NOP. */
4468 update_next_frag_state (fragS
*fragP
)
4470 fragS
*next_fragP
= fragP
->fr_next
;
4471 fragS
*new_target
= NULL
;
4475 /* We are guaranteed there will be one of these... */
4476 while (!(next_fragP
->fr_type
== rs_machine_dependent
4477 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4478 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4479 next_fragP
= next_fragP
->fr_next
;
4481 assert (next_fragP
->fr_type
== rs_machine_dependent
4482 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4483 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4485 /* ...and one of these. */
4486 new_target
= next_fragP
->fr_next
;
4487 while (!(new_target
->fr_type
== rs_machine_dependent
4488 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4489 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4490 new_target
= new_target
->fr_next
;
4492 assert (new_target
->fr_type
== rs_machine_dependent
4493 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4494 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4497 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4499 if (next_fragP
->fr_type
== rs_machine_dependent
4500 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4502 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4506 next_fragP
= next_fragP
->fr_next
;
4512 next_frag_is_branch_target (const fragS
*fragP
)
4514 /* Sometimes an empty will end up here due to storage allocation issues,
4515 so we have to skip until we find something legit. */
4516 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4518 if (fragP
->tc_frag_data
.is_branch_target
)
4520 if (fragP
->fr_fix
!= 0)
4528 next_frag_is_loop_target (const fragS
*fragP
)
4530 /* Sometimes an empty will end up here due storage allocation issues.
4531 So we have to skip until we find something legit. */
4532 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4534 if (fragP
->tc_frag_data
.is_loop_target
)
4536 if (fragP
->fr_fix
!= 0)
4544 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4546 const fragS
*next_fragp
= fragp
->fr_next
;
4547 xtensa_opcode next_opcode
;
4549 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4552 /* Sometimes an empty will end up here due to storage allocation issues,
4553 so we have to skip until we find something legit. */
4554 while (next_fragp
->fr_fix
== 0)
4555 next_fragp
= next_fragp
->fr_next
;
4557 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4560 /* There is some implicit knowledge encoded in here.
4561 The LOOP instructions that are NOT RELAX_IMMED have
4562 been relaxed. Note that we can assume that the LOOP
4563 instruction is in slot 0 because loops aren't bundleable. */
4564 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4565 return get_expanded_loop_offset (next_opcode
);
4571 /* Mark a location where we can later insert literal frags. Update
4572 the section's literal_pool_loc, so subsequent literals can be
4573 placed nearest to their use. */
4576 xtensa_mark_literal_pool_location (void)
4578 /* Any labels pointing to the current location need
4579 to be adjusted to after the literal pool. */
4581 fragS
*pool_location
;
4583 if (use_literal_section
)
4586 /* We stash info in these frags so we can later move the literal's
4587 fixes into this frchain's fix list. */
4588 pool_location
= frag_now
;
4589 frag_now
->tc_frag_data
.lit_frchain
= frchain_now
;
4590 frag_now
->tc_frag_data
.literal_frag
= frag_now
;
4591 frag_variant (rs_machine_dependent
, 0, 0,
4592 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4593 xtensa_set_frag_assembly_state (frag_now
);
4594 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
4595 frag_variant (rs_machine_dependent
, 0, 0,
4596 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4597 xtensa_set_frag_assembly_state (frag_now
);
4599 /* Now put a frag into the literal pool that points to this location. */
4600 set_literal_pool_location (now_seg
, pool_location
);
4601 xtensa_switch_to_non_abs_literal_fragment (&s
);
4602 frag_align (2, 0, 0);
4603 record_alignment (now_seg
, 2);
4605 /* Close whatever frag is there. */
4606 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4607 xtensa_set_frag_assembly_state (frag_now
);
4608 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
4609 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4610 xtensa_restore_emit_state (&s
);
4611 xtensa_set_frag_assembly_state (frag_now
);
4615 /* Build a nop of the correct size into tinsn. */
4618 build_nop (TInsn
*tinsn
, int size
)
4624 tinsn
->opcode
= xtensa_nop_n_opcode
;
4626 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4627 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4631 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4633 tinsn
->opcode
= xtensa_or_opcode
;
4634 set_expr_const (&tinsn
->tok
[0], 1);
4635 set_expr_const (&tinsn
->tok
[1], 1);
4636 set_expr_const (&tinsn
->tok
[2], 1);
4640 tinsn
->opcode
= xtensa_nop_opcode
;
4642 assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4647 /* Assemble a NOP of the requested size in the buffer. User must have
4648 allocated "buf" with at least "size" bytes. */
4651 assemble_nop (int size
, char *buf
)
4653 static xtensa_insnbuf insnbuf
= NULL
;
4656 build_nop (&tinsn
, size
);
4659 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4661 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4662 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4663 (unsigned char *) buf
, 0);
4667 /* Return the number of bytes for the offset of the expanded loop
4668 instruction. This should be incorporated into the relaxation
4669 specification but is hard-coded here. This is used to auto-align
4670 the loop instruction. It is invalid to call this function if the
4671 configuration does not have loops or if the opcode is not a loop
4675 get_expanded_loop_offset (xtensa_opcode opcode
)
4677 /* This is the OFFSET of the loop instruction in the expanded loop.
4678 This MUST correspond directly to the specification of the loop
4679 expansion. It will be validated on fragment conversion. */
4680 assert (opcode
!= XTENSA_UNDEFINED
);
4681 if (opcode
== xtensa_loop_opcode
)
4683 if (opcode
== xtensa_loopnez_opcode
)
4685 if (opcode
== xtensa_loopgtz_opcode
)
4687 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4693 get_literal_pool_location (segT seg
)
4695 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4700 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4702 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4706 /* Set frag assembly state should be called when a new frag is
4707 opened and after a frag has been closed. */
4710 xtensa_set_frag_assembly_state (fragS
*fragP
)
4712 if (!density_supported
)
4713 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4715 /* This function is called from subsegs_finish, which is called
4716 after xtensa_end, so we can't use "use_transform" or
4717 "use_schedule" here. */
4718 if (!directive_state
[directive_transform
])
4719 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4720 if (directive_state
[directive_longcalls
])
4721 fragP
->tc_frag_data
.use_longcalls
= TRUE
;
4722 fragP
->tc_frag_data
.use_absolute_literals
=
4723 directive_state
[directive_absolute_literals
];
4724 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4729 relaxable_section (asection
*sec
)
4731 return (sec
->flags
& SEC_DEBUGGING
) == 0;
4736 xtensa_mark_frags_for_org (void)
4740 /* Walk over each fragment of all of the current segments. If we find
4741 a .org frag in any of the segments, mark all frags prior to it as
4742 "no transform", which will prevent linker optimizations from messing
4743 up the .org distance. This should be done after
4744 xtensa_find_unmarked_state_frags, because we don't want to worry here
4745 about that function trashing the data we save here. */
4747 for (seclist
= &stdoutput
->sections
;
4748 seclist
&& *seclist
;
4749 seclist
= &(*seclist
)->next
)
4751 segT sec
= *seclist
;
4752 segment_info_type
*seginfo
;
4755 flags
= bfd_get_section_flags (stdoutput
, sec
);
4756 if (flags
& SEC_DEBUGGING
)
4758 if (!(flags
& SEC_ALLOC
))
4761 seginfo
= seg_info (sec
);
4762 if (seginfo
&& seginfo
->frchainP
)
4764 fragS
*last_fragP
= seginfo
->frchainP
->frch_root
;
4765 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4766 fragP
= fragP
->fr_next
)
4768 /* cvt_frag_to_fill has changed the fr_type of org frags to
4769 rs_fill, so use the value as cached in rs_subtype here. */
4770 if (fragP
->fr_subtype
== RELAX_ORG
)
4772 while (last_fragP
!= fragP
->fr_next
)
4774 last_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4775 last_fragP
= last_fragP
->fr_next
;
4785 xtensa_find_unmarked_state_frags (void)
4789 /* Walk over each fragment of all of the current segments. For each
4790 unmarked fragment, mark it with the same info as the previous
4792 for (seclist
= &stdoutput
->sections
;
4793 seclist
&& *seclist
;
4794 seclist
= &(*seclist
)->next
)
4796 segT sec
= *seclist
;
4797 segment_info_type
*seginfo
;
4800 flags
= bfd_get_section_flags (stdoutput
, sec
);
4801 if (flags
& SEC_DEBUGGING
)
4803 if (!(flags
& SEC_ALLOC
))
4806 seginfo
= seg_info (sec
);
4807 if (seginfo
&& seginfo
->frchainP
)
4809 fragS
*last_fragP
= 0;
4810 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4811 fragP
= fragP
->fr_next
)
4813 if (fragP
->fr_fix
!= 0
4814 && !fragP
->tc_frag_data
.is_assembly_state_set
)
4816 if (last_fragP
== 0)
4818 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
4819 _("assembly state not set for first frag in section %s"),
4824 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4825 fragP
->tc_frag_data
.is_no_density
=
4826 last_fragP
->tc_frag_data
.is_no_density
;
4827 fragP
->tc_frag_data
.is_no_transform
=
4828 last_fragP
->tc_frag_data
.is_no_transform
;
4829 fragP
->tc_frag_data
.use_longcalls
=
4830 last_fragP
->tc_frag_data
.use_longcalls
;
4831 fragP
->tc_frag_data
.use_absolute_literals
=
4832 last_fragP
->tc_frag_data
.use_absolute_literals
;
4835 if (fragP
->tc_frag_data
.is_assembly_state_set
)
4844 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
4846 void *unused ATTRIBUTE_UNUSED
)
4848 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4849 segment_info_type
*seginfo
= seg_info (sec
);
4850 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4852 if (flags
& SEC_CODE
)
4854 xtensa_isa isa
= xtensa_default_isa
;
4855 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4856 while (frag
!= NULL
)
4858 if (frag
->tc_frag_data
.is_branch_target
)
4861 addressT branch_align
, frag_addr
;
4864 xtensa_insnbuf_from_chars
4865 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4866 fmt
= xtensa_format_decode (isa
, insnbuf
);
4867 op_size
= xtensa_format_length (isa
, fmt
);
4868 branch_align
= 1 << branch_align_power (sec
);
4869 frag_addr
= frag
->fr_address
% branch_align
;
4870 if (frag_addr
+ op_size
> branch_align
)
4871 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4872 _("unaligned branch target: %d bytes at 0x%lx"),
4873 op_size
, (long) frag
->fr_address
);
4875 frag
= frag
->fr_next
;
4877 xtensa_insnbuf_free (isa
, insnbuf
);
4883 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
4885 void *unused ATTRIBUTE_UNUSED
)
4887 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4888 segment_info_type
*seginfo
= seg_info (sec
);
4889 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4890 xtensa_isa isa
= xtensa_default_isa
;
4892 if (flags
& SEC_CODE
)
4894 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4895 while (frag
!= NULL
)
4897 if (frag
->tc_frag_data
.is_first_loop_insn
)
4903 xtensa_insnbuf_from_chars
4904 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4905 fmt
= xtensa_format_decode (isa
, insnbuf
);
4906 op_size
= xtensa_format_length (isa
, fmt
);
4907 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
4909 if (frag_addr
+ op_size
> xtensa_fetch_width
)
4910 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4911 _("unaligned loop: %d bytes at 0x%lx"),
4912 op_size
, (long) frag
->fr_address
);
4914 frag
= frag
->fr_next
;
4916 xtensa_insnbuf_free (isa
, insnbuf
);
4922 xg_apply_fix_value (fixS
*fixP
, valueT val
)
4924 xtensa_isa isa
= xtensa_default_isa
;
4925 static xtensa_insnbuf insnbuf
= NULL
;
4926 static xtensa_insnbuf slotbuf
= NULL
;
4929 bfd_boolean alt_reloc
;
4930 xtensa_opcode opcode
;
4931 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
4933 (void) decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
);
4935 as_fatal (_("unexpected fix"));
4939 insnbuf
= xtensa_insnbuf_alloc (isa
);
4940 slotbuf
= xtensa_insnbuf_alloc (isa
);
4943 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4944 fmt
= xtensa_format_decode (isa
, insnbuf
);
4945 if (fmt
== XTENSA_UNDEFINED
)
4946 as_fatal (_("undecodable fix"));
4947 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4948 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
4949 if (opcode
== XTENSA_UNDEFINED
)
4950 as_fatal (_("undecodable fix"));
4952 /* CONST16 immediates are not PC-relative, despite the fact that we
4953 reuse the normal PC-relative operand relocations for the low part
4954 of a CONST16 operand. */
4955 if (opcode
== xtensa_const16_opcode
)
4958 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
4959 get_relaxable_immed (opcode
), val
,
4960 fixP
->fx_file
, fixP
->fx_line
);
4962 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4963 xtensa_insnbuf_to_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4969 /* External Functions and Other GAS Hooks. */
4972 xtensa_target_format (void)
4974 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
4979 xtensa_file_arch_init (bfd
*abfd
)
4981 bfd_set_private_flags (abfd
, 0x100 | 0x200);
4986 md_number_to_chars (char *buf
, valueT val
, int n
)
4988 if (target_big_endian
)
4989 number_to_chars_bigendian (buf
, val
, n
);
4991 number_to_chars_littleendian (buf
, val
, n
);
4995 /* This function is called once, at assembler startup time. It should
4996 set up all the tables, etc. that the MD part of the assembler will
5002 segT current_section
= now_seg
;
5003 int current_subsec
= now_subseg
;
5006 xtensa_default_isa
= xtensa_isa_init (0, 0);
5007 isa
= xtensa_default_isa
;
5011 /* Set up the literal sections. */
5012 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
5014 subseg_set (current_section
, current_subsec
);
5016 xg_init_vinsn (&cur_vinsn
);
5018 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
5019 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
5020 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
5021 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
5022 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
5023 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
5024 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
5025 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
5026 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
5027 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
5028 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
5029 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
5030 xtensa_extui_opcode
= xtensa_opcode_lookup (isa
, "extui");
5031 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
5032 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
5033 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
5034 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
5035 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
5036 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
5037 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
5038 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
5039 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
5040 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
5041 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
5042 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
5043 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
5044 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
5045 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
5046 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
5047 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
5049 init_op_placement_info_table ();
5051 /* Set up the assembly state. */
5052 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5053 xtensa_set_frag_assembly_state (frag_now
);
5057 /* TC_INIT_FIX_DATA hook */
5060 xtensa_init_fix_data (fixS
*x
)
5062 x
->tc_fix_data
.slot
= 0;
5063 x
->tc_fix_data
.X_add_symbol
= NULL
;
5064 x
->tc_fix_data
.X_add_number
= 0;
5068 /* tc_frob_label hook */
5071 xtensa_frob_label (symbolS
*sym
)
5075 if (cur_vinsn
.inside_bundle
)
5077 as_bad (_("labels are not valid inside bundles"));
5081 freq
= get_subseg_target_freq (now_seg
, now_subseg
);
5083 /* Since the label was already attached to a frag associated with the
5084 previous basic block, it now needs to be reset to the current frag. */
5085 symbol_set_frag (sym
, frag_now
);
5086 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5088 if (generating_literals
)
5089 xtensa_add_literal_sym (sym
);
5091 xtensa_add_insn_label (sym
);
5093 if (symbol_get_tc (sym
)->is_loop_target
)
5095 if ((get_last_insn_flags (now_seg
, now_subseg
)
5096 & FLAG_IS_BAD_LOOPEND
) != 0)
5097 as_bad (_("invalid last instruction for a zero-overhead loop"));
5099 xtensa_set_frag_assembly_state (frag_now
);
5100 frag_var (rs_machine_dependent
, 4, 4, RELAX_LOOP_END
,
5101 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5103 xtensa_set_frag_assembly_state (frag_now
);
5104 xtensa_move_labels (frag_now
, 0);
5107 /* No target aligning in the absolute section. */
5108 if (now_seg
!= absolute_section
5109 && do_align_targets ()
5110 && !is_unaligned_label (sym
)
5111 && !generating_literals
)
5113 xtensa_set_frag_assembly_state (frag_now
);
5115 frag_var (rs_machine_dependent
,
5117 RELAX_DESIRE_ALIGN_IF_TARGET
,
5118 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5119 xtensa_set_frag_assembly_state (frag_now
);
5120 xtensa_move_labels (frag_now
, 0);
5123 /* We need to mark the following properties even if we aren't aligning. */
5125 /* If the label is already known to be a branch target, i.e., a
5126 forward branch, mark the frag accordingly. Backward branches
5127 are handled by xg_add_branch_and_loop_targets. */
5128 if (symbol_get_tc (sym
)->is_branch_target
)
5129 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5131 /* Loops only go forward, so they can be identified here. */
5132 if (symbol_get_tc (sym
)->is_loop_target
)
5133 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5135 dwarf2_emit_label (sym
);
5139 /* tc_unrecognized_line hook */
5142 xtensa_unrecognized_line (int ch
)
5147 if (cur_vinsn
.inside_bundle
== 0)
5149 /* PR8110: Cannot emit line number info inside a FLIX bundle
5150 when using --gstabs. Temporarily disable debug info. */
5151 generate_lineno_debug ();
5152 if (debug_type
== DEBUG_STABS
)
5154 xt_saved_debug_type
= debug_type
;
5155 debug_type
= DEBUG_NONE
;
5158 cur_vinsn
.inside_bundle
= 1;
5162 as_bad (_("extra opening brace"));
5168 if (cur_vinsn
.inside_bundle
)
5169 finish_vinsn (&cur_vinsn
);
5172 as_bad (_("extra closing brace"));
5177 as_bad (_("syntax error"));
5184 /* md_flush_pending_output hook */
5187 xtensa_flush_pending_output (void)
5189 /* This line fixes a bug where automatically generated gstabs info
5190 separates a function label from its entry instruction, ending up
5191 with the literal position between the function label and the entry
5192 instruction and crashing code. It only happens with --gstabs and
5193 --text-section-literals, and when several other obscure relaxation
5194 conditions are met. */
5195 if (outputting_stabs_line_debug
)
5198 if (cur_vinsn
.inside_bundle
)
5199 as_bad (_("missing closing brace"));
5201 /* If there is a non-zero instruction fragment, close it. */
5202 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5204 frag_wane (frag_now
);
5206 xtensa_set_frag_assembly_state (frag_now
);
5208 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5210 xtensa_clear_insn_labels ();
5214 /* We had an error while parsing an instruction. The string might look
5215 like this: "insn arg1, arg2 }". If so, we need to see the closing
5216 brace and reset some fields. Otherwise, the vinsn never gets closed
5217 and the num_slots field will grow past the end of the array of slots,
5218 and bad things happen. */
5221 error_reset_cur_vinsn (void)
5223 if (cur_vinsn
.inside_bundle
)
5225 if (*input_line_pointer
== '}'
5226 || *(input_line_pointer
- 1) == '}'
5227 || *(input_line_pointer
- 2) == '}')
5228 xg_clear_vinsn (&cur_vinsn
);
5234 md_assemble (char *str
)
5236 xtensa_isa isa
= xtensa_default_isa
;
5237 char *opname
, *file_name
;
5239 bfd_boolean has_underbar
= FALSE
;
5240 char *arg_strings
[MAX_INSN_ARGS
];
5242 TInsn orig_insn
; /* Original instruction from the input. */
5244 tinsn_init (&orig_insn
);
5246 /* Split off the opcode. */
5247 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5248 opname
= xmalloc (opnamelen
+ 1);
5249 memcpy (opname
, str
, opnamelen
);
5250 opname
[opnamelen
] = '\0';
5252 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5255 as_bad (_("syntax error"));
5259 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5262 /* Check for an underbar prefix. */
5265 has_underbar
= TRUE
;
5269 orig_insn
.insn_type
= ITYPE_INSN
;
5271 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5273 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5274 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5276 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5277 if (fmt
== XTENSA_UNDEFINED
)
5279 as_bad (_("unknown opcode or format name '%s'"), opname
);
5280 error_reset_cur_vinsn ();
5283 if (!cur_vinsn
.inside_bundle
)
5285 as_bad (_("format names only valid inside bundles"));
5286 error_reset_cur_vinsn ();
5289 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5290 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5292 cur_vinsn
.format
= fmt
;
5293 free (has_underbar
? opname
- 1 : opname
);
5294 error_reset_cur_vinsn ();
5298 /* Parse the arguments. */
5299 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5301 as_bad (_("syntax error"));
5302 error_reset_cur_vinsn ();
5306 /* Free the opcode and argument strings, now that they've been parsed. */
5307 free (has_underbar
? opname
- 1 : opname
);
5309 while (num_args
-- > 0)
5310 free (arg_strings
[num_args
]);
5312 /* Get expressions for invisible operands. */
5313 if (get_invisible_operands (&orig_insn
))
5315 error_reset_cur_vinsn ();
5319 /* Check for the right number and type of arguments. */
5320 if (tinsn_check_arguments (&orig_insn
))
5322 error_reset_cur_vinsn ();
5326 /* A FLIX bundle may be spread across multiple input lines. We want to
5327 report the first such line in the debug information. Record the line
5328 number for each TInsn (assume the file name doesn't change), so the
5329 first line can be found later. */
5330 as_where (&file_name
, &orig_insn
.linenum
);
5332 xg_add_branch_and_loop_targets (&orig_insn
);
5334 /* Check that immediate value for ENTRY is >= 16. */
5335 if (orig_insn
.opcode
== xtensa_entry_opcode
&& orig_insn
.ntok
>= 3)
5337 expressionS
*exp
= &orig_insn
.tok
[2];
5338 if (exp
->X_op
== O_constant
&& exp
->X_add_number
< 16)
5339 as_warn (_("entry instruction with stack decrement < 16"));
5343 assemble_tokens (opcode, tok, ntok);
5344 expand the tokens from the orig_insn into the
5345 stack of instructions that will not expand
5346 unless required at relaxation time. */
5348 if (!cur_vinsn
.inside_bundle
)
5349 emit_single_op (&orig_insn
);
5350 else /* We are inside a bundle. */
5352 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5353 cur_vinsn
.num_slots
++;
5354 if (*input_line_pointer
== '}'
5355 || *(input_line_pointer
- 1) == '}'
5356 || *(input_line_pointer
- 2) == '}')
5357 finish_vinsn (&cur_vinsn
);
5360 /* We've just emitted a new instruction so clear the list of labels. */
5361 xtensa_clear_insn_labels ();
5365 /* HANDLE_ALIGN hook */
5367 /* For a .align directive, we mark the previous block with the alignment
5368 information. This will be placed in the object file in the
5369 property section corresponding to this section. */
5372 xtensa_handle_align (fragS
*fragP
)
5375 && ! fragP
->tc_frag_data
.is_literal
5376 && (fragP
->fr_type
== rs_align
5377 || fragP
->fr_type
== rs_align_code
)
5378 && fragP
->fr_address
+ fragP
->fr_fix
> 0
5379 && fragP
->fr_offset
> 0
5380 && now_seg
!= bss_section
)
5382 fragP
->tc_frag_data
.is_align
= TRUE
;
5383 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5386 if (fragP
->fr_type
== rs_align_test
)
5389 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5391 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5392 _("unaligned entry instruction"));
5395 if (linkrelax
&& fragP
->fr_type
== rs_org
)
5396 fragP
->fr_subtype
= RELAX_ORG
;
5400 /* TC_FRAG_INIT hook */
5403 xtensa_frag_init (fragS
*frag
)
5405 xtensa_set_frag_assembly_state (frag
);
5410 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5416 /* Round up a section size to the appropriate boundary. */
5419 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5421 return size
; /* Byte alignment is fine. */
5426 md_pcrel_from (fixS
*fixP
)
5429 static xtensa_insnbuf insnbuf
= NULL
;
5430 static xtensa_insnbuf slotbuf
= NULL
;
5433 xtensa_opcode opcode
;
5436 xtensa_isa isa
= xtensa_default_isa
;
5437 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5438 bfd_boolean alt_reloc
;
5440 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5445 insnbuf
= xtensa_insnbuf_alloc (isa
);
5446 slotbuf
= xtensa_insnbuf_alloc (isa
);
5449 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5450 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) insn_p
, 0);
5451 fmt
= xtensa_format_decode (isa
, insnbuf
);
5453 if (fmt
== XTENSA_UNDEFINED
)
5454 as_fatal (_("bad instruction format"));
5456 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5457 as_fatal (_("invalid relocation"));
5459 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5460 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5462 /* Check for "alternate" relocations (operand not specified). None
5463 of the current uses for these are really PC-relative. */
5464 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5466 if (opcode
!= xtensa_l32r_opcode
5467 && opcode
!= xtensa_const16_opcode
)
5468 as_fatal (_("invalid relocation for '%s' instruction"),
5469 xtensa_opcode_name (isa
, opcode
));
5473 opnum
= get_relaxable_immed (opcode
);
5475 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5476 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5478 as_bad_where (fixP
->fx_file
,
5480 _("invalid relocation for operand %d of '%s'"),
5481 opnum
, xtensa_opcode_name (isa
, opcode
));
5484 return 0 - opnd_value
;
5488 /* TC_FORCE_RELOCATION hook */
5491 xtensa_force_relocation (fixS
*fix
)
5493 switch (fix
->fx_r_type
)
5495 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5496 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5497 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5498 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5499 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5500 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5501 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5502 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5503 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5504 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5505 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5506 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5507 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5508 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5509 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5510 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5516 if (linkrelax
&& fix
->fx_addsy
5517 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5520 return generic_force_reloc (fix
);
5524 /* TC_VALIDATE_FIX_SUB hook */
5527 xtensa_validate_fix_sub (fixS
*fix
)
5529 segT add_symbol_segment
, sub_symbol_segment
;
5531 /* The difference of two symbols should be resolved by the assembler when
5532 linkrelax is not set. If the linker may relax the section containing
5533 the symbols, then an Xtensa DIFF relocation must be generated so that
5534 the linker knows to adjust the difference value. */
5535 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
5538 /* Make sure both symbols are in the same segment, and that segment is
5539 "normal" and relaxable. If the segment is not "normal", then the
5540 fix is not valid. If the segment is not "relaxable", then the fix
5541 should have been handled earlier. */
5542 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
5543 if (! SEG_NORMAL (add_symbol_segment
) ||
5544 ! relaxable_section (add_symbol_segment
))
5546 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
5547 return (sub_symbol_segment
== add_symbol_segment
);
5551 /* NO_PSEUDO_DOT hook */
5553 /* This function has nothing to do with pseudo dots, but this is the
5554 nearest macro to where the check needs to take place. FIXME: This
5558 xtensa_check_inside_bundle (void)
5560 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5561 as_bad (_("directives are not valid inside bundles"));
5563 /* This function must always return FALSE because it is called via a
5564 macro that has nothing to do with bundling. */
5569 /* md_elf_section_change_hook */
5572 xtensa_elf_section_change_hook (void)
5574 /* Set up the assembly state. */
5575 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5576 xtensa_set_frag_assembly_state (frag_now
);
5580 /* tc_fix_adjustable hook */
5583 xtensa_fix_adjustable (fixS
*fixP
)
5585 /* An offset is not allowed in combination with the difference of two
5586 symbols, but that cannot be easily detected after a local symbol
5587 has been adjusted to a (section+offset) form. Return 0 so that such
5588 an fix will not be adjusted. */
5589 if (fixP
->fx_subsy
&& fixP
->fx_addsy
&& fixP
->fx_offset
5590 && relaxable_section (S_GET_SEGMENT (fixP
->fx_subsy
)))
5593 /* We need the symbol name for the VTABLE entries. */
5594 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5595 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5603 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg
)
5605 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5608 /* Subtracted symbols are only allowed for a few relocation types, and
5609 unless linkrelax is enabled, they should not make it to this point. */
5610 if (fixP
->fx_subsy
&& !(linkrelax
&& (fixP
->fx_r_type
== BFD_RELOC_32
5611 || fixP
->fx_r_type
== BFD_RELOC_16
5612 || fixP
->fx_r_type
== BFD_RELOC_8
)))
5613 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("expression too complex"));
5615 switch (fixP
->fx_r_type
)
5622 switch (fixP
->fx_r_type
)
5625 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF8
;
5628 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF16
;
5631 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF32
;
5637 /* An offset is only allowed when it results from adjusting a
5638 local symbol into a section-relative offset. If the offset
5639 came from the original expression, tc_fix_adjustable will have
5640 prevented the fix from being converted to a section-relative
5641 form so that we can flag the error here. */
5642 if (fixP
->fx_offset
!= 0 && !symbol_section_p (fixP
->fx_addsy
))
5643 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5644 _("cannot represent subtraction with an offset"));
5646 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5647 - S_GET_VALUE (fixP
->fx_subsy
));
5649 /* The difference value gets written out, and the DIFF reloc
5650 identifies the address of the subtracted symbol (i.e., the one
5651 with the lowest address). */
5653 fixP
->fx_offset
-= val
;
5654 fixP
->fx_subsy
= NULL
;
5656 else if (! fixP
->fx_addsy
)
5663 case BFD_RELOC_XTENSA_PLT
:
5664 md_number_to_chars (fixpos
, val
, fixP
->fx_size
);
5665 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5668 case BFD_RELOC_XTENSA_SLOT0_OP
:
5669 case BFD_RELOC_XTENSA_SLOT1_OP
:
5670 case BFD_RELOC_XTENSA_SLOT2_OP
:
5671 case BFD_RELOC_XTENSA_SLOT3_OP
:
5672 case BFD_RELOC_XTENSA_SLOT4_OP
:
5673 case BFD_RELOC_XTENSA_SLOT5_OP
:
5674 case BFD_RELOC_XTENSA_SLOT6_OP
:
5675 case BFD_RELOC_XTENSA_SLOT7_OP
:
5676 case BFD_RELOC_XTENSA_SLOT8_OP
:
5677 case BFD_RELOC_XTENSA_SLOT9_OP
:
5678 case BFD_RELOC_XTENSA_SLOT10_OP
:
5679 case BFD_RELOC_XTENSA_SLOT11_OP
:
5680 case BFD_RELOC_XTENSA_SLOT12_OP
:
5681 case BFD_RELOC_XTENSA_SLOT13_OP
:
5682 case BFD_RELOC_XTENSA_SLOT14_OP
:
5685 /* Write the tentative value of a PC-relative relocation to a
5686 local symbol into the instruction. The value will be ignored
5687 by the linker, and it makes the object file disassembly
5688 readable when all branch targets are encoded in relocations. */
5690 assert (fixP
->fx_addsy
);
5691 if (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
5692 && !S_FORCE_RELOC (fixP
->fx_addsy
, 1))
5694 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5695 - md_pcrel_from (fixP
));
5696 (void) xg_apply_fix_value (fixP
, val
);
5699 else if (! fixP
->fx_addsy
)
5702 if (xg_apply_fix_value (fixP
, val
))
5707 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5708 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5709 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5710 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5711 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5712 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5713 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5714 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5715 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5716 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5717 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5718 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5719 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5720 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5721 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5722 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5723 /* These all need to be resolved at link-time. Do nothing now. */
5726 case BFD_RELOC_VTABLE_INHERIT
:
5727 case BFD_RELOC_VTABLE_ENTRY
:
5732 as_bad (_("unhandled local relocation fix %s"),
5733 bfd_get_reloc_code_name (fixP
->fx_r_type
));
5739 md_atof (int type
, char *litP
, int *sizeP
)
5741 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
5746 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
5748 return total_frag_text_expansion (fragP
);
5752 /* Translate internal representation of relocation info to BFD target
5756 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
5760 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
5761 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5762 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5763 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5765 /* Make sure none of our internal relocations make it this far.
5766 They'd better have been fully resolved by this point. */
5767 assert ((int) fixp
->fx_r_type
> 0);
5769 reloc
->addend
= fixp
->fx_offset
;
5771 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
5772 if (reloc
->howto
== NULL
)
5774 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5775 _("cannot represent `%s' relocation in object file"),
5776 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5777 free (reloc
->sym_ptr_ptr
);
5782 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
5783 as_fatal (_("internal error? cannot generate `%s' relocation"),
5784 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5790 /* Checks for resource conflicts between instructions. */
5792 /* The func unit stuff could be implemented as bit-vectors rather
5793 than the iterative approach here. If it ends up being too
5794 slow, we will switch it. */
5797 new_resource_table (void *data
,
5800 unit_num_copies_func uncf
,
5801 opcode_num_units_func onuf
,
5802 opcode_funcUnit_use_unit_func ouuf
,
5803 opcode_funcUnit_use_stage_func ousf
)
5806 resource_table
*rt
= (resource_table
*) xmalloc (sizeof (resource_table
));
5808 rt
->cycles
= cycles
;
5809 rt
->allocated_cycles
= cycles
;
5811 rt
->unit_num_copies
= uncf
;
5812 rt
->opcode_num_units
= onuf
;
5813 rt
->opcode_unit_use
= ouuf
;
5814 rt
->opcode_unit_stage
= ousf
;
5816 rt
->units
= (unsigned char **) xcalloc (cycles
, sizeof (unsigned char *));
5817 for (i
= 0; i
< cycles
; i
++)
5818 rt
->units
[i
] = (unsigned char *) xcalloc (nu
, sizeof (unsigned char));
5825 clear_resource_table (resource_table
*rt
)
5828 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
5829 for (j
= 0; j
< rt
->num_units
; j
++)
5830 rt
->units
[i
][j
] = 0;
5834 /* We never shrink it, just fake it into thinking so. */
5837 resize_resource_table (resource_table
*rt
, int cycles
)
5841 rt
->cycles
= cycles
;
5842 if (cycles
<= rt
->allocated_cycles
)
5845 old_cycles
= rt
->allocated_cycles
;
5846 rt
->allocated_cycles
= cycles
;
5848 rt
->units
= xrealloc (rt
->units
,
5849 rt
->allocated_cycles
* sizeof (unsigned char *));
5850 for (i
= 0; i
< old_cycles
; i
++)
5851 rt
->units
[i
] = xrealloc (rt
->units
[i
],
5852 rt
->num_units
* sizeof (unsigned char));
5853 for (i
= old_cycles
; i
< cycles
; i
++)
5854 rt
->units
[i
] = xcalloc (rt
->num_units
, sizeof (unsigned char));
5859 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5862 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5864 for (i
= 0; i
< uses
; i
++)
5866 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5867 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5868 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
5869 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
5870 if (copies_in_use
>= copies
)
5878 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5881 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5883 for (i
= 0; i
< uses
; i
++)
5885 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5886 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5887 /* Note that this allows resources to be oversubscribed. That's
5888 essential to the way the optional scheduler works.
5889 resources_available reports when a resource is over-subscribed,
5890 so it's easy to tell. */
5891 rt
->units
[stage
+ cycle
][unit
]++;
5897 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5900 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5902 for (i
= 0; i
< uses
; i
++)
5904 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5905 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5906 assert (rt
->units
[stage
+ cycle
][unit
] > 0);
5907 rt
->units
[stage
+ cycle
][unit
]--;
5912 /* Wrapper functions make parameterized resource reservation
5916 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
5918 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5924 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
5926 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5931 /* Note that this function does not check issue constraints, but
5932 solely whether the hardware is available to execute the given
5933 instructions together. It also doesn't check if the tinsns
5934 write the same state, or access the same tieports. That is
5935 checked by check_t1_t2_reads_and_writes. */
5938 resources_conflict (vliw_insn
*vinsn
)
5941 static resource_table
*rt
= NULL
;
5943 /* This is the most common case by far. Optimize it. */
5944 if (vinsn
->num_slots
== 1)
5949 xtensa_isa isa
= xtensa_default_isa
;
5950 rt
= new_resource_table
5951 (isa
, xtensa_isa_num_pipe_stages (isa
),
5952 xtensa_isa_num_funcUnits (isa
),
5953 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
5954 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
5955 opcode_funcUnit_use_unit
,
5956 opcode_funcUnit_use_stage
);
5959 clear_resource_table (rt
);
5961 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5963 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
5965 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
5972 /* finish_vinsn, emit_single_op and helper functions. */
5974 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
5975 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
5976 static void xg_assemble_vliw_tokens (vliw_insn
*);
5979 /* We have reached the end of a bundle; emit into the frag. */
5982 finish_vinsn (vliw_insn
*vinsn
)
5989 if (find_vinsn_conflicts (vinsn
))
5991 xg_clear_vinsn (vinsn
);
5995 /* First, find a format that works. */
5996 if (vinsn
->format
== XTENSA_UNDEFINED
)
5997 vinsn
->format
= xg_find_narrowest_format (vinsn
);
5999 if (vinsn
->format
== XTENSA_UNDEFINED
)
6001 as_where (&file_name
, &line
);
6002 as_bad_where (file_name
, line
,
6003 _("couldn't find a valid instruction format"));
6004 fprintf (stderr
, _(" ops were: "));
6005 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6006 fprintf (stderr
, _(" %s;"),
6007 xtensa_opcode_name (xtensa_default_isa
,
6008 vinsn
->slots
[i
].opcode
));
6009 fprintf (stderr
, _("\n"));
6010 xg_clear_vinsn (vinsn
);
6014 if (vinsn
->num_slots
6015 != xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
))
6017 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
6018 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
6019 xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
),
6021 xg_clear_vinsn (vinsn
);
6025 if (resources_conflict (vinsn
))
6027 as_where (&file_name
, &line
);
6028 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6029 fprintf (stderr
, " ops were: ");
6030 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6031 fprintf (stderr
, " %s;",
6032 xtensa_opcode_name (xtensa_default_isa
,
6033 vinsn
->slots
[i
].opcode
));
6034 fprintf (stderr
, "\n");
6035 xg_clear_vinsn (vinsn
);
6039 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6041 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
6043 symbolS
*lit_sym
= NULL
;
6045 bfd_boolean e
= FALSE
;
6046 bfd_boolean saved_density
= density_supported
;
6048 /* We don't want to narrow ops inside multi-slot bundles. */
6049 if (vinsn
->num_slots
> 1)
6050 density_supported
= FALSE
;
6052 istack_init (&slotstack
);
6053 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
6055 vinsn
->slots
[i
].opcode
=
6056 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6058 vinsn
->slots
[i
].ntok
= 0;
6061 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
6067 density_supported
= saved_density
;
6071 xg_clear_vinsn (vinsn
);
6075 for (j
= 0; j
< slotstack
.ninsn
; j
++)
6077 TInsn
*insn
= &slotstack
.insn
[j
];
6078 if (insn
->insn_type
== ITYPE_LITERAL
)
6080 assert (lit_sym
== NULL
);
6081 lit_sym
= xg_assemble_literal (insn
);
6085 assert (insn
->insn_type
== ITYPE_INSN
);
6087 xg_resolve_literals (insn
, lit_sym
);
6088 if (j
!= slotstack
.ninsn
- 1)
6089 emit_single_op (insn
);
6093 if (vinsn
->num_slots
> 1)
6095 if (opcode_fits_format_slot
6096 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6099 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6103 emit_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6104 if (vinsn
->format
== XTENSA_UNDEFINED
)
6105 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6107 vinsn
->slots
[i
].opcode
6108 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6111 vinsn
->slots
[i
].ntok
= 0;
6116 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6117 vinsn
->format
= XTENSA_UNDEFINED
;
6122 /* Now check resource conflicts on the modified bundle. */
6123 if (resources_conflict (vinsn
))
6125 as_where (&file_name
, &line
);
6126 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6127 fprintf (stderr
, " ops were: ");
6128 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6129 fprintf (stderr
, " %s;",
6130 xtensa_opcode_name (xtensa_default_isa
,
6131 vinsn
->slots
[i
].opcode
));
6132 fprintf (stderr
, "\n");
6133 xg_clear_vinsn (vinsn
);
6137 /* First, find a format that works. */
6138 if (vinsn
->format
== XTENSA_UNDEFINED
)
6139 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6141 xg_assemble_vliw_tokens (vinsn
);
6143 xg_clear_vinsn (vinsn
);
6147 /* Given an vliw instruction, what conflicts are there in register
6148 usage and in writes to states and queues?
6150 This function does two things:
6151 1. Reports an error when a vinsn contains illegal combinations
6152 of writes to registers states or queues.
6153 2. Marks individual tinsns as not relaxable if the combination
6154 contains antidependencies.
6156 Job 2 handles things like swap semantics in instructions that need
6157 to be relaxed. For example,
6161 normally would be relaxed to
6166 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6168 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6170 then we can't relax it into
6173 { add a0, a1, a0 ; add a2, a0, a4 ; }
6175 because the value of a0 is trashed before the second add can read it. */
6177 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6180 find_vinsn_conflicts (vliw_insn
*vinsn
)
6184 xtensa_isa isa
= xtensa_default_isa
;
6186 assert (!past_xtensa_end
);
6188 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6190 TInsn
*op1
= &vinsn
->slots
[i
];
6191 if (op1
->is_specific_opcode
)
6192 op1
->keep_wide
= TRUE
;
6194 op1
->keep_wide
= FALSE
;
6197 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6199 TInsn
*op1
= &vinsn
->slots
[i
];
6201 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6204 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6208 TInsn
*op2
= &vinsn
->slots
[j
];
6209 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6210 switch (conflict_type
)
6213 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6214 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6215 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6218 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6219 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6220 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6223 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"),
6224 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6225 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6228 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"),
6229 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6230 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6233 /* Everything is OK. */
6236 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6237 || conflict_type
== 'a');
6244 as_bad (_("multiple branches or jumps in the same bundle"));
6252 /* Check how the state used by t1 and t2 relate.
6255 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6256 case B: no relationship between what is read and written (both could
6257 read the same reg though)
6258 case C: t1 writes a register t2 writes (a register conflict within a
6260 case D: t1 writes a state that t2 also writes
6261 case E: t1 writes a tie queue that t2 also writes
6262 case F: two volatile queue accesses
6266 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6268 xtensa_isa isa
= xtensa_default_isa
;
6269 xtensa_regfile t1_regfile
, t2_regfile
;
6271 int t1_base_reg
, t1_last_reg
;
6272 int t2_base_reg
, t2_last_reg
;
6273 char t1_inout
, t2_inout
;
6275 char conflict
= 'b';
6280 bfd_boolean t1_volatile
= FALSE
;
6281 bfd_boolean t2_volatile
= FALSE
;
6283 /* Check registers. */
6284 for (j
= 0; j
< t2
->ntok
; j
++)
6286 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6289 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6290 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6291 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6293 for (i
= 0; i
< t1
->ntok
; i
++)
6295 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6298 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6300 if (t1_regfile
!= t2_regfile
)
6303 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6304 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6306 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6307 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6309 if (t1_inout
== 'm' || t1_inout
== 'o'
6310 || t2_inout
== 'm' || t2_inout
== 'o')
6317 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6318 t1_last_reg
= (t1_base_reg
6319 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6321 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6323 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6325 if (t1_reg
!= t2_reg
)
6328 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6334 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6340 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6348 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6349 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6350 for (j
= 0; j
< t2_states
; j
++)
6352 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6353 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6354 for (i
= 0; i
< t1_states
; i
++)
6356 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6357 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6361 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6367 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6373 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6378 /* Check tieports. */
6379 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6380 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6381 for (j
= 0; j
< t2_interfaces
; j
++)
6383 xtensa_interface t2_int
6384 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6385 int t2_class
= xtensa_interface_class_id (isa
, t2_int
);
6387 t2_inout
= xtensa_interface_inout (isa
, t2_int
);
6388 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1)
6391 for (i
= 0; i
< t1_interfaces
; i
++)
6393 xtensa_interface t1_int
6394 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6395 int t1_class
= xtensa_interface_class_id (isa
, t1_int
);
6397 t1_inout
= xtensa_interface_inout (isa
, t1_int
);
6398 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1)
6401 if (t1_volatile
&& t2_volatile
&& (t1_class
== t2_class
))
6404 if (t1_int
!= t2_int
)
6407 if (t2_inout
== 'i' && t1_inout
== 'o')
6413 if (t1_inout
== 'i' && t2_inout
== 'o')
6419 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6428 static xtensa_format
6429 xg_find_narrowest_format (vliw_insn
*vinsn
)
6431 /* Right now we assume that the ops within the vinsn are properly
6432 ordered for the slots that the programmer wanted them in. In
6433 other words, we don't rearrange the ops in hopes of finding a
6434 better format. The scheduler handles that. */
6436 xtensa_isa isa
= xtensa_default_isa
;
6437 xtensa_format format
;
6438 vliw_insn v_copy
= *vinsn
;
6439 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6441 if (vinsn
->num_slots
== 1)
6442 return xg_get_single_format (vinsn
->slots
[0].opcode
);
6444 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6447 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6451 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6453 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6455 v_copy
.slots
[slot
].opcode
=
6456 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6457 v_copy
.slots
[slot
].ntok
= 0;
6460 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6463 else if (v_copy
.num_slots
> 1)
6466 /* Try the widened version. */
6467 if (!v_copy
.slots
[slot
].keep_wide
6468 && !v_copy
.slots
[slot
].is_specific_opcode
6469 && xg_is_single_relaxable_insn (&v_copy
.slots
[slot
],
6471 && opcode_fits_format_slot (widened
.opcode
,
6474 v_copy
.slots
[slot
] = widened
;
6479 if (fit
== v_copy
.num_slots
)
6482 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6483 vinsn
->format
= format
;
6489 if (format
== xtensa_isa_num_formats (isa
))
6490 return XTENSA_UNDEFINED
;
6496 /* Return the additional space needed in a frag
6497 for possible relaxations of any ops in a VLIW insn.
6498 Also fill out the relaxations that might be required of
6499 each tinsn in the vinsn. */
6502 relaxation_requirements (vliw_insn
*vinsn
, bfd_boolean
*pfinish_frag
)
6504 bfd_boolean finish_frag
= FALSE
;
6505 int extra_space
= 0;
6508 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6510 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6511 if (!tinsn_has_symbolic_operands (tinsn
))
6513 /* A narrow instruction could be widened later to help
6514 alignment issues. */
6515 if (xg_is_single_relaxable_insn (tinsn
, 0, TRUE
)
6516 && !tinsn
->is_specific_opcode
6517 && vinsn
->num_slots
== 1)
6519 /* Difference in bytes between narrow and wide insns... */
6521 tinsn
->subtype
= RELAX_NARROW
;
6526 if (workaround_b_j_loop_end
6527 && tinsn
->opcode
== xtensa_jx_opcode
6528 && use_transform ())
6530 /* Add 2 of these. */
6531 extra_space
+= 3; /* for the nop size */
6532 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6535 /* Need to assemble it with space for the relocation. */
6536 if (xg_is_relaxable_insn (tinsn
, 0)
6537 && !tinsn
->is_specific_opcode
)
6539 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6540 int max_literal_size
=
6541 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6543 tinsn
->literal_space
= max_literal_size
;
6545 tinsn
->subtype
= RELAX_IMMED
;
6546 extra_space
+= max_size
;
6550 /* A fix record will be added for this instruction prior
6551 to relaxation, so make it end the frag. */
6556 *pfinish_frag
= finish_frag
;
6562 bundle_tinsn (TInsn
*tinsn
, vliw_insn
*vinsn
)
6564 xtensa_isa isa
= xtensa_default_isa
;
6565 int slot
, chosen_slot
;
6567 vinsn
->format
= xg_get_single_format (tinsn
->opcode
);
6568 assert (vinsn
->format
!= XTENSA_UNDEFINED
);
6569 vinsn
->num_slots
= xtensa_format_num_slots (isa
, vinsn
->format
);
6571 chosen_slot
= xg_get_single_slot (tinsn
->opcode
);
6572 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6574 if (slot
== chosen_slot
)
6575 vinsn
->slots
[slot
] = *tinsn
;
6578 vinsn
->slots
[slot
].opcode
=
6579 xtensa_format_slot_nop_opcode (isa
, vinsn
->format
, slot
);
6580 vinsn
->slots
[slot
].ntok
= 0;
6581 vinsn
->slots
[slot
].insn_type
= ITYPE_INSN
;
6588 emit_single_op (TInsn
*orig_insn
)
6591 IStack istack
; /* put instructions into here */
6592 symbolS
*lit_sym
= NULL
;
6593 symbolS
*label_sym
= NULL
;
6595 istack_init (&istack
);
6597 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6598 Because the scheduling and bundling characteristics of movi and
6599 l32r or const16 are so different, we can do much better if we relax
6600 it prior to scheduling and bundling, rather than after. */
6601 if ((orig_insn
->opcode
== xtensa_movi_opcode
6602 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
6603 && !cur_vinsn
.inside_bundle
6604 && (orig_insn
->tok
[1].X_op
== O_symbol
6605 || orig_insn
->tok
[1].X_op
== O_pltrel
)
6606 && !orig_insn
->is_specific_opcode
&& use_transform ())
6607 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
6609 if (xg_expand_assembly_insn (&istack
, orig_insn
))
6612 for (i
= 0; i
< istack
.ninsn
; i
++)
6614 TInsn
*insn
= &istack
.insn
[i
];
6615 switch (insn
->insn_type
)
6618 assert (lit_sym
== NULL
);
6619 lit_sym
= xg_assemble_literal (insn
);
6623 static int relaxed_sym_idx
= 0;
6624 char *label
= xmalloc (strlen (FAKE_LABEL_NAME
) + 12);
6625 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
6627 assert (label_sym
== NULL
);
6628 label_sym
= symbol_find_or_make (label
);
6637 xg_resolve_literals (insn
, lit_sym
);
6639 xg_resolve_labels (insn
, label_sym
);
6641 bundle_tinsn (insn
, &v
);
6656 total_frag_text_expansion (fragS
*fragP
)
6659 int total_expansion
= 0;
6661 for (slot
= 0; slot
< MAX_SLOTS
; slot
++)
6662 total_expansion
+= fragP
->tc_frag_data
.text_expansion
[slot
];
6664 return total_expansion
;
6668 /* Emit a vliw instruction to the current fragment. */
6671 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
6673 bfd_boolean finish_frag
;
6674 bfd_boolean is_jump
= FALSE
;
6675 bfd_boolean is_branch
= FALSE
;
6676 xtensa_isa isa
= xtensa_default_isa
;
6682 unsigned current_line
, best_linenum
;
6685 best_linenum
= UINT_MAX
;
6687 if (generating_literals
)
6689 static int reported
= 0;
6691 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
6692 _("cannot assemble into a literal fragment"));
6699 if (frag_now_fix () != 0
6700 && (! frag_now
->tc_frag_data
.is_insn
6701 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6702 || !use_transform () != frag_now
->tc_frag_data
.is_no_transform
6703 || (directive_state
[directive_longcalls
]
6704 != frag_now
->tc_frag_data
.use_longcalls
)
6705 || (directive_state
[directive_absolute_literals
]
6706 != frag_now
->tc_frag_data
.use_absolute_literals
)))
6708 frag_wane (frag_now
);
6710 xtensa_set_frag_assembly_state (frag_now
);
6713 if (workaround_a0_b_retw
6714 && vinsn
->num_slots
== 1
6715 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
6716 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
6717 && use_transform ())
6719 has_a0_b_retw
= TRUE
;
6721 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
6722 After the first assembly pass we will check all of them and
6723 add a nop if needed. */
6724 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6725 frag_var (rs_machine_dependent
, 4, 4,
6726 RELAX_ADD_NOP_IF_A0_B_RETW
,
6727 frag_now
->fr_symbol
,
6728 frag_now
->fr_offset
,
6730 xtensa_set_frag_assembly_state (frag_now
);
6731 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6732 frag_var (rs_machine_dependent
, 4, 4,
6733 RELAX_ADD_NOP_IF_A0_B_RETW
,
6734 frag_now
->fr_symbol
,
6735 frag_now
->fr_offset
,
6737 xtensa_set_frag_assembly_state (frag_now
);
6740 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6742 /* See if the instruction implies an aligned section. */
6743 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[i
].opcode
) == 1)
6744 record_alignment (now_seg
, 2);
6746 /* Also determine the best line number for debug info. */
6747 best_linenum
= vinsn
->slots
[i
].linenum
< best_linenum
6748 ? vinsn
->slots
[i
].linenum
: best_linenum
;
6751 /* Special cases for instructions that force an alignment... */
6752 /* None of these opcodes are bundle-able. */
6753 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
6757 /* Remember the symbol that marks the end of the loop in the frag
6758 that marks the start of the loop. This way we can easily find
6759 the end of the loop at the beginning, without adding special code
6760 to mark the loop instructions themselves. */
6761 symbolS
*target_sym
= NULL
;
6762 if (vinsn
->slots
[0].tok
[1].X_op
== O_symbol
)
6763 target_sym
= vinsn
->slots
[0].tok
[1].X_add_symbol
;
6765 xtensa_set_frag_assembly_state (frag_now
);
6766 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6768 max_fill
= get_text_align_max_fill_size
6769 (get_text_align_power (xtensa_fetch_width
),
6770 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
6772 if (use_transform ())
6773 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
6774 RELAX_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
6776 frag_var (rs_machine_dependent
, 0, 0,
6777 RELAX_CHECK_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
6778 xtensa_set_frag_assembly_state (frag_now
);
6781 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
6782 && !vinsn
->slots
[0].is_specific_opcode
)
6784 xtensa_mark_literal_pool_location ();
6785 xtensa_move_labels (frag_now
, 0);
6786 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
6789 if (vinsn
->num_slots
== 1)
6791 if (workaround_a0_b_retw
&& use_transform ())
6792 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
6793 is_register_writer (&vinsn
->slots
[0], "a", 0));
6795 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
6796 is_bad_loopend_opcode (&vinsn
->slots
[0]));
6799 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
6801 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
6803 extra_space
= relaxation_requirements (vinsn
, &finish_frag
);
6805 /* vinsn_to_insnbuf will produce the error. */
6806 if (vinsn
->format
!= XTENSA_UNDEFINED
)
6808 f
= frag_more (insn_size
+ extra_space
);
6809 xtensa_set_frag_assembly_state (frag_now
);
6810 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6813 vinsn_to_insnbuf (vinsn
, f
, frag_now
, FALSE
);
6814 if (vinsn
->format
== XTENSA_UNDEFINED
)
6817 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, (unsigned char *) f
, 0);
6819 /* Temporarily set the logical line number to the one we want to appear
6820 in the debug information. */
6821 as_where (¤t_file
, ¤t_line
);
6822 new_logical_line (current_file
, best_linenum
);
6823 dwarf2_emit_insn (insn_size
+ extra_space
);
6824 new_logical_line (current_file
, current_line
);
6826 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6828 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6829 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
6830 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
6831 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
6832 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
6833 if (tinsn
->literal_space
!= 0)
6834 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
6836 if (tinsn
->subtype
== RELAX_NARROW
)
6837 assert (vinsn
->num_slots
== 1);
6838 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
6840 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
6843 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->offset
6844 || tinsn
->literal_frag
|| is_jump
|| is_branch
)
6848 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6849 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
6853 frag_variant (rs_machine_dependent
,
6854 extra_space
, extra_space
, RELAX_SLOTS
,
6855 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
6856 xtensa_set_frag_assembly_state (frag_now
);
6859 /* Special cases for loops:
6860 close_loop_end should be inserted AFTER short_loop.
6861 Make sure that CLOSE loops are processed BEFORE short_loops
6862 when converting them. */
6864 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
6865 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1
6866 && !vinsn
->slots
[0].is_specific_opcode
)
6868 if (workaround_short_loop
&& use_transform ())
6870 maybe_has_short_loop
= TRUE
;
6871 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6872 frag_var (rs_machine_dependent
, 4, 4,
6873 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6874 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6875 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6876 frag_var (rs_machine_dependent
, 4, 4,
6877 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6878 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6881 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
6882 loop at least 12 bytes away from another loop's end. */
6883 if (workaround_close_loop_end
&& use_transform ())
6885 maybe_has_close_loop_end
= TRUE
;
6886 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6887 frag_var (rs_machine_dependent
, 12, 12,
6888 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
6889 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6893 if (use_transform ())
6897 assert (finish_frag
);
6898 frag_var (rs_machine_dependent
,
6899 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6901 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6902 xtensa_set_frag_assembly_state (frag_now
);
6904 else if (is_branch
&& do_align_targets ())
6906 assert (finish_frag
);
6907 frag_var (rs_machine_dependent
,
6908 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6909 RELAX_MAYBE_UNREACHABLE
,
6910 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6911 xtensa_set_frag_assembly_state (frag_now
);
6912 frag_var (rs_machine_dependent
,
6914 RELAX_MAYBE_DESIRE_ALIGN
,
6915 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6916 xtensa_set_frag_assembly_state (frag_now
);
6920 /* Now, if the original opcode was a call... */
6921 if (do_align_targets ()
6922 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
6924 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
6925 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6926 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
6927 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6928 xtensa_set_frag_assembly_state (frag_now
);
6931 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6933 frag_wane (frag_now
);
6935 xtensa_set_frag_assembly_state (frag_now
);
6940 /* xtensa_end and helper functions. */
6942 static void xtensa_cleanup_align_frags (void);
6943 static void xtensa_fix_target_frags (void);
6944 static void xtensa_mark_narrow_branches (void);
6945 static void xtensa_mark_zcl_first_insns (void);
6946 static void xtensa_fix_a0_b_retw_frags (void);
6947 static void xtensa_fix_b_j_loop_end_frags (void);
6948 static void xtensa_fix_close_loop_end_frags (void);
6949 static void xtensa_fix_short_loop_frags (void);
6950 static void xtensa_sanity_check (void);
6951 static void xtensa_add_config_info (void);
6956 directive_balance ();
6957 xtensa_flush_pending_output ();
6959 past_xtensa_end
= TRUE
;
6961 xtensa_move_literals ();
6963 xtensa_reorder_segments ();
6964 xtensa_cleanup_align_frags ();
6965 xtensa_fix_target_frags ();
6966 if (workaround_a0_b_retw
&& has_a0_b_retw
)
6967 xtensa_fix_a0_b_retw_frags ();
6968 if (workaround_b_j_loop_end
)
6969 xtensa_fix_b_j_loop_end_frags ();
6971 /* "close_loop_end" should be processed BEFORE "short_loop". */
6972 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
6973 xtensa_fix_close_loop_end_frags ();
6975 if (workaround_short_loop
&& maybe_has_short_loop
)
6976 xtensa_fix_short_loop_frags ();
6978 xtensa_mark_narrow_branches ();
6979 xtensa_mark_zcl_first_insns ();
6981 xtensa_sanity_check ();
6983 xtensa_add_config_info ();
6988 xtensa_cleanup_align_frags (void)
6993 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
6994 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
6997 /* Walk over all of the fragments in a subsection. */
6998 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7000 if ((fragP
->fr_type
== rs_align
7001 || fragP
->fr_type
== rs_align_code
7002 || (fragP
->fr_type
== rs_machine_dependent
7003 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
7004 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
7005 && fragP
->fr_fix
== 0)
7007 fragS
*next
= fragP
->fr_next
;
7010 && next
->fr_fix
== 0
7011 && next
->fr_type
== rs_machine_dependent
7012 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7015 next
= next
->fr_next
;
7018 /* If we don't widen branch targets, then they
7019 will be easier to align. */
7020 if (fragP
->tc_frag_data
.is_branch_target
7021 && fragP
->fr_opcode
== fragP
->fr_literal
7022 && fragP
->fr_type
== rs_machine_dependent
7023 && fragP
->fr_subtype
== RELAX_SLOTS
7024 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
7026 if (fragP
->fr_type
== rs_machine_dependent
7027 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
7028 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
7034 /* Re-process all of the fragments looking to convert all of the
7035 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
7036 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7037 Otherwise, convert to a .fill 0. */
7040 xtensa_fix_target_frags (void)
7045 /* When this routine is called, all of the subsections are still intact
7046 so we walk over subsections instead of sections. */
7047 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7048 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7052 /* Walk over all of the fragments in a subsection. */
7053 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7055 if (fragP
->fr_type
== rs_machine_dependent
7056 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7058 if (next_frag_is_branch_target (fragP
))
7059 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7068 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
7071 xtensa_mark_narrow_branches (void)
7076 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7077 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7080 /* Walk over all of the fragments in a subsection. */
7081 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7083 if (fragP
->fr_type
== rs_machine_dependent
7084 && fragP
->fr_subtype
== RELAX_SLOTS
7085 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7089 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7090 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
7092 if (vinsn
.num_slots
== 1
7093 && xtensa_opcode_is_branch (xtensa_default_isa
,
7094 vinsn
.slots
[0].opcode
) == 1
7095 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
7096 && is_narrow_branch_guaranteed_in_range (fragP
,
7099 fragP
->fr_subtype
= RELAX_SLOTS
;
7100 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
7101 fragP
->tc_frag_data
.is_aligning_branch
= 1;
7109 /* A branch is typically widened only when its target is out of
7110 range. However, we would like to widen them to align a subsequent
7111 branch target when possible.
7113 Because the branch relaxation code is so convoluted, the optimal solution
7114 (combining the two cases) is difficult to get right in all circumstances.
7115 We therefore go with an "almost as good" solution, where we only
7116 use for alignment narrow branches that definitely will not expand to a
7117 jump and a branch. These functions find and mark these cases. */
7119 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
7120 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7121 We start counting beginning with the frag after the 2-byte branch, so the
7122 maximum offset is (4 - 2) + 63 = 65. */
7123 #define MAX_IMMED6 65
7125 static offsetT
unrelaxed_frag_max_size (fragS
*);
7128 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
7130 const expressionS
*expr
= &tinsn
->tok
[1];
7131 symbolS
*symbolP
= expr
->X_add_symbol
;
7132 offsetT max_distance
= expr
->X_add_number
;
7135 if (expr
->X_op
!= O_symbol
)
7138 target_frag
= symbol_get_frag (symbolP
);
7140 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
7141 if (is_branch_jmp_to_next (tinsn
, fragP
))
7144 /* The branch doesn't branch over it's own frag,
7145 but over the subsequent ones. */
7146 fragP
= fragP
->fr_next
;
7147 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
7149 max_distance
+= unrelaxed_frag_max_size (fragP
);
7150 fragP
= fragP
->fr_next
;
7152 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
7159 xtensa_mark_zcl_first_insns (void)
7164 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7165 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7168 /* Walk over all of the fragments in a subsection. */
7169 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7171 if (fragP
->fr_type
== rs_machine_dependent
7172 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7173 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7175 /* Find the loop frag. */
7176 fragS
*targ_frag
= next_non_empty_frag (fragP
);
7177 /* Find the first insn frag. */
7178 targ_frag
= next_non_empty_frag (targ_frag
);
7180 /* Of course, sometimes (mostly for toy test cases) a
7181 zero-cost loop instruction is the last in a section. */
7184 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
7185 /* Do not widen a frag that is the first instruction of a
7186 zero-cost loop. It makes that loop harder to align. */
7187 if (targ_frag
->fr_type
== rs_machine_dependent
7188 && targ_frag
->fr_subtype
== RELAX_SLOTS
7189 && (targ_frag
->tc_frag_data
.slot_subtypes
[0]
7192 if (targ_frag
->tc_frag_data
.is_aligning_branch
)
7193 targ_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
7196 frag_wane (targ_frag
);
7197 targ_frag
->tc_frag_data
.slot_subtypes
[0] = 0;
7201 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
7209 /* Re-process all of the fragments looking to convert all of the
7210 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7211 conditional branch or a retw/retw.n, convert this frag to one that
7212 will generate a NOP. In any case close it off with a .fill 0. */
7214 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
7217 xtensa_fix_a0_b_retw_frags (void)
7222 /* When this routine is called, all of the subsections are still intact
7223 so we walk over subsections instead of sections. */
7224 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7225 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7229 /* Walk over all of the fragments in a subsection. */
7230 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7232 if (fragP
->fr_type
== rs_machine_dependent
7233 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
7235 if (next_instrs_are_b_retw (fragP
))
7237 if (fragP
->tc_frag_data
.is_no_transform
)
7238 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7240 relax_frag_add_nop (fragP
);
7250 next_instrs_are_b_retw (fragS
*fragP
)
7252 xtensa_opcode opcode
;
7254 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
7255 static xtensa_insnbuf insnbuf
= NULL
;
7256 static xtensa_insnbuf slotbuf
= NULL
;
7257 xtensa_isa isa
= xtensa_default_isa
;
7260 bfd_boolean branch_seen
= FALSE
;
7264 insnbuf
= xtensa_insnbuf_alloc (isa
);
7265 slotbuf
= xtensa_insnbuf_alloc (isa
);
7268 if (next_fragP
== NULL
)
7271 /* Check for the conditional branch. */
7272 xtensa_insnbuf_from_chars
7273 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7274 fmt
= xtensa_format_decode (isa
, insnbuf
);
7275 if (fmt
== XTENSA_UNDEFINED
)
7278 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7280 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
7281 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
7283 branch_seen
= (branch_seen
7284 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
7290 offset
+= xtensa_format_length (isa
, fmt
);
7291 if (offset
== next_fragP
->fr_fix
)
7293 next_fragP
= next_non_empty_frag (next_fragP
);
7297 if (next_fragP
== NULL
)
7300 /* Check for the retw/retw.n. */
7301 xtensa_insnbuf_from_chars
7302 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7303 fmt
= xtensa_format_decode (isa
, insnbuf
);
7305 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
7306 have no problems. */
7307 if (fmt
== XTENSA_UNDEFINED
7308 || xtensa_format_num_slots (isa
, fmt
) != 1)
7311 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
7312 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
7314 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
7321 /* Re-process all of the fragments looking to convert all of the
7322 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
7323 loop end label, convert this frag to one that will generate a NOP.
7324 In any case close it off with a .fill 0. */
7326 static bfd_boolean
next_instr_is_loop_end (fragS
*);
7329 xtensa_fix_b_j_loop_end_frags (void)
7334 /* When this routine is called, all of the subsections are still intact
7335 so we walk over subsections instead of sections. */
7336 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7337 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7341 /* Walk over all of the fragments in a subsection. */
7342 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7344 if (fragP
->fr_type
== rs_machine_dependent
7345 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
7347 if (next_instr_is_loop_end (fragP
))
7349 if (fragP
->tc_frag_data
.is_no_transform
)
7350 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
7352 relax_frag_add_nop (fragP
);
7362 next_instr_is_loop_end (fragS
*fragP
)
7364 const fragS
*next_fragP
;
7366 if (next_frag_is_loop_target (fragP
))
7369 next_fragP
= next_non_empty_frag (fragP
);
7370 if (next_fragP
== NULL
)
7373 if (!next_frag_is_loop_target (next_fragP
))
7376 /* If the size is >= 3 then there is more than one instruction here.
7377 The hardware bug will not fire. */
7378 if (next_fragP
->fr_fix
> 3)
7385 /* Re-process all of the fragments looking to convert all of the
7386 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
7387 not MY loop's loop end within 12 bytes, add enough nops here to
7388 make it at least 12 bytes away. In any case close it off with a
7391 static offsetT min_bytes_to_other_loop_end
7392 (fragS
*, fragS
*, offsetT
);
7395 xtensa_fix_close_loop_end_frags (void)
7400 /* When this routine is called, all of the subsections are still intact
7401 so we walk over subsections instead of sections. */
7402 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7403 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7407 fragS
*current_target
= NULL
;
7409 /* Walk over all of the fragments in a subsection. */
7410 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7412 if (fragP
->fr_type
== rs_machine_dependent
7413 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7414 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7415 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7418 && fragP
->fr_type
== rs_machine_dependent
7419 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
7422 int bytes_added
= 0;
7424 #define REQUIRED_LOOP_DIVIDING_BYTES 12
7425 /* Max out at 12. */
7426 min_bytes
= min_bytes_to_other_loop_end
7427 (fragP
->fr_next
, current_target
, REQUIRED_LOOP_DIVIDING_BYTES
);
7429 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
7431 if (fragP
->tc_frag_data
.is_no_transform
)
7432 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
7435 while (min_bytes
+ bytes_added
7436 < REQUIRED_LOOP_DIVIDING_BYTES
)
7440 if (fragP
->fr_var
< length
)
7441 as_fatal (_("fr_var %lu < length %d"),
7442 (long) fragP
->fr_var
, length
);
7445 assemble_nop (length
,
7446 fragP
->fr_literal
+ fragP
->fr_fix
);
7447 fragP
->fr_fix
+= length
;
7448 fragP
->fr_var
-= length
;
7450 bytes_added
+= length
;
7456 assert (fragP
->fr_type
!= rs_machine_dependent
7457 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
7463 static offsetT
unrelaxed_frag_min_size (fragS
*);
7466 min_bytes_to_other_loop_end (fragS
*fragP
,
7467 fragS
*current_target
,
7471 fragS
*current_fragP
;
7473 for (current_fragP
= fragP
;
7475 current_fragP
= current_fragP
->fr_next
)
7477 if (current_fragP
->tc_frag_data
.is_loop_target
7478 && current_fragP
!= current_target
)
7481 offset
+= unrelaxed_frag_min_size (current_fragP
);
7483 if (offset
>= max_size
)
7491 unrelaxed_frag_min_size (fragS
*fragP
)
7493 offsetT size
= fragP
->fr_fix
;
7495 /* Add fill size. */
7496 if (fragP
->fr_type
== rs_fill
)
7497 size
+= fragP
->fr_offset
;
7504 unrelaxed_frag_max_size (fragS
*fragP
)
7506 offsetT size
= fragP
->fr_fix
;
7507 switch (fragP
->fr_type
)
7510 /* Empty frags created by the obstack allocation scheme
7511 end up with type 0. */
7516 size
+= fragP
->fr_offset
;
7524 /* No further adjustments needed. */
7526 case rs_machine_dependent
:
7527 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
7528 size
+= fragP
->fr_var
;
7531 /* We had darn well better know how big it is. */
7540 /* Re-process all of the fragments looking to convert all
7541 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
7544 1) the instruction size count to the loop end label
7545 is too short (<= 2 instructions),
7546 2) loop has a jump or branch in it
7549 1) workaround_all_short_loops is TRUE
7550 2) The generating loop was a 'loopgtz' or 'loopnez'
7551 3) the instruction size count to the loop end label is too short
7553 then convert this frag (and maybe the next one) to generate a NOP.
7554 In any case close it off with a .fill 0. */
7556 static int count_insns_to_loop_end (fragS
*, bfd_boolean
, int);
7557 static bfd_boolean
branch_before_loop_end (fragS
*);
7560 xtensa_fix_short_loop_frags (void)
7565 /* When this routine is called, all of the subsections are still intact
7566 so we walk over subsections instead of sections. */
7567 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7568 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7571 fragS
*current_target
= NULL
;
7572 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
7574 /* Walk over all of the fragments in a subsection. */
7575 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7577 if (fragP
->fr_type
== rs_machine_dependent
7578 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7579 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7582 fragS
*loop_frag
= next_non_empty_frag (fragP
);
7583 tinsn_from_chars (&t_insn
, loop_frag
->fr_opcode
, 0);
7584 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7585 current_opcode
= t_insn
.opcode
;
7586 assert (xtensa_opcode_is_loop (xtensa_default_isa
,
7587 current_opcode
) == 1);
7590 if (fragP
->fr_type
== rs_machine_dependent
7591 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7593 if (count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3) < 3
7594 && (branch_before_loop_end (fragP
->fr_next
)
7595 || (workaround_all_short_loops
7596 && current_opcode
!= XTENSA_UNDEFINED
7597 && current_opcode
!= xtensa_loop_opcode
)))
7599 if (fragP
->tc_frag_data
.is_no_transform
)
7600 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
7602 relax_frag_add_nop (fragP
);
7611 static int unrelaxed_frag_min_insn_count (fragS
*);
7614 count_insns_to_loop_end (fragS
*base_fragP
,
7615 bfd_boolean count_relax_add
,
7618 fragS
*fragP
= NULL
;
7623 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
7625 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
7626 if (insn_count
>= max_count
)
7629 if (count_relax_add
)
7631 if (fragP
->fr_type
== rs_machine_dependent
7632 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7634 /* In order to add the appropriate number of
7635 NOPs, we count an instruction for downstream
7638 if (insn_count
>= max_count
)
7648 unrelaxed_frag_min_insn_count (fragS
*fragP
)
7650 xtensa_isa isa
= xtensa_default_isa
;
7651 static xtensa_insnbuf insnbuf
= NULL
;
7655 if (!fragP
->tc_frag_data
.is_insn
)
7659 insnbuf
= xtensa_insnbuf_alloc (isa
);
7661 /* Decode the fixed instructions. */
7662 while (offset
< fragP
->fr_fix
)
7666 xtensa_insnbuf_from_chars
7667 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7668 fmt
= xtensa_format_decode (isa
, insnbuf
);
7670 if (fmt
== XTENSA_UNDEFINED
)
7672 as_fatal (_("undecodable instruction in instruction frag"));
7675 offset
+= xtensa_format_length (isa
, fmt
);
7683 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
7686 branch_before_loop_end (fragS
*base_fragP
)
7690 for (fragP
= base_fragP
;
7691 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
7692 fragP
= fragP
->fr_next
)
7694 if (unrelaxed_frag_has_b_j (fragP
))
7702 unrelaxed_frag_has_b_j (fragS
*fragP
)
7704 static xtensa_insnbuf insnbuf
= NULL
;
7705 xtensa_isa isa
= xtensa_default_isa
;
7708 if (!fragP
->tc_frag_data
.is_insn
)
7712 insnbuf
= xtensa_insnbuf_alloc (isa
);
7714 /* Decode the fixed instructions. */
7715 while (offset
< fragP
->fr_fix
)
7720 xtensa_insnbuf_from_chars
7721 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7722 fmt
= xtensa_format_decode (isa
, insnbuf
);
7723 if (fmt
== XTENSA_UNDEFINED
)
7726 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7728 xtensa_opcode opcode
=
7729 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
7730 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
7731 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
7734 offset
+= xtensa_format_length (isa
, fmt
);
7740 /* Checks to be made after initial assembly but before relaxation. */
7742 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
7743 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
7746 xtensa_sanity_check (void)
7753 as_where (&file_name
, &line
);
7754 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7755 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7759 /* Walk over all of the fragments in a subsection. */
7760 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7762 if (fragP
->fr_type
== rs_machine_dependent
7763 && fragP
->fr_subtype
== RELAX_SLOTS
7764 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7766 static xtensa_insnbuf insnbuf
= NULL
;
7769 if (fragP
->fr_opcode
!= NULL
)
7772 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7773 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7774 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
7776 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7777 t_insn
.opcode
) == 1)
7779 if (is_empty_loop (&t_insn
, fragP
))
7781 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7782 as_bad (_("invalid empty loop"));
7784 if (!is_local_forward_loop (&t_insn
, fragP
))
7786 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7787 as_bad (_("loop target does not follow "
7788 "loop instruction in section"));
7795 new_logical_line (file_name
, line
);
7799 #define LOOP_IMMED_OPN 1
7801 /* Return TRUE if the loop target is the next non-zero fragment. */
7804 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
7806 const expressionS
*expr
;
7810 if (insn
->insn_type
!= ITYPE_INSN
)
7813 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
7816 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7819 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7821 if (expr
->X_op
!= O_symbol
)
7824 symbolP
= expr
->X_add_symbol
;
7828 if (symbol_get_frag (symbolP
) == NULL
)
7831 if (S_GET_VALUE (symbolP
) != 0)
7834 /* Walk through the zero-size fragments from this one. If we find
7835 the target fragment, then this is a zero-size loop. */
7837 for (next_fragP
= fragP
->fr_next
;
7839 next_fragP
= next_fragP
->fr_next
)
7841 if (next_fragP
== symbol_get_frag (symbolP
))
7843 if (next_fragP
->fr_fix
!= 0)
7851 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
7853 const expressionS
*expr
;
7857 if (insn
->insn_type
!= ITYPE_INSN
)
7860 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
7863 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7866 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7868 if (expr
->X_op
!= O_symbol
)
7871 symbolP
= expr
->X_add_symbol
;
7875 if (symbol_get_frag (symbolP
) == NULL
)
7878 /* Walk through fragments until we find the target.
7879 If we do not find the target, then this is an invalid loop. */
7881 for (next_fragP
= fragP
->fr_next
;
7883 next_fragP
= next_fragP
->fr_next
)
7885 if (next_fragP
== symbol_get_frag (symbolP
))
7893 #define XTINFO_NAME "Xtensa_Info"
7894 #define XTINFO_NAMESZ 12
7895 #define XTINFO_TYPE 1
7898 xtensa_add_config_info (void)
7904 info_sec
= subseg_new (".xtensa.info", 0);
7905 bfd_set_section_flags (stdoutput
, info_sec
, SEC_HAS_CONTENTS
| SEC_READONLY
);
7907 data
= xmalloc (100);
7908 sprintf (data
, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n",
7909 XSHAL_USE_ABSOLUTE_LITERALS
, XSHAL_ABI
);
7910 sz
= strlen (data
) + 1;
7912 /* Add enough null terminators to pad to a word boundary. */
7915 while ((sz
& 3) != 0);
7917 /* Follow the standard note section layout:
7918 First write the length of the name string. */
7920 md_number_to_chars (p
, (valueT
) XTINFO_NAMESZ
, 4);
7922 /* Next comes the length of the "descriptor", i.e., the actual data. */
7924 md_number_to_chars (p
, (valueT
) sz
, 4);
7926 /* Write the note type. */
7928 md_number_to_chars (p
, (valueT
) XTINFO_TYPE
, 4);
7930 /* Write the name field. */
7931 p
= frag_more (XTINFO_NAMESZ
);
7932 memcpy (p
, XTINFO_NAME
, XTINFO_NAMESZ
);
7934 /* Finally, write the descriptor. */
7936 memcpy (p
, data
, sz
);
7942 /* Alignment Functions. */
7945 get_text_align_power (unsigned target_size
)
7947 if (target_size
<= 4)
7949 assert (target_size
== 8);
7955 get_text_align_max_fill_size (int align_pow
,
7956 bfd_boolean use_nops
,
7957 bfd_boolean use_no_density
)
7960 return (1 << align_pow
);
7962 return 3 * (1 << align_pow
);
7964 return 1 + (1 << align_pow
);
7968 /* Calculate the minimum bytes of fill needed at "address" to align a
7969 target instruction of size "target_size" so that it does not cross a
7970 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE,
7971 the fill can be an arbitrary number of bytes. Otherwise, the space must
7972 be filled by NOP instructions. */
7975 get_text_align_fill_size (addressT address
,
7978 bfd_boolean use_nops
,
7979 bfd_boolean use_no_density
)
7981 addressT alignment
, fill
, fill_limit
, fill_step
;
7982 bfd_boolean skip_one
= FALSE
;
7984 alignment
= (1 << align_pow
);
7985 assert (target_size
> 0 && alignment
>= (addressT
) target_size
);
7989 fill_limit
= alignment
;
7992 else if (!use_no_density
)
7994 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */
7995 fill_limit
= alignment
* 2;
8001 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */
8002 fill_limit
= alignment
* 3;
8006 /* Try all fill sizes until finding one that works. */
8007 for (fill
= 0; fill
< fill_limit
; fill
+= fill_step
)
8009 if (skip_one
&& fill
== 1)
8011 if ((address
+ fill
) >> align_pow
8012 == (address
+ fill
+ target_size
- 1) >> align_pow
)
8021 branch_align_power (segT sec
)
8023 /* If the Xtensa processor has a fetch width of 8 bytes, and the section
8024 is aligned to at least an 8-byte boundary, then a branch target need
8025 only fit within an 8-byte aligned block of memory to avoid a stall.
8026 Otherwise, try to fit branch targets within 4-byte aligned blocks
8027 (which may be insufficient, e.g., if the section has no alignment, but
8028 it's good enough). */
8029 if (xtensa_fetch_width
== 8)
8031 if (get_recorded_alignment (sec
) >= 3)
8035 assert (xtensa_fetch_width
== 4);
8041 /* This will assert if it is not possible. */
8044 get_text_align_nop_count (offsetT fill_size
, bfd_boolean use_no_density
)
8050 assert (fill_size
% 3 == 0);
8051 return (fill_size
/ 3);
8054 assert (fill_size
!= 1); /* Bad argument. */
8056 while (fill_size
> 1)
8059 if (fill_size
== 2 || fill_size
== 4)
8061 fill_size
-= insn_size
;
8064 assert (fill_size
!= 1); /* Bad algorithm. */
8070 get_text_align_nth_nop_size (offsetT fill_size
,
8072 bfd_boolean use_no_density
)
8079 assert (fill_size
!= 1); /* Bad argument. */
8081 while (fill_size
> 1)
8084 if (fill_size
== 2 || fill_size
== 4)
8086 fill_size
-= insn_size
;
8096 /* For the given fragment, find the appropriate address
8097 for it to begin at if we are using NOPs to align it. */
8100 get_noop_aligned_address (fragS
*fragP
, addressT address
)
8102 /* The rule is: get next fragment's FIRST instruction. Find
8103 the smallest number of bytes that need to be added to
8104 ensure that the next fragment's FIRST instruction will fit
8107 E.G., 2 bytes : 0, 1, 2 mod 4
8110 If the FIRST instruction MIGHT be relaxed,
8111 assume that it will become a 3-byte instruction.
8113 Note again here that LOOP instructions are not bundleable,
8114 and this relaxation only applies to LOOP opcodes. */
8117 int first_insn_size
;
8119 addressT pre_opcode_bytes
;
8122 xtensa_opcode opcode
;
8123 bfd_boolean is_loop
;
8125 assert (fragP
->fr_type
== rs_machine_dependent
);
8126 assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
8128 /* Find the loop frag. */
8129 first_insn
= next_non_empty_frag (fragP
);
8130 /* Now find the first insn frag. */
8131 first_insn
= next_non_empty_frag (first_insn
);
8133 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
8135 loop_insn_size
= xg_get_single_size (opcode
);
8137 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
8138 pre_opcode_bytes
+= loop_insn_size
;
8140 /* For loops, the alignment depends on the size of the
8141 instruction following the loop, not the LOOP instruction. */
8143 if (first_insn
== NULL
)
8144 first_insn_size
= xtensa_fetch_width
;
8146 first_insn_size
= get_loop_align_size (frag_format_size (first_insn
));
8148 /* If it was 8, then we'll need a larger alignment for the section. */
8149 align_power
= get_text_align_power (first_insn_size
);
8150 record_alignment (now_seg
, align_power
);
8152 fill_size
= get_text_align_fill_size
8153 (address
+ pre_opcode_bytes
, align_power
, first_insn_size
, TRUE
,
8154 fragP
->tc_frag_data
.is_no_density
);
8156 return address
+ fill_size
;
8160 /* 3 mechanisms for relaxing an alignment:
8162 Align to a power of 2.
8163 Align so the next fragment's instruction does not cross a word boundary.
8164 Align the current instruction so that if the next instruction
8165 were 3 bytes, it would not cross a word boundary.
8169 zeros - This is easy; always insert zeros.
8170 nops - 3-byte and 2-byte instructions
8174 >=5 : 3-byte instruction + fn (n-3)
8175 widening - widen previous instructions. */
8178 get_aligned_diff (fragS
*fragP
, addressT address
, offsetT
*max_diff
)
8180 addressT target_address
, loop_insn_offset
;
8182 xtensa_opcode loop_opcode
;
8183 bfd_boolean is_loop
;
8186 offsetT branch_align
;
8188 assert (fragP
->fr_type
== rs_machine_dependent
);
8189 switch (fragP
->fr_subtype
)
8191 case RELAX_DESIRE_ALIGN
:
8192 target_size
= next_frag_format_size (fragP
);
8193 if (target_size
== XTENSA_UNDEFINED
)
8195 align_power
= branch_align_power (now_seg
);
8196 branch_align
= 1 << align_power
;
8197 /* Don't count on the section alignment being as large as the target. */
8198 if (target_size
> branch_align
)
8199 target_size
= branch_align
;
8200 opt_diff
= get_text_align_fill_size (address
, align_power
,
8201 target_size
, FALSE
, FALSE
);
8203 *max_diff
= (opt_diff
+ branch_align
8204 - (target_size
+ ((address
+ opt_diff
) % branch_align
)));
8205 assert (*max_diff
>= opt_diff
);
8208 case RELAX_ALIGN_NEXT_OPCODE
:
8209 target_size
= get_loop_align_size (next_frag_format_size (fragP
));
8210 loop_insn_offset
= 0;
8211 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
8214 /* If the loop has been expanded then the LOOP instruction
8215 could be at an offset from this fragment. */
8216 if (next_non_empty_frag(fragP
)->tc_frag_data
.slot_subtypes
[0]
8218 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
8220 /* In an ideal world, which is what we are shooting for here,
8221 we wouldn't need to use any NOPs immediately prior to the
8222 LOOP instruction. If this approach fails, relax_frag_loop_align
8223 will call get_noop_aligned_address. */
8225 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
8226 align_power
= get_text_align_power (target_size
),
8227 opt_diff
= get_text_align_fill_size (target_address
, align_power
,
8228 target_size
, FALSE
, FALSE
);
8230 *max_diff
= xtensa_fetch_width
8231 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
8232 - target_size
+ opt_diff
;
8233 assert (*max_diff
>= opt_diff
);
8244 /* md_relax_frag Hook and Helper Functions. */
8246 static long relax_frag_loop_align (fragS
*, long);
8247 static long relax_frag_for_align (fragS
*, long);
8248 static long relax_frag_immed
8249 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
8252 /* Return the number of bytes added to this fragment, given that the
8253 input has been stretched already by "stretch". */
8256 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
8258 xtensa_isa isa
= xtensa_default_isa
;
8259 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
8260 long new_stretch
= 0;
8264 static xtensa_insnbuf vbuf
= NULL
;
8265 int slot
, num_slots
;
8268 as_where (&file_name
, &line
);
8269 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8271 fragP
->tc_frag_data
.unreported_expansion
= 0;
8273 switch (fragP
->fr_subtype
)
8275 case RELAX_ALIGN_NEXT_OPCODE
:
8276 /* Always convert. */
8277 if (fragP
->tc_frag_data
.relax_seen
)
8278 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
8281 case RELAX_LOOP_END
:
8285 case RELAX_LOOP_END_ADD_NOP
:
8286 /* Add a NOP and switch to .fill 0. */
8287 new_stretch
= relax_frag_add_nop (fragP
);
8291 case RELAX_DESIRE_ALIGN
:
8292 /* Do nothing. The narrowing before this frag will either align
8297 case RELAX_LITERAL_FINAL
:
8300 case RELAX_LITERAL_NR
:
8302 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
8303 assert (unreported
== lit_size
);
8304 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
8305 fragP
->fr_var
-= lit_size
;
8306 fragP
->fr_fix
+= lit_size
;
8312 vbuf
= xtensa_insnbuf_alloc (isa
);
8314 xtensa_insnbuf_from_chars
8315 (isa
, vbuf
, (unsigned char *) fragP
->fr_opcode
, 0);
8316 fmt
= xtensa_format_decode (isa
, vbuf
);
8317 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8319 for (slot
= 0; slot
< num_slots
; slot
++)
8321 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
8324 if (fragP
->tc_frag_data
.relax_seen
)
8325 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8329 case RELAX_IMMED_STEP1
:
8330 case RELAX_IMMED_STEP2
:
8331 case RELAX_IMMED_STEP3
:
8332 /* Place the immediate. */
8333 new_stretch
+= relax_frag_immed
8334 (now_seg
, fragP
, stretch
,
8335 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8336 fmt
, slot
, stretched_p
, FALSE
);
8340 /* This is OK; see the note in xg_assemble_vliw_tokens. */
8346 case RELAX_LITERAL_POOL_BEGIN
:
8347 case RELAX_LITERAL_POOL_END
:
8348 case RELAX_MAYBE_UNREACHABLE
:
8349 case RELAX_MAYBE_DESIRE_ALIGN
:
8350 /* No relaxation required. */
8353 case RELAX_FILL_NOP
:
8354 case RELAX_UNREACHABLE
:
8355 if (fragP
->tc_frag_data
.relax_seen
)
8356 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8360 as_bad (_("bad relaxation state"));
8363 /* Tell gas we need another relaxation pass. */
8364 if (! fragP
->tc_frag_data
.relax_seen
)
8366 fragP
->tc_frag_data
.relax_seen
= TRUE
;
8370 new_logical_line (file_name
, line
);
8376 relax_frag_loop_align (fragS
*fragP
, long stretch
)
8378 addressT old_address
, old_next_address
, old_size
;
8379 addressT new_address
, new_next_address
, new_size
;
8382 /* All the frags with relax_frag_for_alignment prior to this one in the
8383 section have been done, hopefully eliminating the need for a NOP here.
8384 But, this will put it in if necessary. */
8386 /* Calculate the old address of this fragment and the next fragment. */
8387 old_address
= fragP
->fr_address
- stretch
;
8388 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
8389 fragP
->tc_frag_data
.text_expansion
[0]);
8390 old_size
= old_next_address
- old_address
;
8392 /* Calculate the new address of this fragment and the next fragment. */
8393 new_address
= fragP
->fr_address
;
8395 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
8396 new_size
= new_next_address
- new_address
;
8398 growth
= new_size
- old_size
;
8400 /* Fix up the text_expansion field and return the new growth. */
8401 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
8406 /* Add a NOP instruction. */
8409 relax_frag_add_nop (fragS
*fragP
)
8411 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
8412 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
8413 assemble_nop (length
, nop_buf
);
8414 fragP
->tc_frag_data
.is_insn
= TRUE
;
8416 if (fragP
->fr_var
< length
)
8418 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP
->fr_var
, length
);
8422 fragP
->fr_fix
+= length
;
8423 fragP
->fr_var
-= length
;
8428 static long future_alignment_required (fragS
*, long);
8431 relax_frag_for_align (fragS
*fragP
, long stretch
)
8433 /* Overview of the relaxation procedure for alignment:
8434 We can widen with NOPs or by widening instructions or by filling
8435 bytes after jump instructions. Find the opportune places and widen
8436 them if necessary. */
8441 assert (fragP
->fr_subtype
== RELAX_FILL_NOP
8442 || fragP
->fr_subtype
== RELAX_UNREACHABLE
8443 || (fragP
->fr_subtype
== RELAX_SLOTS
8444 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
8446 stretch_me
= future_alignment_required (fragP
, stretch
);
8447 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
8453 /* We expanded on a previous pass. Can we shrink now? */
8454 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
8455 if (shrink
<= stretch
&& stretch
> 0)
8457 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8463 /* Below here, diff > 0. */
8464 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8470 /* Return the address of the next frag that should be aligned.
8472 By "address" we mean the address it _would_ be at if there
8473 is no action taken to align it between here and the target frag.
8474 In other words, if no narrows and no fill nops are used between
8475 here and the frag to align, _even_if_ some of the frags we use
8476 to align targets have already expanded on a previous relaxation
8479 Also, count each frag that may be used to help align the target.
8481 Return 0 if there are no frags left in the chain that need to be
8485 find_address_of_next_align_frag (fragS
**fragPP
,
8489 bfd_boolean
*paddable
)
8491 fragS
*fragP
= *fragPP
;
8492 addressT address
= fragP
->fr_address
;
8494 /* Do not reset the counts to 0. */
8498 /* Limit this to a small search. */
8499 if (*widens
>= (int) xtensa_fetch_width
)
8504 address
+= fragP
->fr_fix
;
8506 if (fragP
->fr_type
== rs_fill
)
8507 address
+= fragP
->fr_offset
* fragP
->fr_var
;
8508 else if (fragP
->fr_type
== rs_machine_dependent
)
8510 switch (fragP
->fr_subtype
)
8512 case RELAX_UNREACHABLE
:
8516 case RELAX_FILL_NOP
:
8518 if (!fragP
->tc_frag_data
.is_no_density
)
8523 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8528 address
+= total_frag_text_expansion (fragP
);;
8532 address
+= fragP
->tc_frag_data
.text_expansion
[0];
8535 case RELAX_ALIGN_NEXT_OPCODE
:
8536 case RELAX_DESIRE_ALIGN
:
8540 case RELAX_MAYBE_UNREACHABLE
:
8541 case RELAX_MAYBE_DESIRE_ALIGN
:
8546 /* Just punt if we don't know the type. */
8553 /* Just punt if we don't know the type. */
8557 fragP
= fragP
->fr_next
;
8565 static long bytes_to_stretch (fragS
*, int, int, int, int);
8568 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
8570 fragS
*this_frag
= fragP
;
8574 int narrow_nops
= 0;
8575 bfd_boolean paddable
= FALSE
;
8576 offsetT local_opt_diff
;
8579 int stretch_amount
= 0;
8580 int local_stretch_amount
;
8581 int global_stretch_amount
;
8583 address
= find_address_of_next_align_frag
8584 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
8588 if (this_frag
->tc_frag_data
.is_aligning_branch
)
8589 this_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
8591 frag_wane (this_frag
);
8595 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
8596 opt_diff
= local_opt_diff
;
8597 assert (opt_diff
>= 0);
8598 assert (max_diff
>= opt_diff
);
8603 fragP
= fragP
->fr_next
;
8605 while (fragP
&& opt_diff
< max_diff
&& address
)
8607 /* We only use these to determine if we can exit early
8608 because there will be plenty of ways to align future
8610 int glob_widens
= 0;
8613 bfd_boolean glob_pad
= 0;
8614 address
= find_address_of_next_align_frag
8615 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
8616 /* If there is a padable portion, then skip. */
8617 if (glob_pad
|| glob_widens
>= (1 << branch_align_power (now_seg
)))
8622 offsetT next_m_diff
;
8623 offsetT next_o_diff
;
8625 /* Downrange frags haven't had stretch added to them yet. */
8628 /* The address also includes any text expansion from this
8629 frag in a previous pass, but we don't want that. */
8630 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
8632 /* Assume we are going to move at least opt_diff. In
8633 reality, we might not be able to, but assuming that
8634 we will helps catch cases where moving opt_diff pushes
8635 the next target from aligned to unaligned. */
8636 address
+= opt_diff
;
8638 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
8640 /* Now cleanup for the adjustments to address. */
8641 next_o_diff
+= opt_diff
;
8642 next_m_diff
+= opt_diff
;
8643 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
8644 opt_diff
= next_o_diff
;
8645 if (next_m_diff
< max_diff
)
8646 max_diff
= next_m_diff
;
8647 fragP
= fragP
->fr_next
;
8651 /* If there are enough wideners in between, do it. */
8654 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
8656 assert (opt_diff
<= UNREACHABLE_MAX_WIDTH
);
8661 local_stretch_amount
8662 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8663 num_widens
, local_opt_diff
);
8664 global_stretch_amount
8665 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8666 num_widens
, opt_diff
);
8667 /* If the condition below is true, then the frag couldn't
8668 stretch the correct amount for the global case, so we just
8669 optimize locally. We'll rely on the subsequent frags to get
8670 the correct alignment in the global case. */
8671 if (global_stretch_amount
< local_stretch_amount
)
8672 stretch_amount
= local_stretch_amount
;
8674 stretch_amount
= global_stretch_amount
;
8676 if (this_frag
->fr_subtype
== RELAX_SLOTS
8677 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8678 assert (stretch_amount
<= 1);
8679 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8681 if (this_frag
->tc_frag_data
.is_no_density
)
8682 assert (stretch_amount
== 3 || stretch_amount
== 0);
8684 assert (stretch_amount
<= 3);
8687 return stretch_amount
;
8691 /* The idea: widen everything you can to get a target or loop aligned,
8692 then start using NOPs.
8694 When we must have a NOP, here is a table of how we decide
8695 (so you don't have to fight through the control flow below):
8697 wide_nops = the number of wide NOPs available for aligning
8698 narrow_nops = the number of narrow NOPs available for aligning
8699 (a subset of wide_nops)
8700 widens = the number of narrow instructions that should be widened
8707 b 0 1 1 (case 3a makes this case unnecessary)
8710 c 0 1 2 (case 4a makes this case unnecessary)
8713 c 0 2 1 (case 5b makes this case unnecessary)
8716 c 0 1 4 (case 6b makes this case unnecessary)
8717 d 1 1 1 (case 6a makes this case unnecessary)
8718 e 0 2 2 (case 6a makes this case unnecessary)
8719 f 0 3 0 (case 6a makes this case unnecessary)
8722 c 1 1 2 (case 7b makes this case unnecessary)
8723 d 0 1 5 (case 7a makes this case unnecessary)
8724 e 0 2 3 (case 7b makes this case unnecessary)
8725 f 0 3 1 (case 7b makes this case unnecessary)
8726 g 1 2 1 (case 7b makes this case unnecessary)
8730 bytes_to_stretch (fragS
*this_frag
,
8736 int bytes_short
= desired_diff
- num_widens
;
8738 assert (desired_diff
>= 0 && desired_diff
< 8);
8739 if (desired_diff
== 0)
8742 assert (wide_nops
> 0 || num_widens
> 0);
8744 /* Always prefer widening to NOP-filling. */
8745 if (bytes_short
< 0)
8747 /* There are enough RELAX_NARROW frags after this one
8748 to align the target without widening this frag in any way. */
8752 if (bytes_short
== 0)
8754 /* Widen every narrow between here and the align target
8755 and the align target will be properly aligned. */
8756 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8762 /* From here we will need at least one NOP to get an alignment.
8763 However, we may not be able to align at all, in which case,
8765 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8767 switch (desired_diff
)
8772 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 1)
8773 return 2; /* case 2 */
8779 return 3; /* case 3a */
8781 if (num_widens
>= 1 && wide_nops
== 1)
8782 return 3; /* case 4a */
8783 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 2)
8784 return 2; /* case 4b */
8787 if (num_widens
>= 2 && wide_nops
== 1)
8788 return 3; /* case 5a */
8789 /* We will need two nops. Are there enough nops
8790 between here and the align target? */
8791 if (wide_nops
< 2 || narrow_nops
== 0)
8793 /* Are there other nops closer that can serve instead? */
8794 if (wide_nops
> 2 && narrow_nops
> 1)
8796 /* Take the density one first, because there might not be
8797 another density one available. */
8798 if (!this_frag
->tc_frag_data
.is_no_density
)
8799 return 2; /* case 5b narrow */
8801 return 3; /* case 5b wide */
8805 return 3; /* case 6a */
8806 else if (num_widens
>= 3 && wide_nops
== 1)
8807 return 3; /* case 6b */
8810 if (wide_nops
== 1 && num_widens
>= 4)
8811 return 3; /* case 7a */
8812 else if (wide_nops
== 2 && num_widens
>= 1)
8813 return 3; /* case 7b */
8821 /* We will need a NOP no matter what, but should we widen
8822 this instruction to help?
8824 This is a RELAX_NARROW frag. */
8825 switch (desired_diff
)
8834 if (wide_nops
>= 1 && num_widens
== 1)
8835 return 1; /* case 4a */
8838 if (wide_nops
>= 1 && num_widens
== 2)
8839 return 1; /* case 5a */
8843 return 0; /* case 6a */
8844 else if (wide_nops
>= 1 && num_widens
== 3)
8845 return 1; /* case 6b */
8848 if (wide_nops
>= 1 && num_widens
== 4)
8849 return 1; /* case 7a */
8850 else if (wide_nops
>= 2 && num_widens
== 1)
8851 return 1; /* case 7b */
8864 relax_frag_immed (segT segP
,
8871 bfd_boolean estimate_only
)
8875 bfd_boolean negatable_branch
= FALSE
;
8876 bfd_boolean branch_jmp_to_next
= FALSE
;
8877 bfd_boolean wide_insn
= FALSE
;
8878 xtensa_isa isa
= xtensa_default_isa
;
8880 offsetT frag_offset
;
8883 int num_text_bytes
, num_literal_bytes
;
8884 int literal_diff
, total_text_diff
, this_text_diff
, first
;
8886 assert (fragP
->fr_opcode
!= NULL
);
8888 xg_clear_vinsn (&cur_vinsn
);
8889 vinsn_from_chars (&cur_vinsn
, fragP
->fr_opcode
);
8890 if (cur_vinsn
.num_slots
> 1)
8893 tinsn
= cur_vinsn
.slots
[slot
];
8894 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
8896 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
) == 1)
8899 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
8900 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
8902 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
8904 old_size
= xtensa_format_length (isa
, fmt
);
8906 /* Special case: replace a branch to the next instruction with a NOP.
8907 This is required to work around a hardware bug in T1040.0 and also
8908 serves as an optimization. */
8910 if (branch_jmp_to_next
8911 && ((old_size
== 2) || (old_size
== 3))
8912 && !next_frag_is_loop_target (fragP
))
8915 /* Here is the fun stuff: Get the immediate field from this
8916 instruction. If it fits, we are done. If not, find the next
8917 instruction sequence that fits. */
8919 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
8920 istack_init (&istack
);
8921 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
8922 min_steps
, stretch
);
8923 if (num_steps
< min_steps
)
8925 as_fatal (_("internal error: relaxation failed"));
8929 if (num_steps
> RELAX_IMMED_MAXSTEPS
)
8931 as_fatal (_("internal error: relaxation requires too many steps"));
8935 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
8937 /* Figure out the number of bytes needed. */
8939 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
8941 num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
8943 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
8945 num_text_bytes
= get_num_stack_text_bytes (&istack
);
8948 num_text_bytes
+= old_size
;
8949 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
8950 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
8952 total_text_diff
= num_text_bytes
- old_size
;
8953 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
8955 /* It MUST get larger. If not, we could get an infinite loop. */
8956 assert (num_text_bytes
>= 0);
8957 assert (literal_diff
>= 0);
8958 assert (total_text_diff
>= 0);
8960 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
8961 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
8962 assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
8963 assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
8965 /* Find the associated expandable literal for this. */
8966 if (literal_diff
!= 0)
8968 lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
8971 assert (literal_diff
== 4);
8972 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
8974 /* We expect that the literal section state has NOT been
8976 assert (lit_fragP
->fr_type
== rs_machine_dependent
8977 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
8978 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
8980 /* We need to mark this section for another iteration
8986 if (negatable_branch
&& istack
.ninsn
> 1)
8987 update_next_frag_state (fragP
);
8989 return this_text_diff
;
8993 /* md_convert_frag Hook and Helper Functions. */
8995 static void convert_frag_align_next_opcode (fragS
*);
8996 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
8997 static void convert_frag_fill_nop (fragS
*);
8998 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
9001 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
9003 static xtensa_insnbuf vbuf
= NULL
;
9004 xtensa_isa isa
= xtensa_default_isa
;
9011 as_where (&file_name
, &line
);
9012 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
9014 switch (fragp
->fr_subtype
)
9016 case RELAX_ALIGN_NEXT_OPCODE
:
9017 /* Always convert. */
9018 convert_frag_align_next_opcode (fragp
);
9021 case RELAX_DESIRE_ALIGN
:
9022 /* Do nothing. If not aligned already, too bad. */
9026 case RELAX_LITERAL_FINAL
:
9031 vbuf
= xtensa_insnbuf_alloc (isa
);
9033 xtensa_insnbuf_from_chars
9034 (isa
, vbuf
, (unsigned char *) fragp
->fr_opcode
, 0);
9035 fmt
= xtensa_format_decode (isa
, vbuf
);
9036 num_slots
= xtensa_format_num_slots (isa
, fmt
);
9038 for (slot
= 0; slot
< num_slots
; slot
++)
9040 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
9043 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
9047 case RELAX_IMMED_STEP1
:
9048 case RELAX_IMMED_STEP2
:
9049 case RELAX_IMMED_STEP3
:
9050 /* Place the immediate. */
9053 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
9058 /* This is OK because some slots could have
9059 relaxations and others have none. */
9065 case RELAX_UNREACHABLE
:
9066 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
9067 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
9068 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
9072 case RELAX_MAYBE_UNREACHABLE
:
9073 case RELAX_MAYBE_DESIRE_ALIGN
:
9077 case RELAX_FILL_NOP
:
9078 convert_frag_fill_nop (fragp
);
9081 case RELAX_LITERAL_NR
:
9082 if (use_literal_section
)
9084 /* This should have been handled during relaxation. When
9085 relaxing a code segment, literals sometimes need to be
9086 added to the corresponding literal segment. If that
9087 literal segment has already been relaxed, then we end up
9088 in this situation. Marking the literal segments as data
9089 would make this happen less often (since GAS always relaxes
9090 code before data), but we could still get into trouble if
9091 there are instructions in a segment that is not marked as
9092 containing code. Until we can implement a better solution,
9093 cheat and adjust the addresses of all the following frags.
9094 This could break subsequent alignments, but the linker's
9095 literal coalescing will do that anyway. */
9098 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
9099 assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
9100 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
9103 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
9107 as_bad (_("invalid relaxation fragment result"));
9112 new_logical_line (file_name
, line
);
9117 convert_frag_align_next_opcode (fragS
*fragp
)
9119 char *nop_buf
; /* Location for Writing. */
9120 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
9121 addressT aligned_address
;
9125 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
9127 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
9128 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
9129 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
9131 for (nop
= 0; nop
< nop_count
; nop
++)
9134 nop_size
= get_text_align_nth_nop_size (fill_size
, nop
, use_no_density
);
9136 assemble_nop (nop_size
, nop_buf
);
9137 nop_buf
+= nop_size
;
9140 fragp
->fr_fix
+= fill_size
;
9141 fragp
->fr_var
-= fill_size
;
9146 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
9148 TInsn tinsn
, single_target
;
9149 int size
, old_size
, diff
;
9150 offsetT frag_offset
;
9153 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
9155 if (fragP
->tc_frag_data
.is_aligning_branch
== 1)
9157 assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
9158 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
9159 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
9164 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
9166 /* No conversion. */
9171 assert (fragP
->fr_opcode
!= NULL
);
9173 /* Frags in this relaxation state should only contain
9174 single instruction bundles. */
9175 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
9177 /* Just convert it to a wide form.... */
9179 old_size
= xg_get_single_size (tinsn
.opcode
);
9181 tinsn_init (&single_target
);
9182 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9184 if (! xg_is_single_relaxable_insn (&tinsn
, &single_target
, FALSE
))
9186 as_bad (_("unable to widen instruction"));
9190 size
= xg_get_single_size (single_target
.opcode
);
9191 xg_emit_insn_to_buf (&single_target
, fragP
->fr_opcode
, fragP
,
9194 diff
= size
- old_size
;
9196 assert (diff
<= fragP
->fr_var
);
9197 fragP
->fr_var
-= diff
;
9198 fragP
->fr_fix
+= diff
;
9206 convert_frag_fill_nop (fragS
*fragP
)
9208 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
9209 int size
= fragP
->tc_frag_data
.text_expansion
[0];
9210 assert ((unsigned) size
== (fragP
->fr_next
->fr_address
9211 - fragP
->fr_address
- fragP
->fr_fix
));
9214 /* No conversion. */
9218 assemble_nop (size
, loc
);
9219 fragP
->tc_frag_data
.is_insn
= TRUE
;
9220 fragP
->fr_var
-= size
;
9221 fragP
->fr_fix
+= size
;
9226 static fixS
*fix_new_exp_in_seg
9227 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
9228 bfd_reloc_code_real_type
);
9229 static void convert_frag_immed_finish_loop (segT
, fragS
*, TInsn
*);
9232 convert_frag_immed (segT segP
,
9238 char *immed_instr
= fragP
->fr_opcode
;
9240 bfd_boolean expanded
= FALSE
;
9241 bfd_boolean branch_jmp_to_next
= FALSE
;
9242 char *fr_opcode
= fragP
->fr_opcode
;
9243 xtensa_isa isa
= xtensa_default_isa
;
9244 bfd_boolean wide_insn
= FALSE
;
9246 bfd_boolean is_loop
;
9248 assert (fr_opcode
!= NULL
);
9250 xg_clear_vinsn (&cur_vinsn
);
9252 vinsn_from_chars (&cur_vinsn
, fr_opcode
);
9253 if (cur_vinsn
.num_slots
> 1)
9256 orig_tinsn
= cur_vinsn
.slots
[slot
];
9257 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
9259 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
9261 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9262 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
9264 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
9266 /* Conversion just inserts a NOP and marks the fix as completed. */
9267 bytes
= xtensa_format_length (isa
, fmt
);
9270 cur_vinsn
.slots
[slot
].opcode
=
9271 xtensa_format_slot_nop_opcode (isa
, cur_vinsn
.format
, slot
);
9272 cur_vinsn
.slots
[slot
].ntok
= 0;
9276 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
9277 assert (bytes
== 2 || bytes
== 3);
9278 build_nop (&cur_vinsn
.slots
[0], bytes
);
9279 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
9281 vinsn_to_insnbuf (&cur_vinsn
, fr_opcode
, frag_now
, TRUE
);
9282 xtensa_insnbuf_to_chars
9283 (isa
, cur_vinsn
.insnbuf
, (unsigned char *) fr_opcode
, 0);
9288 /* Here is the fun stuff: Get the immediate field from this
9289 instruction. If it fits, we're done. If not, find the next
9290 instruction sequence that fits. */
9294 symbolS
*lit_sym
= NULL
;
9296 int target_offset
= 0;
9299 symbolS
*gen_label
= NULL
;
9300 offsetT frag_offset
;
9301 bfd_boolean first
= TRUE
;
9302 bfd_boolean last_is_jump
;
9304 /* It does not fit. Find something that does and
9305 convert immediately. */
9306 frag_offset
= fr_opcode
- fragP
->fr_literal
;
9307 istack_init (&istack
);
9308 xg_assembly_relax (&istack
, &orig_tinsn
,
9309 segP
, fragP
, frag_offset
, min_steps
, 0);
9311 old_size
= xtensa_format_length (isa
, fmt
);
9313 /* Assemble this right inline. */
9315 /* First, create the mapping from a label name to the REAL label. */
9317 for (i
= 0; i
< istack
.ninsn
; i
++)
9319 TInsn
*tinsn
= &istack
.insn
[i
];
9322 switch (tinsn
->insn_type
)
9325 if (lit_sym
!= NULL
)
9326 as_bad (_("multiple literals in expansion"));
9327 /* First find the appropriate space in the literal pool. */
9328 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9329 if (lit_frag
== NULL
)
9330 as_bad (_("no registered fragment for literal"));
9331 if (tinsn
->ntok
!= 1)
9332 as_bad (_("number of literal tokens != 1"));
9334 /* Set the literal symbol and add a fixup. */
9335 lit_sym
= lit_frag
->fr_symbol
;
9339 if (align_targets
&& !is_loop
)
9341 fragS
*unreach
= fragP
->fr_next
;
9342 while (!(unreach
->fr_type
== rs_machine_dependent
9343 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9344 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
9346 unreach
= unreach
->fr_next
;
9349 assert (unreach
->fr_type
== rs_machine_dependent
9350 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9351 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
9353 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
9355 assert (gen_label
== NULL
);
9356 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
9357 fr_opcode
- fragP
->fr_literal
9358 + target_offset
, fragP
);
9362 if (first
&& wide_insn
)
9364 target_offset
+= xtensa_format_length (isa
, fmt
);
9366 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9367 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9370 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9377 last_is_jump
= FALSE
;
9378 for (i
= 0; i
< istack
.ninsn
; i
++)
9380 TInsn
*tinsn
= &istack
.insn
[i
];
9384 bfd_reloc_code_real_type reloc_type
;
9386 switch (tinsn
->insn_type
)
9389 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9390 /* Already checked. */
9391 assert (lit_frag
!= NULL
);
9392 assert (lit_sym
!= NULL
);
9393 assert (tinsn
->ntok
== 1);
9395 target_seg
= S_GET_SEGMENT (lit_sym
);
9396 assert (target_seg
);
9397 reloc_type
= map_operator_to_reloc (tinsn
->tok
[0].X_op
);
9398 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
9399 &tinsn
->tok
[0], FALSE
, reloc_type
);
9406 xg_resolve_labels (tinsn
, gen_label
);
9407 xg_resolve_literals (tinsn
, lit_sym
);
9408 if (wide_insn
&& first
)
9411 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9413 cur_vinsn
.slots
[slot
] = *tinsn
;
9417 cur_vinsn
.slots
[slot
].opcode
=
9418 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
9419 cur_vinsn
.slots
[slot
].ntok
= 0;
9421 vinsn_to_insnbuf (&cur_vinsn
, immed_instr
, fragP
, TRUE
);
9422 xtensa_insnbuf_to_chars (isa
, cur_vinsn
.insnbuf
,
9423 (unsigned char *) immed_instr
, 0);
9424 fragP
->tc_frag_data
.is_insn
= TRUE
;
9425 size
= xtensa_format_length (isa
, fmt
);
9426 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9429 (tinsn
, immed_instr
+ size
, fragP
,
9430 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
9431 size
+= xg_get_single_size (tinsn
->opcode
);
9436 size
= xg_get_single_size (tinsn
->opcode
);
9437 xg_emit_insn_to_buf (tinsn
, immed_instr
, fragP
,
9438 immed_instr
- fragP
->fr_literal
, TRUE
);
9440 immed_instr
+= size
;
9446 diff
= total_size
- old_size
;
9450 assert (diff
<= fragP
->fr_var
);
9451 fragP
->fr_var
-= diff
;
9452 fragP
->fr_fix
+= diff
;
9455 /* Check for undefined immediates in LOOP instructions. */
9459 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
9460 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9462 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9465 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
9466 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9468 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9473 if (expanded
&& xtensa_opcode_is_loop (isa
, orig_tinsn
.opcode
) == 1)
9474 convert_frag_immed_finish_loop (segP
, fragP
, &orig_tinsn
);
9476 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
9478 /* Add an expansion note on the expanded instruction. */
9479 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
9480 &orig_tinsn
.tok
[0], TRUE
,
9481 BFD_RELOC_XTENSA_ASM_EXPAND
);
9486 /* Add a new fix expression into the desired segment. We have to
9487 switch to that segment to do this. */
9490 fix_new_exp_in_seg (segT new_seg
,
9497 bfd_reloc_code_real_type r_type
)
9501 subsegT subseg
= now_subseg
;
9503 assert (new_seg
!= 0);
9504 subseg_set (new_seg
, new_subseg
);
9506 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
9507 subseg_set (seg
, subseg
);
9512 /* Relax a loop instruction so that it can span loop >256 bytes.
9518 addi as, as, lo8 (label-.L1)
9519 addmi as, as, mid8 (label-.L1)
9530 convert_frag_immed_finish_loop (segT segP
, fragS
*fragP
, TInsn
*tinsn
)
9535 unsigned long target
;
9536 static xtensa_insnbuf insnbuf
= NULL
;
9537 unsigned int loop_length
, loop_length_hi
, loop_length_lo
;
9538 xtensa_isa isa
= xtensa_default_isa
;
9539 addressT loop_offset
;
9540 addressT addi_offset
= 9;
9541 addressT addmi_offset
= 12;
9546 insnbuf
= xtensa_insnbuf_alloc (isa
);
9548 /* Get the loop offset. */
9549 loop_offset
= get_expanded_loop_offset (tinsn
->opcode
);
9551 /* Validate that there really is a LOOP at the loop_offset. Because
9552 loops are not bundleable, we can assume that the instruction will be
9554 tinsn_from_chars (&loop_insn
, fragP
->fr_opcode
+ loop_offset
, 0);
9555 tinsn_immed_from_frag (&loop_insn
, fragP
, 0);
9557 assert (xtensa_opcode_is_loop (isa
, loop_insn
.opcode
) == 1);
9558 addi_offset
+= loop_offset
;
9559 addmi_offset
+= loop_offset
;
9561 assert (tinsn
->ntok
== 2);
9562 if (tinsn
->tok
[1].X_op
== O_constant
)
9563 target
= tinsn
->tok
[1].X_add_number
;
9564 else if (tinsn
->tok
[1].X_op
== O_symbol
)
9566 /* Find the fragment. */
9567 symbolS
*sym
= tinsn
->tok
[1].X_add_symbol
;
9568 assert (S_GET_SEGMENT (sym
) == segP
9569 || S_GET_SEGMENT (sym
) == absolute_section
);
9570 target
= (S_GET_VALUE (sym
) + tinsn
->tok
[1].X_add_number
);
9574 as_bad (_("invalid expression evaluation type %d"), tinsn
->tok
[1].X_op
);
9578 loop_length
= target
- (fragP
->fr_address
+ fragP
->fr_fix
);
9579 loop_length_hi
= loop_length
& ~0x0ff;
9580 loop_length_lo
= loop_length
& 0x0ff;
9581 if (loop_length_lo
>= 128)
9583 loop_length_lo
-= 256;
9584 loop_length_hi
+= 256;
9587 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
9588 32512. If the loop is larger than that, then we just fail. */
9589 if (loop_length_hi
> 32512)
9590 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9591 _("loop too long for LOOP instruction"));
9593 tinsn_from_chars (&addi_insn
, fragP
->fr_opcode
+ addi_offset
, 0);
9594 assert (addi_insn
.opcode
== xtensa_addi_opcode
);
9596 tinsn_from_chars (&addmi_insn
, fragP
->fr_opcode
+ addmi_offset
, 0);
9597 assert (addmi_insn
.opcode
== xtensa_addmi_opcode
);
9599 set_expr_const (&addi_insn
.tok
[2], loop_length_lo
);
9600 tinsn_to_insnbuf (&addi_insn
, insnbuf
);
9602 fragP
->tc_frag_data
.is_insn
= TRUE
;
9603 xtensa_insnbuf_to_chars
9604 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addi_offset
, 0);
9606 set_expr_const (&addmi_insn
.tok
[2], loop_length_hi
);
9607 tinsn_to_insnbuf (&addmi_insn
, insnbuf
);
9608 xtensa_insnbuf_to_chars
9609 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addmi_offset
, 0);
9611 /* Walk through all of the frags from here to the loop end
9612 and mark them as no_transform to keep them from being modified
9613 by the linker. If we ever have a relocation for the
9614 addi/addmi of the difference of two symbols we can remove this. */
9617 for (next_fragP
= fragP
; next_fragP
!= NULL
;
9618 next_fragP
= next_fragP
->fr_next
)
9620 next_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
9621 if (next_fragP
->tc_frag_data
.is_loop_target
)
9623 if (target_count
== 2)
9629 /* A map that keeps information on a per-subsegment basis. This is
9630 maintained during initial assembly, but is invalid once the
9631 subsegments are smashed together. I.E., it cannot be used during
9634 typedef struct subseg_map_struct
9642 float total_freq
; /* fall-through + branch target frequency */
9643 float target_freq
; /* branch target frequency alone */
9645 struct subseg_map_struct
*next
;
9649 static subseg_map
*sseg_map
= NULL
;
9652 get_subseg_info (segT seg
, subsegT subseg
)
9654 subseg_map
*subseg_e
;
9656 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
9658 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
9666 add_subseg_info (segT seg
, subsegT subseg
)
9668 subseg_map
*subseg_e
= (subseg_map
*) xmalloc (sizeof (subseg_map
));
9669 memset (subseg_e
, 0, sizeof (subseg_map
));
9670 subseg_e
->seg
= seg
;
9671 subseg_e
->subseg
= subseg
;
9672 subseg_e
->flags
= 0;
9673 /* Start off considering every branch target very important. */
9674 subseg_e
->target_freq
= 1.0;
9675 subseg_e
->total_freq
= 1.0;
9676 subseg_e
->next
= sseg_map
;
9677 sseg_map
= subseg_e
;
9683 get_last_insn_flags (segT seg
, subsegT subseg
)
9685 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9687 return subseg_e
->flags
;
9693 set_last_insn_flags (segT seg
,
9698 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9700 subseg_e
= add_subseg_info (seg
, subseg
);
9702 subseg_e
->flags
|= fl
;
9704 subseg_e
->flags
&= ~fl
;
9709 get_subseg_total_freq (segT seg
, subsegT subseg
)
9711 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9713 return subseg_e
->total_freq
;
9719 get_subseg_target_freq (segT seg
, subsegT subseg
)
9721 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9723 return subseg_e
->target_freq
;
9729 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
9731 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9733 subseg_e
= add_subseg_info (seg
, subseg
);
9734 subseg_e
->total_freq
= total_f
;
9735 subseg_e
->target_freq
= target_f
;
9739 /* Segment Lists and emit_state Stuff. */
9742 xtensa_move_seg_list_to_beginning (seg_list
*head
)
9747 segT literal_section
= head
->seg
;
9749 /* Move the literal section to the front of the section list. */
9750 assert (literal_section
);
9751 if (literal_section
!= stdoutput
->sections
)
9753 bfd_section_list_remove (stdoutput
, literal_section
);
9754 bfd_section_list_prepend (stdoutput
, literal_section
);
9761 static void mark_literal_frags (seg_list
*);
9764 xtensa_move_literals (void)
9767 frchainS
*frchain_from
, *frchain_to
;
9768 fragS
*search_frag
, *next_frag
, *last_frag
, *literal_pool
, *insert_after
;
9769 fragS
**frag_splice
;
9772 fixS
*fix
, *next_fix
, **fix_splice
;
9775 mark_literal_frags (literal_head
->next
);
9777 if (use_literal_section
)
9780 for (segment
= literal_head
->next
; segment
; segment
= segment
->next
)
9782 /* Keep the literals for .init and .fini in separate sections. */
9783 if (!strcmp (segment_name (segment
->seg
), INIT_SECTION_NAME
)
9784 || !strcmp (segment_name (segment
->seg
), FINI_SECTION_NAME
))
9787 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9788 search_frag
= frchain_from
->frch_root
;
9789 literal_pool
= NULL
;
9791 frag_splice
= &(frchain_from
->frch_root
);
9793 while (!search_frag
->tc_frag_data
.literal_frag
)
9795 assert (search_frag
->fr_fix
== 0
9796 || search_frag
->fr_type
== rs_align
);
9797 search_frag
= search_frag
->fr_next
;
9800 assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
9801 == RELAX_LITERAL_POOL_BEGIN
);
9802 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
9804 /* Make sure that all the frags in this series are closed, and
9805 that there is at least one left over of zero-size. This
9806 prevents us from making a segment with an frchain without any
9808 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9809 xtensa_set_frag_assembly_state (frag_now
);
9810 last_frag
= frag_now
;
9811 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9812 xtensa_set_frag_assembly_state (frag_now
);
9814 while (search_frag
!= frag_now
)
9816 next_frag
= search_frag
->fr_next
;
9818 /* First, move the frag out of the literal section and
9819 to the appropriate place. */
9820 if (search_frag
->tc_frag_data
.literal_frag
)
9822 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
9823 assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
9824 frchain_to
= literal_pool
->tc_frag_data
.lit_frchain
;
9825 assert (frchain_to
);
9827 insert_after
= literal_pool
->tc_frag_data
.literal_frag
;
9828 dest_seg
= insert_after
->fr_next
->tc_frag_data
.lit_seg
;
9830 *frag_splice
= next_frag
;
9831 search_frag
->fr_next
= insert_after
->fr_next
;
9832 insert_after
->fr_next
= search_frag
;
9833 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
9834 literal_pool
->tc_frag_data
.literal_frag
= search_frag
;
9836 /* Now move any fixups associated with this frag to the
9838 fix
= frchain_from
->fix_root
;
9839 fix_splice
= &(frchain_from
->fix_root
);
9842 next_fix
= fix
->fx_next
;
9843 if (fix
->fx_frag
== search_frag
)
9845 *fix_splice
= next_fix
;
9846 fix
->fx_next
= frchain_to
->fix_root
;
9847 frchain_to
->fix_root
= fix
;
9848 if (frchain_to
->fix_tail
== NULL
)
9849 frchain_to
->fix_tail
= fix
;
9852 fix_splice
= &(fix
->fx_next
);
9855 search_frag
= next_frag
;
9858 if (frchain_from
->fix_root
!= NULL
)
9860 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9861 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
9863 assert (frchain_from
->fix_root
== NULL
);
9865 frchain_from
->fix_tail
= NULL
;
9866 xtensa_restore_emit_state (&state
);
9869 /* Now fix up the SEGMENT value for all the literal symbols. */
9870 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
9872 symbolS
*lit_sym
= lit
->sym
;
9873 segT dest_seg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
9875 S_SET_SEGMENT (lit_sym
, dest_seg
);
9880 /* Walk over all the frags for segments in a list and mark them as
9881 containing literals. As clunky as this is, we can't rely on frag_var
9882 and frag_variant to get called in all situations. */
9885 mark_literal_frags (seg_list
*segment
)
9887 frchainS
*frchain_from
;
9892 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9893 search_frag
= frchain_from
->frch_root
;
9896 search_frag
->tc_frag_data
.is_literal
= TRUE
;
9897 search_frag
= search_frag
->fr_next
;
9899 segment
= segment
->next
;
9905 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
9907 /* Move all of the sections in the section list to come
9908 after "after" in the gnu segment list. */
9913 segT literal_section
= head
->seg
;
9915 /* Move the literal section after "after". */
9916 assert (literal_section
);
9917 if (literal_section
!= after
)
9919 bfd_section_list_remove (stdoutput
, literal_section
);
9920 bfd_section_list_insert_after (stdoutput
, after
, literal_section
);
9928 /* Push all the literal segments to the end of the gnu list. */
9931 xtensa_reorder_segments (void)
9938 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
9944 /* Now that we have the last section, push all the literal
9945 sections to the end. */
9946 xtensa_reorder_seg_list (literal_head
, last_sec
);
9948 /* Now perform the final error check. */
9949 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
9951 assert (new_count
== old_count
);
9955 /* Change the emit state (seg, subseg, and frag related stuff) to the
9956 correct location. Return a emit_state which can be passed to
9957 xtensa_restore_emit_state to return to current fragment. */
9960 xtensa_switch_to_literal_fragment (emit_state
*result
)
9962 if (directive_state
[directive_absolute_literals
])
9964 segT lit4_seg
= cache_literal_section (TRUE
);
9965 xtensa_switch_section_emit_state (result
, lit4_seg
, 0);
9968 xtensa_switch_to_non_abs_literal_fragment (result
);
9970 /* Do a 4-byte align here. */
9971 frag_align (2, 0, 0);
9972 record_alignment (now_seg
, 2);
9977 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
9979 static bfd_boolean recursive
= FALSE
;
9980 fragS
*pool_location
= get_literal_pool_location (now_seg
);
9982 bfd_boolean is_init
=
9983 (now_seg
&& !strcmp (segment_name (now_seg
), INIT_SECTION_NAME
));
9984 bfd_boolean is_fini
=
9985 (now_seg
&& !strcmp (segment_name (now_seg
), FINI_SECTION_NAME
));
9987 if (pool_location
== NULL
9988 && !use_literal_section
9990 && !is_init
&& ! is_fini
)
9992 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
9994 /* When we mark a literal pool location, we want to put a frag in
9995 the literal pool that points to it. But to do that, we want to
9996 switch_to_literal_fragment. But literal sections don't have
9997 literal pools, so their location is always null, so we would
9998 recurse forever. This is kind of hacky, but it works. */
10001 xtensa_mark_literal_pool_location ();
10005 lit_seg
= cache_literal_section (FALSE
);
10006 xtensa_switch_section_emit_state (result
, lit_seg
, 0);
10008 if (!use_literal_section
10009 && !is_init
&& !is_fini
10010 && get_literal_pool_location (now_seg
) != pool_location
)
10012 /* Close whatever frag is there. */
10013 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10014 xtensa_set_frag_assembly_state (frag_now
);
10015 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
10016 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10017 xtensa_set_frag_assembly_state (frag_now
);
10022 /* Call this function before emitting data into the literal section.
10023 This is a helper function for xtensa_switch_to_literal_fragment.
10024 This is similar to a .section new_now_seg subseg. */
10027 xtensa_switch_section_emit_state (emit_state
*state
,
10029 subsegT new_now_subseg
)
10031 state
->name
= now_seg
->name
;
10032 state
->now_seg
= now_seg
;
10033 state
->now_subseg
= now_subseg
;
10034 state
->generating_literals
= generating_literals
;
10035 generating_literals
++;
10036 subseg_set (new_now_seg
, new_now_subseg
);
10040 /* Use to restore the emitting into the normal place. */
10043 xtensa_restore_emit_state (emit_state
*state
)
10045 generating_literals
= state
->generating_literals
;
10046 subseg_set (state
->now_seg
, state
->now_subseg
);
10050 /* Predicate function used to look up a section in a particular group. */
10053 match_section_group (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
, void *inf
)
10055 const char *gname
= inf
;
10056 const char *group_name
= elf_group_name (sec
);
10058 return (group_name
== gname
10059 || (group_name
!= NULL
10061 && strcmp (group_name
, gname
) == 0));
10065 /* Get the literal section to be used for the current text section.
10066 The result may be cached in the default_lit_sections structure. */
10069 cache_literal_section (bfd_boolean use_abs_literals
)
10071 const char *text_name
, *group_name
= 0;
10072 char *base_name
, *name
, *suffix
;
10074 segT seg
, current_section
;
10075 int current_subsec
;
10076 bfd_boolean linkonce
= FALSE
;
10078 /* Save the current section/subsection. */
10079 current_section
= now_seg
;
10080 current_subsec
= now_subseg
;
10082 /* Clear the cached values if they are no longer valid. */
10083 if (now_seg
!= default_lit_sections
.current_text_seg
)
10085 default_lit_sections
.current_text_seg
= now_seg
;
10086 default_lit_sections
.lit_seg
= NULL
;
10087 default_lit_sections
.lit4_seg
= NULL
;
10090 /* Check if the literal section is already cached. */
10091 if (use_abs_literals
)
10092 pcached
= &default_lit_sections
.lit4_seg
;
10094 pcached
= &default_lit_sections
.lit_seg
;
10099 text_name
= default_lit_sections
.lit_prefix
;
10100 if (! text_name
|| ! *text_name
)
10102 text_name
= segment_name (current_section
);
10103 group_name
= elf_group_name (current_section
);
10104 linkonce
= (current_section
->flags
& SEC_LINK_ONCE
) != 0;
10107 base_name
= use_abs_literals
? ".lit4" : ".literal";
10110 name
= xmalloc (strlen (base_name
) + strlen (group_name
) + 2);
10111 sprintf (name
, "%s.%s", base_name
, group_name
);
10113 else if (strncmp (text_name
, ".gnu.linkonce.", linkonce_len
) == 0)
10115 suffix
= strchr (text_name
+ linkonce_len
, '.');
10117 name
= xmalloc (linkonce_len
+ strlen (base_name
) + 1
10118 + (suffix
? strlen (suffix
) : 0));
10119 strcpy (name
, ".gnu.linkonce");
10120 strcat (name
, base_name
);
10122 strcat (name
, suffix
);
10127 /* If the section name ends with ".text", then replace that suffix
10128 instead of appending an additional suffix. */
10129 size_t len
= strlen (text_name
);
10130 if (len
>= 5 && strcmp (text_name
+ len
- 5, ".text") == 0)
10133 name
= xmalloc (len
+ strlen (base_name
) + 1);
10134 strcpy (name
, text_name
);
10135 strcpy (name
+ len
, base_name
);
10138 /* Canonicalize section names to allow renaming literal sections.
10139 The group name, if any, came from the current text section and
10140 has already been canonicalized. */
10141 name
= tc_canonicalize_symbol_name (name
);
10143 seg
= bfd_get_section_by_name_if (stdoutput
, name
, match_section_group
,
10144 (void *) group_name
);
10149 seg
= subseg_force_new (name
, 0);
10151 if (! use_abs_literals
)
10153 /* Add the newly created literal segment to the list. */
10154 seg_list
*n
= (seg_list
*) xmalloc (sizeof (seg_list
));
10156 n
->next
= literal_head
->next
;
10157 literal_head
->next
= n
;
10160 flags
= (SEC_HAS_CONTENTS
| SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
10161 | (linkonce
? (SEC_LINK_ONCE
| SEC_LINK_DUPLICATES_DISCARD
) : 0)
10162 | (use_abs_literals
? SEC_DATA
: SEC_CODE
));
10164 elf_group_name (seg
) = group_name
;
10166 bfd_set_section_flags (stdoutput
, seg
, flags
);
10167 bfd_set_section_alignment (stdoutput
, seg
, 2);
10171 subseg_set (current_section
, current_subsec
);
10176 /* Property Tables Stuff. */
10178 #define XTENSA_INSN_SEC_NAME ".xt.insn"
10179 #define XTENSA_LIT_SEC_NAME ".xt.lit"
10180 #define XTENSA_PROP_SEC_NAME ".xt.prop"
10182 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
10183 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
10185 static bfd_boolean
get_frag_is_literal (const fragS
*);
10186 static void xtensa_create_property_segments
10187 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
10188 static void xtensa_create_xproperty_segments
10189 (frag_flags_fn
, const char *, xt_section_type
);
10190 static segment_info_type
*retrieve_segment_info (segT
);
10191 static bfd_boolean
section_has_property (segT
, frag_predicate
);
10192 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
10193 static void add_xt_block_frags
10194 (segT
, segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
10195 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
10196 static void xtensa_frag_flags_init (frag_flags
*);
10197 static void get_frag_property_flags (const fragS
*, frag_flags
*);
10198 static bfd_vma
frag_flags_to_number (const frag_flags
*);
10199 static void add_xt_prop_frags
10200 (segT
, segT
, xtensa_block_info
**, frag_flags_fn
);
10202 /* Set up property tables after relaxation. */
10205 xtensa_post_relax_hook (void)
10207 xtensa_move_seg_list_to_beginning (literal_head
);
10209 xtensa_find_unmarked_state_frags ();
10210 xtensa_mark_frags_for_org ();
10212 xtensa_create_property_segments (get_frag_is_literal
,
10214 XTENSA_LIT_SEC_NAME
,
10216 xtensa_create_xproperty_segments (get_frag_property_flags
,
10217 XTENSA_PROP_SEC_NAME
,
10220 if (warn_unaligned_branch_targets
)
10221 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
10222 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
10226 /* This function is only meaningful after xtensa_move_literals. */
10229 get_frag_is_literal (const fragS
*fragP
)
10231 assert (fragP
!= NULL
);
10232 return fragP
->tc_frag_data
.is_literal
;
10237 xtensa_create_property_segments (frag_predicate property_function
,
10238 frag_predicate end_property_function
,
10239 const char *section_name_base
,
10240 xt_section_type sec_type
)
10244 /* Walk over all of the current segments.
10245 Walk over each fragment
10246 For each non-empty fragment,
10247 Build a property record (append where possible). */
10249 for (seclist
= &stdoutput
->sections
;
10250 seclist
&& *seclist
;
10251 seclist
= &(*seclist
)->next
)
10253 segT sec
= *seclist
;
10256 flags
= bfd_get_section_flags (stdoutput
, sec
);
10257 if (flags
& SEC_DEBUGGING
)
10259 if (!(flags
& SEC_ALLOC
))
10262 if (section_has_property (sec
, property_function
))
10265 xtensa_get_property_section (sec
, section_name_base
);
10266 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10267 xtensa_block_info
**xt_blocks
=
10268 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10269 /* Walk over all of the frchains here and add new sections. */
10270 add_xt_block_frags (sec
, insn_sec
, xt_blocks
, property_function
,
10271 end_property_function
);
10275 /* Now we fill them out.... */
10277 for (seclist
= &stdoutput
->sections
;
10278 seclist
&& *seclist
;
10279 seclist
= &(*seclist
)->next
)
10281 segment_info_type
*seginfo
;
10282 xtensa_block_info
*block
;
10283 segT sec
= *seclist
;
10285 seginfo
= seg_info (sec
);
10286 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10290 xtensa_block_info
*cur_block
;
10291 /* This is a section with some data. */
10293 bfd_size_type rec_size
;
10295 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10298 rec_size
= num_recs
* 8;
10299 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10301 /* In order to make this work with the assembler, we have to
10302 build some frags and then build the "fixups" for it. It
10303 would be easier to just set the contents then set the
10308 /* Allocate a fragment and leak it. */
10310 bfd_size_type frag_size
;
10312 frchainS
*frchainP
;
10316 frag_size
= sizeof (fragS
) + rec_size
;
10317 fragP
= (fragS
*) xmalloc (frag_size
);
10319 memset (fragP
, 0, frag_size
);
10320 fragP
->fr_address
= 0;
10321 fragP
->fr_next
= NULL
;
10322 fragP
->fr_fix
= rec_size
;
10324 fragP
->fr_type
= rs_fill
;
10325 /* The rest are zeros. */
10327 frchainP
= seginfo
->frchainP
;
10328 frchainP
->frch_root
= fragP
;
10329 frchainP
->frch_last
= fragP
;
10331 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10332 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10334 seginfo
->fix_root
= fixes
;
10335 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10337 frag_data
= &fragP
->fr_literal
[0];
10338 for (i
= 0; i
< num_recs
; i
++)
10340 fixS
*fix
= &fixes
[i
];
10341 assert (cur_block
);
10343 /* Write the fixup. */
10344 if (i
!= num_recs
- 1)
10345 fix
->fx_next
= &fixes
[i
+ 1];
10347 fix
->fx_next
= NULL
;
10350 fix
->fx_frag
= fragP
;
10351 fix
->fx_where
= i
* 8;
10352 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10353 fix
->fx_offset
= cur_block
->offset
;
10354 fix
->fx_r_type
= BFD_RELOC_32
;
10355 fix
->fx_file
= "Internal Assembly";
10358 /* Write the length. */
10359 md_number_to_chars (&frag_data
[4 + 8 * i
],
10360 cur_block
->size
, 4);
10361 cur_block
= cur_block
->next
;
10370 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
10371 const char *section_name_base
,
10372 xt_section_type sec_type
)
10376 /* Walk over all of the current segments.
10377 Walk over each fragment.
10378 For each fragment that has instructions,
10379 build an instruction record (append where possible). */
10381 for (seclist
= &stdoutput
->sections
;
10382 seclist
&& *seclist
;
10383 seclist
= &(*seclist
)->next
)
10385 segT sec
= *seclist
;
10388 flags
= bfd_get_section_flags (stdoutput
, sec
);
10389 if ((flags
& SEC_DEBUGGING
)
10390 || !(flags
& SEC_ALLOC
)
10391 || (flags
& SEC_MERGE
))
10394 if (section_has_xproperty (sec
, flag_fn
))
10397 xtensa_get_property_section (sec
, section_name_base
);
10398 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10399 xtensa_block_info
**xt_blocks
=
10400 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10401 /* Walk over all of the frchains here and add new sections. */
10402 add_xt_prop_frags (sec
, insn_sec
, xt_blocks
, flag_fn
);
10406 /* Now we fill them out.... */
10408 for (seclist
= &stdoutput
->sections
;
10409 seclist
&& *seclist
;
10410 seclist
= &(*seclist
)->next
)
10412 segment_info_type
*seginfo
;
10413 xtensa_block_info
*block
;
10414 segT sec
= *seclist
;
10416 seginfo
= seg_info (sec
);
10417 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10421 xtensa_block_info
*cur_block
;
10422 /* This is a section with some data. */
10424 bfd_size_type rec_size
;
10426 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10429 rec_size
= num_recs
* (8 + 4);
10430 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10432 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
10434 /* In order to make this work with the assembler, we have to build
10435 some frags then build the "fixups" for it. It would be easier to
10436 just set the contents then set the arlents. */
10440 /* Allocate a fragment and (unfortunately) leak it. */
10442 bfd_size_type frag_size
;
10444 frchainS
*frchainP
;
10448 frag_size
= sizeof (fragS
) + rec_size
;
10449 fragP
= (fragS
*) xmalloc (frag_size
);
10451 memset (fragP
, 0, frag_size
);
10452 fragP
->fr_address
= 0;
10453 fragP
->fr_next
= NULL
;
10454 fragP
->fr_fix
= rec_size
;
10456 fragP
->fr_type
= rs_fill
;
10457 /* The rest are zeros. */
10459 frchainP
= seginfo
->frchainP
;
10460 frchainP
->frch_root
= fragP
;
10461 frchainP
->frch_last
= fragP
;
10463 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10464 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10466 seginfo
->fix_root
= fixes
;
10467 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10469 frag_data
= &fragP
->fr_literal
[0];
10470 for (i
= 0; i
< num_recs
; i
++)
10472 fixS
*fix
= &fixes
[i
];
10473 assert (cur_block
);
10475 /* Write the fixup. */
10476 if (i
!= num_recs
- 1)
10477 fix
->fx_next
= &fixes
[i
+ 1];
10479 fix
->fx_next
= NULL
;
10482 fix
->fx_frag
= fragP
;
10483 fix
->fx_where
= i
* (8 + 4);
10484 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10485 fix
->fx_offset
= cur_block
->offset
;
10486 fix
->fx_r_type
= BFD_RELOC_32
;
10487 fix
->fx_file
= "Internal Assembly";
10490 /* Write the length. */
10491 md_number_to_chars (&frag_data
[4 + (8+4) * i
],
10492 cur_block
->size
, 4);
10493 md_number_to_chars (&frag_data
[8 + (8+4) * i
],
10494 frag_flags_to_number (&cur_block
->flags
),
10496 cur_block
= cur_block
->next
;
10504 static segment_info_type
*
10505 retrieve_segment_info (segT seg
)
10507 segment_info_type
*seginfo
;
10508 seginfo
= (segment_info_type
*) bfd_get_section_userdata (stdoutput
, seg
);
10511 frchainS
*frchainP
;
10513 seginfo
= (segment_info_type
*) xmalloc (sizeof (*seginfo
));
10514 memset ((void *) seginfo
, 0, sizeof (*seginfo
));
10515 seginfo
->fix_root
= NULL
;
10516 seginfo
->fix_tail
= NULL
;
10517 seginfo
->bfd_section
= seg
;
10519 /* We will not be dealing with these, only our special ones. */
10520 bfd_set_section_userdata (stdoutput
, seg
, (void *) seginfo
);
10522 frchainP
= (frchainS
*) xmalloc (sizeof (frchainS
));
10523 frchainP
->frch_root
= NULL
;
10524 frchainP
->frch_last
= NULL
;
10525 frchainP
->frch_next
= NULL
;
10526 frchainP
->frch_subseg
= 0;
10527 frchainP
->fix_root
= NULL
;
10528 frchainP
->fix_tail
= NULL
;
10529 /* Do not init the objstack. */
10530 /* obstack_begin (&frchainP->frch_obstack, chunksize); */
10531 /* frchainP->frch_frag_now = fragP; */
10532 frchainP
->frch_frag_now
= NULL
;
10534 seginfo
->frchainP
= frchainP
;
10542 section_has_property (segT sec
, frag_predicate property_function
)
10544 segment_info_type
*seginfo
= seg_info (sec
);
10547 if (seginfo
&& seginfo
->frchainP
)
10549 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10551 if (property_function (fragP
)
10552 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10561 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
10563 segment_info_type
*seginfo
= seg_info (sec
);
10566 if (seginfo
&& seginfo
->frchainP
)
10568 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10570 frag_flags prop_flags
;
10571 property_function (fragP
, &prop_flags
);
10572 if (!xtensa_frag_flags_is_empty (&prop_flags
))
10580 /* Two types of block sections exist right now: literal and insns. */
10583 add_xt_block_frags (segT sec
,
10585 xtensa_block_info
**xt_block
,
10586 frag_predicate property_function
,
10587 frag_predicate end_property_function
)
10589 segment_info_type
*seg_info
;
10590 segment_info_type
*xt_seg_info
;
10591 bfd_vma seg_offset
;
10594 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
10595 seg_info
= retrieve_segment_info (sec
);
10597 /* Build it if needed. */
10598 while (*xt_block
!= NULL
)
10599 xt_block
= &(*xt_block
)->next
;
10600 /* We are either at NULL at the beginning or at the end. */
10602 /* Walk through the frags. */
10605 if (seg_info
->frchainP
)
10607 for (fragP
= seg_info
->frchainP
->frch_root
;
10609 fragP
= fragP
->fr_next
)
10611 if (property_function (fragP
)
10612 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10614 if (*xt_block
!= NULL
)
10616 if ((*xt_block
)->offset
+ (*xt_block
)->size
10617 == fragP
->fr_address
)
10618 (*xt_block
)->size
+= fragP
->fr_fix
;
10620 xt_block
= &((*xt_block
)->next
);
10622 if (*xt_block
== NULL
)
10624 xtensa_block_info
*new_block
= (xtensa_block_info
*)
10625 xmalloc (sizeof (xtensa_block_info
));
10626 new_block
->sec
= sec
;
10627 new_block
->offset
= fragP
->fr_address
;
10628 new_block
->size
= fragP
->fr_fix
;
10629 new_block
->next
= NULL
;
10630 xtensa_frag_flags_init (&new_block
->flags
);
10631 *xt_block
= new_block
;
10633 if (end_property_function
10634 && end_property_function (fragP
))
10636 xt_block
= &((*xt_block
)->next
);
10644 /* Break the encapsulation of add_xt_prop_frags here. */
10647 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
10649 if (prop_flags
->is_literal
10650 || prop_flags
->is_insn
10651 || prop_flags
->is_data
10652 || prop_flags
->is_unreachable
)
10659 xtensa_frag_flags_init (frag_flags
*prop_flags
)
10661 memset (prop_flags
, 0, sizeof (frag_flags
));
10666 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
10668 xtensa_frag_flags_init (prop_flags
);
10669 if (fragP
->tc_frag_data
.is_literal
)
10670 prop_flags
->is_literal
= TRUE
;
10671 if (fragP
->tc_frag_data
.is_specific_opcode
10672 || fragP
->tc_frag_data
.is_no_transform
)
10673 prop_flags
->is_no_transform
= TRUE
;
10674 if (fragP
->tc_frag_data
.is_unreachable
)
10675 prop_flags
->is_unreachable
= TRUE
;
10676 else if (fragP
->tc_frag_data
.is_insn
)
10678 prop_flags
->is_insn
= TRUE
;
10679 if (fragP
->tc_frag_data
.is_loop_target
)
10680 prop_flags
->insn
.is_loop_target
= TRUE
;
10681 if (fragP
->tc_frag_data
.is_branch_target
)
10682 prop_flags
->insn
.is_branch_target
= TRUE
;
10683 if (fragP
->tc_frag_data
.is_no_density
)
10684 prop_flags
->insn
.is_no_density
= TRUE
;
10685 if (fragP
->tc_frag_data
.use_absolute_literals
)
10686 prop_flags
->insn
.is_abslit
= TRUE
;
10688 if (fragP
->tc_frag_data
.is_align
)
10690 prop_flags
->is_align
= TRUE
;
10691 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
10692 if (xtensa_frag_flags_is_empty (prop_flags
))
10693 prop_flags
->is_data
= TRUE
;
10699 frag_flags_to_number (const frag_flags
*prop_flags
)
10702 if (prop_flags
->is_literal
)
10703 num
|= XTENSA_PROP_LITERAL
;
10704 if (prop_flags
->is_insn
)
10705 num
|= XTENSA_PROP_INSN
;
10706 if (prop_flags
->is_data
)
10707 num
|= XTENSA_PROP_DATA
;
10708 if (prop_flags
->is_unreachable
)
10709 num
|= XTENSA_PROP_UNREACHABLE
;
10710 if (prop_flags
->insn
.is_loop_target
)
10711 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
10712 if (prop_flags
->insn
.is_branch_target
)
10714 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
10715 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
10718 if (prop_flags
->insn
.is_no_density
)
10719 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
10720 if (prop_flags
->is_no_transform
)
10721 num
|= XTENSA_PROP_NO_TRANSFORM
;
10722 if (prop_flags
->insn
.is_no_reorder
)
10723 num
|= XTENSA_PROP_INSN_NO_REORDER
;
10724 if (prop_flags
->insn
.is_abslit
)
10725 num
|= XTENSA_PROP_INSN_ABSLIT
;
10727 if (prop_flags
->is_align
)
10729 num
|= XTENSA_PROP_ALIGN
;
10730 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
10738 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
10739 const frag_flags
*prop_flags_2
)
10741 /* Cannot combine with an end marker. */
10743 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
10745 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
10747 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
10750 if (prop_flags_1
->is_insn
)
10752 /* Properties of the beginning of the frag. */
10753 if (prop_flags_2
->insn
.is_loop_target
)
10755 if (prop_flags_2
->insn
.is_branch_target
)
10757 if (prop_flags_1
->insn
.is_no_density
!=
10758 prop_flags_2
->insn
.is_no_density
)
10760 if (prop_flags_1
->is_no_transform
!=
10761 prop_flags_2
->is_no_transform
)
10763 if (prop_flags_1
->insn
.is_no_reorder
!=
10764 prop_flags_2
->insn
.is_no_reorder
)
10766 if (prop_flags_1
->insn
.is_abslit
!=
10767 prop_flags_2
->insn
.is_abslit
)
10771 if (prop_flags_1
->is_align
)
10779 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
10782 unsigned align_bits
;
10784 if (!xt_block
->flags
.is_align
)
10785 return xt_block
->size
;
10787 end_addr
= xt_block
->offset
+ xt_block
->size
;
10788 align_bits
= xt_block
->flags
.alignment
;
10789 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
10790 return end_addr
- xt_block
->offset
;
10795 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
10796 const xtensa_block_info
*xt_block_2
)
10798 if (xt_block
->sec
!= xt_block_2
->sec
)
10800 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
10801 != xt_block_2
->offset
)
10804 if (xt_block_2
->size
== 0
10805 && (!xt_block_2
->flags
.is_unreachable
10806 || xt_block
->flags
.is_unreachable
))
10808 if (xt_block_2
->flags
.is_align
10809 && xt_block
->flags
.is_align
)
10811 /* Nothing needed. */
10812 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
10817 if (xt_block_2
->flags
.is_align
)
10819 /* Push alignment to previous entry. */
10820 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
10821 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10826 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
10827 &xt_block_2
->flags
))
10830 xt_block
->size
+= xt_block_2
->size
;
10832 if (xt_block_2
->flags
.is_align
)
10834 xt_block
->flags
.is_align
= TRUE
;
10835 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10843 add_xt_prop_frags (segT sec
,
10845 xtensa_block_info
**xt_block
,
10846 frag_flags_fn property_function
)
10848 segment_info_type
*seg_info
;
10849 segment_info_type
*xt_seg_info
;
10850 bfd_vma seg_offset
;
10853 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
10854 seg_info
= retrieve_segment_info (sec
);
10855 /* Build it if needed. */
10856 while (*xt_block
!= NULL
)
10858 xt_block
= &(*xt_block
)->next
;
10860 /* We are either at NULL at the beginning or at the end. */
10862 /* Walk through the frags. */
10865 if (seg_info
->frchainP
)
10867 for (fragP
= seg_info
->frchainP
->frch_root
; fragP
;
10868 fragP
= fragP
->fr_next
)
10870 xtensa_block_info tmp_block
;
10871 tmp_block
.sec
= sec
;
10872 tmp_block
.offset
= fragP
->fr_address
;
10873 tmp_block
.size
= fragP
->fr_fix
;
10874 tmp_block
.next
= NULL
;
10875 property_function (fragP
, &tmp_block
.flags
);
10877 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
10878 /* && fragP->fr_fix != 0) */
10880 if ((*xt_block
) == NULL
10881 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
10883 xtensa_block_info
*new_block
;
10884 if ((*xt_block
) != NULL
)
10885 xt_block
= &(*xt_block
)->next
;
10886 new_block
= (xtensa_block_info
*)
10887 xmalloc (sizeof (xtensa_block_info
));
10888 *new_block
= tmp_block
;
10889 *xt_block
= new_block
;
10897 /* op_placement_info_table */
10899 /* op_placement_info makes it easier to determine which
10900 ops can go in which slots. */
10903 init_op_placement_info_table (void)
10905 xtensa_isa isa
= xtensa_default_isa
;
10906 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
10907 xtensa_opcode opcode
;
10910 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
10912 op_placement_table
= (op_placement_info_table
)
10913 xmalloc (sizeof (op_placement_info
) * num_opcodes
);
10914 assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
10916 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
10918 op_placement_info
*opi
= &op_placement_table
[opcode
];
10919 /* FIXME: Make tinsn allocation dynamic. */
10920 if (xtensa_opcode_num_operands (isa
, opcode
) >= MAX_INSN_ARGS
)
10921 as_fatal (_("too many operands in instruction"));
10922 opi
->narrowest
= XTENSA_UNDEFINED
;
10923 opi
->narrowest_size
= 0x7F;
10924 opi
->narrowest_slot
= 0;
10926 opi
->num_formats
= 0;
10928 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
10930 opi
->slots
[fmt
] = 0;
10931 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
10933 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
10935 int fmt_length
= xtensa_format_length (isa
, fmt
);
10937 set_bit (fmt
, opi
->formats
);
10938 set_bit (slot
, opi
->slots
[fmt
]);
10939 if (fmt_length
< opi
->narrowest_size
10940 || (fmt_length
== opi
->narrowest_size
10941 && (xtensa_format_num_slots (isa
, fmt
)
10942 < xtensa_format_num_slots (isa
,
10945 opi
->narrowest
= fmt
;
10946 opi
->narrowest_size
= fmt_length
;
10947 opi
->narrowest_slot
= slot
;
10952 opi
->num_formats
++;
10955 xtensa_insnbuf_free (isa
, ibuf
);
10960 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
10962 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
10966 /* If the opcode is available in a single slot format, return its size. */
10969 xg_get_single_size (xtensa_opcode opcode
)
10971 return op_placement_table
[opcode
].narrowest_size
;
10975 static xtensa_format
10976 xg_get_single_format (xtensa_opcode opcode
)
10978 return op_placement_table
[opcode
].narrowest
;
10983 xg_get_single_slot (xtensa_opcode opcode
)
10985 return op_placement_table
[opcode
].narrowest_slot
;
10989 /* Instruction Stack Functions (from "xtensa-istack.h"). */
10992 istack_init (IStack
*stack
)
10994 memset (stack
, 0, sizeof (IStack
));
11000 istack_empty (IStack
*stack
)
11002 return (stack
->ninsn
== 0);
11007 istack_full (IStack
*stack
)
11009 return (stack
->ninsn
== MAX_ISTACK
);
11013 /* Return a pointer to the top IStack entry.
11014 It is an error to call this if istack_empty () is TRUE. */
11017 istack_top (IStack
*stack
)
11019 int rec
= stack
->ninsn
- 1;
11020 assert (!istack_empty (stack
));
11021 return &stack
->insn
[rec
];
11025 /* Add a new TInsn to an IStack.
11026 It is an error to call this if istack_full () is TRUE. */
11029 istack_push (IStack
*stack
, TInsn
*insn
)
11031 int rec
= stack
->ninsn
;
11032 assert (!istack_full (stack
));
11033 stack
->insn
[rec
] = *insn
;
11038 /* Clear space for the next TInsn on the IStack and return a pointer
11039 to it. It is an error to call this if istack_full () is TRUE. */
11042 istack_push_space (IStack
*stack
)
11044 int rec
= stack
->ninsn
;
11046 assert (!istack_full (stack
));
11047 insn
= &stack
->insn
[rec
];
11054 /* Remove the last pushed instruction. It is an error to call this if
11055 istack_empty () returns TRUE. */
11058 istack_pop (IStack
*stack
)
11060 int rec
= stack
->ninsn
- 1;
11061 assert (!istack_empty (stack
));
11063 tinsn_init (&stack
->insn
[rec
]);
11067 /* TInsn functions. */
11070 tinsn_init (TInsn
*dst
)
11072 memset (dst
, 0, sizeof (TInsn
));
11076 /* Return TRUE if ANY of the operands in the insn are symbolic. */
11079 tinsn_has_symbolic_operands (const TInsn
*insn
)
11082 int n
= insn
->ntok
;
11084 assert (insn
->insn_type
== ITYPE_INSN
);
11086 for (i
= 0; i
< n
; ++i
)
11088 switch (insn
->tok
[i
].X_op
)
11102 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
11104 xtensa_isa isa
= xtensa_default_isa
;
11106 int n
= insn
->ntok
;
11108 assert (insn
->insn_type
== ITYPE_INSN
);
11110 for (i
= 0; i
< n
; ++i
)
11112 switch (insn
->tok
[i
].X_op
)
11120 /* Errors for these types are caught later. */
11125 /* Symbolic immediates are only allowed on the last immediate
11126 operand. At this time, CONST16 is the only opcode where we
11127 support non-PC-relative relocations. */
11128 if (i
!= get_relaxable_immed (insn
->opcode
)
11129 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
11130 && insn
->opcode
!= xtensa_const16_opcode
))
11132 as_bad (_("invalid symbolic operand"));
11141 /* For assembly code with complex expressions (e.g. subtraction),
11142 we have to build them in the literal pool so that
11143 their results are calculated correctly after relaxation.
11144 The relaxation only handles expressions that
11145 boil down to SYMBOL + OFFSET. */
11148 tinsn_has_complex_operands (const TInsn
*insn
)
11151 int n
= insn
->ntok
;
11152 assert (insn
->insn_type
== ITYPE_INSN
);
11153 for (i
= 0; i
< n
; ++i
)
11155 switch (insn
->tok
[i
].X_op
)
11171 /* Encode a TInsn opcode and its constant operands into slotbuf.
11172 Return TRUE if there is a symbol in the immediate field. This
11173 function assumes that:
11174 1) The number of operands are correct.
11175 2) The insn_type is ITYPE_INSN.
11176 3) The opcode can be encoded in the specified format and slot.
11177 4) Operands are either O_constant or O_symbol, and all constants fit. */
11180 tinsn_to_slotbuf (xtensa_format fmt
,
11183 xtensa_insnbuf slotbuf
)
11185 xtensa_isa isa
= xtensa_default_isa
;
11186 xtensa_opcode opcode
= tinsn
->opcode
;
11187 bfd_boolean has_fixup
= FALSE
;
11188 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11191 assert (tinsn
->insn_type
== ITYPE_INSN
);
11192 if (noperands
!= tinsn
->ntok
)
11193 as_fatal (_("operand number mismatch"));
11195 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
11197 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
11198 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
11202 for (i
= 0; i
< noperands
; i
++)
11204 expressionS
*expr
= &tinsn
->tok
[i
];
11210 switch (expr
->X_op
)
11213 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11215 /* The register number has already been checked in
11216 expression_maybe_register, so we don't need to check here. */
11217 opnd_value
= expr
->X_add_number
;
11218 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11219 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
11222 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
11226 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11228 as_where (&file_name
, &line
);
11229 /* It is a constant and we called this function
11230 then we have to try to fit it. */
11231 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
11232 expr
->X_add_number
, file_name
, line
);
11245 /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded
11246 into a multi-slot instruction, fill the other slots with NOPs.
11247 Return TRUE if there is a symbol in the immediate field. See also the
11248 assumptions listed for tinsn_to_slotbuf. */
11251 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
11253 static xtensa_insnbuf slotbuf
= 0;
11254 static vliw_insn vinsn
;
11255 xtensa_isa isa
= xtensa_default_isa
;
11256 bfd_boolean has_fixup
= FALSE
;
11261 slotbuf
= xtensa_insnbuf_alloc (isa
);
11262 xg_init_vinsn (&vinsn
);
11265 xg_clear_vinsn (&vinsn
);
11267 bundle_tinsn (tinsn
, &vinsn
);
11269 xtensa_format_encode (isa
, vinsn
.format
, insnbuf
);
11271 for (i
= 0; i
< vinsn
.num_slots
; i
++)
11273 /* Only one slot may have a fix-up because the rest contains NOPs. */
11275 tinsn_to_slotbuf (vinsn
.format
, i
, &vinsn
.slots
[i
], vinsn
.slotbuf
[i
]);
11276 xtensa_format_set_slot (isa
, vinsn
.format
, i
, insnbuf
, vinsn
.slotbuf
[i
]);
11283 /* Check the instruction arguments. Return TRUE on failure. */
11286 tinsn_check_arguments (const TInsn
*insn
)
11288 xtensa_isa isa
= xtensa_default_isa
;
11289 xtensa_opcode opcode
= insn
->opcode
;
11291 if (opcode
== XTENSA_UNDEFINED
)
11293 as_bad (_("invalid opcode"));
11297 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
11299 as_bad (_("too few operands"));
11303 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
11305 as_bad (_("too many operands"));
11312 /* Load an instruction from its encoded form. */
11315 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
11319 xg_init_vinsn (&vinsn
);
11320 vinsn_from_chars (&vinsn
, f
);
11322 *tinsn
= vinsn
.slots
[slot
];
11323 xg_free_vinsn (&vinsn
);
11328 tinsn_from_insnbuf (TInsn
*tinsn
,
11329 xtensa_insnbuf slotbuf
,
11334 xtensa_isa isa
= xtensa_default_isa
;
11336 /* Find the immed. */
11337 tinsn_init (tinsn
);
11338 tinsn
->insn_type
= ITYPE_INSN
;
11339 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
11340 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
11341 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
11342 for (i
= 0; i
< tinsn
->ntok
; i
++)
11344 set_expr_const (&tinsn
->tok
[i
],
11345 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
11346 tinsn
->opcode
, i
));
11351 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
11354 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
11356 xtensa_opcode opcode
= tinsn
->opcode
;
11359 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
11361 opnum
= get_relaxable_immed (opcode
);
11362 assert (opnum
>= 0);
11363 set_expr_symbol_offset (&tinsn
->tok
[opnum
],
11364 fragP
->tc_frag_data
.slot_symbols
[slot
],
11365 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11371 get_num_stack_text_bytes (IStack
*istack
)
11374 int text_bytes
= 0;
11376 for (i
= 0; i
< istack
->ninsn
; i
++)
11378 TInsn
*tinsn
= &istack
->insn
[i
];
11379 if (tinsn
->insn_type
== ITYPE_INSN
)
11380 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
11387 get_num_stack_literal_bytes (IStack
*istack
)
11392 for (i
= 0; i
< istack
->ninsn
; i
++)
11394 TInsn
*tinsn
= &istack
->insn
[i
];
11395 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
11402 /* vliw_insn functions. */
11405 xg_init_vinsn (vliw_insn
*v
)
11408 xtensa_isa isa
= xtensa_default_isa
;
11410 xg_clear_vinsn (v
);
11412 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
11413 if (v
->insnbuf
== NULL
)
11414 as_fatal (_("out of memory"));
11416 for (i
= 0; i
< MAX_SLOTS
; i
++)
11418 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
11419 if (v
->slotbuf
[i
] == NULL
)
11420 as_fatal (_("out of memory"));
11426 xg_clear_vinsn (vliw_insn
*v
)
11430 memset (v
, 0, offsetof (vliw_insn
, insnbuf
));
11432 v
->format
= XTENSA_UNDEFINED
;
11434 v
->inside_bundle
= FALSE
;
11436 if (xt_saved_debug_type
!= DEBUG_NONE
)
11437 debug_type
= xt_saved_debug_type
;
11439 for (i
= 0; i
< MAX_SLOTS
; i
++)
11440 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
11445 vinsn_has_specific_opcodes (vliw_insn
*v
)
11449 for (i
= 0; i
< v
->num_slots
; i
++)
11451 if (v
->slots
[i
].is_specific_opcode
)
11459 xg_free_vinsn (vliw_insn
*v
)
11462 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
11463 for (i
= 0; i
< MAX_SLOTS
; i
++)
11464 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
11468 /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic
11469 operands. See also the assumptions listed for tinsn_to_slotbuf. */
11472 vinsn_to_insnbuf (vliw_insn
*vinsn
,
11475 bfd_boolean record_fixup
)
11477 xtensa_isa isa
= xtensa_default_isa
;
11478 xtensa_format fmt
= vinsn
->format
;
11479 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
11481 bfd_boolean has_fixup
= FALSE
;
11483 xtensa_format_encode (isa
, fmt
, insnbuf
);
11485 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
11487 TInsn
*tinsn
= &vinsn
->slots
[slot
];
11488 bfd_boolean tinsn_has_fixup
=
11489 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
11490 vinsn
->slotbuf
[slot
]);
11492 xtensa_format_set_slot (isa
, fmt
, slot
,
11493 insnbuf
, vinsn
->slotbuf
[slot
]);
11494 if (tinsn_has_fixup
)
11497 xtensa_opcode opcode
= tinsn
->opcode
;
11498 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11501 for (i
= 0; i
< noperands
; i
++)
11503 expressionS
* expr
= &tinsn
->tok
[i
];
11504 switch (expr
->X_op
)
11509 if (get_relaxable_immed (opcode
) == i
)
11511 /* Add a fix record for the instruction, except if this
11512 function is being called prior to relaxation, i.e.,
11513 if record_fixup is false, and the instruction might
11514 be relaxed later. */
11516 || tinsn
->is_specific_opcode
11517 || !xg_is_relaxable_insn (tinsn
, 0))
11519 xg_add_opcode_fix (tinsn
, i
, fmt
, slot
, expr
, fragP
,
11520 frag_offset
- fragP
->fr_literal
);
11524 if (expr
->X_op
!= O_symbol
)
11525 as_bad (_("invalid operand"));
11526 tinsn
->symbol
= expr
->X_add_symbol
;
11527 tinsn
->offset
= expr
->X_add_number
;
11531 as_bad (_("symbolic operand not allowed"));
11539 as_bad (_("expression too complex"));
11551 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
11553 static xtensa_insnbuf insnbuf
= NULL
;
11554 static xtensa_insnbuf slotbuf
= NULL
;
11557 xtensa_isa isa
= xtensa_default_isa
;
11561 insnbuf
= xtensa_insnbuf_alloc (isa
);
11562 slotbuf
= xtensa_insnbuf_alloc (isa
);
11565 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) f
, 0);
11566 fmt
= xtensa_format_decode (isa
, insnbuf
);
11567 if (fmt
== XTENSA_UNDEFINED
)
11568 as_fatal (_("cannot decode instruction format"));
11569 vinsn
->format
= fmt
;
11570 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
11572 for (i
= 0; i
< vinsn
->num_slots
; i
++)
11574 TInsn
*tinsn
= &vinsn
->slots
[i
];
11575 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
11576 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
11581 /* Expression utilities. */
11583 /* Return TRUE if the expression is an integer constant. */
11586 expr_is_const (const expressionS
*s
)
11588 return (s
->X_op
== O_constant
);
11592 /* Get the expression constant.
11593 Calling this is illegal if expr_is_const () returns TRUE. */
11596 get_expr_const (const expressionS
*s
)
11598 assert (expr_is_const (s
));
11599 return s
->X_add_number
;
11603 /* Set the expression to a constant value. */
11606 set_expr_const (expressionS
*s
, offsetT val
)
11608 s
->X_op
= O_constant
;
11609 s
->X_add_number
= val
;
11610 s
->X_add_symbol
= NULL
;
11611 s
->X_op_symbol
= NULL
;
11616 expr_is_register (const expressionS
*s
)
11618 return (s
->X_op
== O_register
);
11622 /* Get the expression constant.
11623 Calling this is illegal if expr_is_const () returns TRUE. */
11626 get_expr_register (const expressionS
*s
)
11628 assert (expr_is_register (s
));
11629 return s
->X_add_number
;
11633 /* Set the expression to a symbol + constant offset. */
11636 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
11638 s
->X_op
= O_symbol
;
11639 s
->X_add_symbol
= sym
;
11640 s
->X_op_symbol
= NULL
; /* unused */
11641 s
->X_add_number
= offset
;
11645 /* Return TRUE if the two expressions are equal. */
11648 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
11650 if (s1
->X_op
!= s2
->X_op
)
11652 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
11654 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
11656 if (s1
->X_add_number
!= s2
->X_add_number
)
11663 copy_expr (expressionS
*dst
, const expressionS
*src
)
11665 memcpy (dst
, src
, sizeof (expressionS
));
11669 /* Support for the "--rename-section" option. */
11671 struct rename_section_struct
11675 struct rename_section_struct
*next
;
11678 static struct rename_section_struct
*section_rename
;
11681 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
11682 entries to the section_rename list. Note: Specifying multiple
11683 renamings separated by colons is not documented and is retained only
11684 for backward compatibility. */
11687 build_section_rename (const char *arg
)
11689 struct rename_section_struct
*r
;
11690 char *this_arg
= NULL
;
11691 char *next_arg
= NULL
;
11693 for (this_arg
= xstrdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
11695 char *old_name
, *new_name
;
11699 next_arg
= strchr (this_arg
, ':');
11707 old_name
= this_arg
;
11708 new_name
= strchr (this_arg
, '=');
11710 if (*old_name
== '\0')
11712 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
11715 if (!new_name
|| new_name
[1] == '\0')
11717 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
11724 /* Check for invalid section renaming. */
11725 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11727 if (strcmp (r
->old_name
, old_name
) == 0)
11728 as_bad (_("section %s renamed multiple times"), old_name
);
11729 if (strcmp (r
->new_name
, new_name
) == 0)
11730 as_bad (_("multiple sections remapped to output section %s"),
11735 r
= (struct rename_section_struct
*)
11736 xmalloc (sizeof (struct rename_section_struct
));
11737 r
->old_name
= xstrdup (old_name
);
11738 r
->new_name
= xstrdup (new_name
);
11739 r
->next
= section_rename
;
11740 section_rename
= r
;
11746 xtensa_section_rename (char *name
)
11748 struct rename_section_struct
*r
= section_rename
;
11750 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11752 if (strcmp (r
->old_name
, name
) == 0)
11753 return r
->new_name
;