1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
24 #include "safe-ctype.h"
25 #include "tc-xtensa.h"
27 #include "xtensa-relax.h"
28 #include "xtensa-istack.h"
29 #include "dwarf2dbg.h"
30 #include "struc-symbol.h"
31 #include "xtensa-config.h"
33 /* Provide default values for new configuration settings. */
39 #define uint32 unsigned int
42 #define int32 signed int
47 Naming conventions (used somewhat inconsistently):
48 The xtensa_ functions are exported
49 The xg_ functions are internal
51 We also have a couple of different extensibility mechanisms.
52 1) The idiom replacement:
53 This is used when a line is first parsed to
54 replace an instruction pattern with another instruction
55 It is currently limited to replacements of instructions
56 with constant operands.
57 2) The xtensa-relax.c mechanism that has stronger instruction
58 replacement patterns. When an instruction's immediate field
59 does not fit the next instruction sequence is attempted.
60 In addition, "narrow" opcodes are supported this way. */
63 /* Define characters with special meanings to GAS. */
64 const char comment_chars
[] = "#";
65 const char line_comment_chars
[] = "#";
66 const char line_separator_chars
[] = ";";
67 const char EXP_CHARS
[] = "eE";
68 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
71 /* Flags to indicate whether the hardware supports the density and
72 absolute literals options. */
74 bfd_boolean density_supported
= XCHAL_HAVE_DENSITY
;
75 bfd_boolean absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
77 /* Maximum width we would pad an unreachable frag to get alignment. */
78 #define UNREACHABLE_MAX_WIDTH 8
80 static vliw_insn cur_vinsn
;
82 unsigned xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
84 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
86 /* Some functions are only valid in the front end. This variable
87 allows us to assert that we haven't crossed over into the
89 static bfd_boolean past_xtensa_end
= FALSE
;
91 /* Flags for properties of the last instruction in a segment. */
92 #define FLAG_IS_A0_WRITER 0x1
93 #define FLAG_IS_BAD_LOOPEND 0x2
96 /* We define a special segment names ".literal" to place literals
97 into. The .fini and .init sections are special because they
98 contain code that is moved together by the linker. We give them
99 their own special .fini.literal and .init.literal sections. */
101 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
102 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
103 #define INIT_SECTION_NAME xtensa_section_rename (".init")
104 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
107 /* This type is used for the directive_stack to keep track of the
108 state of the literal collection pools. If lit_prefix is set, it is
109 used to determine the literal section names; otherwise, the literal
110 sections are determined based on the current text section. The
111 lit_seg and lit4_seg fields cache these literal sections, with the
112 current_text_seg field used a tag to indicate whether the cached
115 typedef struct lit_state_struct
118 segT current_text_seg
;
123 static lit_state default_lit_sections
;
126 /* We keep a list of literal segments. The seg_list type is the node
127 for this list. The literal_head pointer is the head of the list,
128 with the literal_head_h dummy node at the start. */
130 typedef struct seg_list_struct
132 struct seg_list_struct
*next
;
136 static seg_list literal_head_h
;
137 static seg_list
*literal_head
= &literal_head_h
;
140 /* Lists of symbols. We keep a list of symbols that label the current
141 instruction, so that we can adjust the symbols when inserting alignment
142 for various instructions. We also keep a list of all the symbols on
143 literals, so that we can fix up those symbols when the literals are
144 later moved into the text sections. */
146 typedef struct sym_list_struct
148 struct sym_list_struct
*next
;
152 static sym_list
*insn_labels
= NULL
;
153 static sym_list
*free_insn_labels
= NULL
;
154 static sym_list
*saved_insn_labels
= NULL
;
156 static sym_list
*literal_syms
;
159 /* Flags to determine whether to prefer const16 or l32r
160 if both options are available. */
161 int prefer_const16
= 0;
164 /* Global flag to indicate when we are emitting literals. */
165 int generating_literals
= 0;
167 /* The following PROPERTY table definitions are copied from
168 <elf/xtensa.h> and must be kept in sync with the code there. */
170 /* Flags in the property tables to specify whether blocks of memory
171 are literals, instructions, data, or unreachable. For
172 instructions, blocks that begin loop targets and branch targets are
173 designated. Blocks that do not allow density, instruction
174 reordering or transformation are also specified. Finally, for
175 branch targets, branch target alignment priority is included.
176 Alignment of the next block is specified in the current block
177 and the size of the current block does not include any fill required
178 to align to the next block. */
180 #define XTENSA_PROP_LITERAL 0x00000001
181 #define XTENSA_PROP_INSN 0x00000002
182 #define XTENSA_PROP_DATA 0x00000004
183 #define XTENSA_PROP_UNREACHABLE 0x00000008
184 /* Instruction only properties at beginning of code. */
185 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
186 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
187 /* Instruction only properties about code. */
188 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
189 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
190 /* Historically, NO_TRANSFORM was a property of instructions,
191 but it should apply to literals under certain circumstances. */
192 #define XTENSA_PROP_NO_TRANSFORM 0x00000100
194 /* Branch target alignment information. This transmits information
195 to the linker optimization about the priority of aligning a
196 particular block for branch target alignment: None, low priority,
197 high priority, or required. These only need to be checked in
198 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
201 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
202 case XTENSA_PROP_BT_ALIGN_NONE:
203 case XTENSA_PROP_BT_ALIGN_LOW:
204 case XTENSA_PROP_BT_ALIGN_HIGH:
205 case XTENSA_PROP_BT_ALIGN_REQUIRE:
207 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
209 /* No branch target alignment. */
210 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
211 /* Low priority branch target alignment. */
212 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
213 /* High priority branch target alignment. */
214 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
215 /* Required branch target alignment. */
216 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
218 #define GET_XTENSA_PROP_BT_ALIGN(flag) \
219 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
220 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
221 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
222 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
225 /* Alignment is specified in the block BEFORE the one that needs
226 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
227 get the required alignment specified as a power of 2. Use
228 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
229 alignment. Be careful of side effects since the SET will evaluate
230 flags twice. Also, note that the SIZE of a block in the property
231 table does not include the alignment size, so the alignment fill
232 must be calculated to determine if two blocks are contiguous.
233 TEXT_ALIGN is not currently implemented but is a placeholder for a
234 possible future implementation. */
236 #define XTENSA_PROP_ALIGN 0x00000800
238 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
240 #define GET_XTENSA_PROP_ALIGNMENT(flag) \
241 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
242 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
243 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
244 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
246 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
249 /* Structure for saving instruction and alignment per-fragment data
250 that will be written to the object file. This structure is
251 equivalent to the actual data that will be written out to the file
252 but is easier to use. We provide a conversion to file flags
253 in frag_flags_to_number. */
255 typedef struct frag_flags_struct frag_flags
;
257 struct frag_flags_struct
259 /* is_literal should only be used after xtensa_move_literals.
260 If you need to check if you are generating a literal fragment,
261 then use the generating_literals global. */
263 unsigned is_literal
: 1;
264 unsigned is_insn
: 1;
265 unsigned is_data
: 1;
266 unsigned is_unreachable
: 1;
268 /* is_specific_opcode implies no_transform. */
269 unsigned is_no_transform
: 1;
273 unsigned is_loop_target
: 1;
274 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
275 unsigned bt_align_priority
: 2;
277 unsigned is_no_density
: 1;
278 /* no_longcalls flag does not need to be placed in the object file. */
280 unsigned is_no_reorder
: 1;
282 /* Uses absolute literal addressing for l32r. */
283 unsigned is_abslit
: 1;
285 unsigned is_align
: 1;
286 unsigned alignment
: 5;
290 /* Structure for saving information about a block of property data
291 for frags that have the same flags. */
292 struct xtensa_block_info_struct
298 struct xtensa_block_info_struct
*next
;
302 /* Structure for saving the current state before emitting literals. */
303 typedef struct emit_state_struct
308 int generating_literals
;
312 /* Opcode placement information */
314 typedef unsigned long long bitfield
;
315 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
316 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
317 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
319 #define MAX_FORMATS 32
321 typedef struct op_placement_info_struct
324 /* A number describing how restrictive the issue is for this
325 opcode. For example, an opcode that fits lots of different
326 formats has a high freedom, as does an opcode that fits
327 only one format but many slots in that format. The most
328 restrictive is the opcode that fits only one slot in one
331 xtensa_format narrowest
;
335 /* formats is a bitfield with the Nth bit set
336 if the opcode fits in the Nth xtensa_format. */
339 /* slots[N]'s Mth bit is set if the op fits in the
340 Mth slot of the Nth xtensa_format. */
341 bitfield slots
[MAX_FORMATS
];
343 /* A count of the number of slots in a given format
344 an op can fit (i.e., the bitcount of the slot field above). */
345 char slots_in_format
[MAX_FORMATS
];
347 } op_placement_info
, *op_placement_info_table
;
349 op_placement_info_table op_placement_table
;
352 /* Extra expression types. */
354 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
355 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
356 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
358 struct suffix_reloc_map
362 bfd_reloc_code_real_type reloc
;
363 unsigned char operator;
366 #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op }
368 static struct suffix_reloc_map suffix_relocs
[] =
370 SUFFIX_MAP ("l", BFD_RELOC_LO16
, O_lo16
),
371 SUFFIX_MAP ("h", BFD_RELOC_HI16
, O_hi16
),
372 SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT
, O_pltrel
),
373 { (char *) 0, 0, BFD_RELOC_UNUSED
, 0 }
387 directive_literal_prefix
,
389 directive_absolute_literals
,
390 directive_last_directive
396 bfd_boolean can_be_negated
;
399 const directive_infoS directive_info
[] =
402 { "literal", FALSE
},
404 { "transform", TRUE
},
405 { "freeregs", FALSE
},
406 { "longcalls", TRUE
},
407 { "literal_prefix", FALSE
},
408 { "schedule", TRUE
},
409 { "absolute-literals", TRUE
}
412 bfd_boolean directive_state
[] =
416 #if !XCHAL_HAVE_DENSITY
421 TRUE
, /* transform */
422 FALSE
, /* freeregs */
423 FALSE
, /* longcalls */
424 FALSE
, /* literal_prefix */
425 FALSE
, /* schedule */
426 #if XSHAL_USE_ABSOLUTE_LITERALS
427 TRUE
/* absolute_literals */
429 FALSE
/* absolute_literals */
434 /* Directive functions. */
436 static void xtensa_begin_directive (int);
437 static void xtensa_end_directive (int);
438 static void xtensa_literal_prefix (void);
439 static void xtensa_literal_position (int);
440 static void xtensa_literal_pseudo (int);
441 static void xtensa_frequency_pseudo (int);
442 static void xtensa_elf_cons (int);
444 /* Parsing and Idiom Translation. */
446 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
448 /* Various Other Internal Functions. */
450 extern bfd_boolean
xg_is_single_relaxable_insn (TInsn
*, TInsn
*, bfd_boolean
);
451 static bfd_boolean
xg_build_to_insn (TInsn
*, TInsn
*, BuildInstr
*);
452 static void xtensa_mark_literal_pool_location (void);
453 static addressT
get_expanded_loop_offset (xtensa_opcode
);
454 static fragS
*get_literal_pool_location (segT
);
455 static void set_literal_pool_location (segT
, fragS
*);
456 static void xtensa_set_frag_assembly_state (fragS
*);
457 static void finish_vinsn (vliw_insn
*);
458 static bfd_boolean
emit_single_op (TInsn
*);
459 static int total_frag_text_expansion (fragS
*);
461 /* Alignment Functions. */
463 static int get_text_align_power (unsigned);
464 static int get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
465 static int branch_align_power (segT
);
467 /* Helpers for xtensa_relax_frag(). */
469 static long relax_frag_add_nop (fragS
*);
471 /* Accessors for additional per-subsegment information. */
473 static unsigned get_last_insn_flags (segT
, subsegT
);
474 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
475 static float get_subseg_total_freq (segT
, subsegT
);
476 static float get_subseg_target_freq (segT
, subsegT
);
477 static void set_subseg_freq (segT
, subsegT
, float, float);
479 /* Segment list functions. */
481 static void xtensa_move_literals (void);
482 static void xtensa_reorder_segments (void);
483 static void xtensa_switch_to_literal_fragment (emit_state
*);
484 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
485 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
486 static void xtensa_restore_emit_state (emit_state
*);
487 static segT
cache_literal_section (bfd_boolean
);
489 /* Import from elf32-xtensa.c in BFD library. */
491 extern asection
*xtensa_get_property_section (asection
*, const char *);
493 /* op_placement_info functions. */
495 static void init_op_placement_info_table (void);
496 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
497 static int xg_get_single_size (xtensa_opcode
);
498 static xtensa_format
xg_get_single_format (xtensa_opcode
);
499 static int xg_get_single_slot (xtensa_opcode
);
501 /* TInsn and IStack functions. */
503 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
504 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
505 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
506 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
507 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
508 static void tinsn_from_chars (TInsn
*, char *, int);
509 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
510 static int get_num_stack_text_bytes (IStack
*);
511 static int get_num_stack_literal_bytes (IStack
*);
513 /* vliw_insn functions. */
515 static void xg_init_vinsn (vliw_insn
*);
516 static void xg_clear_vinsn (vliw_insn
*);
517 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
518 static void xg_free_vinsn (vliw_insn
*);
519 static bfd_boolean vinsn_to_insnbuf
520 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
521 static void vinsn_from_chars (vliw_insn
*, char *);
523 /* Expression Utilities. */
525 bfd_boolean
expr_is_const (const expressionS
*);
526 offsetT
get_expr_const (const expressionS
*);
527 void set_expr_const (expressionS
*, offsetT
);
528 bfd_boolean
expr_is_register (const expressionS
*);
529 offsetT
get_expr_register (const expressionS
*);
530 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
531 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
532 static void copy_expr (expressionS
*, const expressionS
*);
534 /* Section renaming. */
536 static void build_section_rename (const char *);
539 /* ISA imported from bfd. */
540 extern xtensa_isa xtensa_default_isa
;
542 extern int target_big_endian
;
544 static xtensa_opcode xtensa_addi_opcode
;
545 static xtensa_opcode xtensa_addmi_opcode
;
546 static xtensa_opcode xtensa_call0_opcode
;
547 static xtensa_opcode xtensa_call4_opcode
;
548 static xtensa_opcode xtensa_call8_opcode
;
549 static xtensa_opcode xtensa_call12_opcode
;
550 static xtensa_opcode xtensa_callx0_opcode
;
551 static xtensa_opcode xtensa_callx4_opcode
;
552 static xtensa_opcode xtensa_callx8_opcode
;
553 static xtensa_opcode xtensa_callx12_opcode
;
554 static xtensa_opcode xtensa_const16_opcode
;
555 static xtensa_opcode xtensa_entry_opcode
;
556 static xtensa_opcode xtensa_extui_opcode
;
557 static xtensa_opcode xtensa_movi_opcode
;
558 static xtensa_opcode xtensa_movi_n_opcode
;
559 static xtensa_opcode xtensa_isync_opcode
;
560 static xtensa_opcode xtensa_jx_opcode
;
561 static xtensa_opcode xtensa_l32r_opcode
;
562 static xtensa_opcode xtensa_loop_opcode
;
563 static xtensa_opcode xtensa_loopnez_opcode
;
564 static xtensa_opcode xtensa_loopgtz_opcode
;
565 static xtensa_opcode xtensa_nop_opcode
;
566 static xtensa_opcode xtensa_nop_n_opcode
;
567 static xtensa_opcode xtensa_or_opcode
;
568 static xtensa_opcode xtensa_ret_opcode
;
569 static xtensa_opcode xtensa_ret_n_opcode
;
570 static xtensa_opcode xtensa_retw_opcode
;
571 static xtensa_opcode xtensa_retw_n_opcode
;
572 static xtensa_opcode xtensa_rsr_lcount_opcode
;
573 static xtensa_opcode xtensa_waiti_opcode
;
576 /* Command-line Options. */
578 bfd_boolean use_literal_section
= TRUE
;
579 static bfd_boolean align_targets
= TRUE
;
580 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
581 static bfd_boolean has_a0_b_retw
= FALSE
;
582 static bfd_boolean workaround_a0_b_retw
= FALSE
;
583 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
584 static bfd_boolean workaround_short_loop
= FALSE
;
585 static bfd_boolean maybe_has_short_loop
= FALSE
;
586 static bfd_boolean workaround_close_loop_end
= FALSE
;
587 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
588 static bfd_boolean enforce_three_byte_loop_align
= FALSE
;
590 /* When workaround_short_loops is TRUE, all loops with early exits must
591 have at least 3 instructions. workaround_all_short_loops is a modifier
592 to the workaround_short_loop flag. In addition to the
593 workaround_short_loop actions, all straightline loopgtz and loopnez
594 must have at least 3 instructions. */
596 static bfd_boolean workaround_all_short_loops
= FALSE
;
600 xtensa_setup_hw_workarounds (int earliest
, int latest
)
602 if (earliest
> latest
)
603 as_fatal (_("illegal range of target hardware versions"));
605 /* Enable all workarounds for pre-T1050.0 hardware. */
606 if (earliest
< 105000 || latest
< 105000)
608 workaround_a0_b_retw
|= TRUE
;
609 workaround_b_j_loop_end
|= TRUE
;
610 workaround_short_loop
|= TRUE
;
611 workaround_close_loop_end
|= TRUE
;
612 workaround_all_short_loops
|= TRUE
;
613 enforce_three_byte_loop_align
= TRUE
;
620 option_density
= OPTION_MD_BASE
,
627 option_no_link_relax
,
635 option_text_section_literals
,
636 option_no_text_section_literals
,
638 option_absolute_literals
,
639 option_no_absolute_literals
,
641 option_align_targets
,
642 option_no_align_targets
,
644 option_warn_unaligned_targets
,
649 option_workaround_a0_b_retw
,
650 option_no_workaround_a0_b_retw
,
652 option_workaround_b_j_loop_end
,
653 option_no_workaround_b_j_loop_end
,
655 option_workaround_short_loop
,
656 option_no_workaround_short_loop
,
658 option_workaround_all_short_loops
,
659 option_no_workaround_all_short_loops
,
661 option_workaround_close_loop_end
,
662 option_no_workaround_close_loop_end
,
664 option_no_workarounds
,
666 option_rename_section_name
,
669 option_prefer_const16
,
671 option_target_hardware
674 const char *md_shortopts
= "";
676 struct option md_longopts
[] =
678 { "density", no_argument
, NULL
, option_density
},
679 { "no-density", no_argument
, NULL
, option_no_density
},
681 /* Both "relax" and "generics" are deprecated and treated as equivalent
682 to the "transform" option. */
683 { "relax", no_argument
, NULL
, option_relax
},
684 { "no-relax", no_argument
, NULL
, option_no_relax
},
685 { "generics", no_argument
, NULL
, option_generics
},
686 { "no-generics", no_argument
, NULL
, option_no_generics
},
688 { "transform", no_argument
, NULL
, option_transform
},
689 { "no-transform", no_argument
, NULL
, option_no_transform
},
690 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
691 { "no-text-section-literals", no_argument
, NULL
,
692 option_no_text_section_literals
},
693 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
694 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
695 /* This option was changed from -align-target to -target-align
696 because it conflicted with the "-al" option. */
697 { "target-align", no_argument
, NULL
, option_align_targets
},
698 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
699 { "warn-unaligned-targets", no_argument
, NULL
,
700 option_warn_unaligned_targets
},
701 { "longcalls", no_argument
, NULL
, option_longcalls
},
702 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
704 { "no-workaround-a0-b-retw", no_argument
, NULL
,
705 option_no_workaround_a0_b_retw
},
706 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
708 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
709 option_no_workaround_b_j_loop_end
},
710 { "workaround-b-j-loop-end", no_argument
, NULL
,
711 option_workaround_b_j_loop_end
},
713 { "no-workaround-short-loops", no_argument
, NULL
,
714 option_no_workaround_short_loop
},
715 { "workaround-short-loops", no_argument
, NULL
,
716 option_workaround_short_loop
},
718 { "no-workaround-all-short-loops", no_argument
, NULL
,
719 option_no_workaround_all_short_loops
},
720 { "workaround-all-short-loop", no_argument
, NULL
,
721 option_workaround_all_short_loops
},
723 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
724 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
726 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
728 { "no-workaround-close-loop-end", no_argument
, NULL
,
729 option_no_workaround_close_loop_end
},
730 { "workaround-close-loop-end", no_argument
, NULL
,
731 option_workaround_close_loop_end
},
733 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
735 { "link-relax", no_argument
, NULL
, option_link_relax
},
736 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
738 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
740 { NULL
, no_argument
, NULL
, 0 }
743 size_t md_longopts_size
= sizeof md_longopts
;
747 md_parse_option (int c
, char *arg
)
752 as_warn (_("--density option is ignored"));
754 case option_no_density
:
755 as_warn (_("--no-density option is ignored"));
757 case option_link_relax
:
760 case option_no_link_relax
:
763 case option_generics
:
764 as_warn (_("--generics is deprecated; use --transform instead"));
765 return md_parse_option (option_transform
, arg
);
766 case option_no_generics
:
767 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
768 return md_parse_option (option_no_transform
, arg
);
770 as_warn (_("--relax is deprecated; use --transform instead"));
771 return md_parse_option (option_transform
, arg
);
772 case option_no_relax
:
773 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
774 return md_parse_option (option_no_transform
, arg
);
775 case option_longcalls
:
776 directive_state
[directive_longcalls
] = TRUE
;
778 case option_no_longcalls
:
779 directive_state
[directive_longcalls
] = FALSE
;
781 case option_text_section_literals
:
782 use_literal_section
= FALSE
;
784 case option_no_text_section_literals
:
785 use_literal_section
= TRUE
;
787 case option_absolute_literals
:
788 if (!absolute_literals_supported
)
790 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
793 directive_state
[directive_absolute_literals
] = TRUE
;
795 case option_no_absolute_literals
:
796 directive_state
[directive_absolute_literals
] = FALSE
;
799 case option_workaround_a0_b_retw
:
800 workaround_a0_b_retw
= TRUE
;
802 case option_no_workaround_a0_b_retw
:
803 workaround_a0_b_retw
= FALSE
;
805 case option_workaround_b_j_loop_end
:
806 workaround_b_j_loop_end
= TRUE
;
808 case option_no_workaround_b_j_loop_end
:
809 workaround_b_j_loop_end
= FALSE
;
812 case option_workaround_short_loop
:
813 workaround_short_loop
= TRUE
;
815 case option_no_workaround_short_loop
:
816 workaround_short_loop
= FALSE
;
819 case option_workaround_all_short_loops
:
820 workaround_all_short_loops
= TRUE
;
822 case option_no_workaround_all_short_loops
:
823 workaround_all_short_loops
= FALSE
;
826 case option_workaround_close_loop_end
:
827 workaround_close_loop_end
= TRUE
;
829 case option_no_workaround_close_loop_end
:
830 workaround_close_loop_end
= FALSE
;
833 case option_no_workarounds
:
834 workaround_a0_b_retw
= FALSE
;
835 workaround_b_j_loop_end
= FALSE
;
836 workaround_short_loop
= FALSE
;
837 workaround_all_short_loops
= FALSE
;
838 workaround_close_loop_end
= FALSE
;
841 case option_align_targets
:
842 align_targets
= TRUE
;
844 case option_no_align_targets
:
845 align_targets
= FALSE
;
848 case option_warn_unaligned_targets
:
849 warn_unaligned_branch_targets
= TRUE
;
852 case option_rename_section_name
:
853 build_section_rename (arg
);
857 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
858 should be emitted or not. FIXME: Not implemented. */
861 case option_prefer_l32r
:
863 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
867 case option_prefer_const16
:
869 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
873 case option_target_hardware
:
875 int earliest
, latest
= 0;
876 if (*arg
== 0 || *arg
== '-')
877 as_fatal (_("invalid target hardware version"));
879 earliest
= strtol (arg
, &arg
, 0);
883 else if (*arg
== '-')
886 as_fatal (_("invalid target hardware version"));
887 latest
= strtol (arg
, &arg
, 0);
890 as_fatal (_("invalid target hardware version"));
892 xtensa_setup_hw_workarounds (earliest
, latest
);
896 case option_transform
:
897 /* This option has no affect other than to use the defaults,
898 which are already set. */
901 case option_no_transform
:
902 /* This option turns off all transformations of any kind.
903 However, because we want to preserve the state of other
904 directives, we only change its own field. Thus, before
905 you perform any transformation, always check if transform
906 is available. If you use the functions we provide for this
907 purpose, you will be ok. */
908 directive_state
[directive_transform
] = FALSE
;
918 md_show_usage (FILE *stream
)
922 --[no-]text-section-literals\n\
923 [Do not] put literals in the text section\n\
924 --[no-]absolute-literals\n\
925 [Do not] default to use non-PC-relative literals\n\
926 --[no-]target-align [Do not] try to align branch targets\n\
927 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
928 --[no-]transform [Do not] transform instructions\n\
929 --rename-section old=new Rename section 'old' to 'new'\n", stream
);
933 /* Functions related to the list of current label symbols. */
936 xtensa_add_insn_label (symbolS
*sym
)
940 if (!free_insn_labels
)
941 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
944 l
= free_insn_labels
;
945 free_insn_labels
= l
->next
;
949 l
->next
= insn_labels
;
955 xtensa_clear_insn_labels (void)
959 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
967 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
)
971 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
973 symbolS
*lit_sym
= lit
->sym
;
974 S_SET_VALUE (lit_sym
, new_offset
);
975 symbol_set_frag (lit_sym
, new_frag
);
980 /* Directive data and functions. */
982 typedef struct state_stackS_struct
984 directiveE directive
;
986 bfd_boolean old_state
;
990 struct state_stackS_struct
*prev
;
993 state_stackS
*directive_state_stack
;
995 const pseudo_typeS md_pseudo_table
[] =
997 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
998 { "literal_position", xtensa_literal_position
, 0 },
999 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
1000 { "long", xtensa_elf_cons
, 4 },
1001 { "word", xtensa_elf_cons
, 4 },
1002 { "short", xtensa_elf_cons
, 2 },
1003 { "begin", xtensa_begin_directive
, 0 },
1004 { "end", xtensa_end_directive
, 0 },
1005 { "literal", xtensa_literal_pseudo
, 0 },
1006 { "frequency", xtensa_frequency_pseudo
, 0 },
1012 use_transform (void)
1014 /* After md_end, you should be checking frag by frag, rather
1015 than state directives. */
1016 assert (!past_xtensa_end
);
1017 return directive_state
[directive_transform
];
1022 do_align_targets (void)
1024 /* Do not use this function after md_end; just look at align_targets
1025 instead. There is no target-align directive, so alignment is either
1026 enabled for all frags or not done at all. */
1027 assert (!past_xtensa_end
);
1028 return align_targets
&& use_transform ();
1033 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1037 state_stackS
*stack
= (state_stackS
*) xmalloc (sizeof (state_stackS
));
1039 as_where (&file
, &line
);
1041 stack
->directive
= directive
;
1042 stack
->negated
= negated
;
1043 stack
->old_state
= directive_state
[directive
];
1046 stack
->datum
= datum
;
1047 stack
->prev
= directive_state_stack
;
1048 directive_state_stack
= stack
;
1050 directive_state
[directive
] = !negated
;
1055 directive_pop (directiveE
*directive
,
1056 bfd_boolean
*negated
,
1061 state_stackS
*top
= directive_state_stack
;
1063 if (!directive_state_stack
)
1065 as_bad (_("unmatched end directive"));
1066 *directive
= directive_none
;
1070 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1071 *directive
= top
->directive
;
1072 *negated
= top
->negated
;
1075 *datum
= top
->datum
;
1076 directive_state_stack
= top
->prev
;
1082 directive_balance (void)
1084 while (directive_state_stack
)
1086 directiveE directive
;
1087 bfd_boolean negated
;
1092 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1093 as_warn_where ((char *) file
, line
,
1094 _(".begin directive with no matching .end directive"));
1100 inside_directive (directiveE dir
)
1102 state_stackS
*top
= directive_state_stack
;
1104 while (top
&& top
->directive
!= dir
)
1107 return (top
!= NULL
);
1112 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1116 char *directive_string
;
1118 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1123 input_line_pointer
+= 3;
1126 len
= strspn (input_line_pointer
,
1127 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1129 /* This code is a hack to make .begin [no-][generics|relax] exactly
1130 equivalent to .begin [no-]transform. We should remove it when
1131 we stop accepting those options. */
1133 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1135 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1136 directive_string
= "transform";
1138 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1140 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1141 directive_string
= "transform";
1144 directive_string
= input_line_pointer
;
1146 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1148 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1150 input_line_pointer
+= len
;
1151 *directive
= (directiveE
) i
;
1152 if (*negated
&& !directive_info
[i
].can_be_negated
)
1153 as_bad (_("directive %s cannot be negated"),
1154 directive_info
[i
].name
);
1159 as_bad (_("unknown directive"));
1160 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1165 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1167 directiveE directive
;
1168 bfd_boolean negated
;
1172 get_directive (&directive
, &negated
);
1173 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1175 discard_rest_of_line ();
1179 if (cur_vinsn
.inside_bundle
)
1180 as_bad (_("directives are not valid inside bundles"));
1184 case directive_literal
:
1185 if (!inside_directive (directive_literal
))
1187 /* Previous labels go with whatever follows this directive, not with
1188 the literal, so save them now. */
1189 saved_insn_labels
= insn_labels
;
1192 as_warn (_(".begin literal is deprecated; use .literal instead"));
1193 state
= (emit_state
*) xmalloc (sizeof (emit_state
));
1194 xtensa_switch_to_literal_fragment (state
);
1195 directive_push (directive_literal
, negated
, state
);
1198 case directive_literal_prefix
:
1199 /* Have to flush pending output because a movi relaxed to an l32r
1200 might produce a literal. */
1201 md_flush_pending_output ();
1202 /* Check to see if the current fragment is a literal
1203 fragment. If it is, then this operation is not allowed. */
1204 if (generating_literals
)
1206 as_bad (_("cannot set literal_prefix inside literal fragment"));
1210 /* Allocate the literal state for this section and push
1211 onto the directive stack. */
1212 ls
= xmalloc (sizeof (lit_state
));
1215 *ls
= default_lit_sections
;
1216 directive_push (directive_literal_prefix
, negated
, ls
);
1218 /* Process the new prefix. */
1219 xtensa_literal_prefix ();
1222 case directive_freeregs
:
1223 /* This information is currently unused, but we'll accept the statement
1224 and just discard the rest of the line. This won't check the syntax,
1225 but it will accept every correct freeregs directive. */
1226 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1227 directive_push (directive_freeregs
, negated
, 0);
1230 case directive_schedule
:
1231 md_flush_pending_output ();
1232 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1233 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1234 directive_push (directive_schedule
, negated
, 0);
1235 xtensa_set_frag_assembly_state (frag_now
);
1238 case directive_density
:
1239 as_warn (_(".begin [no-]density is ignored"));
1242 case directive_absolute_literals
:
1243 md_flush_pending_output ();
1244 if (!absolute_literals_supported
&& !negated
)
1246 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1249 xtensa_set_frag_assembly_state (frag_now
);
1250 directive_push (directive
, negated
, 0);
1254 md_flush_pending_output ();
1255 xtensa_set_frag_assembly_state (frag_now
);
1256 directive_push (directive
, negated
, 0);
1260 demand_empty_rest_of_line ();
1265 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1267 directiveE begin_directive
, end_directive
;
1268 bfd_boolean begin_negated
, end_negated
;
1272 emit_state
**state_ptr
;
1275 if (cur_vinsn
.inside_bundle
)
1276 as_bad (_("directives are not valid inside bundles"));
1278 get_directive (&end_directive
, &end_negated
);
1280 md_flush_pending_output ();
1282 switch (end_directive
)
1284 case (directiveE
) XTENSA_UNDEFINED
:
1285 discard_rest_of_line ();
1288 case directive_density
:
1289 as_warn (_(".end [no-]density is ignored"));
1290 demand_empty_rest_of_line ();
1293 case directive_absolute_literals
:
1294 if (!absolute_literals_supported
&& !end_negated
)
1296 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1297 demand_empty_rest_of_line ();
1306 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1307 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1308 (const void **) state_ptr
);
1310 if (begin_directive
!= directive_none
)
1312 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1314 as_bad (_("does not match begin %s%s at %s:%d"),
1315 begin_negated
? "no-" : "",
1316 directive_info
[begin_directive
].name
, file
, line
);
1320 switch (end_directive
)
1322 case directive_literal
:
1323 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1324 xtensa_restore_emit_state (state
);
1325 xtensa_set_frag_assembly_state (frag_now
);
1327 if (!inside_directive (directive_literal
))
1329 /* Restore the list of current labels. */
1330 xtensa_clear_insn_labels ();
1331 insn_labels
= saved_insn_labels
;
1335 case directive_literal_prefix
:
1336 /* Restore the default collection sections from saved state. */
1337 s
= (lit_state
*) state
;
1339 default_lit_sections
= *s
;
1341 /* Free the state storage. */
1342 free (s
->lit_prefix
);
1346 case directive_schedule
:
1347 case directive_freeregs
:
1351 xtensa_set_frag_assembly_state (frag_now
);
1357 demand_empty_rest_of_line ();
1361 /* Place an aligned literal fragment at the current location. */
1364 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1366 md_flush_pending_output ();
1368 if (inside_directive (directive_literal
))
1369 as_warn (_(".literal_position inside literal directive; ignoring"));
1370 xtensa_mark_literal_pool_location ();
1372 demand_empty_rest_of_line ();
1373 xtensa_clear_insn_labels ();
1377 /* Support .literal label, expr, ... */
1380 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1383 char *p
, *base_name
;
1387 if (inside_directive (directive_literal
))
1389 as_bad (_(".literal not allowed inside .begin literal region"));
1390 ignore_rest_of_line ();
1394 md_flush_pending_output ();
1396 /* Previous labels go with whatever follows this directive, not with
1397 the literal, so save them now. */
1398 saved_insn_labels
= insn_labels
;
1401 /* If we are using text-section literals, then this is the right value... */
1404 base_name
= input_line_pointer
;
1406 xtensa_switch_to_literal_fragment (&state
);
1408 /* ...but if we aren't using text-section-literals, then we
1409 need to put them in the section we just switched to. */
1410 if (use_literal_section
|| directive_state
[directive_absolute_literals
])
1413 /* All literals are aligned to four-byte boundaries. */
1414 frag_align (2, 0, 0);
1415 record_alignment (now_seg
, 2);
1417 c
= get_symbol_end ();
1418 /* Just after name is now '\0'. */
1419 p
= input_line_pointer
;
1423 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1425 as_bad (_("expected comma or colon after symbol name; "
1426 "rest of line ignored"));
1427 ignore_rest_of_line ();
1428 xtensa_restore_emit_state (&state
);
1436 input_line_pointer
++; /* skip ',' or ':' */
1438 xtensa_elf_cons (4);
1440 xtensa_restore_emit_state (&state
);
1442 /* Restore the list of current labels. */
1443 xtensa_clear_insn_labels ();
1444 insn_labels
= saved_insn_labels
;
1449 xtensa_literal_prefix (void)
1454 /* Parse the new prefix from the input_line_pointer. */
1456 len
= strspn (input_line_pointer
,
1457 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1458 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1460 /* Get a null-terminated copy of the name. */
1461 name
= xmalloc (len
+ 1);
1463 strncpy (name
, input_line_pointer
, len
);
1466 /* Skip the name in the input line. */
1467 input_line_pointer
+= len
;
1469 default_lit_sections
.lit_prefix
= name
;
1471 /* Clear cached literal sections, since the prefix has changed. */
1472 default_lit_sections
.lit_seg
= NULL
;
1473 default_lit_sections
.lit4_seg
= NULL
;
1477 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1480 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1482 float fall_through_f
, target_f
;
1484 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1485 if (fall_through_f
< 0)
1487 as_bad (_("fall through frequency must be greater than 0"));
1488 ignore_rest_of_line ();
1492 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1495 as_bad (_("branch target frequency must be greater than 0"));
1496 ignore_rest_of_line ();
1500 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1502 demand_empty_rest_of_line ();
1506 /* Like normal .long/.short/.word, except support @plt, etc.
1507 Clobbers input_line_pointer, checks end-of-line. */
1510 xtensa_elf_cons (int nbytes
)
1513 bfd_reloc_code_real_type reloc
;
1515 md_flush_pending_output ();
1517 if (cur_vinsn
.inside_bundle
)
1518 as_bad (_("directives are not valid inside bundles"));
1520 if (is_it_end_of_statement ())
1522 demand_empty_rest_of_line ();
1529 if (exp
.X_op
== O_symbol
1530 && *input_line_pointer
== '@'
1531 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1534 reloc_howto_type
*reloc_howto
=
1535 bfd_reloc_type_lookup (stdoutput
, reloc
);
1537 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1538 as_bad (_("unsupported relocation"));
1539 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1540 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1541 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1542 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1543 as_bad (_("opcode-specific %s relocation used outside "
1544 "an instruction"), reloc_howto
->name
);
1545 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1546 as_bad (_("%s relocations do not fit in %d bytes"),
1547 reloc_howto
->name
, nbytes
);
1550 char *p
= frag_more ((int) nbytes
);
1551 xtensa_set_frag_assembly_state (frag_now
);
1552 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1553 nbytes
, &exp
, 0, reloc
);
1557 emit_expr (&exp
, (unsigned int) nbytes
);
1559 while (*input_line_pointer
++ == ',');
1561 input_line_pointer
--; /* Put terminator back into stream. */
1562 demand_empty_rest_of_line ();
1566 /* Parsing and Idiom Translation. */
1568 /* Parse @plt, etc. and return the desired relocation. */
1569 static bfd_reloc_code_real_type
1570 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1577 struct suffix_reloc_map
*ptr
;
1580 return BFD_RELOC_NONE
;
1582 for (ch
= *str
, str2
= ident
;
1583 (str2
< ident
+ sizeof (ident
) - 1
1584 && (ISALNUM (ch
) || ch
== '@'));
1587 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1594 for (ptr
= &suffix_relocs
[0]; ptr
->length
> 0; ptr
++)
1595 if (ch
== ptr
->suffix
[0]
1596 && len
== ptr
->length
1597 && memcmp (ident
, ptr
->suffix
, ptr
->length
) == 0)
1599 /* Now check for "identifier@suffix+constant". */
1600 if (*str
== '-' || *str
== '+')
1602 char *orig_line
= input_line_pointer
;
1603 expressionS new_exp
;
1605 input_line_pointer
= str
;
1606 expression (&new_exp
);
1607 if (new_exp
.X_op
== O_constant
)
1609 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1610 str
= input_line_pointer
;
1613 if (&input_line_pointer
!= str_p
)
1614 input_line_pointer
= orig_line
;
1621 return BFD_RELOC_UNUSED
;
1625 /* Find the matching operator type. */
1626 static unsigned char
1627 map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc
)
1629 struct suffix_reloc_map
*sfx
;
1630 unsigned char operator = (unsigned char) -1;
1632 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1634 if (sfx
->reloc
== reloc
)
1636 operator = sfx
->operator;
1640 assert (operator != (unsigned char) -1);
1645 /* Find the matching reloc type. */
1646 static bfd_reloc_code_real_type
1647 map_operator_to_reloc (unsigned char operator)
1649 struct suffix_reloc_map
*sfx
;
1650 bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
1652 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1654 if (sfx
->operator == operator)
1661 if (reloc
== BFD_RELOC_UNUSED
)
1662 return BFD_RELOC_32
;
1669 expression_end (const char *name
)
1692 #define ERROR_REG_NUM ((unsigned) -1)
1695 tc_get_register (const char *prefix
)
1698 const char *next_expr
;
1699 const char *old_line_pointer
;
1702 old_line_pointer
= input_line_pointer
;
1704 if (*input_line_pointer
== '$')
1705 ++input_line_pointer
;
1707 /* Accept "sp" as a synonym for "a1". */
1708 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1709 && expression_end (input_line_pointer
+ 2))
1711 input_line_pointer
+= 2;
1712 return 1; /* AR[1] */
1715 while (*input_line_pointer
++ == *prefix
++)
1717 --input_line_pointer
;
1722 as_bad (_("bad register name: %s"), old_line_pointer
);
1723 return ERROR_REG_NUM
;
1726 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1728 as_bad (_("bad register number: %s"), input_line_pointer
);
1729 return ERROR_REG_NUM
;
1734 while (ISDIGIT ((int) *input_line_pointer
))
1735 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1737 if (!(next_expr
= expression_end (input_line_pointer
)))
1739 as_bad (_("bad register name: %s"), old_line_pointer
);
1740 return ERROR_REG_NUM
;
1743 input_line_pointer
= (char *) next_expr
;
1750 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1752 xtensa_isa isa
= xtensa_default_isa
;
1754 /* Check if this is an immediate operand. */
1755 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1757 bfd_reloc_code_real_type reloc
;
1758 segT t
= expression (tok
);
1759 if (t
== absolute_section
1760 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1762 assert (tok
->X_op
== O_constant
);
1763 tok
->X_op
= O_symbol
;
1764 tok
->X_add_symbol
= &abs_symbol
;
1767 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1768 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1771 if (reloc
== BFD_RELOC_UNUSED
)
1773 as_bad (_("unsupported relocation"));
1777 if (tok
->X_op
== O_constant
)
1781 case BFD_RELOC_LO16
:
1782 tok
->X_add_number
&= 0xffff;
1785 case BFD_RELOC_HI16
:
1786 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1793 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
1798 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1799 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1801 if (reg
!= ERROR_REG_NUM
) /* Already errored */
1804 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
1805 as_bad (_("register number out of range"));
1808 tok
->X_op
= O_register
;
1809 tok
->X_add_symbol
= 0;
1810 tok
->X_add_number
= reg
;
1815 /* Split up the arguments for an opcode or pseudo-op. */
1818 tokenize_arguments (char **args
, char *str
)
1820 char *old_input_line_pointer
;
1821 bfd_boolean saw_comma
= FALSE
;
1822 bfd_boolean saw_arg
= FALSE
;
1823 bfd_boolean saw_colon
= FALSE
;
1825 char *arg_end
, *arg
;
1828 /* Save and restore input_line_pointer around this function. */
1829 old_input_line_pointer
= input_line_pointer
;
1830 input_line_pointer
= str
;
1832 while (*input_line_pointer
)
1835 switch (*input_line_pointer
)
1842 input_line_pointer
++;
1843 if (saw_comma
|| saw_colon
|| !saw_arg
)
1849 input_line_pointer
++;
1850 if (saw_comma
|| saw_colon
|| !saw_arg
)
1856 if (!saw_comma
&& !saw_colon
&& saw_arg
)
1859 arg_end
= input_line_pointer
+ 1;
1860 while (!expression_end (arg_end
))
1863 arg_len
= arg_end
- input_line_pointer
;
1864 arg
= (char *) xmalloc ((saw_colon
? 1 : 0) + arg_len
+ 1);
1865 args
[num_args
] = arg
;
1869 strncpy (arg
, input_line_pointer
, arg_len
);
1870 arg
[arg_len
] = '\0';
1872 input_line_pointer
= arg_end
;
1882 if (saw_comma
|| saw_colon
)
1884 input_line_pointer
= old_input_line_pointer
;
1889 as_bad (_("extra comma"));
1891 as_bad (_("extra colon"));
1893 as_bad (_("missing argument"));
1895 as_bad (_("missing comma or colon"));
1896 input_line_pointer
= old_input_line_pointer
;
1901 /* Parse the arguments to an opcode. Return TRUE on error. */
1904 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
1906 expressionS
*tok
, *last_tok
;
1907 xtensa_opcode opcode
= insn
->opcode
;
1908 bfd_boolean had_error
= TRUE
;
1909 xtensa_isa isa
= xtensa_default_isa
;
1910 int n
, num_regs
= 0;
1911 int opcode_operand_count
;
1912 int opnd_cnt
, last_opnd_cnt
;
1913 unsigned int next_reg
= 0;
1914 char *old_input_line_pointer
;
1916 if (insn
->insn_type
== ITYPE_LITERAL
)
1917 opcode_operand_count
= 1;
1919 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
1922 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
1924 /* Save and restore input_line_pointer around this function. */
1925 old_input_line_pointer
= input_line_pointer
;
1931 /* Skip invisible operands. */
1932 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
1938 for (n
= 0; n
< num_args
; n
++)
1940 input_line_pointer
= arg_strings
[n
];
1941 if (*input_line_pointer
== ':')
1943 xtensa_regfile opnd_rf
;
1944 input_line_pointer
++;
1947 assert (opnd_cnt
> 0);
1949 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
1951 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
1952 as_warn (_("incorrect register number, ignoring"));
1957 if (opnd_cnt
>= opcode_operand_count
)
1959 as_warn (_("too many arguments"));
1962 assert (opnd_cnt
< MAX_INSN_ARGS
);
1964 expression_maybe_register (opcode
, opnd_cnt
, tok
);
1965 next_reg
= tok
->X_add_number
+ 1;
1967 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
1969 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
1971 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
1972 /* minus 1 because we are seeing one right now */
1978 last_opnd_cnt
= opnd_cnt
;
1985 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
1989 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
1992 insn
->ntok
= tok
- insn
->tok
;
1996 input_line_pointer
= old_input_line_pointer
;
2002 get_invisible_operands (TInsn
*insn
)
2004 xtensa_isa isa
= xtensa_default_isa
;
2005 static xtensa_insnbuf slotbuf
= NULL
;
2007 xtensa_opcode opc
= insn
->opcode
;
2008 int slot
, opnd
, fmt_found
;
2012 slotbuf
= xtensa_insnbuf_alloc (isa
);
2014 /* Find format/slot where this can be encoded. */
2017 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2019 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2021 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2027 if (fmt_found
) break;
2032 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2036 /* First encode all the visible operands
2037 (to deal with shared field operands). */
2038 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2040 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2041 && (insn
->tok
[opnd
].X_op
== O_register
2042 || insn
->tok
[opnd
].X_op
== O_constant
))
2044 val
= insn
->tok
[opnd
].X_add_number
;
2045 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2046 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2050 /* Then pull out the values for the invisible ones. */
2051 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2053 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2055 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2056 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2057 insn
->tok
[opnd
].X_add_number
= val
;
2058 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2059 insn
->tok
[opnd
].X_op
= O_register
;
2061 insn
->tok
[opnd
].X_op
= O_constant
;
2070 xg_reverse_shift_count (char **cnt_argp
)
2072 char *cnt_arg
, *new_arg
;
2073 cnt_arg
= *cnt_argp
;
2075 /* replace the argument with "31-(argument)" */
2076 new_arg
= (char *) xmalloc (strlen (cnt_arg
) + 6);
2077 sprintf (new_arg
, "31-(%s)", cnt_arg
);
2080 *cnt_argp
= new_arg
;
2084 /* If "arg" is a constant expression, return non-zero with the value
2088 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2091 char *save_ptr
= input_line_pointer
;
2093 input_line_pointer
= arg
;
2095 input_line_pointer
= save_ptr
;
2097 if (exp
.X_op
== O_constant
)
2099 *valp
= exp
.X_add_number
;
2108 xg_replace_opname (char **popname
, char *newop
)
2111 *popname
= (char *) xmalloc (strlen (newop
) + 1);
2112 strcpy (*popname
, newop
);
2117 xg_check_num_args (int *pnum_args
,
2122 int num_args
= *pnum_args
;
2124 if (num_args
< expected_num
)
2126 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2127 num_args
, opname
, expected_num
);
2131 if (num_args
> expected_num
)
2133 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2134 num_args
, opname
, expected_num
);
2135 while (num_args
-- > expected_num
)
2137 free (arg_strings
[num_args
]);
2138 arg_strings
[num_args
] = 0;
2140 *pnum_args
= expected_num
;
2148 /* If the register is not specified as part of the opcode,
2149 then get it from the operand and move it to the opcode. */
2152 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2154 xtensa_isa isa
= xtensa_default_isa
;
2156 char *opname
, *new_opname
;
2157 const char *sr_name
;
2158 int is_user
, is_write
;
2163 is_user
= (opname
[1] == 'u');
2164 is_write
= (opname
[0] == 'w');
2166 /* Opname == [rw]ur or [rwx]sr... */
2168 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2171 /* Check if the argument is a symbolic register name. */
2172 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2173 /* Handle WSR to "INTSET" as a special case. */
2174 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2175 && !strcasecmp (arg_strings
[1], "intset"))
2176 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2177 if (sr
== XTENSA_UNDEFINED
2178 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2180 /* Maybe it's a register number.... */
2182 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2184 as_bad (_("invalid register '%s' for '%s' instruction"),
2185 arg_strings
[1], opname
);
2188 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2189 if (sr
== XTENSA_UNDEFINED
)
2191 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2192 (long) val
, opname
);
2197 /* Remove the last argument, which is now part of the opcode. */
2198 free (arg_strings
[1]);
2202 /* Translate the opcode. */
2203 sr_name
= xtensa_sysreg_name (isa
, sr
);
2204 /* Another special case for "WSR.INTSET".... */
2205 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2207 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2208 sprintf (new_opname
, "%s.%s", *popname
, sr_name
);
2210 *popname
= new_opname
;
2217 xtensa_translate_old_userreg_ops (char **popname
)
2219 xtensa_isa isa
= xtensa_default_isa
;
2221 char *opname
, *new_opname
;
2222 const char *sr_name
;
2223 bfd_boolean has_underbar
= FALSE
;
2226 if (opname
[0] == '_')
2228 has_underbar
= TRUE
;
2232 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2233 if (sr
!= XTENSA_UNDEFINED
)
2235 /* The new default name ("nnn") is different from the old default
2236 name ("URnnn"). The old default is handled below, and we don't
2237 want to recognize [RW]nnn, so do nothing if the name is the (new)
2239 static char namebuf
[10];
2240 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2241 if (strcmp (namebuf
, opname
+ 1) == 0)
2249 /* Only continue if the reg name is "URnnn". */
2250 if (opname
[1] != 'u' || opname
[2] != 'r')
2252 val
= strtoul (opname
+ 3, &end
, 10);
2256 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2257 if (sr
== XTENSA_UNDEFINED
)
2259 as_bad (_("invalid register number (%ld) for '%s'"),
2260 (long) val
, opname
);
2265 /* Translate the opcode. */
2266 sr_name
= xtensa_sysreg_name (isa
, sr
);
2267 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2268 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2269 opname
[0], sr_name
);
2271 *popname
= new_opname
;
2278 xtensa_translate_zero_immed (char *old_op
,
2288 assert (opname
[0] != '_');
2290 if (strcmp (opname
, old_op
) != 0)
2293 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2295 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2297 xg_replace_opname (popname
, new_op
);
2298 free (arg_strings
[1]);
2299 arg_strings
[1] = arg_strings
[2];
2308 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2309 Returns non-zero if an error was found. */
2312 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2314 char *opname
= *popname
;
2315 bfd_boolean has_underbar
= FALSE
;
2319 has_underbar
= TRUE
;
2323 if (strcmp (opname
, "mov") == 0)
2325 if (use_transform () && !has_underbar
&& density_supported
)
2326 xg_replace_opname (popname
, "mov.n");
2329 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2331 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2332 arg_strings
[2] = (char *) xmalloc (strlen (arg_strings
[1]) + 1);
2333 strcpy (arg_strings
[2], arg_strings
[1]);
2339 if (strcmp (opname
, "bbsi.l") == 0)
2341 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2343 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2344 if (target_big_endian
)
2345 xg_reverse_shift_count (&arg_strings
[1]);
2349 if (strcmp (opname
, "bbci.l") == 0)
2351 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2353 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2354 if (target_big_endian
)
2355 xg_reverse_shift_count (&arg_strings
[1]);
2359 /* Don't do anything special with NOPs inside FLIX instructions. They
2360 are handled elsewhere. Real NOP instructions are always available
2361 in configurations with FLIX, so this should never be an issue but
2362 check for it anyway. */
2363 if (!cur_vinsn
.inside_bundle
&& xtensa_nop_opcode
== XTENSA_UNDEFINED
2364 && strcmp (opname
, "nop") == 0)
2366 if (use_transform () && !has_underbar
&& density_supported
)
2367 xg_replace_opname (popname
, "nop.n");
2370 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2372 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2373 arg_strings
[0] = (char *) xmalloc (3);
2374 arg_strings
[1] = (char *) xmalloc (3);
2375 arg_strings
[2] = (char *) xmalloc (3);
2376 strcpy (arg_strings
[0], "a1");
2377 strcpy (arg_strings
[1], "a1");
2378 strcpy (arg_strings
[2], "a1");
2384 /* Recognize [RW]UR and [RWX]SR. */
2385 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2386 && (opname
[1] == 'u' || opname
[1] == 's'))
2387 || (opname
[0] == 'x' && opname
[1] == 's'))
2389 && opname
[3] == '\0')
2390 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2392 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2393 [RW]<name> if <name> is the non-default name of a user register. */
2394 if ((opname
[0] == 'r' || opname
[0] == 'w')
2395 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2396 return xtensa_translate_old_userreg_ops (popname
);
2398 /* Relax branches that don't allow comparisons against an immediate value
2399 of zero to the corresponding branches with implicit zero immediates. */
2400 if (!has_underbar
&& use_transform ())
2402 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2403 pnum_args
, arg_strings
))
2406 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2407 pnum_args
, arg_strings
))
2410 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2411 pnum_args
, arg_strings
))
2414 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2415 pnum_args
, arg_strings
))
2423 /* Functions for dealing with the Xtensa ISA. */
2425 /* Currently the assembler only allows us to use a single target per
2426 fragment. Because of this, only one operand for a given
2427 instruction may be symbolic. If there is a PC-relative operand,
2428 the last one is chosen. Otherwise, the result is the number of the
2429 last immediate operand, and if there are none of those, we fail and
2433 get_relaxable_immed (xtensa_opcode opcode
)
2435 int last_immed
= -1;
2438 if (opcode
== XTENSA_UNDEFINED
)
2441 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2442 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2444 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2446 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2448 if (last_immed
== -1
2449 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2456 static xtensa_opcode
2457 get_opcode_from_buf (const char *buf
, int slot
)
2459 static xtensa_insnbuf insnbuf
= NULL
;
2460 static xtensa_insnbuf slotbuf
= NULL
;
2461 xtensa_isa isa
= xtensa_default_isa
;
2466 insnbuf
= xtensa_insnbuf_alloc (isa
);
2467 slotbuf
= xtensa_insnbuf_alloc (isa
);
2470 xtensa_insnbuf_from_chars (isa
, insnbuf
, (const unsigned char *) buf
, 0);
2471 fmt
= xtensa_format_decode (isa
, insnbuf
);
2472 if (fmt
== XTENSA_UNDEFINED
)
2473 return XTENSA_UNDEFINED
;
2475 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2476 return XTENSA_UNDEFINED
;
2478 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2479 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2483 #ifdef TENSILICA_DEBUG
2485 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2488 xtensa_print_insn_table (void)
2490 int num_opcodes
, num_operands
;
2491 xtensa_opcode opcode
;
2492 xtensa_isa isa
= xtensa_default_isa
;
2494 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2495 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2498 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2499 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2500 for (opn
= 0; opn
< num_operands
; opn
++)
2502 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2504 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2506 xtensa_regfile opnd_rf
=
2507 xtensa_operand_regfile (isa
, opcode
, opn
);
2508 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2510 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2511 fputs ("[lLr] ", stderr
);
2513 fputs ("i ", stderr
);
2515 fprintf (stderr
, "\n");
2521 print_vliw_insn (xtensa_insnbuf vbuf
)
2523 xtensa_isa isa
= xtensa_default_isa
;
2524 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2525 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2528 fprintf (stderr
, "format = %d\n", f
);
2530 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2532 xtensa_opcode opcode
;
2536 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2537 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2538 opname
= xtensa_opcode_name (isa
, opcode
);
2540 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2541 fprintf (stderr
, " operands = ");
2543 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2547 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2549 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2550 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2551 fprintf (stderr
, "%d ", val
);
2553 fprintf (stderr
, "\n");
2555 xtensa_insnbuf_free (isa
, sbuf
);
2558 #endif /* TENSILICA_DEBUG */
2562 is_direct_call_opcode (xtensa_opcode opcode
)
2564 xtensa_isa isa
= xtensa_default_isa
;
2565 int n
, num_operands
;
2567 if (xtensa_opcode_is_call (isa
, opcode
) != 1)
2570 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2571 for (n
= 0; n
< num_operands
; n
++)
2573 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2574 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2581 /* Convert from BFD relocation type code to slot and operand number.
2582 Returns non-zero on failure. */
2585 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2587 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2588 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2590 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2593 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2594 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2596 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2606 /* Convert from slot number to BFD relocation type code for the
2607 standard PC-relative relocations. Return BFD_RELOC_NONE on
2610 static bfd_reloc_code_real_type
2611 encode_reloc (int slot
)
2613 if (slot
< 0 || slot
> 14)
2614 return BFD_RELOC_NONE
;
2616 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2620 /* Convert from slot numbers to BFD relocation type code for the
2621 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2623 static bfd_reloc_code_real_type
2624 encode_alt_reloc (int slot
)
2626 if (slot
< 0 || slot
> 14)
2627 return BFD_RELOC_NONE
;
2629 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2634 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2637 xtensa_opcode opcode
,
2643 uint32 valbuf
= value
;
2645 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2647 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2649 as_bad_where ((char *) file
, line
,
2650 _("operand %d of '%s' has out of range value '%u'"),
2652 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2655 as_bad_where ((char *) file
, line
,
2656 _("operand %d of '%s' has invalid value '%u'"),
2658 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2663 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2669 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2672 xtensa_opcode opcode
,
2676 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2677 fmt
, slot
, slotbuf
, &val
);
2678 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2683 /* Checks for rules from xtensa-relax tables. */
2685 /* The routine xg_instruction_matches_option_term must return TRUE
2686 when a given option term is true. The meaning of all of the option
2687 terms is given interpretation by this function. This is needed when
2688 an option depends on the state of a directive, but there are no such
2689 options in use right now. */
2692 xg_instruction_matches_option_term (TInsn
*insn ATTRIBUTE_UNUSED
,
2693 const ReqOrOption
*option
)
2695 if (strcmp (option
->option_name
, "realnop") == 0
2696 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2698 /* These conditions were evaluated statically when building the
2699 relaxation table. There's no need to reevaluate them now. */
2704 as_fatal (_("internal error: unknown option name '%s'"),
2705 option
->option_name
);
2711 xg_instruction_matches_or_options (TInsn
*insn
,
2712 const ReqOrOptionList
*or_option
)
2714 const ReqOrOption
*option
;
2715 /* Must match each of the AND terms. */
2716 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2718 if (xg_instruction_matches_option_term (insn
, option
))
2726 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2728 const ReqOption
*req_options
;
2729 /* Must match each of the AND terms. */
2730 for (req_options
= options
;
2731 req_options
!= NULL
;
2732 req_options
= req_options
->next
)
2734 /* Must match one of the OR clauses. */
2735 if (!xg_instruction_matches_or_options (insn
,
2736 req_options
->or_option_terms
))
2743 /* Return the transition rule that matches or NULL if none matches. */
2746 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2748 PreconditionList
*condition_l
;
2750 if (rule
->opcode
!= insn
->opcode
)
2753 for (condition_l
= rule
->conditions
;
2754 condition_l
!= NULL
;
2755 condition_l
= condition_l
->next
)
2759 Precondition
*cond
= condition_l
->precond
;
2764 /* The expression must be the constant. */
2765 assert (cond
->op_num
< insn
->ntok
);
2766 exp1
= &insn
->tok
[cond
->op_num
];
2767 if (expr_is_const (exp1
))
2772 if (get_expr_const (exp1
) != cond
->op_data
)
2776 if (get_expr_const (exp1
) == cond
->op_data
)
2783 else if (expr_is_register (exp1
))
2788 if (get_expr_register (exp1
) != cond
->op_data
)
2792 if (get_expr_register (exp1
) == cond
->op_data
)
2804 assert (cond
->op_num
< insn
->ntok
);
2805 assert (cond
->op_data
< insn
->ntok
);
2806 exp1
= &insn
->tok
[cond
->op_num
];
2807 exp2
= &insn
->tok
[cond
->op_data
];
2812 if (!expr_is_equal (exp1
, exp2
))
2816 if (expr_is_equal (exp1
, exp2
))
2828 if (!xg_instruction_matches_options (insn
, rule
->options
))
2836 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
2838 bfd_boolean a_greater
= FALSE
;
2839 bfd_boolean b_greater
= FALSE
;
2841 ReqOptionList
*l_a
= a
->options
;
2842 ReqOptionList
*l_b
= b
->options
;
2844 /* We only care if they both are the same except for
2845 a const16 vs. an l32r. */
2847 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2849 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
2850 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
2851 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2853 if (l_or_a
->is_true
!= l_or_b
->is_true
)
2855 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
2857 /* This is the case we care about. */
2858 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
2859 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
2866 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
2867 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
2877 l_or_a
= l_or_a
->next
;
2878 l_or_b
= l_or_b
->next
;
2880 if (l_or_a
|| l_or_b
)
2889 /* Incomparable if the substitution was used differently in two cases. */
2890 if (a_greater
&& b_greater
)
2902 static TransitionRule
*
2903 xg_instruction_match (TInsn
*insn
)
2905 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
2907 assert (insn
->opcode
< table
->num_opcodes
);
2909 /* Walk through all of the possible transitions. */
2910 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2912 TransitionRule
*rule
= l
->rule
;
2913 if (xg_instruction_matches_rule (insn
, rule
))
2920 /* Various Other Internal Functions. */
2923 is_unique_insn_expansion (TransitionRule
*r
)
2925 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
2927 if (r
->to_instr
->typ
!= INSTR_INSTR
)
2933 /* Check if there is exactly one relaxation for INSN that converts it to
2934 another instruction of equal or larger size. If so, and if TARG is
2935 non-null, go ahead and generate the relaxed instruction into TARG. If
2936 NARROW_ONLY is true, then only consider relaxations that widen a narrow
2937 instruction, i.e., ignore relaxations that convert to an instruction of
2938 equal size. In some contexts where this function is used, only
2939 a single widening is allowed and the NARROW_ONLY argument is used to
2940 exclude cases like ADDI being "widened" to an ADDMI, which may
2941 later be relaxed to an ADDMI/ADDI pair. */
2944 xg_is_single_relaxable_insn (TInsn
*insn
, TInsn
*targ
, bfd_boolean narrow_only
)
2946 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
2948 TransitionRule
*match
= 0;
2950 assert (insn
->insn_type
== ITYPE_INSN
);
2951 assert (insn
->opcode
< table
->num_opcodes
);
2953 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2955 TransitionRule
*rule
= l
->rule
;
2957 if (xg_instruction_matches_rule (insn
, rule
)
2958 && is_unique_insn_expansion (rule
)
2959 && (xg_get_single_size (insn
->opcode
) + (narrow_only
? 1 : 0)
2960 <= xg_get_single_size (rule
->to_instr
->opcode
)))
2971 xg_build_to_insn (targ
, insn
, match
->to_instr
);
2976 /* Return the maximum number of bytes this opcode can expand to. */
2979 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
2981 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
2983 int max_size
= xg_get_single_size (opcode
);
2985 assert (opcode
< table
->num_opcodes
);
2987 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
2989 TransitionRule
*rule
= l
->rule
;
2990 BuildInstr
*build_list
;
2995 build_list
= rule
->to_instr
;
2996 if (is_unique_insn_expansion (rule
))
2998 assert (build_list
->typ
== INSTR_INSTR
);
2999 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
3002 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3004 switch (build_list
->typ
)
3007 this_size
+= xg_get_single_size (build_list
->opcode
);
3009 case INSTR_LITERAL_DEF
:
3010 case INSTR_LABEL_DEF
:
3015 if (this_size
> max_size
)
3016 max_size
= this_size
;
3022 /* Return the maximum number of literal bytes this opcode can generate. */
3025 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3027 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3031 assert (opcode
< table
->num_opcodes
);
3033 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3035 TransitionRule
*rule
= l
->rule
;
3036 BuildInstr
*build_list
;
3041 build_list
= rule
->to_instr
;
3042 if (is_unique_insn_expansion (rule
))
3044 assert (build_list
->typ
== INSTR_INSTR
);
3045 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3048 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3050 switch (build_list
->typ
)
3052 case INSTR_LITERAL_DEF
:
3053 /* Hard-coded 4-byte literal. */
3057 case INSTR_LABEL_DEF
:
3062 if (this_size
> max_size
)
3063 max_size
= this_size
;
3070 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3072 int steps_taken
= 0;
3073 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3076 assert (insn
->insn_type
== ITYPE_INSN
);
3077 assert (insn
->opcode
< table
->num_opcodes
);
3079 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3081 TransitionRule
*rule
= l
->rule
;
3083 if (xg_instruction_matches_rule (insn
, rule
))
3085 if (steps_taken
== lateral_steps
)
3095 get_special_literal_symbol (void)
3097 static symbolS
*sym
= NULL
;
3100 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3106 get_special_label_symbol (void)
3108 static symbolS
*sym
= NULL
;
3111 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3117 xg_valid_literal_expression (const expressionS
*exp
)
3134 /* This will check to see if the value can be converted into the
3135 operand type. It will return TRUE if it does not fit. */
3138 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3140 uint32 valbuf
= value
;
3141 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3147 /* Assumes: All immeds are constants. Check that all constants fit
3148 into their immeds; return FALSE if not. */
3151 xg_immeds_fit (const TInsn
*insn
)
3153 xtensa_isa isa
= xtensa_default_isa
;
3157 assert (insn
->insn_type
== ITYPE_INSN
);
3158 for (i
= 0; i
< n
; ++i
)
3160 const expressionS
*expr
= &insn
->tok
[i
];
3161 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3168 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3173 /* The symbol should have a fixup associated with it. */
3182 /* This should only be called after we have an initial
3183 estimate of the addresses. */
3186 xg_symbolic_immeds_fit (const TInsn
*insn
,
3192 xtensa_isa isa
= xtensa_default_isa
;
3200 assert (insn
->insn_type
== ITYPE_INSN
);
3202 for (i
= 0; i
< n
; ++i
)
3204 const expressionS
*expr
= &insn
->tok
[i
];
3205 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3212 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3218 /* Check for the worst case. */
3219 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3224 /* We only allow symbols for PC-relative references.
3225 If pc_frag == 0, then we don't have frag locations yet. */
3227 || xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0)
3230 /* If it is a weak symbol, then assume it won't reach. */
3231 if (S_IS_WEAK (expr
->X_add_symbol
))
3234 if (is_direct_call_opcode (insn
->opcode
)
3235 && ! pc_frag
->tc_frag_data
.use_longcalls
)
3237 /* If callee is undefined or in a different segment, be
3238 optimistic and assume it will be in range. */
3239 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3243 /* Only references within a segment can be known to fit in the
3244 operands at assembly time. */
3245 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3248 symbolP
= expr
->X_add_symbol
;
3249 sym_frag
= symbol_get_frag (symbolP
);
3250 target
= S_GET_VALUE (symbolP
) + expr
->X_add_number
;
3251 pc
= pc_frag
->fr_address
+ pc_offset
;
3253 /* If frag has yet to be reached on this pass, assume it
3254 will move by STRETCH just as we did. If this is not so,
3255 it will be because some frag between grows, and that will
3256 force another pass. Beware zero-length frags. There
3257 should be a faster way to do this. */
3260 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3261 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3266 new_offset
= target
;
3267 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3268 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3273 /* The symbol should have a fixup associated with it. */
3282 /* Return TRUE on success. */
3285 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3291 targ
->linenum
= insn
->linenum
;
3296 targ
->opcode
= bi
->opcode
;
3297 targ
->insn_type
= ITYPE_INSN
;
3298 targ
->is_specific_opcode
= FALSE
;
3300 for (; op
!= NULL
; op
= op
->next
)
3302 int op_num
= op
->op_num
;
3303 int op_data
= op
->op_data
;
3305 assert (op
->op_num
< MAX_INSN_ARGS
);
3307 if (targ
->ntok
<= op_num
)
3308 targ
->ntok
= op_num
+ 1;
3313 set_expr_const (&targ
->tok
[op_num
], op_data
);
3316 assert (op_data
< insn
->ntok
);
3317 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3320 sym
= get_special_literal_symbol ();
3321 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3324 sym
= get_special_label_symbol ();
3325 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3327 case OP_OPERAND_HI16U
:
3328 case OP_OPERAND_LOW16U
:
3329 assert (op_data
< insn
->ntok
);
3330 if (expr_is_const (&insn
->tok
[op_data
]))
3333 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3334 val
= xg_apply_userdef_op_fn (op
->typ
,
3337 targ
->tok
[op_num
].X_add_number
= val
;
3341 /* For const16 we can create relocations for these. */
3342 if (targ
->opcode
== XTENSA_UNDEFINED
3343 || (targ
->opcode
!= xtensa_const16_opcode
))
3345 assert (op_data
< insn
->ntok
);
3346 /* Need to build a O_lo16 or O_hi16. */
3347 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3348 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3350 if (op
->typ
== OP_OPERAND_HI16U
)
3351 targ
->tok
[op_num
].X_op
= O_hi16
;
3352 else if (op
->typ
== OP_OPERAND_LOW16U
)
3353 targ
->tok
[op_num
].X_op
= O_lo16
;
3360 /* currently handles:
3363 OP_OPERAND_F32MINUS */
3364 if (xg_has_userdef_op_fn (op
->typ
))
3366 assert (op_data
< insn
->ntok
);
3367 if (expr_is_const (&insn
->tok
[op_data
]))
3370 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3371 val
= xg_apply_userdef_op_fn (op
->typ
,
3374 targ
->tok
[op_num
].X_add_number
= val
;
3377 return FALSE
; /* We cannot use a relocation for this. */
3386 case INSTR_LITERAL_DEF
:
3388 targ
->opcode
= XTENSA_UNDEFINED
;
3389 targ
->insn_type
= ITYPE_LITERAL
;
3390 targ
->is_specific_opcode
= FALSE
;
3391 for (; op
!= NULL
; op
= op
->next
)
3393 int op_num
= op
->op_num
;
3394 int op_data
= op
->op_data
;
3395 assert (op
->op_num
< MAX_INSN_ARGS
);
3397 if (targ
->ntok
<= op_num
)
3398 targ
->ntok
= op_num
+ 1;
3403 assert (op_data
< insn
->ntok
);
3404 /* We can only pass resolvable literals through. */
3405 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3407 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3419 case INSTR_LABEL_DEF
:
3421 targ
->opcode
= XTENSA_UNDEFINED
;
3422 targ
->insn_type
= ITYPE_LABEL
;
3423 targ
->is_specific_opcode
= FALSE
;
3424 /* Literal with no ops is a label? */
3425 assert (op
== NULL
);
3436 /* Return TRUE on success. */
3439 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3441 for (; bi
!= NULL
; bi
= bi
->next
)
3443 TInsn
*next_insn
= istack_push_space (istack
);
3445 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3452 /* Return TRUE on valid expansion. */
3455 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3457 int stack_size
= istack
->ninsn
;
3458 int steps_taken
= 0;
3459 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3462 assert (insn
->insn_type
== ITYPE_INSN
);
3463 assert (insn
->opcode
< table
->num_opcodes
);
3465 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3467 TransitionRule
*rule
= l
->rule
;
3469 if (xg_instruction_matches_rule (insn
, rule
))
3471 if (lateral_steps
== steps_taken
)
3475 /* This is it. Expand the rule to the stack. */
3476 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3479 /* Check to see if it fits. */
3480 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3482 TInsn
*insn
= &istack
->insn
[i
];
3484 if (insn
->insn_type
== ITYPE_INSN
3485 && !tinsn_has_symbolic_operands (insn
)
3486 && !xg_immeds_fit (insn
))
3488 istack
->ninsn
= stack_size
;
3501 /* Relax the assembly instruction at least "min_steps".
3502 Return the number of steps taken.
3504 For relaxation to correctly terminate, every relaxation chain must
3505 terminate in one of two ways:
3507 1. If the chain from one instruction to the next consists entirely of
3508 single instructions, then the chain *must* handle all possible
3509 immediates without failing. It must not ever fail because an
3510 immediate is out of range. The MOVI.N -> MOVI -> L32R relaxation
3511 chain is one example. L32R loads 32 bits, and there cannot be an
3512 immediate larger than 32 bits, so it satisfies this condition.
3513 Single instruction relaxation chains are as defined by
3514 xg_is_single_relaxable_instruction.
3516 2. Otherwise, the chain must end in a multi-instruction expansion: e.g.,
3517 BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J
3519 Strictly speaking, in most cases you can violate condition 1 and be OK
3520 -- in particular when the last two instructions have the same single
3521 size. But nevertheless, you should guarantee the above two conditions.
3523 We could fix this so that single-instruction expansions correctly
3524 terminate when they can't handle the range, but the error messages are
3525 worse, and it actually turns out that in every case but one (18-bit wide
3526 branches), you need a multi-instruction expansion to get the full range
3527 anyway. And because 18-bit branches are handled identically to 15-bit
3528 branches, there isn't any point in changing it. */
3531 xg_assembly_relax (IStack
*istack
,
3534 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3535 offsetT pc_offset
, /* offset in fragment */
3536 int min_steps
, /* minimum conversion steps */
3537 long stretch
) /* number of bytes stretched so far */
3539 int steps_taken
= 0;
3541 /* Some of its immeds don't fit. Try to build a relaxed version.
3542 This may go through a couple of stages of single instruction
3543 transformations before we get there. */
3545 TInsn single_target
;
3547 int lateral_steps
= 0;
3548 int istack_size
= istack
->ninsn
;
3550 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3551 && steps_taken
>= min_steps
)
3553 istack_push (istack
, insn
);
3556 current_insn
= *insn
;
3558 /* Walk through all of the single instruction expansions. */
3559 while (xg_is_single_relaxable_insn (¤t_insn
, &single_target
, FALSE
))
3562 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3565 if (steps_taken
>= min_steps
)
3567 istack_push (istack
, &single_target
);
3571 current_insn
= single_target
;
3574 /* Now check for a multi-instruction expansion. */
3575 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3577 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3580 if (steps_taken
>= min_steps
)
3582 istack_push (istack
, ¤t_insn
);
3587 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3589 if (steps_taken
>= min_steps
)
3593 istack
->ninsn
= istack_size
;
3596 /* It's not going to work -- use the original. */
3597 istack_push (istack
, insn
);
3603 xg_force_frag_space (int size
)
3605 /* This may have the side effect of creating a new fragment for the
3606 space to go into. I just do not like the name of the "frag"
3613 xg_finish_frag (char *last_insn
,
3614 enum xtensa_relax_statesE frag_state
,
3615 enum xtensa_relax_statesE slot0_state
,
3617 bfd_boolean is_insn
)
3619 /* Finish off this fragment so that it has at LEAST the desired
3620 max_growth. If it doesn't fit in this fragment, close this one
3621 and start a new one. In either case, return a pointer to the
3622 beginning of the growth area. */
3626 xg_force_frag_space (max_growth
);
3628 old_frag
= frag_now
;
3630 frag_now
->fr_opcode
= last_insn
;
3632 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3634 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3635 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3637 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3638 xtensa_set_frag_assembly_state (frag_now
);
3640 /* Just to make sure that we did not split it up. */
3641 assert (old_frag
->fr_next
== frag_now
);
3645 /* Return TRUE if the target frag is one of the next non-empty frags. */
3648 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3653 for (; fragP
; fragP
= fragP
->fr_next
)
3655 if (fragP
== target
)
3657 if (fragP
->fr_fix
!= 0)
3659 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3661 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3662 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3664 if (fragP
->fr_type
== rs_space
)
3672 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3674 xtensa_isa isa
= xtensa_default_isa
;
3676 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3681 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) != 1
3682 && xtensa_opcode_is_jump (isa
, insn
->opcode
) != 1)
3685 for (i
= 0; i
< num_ops
; i
++)
3687 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3693 if (target_op
== -1)
3696 if (insn
->ntok
<= target_op
)
3699 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3702 sym
= insn
->tok
[target_op
].X_add_symbol
;
3706 if (insn
->tok
[target_op
].X_add_number
!= 0)
3709 target_frag
= symbol_get_frag (sym
);
3710 if (target_frag
== NULL
)
3713 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3714 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3722 xg_add_branch_and_loop_targets (TInsn
*insn
)
3724 xtensa_isa isa
= xtensa_default_isa
;
3725 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3727 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3730 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3731 && insn
->tok
[i
].X_op
== O_symbol
)
3732 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3736 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3737 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3741 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3743 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3744 && insn
->tok
[i
].X_op
== O_symbol
)
3746 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3747 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3748 if (S_IS_DEFINED (sym
))
3749 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3756 /* Return FALSE if no error. */
3759 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3764 switch (instr_spec
->typ
)
3767 new_insn
->insn_type
= ITYPE_INSN
;
3768 new_insn
->opcode
= instr_spec
->opcode
;
3769 new_insn
->is_specific_opcode
= FALSE
;
3770 new_insn
->linenum
= old_insn
->linenum
;
3772 case INSTR_LITERAL_DEF
:
3773 new_insn
->insn_type
= ITYPE_LITERAL
;
3774 new_insn
->opcode
= XTENSA_UNDEFINED
;
3775 new_insn
->is_specific_opcode
= FALSE
;
3776 new_insn
->linenum
= old_insn
->linenum
;
3778 case INSTR_LABEL_DEF
:
3779 as_bad (_("INSTR_LABEL_DEF not supported yet"));
3783 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3786 const expressionS
*src_exp
;
3792 /* The expression must be the constant. */
3793 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3794 exp
= &new_insn
->tok
[b_op
->op_num
];
3795 set_expr_const (exp
, b_op
->op_data
);
3799 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3800 assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
3801 src_exp
= &old_insn
->tok
[b_op
->op_data
];
3802 exp
= &new_insn
->tok
[b_op
->op_num
];
3803 copy_expr (exp
, src_exp
);
3808 as_bad (_("can't handle generation of literal/labels yet"));
3812 as_bad (_("can't handle undefined OP TYPE"));
3817 new_insn
->ntok
= num_ops
;
3822 /* Return TRUE if it was simplified. */
3825 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
3827 TransitionRule
*rule
;
3828 BuildInstr
*insn_spec
;
3830 if (old_insn
->is_specific_opcode
|| !density_supported
)
3833 rule
= xg_instruction_match (old_insn
);
3837 insn_spec
= rule
->to_instr
;
3838 /* There should only be one. */
3839 assert (insn_spec
!= NULL
);
3840 assert (insn_spec
->next
== NULL
);
3841 if (insn_spec
->next
!= NULL
)
3844 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
3850 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3851 l32i.n. (2) Check the number of operands. (3) Place the instruction
3852 tokens into the stack or relax it and place multiple
3853 instructions/literals onto the stack. Return FALSE if no error. */
3856 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
3860 bfd_boolean do_expand
;
3862 tinsn_init (&new_insn
);
3864 /* Narrow it if we can. xg_simplify_insn now does all the
3865 appropriate checking (e.g., for the density option). */
3866 if (xg_simplify_insn (orig_insn
, &new_insn
))
3867 orig_insn
= &new_insn
;
3869 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
3871 if (orig_insn
->ntok
< noperands
)
3873 as_bad (_("found %d operands for '%s': Expected %d"),
3875 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3879 if (orig_insn
->ntok
> noperands
)
3880 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
3882 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3885 /* If there are not enough operands, we will assert above. If there
3886 are too many, just cut out the extras here. */
3887 orig_insn
->ntok
= noperands
;
3889 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
3892 /* Special case for extui opcode which has constraints not handled
3893 by the ordinary operand encoding checks. The number of operands
3894 and related syntax issues have already been checked. */
3895 if (orig_insn
->opcode
== xtensa_extui_opcode
)
3897 int shiftimm
= orig_insn
->tok
[2].X_add_number
;
3898 int maskimm
= orig_insn
->tok
[3].X_add_number
;
3899 if (shiftimm
+ maskimm
> 32)
3901 as_bad (_("immediate operands sum to greater than 32"));
3906 /* If the instruction will definitely need to be relaxed, it is better
3907 to expand it now for better scheduling. Decide whether to expand
3909 do_expand
= (!orig_insn
->is_specific_opcode
&& use_transform ());
3911 /* Calls should be expanded to longcalls only in the backend relaxation
3912 so that the assembly scheduler will keep the L32R/CALLX instructions
3914 if (is_direct_call_opcode (orig_insn
->opcode
))
3917 if (tinsn_has_symbolic_operands (orig_insn
))
3919 /* The values of symbolic operands are not known yet, so only expand
3920 now if an operand is "complex" (e.g., difference of symbols) and
3921 will have to be stored as a literal regardless of the value. */
3922 if (!tinsn_has_complex_operands (orig_insn
))
3925 else if (xg_immeds_fit (orig_insn
))
3929 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
3931 istack_push (istack
, orig_insn
);
3937 /* Return TRUE if the section flags are marked linkonce
3938 or the name is .gnu.linkonce.*. */
3940 static int linkonce_len
= sizeof (".gnu.linkonce.") - 1;
3943 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
3945 flagword flags
, link_once_flags
;
3947 flags
= bfd_get_section_flags (abfd
, sec
);
3948 link_once_flags
= (flags
& SEC_LINK_ONCE
);
3950 /* Flags might not be set yet. */
3951 if (!link_once_flags
3952 && strncmp (segment_name (sec
), ".gnu.linkonce.", linkonce_len
) == 0)
3953 link_once_flags
= SEC_LINK_ONCE
;
3955 return (link_once_flags
!= 0);
3960 xtensa_add_literal_sym (symbolS
*sym
)
3964 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
3966 l
->next
= literal_syms
;
3972 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
3974 static int lit_num
= 0;
3975 static char name
[256];
3978 sprintf (name
, ".L_lit_sym%d", lit_num
);
3980 /* Create a local symbol. If it is in a linkonce section, we have to
3981 be careful to make sure that if it is used in a relocation that the
3982 symbol will be in the output file. */
3983 if (get_is_linkonce_section (stdoutput
, sec
))
3985 symbolP
= symbol_new (name
, sec
, 0, frag
);
3986 S_CLEAR_EXTERNAL (symbolP
);
3987 /* symbolP->local = 1; */
3990 symbolP
= symbol_new (name
, sec
, 0, frag
);
3992 xtensa_add_literal_sym (symbolP
);
3999 /* Currently all literals that are generated here are 32-bit L32R targets. */
4002 xg_assemble_literal (/* const */ TInsn
*insn
)
4005 symbolS
*lit_sym
= NULL
;
4006 bfd_reloc_code_real_type reloc
;
4009 /* size = 4 for L32R. It could easily be larger when we move to
4010 larger constants. Add a parameter later. */
4011 offsetT litsize
= 4;
4012 offsetT litalign
= 2; /* 2^2 = 4 */
4013 expressionS saved_loc
;
4014 expressionS
* emit_val
;
4016 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
4018 assert (insn
->insn_type
== ITYPE_LITERAL
);
4019 assert (insn
->ntok
== 1); /* must be only one token here */
4021 xtensa_switch_to_literal_fragment (&state
);
4023 emit_val
= &insn
->tok
[0];
4024 if (emit_val
->X_op
== O_big
)
4026 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
4029 /* This happens when someone writes a "movi a2, big_number". */
4030 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4031 _("invalid immediate"));
4032 xtensa_restore_emit_state (&state
);
4037 /* Force a 4-byte align here. Note that this opens a new frag, so all
4038 literals done with this function have a frag to themselves. That's
4039 important for the way text section literals work. */
4040 frag_align (litalign
, 0, 0);
4041 record_alignment (now_seg
, litalign
);
4043 switch (emit_val
->X_op
)
4046 p
= frag_more (litsize
);
4047 xtensa_set_frag_assembly_state (frag_now
);
4048 reloc
= map_operator_to_reloc (emit_val
->X_op
);
4049 if (emit_val
->X_add_symbol
)
4050 emit_val
->X_op
= O_symbol
;
4052 emit_val
->X_op
= O_constant
;
4053 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
4054 litsize
, emit_val
, 0, reloc
);
4058 emit_expr (emit_val
, litsize
);
4062 assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
4063 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4064 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4065 lit_sym
= frag_now
->fr_symbol
;
4068 xtensa_restore_emit_state (&state
);
4074 xg_assemble_literal_space (/* const */ int size
, int slot
)
4077 /* We might have to do something about this alignment. It only
4078 takes effect if something is placed here. */
4079 offsetT litalign
= 2; /* 2^2 = 4 */
4080 fragS
*lit_saved_frag
;
4082 assert (size
% 4 == 0);
4084 xtensa_switch_to_literal_fragment (&state
);
4086 /* Force a 4-byte align here. */
4087 frag_align (litalign
, 0, 0);
4088 record_alignment (now_seg
, litalign
);
4090 xg_force_frag_space (size
);
4092 lit_saved_frag
= frag_now
;
4093 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4094 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4095 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4098 xtensa_restore_emit_state (&state
);
4099 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4103 /* Put in a fixup record based on the opcode.
4104 Return TRUE on success. */
4107 xg_add_opcode_fix (TInsn
*tinsn
,
4115 xtensa_opcode opcode
= tinsn
->opcode
;
4116 bfd_reloc_code_real_type reloc
;
4117 reloc_howto_type
*howto
;
4121 reloc
= BFD_RELOC_NONE
;
4123 /* First try the special cases for "alternate" relocs. */
4124 if (opcode
== xtensa_l32r_opcode
)
4126 if (fragP
->tc_frag_data
.use_absolute_literals
)
4127 reloc
= encode_alt_reloc (slot
);
4129 else if (opcode
== xtensa_const16_opcode
)
4131 if (expr
->X_op
== O_lo16
)
4133 reloc
= encode_reloc (slot
);
4134 expr
->X_op
= O_symbol
;
4136 else if (expr
->X_op
== O_hi16
)
4138 reloc
= encode_alt_reloc (slot
);
4139 expr
->X_op
= O_symbol
;
4143 if (opnum
!= get_relaxable_immed (opcode
))
4145 as_bad (_("invalid relocation for operand %i of '%s'"),
4146 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4150 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4151 into the symbol table where the generic portions of the assembler
4152 won't know what to do with them. */
4153 if (expr
->X_op
== O_lo16
|| expr
->X_op
== O_hi16
)
4155 as_bad (_("invalid expression for operand %i of '%s'"),
4156 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4160 /* Next try the generic relocs. */
4161 if (reloc
== BFD_RELOC_NONE
)
4162 reloc
= encode_reloc (slot
);
4163 if (reloc
== BFD_RELOC_NONE
)
4165 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4169 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4172 as_bad (_("undefined symbol for opcode \"%s\""),
4173 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4177 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4178 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, expr
,
4179 howto
->pc_relative
, reloc
);
4180 the_fix
->fx_no_overflow
= 1;
4181 the_fix
->tc_fix_data
.X_add_symbol
= expr
->X_add_symbol
;
4182 the_fix
->tc_fix_data
.X_add_number
= expr
->X_add_number
;
4183 the_fix
->tc_fix_data
.slot
= slot
;
4190 xg_emit_insn_to_buf (TInsn
*tinsn
,
4194 bfd_boolean build_fix
)
4196 static xtensa_insnbuf insnbuf
= NULL
;
4197 bfd_boolean has_symbolic_immed
= FALSE
;
4198 bfd_boolean ok
= TRUE
;
4201 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4203 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4204 if (has_symbolic_immed
&& build_fix
)
4207 xtensa_format fmt
= xg_get_single_format (tinsn
->opcode
);
4208 int slot
= xg_get_single_slot (tinsn
->opcode
);
4209 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4210 expressionS
*exp
= &tinsn
->tok
[opnum
];
4212 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, slot
, exp
, fragP
, offset
))
4215 fragP
->tc_frag_data
.is_insn
= TRUE
;
4216 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4217 (unsigned char *) buf
, 0);
4223 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4225 symbolS
*sym
= get_special_literal_symbol ();
4229 assert (insn
->insn_type
== ITYPE_INSN
);
4230 for (i
= 0; i
< insn
->ntok
; i
++)
4231 if (insn
->tok
[i
].X_add_symbol
== sym
)
4232 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4238 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4240 symbolS
*sym
= get_special_label_symbol ();
4242 for (i
= 0; i
< insn
->ntok
; i
++)
4243 if (insn
->tok
[i
].X_add_symbol
== sym
)
4244 insn
->tok
[i
].X_add_symbol
= label_sym
;
4249 /* Return TRUE if the instruction can write to the specified
4250 integer register. */
4253 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4257 xtensa_isa isa
= xtensa_default_isa
;
4259 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4261 for (i
= 0; i
< num_ops
; i
++)
4264 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4265 if ((inout
== 'o' || inout
== 'm')
4266 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4268 xtensa_regfile opnd_rf
=
4269 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4270 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4272 if ((insn
->tok
[i
].X_op
== O_register
)
4273 && (insn
->tok
[i
].X_add_number
== regnum
))
4283 is_bad_loopend_opcode (const TInsn
*tinsn
)
4285 xtensa_opcode opcode
= tinsn
->opcode
;
4287 if (opcode
== XTENSA_UNDEFINED
)
4290 if (opcode
== xtensa_call0_opcode
4291 || opcode
== xtensa_callx0_opcode
4292 || opcode
== xtensa_call4_opcode
4293 || opcode
== xtensa_callx4_opcode
4294 || opcode
== xtensa_call8_opcode
4295 || opcode
== xtensa_callx8_opcode
4296 || opcode
== xtensa_call12_opcode
4297 || opcode
== xtensa_callx12_opcode
4298 || opcode
== xtensa_isync_opcode
4299 || opcode
== xtensa_ret_opcode
4300 || opcode
== xtensa_ret_n_opcode
4301 || opcode
== xtensa_retw_opcode
4302 || opcode
== xtensa_retw_n_opcode
4303 || opcode
== xtensa_waiti_opcode
4304 || opcode
== xtensa_rsr_lcount_opcode
)
4311 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4312 This allows the debugger to add unaligned labels.
4313 Also, the assembler generates stabs labels that need
4314 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4317 is_unaligned_label (symbolS
*sym
)
4319 const char *name
= S_GET_NAME (sym
);
4320 static size_t fake_size
= 0;
4324 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4327 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4329 fake_size
= strlen (FAKE_LABEL_NAME
);
4332 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4333 && (name
[fake_size
] == 'F'
4334 || name
[fake_size
] == 'L'
4335 || (name
[fake_size
] == 'e'
4336 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4344 next_non_empty_frag (const fragS
*fragP
)
4346 fragS
*next_fragP
= fragP
->fr_next
;
4348 /* Sometimes an empty will end up here due storage allocation issues.
4349 So we have to skip until we find something legit. */
4350 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4351 next_fragP
= next_fragP
->fr_next
;
4353 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4361 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4363 xtensa_opcode out_opcode
;
4364 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4366 if (next_fragP
== NULL
)
4369 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4370 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4372 *opcode
= out_opcode
;
4380 frag_format_size (const fragS
*fragP
)
4382 static xtensa_insnbuf insnbuf
= NULL
;
4383 xtensa_isa isa
= xtensa_default_isa
;
4388 insnbuf
= xtensa_insnbuf_alloc (isa
);
4391 return XTENSA_UNDEFINED
;
4393 xtensa_insnbuf_from_chars (isa
, insnbuf
,
4394 (unsigned char *) fragP
->fr_literal
, 0);
4396 fmt
= xtensa_format_decode (isa
, insnbuf
);
4397 if (fmt
== XTENSA_UNDEFINED
)
4398 return XTENSA_UNDEFINED
;
4399 fmt_size
= xtensa_format_length (isa
, fmt
);
4401 /* If the next format won't be changing due to relaxation, just
4402 return the length of the first format. */
4403 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4406 /* If during relaxation we have to pull an instruction out of a
4407 multi-slot instruction, we will return the more conservative
4408 number. This works because alignment on bigger instructions
4409 is more restrictive than alignment on smaller instructions.
4410 This is more conservative than we would like, but it happens
4413 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4416 /* If we aren't doing one of our own relaxations or it isn't
4417 slot-based, then the insn size won't change. */
4418 if (fragP
->fr_type
!= rs_machine_dependent
)
4420 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4423 /* If an instruction is about to grow, return the longer size. */
4424 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4425 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
4426 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP3
)
4429 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4430 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4437 next_frag_format_size (const fragS
*fragP
)
4439 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4440 return frag_format_size (next_fragP
);
4444 /* In early Xtensa Processors, for reasons that are unclear, the ISA
4445 required two-byte instructions to be treated as three-byte instructions
4446 for loop instruction alignment. This restriction was removed beginning
4447 with Xtensa LX. Now the only requirement on loop instruction alignment
4448 is that the first instruction of the loop must appear at an address that
4449 does not cross a fetch boundary. */
4452 get_loop_align_size (int insn_size
)
4454 if (insn_size
== XTENSA_UNDEFINED
)
4455 return xtensa_fetch_width
;
4457 if (enforce_three_byte_loop_align
&& insn_size
== 2)
4464 /* If the next legit fragment is an end-of-loop marker,
4465 switch its state so it will instantiate a NOP. */
4468 update_next_frag_state (fragS
*fragP
)
4470 fragS
*next_fragP
= fragP
->fr_next
;
4471 fragS
*new_target
= NULL
;
4475 /* We are guaranteed there will be one of these... */
4476 while (!(next_fragP
->fr_type
== rs_machine_dependent
4477 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4478 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4479 next_fragP
= next_fragP
->fr_next
;
4481 assert (next_fragP
->fr_type
== rs_machine_dependent
4482 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4483 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4485 /* ...and one of these. */
4486 new_target
= next_fragP
->fr_next
;
4487 while (!(new_target
->fr_type
== rs_machine_dependent
4488 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4489 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4490 new_target
= new_target
->fr_next
;
4492 assert (new_target
->fr_type
== rs_machine_dependent
4493 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4494 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4497 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4499 if (next_fragP
->fr_type
== rs_machine_dependent
4500 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4502 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4506 next_fragP
= next_fragP
->fr_next
;
4512 next_frag_is_branch_target (const fragS
*fragP
)
4514 /* Sometimes an empty will end up here due to storage allocation issues,
4515 so we have to skip until we find something legit. */
4516 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4518 if (fragP
->tc_frag_data
.is_branch_target
)
4520 if (fragP
->fr_fix
!= 0)
4528 next_frag_is_loop_target (const fragS
*fragP
)
4530 /* Sometimes an empty will end up here due storage allocation issues.
4531 So we have to skip until we find something legit. */
4532 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4534 if (fragP
->tc_frag_data
.is_loop_target
)
4536 if (fragP
->fr_fix
!= 0)
4544 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4546 const fragS
*next_fragp
= fragp
->fr_next
;
4547 xtensa_opcode next_opcode
;
4549 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4552 /* Sometimes an empty will end up here due to storage allocation issues,
4553 so we have to skip until we find something legit. */
4554 while (next_fragp
->fr_fix
== 0)
4555 next_fragp
= next_fragp
->fr_next
;
4557 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4560 /* There is some implicit knowledge encoded in here.
4561 The LOOP instructions that are NOT RELAX_IMMED have
4562 been relaxed. Note that we can assume that the LOOP
4563 instruction is in slot 0 because loops aren't bundleable. */
4564 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4565 return get_expanded_loop_offset (next_opcode
);
4571 /* Mark a location where we can later insert literal frags. Update
4572 the section's literal_pool_loc, so subsequent literals can be
4573 placed nearest to their use. */
4576 xtensa_mark_literal_pool_location (void)
4578 /* Any labels pointing to the current location need
4579 to be adjusted to after the literal pool. */
4581 fragS
*pool_location
;
4583 if (use_literal_section
)
4586 /* We stash info in these frags so we can later move the literal's
4587 fixes into this frchain's fix list. */
4588 pool_location
= frag_now
;
4589 frag_now
->tc_frag_data
.lit_frchain
= frchain_now
;
4590 frag_now
->tc_frag_data
.literal_frag
= frag_now
;
4591 frag_variant (rs_machine_dependent
, 0, 0,
4592 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4593 xtensa_set_frag_assembly_state (frag_now
);
4594 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
4595 frag_variant (rs_machine_dependent
, 0, 0,
4596 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4597 xtensa_set_frag_assembly_state (frag_now
);
4599 /* Now put a frag into the literal pool that points to this location. */
4600 set_literal_pool_location (now_seg
, pool_location
);
4601 xtensa_switch_to_non_abs_literal_fragment (&s
);
4602 frag_align (2, 0, 0);
4603 record_alignment (now_seg
, 2);
4605 /* Close whatever frag is there. */
4606 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4607 xtensa_set_frag_assembly_state (frag_now
);
4608 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
4609 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4610 xtensa_restore_emit_state (&s
);
4611 xtensa_set_frag_assembly_state (frag_now
);
4615 /* Build a nop of the correct size into tinsn. */
4618 build_nop (TInsn
*tinsn
, int size
)
4624 tinsn
->opcode
= xtensa_nop_n_opcode
;
4626 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4627 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4631 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4633 tinsn
->opcode
= xtensa_or_opcode
;
4634 set_expr_const (&tinsn
->tok
[0], 1);
4635 set_expr_const (&tinsn
->tok
[1], 1);
4636 set_expr_const (&tinsn
->tok
[2], 1);
4640 tinsn
->opcode
= xtensa_nop_opcode
;
4642 assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4647 /* Assemble a NOP of the requested size in the buffer. User must have
4648 allocated "buf" with at least "size" bytes. */
4651 assemble_nop (int size
, char *buf
)
4653 static xtensa_insnbuf insnbuf
= NULL
;
4656 build_nop (&tinsn
, size
);
4659 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4661 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4662 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4663 (unsigned char *) buf
, 0);
4667 /* Return the number of bytes for the offset of the expanded loop
4668 instruction. This should be incorporated into the relaxation
4669 specification but is hard-coded here. This is used to auto-align
4670 the loop instruction. It is invalid to call this function if the
4671 configuration does not have loops or if the opcode is not a loop
4675 get_expanded_loop_offset (xtensa_opcode opcode
)
4677 /* This is the OFFSET of the loop instruction in the expanded loop.
4678 This MUST correspond directly to the specification of the loop
4679 expansion. It will be validated on fragment conversion. */
4680 assert (opcode
!= XTENSA_UNDEFINED
);
4681 if (opcode
== xtensa_loop_opcode
)
4683 if (opcode
== xtensa_loopnez_opcode
)
4685 if (opcode
== xtensa_loopgtz_opcode
)
4687 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4693 get_literal_pool_location (segT seg
)
4695 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4700 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4702 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4706 /* Set frag assembly state should be called when a new frag is
4707 opened and after a frag has been closed. */
4710 xtensa_set_frag_assembly_state (fragS
*fragP
)
4712 if (!density_supported
)
4713 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4715 /* This function is called from subsegs_finish, which is called
4716 after xtensa_end, so we can't use "use_transform" or
4717 "use_schedule" here. */
4718 if (!directive_state
[directive_transform
])
4719 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4720 if (directive_state
[directive_longcalls
])
4721 fragP
->tc_frag_data
.use_longcalls
= TRUE
;
4722 fragP
->tc_frag_data
.use_absolute_literals
=
4723 directive_state
[directive_absolute_literals
];
4724 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4729 relaxable_section (asection
*sec
)
4731 return (sec
->flags
& SEC_DEBUGGING
) == 0;
4736 xtensa_mark_frags_for_org (void)
4740 /* Walk over each fragment of all of the current segments. If we find
4741 a .org frag in any of the segments, mark all frags prior to it as
4742 "no transform", which will prevent linker optimizations from messing
4743 up the .org distance. This should be done after
4744 xtensa_find_unmarked_state_frags, because we don't want to worry here
4745 about that function trashing the data we save here. */
4747 for (seclist
= &stdoutput
->sections
;
4748 seclist
&& *seclist
;
4749 seclist
= &(*seclist
)->next
)
4751 segT sec
= *seclist
;
4752 segment_info_type
*seginfo
;
4755 flags
= bfd_get_section_flags (stdoutput
, sec
);
4756 if (flags
& SEC_DEBUGGING
)
4758 if (!(flags
& SEC_ALLOC
))
4761 seginfo
= seg_info (sec
);
4762 if (seginfo
&& seginfo
->frchainP
)
4764 fragS
*last_fragP
= seginfo
->frchainP
->frch_root
;
4765 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4766 fragP
= fragP
->fr_next
)
4768 /* cvt_frag_to_fill has changed the fr_type of org frags to
4769 rs_fill, so use the value as cached in rs_subtype here. */
4770 if (fragP
->fr_subtype
== RELAX_ORG
)
4772 while (last_fragP
!= fragP
->fr_next
)
4774 last_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4775 last_fragP
= last_fragP
->fr_next
;
4785 xtensa_find_unmarked_state_frags (void)
4789 /* Walk over each fragment of all of the current segments. For each
4790 unmarked fragment, mark it with the same info as the previous
4792 for (seclist
= &stdoutput
->sections
;
4793 seclist
&& *seclist
;
4794 seclist
= &(*seclist
)->next
)
4796 segT sec
= *seclist
;
4797 segment_info_type
*seginfo
;
4800 flags
= bfd_get_section_flags (stdoutput
, sec
);
4801 if (flags
& SEC_DEBUGGING
)
4803 if (!(flags
& SEC_ALLOC
))
4806 seginfo
= seg_info (sec
);
4807 if (seginfo
&& seginfo
->frchainP
)
4809 fragS
*last_fragP
= 0;
4810 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4811 fragP
= fragP
->fr_next
)
4813 if (fragP
->fr_fix
!= 0
4814 && !fragP
->tc_frag_data
.is_assembly_state_set
)
4816 if (last_fragP
== 0)
4818 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
4819 _("assembly state not set for first frag in section %s"),
4824 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4825 fragP
->tc_frag_data
.is_no_density
=
4826 last_fragP
->tc_frag_data
.is_no_density
;
4827 fragP
->tc_frag_data
.is_no_transform
=
4828 last_fragP
->tc_frag_data
.is_no_transform
;
4829 fragP
->tc_frag_data
.use_longcalls
=
4830 last_fragP
->tc_frag_data
.use_longcalls
;
4831 fragP
->tc_frag_data
.use_absolute_literals
=
4832 last_fragP
->tc_frag_data
.use_absolute_literals
;
4835 if (fragP
->tc_frag_data
.is_assembly_state_set
)
4844 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
4846 void *unused ATTRIBUTE_UNUSED
)
4848 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4849 segment_info_type
*seginfo
= seg_info (sec
);
4850 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4852 if (flags
& SEC_CODE
)
4854 xtensa_isa isa
= xtensa_default_isa
;
4855 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4856 while (frag
!= NULL
)
4858 if (frag
->tc_frag_data
.is_branch_target
)
4861 addressT branch_align
, frag_addr
;
4864 xtensa_insnbuf_from_chars
4865 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4866 fmt
= xtensa_format_decode (isa
, insnbuf
);
4867 op_size
= xtensa_format_length (isa
, fmt
);
4868 branch_align
= 1 << branch_align_power (sec
);
4869 frag_addr
= frag
->fr_address
% branch_align
;
4870 if (frag_addr
+ op_size
> branch_align
)
4871 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4872 _("unaligned branch target: %d bytes at 0x%lx"),
4873 op_size
, (long) frag
->fr_address
);
4875 frag
= frag
->fr_next
;
4877 xtensa_insnbuf_free (isa
, insnbuf
);
4883 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
4885 void *unused ATTRIBUTE_UNUSED
)
4887 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4888 segment_info_type
*seginfo
= seg_info (sec
);
4889 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4890 xtensa_isa isa
= xtensa_default_isa
;
4892 if (flags
& SEC_CODE
)
4894 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4895 while (frag
!= NULL
)
4897 if (frag
->tc_frag_data
.is_first_loop_insn
)
4903 xtensa_insnbuf_from_chars
4904 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4905 fmt
= xtensa_format_decode (isa
, insnbuf
);
4906 op_size
= xtensa_format_length (isa
, fmt
);
4907 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
4909 if (frag_addr
+ op_size
> xtensa_fetch_width
)
4910 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4911 _("unaligned loop: %d bytes at 0x%lx"),
4912 op_size
, (long) frag
->fr_address
);
4914 frag
= frag
->fr_next
;
4916 xtensa_insnbuf_free (isa
, insnbuf
);
4922 xg_apply_fix_value (fixS
*fixP
, valueT val
)
4924 xtensa_isa isa
= xtensa_default_isa
;
4925 static xtensa_insnbuf insnbuf
= NULL
;
4926 static xtensa_insnbuf slotbuf
= NULL
;
4929 bfd_boolean alt_reloc
;
4930 xtensa_opcode opcode
;
4931 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
4933 (void) decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
);
4935 as_fatal (_("unexpected fix"));
4939 insnbuf
= xtensa_insnbuf_alloc (isa
);
4940 slotbuf
= xtensa_insnbuf_alloc (isa
);
4943 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4944 fmt
= xtensa_format_decode (isa
, insnbuf
);
4945 if (fmt
== XTENSA_UNDEFINED
)
4946 as_fatal (_("undecodable fix"));
4947 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4948 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
4949 if (opcode
== XTENSA_UNDEFINED
)
4950 as_fatal (_("undecodable fix"));
4952 /* CONST16 immediates are not PC-relative, despite the fact that we
4953 reuse the normal PC-relative operand relocations for the low part
4954 of a CONST16 operand. */
4955 if (opcode
== xtensa_const16_opcode
)
4958 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
4959 get_relaxable_immed (opcode
), val
,
4960 fixP
->fx_file
, fixP
->fx_line
);
4962 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4963 xtensa_insnbuf_to_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4969 /* External Functions and Other GAS Hooks. */
4972 xtensa_target_format (void)
4974 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
4979 xtensa_file_arch_init (bfd
*abfd
)
4981 bfd_set_private_flags (abfd
, 0x100 | 0x200);
4986 md_number_to_chars (char *buf
, valueT val
, int n
)
4988 if (target_big_endian
)
4989 number_to_chars_bigendian (buf
, val
, n
);
4991 number_to_chars_littleendian (buf
, val
, n
);
4995 /* This function is called once, at assembler startup time. It should
4996 set up all the tables, etc. that the MD part of the assembler will
5002 segT current_section
= now_seg
;
5003 int current_subsec
= now_subseg
;
5006 xtensa_default_isa
= xtensa_isa_init (0, 0);
5007 isa
= xtensa_default_isa
;
5011 /* Set up the literal sections. */
5012 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
5014 subseg_set (current_section
, current_subsec
);
5016 xg_init_vinsn (&cur_vinsn
);
5018 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
5019 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
5020 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
5021 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
5022 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
5023 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
5024 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
5025 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
5026 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
5027 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
5028 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
5029 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
5030 xtensa_extui_opcode
= xtensa_opcode_lookup (isa
, "extui");
5031 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
5032 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
5033 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
5034 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
5035 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
5036 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
5037 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
5038 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
5039 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
5040 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
5041 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
5042 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
5043 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
5044 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
5045 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
5046 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
5047 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
5049 init_op_placement_info_table ();
5051 /* Set up the assembly state. */
5052 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5053 xtensa_set_frag_assembly_state (frag_now
);
5057 /* TC_INIT_FIX_DATA hook */
5060 xtensa_init_fix_data (fixS
*x
)
5062 x
->tc_fix_data
.slot
= 0;
5063 x
->tc_fix_data
.X_add_symbol
= NULL
;
5064 x
->tc_fix_data
.X_add_number
= 0;
5068 /* tc_frob_label hook */
5071 xtensa_frob_label (symbolS
*sym
)
5075 if (cur_vinsn
.inside_bundle
)
5077 as_bad (_("labels are not valid inside bundles"));
5081 freq
= get_subseg_target_freq (now_seg
, now_subseg
);
5083 /* Since the label was already attached to a frag associated with the
5084 previous basic block, it now needs to be reset to the current frag. */
5085 symbol_set_frag (sym
, frag_now
);
5086 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5088 if (generating_literals
)
5089 xtensa_add_literal_sym (sym
);
5091 xtensa_add_insn_label (sym
);
5093 if (symbol_get_tc (sym
)->is_loop_target
)
5095 if ((get_last_insn_flags (now_seg
, now_subseg
)
5096 & FLAG_IS_BAD_LOOPEND
) != 0)
5097 as_bad (_("invalid last instruction for a zero-overhead loop"));
5099 xtensa_set_frag_assembly_state (frag_now
);
5100 frag_var (rs_machine_dependent
, 4, 4, RELAX_LOOP_END
,
5101 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5103 xtensa_set_frag_assembly_state (frag_now
);
5104 xtensa_move_labels (frag_now
, 0);
5107 /* No target aligning in the absolute section. */
5108 if (now_seg
!= absolute_section
5109 && do_align_targets ()
5110 && !is_unaligned_label (sym
)
5111 && !generating_literals
)
5113 xtensa_set_frag_assembly_state (frag_now
);
5115 frag_var (rs_machine_dependent
,
5117 RELAX_DESIRE_ALIGN_IF_TARGET
,
5118 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5119 xtensa_set_frag_assembly_state (frag_now
);
5120 xtensa_move_labels (frag_now
, 0);
5123 /* We need to mark the following properties even if we aren't aligning. */
5125 /* If the label is already known to be a branch target, i.e., a
5126 forward branch, mark the frag accordingly. Backward branches
5127 are handled by xg_add_branch_and_loop_targets. */
5128 if (symbol_get_tc (sym
)->is_branch_target
)
5129 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5131 /* Loops only go forward, so they can be identified here. */
5132 if (symbol_get_tc (sym
)->is_loop_target
)
5133 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5135 dwarf2_emit_label (sym
);
5139 /* tc_unrecognized_line hook */
5142 xtensa_unrecognized_line (int ch
)
5147 if (cur_vinsn
.inside_bundle
== 0)
5149 /* PR8110: Cannot emit line number info inside a FLIX bundle
5150 when using --gstabs. Temporarily disable debug info. */
5151 generate_lineno_debug ();
5152 if (debug_type
== DEBUG_STABS
)
5154 xt_saved_debug_type
= debug_type
;
5155 debug_type
= DEBUG_NONE
;
5158 cur_vinsn
.inside_bundle
= 1;
5162 as_bad (_("extra opening brace"));
5168 if (cur_vinsn
.inside_bundle
)
5169 finish_vinsn (&cur_vinsn
);
5172 as_bad (_("extra closing brace"));
5177 as_bad (_("syntax error"));
5184 /* md_flush_pending_output hook */
5187 xtensa_flush_pending_output (void)
5189 /* This line fixes a bug where automatically generated gstabs info
5190 separates a function label from its entry instruction, ending up
5191 with the literal position between the function label and the entry
5192 instruction and crashing code. It only happens with --gstabs and
5193 --text-section-literals, and when several other obscure relaxation
5194 conditions are met. */
5195 if (outputting_stabs_line_debug
)
5198 if (cur_vinsn
.inside_bundle
)
5199 as_bad (_("missing closing brace"));
5201 /* If there is a non-zero instruction fragment, close it. */
5202 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5204 frag_wane (frag_now
);
5206 xtensa_set_frag_assembly_state (frag_now
);
5208 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5210 xtensa_clear_insn_labels ();
5214 /* We had an error while parsing an instruction. The string might look
5215 like this: "insn arg1, arg2 }". If so, we need to see the closing
5216 brace and reset some fields. Otherwise, the vinsn never gets closed
5217 and the num_slots field will grow past the end of the array of slots,
5218 and bad things happen. */
5221 error_reset_cur_vinsn (void)
5223 if (cur_vinsn
.inside_bundle
)
5225 if (*input_line_pointer
== '}'
5226 || *(input_line_pointer
- 1) == '}'
5227 || *(input_line_pointer
- 2) == '}')
5228 xg_clear_vinsn (&cur_vinsn
);
5234 md_assemble (char *str
)
5236 xtensa_isa isa
= xtensa_default_isa
;
5237 char *opname
, *file_name
;
5239 bfd_boolean has_underbar
= FALSE
;
5240 char *arg_strings
[MAX_INSN_ARGS
];
5242 TInsn orig_insn
; /* Original instruction from the input. */
5244 tinsn_init (&orig_insn
);
5246 /* Split off the opcode. */
5247 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5248 opname
= xmalloc (opnamelen
+ 1);
5249 memcpy (opname
, str
, opnamelen
);
5250 opname
[opnamelen
] = '\0';
5252 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5255 as_bad (_("syntax error"));
5259 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5262 /* Check for an underbar prefix. */
5265 has_underbar
= TRUE
;
5269 orig_insn
.insn_type
= ITYPE_INSN
;
5271 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5273 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5274 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5276 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5277 if (fmt
== XTENSA_UNDEFINED
)
5279 as_bad (_("unknown opcode or format name '%s'"), opname
);
5280 error_reset_cur_vinsn ();
5283 if (!cur_vinsn
.inside_bundle
)
5285 as_bad (_("format names only valid inside bundles"));
5286 error_reset_cur_vinsn ();
5289 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5290 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5292 cur_vinsn
.format
= fmt
;
5293 free (has_underbar
? opname
- 1 : opname
);
5294 error_reset_cur_vinsn ();
5298 /* Parse the arguments. */
5299 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5301 as_bad (_("syntax error"));
5302 error_reset_cur_vinsn ();
5306 /* Free the opcode and argument strings, now that they've been parsed. */
5307 free (has_underbar
? opname
- 1 : opname
);
5309 while (num_args
-- > 0)
5310 free (arg_strings
[num_args
]);
5312 /* Get expressions for invisible operands. */
5313 if (get_invisible_operands (&orig_insn
))
5315 error_reset_cur_vinsn ();
5319 /* Check for the right number and type of arguments. */
5320 if (tinsn_check_arguments (&orig_insn
))
5322 error_reset_cur_vinsn ();
5326 /* A FLIX bundle may be spread across multiple input lines. We want to
5327 report the first such line in the debug information. Record the line
5328 number for each TInsn (assume the file name doesn't change), so the
5329 first line can be found later. */
5330 as_where (&file_name
, &orig_insn
.linenum
);
5332 xg_add_branch_and_loop_targets (&orig_insn
);
5334 /* Check that immediate value for ENTRY is >= 16. */
5335 if (orig_insn
.opcode
== xtensa_entry_opcode
&& orig_insn
.ntok
>= 3)
5337 expressionS
*exp
= &orig_insn
.tok
[2];
5338 if (exp
->X_op
== O_constant
&& exp
->X_add_number
< 16)
5339 as_warn (_("entry instruction with stack decrement < 16"));
5343 assemble_tokens (opcode, tok, ntok);
5344 expand the tokens from the orig_insn into the
5345 stack of instructions that will not expand
5346 unless required at relaxation time. */
5348 if (!cur_vinsn
.inside_bundle
)
5349 emit_single_op (&orig_insn
);
5350 else /* We are inside a bundle. */
5352 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5353 cur_vinsn
.num_slots
++;
5354 if (*input_line_pointer
== '}'
5355 || *(input_line_pointer
- 1) == '}'
5356 || *(input_line_pointer
- 2) == '}')
5357 finish_vinsn (&cur_vinsn
);
5360 /* We've just emitted a new instruction so clear the list of labels. */
5361 xtensa_clear_insn_labels ();
5365 /* HANDLE_ALIGN hook */
5367 /* For a .align directive, we mark the previous block with the alignment
5368 information. This will be placed in the object file in the
5369 property section corresponding to this section. */
5372 xtensa_handle_align (fragS
*fragP
)
5375 && ! fragP
->tc_frag_data
.is_literal
5376 && (fragP
->fr_type
== rs_align
5377 || fragP
->fr_type
== rs_align_code
)
5378 && fragP
->fr_address
+ fragP
->fr_fix
> 0
5379 && fragP
->fr_offset
> 0
5380 && now_seg
!= bss_section
)
5382 fragP
->tc_frag_data
.is_align
= TRUE
;
5383 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5386 if (fragP
->fr_type
== rs_align_test
)
5389 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5391 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5392 _("unaligned entry instruction"));
5395 if (linkrelax
&& fragP
->fr_type
== rs_org
)
5396 fragP
->fr_subtype
= RELAX_ORG
;
5400 /* TC_FRAG_INIT hook */
5403 xtensa_frag_init (fragS
*frag
)
5405 xtensa_set_frag_assembly_state (frag
);
5410 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5416 /* Round up a section size to the appropriate boundary. */
5419 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5421 return size
; /* Byte alignment is fine. */
5426 md_pcrel_from (fixS
*fixP
)
5429 static xtensa_insnbuf insnbuf
= NULL
;
5430 static xtensa_insnbuf slotbuf
= NULL
;
5433 xtensa_opcode opcode
;
5436 xtensa_isa isa
= xtensa_default_isa
;
5437 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5438 bfd_boolean alt_reloc
;
5440 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5445 insnbuf
= xtensa_insnbuf_alloc (isa
);
5446 slotbuf
= xtensa_insnbuf_alloc (isa
);
5449 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5450 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) insn_p
, 0);
5451 fmt
= xtensa_format_decode (isa
, insnbuf
);
5453 if (fmt
== XTENSA_UNDEFINED
)
5454 as_fatal (_("bad instruction format"));
5456 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5457 as_fatal (_("invalid relocation"));
5459 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5460 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5462 /* Check for "alternate" relocations (operand not specified). None
5463 of the current uses for these are really PC-relative. */
5464 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5466 if (opcode
!= xtensa_l32r_opcode
5467 && opcode
!= xtensa_const16_opcode
)
5468 as_fatal (_("invalid relocation for '%s' instruction"),
5469 xtensa_opcode_name (isa
, opcode
));
5473 opnum
= get_relaxable_immed (opcode
);
5475 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5476 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5478 as_bad_where (fixP
->fx_file
,
5480 _("invalid relocation for operand %d of '%s'"),
5481 opnum
, xtensa_opcode_name (isa
, opcode
));
5484 return 0 - opnd_value
;
5488 /* TC_FORCE_RELOCATION hook */
5491 xtensa_force_relocation (fixS
*fix
)
5493 switch (fix
->fx_r_type
)
5495 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5496 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5497 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5498 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5499 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5500 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5501 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5502 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5503 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5504 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5505 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5506 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5507 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5508 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5509 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5510 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5516 if (linkrelax
&& fix
->fx_addsy
5517 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5520 return generic_force_reloc (fix
);
5524 /* TC_VALIDATE_FIX_SUB hook */
5527 xtensa_validate_fix_sub (fixS
*fix
)
5529 segT add_symbol_segment
, sub_symbol_segment
;
5531 /* The difference of two symbols should be resolved by the assembler when
5532 linkrelax is not set. If the linker may relax the section containing
5533 the symbols, then an Xtensa DIFF relocation must be generated so that
5534 the linker knows to adjust the difference value. */
5535 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
5538 /* Make sure both symbols are in the same segment, and that segment is
5539 "normal" and relaxable. If the segment is not "normal", then the
5540 fix is not valid. If the segment is not "relaxable", then the fix
5541 should have been handled earlier. */
5542 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
5543 if (! SEG_NORMAL (add_symbol_segment
) ||
5544 ! relaxable_section (add_symbol_segment
))
5546 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
5547 return (sub_symbol_segment
== add_symbol_segment
);
5551 /* NO_PSEUDO_DOT hook */
5553 /* This function has nothing to do with pseudo dots, but this is the
5554 nearest macro to where the check needs to take place. FIXME: This
5558 xtensa_check_inside_bundle (void)
5560 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5561 as_bad (_("directives are not valid inside bundles"));
5563 /* This function must always return FALSE because it is called via a
5564 macro that has nothing to do with bundling. */
5569 /* md_elf_section_change_hook */
5572 xtensa_elf_section_change_hook (void)
5574 /* Set up the assembly state. */
5575 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5576 xtensa_set_frag_assembly_state (frag_now
);
5580 /* tc_fix_adjustable hook */
5583 xtensa_fix_adjustable (fixS
*fixP
)
5585 /* An offset is not allowed in combination with the difference of two
5586 symbols, but that cannot be easily detected after a local symbol
5587 has been adjusted to a (section+offset) form. Return 0 so that such
5588 an fix will not be adjusted. */
5589 if (fixP
->fx_subsy
&& fixP
->fx_addsy
&& fixP
->fx_offset
5590 && relaxable_section (S_GET_SEGMENT (fixP
->fx_subsy
)))
5593 /* We need the symbol name for the VTABLE entries. */
5594 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5595 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5602 /* tc_symbol_new_hook */
5604 symbolS
*expr_symbols
= NULL
;
5607 xtensa_symbol_new_hook (symbolS
*sym
)
5609 if (S_GET_SEGMENT (sym
) == expr_section
)
5611 symbol_get_tc (sym
)->next_expr_symbol
= expr_symbols
;
5619 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg
)
5621 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5624 /* Subtracted symbols are only allowed for a few relocation types, and
5625 unless linkrelax is enabled, they should not make it to this point. */
5626 if (fixP
->fx_subsy
&& !(linkrelax
&& (fixP
->fx_r_type
== BFD_RELOC_32
5627 || fixP
->fx_r_type
== BFD_RELOC_16
5628 || fixP
->fx_r_type
== BFD_RELOC_8
)))
5629 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("expression too complex"));
5631 switch (fixP
->fx_r_type
)
5638 switch (fixP
->fx_r_type
)
5641 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF8
;
5644 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF16
;
5647 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF32
;
5653 /* An offset is only allowed when it results from adjusting a
5654 local symbol into a section-relative offset. If the offset
5655 came from the original expression, tc_fix_adjustable will have
5656 prevented the fix from being converted to a section-relative
5657 form so that we can flag the error here. */
5658 if (fixP
->fx_offset
!= 0 && !symbol_section_p (fixP
->fx_addsy
))
5659 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5660 _("cannot represent subtraction with an offset"));
5662 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5663 - S_GET_VALUE (fixP
->fx_subsy
));
5665 /* The difference value gets written out, and the DIFF reloc
5666 identifies the address of the subtracted symbol (i.e., the one
5667 with the lowest address). */
5669 fixP
->fx_offset
-= val
;
5670 fixP
->fx_subsy
= NULL
;
5672 else if (! fixP
->fx_addsy
)
5679 case BFD_RELOC_XTENSA_PLT
:
5680 md_number_to_chars (fixpos
, val
, fixP
->fx_size
);
5681 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5684 case BFD_RELOC_XTENSA_SLOT0_OP
:
5685 case BFD_RELOC_XTENSA_SLOT1_OP
:
5686 case BFD_RELOC_XTENSA_SLOT2_OP
:
5687 case BFD_RELOC_XTENSA_SLOT3_OP
:
5688 case BFD_RELOC_XTENSA_SLOT4_OP
:
5689 case BFD_RELOC_XTENSA_SLOT5_OP
:
5690 case BFD_RELOC_XTENSA_SLOT6_OP
:
5691 case BFD_RELOC_XTENSA_SLOT7_OP
:
5692 case BFD_RELOC_XTENSA_SLOT8_OP
:
5693 case BFD_RELOC_XTENSA_SLOT9_OP
:
5694 case BFD_RELOC_XTENSA_SLOT10_OP
:
5695 case BFD_RELOC_XTENSA_SLOT11_OP
:
5696 case BFD_RELOC_XTENSA_SLOT12_OP
:
5697 case BFD_RELOC_XTENSA_SLOT13_OP
:
5698 case BFD_RELOC_XTENSA_SLOT14_OP
:
5701 /* Write the tentative value of a PC-relative relocation to a
5702 local symbol into the instruction. The value will be ignored
5703 by the linker, and it makes the object file disassembly
5704 readable when all branch targets are encoded in relocations. */
5706 assert (fixP
->fx_addsy
);
5707 if (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
5708 && !S_FORCE_RELOC (fixP
->fx_addsy
, 1))
5710 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5711 - md_pcrel_from (fixP
));
5712 (void) xg_apply_fix_value (fixP
, val
);
5715 else if (! fixP
->fx_addsy
)
5718 if (xg_apply_fix_value (fixP
, val
))
5723 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5724 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5725 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5726 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5727 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5728 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5729 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5730 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5731 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5732 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5733 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5734 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5735 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5736 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5737 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5738 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5739 /* These all need to be resolved at link-time. Do nothing now. */
5742 case BFD_RELOC_VTABLE_INHERIT
:
5743 case BFD_RELOC_VTABLE_ENTRY
:
5748 as_bad (_("unhandled local relocation fix %s"),
5749 bfd_get_reloc_code_name (fixP
->fx_r_type
));
5755 md_atof (int type
, char *litP
, int *sizeP
)
5757 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
5762 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
5764 return total_frag_text_expansion (fragP
);
5768 /* Translate internal representation of relocation info to BFD target
5772 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
5776 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
5777 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5778 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5779 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5781 /* Make sure none of our internal relocations make it this far.
5782 They'd better have been fully resolved by this point. */
5783 assert ((int) fixp
->fx_r_type
> 0);
5785 reloc
->addend
= fixp
->fx_offset
;
5787 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
5788 if (reloc
->howto
== NULL
)
5790 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5791 _("cannot represent `%s' relocation in object file"),
5792 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5793 free (reloc
->sym_ptr_ptr
);
5798 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
5799 as_fatal (_("internal error? cannot generate `%s' relocation"),
5800 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5806 /* Checks for resource conflicts between instructions. */
5808 /* The func unit stuff could be implemented as bit-vectors rather
5809 than the iterative approach here. If it ends up being too
5810 slow, we will switch it. */
5813 new_resource_table (void *data
,
5816 unit_num_copies_func uncf
,
5817 opcode_num_units_func onuf
,
5818 opcode_funcUnit_use_unit_func ouuf
,
5819 opcode_funcUnit_use_stage_func ousf
)
5822 resource_table
*rt
= (resource_table
*) xmalloc (sizeof (resource_table
));
5824 rt
->cycles
= cycles
;
5825 rt
->allocated_cycles
= cycles
;
5827 rt
->unit_num_copies
= uncf
;
5828 rt
->opcode_num_units
= onuf
;
5829 rt
->opcode_unit_use
= ouuf
;
5830 rt
->opcode_unit_stage
= ousf
;
5832 rt
->units
= (unsigned char **) xcalloc (cycles
, sizeof (unsigned char *));
5833 for (i
= 0; i
< cycles
; i
++)
5834 rt
->units
[i
] = (unsigned char *) xcalloc (nu
, sizeof (unsigned char));
5841 clear_resource_table (resource_table
*rt
)
5844 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
5845 for (j
= 0; j
< rt
->num_units
; j
++)
5846 rt
->units
[i
][j
] = 0;
5850 /* We never shrink it, just fake it into thinking so. */
5853 resize_resource_table (resource_table
*rt
, int cycles
)
5857 rt
->cycles
= cycles
;
5858 if (cycles
<= rt
->allocated_cycles
)
5861 old_cycles
= rt
->allocated_cycles
;
5862 rt
->allocated_cycles
= cycles
;
5864 rt
->units
= xrealloc (rt
->units
,
5865 rt
->allocated_cycles
* sizeof (unsigned char *));
5866 for (i
= 0; i
< old_cycles
; i
++)
5867 rt
->units
[i
] = xrealloc (rt
->units
[i
],
5868 rt
->num_units
* sizeof (unsigned char));
5869 for (i
= old_cycles
; i
< cycles
; i
++)
5870 rt
->units
[i
] = xcalloc (rt
->num_units
, sizeof (unsigned char));
5875 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5878 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5880 for (i
= 0; i
< uses
; i
++)
5882 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5883 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5884 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
5885 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
5886 if (copies_in_use
>= copies
)
5894 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5897 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5899 for (i
= 0; i
< uses
; i
++)
5901 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5902 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5903 /* Note that this allows resources to be oversubscribed. That's
5904 essential to the way the optional scheduler works.
5905 resources_available reports when a resource is over-subscribed,
5906 so it's easy to tell. */
5907 rt
->units
[stage
+ cycle
][unit
]++;
5913 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5916 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5918 for (i
= 0; i
< uses
; i
++)
5920 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5921 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5922 assert (rt
->units
[stage
+ cycle
][unit
] > 0);
5923 rt
->units
[stage
+ cycle
][unit
]--;
5928 /* Wrapper functions make parameterized resource reservation
5932 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
5934 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5940 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
5942 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5947 /* Note that this function does not check issue constraints, but
5948 solely whether the hardware is available to execute the given
5949 instructions together. It also doesn't check if the tinsns
5950 write the same state, or access the same tieports. That is
5951 checked by check_t1_t2_reads_and_writes. */
5954 resources_conflict (vliw_insn
*vinsn
)
5957 static resource_table
*rt
= NULL
;
5959 /* This is the most common case by far. Optimize it. */
5960 if (vinsn
->num_slots
== 1)
5965 xtensa_isa isa
= xtensa_default_isa
;
5966 rt
= new_resource_table
5967 (isa
, xtensa_isa_num_pipe_stages (isa
),
5968 xtensa_isa_num_funcUnits (isa
),
5969 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
5970 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
5971 opcode_funcUnit_use_unit
,
5972 opcode_funcUnit_use_stage
);
5975 clear_resource_table (rt
);
5977 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5979 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
5981 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
5988 /* finish_vinsn, emit_single_op and helper functions. */
5990 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
5991 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
5992 static void xg_assemble_vliw_tokens (vliw_insn
*);
5995 /* We have reached the end of a bundle; emit into the frag. */
5998 finish_vinsn (vliw_insn
*vinsn
)
6005 if (find_vinsn_conflicts (vinsn
))
6007 xg_clear_vinsn (vinsn
);
6011 /* First, find a format that works. */
6012 if (vinsn
->format
== XTENSA_UNDEFINED
)
6013 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6015 if (vinsn
->format
== XTENSA_UNDEFINED
)
6017 as_where (&file_name
, &line
);
6018 as_bad_where (file_name
, line
,
6019 _("couldn't find a valid instruction format"));
6020 fprintf (stderr
, _(" ops were: "));
6021 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6022 fprintf (stderr
, _(" %s;"),
6023 xtensa_opcode_name (xtensa_default_isa
,
6024 vinsn
->slots
[i
].opcode
));
6025 fprintf (stderr
, _("\n"));
6026 xg_clear_vinsn (vinsn
);
6030 if (vinsn
->num_slots
6031 != xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
))
6033 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
6034 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
6035 xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
),
6037 xg_clear_vinsn (vinsn
);
6041 if (resources_conflict (vinsn
))
6043 as_where (&file_name
, &line
);
6044 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6045 fprintf (stderr
, " ops were: ");
6046 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6047 fprintf (stderr
, " %s;",
6048 xtensa_opcode_name (xtensa_default_isa
,
6049 vinsn
->slots
[i
].opcode
));
6050 fprintf (stderr
, "\n");
6051 xg_clear_vinsn (vinsn
);
6055 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6057 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
6059 symbolS
*lit_sym
= NULL
;
6061 bfd_boolean e
= FALSE
;
6062 bfd_boolean saved_density
= density_supported
;
6064 /* We don't want to narrow ops inside multi-slot bundles. */
6065 if (vinsn
->num_slots
> 1)
6066 density_supported
= FALSE
;
6068 istack_init (&slotstack
);
6069 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
6071 vinsn
->slots
[i
].opcode
=
6072 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6074 vinsn
->slots
[i
].ntok
= 0;
6077 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
6083 density_supported
= saved_density
;
6087 xg_clear_vinsn (vinsn
);
6091 for (j
= 0; j
< slotstack
.ninsn
; j
++)
6093 TInsn
*insn
= &slotstack
.insn
[j
];
6094 if (insn
->insn_type
== ITYPE_LITERAL
)
6096 assert (lit_sym
== NULL
);
6097 lit_sym
= xg_assemble_literal (insn
);
6101 assert (insn
->insn_type
== ITYPE_INSN
);
6103 xg_resolve_literals (insn
, lit_sym
);
6104 if (j
!= slotstack
.ninsn
- 1)
6105 emit_single_op (insn
);
6109 if (vinsn
->num_slots
> 1)
6111 if (opcode_fits_format_slot
6112 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6115 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6119 emit_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6120 if (vinsn
->format
== XTENSA_UNDEFINED
)
6121 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6123 vinsn
->slots
[i
].opcode
6124 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6127 vinsn
->slots
[i
].ntok
= 0;
6132 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6133 vinsn
->format
= XTENSA_UNDEFINED
;
6138 /* Now check resource conflicts on the modified bundle. */
6139 if (resources_conflict (vinsn
))
6141 as_where (&file_name
, &line
);
6142 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6143 fprintf (stderr
, " ops were: ");
6144 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6145 fprintf (stderr
, " %s;",
6146 xtensa_opcode_name (xtensa_default_isa
,
6147 vinsn
->slots
[i
].opcode
));
6148 fprintf (stderr
, "\n");
6149 xg_clear_vinsn (vinsn
);
6153 /* First, find a format that works. */
6154 if (vinsn
->format
== XTENSA_UNDEFINED
)
6155 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6157 xg_assemble_vliw_tokens (vinsn
);
6159 xg_clear_vinsn (vinsn
);
6163 /* Given an vliw instruction, what conflicts are there in register
6164 usage and in writes to states and queues?
6166 This function does two things:
6167 1. Reports an error when a vinsn contains illegal combinations
6168 of writes to registers states or queues.
6169 2. Marks individual tinsns as not relaxable if the combination
6170 contains antidependencies.
6172 Job 2 handles things like swap semantics in instructions that need
6173 to be relaxed. For example,
6177 normally would be relaxed to
6182 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6184 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6186 then we can't relax it into
6189 { add a0, a1, a0 ; add a2, a0, a4 ; }
6191 because the value of a0 is trashed before the second add can read it. */
6193 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6196 find_vinsn_conflicts (vliw_insn
*vinsn
)
6200 xtensa_isa isa
= xtensa_default_isa
;
6202 assert (!past_xtensa_end
);
6204 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6206 TInsn
*op1
= &vinsn
->slots
[i
];
6207 if (op1
->is_specific_opcode
)
6208 op1
->keep_wide
= TRUE
;
6210 op1
->keep_wide
= FALSE
;
6213 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6215 TInsn
*op1
= &vinsn
->slots
[i
];
6217 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6220 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6224 TInsn
*op2
= &vinsn
->slots
[j
];
6225 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6226 switch (conflict_type
)
6229 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6230 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6231 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6234 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6235 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6236 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6239 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"),
6240 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6241 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6244 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"),
6245 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6246 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6249 /* Everything is OK. */
6252 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6253 || conflict_type
== 'a');
6260 as_bad (_("multiple branches or jumps in the same bundle"));
6268 /* Check how the state used by t1 and t2 relate.
6271 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6272 case B: no relationship between what is read and written (both could
6273 read the same reg though)
6274 case C: t1 writes a register t2 writes (a register conflict within a
6276 case D: t1 writes a state that t2 also writes
6277 case E: t1 writes a tie queue that t2 also writes
6278 case F: two volatile queue accesses
6282 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6284 xtensa_isa isa
= xtensa_default_isa
;
6285 xtensa_regfile t1_regfile
, t2_regfile
;
6287 int t1_base_reg
, t1_last_reg
;
6288 int t2_base_reg
, t2_last_reg
;
6289 char t1_inout
, t2_inout
;
6291 char conflict
= 'b';
6296 bfd_boolean t1_volatile
= FALSE
;
6297 bfd_boolean t2_volatile
= FALSE
;
6299 /* Check registers. */
6300 for (j
= 0; j
< t2
->ntok
; j
++)
6302 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6305 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6306 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6307 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6309 for (i
= 0; i
< t1
->ntok
; i
++)
6311 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6314 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6316 if (t1_regfile
!= t2_regfile
)
6319 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6320 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6322 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6323 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6325 if (t1_inout
== 'm' || t1_inout
== 'o'
6326 || t2_inout
== 'm' || t2_inout
== 'o')
6333 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6334 t1_last_reg
= (t1_base_reg
6335 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6337 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6339 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6341 if (t1_reg
!= t2_reg
)
6344 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6350 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6356 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6364 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6365 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6366 for (j
= 0; j
< t2_states
; j
++)
6368 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6369 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6370 for (i
= 0; i
< t1_states
; i
++)
6372 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6373 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6377 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6383 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6389 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6394 /* Check tieports. */
6395 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6396 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6397 for (j
= 0; j
< t2_interfaces
; j
++)
6399 xtensa_interface t2_int
6400 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6401 int t2_class
= xtensa_interface_class_id (isa
, t2_int
);
6403 t2_inout
= xtensa_interface_inout (isa
, t2_int
);
6404 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1)
6407 for (i
= 0; i
< t1_interfaces
; i
++)
6409 xtensa_interface t1_int
6410 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6411 int t1_class
= xtensa_interface_class_id (isa
, t1_int
);
6413 t1_inout
= xtensa_interface_inout (isa
, t1_int
);
6414 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1)
6417 if (t1_volatile
&& t2_volatile
&& (t1_class
== t2_class
))
6420 if (t1_int
!= t2_int
)
6423 if (t2_inout
== 'i' && t1_inout
== 'o')
6429 if (t1_inout
== 'i' && t2_inout
== 'o')
6435 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6444 static xtensa_format
6445 xg_find_narrowest_format (vliw_insn
*vinsn
)
6447 /* Right now we assume that the ops within the vinsn are properly
6448 ordered for the slots that the programmer wanted them in. In
6449 other words, we don't rearrange the ops in hopes of finding a
6450 better format. The scheduler handles that. */
6452 xtensa_isa isa
= xtensa_default_isa
;
6453 xtensa_format format
;
6454 vliw_insn v_copy
= *vinsn
;
6455 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6457 if (vinsn
->num_slots
== 1)
6458 return xg_get_single_format (vinsn
->slots
[0].opcode
);
6460 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6463 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6467 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6469 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6471 v_copy
.slots
[slot
].opcode
=
6472 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6473 v_copy
.slots
[slot
].ntok
= 0;
6476 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6479 else if (v_copy
.num_slots
> 1)
6482 /* Try the widened version. */
6483 if (!v_copy
.slots
[slot
].keep_wide
6484 && !v_copy
.slots
[slot
].is_specific_opcode
6485 && xg_is_single_relaxable_insn (&v_copy
.slots
[slot
],
6487 && opcode_fits_format_slot (widened
.opcode
,
6490 v_copy
.slots
[slot
] = widened
;
6495 if (fit
== v_copy
.num_slots
)
6498 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6499 vinsn
->format
= format
;
6505 if (format
== xtensa_isa_num_formats (isa
))
6506 return XTENSA_UNDEFINED
;
6512 /* Return the additional space needed in a frag
6513 for possible relaxations of any ops in a VLIW insn.
6514 Also fill out the relaxations that might be required of
6515 each tinsn in the vinsn. */
6518 relaxation_requirements (vliw_insn
*vinsn
, bfd_boolean
*pfinish_frag
)
6520 bfd_boolean finish_frag
= FALSE
;
6521 int extra_space
= 0;
6524 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6526 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6527 if (!tinsn_has_symbolic_operands (tinsn
))
6529 /* A narrow instruction could be widened later to help
6530 alignment issues. */
6531 if (xg_is_single_relaxable_insn (tinsn
, 0, TRUE
)
6532 && !tinsn
->is_specific_opcode
6533 && vinsn
->num_slots
== 1)
6535 /* Difference in bytes between narrow and wide insns... */
6537 tinsn
->subtype
= RELAX_NARROW
;
6542 if (workaround_b_j_loop_end
6543 && tinsn
->opcode
== xtensa_jx_opcode
6544 && use_transform ())
6546 /* Add 2 of these. */
6547 extra_space
+= 3; /* for the nop size */
6548 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6551 /* Need to assemble it with space for the relocation. */
6552 if (xg_is_relaxable_insn (tinsn
, 0)
6553 && !tinsn
->is_specific_opcode
)
6555 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6556 int max_literal_size
=
6557 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6559 tinsn
->literal_space
= max_literal_size
;
6561 tinsn
->subtype
= RELAX_IMMED
;
6562 extra_space
+= max_size
;
6566 /* A fix record will be added for this instruction prior
6567 to relaxation, so make it end the frag. */
6572 *pfinish_frag
= finish_frag
;
6578 bundle_tinsn (TInsn
*tinsn
, vliw_insn
*vinsn
)
6580 xtensa_isa isa
= xtensa_default_isa
;
6581 int slot
, chosen_slot
;
6583 vinsn
->format
= xg_get_single_format (tinsn
->opcode
);
6584 assert (vinsn
->format
!= XTENSA_UNDEFINED
);
6585 vinsn
->num_slots
= xtensa_format_num_slots (isa
, vinsn
->format
);
6587 chosen_slot
= xg_get_single_slot (tinsn
->opcode
);
6588 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6590 if (slot
== chosen_slot
)
6591 vinsn
->slots
[slot
] = *tinsn
;
6594 vinsn
->slots
[slot
].opcode
=
6595 xtensa_format_slot_nop_opcode (isa
, vinsn
->format
, slot
);
6596 vinsn
->slots
[slot
].ntok
= 0;
6597 vinsn
->slots
[slot
].insn_type
= ITYPE_INSN
;
6604 emit_single_op (TInsn
*orig_insn
)
6607 IStack istack
; /* put instructions into here */
6608 symbolS
*lit_sym
= NULL
;
6609 symbolS
*label_sym
= NULL
;
6611 istack_init (&istack
);
6613 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6614 Because the scheduling and bundling characteristics of movi and
6615 l32r or const16 are so different, we can do much better if we relax
6616 it prior to scheduling and bundling, rather than after. */
6617 if ((orig_insn
->opcode
== xtensa_movi_opcode
6618 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
6619 && !cur_vinsn
.inside_bundle
6620 && (orig_insn
->tok
[1].X_op
== O_symbol
6621 || orig_insn
->tok
[1].X_op
== O_pltrel
)
6622 && !orig_insn
->is_specific_opcode
&& use_transform ())
6623 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
6625 if (xg_expand_assembly_insn (&istack
, orig_insn
))
6628 for (i
= 0; i
< istack
.ninsn
; i
++)
6630 TInsn
*insn
= &istack
.insn
[i
];
6631 switch (insn
->insn_type
)
6634 assert (lit_sym
== NULL
);
6635 lit_sym
= xg_assemble_literal (insn
);
6639 static int relaxed_sym_idx
= 0;
6640 char *label
= xmalloc (strlen (FAKE_LABEL_NAME
) + 12);
6641 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
6643 assert (label_sym
== NULL
);
6644 label_sym
= symbol_find_or_make (label
);
6653 xg_resolve_literals (insn
, lit_sym
);
6655 xg_resolve_labels (insn
, label_sym
);
6657 bundle_tinsn (insn
, &v
);
6672 total_frag_text_expansion (fragS
*fragP
)
6675 int total_expansion
= 0;
6677 for (slot
= 0; slot
< MAX_SLOTS
; slot
++)
6678 total_expansion
+= fragP
->tc_frag_data
.text_expansion
[slot
];
6680 return total_expansion
;
6684 /* Emit a vliw instruction to the current fragment. */
6687 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
6689 bfd_boolean finish_frag
;
6690 bfd_boolean is_jump
= FALSE
;
6691 bfd_boolean is_branch
= FALSE
;
6692 xtensa_isa isa
= xtensa_default_isa
;
6698 unsigned current_line
, best_linenum
;
6701 best_linenum
= UINT_MAX
;
6703 if (generating_literals
)
6705 static int reported
= 0;
6707 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
6708 _("cannot assemble into a literal fragment"));
6715 if (frag_now_fix () != 0
6716 && (! frag_now
->tc_frag_data
.is_insn
6717 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6718 || !use_transform () != frag_now
->tc_frag_data
.is_no_transform
6719 || (directive_state
[directive_longcalls
]
6720 != frag_now
->tc_frag_data
.use_longcalls
)
6721 || (directive_state
[directive_absolute_literals
]
6722 != frag_now
->tc_frag_data
.use_absolute_literals
)))
6724 frag_wane (frag_now
);
6726 xtensa_set_frag_assembly_state (frag_now
);
6729 if (workaround_a0_b_retw
6730 && vinsn
->num_slots
== 1
6731 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
6732 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
6733 && use_transform ())
6735 has_a0_b_retw
= TRUE
;
6737 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
6738 After the first assembly pass we will check all of them and
6739 add a nop if needed. */
6740 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6741 frag_var (rs_machine_dependent
, 4, 4,
6742 RELAX_ADD_NOP_IF_A0_B_RETW
,
6743 frag_now
->fr_symbol
,
6744 frag_now
->fr_offset
,
6746 xtensa_set_frag_assembly_state (frag_now
);
6747 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6748 frag_var (rs_machine_dependent
, 4, 4,
6749 RELAX_ADD_NOP_IF_A0_B_RETW
,
6750 frag_now
->fr_symbol
,
6751 frag_now
->fr_offset
,
6753 xtensa_set_frag_assembly_state (frag_now
);
6756 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6758 /* See if the instruction implies an aligned section. */
6759 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[i
].opcode
) == 1)
6760 record_alignment (now_seg
, 2);
6762 /* Also determine the best line number for debug info. */
6763 best_linenum
= vinsn
->slots
[i
].linenum
< best_linenum
6764 ? vinsn
->slots
[i
].linenum
: best_linenum
;
6767 /* Special cases for instructions that force an alignment... */
6768 /* None of these opcodes are bundle-able. */
6769 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
6773 /* Remember the symbol that marks the end of the loop in the frag
6774 that marks the start of the loop. This way we can easily find
6775 the end of the loop at the beginning, without adding special code
6776 to mark the loop instructions themselves. */
6777 symbolS
*target_sym
= NULL
;
6778 if (vinsn
->slots
[0].tok
[1].X_op
== O_symbol
)
6779 target_sym
= vinsn
->slots
[0].tok
[1].X_add_symbol
;
6781 xtensa_set_frag_assembly_state (frag_now
);
6782 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6784 max_fill
= get_text_align_max_fill_size
6785 (get_text_align_power (xtensa_fetch_width
),
6786 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
6788 if (use_transform ())
6789 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
6790 RELAX_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
6792 frag_var (rs_machine_dependent
, 0, 0,
6793 RELAX_CHECK_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
6794 xtensa_set_frag_assembly_state (frag_now
);
6797 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
6798 && !vinsn
->slots
[0].is_specific_opcode
)
6800 xtensa_mark_literal_pool_location ();
6801 xtensa_move_labels (frag_now
, 0);
6802 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
6805 if (vinsn
->num_slots
== 1)
6807 if (workaround_a0_b_retw
&& use_transform ())
6808 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
6809 is_register_writer (&vinsn
->slots
[0], "a", 0));
6811 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
6812 is_bad_loopend_opcode (&vinsn
->slots
[0]));
6815 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
6817 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
6819 extra_space
= relaxation_requirements (vinsn
, &finish_frag
);
6821 /* vinsn_to_insnbuf will produce the error. */
6822 if (vinsn
->format
!= XTENSA_UNDEFINED
)
6824 f
= frag_more (insn_size
+ extra_space
);
6825 xtensa_set_frag_assembly_state (frag_now
);
6826 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6829 vinsn_to_insnbuf (vinsn
, f
, frag_now
, FALSE
);
6830 if (vinsn
->format
== XTENSA_UNDEFINED
)
6833 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, (unsigned char *) f
, 0);
6835 /* Temporarily set the logical line number to the one we want to appear
6836 in the debug information. */
6837 as_where (¤t_file
, ¤t_line
);
6838 new_logical_line (current_file
, best_linenum
);
6839 dwarf2_emit_insn (insn_size
+ extra_space
);
6840 new_logical_line (current_file
, current_line
);
6842 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6844 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6845 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
6846 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
6847 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
6848 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
6849 if (tinsn
->literal_space
!= 0)
6850 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
6852 if (tinsn
->subtype
== RELAX_NARROW
)
6853 assert (vinsn
->num_slots
== 1);
6854 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
6856 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
6859 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->offset
6860 || tinsn
->literal_frag
|| is_jump
|| is_branch
)
6864 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6865 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
6869 frag_variant (rs_machine_dependent
,
6870 extra_space
, extra_space
, RELAX_SLOTS
,
6871 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
6872 xtensa_set_frag_assembly_state (frag_now
);
6875 /* Special cases for loops:
6876 close_loop_end should be inserted AFTER short_loop.
6877 Make sure that CLOSE loops are processed BEFORE short_loops
6878 when converting them. */
6880 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
6881 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1
6882 && !vinsn
->slots
[0].is_specific_opcode
)
6884 if (workaround_short_loop
&& use_transform ())
6886 maybe_has_short_loop
= TRUE
;
6887 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6888 frag_var (rs_machine_dependent
, 4, 4,
6889 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6890 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6891 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6892 frag_var (rs_machine_dependent
, 4, 4,
6893 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6894 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6897 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
6898 loop at least 12 bytes away from another loop's end. */
6899 if (workaround_close_loop_end
&& use_transform ())
6901 maybe_has_close_loop_end
= TRUE
;
6902 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6903 frag_var (rs_machine_dependent
, 12, 12,
6904 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
6905 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6909 if (use_transform ())
6913 assert (finish_frag
);
6914 frag_var (rs_machine_dependent
,
6915 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6917 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6918 xtensa_set_frag_assembly_state (frag_now
);
6920 else if (is_branch
&& do_align_targets ())
6922 assert (finish_frag
);
6923 frag_var (rs_machine_dependent
,
6924 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6925 RELAX_MAYBE_UNREACHABLE
,
6926 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6927 xtensa_set_frag_assembly_state (frag_now
);
6928 frag_var (rs_machine_dependent
,
6930 RELAX_MAYBE_DESIRE_ALIGN
,
6931 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6932 xtensa_set_frag_assembly_state (frag_now
);
6936 /* Now, if the original opcode was a call... */
6937 if (do_align_targets ()
6938 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
6940 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
6941 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6942 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
6943 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6944 xtensa_set_frag_assembly_state (frag_now
);
6947 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6949 frag_wane (frag_now
);
6951 xtensa_set_frag_assembly_state (frag_now
);
6956 /* xtensa_end and helper functions. */
6958 static void xtensa_cleanup_align_frags (void);
6959 static void xtensa_fix_target_frags (void);
6960 static void xtensa_mark_narrow_branches (void);
6961 static void xtensa_mark_zcl_first_insns (void);
6962 static void xtensa_mark_difference_of_two_symbols (void);
6963 static void xtensa_fix_a0_b_retw_frags (void);
6964 static void xtensa_fix_b_j_loop_end_frags (void);
6965 static void xtensa_fix_close_loop_end_frags (void);
6966 static void xtensa_fix_short_loop_frags (void);
6967 static void xtensa_sanity_check (void);
6968 static void xtensa_add_config_info (void);
6973 directive_balance ();
6974 xtensa_flush_pending_output ();
6976 past_xtensa_end
= TRUE
;
6978 xtensa_move_literals ();
6980 xtensa_reorder_segments ();
6981 xtensa_cleanup_align_frags ();
6982 xtensa_fix_target_frags ();
6983 if (workaround_a0_b_retw
&& has_a0_b_retw
)
6984 xtensa_fix_a0_b_retw_frags ();
6985 if (workaround_b_j_loop_end
)
6986 xtensa_fix_b_j_loop_end_frags ();
6988 /* "close_loop_end" should be processed BEFORE "short_loop". */
6989 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
6990 xtensa_fix_close_loop_end_frags ();
6992 if (workaround_short_loop
&& maybe_has_short_loop
)
6993 xtensa_fix_short_loop_frags ();
6995 xtensa_mark_narrow_branches ();
6996 xtensa_mark_zcl_first_insns ();
6998 xtensa_sanity_check ();
7000 xtensa_add_config_info ();
7005 xtensa_cleanup_align_frags (void)
7010 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7011 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7014 /* Walk over all of the fragments in a subsection. */
7015 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7017 if ((fragP
->fr_type
== rs_align
7018 || fragP
->fr_type
== rs_align_code
7019 || (fragP
->fr_type
== rs_machine_dependent
7020 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
7021 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
7022 && fragP
->fr_fix
== 0)
7024 fragS
*next
= fragP
->fr_next
;
7027 && next
->fr_fix
== 0
7028 && next
->fr_type
== rs_machine_dependent
7029 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7032 next
= next
->fr_next
;
7035 /* If we don't widen branch targets, then they
7036 will be easier to align. */
7037 if (fragP
->tc_frag_data
.is_branch_target
7038 && fragP
->fr_opcode
== fragP
->fr_literal
7039 && fragP
->fr_type
== rs_machine_dependent
7040 && fragP
->fr_subtype
== RELAX_SLOTS
7041 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
7043 if (fragP
->fr_type
== rs_machine_dependent
7044 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
7045 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
7051 /* Re-process all of the fragments looking to convert all of the
7052 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
7053 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7054 Otherwise, convert to a .fill 0. */
7057 xtensa_fix_target_frags (void)
7062 /* When this routine is called, all of the subsections are still intact
7063 so we walk over subsections instead of sections. */
7064 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7065 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7069 /* Walk over all of the fragments in a subsection. */
7070 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7072 if (fragP
->fr_type
== rs_machine_dependent
7073 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7075 if (next_frag_is_branch_target (fragP
))
7076 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7085 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
7088 xtensa_mark_narrow_branches (void)
7093 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7094 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7097 /* Walk over all of the fragments in a subsection. */
7098 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7100 if (fragP
->fr_type
== rs_machine_dependent
7101 && fragP
->fr_subtype
== RELAX_SLOTS
7102 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7106 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7107 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
7109 if (vinsn
.num_slots
== 1
7110 && xtensa_opcode_is_branch (xtensa_default_isa
,
7111 vinsn
.slots
[0].opcode
) == 1
7112 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
7113 && is_narrow_branch_guaranteed_in_range (fragP
,
7116 fragP
->fr_subtype
= RELAX_SLOTS
;
7117 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
7118 fragP
->tc_frag_data
.is_aligning_branch
= 1;
7126 /* A branch is typically widened only when its target is out of
7127 range. However, we would like to widen them to align a subsequent
7128 branch target when possible.
7130 Because the branch relaxation code is so convoluted, the optimal solution
7131 (combining the two cases) is difficult to get right in all circumstances.
7132 We therefore go with an "almost as good" solution, where we only
7133 use for alignment narrow branches that definitely will not expand to a
7134 jump and a branch. These functions find and mark these cases. */
7136 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
7137 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7138 We start counting beginning with the frag after the 2-byte branch, so the
7139 maximum offset is (4 - 2) + 63 = 65. */
7140 #define MAX_IMMED6 65
7142 static offsetT
unrelaxed_frag_max_size (fragS
*);
7145 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
7147 const expressionS
*expr
= &tinsn
->tok
[1];
7148 symbolS
*symbolP
= expr
->X_add_symbol
;
7149 offsetT max_distance
= expr
->X_add_number
;
7152 if (expr
->X_op
!= O_symbol
)
7155 target_frag
= symbol_get_frag (symbolP
);
7157 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
7158 if (is_branch_jmp_to_next (tinsn
, fragP
))
7161 /* The branch doesn't branch over it's own frag,
7162 but over the subsequent ones. */
7163 fragP
= fragP
->fr_next
;
7164 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
7166 max_distance
+= unrelaxed_frag_max_size (fragP
);
7167 fragP
= fragP
->fr_next
;
7169 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
7176 xtensa_mark_zcl_first_insns (void)
7181 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7182 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7185 /* Walk over all of the fragments in a subsection. */
7186 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7188 if (fragP
->fr_type
== rs_machine_dependent
7189 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7190 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7192 /* Find the loop frag. */
7193 fragS
*targ_frag
= next_non_empty_frag (fragP
);
7194 /* Find the first insn frag. */
7195 targ_frag
= next_non_empty_frag (targ_frag
);
7197 /* Of course, sometimes (mostly for toy test cases) a
7198 zero-cost loop instruction is the last in a section. */
7201 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
7202 /* Do not widen a frag that is the first instruction of a
7203 zero-cost loop. It makes that loop harder to align. */
7204 if (targ_frag
->fr_type
== rs_machine_dependent
7205 && targ_frag
->fr_subtype
== RELAX_SLOTS
7206 && (targ_frag
->tc_frag_data
.slot_subtypes
[0]
7209 if (targ_frag
->tc_frag_data
.is_aligning_branch
)
7210 targ_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
7213 frag_wane (targ_frag
);
7214 targ_frag
->tc_frag_data
.slot_subtypes
[0] = 0;
7218 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
7226 /* Some difference-of-symbols expressions make it out to the linker. Some
7227 don't. If one does, then the linker can optimize between the two labels.
7228 If it doesn't, then the linker shouldn't. */
7231 xtensa_mark_difference_of_two_symbols (void)
7235 for (expr_sym
= expr_symbols
; expr_sym
;
7236 expr_sym
= symbol_get_tc (expr_sym
)->next_expr_symbol
)
7238 expressionS
*expr
= symbol_get_value_expression (expr_sym
);
7240 if (expr
->X_op
== O_subtract
)
7242 symbolS
*left
= expr
->X_add_symbol
;
7243 symbolS
*right
= expr
->X_op_symbol
;
7245 /* Difference of two symbols not in the same section
7246 are handled with relocations in the linker. */
7247 if (S_GET_SEGMENT (left
) == S_GET_SEGMENT (right
))
7252 if (symbol_get_frag (left
)->fr_address
7253 <= symbol_get_frag (right
)->fr_address
)
7255 start
= symbol_get_frag (left
);
7256 end
= symbol_get_frag (right
);
7260 start
= symbol_get_frag (right
);
7261 end
= symbol_get_frag (left
);
7265 start
->tc_frag_data
.is_no_transform
= 1;
7266 start
= start
->fr_next
;
7268 while (start
&& start
->fr_address
< end
->fr_address
);
7275 /* Re-process all of the fragments looking to convert all of the
7276 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7277 conditional branch or a retw/retw.n, convert this frag to one that
7278 will generate a NOP. In any case close it off with a .fill 0. */
7280 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
7283 xtensa_fix_a0_b_retw_frags (void)
7288 /* When this routine is called, all of the subsections are still intact
7289 so we walk over subsections instead of sections. */
7290 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7291 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7295 /* Walk over all of the fragments in a subsection. */
7296 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7298 if (fragP
->fr_type
== rs_machine_dependent
7299 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
7301 if (next_instrs_are_b_retw (fragP
))
7303 if (fragP
->tc_frag_data
.is_no_transform
)
7304 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7306 relax_frag_add_nop (fragP
);
7316 next_instrs_are_b_retw (fragS
*fragP
)
7318 xtensa_opcode opcode
;
7320 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
7321 static xtensa_insnbuf insnbuf
= NULL
;
7322 static xtensa_insnbuf slotbuf
= NULL
;
7323 xtensa_isa isa
= xtensa_default_isa
;
7326 bfd_boolean branch_seen
= FALSE
;
7330 insnbuf
= xtensa_insnbuf_alloc (isa
);
7331 slotbuf
= xtensa_insnbuf_alloc (isa
);
7334 if (next_fragP
== NULL
)
7337 /* Check for the conditional branch. */
7338 xtensa_insnbuf_from_chars
7339 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7340 fmt
= xtensa_format_decode (isa
, insnbuf
);
7341 if (fmt
== XTENSA_UNDEFINED
)
7344 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7346 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
7347 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
7349 branch_seen
= (branch_seen
7350 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
7356 offset
+= xtensa_format_length (isa
, fmt
);
7357 if (offset
== next_fragP
->fr_fix
)
7359 next_fragP
= next_non_empty_frag (next_fragP
);
7363 if (next_fragP
== NULL
)
7366 /* Check for the retw/retw.n. */
7367 xtensa_insnbuf_from_chars
7368 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7369 fmt
= xtensa_format_decode (isa
, insnbuf
);
7371 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
7372 have no problems. */
7373 if (fmt
== XTENSA_UNDEFINED
7374 || xtensa_format_num_slots (isa
, fmt
) != 1)
7377 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
7378 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
7380 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
7387 /* Re-process all of the fragments looking to convert all of the
7388 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
7389 loop end label, convert this frag to one that will generate a NOP.
7390 In any case close it off with a .fill 0. */
7392 static bfd_boolean
next_instr_is_loop_end (fragS
*);
7395 xtensa_fix_b_j_loop_end_frags (void)
7400 /* When this routine is called, all of the subsections are still intact
7401 so we walk over subsections instead of sections. */
7402 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7403 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7407 /* Walk over all of the fragments in a subsection. */
7408 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7410 if (fragP
->fr_type
== rs_machine_dependent
7411 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
7413 if (next_instr_is_loop_end (fragP
))
7415 if (fragP
->tc_frag_data
.is_no_transform
)
7416 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
7418 relax_frag_add_nop (fragP
);
7428 next_instr_is_loop_end (fragS
*fragP
)
7430 const fragS
*next_fragP
;
7432 if (next_frag_is_loop_target (fragP
))
7435 next_fragP
= next_non_empty_frag (fragP
);
7436 if (next_fragP
== NULL
)
7439 if (!next_frag_is_loop_target (next_fragP
))
7442 /* If the size is >= 3 then there is more than one instruction here.
7443 The hardware bug will not fire. */
7444 if (next_fragP
->fr_fix
> 3)
7451 /* Re-process all of the fragments looking to convert all of the
7452 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
7453 not MY loop's loop end within 12 bytes, add enough nops here to
7454 make it at least 12 bytes away. In any case close it off with a
7457 static offsetT min_bytes_to_other_loop_end
7458 (fragS
*, fragS
*, offsetT
);
7461 xtensa_fix_close_loop_end_frags (void)
7466 /* When this routine is called, all of the subsections are still intact
7467 so we walk over subsections instead of sections. */
7468 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7469 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7473 fragS
*current_target
= NULL
;
7475 /* Walk over all of the fragments in a subsection. */
7476 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7478 if (fragP
->fr_type
== rs_machine_dependent
7479 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7480 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7481 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7484 && fragP
->fr_type
== rs_machine_dependent
7485 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
7488 int bytes_added
= 0;
7490 #define REQUIRED_LOOP_DIVIDING_BYTES 12
7491 /* Max out at 12. */
7492 min_bytes
= min_bytes_to_other_loop_end
7493 (fragP
->fr_next
, current_target
, REQUIRED_LOOP_DIVIDING_BYTES
);
7495 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
7497 if (fragP
->tc_frag_data
.is_no_transform
)
7498 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
7501 while (min_bytes
+ bytes_added
7502 < REQUIRED_LOOP_DIVIDING_BYTES
)
7506 if (fragP
->fr_var
< length
)
7507 as_fatal (_("fr_var %lu < length %d"),
7508 (long) fragP
->fr_var
, length
);
7511 assemble_nop (length
,
7512 fragP
->fr_literal
+ fragP
->fr_fix
);
7513 fragP
->fr_fix
+= length
;
7514 fragP
->fr_var
-= length
;
7516 bytes_added
+= length
;
7522 assert (fragP
->fr_type
!= rs_machine_dependent
7523 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
7529 static offsetT
unrelaxed_frag_min_size (fragS
*);
7532 min_bytes_to_other_loop_end (fragS
*fragP
,
7533 fragS
*current_target
,
7537 fragS
*current_fragP
;
7539 for (current_fragP
= fragP
;
7541 current_fragP
= current_fragP
->fr_next
)
7543 if (current_fragP
->tc_frag_data
.is_loop_target
7544 && current_fragP
!= current_target
)
7547 offset
+= unrelaxed_frag_min_size (current_fragP
);
7549 if (offset
>= max_size
)
7557 unrelaxed_frag_min_size (fragS
*fragP
)
7559 offsetT size
= fragP
->fr_fix
;
7561 /* Add fill size. */
7562 if (fragP
->fr_type
== rs_fill
)
7563 size
+= fragP
->fr_offset
;
7570 unrelaxed_frag_max_size (fragS
*fragP
)
7572 offsetT size
= fragP
->fr_fix
;
7573 switch (fragP
->fr_type
)
7576 /* Empty frags created by the obstack allocation scheme
7577 end up with type 0. */
7582 size
+= fragP
->fr_offset
;
7590 /* No further adjustments needed. */
7592 case rs_machine_dependent
:
7593 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
7594 size
+= fragP
->fr_var
;
7597 /* We had darn well better know how big it is. */
7606 /* Re-process all of the fragments looking to convert all
7607 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
7610 1) the instruction size count to the loop end label
7611 is too short (<= 2 instructions),
7612 2) loop has a jump or branch in it
7615 1) workaround_all_short_loops is TRUE
7616 2) The generating loop was a 'loopgtz' or 'loopnez'
7617 3) the instruction size count to the loop end label is too short
7619 then convert this frag (and maybe the next one) to generate a NOP.
7620 In any case close it off with a .fill 0. */
7622 static int count_insns_to_loop_end (fragS
*, bfd_boolean
, int);
7623 static bfd_boolean
branch_before_loop_end (fragS
*);
7626 xtensa_fix_short_loop_frags (void)
7631 /* When this routine is called, all of the subsections are still intact
7632 so we walk over subsections instead of sections. */
7633 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7634 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7637 fragS
*current_target
= NULL
;
7638 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
7640 /* Walk over all of the fragments in a subsection. */
7641 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7643 if (fragP
->fr_type
== rs_machine_dependent
7644 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7645 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7648 fragS
*loop_frag
= next_non_empty_frag (fragP
);
7649 tinsn_from_chars (&t_insn
, loop_frag
->fr_opcode
, 0);
7650 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7651 current_opcode
= t_insn
.opcode
;
7652 assert (xtensa_opcode_is_loop (xtensa_default_isa
,
7653 current_opcode
) == 1);
7656 if (fragP
->fr_type
== rs_machine_dependent
7657 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7659 if (count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3) < 3
7660 && (branch_before_loop_end (fragP
->fr_next
)
7661 || (workaround_all_short_loops
7662 && current_opcode
!= XTENSA_UNDEFINED
7663 && current_opcode
!= xtensa_loop_opcode
)))
7665 if (fragP
->tc_frag_data
.is_no_transform
)
7666 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
7668 relax_frag_add_nop (fragP
);
7677 static int unrelaxed_frag_min_insn_count (fragS
*);
7680 count_insns_to_loop_end (fragS
*base_fragP
,
7681 bfd_boolean count_relax_add
,
7684 fragS
*fragP
= NULL
;
7689 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
7691 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
7692 if (insn_count
>= max_count
)
7695 if (count_relax_add
)
7697 if (fragP
->fr_type
== rs_machine_dependent
7698 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7700 /* In order to add the appropriate number of
7701 NOPs, we count an instruction for downstream
7704 if (insn_count
>= max_count
)
7714 unrelaxed_frag_min_insn_count (fragS
*fragP
)
7716 xtensa_isa isa
= xtensa_default_isa
;
7717 static xtensa_insnbuf insnbuf
= NULL
;
7721 if (!fragP
->tc_frag_data
.is_insn
)
7725 insnbuf
= xtensa_insnbuf_alloc (isa
);
7727 /* Decode the fixed instructions. */
7728 while (offset
< fragP
->fr_fix
)
7732 xtensa_insnbuf_from_chars
7733 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7734 fmt
= xtensa_format_decode (isa
, insnbuf
);
7736 if (fmt
== XTENSA_UNDEFINED
)
7738 as_fatal (_("undecodable instruction in instruction frag"));
7741 offset
+= xtensa_format_length (isa
, fmt
);
7749 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
7752 branch_before_loop_end (fragS
*base_fragP
)
7756 for (fragP
= base_fragP
;
7757 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
7758 fragP
= fragP
->fr_next
)
7760 if (unrelaxed_frag_has_b_j (fragP
))
7768 unrelaxed_frag_has_b_j (fragS
*fragP
)
7770 static xtensa_insnbuf insnbuf
= NULL
;
7771 xtensa_isa isa
= xtensa_default_isa
;
7774 if (!fragP
->tc_frag_data
.is_insn
)
7778 insnbuf
= xtensa_insnbuf_alloc (isa
);
7780 /* Decode the fixed instructions. */
7781 while (offset
< fragP
->fr_fix
)
7786 xtensa_insnbuf_from_chars
7787 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7788 fmt
= xtensa_format_decode (isa
, insnbuf
);
7789 if (fmt
== XTENSA_UNDEFINED
)
7792 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7794 xtensa_opcode opcode
=
7795 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
7796 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
7797 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
7800 offset
+= xtensa_format_length (isa
, fmt
);
7806 /* Checks to be made after initial assembly but before relaxation. */
7808 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
7809 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
7812 xtensa_sanity_check (void)
7819 as_where (&file_name
, &line
);
7820 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7821 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7825 /* Walk over all of the fragments in a subsection. */
7826 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7828 if (fragP
->fr_type
== rs_machine_dependent
7829 && fragP
->fr_subtype
== RELAX_SLOTS
7830 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7832 static xtensa_insnbuf insnbuf
= NULL
;
7835 if (fragP
->fr_opcode
!= NULL
)
7838 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7839 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7840 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
7842 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7843 t_insn
.opcode
) == 1)
7845 if (is_empty_loop (&t_insn
, fragP
))
7847 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7848 as_bad (_("invalid empty loop"));
7850 if (!is_local_forward_loop (&t_insn
, fragP
))
7852 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7853 as_bad (_("loop target does not follow "
7854 "loop instruction in section"));
7861 new_logical_line (file_name
, line
);
7865 #define LOOP_IMMED_OPN 1
7867 /* Return TRUE if the loop target is the next non-zero fragment. */
7870 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
7872 const expressionS
*expr
;
7876 if (insn
->insn_type
!= ITYPE_INSN
)
7879 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
7882 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7885 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7887 if (expr
->X_op
!= O_symbol
)
7890 symbolP
= expr
->X_add_symbol
;
7894 if (symbol_get_frag (symbolP
) == NULL
)
7897 if (S_GET_VALUE (symbolP
) != 0)
7900 /* Walk through the zero-size fragments from this one. If we find
7901 the target fragment, then this is a zero-size loop. */
7903 for (next_fragP
= fragP
->fr_next
;
7905 next_fragP
= next_fragP
->fr_next
)
7907 if (next_fragP
== symbol_get_frag (symbolP
))
7909 if (next_fragP
->fr_fix
!= 0)
7917 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
7919 const expressionS
*expr
;
7923 if (insn
->insn_type
!= ITYPE_INSN
)
7926 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
7929 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7932 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7934 if (expr
->X_op
!= O_symbol
)
7937 symbolP
= expr
->X_add_symbol
;
7941 if (symbol_get_frag (symbolP
) == NULL
)
7944 /* Walk through fragments until we find the target.
7945 If we do not find the target, then this is an invalid loop. */
7947 for (next_fragP
= fragP
->fr_next
;
7949 next_fragP
= next_fragP
->fr_next
)
7951 if (next_fragP
== symbol_get_frag (symbolP
))
7959 #define XTINFO_NAME "Xtensa_Info"
7960 #define XTINFO_NAMESZ 12
7961 #define XTINFO_TYPE 1
7964 xtensa_add_config_info (void)
7970 info_sec
= subseg_new (".xtensa.info", 0);
7971 bfd_set_section_flags (stdoutput
, info_sec
, SEC_HAS_CONTENTS
| SEC_READONLY
);
7973 data
= xmalloc (100);
7974 sprintf (data
, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n",
7975 XSHAL_USE_ABSOLUTE_LITERALS
, XSHAL_ABI
);
7976 sz
= strlen (data
) + 1;
7978 /* Add enough null terminators to pad to a word boundary. */
7981 while ((sz
& 3) != 0);
7983 /* Follow the standard note section layout:
7984 First write the length of the name string. */
7986 md_number_to_chars (p
, (valueT
) XTINFO_NAMESZ
, 4);
7988 /* Next comes the length of the "descriptor", i.e., the actual data. */
7990 md_number_to_chars (p
, (valueT
) sz
, 4);
7992 /* Write the note type. */
7994 md_number_to_chars (p
, (valueT
) XTINFO_TYPE
, 4);
7996 /* Write the name field. */
7997 p
= frag_more (XTINFO_NAMESZ
);
7998 memcpy (p
, XTINFO_NAME
, XTINFO_NAMESZ
);
8000 /* Finally, write the descriptor. */
8002 memcpy (p
, data
, sz
);
8008 /* Alignment Functions. */
8011 get_text_align_power (unsigned target_size
)
8013 if (target_size
<= 4)
8015 assert (target_size
== 8);
8021 get_text_align_max_fill_size (int align_pow
,
8022 bfd_boolean use_nops
,
8023 bfd_boolean use_no_density
)
8026 return (1 << align_pow
);
8028 return 3 * (1 << align_pow
);
8030 return 1 + (1 << align_pow
);
8034 /* Calculate the minimum bytes of fill needed at "address" to align a
8035 target instruction of size "target_size" so that it does not cross a
8036 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE,
8037 the fill can be an arbitrary number of bytes. Otherwise, the space must
8038 be filled by NOP instructions. */
8041 get_text_align_fill_size (addressT address
,
8044 bfd_boolean use_nops
,
8045 bfd_boolean use_no_density
)
8047 addressT alignment
, fill
, fill_limit
, fill_step
;
8048 bfd_boolean skip_one
= FALSE
;
8050 alignment
= (1 << align_pow
);
8051 assert (target_size
> 0 && alignment
>= (addressT
) target_size
);
8055 fill_limit
= alignment
;
8058 else if (!use_no_density
)
8060 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */
8061 fill_limit
= alignment
* 2;
8067 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */
8068 fill_limit
= alignment
* 3;
8072 /* Try all fill sizes until finding one that works. */
8073 for (fill
= 0; fill
< fill_limit
; fill
+= fill_step
)
8075 if (skip_one
&& fill
== 1)
8077 if ((address
+ fill
) >> align_pow
8078 == (address
+ fill
+ target_size
- 1) >> align_pow
)
8087 branch_align_power (segT sec
)
8089 /* If the Xtensa processor has a fetch width of 8 bytes, and the section
8090 is aligned to at least an 8-byte boundary, then a branch target need
8091 only fit within an 8-byte aligned block of memory to avoid a stall.
8092 Otherwise, try to fit branch targets within 4-byte aligned blocks
8093 (which may be insufficient, e.g., if the section has no alignment, but
8094 it's good enough). */
8095 if (xtensa_fetch_width
== 8)
8097 if (get_recorded_alignment (sec
) >= 3)
8101 assert (xtensa_fetch_width
== 4);
8107 /* This will assert if it is not possible. */
8110 get_text_align_nop_count (offsetT fill_size
, bfd_boolean use_no_density
)
8116 assert (fill_size
% 3 == 0);
8117 return (fill_size
/ 3);
8120 assert (fill_size
!= 1); /* Bad argument. */
8122 while (fill_size
> 1)
8125 if (fill_size
== 2 || fill_size
== 4)
8127 fill_size
-= insn_size
;
8130 assert (fill_size
!= 1); /* Bad algorithm. */
8136 get_text_align_nth_nop_size (offsetT fill_size
,
8138 bfd_boolean use_no_density
)
8145 assert (fill_size
!= 1); /* Bad argument. */
8147 while (fill_size
> 1)
8150 if (fill_size
== 2 || fill_size
== 4)
8152 fill_size
-= insn_size
;
8162 /* For the given fragment, find the appropriate address
8163 for it to begin at if we are using NOPs to align it. */
8166 get_noop_aligned_address (fragS
*fragP
, addressT address
)
8168 /* The rule is: get next fragment's FIRST instruction. Find
8169 the smallest number of bytes that need to be added to
8170 ensure that the next fragment's FIRST instruction will fit
8173 E.G., 2 bytes : 0, 1, 2 mod 4
8176 If the FIRST instruction MIGHT be relaxed,
8177 assume that it will become a 3-byte instruction.
8179 Note again here that LOOP instructions are not bundleable,
8180 and this relaxation only applies to LOOP opcodes. */
8183 int first_insn_size
;
8185 addressT pre_opcode_bytes
;
8188 xtensa_opcode opcode
;
8189 bfd_boolean is_loop
;
8191 assert (fragP
->fr_type
== rs_machine_dependent
);
8192 assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
8194 /* Find the loop frag. */
8195 first_insn
= next_non_empty_frag (fragP
);
8196 /* Now find the first insn frag. */
8197 first_insn
= next_non_empty_frag (first_insn
);
8199 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
8201 loop_insn_size
= xg_get_single_size (opcode
);
8203 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
8204 pre_opcode_bytes
+= loop_insn_size
;
8206 /* For loops, the alignment depends on the size of the
8207 instruction following the loop, not the LOOP instruction. */
8209 if (first_insn
== NULL
)
8210 first_insn_size
= xtensa_fetch_width
;
8212 first_insn_size
= get_loop_align_size (frag_format_size (first_insn
));
8214 /* If it was 8, then we'll need a larger alignment for the section. */
8215 align_power
= get_text_align_power (first_insn_size
);
8216 record_alignment (now_seg
, align_power
);
8218 fill_size
= get_text_align_fill_size
8219 (address
+ pre_opcode_bytes
, align_power
, first_insn_size
, TRUE
,
8220 fragP
->tc_frag_data
.is_no_density
);
8222 return address
+ fill_size
;
8226 /* 3 mechanisms for relaxing an alignment:
8228 Align to a power of 2.
8229 Align so the next fragment's instruction does not cross a word boundary.
8230 Align the current instruction so that if the next instruction
8231 were 3 bytes, it would not cross a word boundary.
8235 zeros - This is easy; always insert zeros.
8236 nops - 3-byte and 2-byte instructions
8240 >=5 : 3-byte instruction + fn (n-3)
8241 widening - widen previous instructions. */
8244 get_aligned_diff (fragS
*fragP
, addressT address
, offsetT
*max_diff
)
8246 addressT target_address
, loop_insn_offset
;
8248 xtensa_opcode loop_opcode
;
8249 bfd_boolean is_loop
;
8252 offsetT branch_align
;
8254 assert (fragP
->fr_type
== rs_machine_dependent
);
8255 switch (fragP
->fr_subtype
)
8257 case RELAX_DESIRE_ALIGN
:
8258 target_size
= next_frag_format_size (fragP
);
8259 if (target_size
== XTENSA_UNDEFINED
)
8261 align_power
= branch_align_power (now_seg
);
8262 branch_align
= 1 << align_power
;
8263 /* Don't count on the section alignment being as large as the target. */
8264 if (target_size
> branch_align
)
8265 target_size
= branch_align
;
8266 opt_diff
= get_text_align_fill_size (address
, align_power
,
8267 target_size
, FALSE
, FALSE
);
8269 *max_diff
= (opt_diff
+ branch_align
8270 - (target_size
+ ((address
+ opt_diff
) % branch_align
)));
8271 assert (*max_diff
>= opt_diff
);
8274 case RELAX_ALIGN_NEXT_OPCODE
:
8275 target_size
= get_loop_align_size (next_frag_format_size (fragP
));
8276 loop_insn_offset
= 0;
8277 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
8280 /* If the loop has been expanded then the LOOP instruction
8281 could be at an offset from this fragment. */
8282 if (next_non_empty_frag(fragP
)->tc_frag_data
.slot_subtypes
[0]
8284 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
8286 /* In an ideal world, which is what we are shooting for here,
8287 we wouldn't need to use any NOPs immediately prior to the
8288 LOOP instruction. If this approach fails, relax_frag_loop_align
8289 will call get_noop_aligned_address. */
8291 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
8292 align_power
= get_text_align_power (target_size
),
8293 opt_diff
= get_text_align_fill_size (target_address
, align_power
,
8294 target_size
, FALSE
, FALSE
);
8296 *max_diff
= xtensa_fetch_width
8297 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
8298 - target_size
+ opt_diff
;
8299 assert (*max_diff
>= opt_diff
);
8310 /* md_relax_frag Hook and Helper Functions. */
8312 static long relax_frag_loop_align (fragS
*, long);
8313 static long relax_frag_for_align (fragS
*, long);
8314 static long relax_frag_immed
8315 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
8318 /* Return the number of bytes added to this fragment, given that the
8319 input has been stretched already by "stretch". */
8322 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
8324 xtensa_isa isa
= xtensa_default_isa
;
8325 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
8326 long new_stretch
= 0;
8330 static xtensa_insnbuf vbuf
= NULL
;
8331 int slot
, num_slots
;
8334 as_where (&file_name
, &line
);
8335 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8337 fragP
->tc_frag_data
.unreported_expansion
= 0;
8339 switch (fragP
->fr_subtype
)
8341 case RELAX_ALIGN_NEXT_OPCODE
:
8342 /* Always convert. */
8343 if (fragP
->tc_frag_data
.relax_seen
)
8344 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
8347 case RELAX_LOOP_END
:
8351 case RELAX_LOOP_END_ADD_NOP
:
8352 /* Add a NOP and switch to .fill 0. */
8353 new_stretch
= relax_frag_add_nop (fragP
);
8357 case RELAX_DESIRE_ALIGN
:
8358 /* Do nothing. The narrowing before this frag will either align
8363 case RELAX_LITERAL_FINAL
:
8366 case RELAX_LITERAL_NR
:
8368 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
8369 assert (unreported
== lit_size
);
8370 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
8371 fragP
->fr_var
-= lit_size
;
8372 fragP
->fr_fix
+= lit_size
;
8378 vbuf
= xtensa_insnbuf_alloc (isa
);
8380 xtensa_insnbuf_from_chars
8381 (isa
, vbuf
, (unsigned char *) fragP
->fr_opcode
, 0);
8382 fmt
= xtensa_format_decode (isa
, vbuf
);
8383 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8385 for (slot
= 0; slot
< num_slots
; slot
++)
8387 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
8390 if (fragP
->tc_frag_data
.relax_seen
)
8391 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8395 case RELAX_IMMED_STEP1
:
8396 case RELAX_IMMED_STEP2
:
8397 case RELAX_IMMED_STEP3
:
8398 /* Place the immediate. */
8399 new_stretch
+= relax_frag_immed
8400 (now_seg
, fragP
, stretch
,
8401 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8402 fmt
, slot
, stretched_p
, FALSE
);
8406 /* This is OK; see the note in xg_assemble_vliw_tokens. */
8412 case RELAX_LITERAL_POOL_BEGIN
:
8413 case RELAX_LITERAL_POOL_END
:
8414 case RELAX_MAYBE_UNREACHABLE
:
8415 case RELAX_MAYBE_DESIRE_ALIGN
:
8416 /* No relaxation required. */
8419 case RELAX_FILL_NOP
:
8420 case RELAX_UNREACHABLE
:
8421 if (fragP
->tc_frag_data
.relax_seen
)
8422 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8426 as_bad (_("bad relaxation state"));
8429 /* Tell gas we need another relaxation pass. */
8430 if (! fragP
->tc_frag_data
.relax_seen
)
8432 fragP
->tc_frag_data
.relax_seen
= TRUE
;
8436 new_logical_line (file_name
, line
);
8442 relax_frag_loop_align (fragS
*fragP
, long stretch
)
8444 addressT old_address
, old_next_address
, old_size
;
8445 addressT new_address
, new_next_address
, new_size
;
8448 /* All the frags with relax_frag_for_alignment prior to this one in the
8449 section have been done, hopefully eliminating the need for a NOP here.
8450 But, this will put it in if necessary. */
8452 /* Calculate the old address of this fragment and the next fragment. */
8453 old_address
= fragP
->fr_address
- stretch
;
8454 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
8455 fragP
->tc_frag_data
.text_expansion
[0]);
8456 old_size
= old_next_address
- old_address
;
8458 /* Calculate the new address of this fragment and the next fragment. */
8459 new_address
= fragP
->fr_address
;
8461 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
8462 new_size
= new_next_address
- new_address
;
8464 growth
= new_size
- old_size
;
8466 /* Fix up the text_expansion field and return the new growth. */
8467 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
8472 /* Add a NOP instruction. */
8475 relax_frag_add_nop (fragS
*fragP
)
8477 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
8478 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
8479 assemble_nop (length
, nop_buf
);
8480 fragP
->tc_frag_data
.is_insn
= TRUE
;
8482 if (fragP
->fr_var
< length
)
8484 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP
->fr_var
, length
);
8488 fragP
->fr_fix
+= length
;
8489 fragP
->fr_var
-= length
;
8494 static long future_alignment_required (fragS
*, long);
8497 relax_frag_for_align (fragS
*fragP
, long stretch
)
8499 /* Overview of the relaxation procedure for alignment:
8500 We can widen with NOPs or by widening instructions or by filling
8501 bytes after jump instructions. Find the opportune places and widen
8502 them if necessary. */
8507 assert (fragP
->fr_subtype
== RELAX_FILL_NOP
8508 || fragP
->fr_subtype
== RELAX_UNREACHABLE
8509 || (fragP
->fr_subtype
== RELAX_SLOTS
8510 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
8512 stretch_me
= future_alignment_required (fragP
, stretch
);
8513 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
8519 /* We expanded on a previous pass. Can we shrink now? */
8520 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
8521 if (shrink
<= stretch
&& stretch
> 0)
8523 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8529 /* Below here, diff > 0. */
8530 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8536 /* Return the address of the next frag that should be aligned.
8538 By "address" we mean the address it _would_ be at if there
8539 is no action taken to align it between here and the target frag.
8540 In other words, if no narrows and no fill nops are used between
8541 here and the frag to align, _even_if_ some of the frags we use
8542 to align targets have already expanded on a previous relaxation
8545 Also, count each frag that may be used to help align the target.
8547 Return 0 if there are no frags left in the chain that need to be
8551 find_address_of_next_align_frag (fragS
**fragPP
,
8555 bfd_boolean
*paddable
)
8557 fragS
*fragP
= *fragPP
;
8558 addressT address
= fragP
->fr_address
;
8560 /* Do not reset the counts to 0. */
8564 /* Limit this to a small search. */
8565 if (*widens
>= (int) xtensa_fetch_width
)
8570 address
+= fragP
->fr_fix
;
8572 if (fragP
->fr_type
== rs_fill
)
8573 address
+= fragP
->fr_offset
* fragP
->fr_var
;
8574 else if (fragP
->fr_type
== rs_machine_dependent
)
8576 switch (fragP
->fr_subtype
)
8578 case RELAX_UNREACHABLE
:
8582 case RELAX_FILL_NOP
:
8584 if (!fragP
->tc_frag_data
.is_no_density
)
8589 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8594 address
+= total_frag_text_expansion (fragP
);;
8598 address
+= fragP
->tc_frag_data
.text_expansion
[0];
8601 case RELAX_ALIGN_NEXT_OPCODE
:
8602 case RELAX_DESIRE_ALIGN
:
8606 case RELAX_MAYBE_UNREACHABLE
:
8607 case RELAX_MAYBE_DESIRE_ALIGN
:
8612 /* Just punt if we don't know the type. */
8619 /* Just punt if we don't know the type. */
8623 fragP
= fragP
->fr_next
;
8631 static long bytes_to_stretch (fragS
*, int, int, int, int);
8634 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
8636 fragS
*this_frag
= fragP
;
8640 int narrow_nops
= 0;
8641 bfd_boolean paddable
= FALSE
;
8642 offsetT local_opt_diff
;
8645 int stretch_amount
= 0;
8646 int local_stretch_amount
;
8647 int global_stretch_amount
;
8649 address
= find_address_of_next_align_frag
8650 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
8654 if (this_frag
->tc_frag_data
.is_aligning_branch
)
8655 this_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
8657 frag_wane (this_frag
);
8661 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
8662 opt_diff
= local_opt_diff
;
8663 assert (opt_diff
>= 0);
8664 assert (max_diff
>= opt_diff
);
8669 fragP
= fragP
->fr_next
;
8671 while (fragP
&& opt_diff
< max_diff
&& address
)
8673 /* We only use these to determine if we can exit early
8674 because there will be plenty of ways to align future
8676 int glob_widens
= 0;
8679 bfd_boolean glob_pad
= 0;
8680 address
= find_address_of_next_align_frag
8681 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
8682 /* If there is a padable portion, then skip. */
8683 if (glob_pad
|| glob_widens
>= (1 << branch_align_power (now_seg
)))
8688 offsetT next_m_diff
;
8689 offsetT next_o_diff
;
8691 /* Downrange frags haven't had stretch added to them yet. */
8694 /* The address also includes any text expansion from this
8695 frag in a previous pass, but we don't want that. */
8696 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
8698 /* Assume we are going to move at least opt_diff. In
8699 reality, we might not be able to, but assuming that
8700 we will helps catch cases where moving opt_diff pushes
8701 the next target from aligned to unaligned. */
8702 address
+= opt_diff
;
8704 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
8706 /* Now cleanup for the adjustments to address. */
8707 next_o_diff
+= opt_diff
;
8708 next_m_diff
+= opt_diff
;
8709 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
8710 opt_diff
= next_o_diff
;
8711 if (next_m_diff
< max_diff
)
8712 max_diff
= next_m_diff
;
8713 fragP
= fragP
->fr_next
;
8717 /* If there are enough wideners in between, do it. */
8720 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
8722 assert (opt_diff
<= UNREACHABLE_MAX_WIDTH
);
8727 local_stretch_amount
8728 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8729 num_widens
, local_opt_diff
);
8730 global_stretch_amount
8731 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8732 num_widens
, opt_diff
);
8733 /* If the condition below is true, then the frag couldn't
8734 stretch the correct amount for the global case, so we just
8735 optimize locally. We'll rely on the subsequent frags to get
8736 the correct alignment in the global case. */
8737 if (global_stretch_amount
< local_stretch_amount
)
8738 stretch_amount
= local_stretch_amount
;
8740 stretch_amount
= global_stretch_amount
;
8742 if (this_frag
->fr_subtype
== RELAX_SLOTS
8743 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8744 assert (stretch_amount
<= 1);
8745 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8747 if (this_frag
->tc_frag_data
.is_no_density
)
8748 assert (stretch_amount
== 3 || stretch_amount
== 0);
8750 assert (stretch_amount
<= 3);
8753 return stretch_amount
;
8757 /* The idea: widen everything you can to get a target or loop aligned,
8758 then start using NOPs.
8760 When we must have a NOP, here is a table of how we decide
8761 (so you don't have to fight through the control flow below):
8763 wide_nops = the number of wide NOPs available for aligning
8764 narrow_nops = the number of narrow NOPs available for aligning
8765 (a subset of wide_nops)
8766 widens = the number of narrow instructions that should be widened
8773 b 0 1 1 (case 3a makes this case unnecessary)
8776 c 0 1 2 (case 4a makes this case unnecessary)
8779 c 0 2 1 (case 5b makes this case unnecessary)
8782 c 0 1 4 (case 6b makes this case unnecessary)
8783 d 1 1 1 (case 6a makes this case unnecessary)
8784 e 0 2 2 (case 6a makes this case unnecessary)
8785 f 0 3 0 (case 6a makes this case unnecessary)
8788 c 1 1 2 (case 7b makes this case unnecessary)
8789 d 0 1 5 (case 7a makes this case unnecessary)
8790 e 0 2 3 (case 7b makes this case unnecessary)
8791 f 0 3 1 (case 7b makes this case unnecessary)
8792 g 1 2 1 (case 7b makes this case unnecessary)
8796 bytes_to_stretch (fragS
*this_frag
,
8802 int bytes_short
= desired_diff
- num_widens
;
8804 assert (desired_diff
>= 0 && desired_diff
< 8);
8805 if (desired_diff
== 0)
8808 assert (wide_nops
> 0 || num_widens
> 0);
8810 /* Always prefer widening to NOP-filling. */
8811 if (bytes_short
< 0)
8813 /* There are enough RELAX_NARROW frags after this one
8814 to align the target without widening this frag in any way. */
8818 if (bytes_short
== 0)
8820 /* Widen every narrow between here and the align target
8821 and the align target will be properly aligned. */
8822 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8828 /* From here we will need at least one NOP to get an alignment.
8829 However, we may not be able to align at all, in which case,
8831 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8833 switch (desired_diff
)
8838 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 1)
8839 return 2; /* case 2 */
8845 return 3; /* case 3a */
8847 if (num_widens
>= 1 && wide_nops
== 1)
8848 return 3; /* case 4a */
8849 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 2)
8850 return 2; /* case 4b */
8853 if (num_widens
>= 2 && wide_nops
== 1)
8854 return 3; /* case 5a */
8855 /* We will need two nops. Are there enough nops
8856 between here and the align target? */
8857 if (wide_nops
< 2 || narrow_nops
== 0)
8859 /* Are there other nops closer that can serve instead? */
8860 if (wide_nops
> 2 && narrow_nops
> 1)
8862 /* Take the density one first, because there might not be
8863 another density one available. */
8864 if (!this_frag
->tc_frag_data
.is_no_density
)
8865 return 2; /* case 5b narrow */
8867 return 3; /* case 5b wide */
8871 return 3; /* case 6a */
8872 else if (num_widens
>= 3 && wide_nops
== 1)
8873 return 3; /* case 6b */
8876 if (wide_nops
== 1 && num_widens
>= 4)
8877 return 3; /* case 7a */
8878 else if (wide_nops
== 2 && num_widens
>= 1)
8879 return 3; /* case 7b */
8887 /* We will need a NOP no matter what, but should we widen
8888 this instruction to help?
8890 This is a RELAX_NARROW frag. */
8891 switch (desired_diff
)
8900 if (wide_nops
>= 1 && num_widens
== 1)
8901 return 1; /* case 4a */
8904 if (wide_nops
>= 1 && num_widens
== 2)
8905 return 1; /* case 5a */
8909 return 0; /* case 6a */
8910 else if (wide_nops
>= 1 && num_widens
== 3)
8911 return 1; /* case 6b */
8914 if (wide_nops
>= 1 && num_widens
== 4)
8915 return 1; /* case 7a */
8916 else if (wide_nops
>= 2 && num_widens
== 1)
8917 return 1; /* case 7b */
8930 relax_frag_immed (segT segP
,
8937 bfd_boolean estimate_only
)
8941 bfd_boolean negatable_branch
= FALSE
;
8942 bfd_boolean branch_jmp_to_next
= FALSE
;
8943 bfd_boolean wide_insn
= FALSE
;
8944 xtensa_isa isa
= xtensa_default_isa
;
8946 offsetT frag_offset
;
8949 int num_text_bytes
, num_literal_bytes
;
8950 int literal_diff
, total_text_diff
, this_text_diff
, first
;
8952 assert (fragP
->fr_opcode
!= NULL
);
8954 xg_clear_vinsn (&cur_vinsn
);
8955 vinsn_from_chars (&cur_vinsn
, fragP
->fr_opcode
);
8956 if (cur_vinsn
.num_slots
> 1)
8959 tinsn
= cur_vinsn
.slots
[slot
];
8960 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
8962 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
) == 1)
8965 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
8966 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
8968 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
8970 old_size
= xtensa_format_length (isa
, fmt
);
8972 /* Special case: replace a branch to the next instruction with a NOP.
8973 This is required to work around a hardware bug in T1040.0 and also
8974 serves as an optimization. */
8976 if (branch_jmp_to_next
8977 && ((old_size
== 2) || (old_size
== 3))
8978 && !next_frag_is_loop_target (fragP
))
8981 /* Here is the fun stuff: Get the immediate field from this
8982 instruction. If it fits, we are done. If not, find the next
8983 instruction sequence that fits. */
8985 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
8986 istack_init (&istack
);
8987 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
8988 min_steps
, stretch
);
8989 if (num_steps
< min_steps
)
8991 as_fatal (_("internal error: relaxation failed"));
8995 if (num_steps
> RELAX_IMMED_MAXSTEPS
)
8997 as_fatal (_("internal error: relaxation requires too many steps"));
9001 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
9003 /* Figure out the number of bytes needed. */
9005 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
9007 num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
9009 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
9011 num_text_bytes
= get_num_stack_text_bytes (&istack
);
9014 num_text_bytes
+= old_size
;
9015 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
9016 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
9018 total_text_diff
= num_text_bytes
- old_size
;
9019 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
9021 /* It MUST get larger. If not, we could get an infinite loop. */
9022 assert (num_text_bytes
>= 0);
9023 assert (literal_diff
>= 0);
9024 assert (total_text_diff
>= 0);
9026 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
9027 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
9028 assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
9029 assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
9031 /* Find the associated expandable literal for this. */
9032 if (literal_diff
!= 0)
9034 lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
9037 assert (literal_diff
== 4);
9038 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
9040 /* We expect that the literal section state has NOT been
9042 assert (lit_fragP
->fr_type
== rs_machine_dependent
9043 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
9044 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
9046 /* We need to mark this section for another iteration
9052 if (negatable_branch
&& istack
.ninsn
> 1)
9053 update_next_frag_state (fragP
);
9055 return this_text_diff
;
9059 /* md_convert_frag Hook and Helper Functions. */
9061 static void convert_frag_align_next_opcode (fragS
*);
9062 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
9063 static void convert_frag_fill_nop (fragS
*);
9064 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
9067 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
9069 static xtensa_insnbuf vbuf
= NULL
;
9070 xtensa_isa isa
= xtensa_default_isa
;
9077 as_where (&file_name
, &line
);
9078 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
9080 switch (fragp
->fr_subtype
)
9082 case RELAX_ALIGN_NEXT_OPCODE
:
9083 /* Always convert. */
9084 convert_frag_align_next_opcode (fragp
);
9087 case RELAX_DESIRE_ALIGN
:
9088 /* Do nothing. If not aligned already, too bad. */
9092 case RELAX_LITERAL_FINAL
:
9097 vbuf
= xtensa_insnbuf_alloc (isa
);
9099 xtensa_insnbuf_from_chars
9100 (isa
, vbuf
, (unsigned char *) fragp
->fr_opcode
, 0);
9101 fmt
= xtensa_format_decode (isa
, vbuf
);
9102 num_slots
= xtensa_format_num_slots (isa
, fmt
);
9104 for (slot
= 0; slot
< num_slots
; slot
++)
9106 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
9109 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
9113 case RELAX_IMMED_STEP1
:
9114 case RELAX_IMMED_STEP2
:
9115 case RELAX_IMMED_STEP3
:
9116 /* Place the immediate. */
9119 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
9124 /* This is OK because some slots could have
9125 relaxations and others have none. */
9131 case RELAX_UNREACHABLE
:
9132 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
9133 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
9134 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
9138 case RELAX_MAYBE_UNREACHABLE
:
9139 case RELAX_MAYBE_DESIRE_ALIGN
:
9143 case RELAX_FILL_NOP
:
9144 convert_frag_fill_nop (fragp
);
9147 case RELAX_LITERAL_NR
:
9148 if (use_literal_section
)
9150 /* This should have been handled during relaxation. When
9151 relaxing a code segment, literals sometimes need to be
9152 added to the corresponding literal segment. If that
9153 literal segment has already been relaxed, then we end up
9154 in this situation. Marking the literal segments as data
9155 would make this happen less often (since GAS always relaxes
9156 code before data), but we could still get into trouble if
9157 there are instructions in a segment that is not marked as
9158 containing code. Until we can implement a better solution,
9159 cheat and adjust the addresses of all the following frags.
9160 This could break subsequent alignments, but the linker's
9161 literal coalescing will do that anyway. */
9164 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
9165 assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
9166 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
9169 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
9173 as_bad (_("invalid relaxation fragment result"));
9178 new_logical_line (file_name
, line
);
9183 convert_frag_align_next_opcode (fragS
*fragp
)
9185 char *nop_buf
; /* Location for Writing. */
9186 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
9187 addressT aligned_address
;
9191 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
9193 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
9194 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
9195 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
9197 for (nop
= 0; nop
< nop_count
; nop
++)
9200 nop_size
= get_text_align_nth_nop_size (fill_size
, nop
, use_no_density
);
9202 assemble_nop (nop_size
, nop_buf
);
9203 nop_buf
+= nop_size
;
9206 fragp
->fr_fix
+= fill_size
;
9207 fragp
->fr_var
-= fill_size
;
9212 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
9214 TInsn tinsn
, single_target
;
9215 int size
, old_size
, diff
;
9216 offsetT frag_offset
;
9219 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
9221 if (fragP
->tc_frag_data
.is_aligning_branch
== 1)
9223 assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
9224 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
9225 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
9230 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
9232 /* No conversion. */
9237 assert (fragP
->fr_opcode
!= NULL
);
9239 /* Frags in this relaxation state should only contain
9240 single instruction bundles. */
9241 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
9243 /* Just convert it to a wide form.... */
9245 old_size
= xg_get_single_size (tinsn
.opcode
);
9247 tinsn_init (&single_target
);
9248 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9250 if (! xg_is_single_relaxable_insn (&tinsn
, &single_target
, FALSE
))
9252 as_bad (_("unable to widen instruction"));
9256 size
= xg_get_single_size (single_target
.opcode
);
9257 xg_emit_insn_to_buf (&single_target
, fragP
->fr_opcode
, fragP
,
9260 diff
= size
- old_size
;
9262 assert (diff
<= fragP
->fr_var
);
9263 fragP
->fr_var
-= diff
;
9264 fragP
->fr_fix
+= diff
;
9272 convert_frag_fill_nop (fragS
*fragP
)
9274 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
9275 int size
= fragP
->tc_frag_data
.text_expansion
[0];
9276 assert ((unsigned) size
== (fragP
->fr_next
->fr_address
9277 - fragP
->fr_address
- fragP
->fr_fix
));
9280 /* No conversion. */
9284 assemble_nop (size
, loc
);
9285 fragP
->tc_frag_data
.is_insn
= TRUE
;
9286 fragP
->fr_var
-= size
;
9287 fragP
->fr_fix
+= size
;
9292 static fixS
*fix_new_exp_in_seg
9293 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
9294 bfd_reloc_code_real_type
);
9295 static void convert_frag_immed_finish_loop (segT
, fragS
*, TInsn
*);
9298 convert_frag_immed (segT segP
,
9304 char *immed_instr
= fragP
->fr_opcode
;
9306 bfd_boolean expanded
= FALSE
;
9307 bfd_boolean branch_jmp_to_next
= FALSE
;
9308 char *fr_opcode
= fragP
->fr_opcode
;
9309 xtensa_isa isa
= xtensa_default_isa
;
9310 bfd_boolean wide_insn
= FALSE
;
9312 bfd_boolean is_loop
;
9314 assert (fr_opcode
!= NULL
);
9316 xg_clear_vinsn (&cur_vinsn
);
9318 vinsn_from_chars (&cur_vinsn
, fr_opcode
);
9319 if (cur_vinsn
.num_slots
> 1)
9322 orig_tinsn
= cur_vinsn
.slots
[slot
];
9323 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
9325 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
9327 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9328 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
9330 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
9332 /* Conversion just inserts a NOP and marks the fix as completed. */
9333 bytes
= xtensa_format_length (isa
, fmt
);
9336 cur_vinsn
.slots
[slot
].opcode
=
9337 xtensa_format_slot_nop_opcode (isa
, cur_vinsn
.format
, slot
);
9338 cur_vinsn
.slots
[slot
].ntok
= 0;
9342 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
9343 assert (bytes
== 2 || bytes
== 3);
9344 build_nop (&cur_vinsn
.slots
[0], bytes
);
9345 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
9347 vinsn_to_insnbuf (&cur_vinsn
, fr_opcode
, frag_now
, TRUE
);
9348 xtensa_insnbuf_to_chars
9349 (isa
, cur_vinsn
.insnbuf
, (unsigned char *) fr_opcode
, 0);
9354 /* Here is the fun stuff: Get the immediate field from this
9355 instruction. If it fits, we're done. If not, find the next
9356 instruction sequence that fits. */
9360 symbolS
*lit_sym
= NULL
;
9362 int target_offset
= 0;
9365 symbolS
*gen_label
= NULL
;
9366 offsetT frag_offset
;
9367 bfd_boolean first
= TRUE
;
9368 bfd_boolean last_is_jump
;
9370 /* It does not fit. Find something that does and
9371 convert immediately. */
9372 frag_offset
= fr_opcode
- fragP
->fr_literal
;
9373 istack_init (&istack
);
9374 xg_assembly_relax (&istack
, &orig_tinsn
,
9375 segP
, fragP
, frag_offset
, min_steps
, 0);
9377 old_size
= xtensa_format_length (isa
, fmt
);
9379 /* Assemble this right inline. */
9381 /* First, create the mapping from a label name to the REAL label. */
9383 for (i
= 0; i
< istack
.ninsn
; i
++)
9385 TInsn
*tinsn
= &istack
.insn
[i
];
9388 switch (tinsn
->insn_type
)
9391 if (lit_sym
!= NULL
)
9392 as_bad (_("multiple literals in expansion"));
9393 /* First find the appropriate space in the literal pool. */
9394 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9395 if (lit_frag
== NULL
)
9396 as_bad (_("no registered fragment for literal"));
9397 if (tinsn
->ntok
!= 1)
9398 as_bad (_("number of literal tokens != 1"));
9400 /* Set the literal symbol and add a fixup. */
9401 lit_sym
= lit_frag
->fr_symbol
;
9405 if (align_targets
&& !is_loop
)
9407 fragS
*unreach
= fragP
->fr_next
;
9408 while (!(unreach
->fr_type
== rs_machine_dependent
9409 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9410 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
9412 unreach
= unreach
->fr_next
;
9415 assert (unreach
->fr_type
== rs_machine_dependent
9416 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9417 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
9419 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
9421 assert (gen_label
== NULL
);
9422 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
9423 fr_opcode
- fragP
->fr_literal
9424 + target_offset
, fragP
);
9428 if (first
&& wide_insn
)
9430 target_offset
+= xtensa_format_length (isa
, fmt
);
9432 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9433 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9436 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9443 last_is_jump
= FALSE
;
9444 for (i
= 0; i
< istack
.ninsn
; i
++)
9446 TInsn
*tinsn
= &istack
.insn
[i
];
9450 bfd_reloc_code_real_type reloc_type
;
9452 switch (tinsn
->insn_type
)
9455 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9456 /* Already checked. */
9457 assert (lit_frag
!= NULL
);
9458 assert (lit_sym
!= NULL
);
9459 assert (tinsn
->ntok
== 1);
9461 target_seg
= S_GET_SEGMENT (lit_sym
);
9462 assert (target_seg
);
9463 reloc_type
= map_operator_to_reloc (tinsn
->tok
[0].X_op
);
9464 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
9465 &tinsn
->tok
[0], FALSE
, reloc_type
);
9472 xg_resolve_labels (tinsn
, gen_label
);
9473 xg_resolve_literals (tinsn
, lit_sym
);
9474 if (wide_insn
&& first
)
9477 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9479 cur_vinsn
.slots
[slot
] = *tinsn
;
9483 cur_vinsn
.slots
[slot
].opcode
=
9484 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
9485 cur_vinsn
.slots
[slot
].ntok
= 0;
9487 vinsn_to_insnbuf (&cur_vinsn
, immed_instr
, fragP
, TRUE
);
9488 xtensa_insnbuf_to_chars (isa
, cur_vinsn
.insnbuf
,
9489 (unsigned char *) immed_instr
, 0);
9490 fragP
->tc_frag_data
.is_insn
= TRUE
;
9491 size
= xtensa_format_length (isa
, fmt
);
9492 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9495 (tinsn
, immed_instr
+ size
, fragP
,
9496 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
9497 size
+= xg_get_single_size (tinsn
->opcode
);
9502 size
= xg_get_single_size (tinsn
->opcode
);
9503 xg_emit_insn_to_buf (tinsn
, immed_instr
, fragP
,
9504 immed_instr
- fragP
->fr_literal
, TRUE
);
9506 immed_instr
+= size
;
9512 diff
= total_size
- old_size
;
9516 assert (diff
<= fragP
->fr_var
);
9517 fragP
->fr_var
-= diff
;
9518 fragP
->fr_fix
+= diff
;
9521 /* Check for undefined immediates in LOOP instructions. */
9525 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
9526 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9528 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9531 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
9532 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9534 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9539 if (expanded
&& xtensa_opcode_is_loop (isa
, orig_tinsn
.opcode
) == 1)
9540 convert_frag_immed_finish_loop (segP
, fragP
, &orig_tinsn
);
9542 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
9544 /* Add an expansion note on the expanded instruction. */
9545 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
9546 &orig_tinsn
.tok
[0], TRUE
,
9547 BFD_RELOC_XTENSA_ASM_EXPAND
);
9552 /* Add a new fix expression into the desired segment. We have to
9553 switch to that segment to do this. */
9556 fix_new_exp_in_seg (segT new_seg
,
9563 bfd_reloc_code_real_type r_type
)
9567 subsegT subseg
= now_subseg
;
9569 assert (new_seg
!= 0);
9570 subseg_set (new_seg
, new_subseg
);
9572 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
9573 subseg_set (seg
, subseg
);
9578 /* Relax a loop instruction so that it can span loop >256 bytes.
9584 addi as, as, lo8 (label-.L1)
9585 addmi as, as, mid8 (label-.L1)
9596 convert_frag_immed_finish_loop (segT segP
, fragS
*fragP
, TInsn
*tinsn
)
9601 unsigned long target
;
9602 static xtensa_insnbuf insnbuf
= NULL
;
9603 unsigned int loop_length
, loop_length_hi
, loop_length_lo
;
9604 xtensa_isa isa
= xtensa_default_isa
;
9605 addressT loop_offset
;
9606 addressT addi_offset
= 9;
9607 addressT addmi_offset
= 12;
9612 insnbuf
= xtensa_insnbuf_alloc (isa
);
9614 /* Get the loop offset. */
9615 loop_offset
= get_expanded_loop_offset (tinsn
->opcode
);
9617 /* Validate that there really is a LOOP at the loop_offset. Because
9618 loops are not bundleable, we can assume that the instruction will be
9620 tinsn_from_chars (&loop_insn
, fragP
->fr_opcode
+ loop_offset
, 0);
9621 tinsn_immed_from_frag (&loop_insn
, fragP
, 0);
9623 assert (xtensa_opcode_is_loop (isa
, loop_insn
.opcode
) == 1);
9624 addi_offset
+= loop_offset
;
9625 addmi_offset
+= loop_offset
;
9627 assert (tinsn
->ntok
== 2);
9628 if (tinsn
->tok
[1].X_op
== O_constant
)
9629 target
= tinsn
->tok
[1].X_add_number
;
9630 else if (tinsn
->tok
[1].X_op
== O_symbol
)
9632 /* Find the fragment. */
9633 symbolS
*sym
= tinsn
->tok
[1].X_add_symbol
;
9634 assert (S_GET_SEGMENT (sym
) == segP
9635 || S_GET_SEGMENT (sym
) == absolute_section
);
9636 target
= (S_GET_VALUE (sym
) + tinsn
->tok
[1].X_add_number
);
9640 as_bad (_("invalid expression evaluation type %d"), tinsn
->tok
[1].X_op
);
9644 loop_length
= target
- (fragP
->fr_address
+ fragP
->fr_fix
);
9645 loop_length_hi
= loop_length
& ~0x0ff;
9646 loop_length_lo
= loop_length
& 0x0ff;
9647 if (loop_length_lo
>= 128)
9649 loop_length_lo
-= 256;
9650 loop_length_hi
+= 256;
9653 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
9654 32512. If the loop is larger than that, then we just fail. */
9655 if (loop_length_hi
> 32512)
9656 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9657 _("loop too long for LOOP instruction"));
9659 tinsn_from_chars (&addi_insn
, fragP
->fr_opcode
+ addi_offset
, 0);
9660 assert (addi_insn
.opcode
== xtensa_addi_opcode
);
9662 tinsn_from_chars (&addmi_insn
, fragP
->fr_opcode
+ addmi_offset
, 0);
9663 assert (addmi_insn
.opcode
== xtensa_addmi_opcode
);
9665 set_expr_const (&addi_insn
.tok
[2], loop_length_lo
);
9666 tinsn_to_insnbuf (&addi_insn
, insnbuf
);
9668 fragP
->tc_frag_data
.is_insn
= TRUE
;
9669 xtensa_insnbuf_to_chars
9670 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addi_offset
, 0);
9672 set_expr_const (&addmi_insn
.tok
[2], loop_length_hi
);
9673 tinsn_to_insnbuf (&addmi_insn
, insnbuf
);
9674 xtensa_insnbuf_to_chars
9675 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addmi_offset
, 0);
9677 /* Walk through all of the frags from here to the loop end
9678 and mark them as no_transform to keep them from being modified
9679 by the linker. If we ever have a relocation for the
9680 addi/addmi of the difference of two symbols we can remove this. */
9683 for (next_fragP
= fragP
; next_fragP
!= NULL
;
9684 next_fragP
= next_fragP
->fr_next
)
9686 next_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
9687 if (next_fragP
->tc_frag_data
.is_loop_target
)
9689 if (target_count
== 2)
9695 /* A map that keeps information on a per-subsegment basis. This is
9696 maintained during initial assembly, but is invalid once the
9697 subsegments are smashed together. I.E., it cannot be used during
9700 typedef struct subseg_map_struct
9708 float total_freq
; /* fall-through + branch target frequency */
9709 float target_freq
; /* branch target frequency alone */
9711 struct subseg_map_struct
*next
;
9715 static subseg_map
*sseg_map
= NULL
;
9718 get_subseg_info (segT seg
, subsegT subseg
)
9720 subseg_map
*subseg_e
;
9722 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
9724 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
9732 add_subseg_info (segT seg
, subsegT subseg
)
9734 subseg_map
*subseg_e
= (subseg_map
*) xmalloc (sizeof (subseg_map
));
9735 memset (subseg_e
, 0, sizeof (subseg_map
));
9736 subseg_e
->seg
= seg
;
9737 subseg_e
->subseg
= subseg
;
9738 subseg_e
->flags
= 0;
9739 /* Start off considering every branch target very important. */
9740 subseg_e
->target_freq
= 1.0;
9741 subseg_e
->total_freq
= 1.0;
9742 subseg_e
->next
= sseg_map
;
9743 sseg_map
= subseg_e
;
9749 get_last_insn_flags (segT seg
, subsegT subseg
)
9751 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9753 return subseg_e
->flags
;
9759 set_last_insn_flags (segT seg
,
9764 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9766 subseg_e
= add_subseg_info (seg
, subseg
);
9768 subseg_e
->flags
|= fl
;
9770 subseg_e
->flags
&= ~fl
;
9775 get_subseg_total_freq (segT seg
, subsegT subseg
)
9777 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9779 return subseg_e
->total_freq
;
9785 get_subseg_target_freq (segT seg
, subsegT subseg
)
9787 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9789 return subseg_e
->target_freq
;
9795 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
9797 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9799 subseg_e
= add_subseg_info (seg
, subseg
);
9800 subseg_e
->total_freq
= total_f
;
9801 subseg_e
->target_freq
= target_f
;
9805 /* Segment Lists and emit_state Stuff. */
9808 xtensa_move_seg_list_to_beginning (seg_list
*head
)
9813 segT literal_section
= head
->seg
;
9815 /* Move the literal section to the front of the section list. */
9816 assert (literal_section
);
9817 if (literal_section
!= stdoutput
->sections
)
9819 bfd_section_list_remove (stdoutput
, literal_section
);
9820 bfd_section_list_prepend (stdoutput
, literal_section
);
9827 static void mark_literal_frags (seg_list
*);
9830 xtensa_move_literals (void)
9833 frchainS
*frchain_from
, *frchain_to
;
9834 fragS
*search_frag
, *next_frag
, *last_frag
, *literal_pool
, *insert_after
;
9835 fragS
**frag_splice
;
9838 fixS
*fix
, *next_fix
, **fix_splice
;
9841 mark_literal_frags (literal_head
->next
);
9843 if (use_literal_section
)
9846 for (segment
= literal_head
->next
; segment
; segment
= segment
->next
)
9848 /* Keep the literals for .init and .fini in separate sections. */
9849 if (!strcmp (segment_name (segment
->seg
), INIT_SECTION_NAME
)
9850 || !strcmp (segment_name (segment
->seg
), FINI_SECTION_NAME
))
9853 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9854 search_frag
= frchain_from
->frch_root
;
9855 literal_pool
= NULL
;
9857 frag_splice
= &(frchain_from
->frch_root
);
9859 while (!search_frag
->tc_frag_data
.literal_frag
)
9861 assert (search_frag
->fr_fix
== 0
9862 || search_frag
->fr_type
== rs_align
);
9863 search_frag
= search_frag
->fr_next
;
9866 assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
9867 == RELAX_LITERAL_POOL_BEGIN
);
9868 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
9870 /* Make sure that all the frags in this series are closed, and
9871 that there is at least one left over of zero-size. This
9872 prevents us from making a segment with an frchain without any
9874 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9875 xtensa_set_frag_assembly_state (frag_now
);
9876 last_frag
= frag_now
;
9877 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9878 xtensa_set_frag_assembly_state (frag_now
);
9880 while (search_frag
!= frag_now
)
9882 next_frag
= search_frag
->fr_next
;
9884 /* First, move the frag out of the literal section and
9885 to the appropriate place. */
9886 if (search_frag
->tc_frag_data
.literal_frag
)
9888 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
9889 assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
9890 frchain_to
= literal_pool
->tc_frag_data
.lit_frchain
;
9891 assert (frchain_to
);
9893 insert_after
= literal_pool
->tc_frag_data
.literal_frag
;
9894 dest_seg
= insert_after
->fr_next
->tc_frag_data
.lit_seg
;
9896 *frag_splice
= next_frag
;
9897 search_frag
->fr_next
= insert_after
->fr_next
;
9898 insert_after
->fr_next
= search_frag
;
9899 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
9900 literal_pool
->tc_frag_data
.literal_frag
= search_frag
;
9902 /* Now move any fixups associated with this frag to the
9904 fix
= frchain_from
->fix_root
;
9905 fix_splice
= &(frchain_from
->fix_root
);
9908 next_fix
= fix
->fx_next
;
9909 if (fix
->fx_frag
== search_frag
)
9911 *fix_splice
= next_fix
;
9912 fix
->fx_next
= frchain_to
->fix_root
;
9913 frchain_to
->fix_root
= fix
;
9914 if (frchain_to
->fix_tail
== NULL
)
9915 frchain_to
->fix_tail
= fix
;
9918 fix_splice
= &(fix
->fx_next
);
9921 search_frag
= next_frag
;
9924 if (frchain_from
->fix_root
!= NULL
)
9926 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9927 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
9929 assert (frchain_from
->fix_root
== NULL
);
9931 frchain_from
->fix_tail
= NULL
;
9932 xtensa_restore_emit_state (&state
);
9935 /* Now fix up the SEGMENT value for all the literal symbols. */
9936 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
9938 symbolS
*lit_sym
= lit
->sym
;
9939 segT dest_seg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
9941 S_SET_SEGMENT (lit_sym
, dest_seg
);
9946 /* Walk over all the frags for segments in a list and mark them as
9947 containing literals. As clunky as this is, we can't rely on frag_var
9948 and frag_variant to get called in all situations. */
9951 mark_literal_frags (seg_list
*segment
)
9953 frchainS
*frchain_from
;
9958 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9959 search_frag
= frchain_from
->frch_root
;
9962 search_frag
->tc_frag_data
.is_literal
= TRUE
;
9963 search_frag
= search_frag
->fr_next
;
9965 segment
= segment
->next
;
9971 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
9973 /* Move all of the sections in the section list to come
9974 after "after" in the gnu segment list. */
9979 segT literal_section
= head
->seg
;
9981 /* Move the literal section after "after". */
9982 assert (literal_section
);
9983 if (literal_section
!= after
)
9985 bfd_section_list_remove (stdoutput
, literal_section
);
9986 bfd_section_list_insert_after (stdoutput
, after
, literal_section
);
9994 /* Push all the literal segments to the end of the gnu list. */
9997 xtensa_reorder_segments (void)
10004 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
10010 /* Now that we have the last section, push all the literal
10011 sections to the end. */
10012 xtensa_reorder_seg_list (literal_head
, last_sec
);
10014 /* Now perform the final error check. */
10015 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
10017 assert (new_count
== old_count
);
10021 /* Change the emit state (seg, subseg, and frag related stuff) to the
10022 correct location. Return a emit_state which can be passed to
10023 xtensa_restore_emit_state to return to current fragment. */
10026 xtensa_switch_to_literal_fragment (emit_state
*result
)
10028 if (directive_state
[directive_absolute_literals
])
10030 segT lit4_seg
= cache_literal_section (TRUE
);
10031 xtensa_switch_section_emit_state (result
, lit4_seg
, 0);
10034 xtensa_switch_to_non_abs_literal_fragment (result
);
10036 /* Do a 4-byte align here. */
10037 frag_align (2, 0, 0);
10038 record_alignment (now_seg
, 2);
10043 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
10045 static bfd_boolean recursive
= FALSE
;
10046 fragS
*pool_location
= get_literal_pool_location (now_seg
);
10048 bfd_boolean is_init
=
10049 (now_seg
&& !strcmp (segment_name (now_seg
), INIT_SECTION_NAME
));
10050 bfd_boolean is_fini
=
10051 (now_seg
&& !strcmp (segment_name (now_seg
), FINI_SECTION_NAME
));
10053 if (pool_location
== NULL
10054 && !use_literal_section
10056 && !is_init
&& ! is_fini
)
10058 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
10060 /* When we mark a literal pool location, we want to put a frag in
10061 the literal pool that points to it. But to do that, we want to
10062 switch_to_literal_fragment. But literal sections don't have
10063 literal pools, so their location is always null, so we would
10064 recurse forever. This is kind of hacky, but it works. */
10067 xtensa_mark_literal_pool_location ();
10071 lit_seg
= cache_literal_section (FALSE
);
10072 xtensa_switch_section_emit_state (result
, lit_seg
, 0);
10074 if (!use_literal_section
10075 && !is_init
&& !is_fini
10076 && get_literal_pool_location (now_seg
) != pool_location
)
10078 /* Close whatever frag is there. */
10079 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10080 xtensa_set_frag_assembly_state (frag_now
);
10081 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
10082 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10083 xtensa_set_frag_assembly_state (frag_now
);
10088 /* Call this function before emitting data into the literal section.
10089 This is a helper function for xtensa_switch_to_literal_fragment.
10090 This is similar to a .section new_now_seg subseg. */
10093 xtensa_switch_section_emit_state (emit_state
*state
,
10095 subsegT new_now_subseg
)
10097 state
->name
= now_seg
->name
;
10098 state
->now_seg
= now_seg
;
10099 state
->now_subseg
= now_subseg
;
10100 state
->generating_literals
= generating_literals
;
10101 generating_literals
++;
10102 subseg_set (new_now_seg
, new_now_subseg
);
10106 /* Use to restore the emitting into the normal place. */
10109 xtensa_restore_emit_state (emit_state
*state
)
10111 generating_literals
= state
->generating_literals
;
10112 subseg_set (state
->now_seg
, state
->now_subseg
);
10116 /* Predicate function used to look up a section in a particular group. */
10119 match_section_group (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
, void *inf
)
10121 const char *gname
= inf
;
10122 const char *group_name
= elf_group_name (sec
);
10124 return (group_name
== gname
10125 || (group_name
!= NULL
10127 && strcmp (group_name
, gname
) == 0));
10131 /* Get the literal section to be used for the current text section.
10132 The result may be cached in the default_lit_sections structure. */
10135 cache_literal_section (bfd_boolean use_abs_literals
)
10137 const char *text_name
, *group_name
= 0;
10138 char *base_name
, *name
, *suffix
;
10140 segT seg
, current_section
;
10141 int current_subsec
;
10142 bfd_boolean linkonce
= FALSE
;
10144 /* Save the current section/subsection. */
10145 current_section
= now_seg
;
10146 current_subsec
= now_subseg
;
10148 /* Clear the cached values if they are no longer valid. */
10149 if (now_seg
!= default_lit_sections
.current_text_seg
)
10151 default_lit_sections
.current_text_seg
= now_seg
;
10152 default_lit_sections
.lit_seg
= NULL
;
10153 default_lit_sections
.lit4_seg
= NULL
;
10156 /* Check if the literal section is already cached. */
10157 if (use_abs_literals
)
10158 pcached
= &default_lit_sections
.lit4_seg
;
10160 pcached
= &default_lit_sections
.lit_seg
;
10165 text_name
= default_lit_sections
.lit_prefix
;
10166 if (! text_name
|| ! *text_name
)
10168 text_name
= segment_name (current_section
);
10169 group_name
= elf_group_name (current_section
);
10170 linkonce
= (current_section
->flags
& SEC_LINK_ONCE
) != 0;
10173 base_name
= use_abs_literals
? ".lit4" : ".literal";
10176 name
= xmalloc (strlen (base_name
) + strlen (group_name
) + 2);
10177 sprintf (name
, "%s.%s", base_name
, group_name
);
10179 else if (strncmp (text_name
, ".gnu.linkonce.", linkonce_len
) == 0)
10181 suffix
= strchr (text_name
+ linkonce_len
, '.');
10183 name
= xmalloc (linkonce_len
+ strlen (base_name
) + 1
10184 + (suffix
? strlen (suffix
) : 0));
10185 strcpy (name
, ".gnu.linkonce");
10186 strcat (name
, base_name
);
10188 strcat (name
, suffix
);
10193 /* If the section name ends with ".text", then replace that suffix
10194 instead of appending an additional suffix. */
10195 size_t len
= strlen (text_name
);
10196 if (len
>= 5 && strcmp (text_name
+ len
- 5, ".text") == 0)
10199 name
= xmalloc (len
+ strlen (base_name
) + 1);
10200 strcpy (name
, text_name
);
10201 strcpy (name
+ len
, base_name
);
10204 /* Canonicalize section names to allow renaming literal sections.
10205 The group name, if any, came from the current text section and
10206 has already been canonicalized. */
10207 name
= tc_canonicalize_symbol_name (name
);
10209 seg
= bfd_get_section_by_name_if (stdoutput
, name
, match_section_group
,
10210 (void *) group_name
);
10215 seg
= subseg_force_new (name
, 0);
10217 if (! use_abs_literals
)
10219 /* Add the newly created literal segment to the list. */
10220 seg_list
*n
= (seg_list
*) xmalloc (sizeof (seg_list
));
10222 n
->next
= literal_head
->next
;
10223 literal_head
->next
= n
;
10226 flags
= (SEC_HAS_CONTENTS
| SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
10227 | (linkonce
? (SEC_LINK_ONCE
| SEC_LINK_DUPLICATES_DISCARD
) : 0)
10228 | (use_abs_literals
? SEC_DATA
: SEC_CODE
));
10230 elf_group_name (seg
) = group_name
;
10232 bfd_set_section_flags (stdoutput
, seg
, flags
);
10233 bfd_set_section_alignment (stdoutput
, seg
, 2);
10237 subseg_set (current_section
, current_subsec
);
10242 /* Property Tables Stuff. */
10244 #define XTENSA_INSN_SEC_NAME ".xt.insn"
10245 #define XTENSA_LIT_SEC_NAME ".xt.lit"
10246 #define XTENSA_PROP_SEC_NAME ".xt.prop"
10248 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
10249 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
10251 static bfd_boolean
get_frag_is_literal (const fragS
*);
10252 static void xtensa_create_property_segments
10253 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
10254 static void xtensa_create_xproperty_segments
10255 (frag_flags_fn
, const char *, xt_section_type
);
10256 static segment_info_type
*retrieve_segment_info (segT
);
10257 static bfd_boolean
section_has_property (segT
, frag_predicate
);
10258 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
10259 static void add_xt_block_frags
10260 (segT
, segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
10261 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
10262 static void xtensa_frag_flags_init (frag_flags
*);
10263 static void get_frag_property_flags (const fragS
*, frag_flags
*);
10264 static bfd_vma
frag_flags_to_number (const frag_flags
*);
10265 static void add_xt_prop_frags
10266 (segT
, segT
, xtensa_block_info
**, frag_flags_fn
);
10268 /* Set up property tables after relaxation. */
10271 xtensa_post_relax_hook (void)
10273 xtensa_move_seg_list_to_beginning (literal_head
);
10275 xtensa_find_unmarked_state_frags ();
10276 xtensa_mark_frags_for_org ();
10277 xtensa_mark_difference_of_two_symbols ();
10279 xtensa_create_property_segments (get_frag_is_literal
,
10281 XTENSA_LIT_SEC_NAME
,
10283 xtensa_create_xproperty_segments (get_frag_property_flags
,
10284 XTENSA_PROP_SEC_NAME
,
10287 if (warn_unaligned_branch_targets
)
10288 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
10289 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
10293 /* This function is only meaningful after xtensa_move_literals. */
10296 get_frag_is_literal (const fragS
*fragP
)
10298 assert (fragP
!= NULL
);
10299 return fragP
->tc_frag_data
.is_literal
;
10304 xtensa_create_property_segments (frag_predicate property_function
,
10305 frag_predicate end_property_function
,
10306 const char *section_name_base
,
10307 xt_section_type sec_type
)
10311 /* Walk over all of the current segments.
10312 Walk over each fragment
10313 For each non-empty fragment,
10314 Build a property record (append where possible). */
10316 for (seclist
= &stdoutput
->sections
;
10317 seclist
&& *seclist
;
10318 seclist
= &(*seclist
)->next
)
10320 segT sec
= *seclist
;
10323 flags
= bfd_get_section_flags (stdoutput
, sec
);
10324 if (flags
& SEC_DEBUGGING
)
10326 if (!(flags
& SEC_ALLOC
))
10329 if (section_has_property (sec
, property_function
))
10332 xtensa_get_property_section (sec
, section_name_base
);
10333 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10334 xtensa_block_info
**xt_blocks
=
10335 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10336 /* Walk over all of the frchains here and add new sections. */
10337 add_xt_block_frags (sec
, insn_sec
, xt_blocks
, property_function
,
10338 end_property_function
);
10342 /* Now we fill them out.... */
10344 for (seclist
= &stdoutput
->sections
;
10345 seclist
&& *seclist
;
10346 seclist
= &(*seclist
)->next
)
10348 segment_info_type
*seginfo
;
10349 xtensa_block_info
*block
;
10350 segT sec
= *seclist
;
10352 seginfo
= seg_info (sec
);
10353 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10357 xtensa_block_info
*cur_block
;
10358 /* This is a section with some data. */
10360 bfd_size_type rec_size
;
10362 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10365 rec_size
= num_recs
* 8;
10366 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10368 /* In order to make this work with the assembler, we have to
10369 build some frags and then build the "fixups" for it. It
10370 would be easier to just set the contents then set the
10375 /* Allocate a fragment and leak it. */
10377 bfd_size_type frag_size
;
10379 frchainS
*frchainP
;
10383 frag_size
= sizeof (fragS
) + rec_size
;
10384 fragP
= (fragS
*) xmalloc (frag_size
);
10386 memset (fragP
, 0, frag_size
);
10387 fragP
->fr_address
= 0;
10388 fragP
->fr_next
= NULL
;
10389 fragP
->fr_fix
= rec_size
;
10391 fragP
->fr_type
= rs_fill
;
10392 /* The rest are zeros. */
10394 frchainP
= seginfo
->frchainP
;
10395 frchainP
->frch_root
= fragP
;
10396 frchainP
->frch_last
= fragP
;
10398 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10399 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10401 seginfo
->fix_root
= fixes
;
10402 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10404 frag_data
= &fragP
->fr_literal
[0];
10405 for (i
= 0; i
< num_recs
; i
++)
10407 fixS
*fix
= &fixes
[i
];
10408 assert (cur_block
);
10410 /* Write the fixup. */
10411 if (i
!= num_recs
- 1)
10412 fix
->fx_next
= &fixes
[i
+ 1];
10414 fix
->fx_next
= NULL
;
10417 fix
->fx_frag
= fragP
;
10418 fix
->fx_where
= i
* 8;
10419 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10420 fix
->fx_offset
= cur_block
->offset
;
10421 fix
->fx_r_type
= BFD_RELOC_32
;
10422 fix
->fx_file
= "Internal Assembly";
10425 /* Write the length. */
10426 md_number_to_chars (&frag_data
[4 + 8 * i
],
10427 cur_block
->size
, 4);
10428 cur_block
= cur_block
->next
;
10437 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
10438 const char *section_name_base
,
10439 xt_section_type sec_type
)
10443 /* Walk over all of the current segments.
10444 Walk over each fragment.
10445 For each fragment that has instructions,
10446 build an instruction record (append where possible). */
10448 for (seclist
= &stdoutput
->sections
;
10449 seclist
&& *seclist
;
10450 seclist
= &(*seclist
)->next
)
10452 segT sec
= *seclist
;
10455 flags
= bfd_get_section_flags (stdoutput
, sec
);
10456 if ((flags
& SEC_DEBUGGING
)
10457 || !(flags
& SEC_ALLOC
)
10458 || (flags
& SEC_MERGE
))
10461 if (section_has_xproperty (sec
, flag_fn
))
10464 xtensa_get_property_section (sec
, section_name_base
);
10465 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10466 xtensa_block_info
**xt_blocks
=
10467 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10468 /* Walk over all of the frchains here and add new sections. */
10469 add_xt_prop_frags (sec
, insn_sec
, xt_blocks
, flag_fn
);
10473 /* Now we fill them out.... */
10475 for (seclist
= &stdoutput
->sections
;
10476 seclist
&& *seclist
;
10477 seclist
= &(*seclist
)->next
)
10479 segment_info_type
*seginfo
;
10480 xtensa_block_info
*block
;
10481 segT sec
= *seclist
;
10483 seginfo
= seg_info (sec
);
10484 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10488 xtensa_block_info
*cur_block
;
10489 /* This is a section with some data. */
10491 bfd_size_type rec_size
;
10493 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10496 rec_size
= num_recs
* (8 + 4);
10497 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10499 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
10501 /* In order to make this work with the assembler, we have to build
10502 some frags then build the "fixups" for it. It would be easier to
10503 just set the contents then set the arlents. */
10507 /* Allocate a fragment and (unfortunately) leak it. */
10509 bfd_size_type frag_size
;
10511 frchainS
*frchainP
;
10515 frag_size
= sizeof (fragS
) + rec_size
;
10516 fragP
= (fragS
*) xmalloc (frag_size
);
10518 memset (fragP
, 0, frag_size
);
10519 fragP
->fr_address
= 0;
10520 fragP
->fr_next
= NULL
;
10521 fragP
->fr_fix
= rec_size
;
10523 fragP
->fr_type
= rs_fill
;
10524 /* The rest are zeros. */
10526 frchainP
= seginfo
->frchainP
;
10527 frchainP
->frch_root
= fragP
;
10528 frchainP
->frch_last
= fragP
;
10530 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10531 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10533 seginfo
->fix_root
= fixes
;
10534 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10536 frag_data
= &fragP
->fr_literal
[0];
10537 for (i
= 0; i
< num_recs
; i
++)
10539 fixS
*fix
= &fixes
[i
];
10540 assert (cur_block
);
10542 /* Write the fixup. */
10543 if (i
!= num_recs
- 1)
10544 fix
->fx_next
= &fixes
[i
+ 1];
10546 fix
->fx_next
= NULL
;
10549 fix
->fx_frag
= fragP
;
10550 fix
->fx_where
= i
* (8 + 4);
10551 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10552 fix
->fx_offset
= cur_block
->offset
;
10553 fix
->fx_r_type
= BFD_RELOC_32
;
10554 fix
->fx_file
= "Internal Assembly";
10557 /* Write the length. */
10558 md_number_to_chars (&frag_data
[4 + (8+4) * i
],
10559 cur_block
->size
, 4);
10560 md_number_to_chars (&frag_data
[8 + (8+4) * i
],
10561 frag_flags_to_number (&cur_block
->flags
),
10563 cur_block
= cur_block
->next
;
10571 static segment_info_type
*
10572 retrieve_segment_info (segT seg
)
10574 segment_info_type
*seginfo
;
10575 seginfo
= (segment_info_type
*) bfd_get_section_userdata (stdoutput
, seg
);
10578 frchainS
*frchainP
;
10580 seginfo
= (segment_info_type
*) xmalloc (sizeof (*seginfo
));
10581 memset ((void *) seginfo
, 0, sizeof (*seginfo
));
10582 seginfo
->fix_root
= NULL
;
10583 seginfo
->fix_tail
= NULL
;
10584 seginfo
->bfd_section
= seg
;
10586 /* We will not be dealing with these, only our special ones. */
10587 bfd_set_section_userdata (stdoutput
, seg
, (void *) seginfo
);
10589 frchainP
= (frchainS
*) xmalloc (sizeof (frchainS
));
10590 frchainP
->frch_root
= NULL
;
10591 frchainP
->frch_last
= NULL
;
10592 frchainP
->frch_next
= NULL
;
10593 frchainP
->frch_subseg
= 0;
10594 frchainP
->fix_root
= NULL
;
10595 frchainP
->fix_tail
= NULL
;
10596 /* Do not init the objstack. */
10597 /* obstack_begin (&frchainP->frch_obstack, chunksize); */
10598 /* frchainP->frch_frag_now = fragP; */
10599 frchainP
->frch_frag_now
= NULL
;
10601 seginfo
->frchainP
= frchainP
;
10609 section_has_property (segT sec
, frag_predicate property_function
)
10611 segment_info_type
*seginfo
= seg_info (sec
);
10614 if (seginfo
&& seginfo
->frchainP
)
10616 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10618 if (property_function (fragP
)
10619 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10628 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
10630 segment_info_type
*seginfo
= seg_info (sec
);
10633 if (seginfo
&& seginfo
->frchainP
)
10635 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10637 frag_flags prop_flags
;
10638 property_function (fragP
, &prop_flags
);
10639 if (!xtensa_frag_flags_is_empty (&prop_flags
))
10647 /* Two types of block sections exist right now: literal and insns. */
10650 add_xt_block_frags (segT sec
,
10652 xtensa_block_info
**xt_block
,
10653 frag_predicate property_function
,
10654 frag_predicate end_property_function
)
10656 segment_info_type
*seg_info
;
10657 segment_info_type
*xt_seg_info
;
10658 bfd_vma seg_offset
;
10661 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
10662 seg_info
= retrieve_segment_info (sec
);
10664 /* Build it if needed. */
10665 while (*xt_block
!= NULL
)
10666 xt_block
= &(*xt_block
)->next
;
10667 /* We are either at NULL at the beginning or at the end. */
10669 /* Walk through the frags. */
10672 if (seg_info
->frchainP
)
10674 for (fragP
= seg_info
->frchainP
->frch_root
;
10676 fragP
= fragP
->fr_next
)
10678 if (property_function (fragP
)
10679 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10681 if (*xt_block
!= NULL
)
10683 if ((*xt_block
)->offset
+ (*xt_block
)->size
10684 == fragP
->fr_address
)
10685 (*xt_block
)->size
+= fragP
->fr_fix
;
10687 xt_block
= &((*xt_block
)->next
);
10689 if (*xt_block
== NULL
)
10691 xtensa_block_info
*new_block
= (xtensa_block_info
*)
10692 xmalloc (sizeof (xtensa_block_info
));
10693 new_block
->sec
= sec
;
10694 new_block
->offset
= fragP
->fr_address
;
10695 new_block
->size
= fragP
->fr_fix
;
10696 new_block
->next
= NULL
;
10697 xtensa_frag_flags_init (&new_block
->flags
);
10698 *xt_block
= new_block
;
10700 if (end_property_function
10701 && end_property_function (fragP
))
10703 xt_block
= &((*xt_block
)->next
);
10711 /* Break the encapsulation of add_xt_prop_frags here. */
10714 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
10716 if (prop_flags
->is_literal
10717 || prop_flags
->is_insn
10718 || prop_flags
->is_data
10719 || prop_flags
->is_unreachable
)
10726 xtensa_frag_flags_init (frag_flags
*prop_flags
)
10728 memset (prop_flags
, 0, sizeof (frag_flags
));
10733 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
10735 xtensa_frag_flags_init (prop_flags
);
10736 if (fragP
->tc_frag_data
.is_literal
)
10737 prop_flags
->is_literal
= TRUE
;
10738 if (fragP
->tc_frag_data
.is_specific_opcode
10739 || fragP
->tc_frag_data
.is_no_transform
)
10740 prop_flags
->is_no_transform
= TRUE
;
10741 if (fragP
->tc_frag_data
.is_unreachable
)
10742 prop_flags
->is_unreachable
= TRUE
;
10743 else if (fragP
->tc_frag_data
.is_insn
)
10745 prop_flags
->is_insn
= TRUE
;
10746 if (fragP
->tc_frag_data
.is_loop_target
)
10747 prop_flags
->insn
.is_loop_target
= TRUE
;
10748 if (fragP
->tc_frag_data
.is_branch_target
)
10749 prop_flags
->insn
.is_branch_target
= TRUE
;
10750 if (fragP
->tc_frag_data
.is_no_density
)
10751 prop_flags
->insn
.is_no_density
= TRUE
;
10752 if (fragP
->tc_frag_data
.use_absolute_literals
)
10753 prop_flags
->insn
.is_abslit
= TRUE
;
10755 if (fragP
->tc_frag_data
.is_align
)
10757 prop_flags
->is_align
= TRUE
;
10758 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
10759 if (xtensa_frag_flags_is_empty (prop_flags
))
10760 prop_flags
->is_data
= TRUE
;
10766 frag_flags_to_number (const frag_flags
*prop_flags
)
10769 if (prop_flags
->is_literal
)
10770 num
|= XTENSA_PROP_LITERAL
;
10771 if (prop_flags
->is_insn
)
10772 num
|= XTENSA_PROP_INSN
;
10773 if (prop_flags
->is_data
)
10774 num
|= XTENSA_PROP_DATA
;
10775 if (prop_flags
->is_unreachable
)
10776 num
|= XTENSA_PROP_UNREACHABLE
;
10777 if (prop_flags
->insn
.is_loop_target
)
10778 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
10779 if (prop_flags
->insn
.is_branch_target
)
10781 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
10782 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
10785 if (prop_flags
->insn
.is_no_density
)
10786 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
10787 if (prop_flags
->is_no_transform
)
10788 num
|= XTENSA_PROP_NO_TRANSFORM
;
10789 if (prop_flags
->insn
.is_no_reorder
)
10790 num
|= XTENSA_PROP_INSN_NO_REORDER
;
10791 if (prop_flags
->insn
.is_abslit
)
10792 num
|= XTENSA_PROP_INSN_ABSLIT
;
10794 if (prop_flags
->is_align
)
10796 num
|= XTENSA_PROP_ALIGN
;
10797 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
10805 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
10806 const frag_flags
*prop_flags_2
)
10808 /* Cannot combine with an end marker. */
10810 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
10812 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
10814 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
10817 if (prop_flags_1
->is_insn
)
10819 /* Properties of the beginning of the frag. */
10820 if (prop_flags_2
->insn
.is_loop_target
)
10822 if (prop_flags_2
->insn
.is_branch_target
)
10824 if (prop_flags_1
->insn
.is_no_density
!=
10825 prop_flags_2
->insn
.is_no_density
)
10827 if (prop_flags_1
->is_no_transform
!=
10828 prop_flags_2
->is_no_transform
)
10830 if (prop_flags_1
->insn
.is_no_reorder
!=
10831 prop_flags_2
->insn
.is_no_reorder
)
10833 if (prop_flags_1
->insn
.is_abslit
!=
10834 prop_flags_2
->insn
.is_abslit
)
10838 if (prop_flags_1
->is_align
)
10846 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
10849 unsigned align_bits
;
10851 if (!xt_block
->flags
.is_align
)
10852 return xt_block
->size
;
10854 end_addr
= xt_block
->offset
+ xt_block
->size
;
10855 align_bits
= xt_block
->flags
.alignment
;
10856 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
10857 return end_addr
- xt_block
->offset
;
10862 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
10863 const xtensa_block_info
*xt_block_2
)
10865 if (xt_block
->sec
!= xt_block_2
->sec
)
10867 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
10868 != xt_block_2
->offset
)
10871 if (xt_block_2
->size
== 0
10872 && (!xt_block_2
->flags
.is_unreachable
10873 || xt_block
->flags
.is_unreachable
))
10875 if (xt_block_2
->flags
.is_align
10876 && xt_block
->flags
.is_align
)
10878 /* Nothing needed. */
10879 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
10884 if (xt_block_2
->flags
.is_align
)
10886 /* Push alignment to previous entry. */
10887 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
10888 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10893 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
10894 &xt_block_2
->flags
))
10897 xt_block
->size
+= xt_block_2
->size
;
10899 if (xt_block_2
->flags
.is_align
)
10901 xt_block
->flags
.is_align
= TRUE
;
10902 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10910 add_xt_prop_frags (segT sec
,
10912 xtensa_block_info
**xt_block
,
10913 frag_flags_fn property_function
)
10915 segment_info_type
*seg_info
;
10916 segment_info_type
*xt_seg_info
;
10917 bfd_vma seg_offset
;
10920 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
10921 seg_info
= retrieve_segment_info (sec
);
10922 /* Build it if needed. */
10923 while (*xt_block
!= NULL
)
10925 xt_block
= &(*xt_block
)->next
;
10927 /* We are either at NULL at the beginning or at the end. */
10929 /* Walk through the frags. */
10932 if (seg_info
->frchainP
)
10934 for (fragP
= seg_info
->frchainP
->frch_root
; fragP
;
10935 fragP
= fragP
->fr_next
)
10937 xtensa_block_info tmp_block
;
10938 tmp_block
.sec
= sec
;
10939 tmp_block
.offset
= fragP
->fr_address
;
10940 tmp_block
.size
= fragP
->fr_fix
;
10941 tmp_block
.next
= NULL
;
10942 property_function (fragP
, &tmp_block
.flags
);
10944 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
10945 /* && fragP->fr_fix != 0) */
10947 if ((*xt_block
) == NULL
10948 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
10950 xtensa_block_info
*new_block
;
10951 if ((*xt_block
) != NULL
)
10952 xt_block
= &(*xt_block
)->next
;
10953 new_block
= (xtensa_block_info
*)
10954 xmalloc (sizeof (xtensa_block_info
));
10955 *new_block
= tmp_block
;
10956 *xt_block
= new_block
;
10964 /* op_placement_info_table */
10966 /* op_placement_info makes it easier to determine which
10967 ops can go in which slots. */
10970 init_op_placement_info_table (void)
10972 xtensa_isa isa
= xtensa_default_isa
;
10973 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
10974 xtensa_opcode opcode
;
10977 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
10979 op_placement_table
= (op_placement_info_table
)
10980 xmalloc (sizeof (op_placement_info
) * num_opcodes
);
10981 assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
10983 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
10985 op_placement_info
*opi
= &op_placement_table
[opcode
];
10986 /* FIXME: Make tinsn allocation dynamic. */
10987 if (xtensa_opcode_num_operands (isa
, opcode
) >= MAX_INSN_ARGS
)
10988 as_fatal (_("too many operands in instruction"));
10989 opi
->narrowest
= XTENSA_UNDEFINED
;
10990 opi
->narrowest_size
= 0x7F;
10991 opi
->narrowest_slot
= 0;
10993 opi
->num_formats
= 0;
10995 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
10997 opi
->slots
[fmt
] = 0;
10998 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
11000 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
11002 int fmt_length
= xtensa_format_length (isa
, fmt
);
11004 set_bit (fmt
, opi
->formats
);
11005 set_bit (slot
, opi
->slots
[fmt
]);
11006 if (fmt_length
< opi
->narrowest_size
11007 || (fmt_length
== opi
->narrowest_size
11008 && (xtensa_format_num_slots (isa
, fmt
)
11009 < xtensa_format_num_slots (isa
,
11012 opi
->narrowest
= fmt
;
11013 opi
->narrowest_size
= fmt_length
;
11014 opi
->narrowest_slot
= slot
;
11019 opi
->num_formats
++;
11022 xtensa_insnbuf_free (isa
, ibuf
);
11027 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
11029 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
11033 /* If the opcode is available in a single slot format, return its size. */
11036 xg_get_single_size (xtensa_opcode opcode
)
11038 return op_placement_table
[opcode
].narrowest_size
;
11042 static xtensa_format
11043 xg_get_single_format (xtensa_opcode opcode
)
11045 return op_placement_table
[opcode
].narrowest
;
11050 xg_get_single_slot (xtensa_opcode opcode
)
11052 return op_placement_table
[opcode
].narrowest_slot
;
11056 /* Instruction Stack Functions (from "xtensa-istack.h"). */
11059 istack_init (IStack
*stack
)
11061 memset (stack
, 0, sizeof (IStack
));
11067 istack_empty (IStack
*stack
)
11069 return (stack
->ninsn
== 0);
11074 istack_full (IStack
*stack
)
11076 return (stack
->ninsn
== MAX_ISTACK
);
11080 /* Return a pointer to the top IStack entry.
11081 It is an error to call this if istack_empty () is TRUE. */
11084 istack_top (IStack
*stack
)
11086 int rec
= stack
->ninsn
- 1;
11087 assert (!istack_empty (stack
));
11088 return &stack
->insn
[rec
];
11092 /* Add a new TInsn to an IStack.
11093 It is an error to call this if istack_full () is TRUE. */
11096 istack_push (IStack
*stack
, TInsn
*insn
)
11098 int rec
= stack
->ninsn
;
11099 assert (!istack_full (stack
));
11100 stack
->insn
[rec
] = *insn
;
11105 /* Clear space for the next TInsn on the IStack and return a pointer
11106 to it. It is an error to call this if istack_full () is TRUE. */
11109 istack_push_space (IStack
*stack
)
11111 int rec
= stack
->ninsn
;
11113 assert (!istack_full (stack
));
11114 insn
= &stack
->insn
[rec
];
11121 /* Remove the last pushed instruction. It is an error to call this if
11122 istack_empty () returns TRUE. */
11125 istack_pop (IStack
*stack
)
11127 int rec
= stack
->ninsn
- 1;
11128 assert (!istack_empty (stack
));
11130 tinsn_init (&stack
->insn
[rec
]);
11134 /* TInsn functions. */
11137 tinsn_init (TInsn
*dst
)
11139 memset (dst
, 0, sizeof (TInsn
));
11143 /* Return TRUE if ANY of the operands in the insn are symbolic. */
11146 tinsn_has_symbolic_operands (const TInsn
*insn
)
11149 int n
= insn
->ntok
;
11151 assert (insn
->insn_type
== ITYPE_INSN
);
11153 for (i
= 0; i
< n
; ++i
)
11155 switch (insn
->tok
[i
].X_op
)
11169 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
11171 xtensa_isa isa
= xtensa_default_isa
;
11173 int n
= insn
->ntok
;
11175 assert (insn
->insn_type
== ITYPE_INSN
);
11177 for (i
= 0; i
< n
; ++i
)
11179 switch (insn
->tok
[i
].X_op
)
11187 /* Errors for these types are caught later. */
11192 /* Symbolic immediates are only allowed on the last immediate
11193 operand. At this time, CONST16 is the only opcode where we
11194 support non-PC-relative relocations. */
11195 if (i
!= get_relaxable_immed (insn
->opcode
)
11196 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
11197 && insn
->opcode
!= xtensa_const16_opcode
))
11199 as_bad (_("invalid symbolic operand"));
11208 /* For assembly code with complex expressions (e.g. subtraction),
11209 we have to build them in the literal pool so that
11210 their results are calculated correctly after relaxation.
11211 The relaxation only handles expressions that
11212 boil down to SYMBOL + OFFSET. */
11215 tinsn_has_complex_operands (const TInsn
*insn
)
11218 int n
= insn
->ntok
;
11219 assert (insn
->insn_type
== ITYPE_INSN
);
11220 for (i
= 0; i
< n
; ++i
)
11222 switch (insn
->tok
[i
].X_op
)
11238 /* Encode a TInsn opcode and its constant operands into slotbuf.
11239 Return TRUE if there is a symbol in the immediate field. This
11240 function assumes that:
11241 1) The number of operands are correct.
11242 2) The insn_type is ITYPE_INSN.
11243 3) The opcode can be encoded in the specified format and slot.
11244 4) Operands are either O_constant or O_symbol, and all constants fit. */
11247 tinsn_to_slotbuf (xtensa_format fmt
,
11250 xtensa_insnbuf slotbuf
)
11252 xtensa_isa isa
= xtensa_default_isa
;
11253 xtensa_opcode opcode
= tinsn
->opcode
;
11254 bfd_boolean has_fixup
= FALSE
;
11255 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11258 assert (tinsn
->insn_type
== ITYPE_INSN
);
11259 if (noperands
!= tinsn
->ntok
)
11260 as_fatal (_("operand number mismatch"));
11262 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
11264 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
11265 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
11269 for (i
= 0; i
< noperands
; i
++)
11271 expressionS
*expr
= &tinsn
->tok
[i
];
11277 switch (expr
->X_op
)
11280 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11282 /* The register number has already been checked in
11283 expression_maybe_register, so we don't need to check here. */
11284 opnd_value
= expr
->X_add_number
;
11285 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11286 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
11289 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
11293 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11295 as_where (&file_name
, &line
);
11296 /* It is a constant and we called this function
11297 then we have to try to fit it. */
11298 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
11299 expr
->X_add_number
, file_name
, line
);
11312 /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded
11313 into a multi-slot instruction, fill the other slots with NOPs.
11314 Return TRUE if there is a symbol in the immediate field. See also the
11315 assumptions listed for tinsn_to_slotbuf. */
11318 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
11320 static xtensa_insnbuf slotbuf
= 0;
11321 static vliw_insn vinsn
;
11322 xtensa_isa isa
= xtensa_default_isa
;
11323 bfd_boolean has_fixup
= FALSE
;
11328 slotbuf
= xtensa_insnbuf_alloc (isa
);
11329 xg_init_vinsn (&vinsn
);
11332 xg_clear_vinsn (&vinsn
);
11334 bundle_tinsn (tinsn
, &vinsn
);
11336 xtensa_format_encode (isa
, vinsn
.format
, insnbuf
);
11338 for (i
= 0; i
< vinsn
.num_slots
; i
++)
11340 /* Only one slot may have a fix-up because the rest contains NOPs. */
11342 tinsn_to_slotbuf (vinsn
.format
, i
, &vinsn
.slots
[i
], vinsn
.slotbuf
[i
]);
11343 xtensa_format_set_slot (isa
, vinsn
.format
, i
, insnbuf
, vinsn
.slotbuf
[i
]);
11350 /* Check the instruction arguments. Return TRUE on failure. */
11353 tinsn_check_arguments (const TInsn
*insn
)
11355 xtensa_isa isa
= xtensa_default_isa
;
11356 xtensa_opcode opcode
= insn
->opcode
;
11358 if (opcode
== XTENSA_UNDEFINED
)
11360 as_bad (_("invalid opcode"));
11364 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
11366 as_bad (_("too few operands"));
11370 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
11372 as_bad (_("too many operands"));
11379 /* Load an instruction from its encoded form. */
11382 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
11386 xg_init_vinsn (&vinsn
);
11387 vinsn_from_chars (&vinsn
, f
);
11389 *tinsn
= vinsn
.slots
[slot
];
11390 xg_free_vinsn (&vinsn
);
11395 tinsn_from_insnbuf (TInsn
*tinsn
,
11396 xtensa_insnbuf slotbuf
,
11401 xtensa_isa isa
= xtensa_default_isa
;
11403 /* Find the immed. */
11404 tinsn_init (tinsn
);
11405 tinsn
->insn_type
= ITYPE_INSN
;
11406 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
11407 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
11408 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
11409 for (i
= 0; i
< tinsn
->ntok
; i
++)
11411 set_expr_const (&tinsn
->tok
[i
],
11412 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
11413 tinsn
->opcode
, i
));
11418 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
11421 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
11423 xtensa_opcode opcode
= tinsn
->opcode
;
11426 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
11428 opnum
= get_relaxable_immed (opcode
);
11429 assert (opnum
>= 0);
11430 set_expr_symbol_offset (&tinsn
->tok
[opnum
],
11431 fragP
->tc_frag_data
.slot_symbols
[slot
],
11432 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11438 get_num_stack_text_bytes (IStack
*istack
)
11441 int text_bytes
= 0;
11443 for (i
= 0; i
< istack
->ninsn
; i
++)
11445 TInsn
*tinsn
= &istack
->insn
[i
];
11446 if (tinsn
->insn_type
== ITYPE_INSN
)
11447 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
11454 get_num_stack_literal_bytes (IStack
*istack
)
11459 for (i
= 0; i
< istack
->ninsn
; i
++)
11461 TInsn
*tinsn
= &istack
->insn
[i
];
11462 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
11469 /* vliw_insn functions. */
11472 xg_init_vinsn (vliw_insn
*v
)
11475 xtensa_isa isa
= xtensa_default_isa
;
11477 xg_clear_vinsn (v
);
11479 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
11480 if (v
->insnbuf
== NULL
)
11481 as_fatal (_("out of memory"));
11483 for (i
= 0; i
< MAX_SLOTS
; i
++)
11485 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
11486 if (v
->slotbuf
[i
] == NULL
)
11487 as_fatal (_("out of memory"));
11493 xg_clear_vinsn (vliw_insn
*v
)
11497 memset (v
, 0, offsetof (vliw_insn
, insnbuf
));
11499 v
->format
= XTENSA_UNDEFINED
;
11501 v
->inside_bundle
= FALSE
;
11503 if (xt_saved_debug_type
!= DEBUG_NONE
)
11504 debug_type
= xt_saved_debug_type
;
11506 for (i
= 0; i
< MAX_SLOTS
; i
++)
11507 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
11512 vinsn_has_specific_opcodes (vliw_insn
*v
)
11516 for (i
= 0; i
< v
->num_slots
; i
++)
11518 if (v
->slots
[i
].is_specific_opcode
)
11526 xg_free_vinsn (vliw_insn
*v
)
11529 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
11530 for (i
= 0; i
< MAX_SLOTS
; i
++)
11531 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
11535 /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic
11536 operands. See also the assumptions listed for tinsn_to_slotbuf. */
11539 vinsn_to_insnbuf (vliw_insn
*vinsn
,
11542 bfd_boolean record_fixup
)
11544 xtensa_isa isa
= xtensa_default_isa
;
11545 xtensa_format fmt
= vinsn
->format
;
11546 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
11548 bfd_boolean has_fixup
= FALSE
;
11550 xtensa_format_encode (isa
, fmt
, insnbuf
);
11552 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
11554 TInsn
*tinsn
= &vinsn
->slots
[slot
];
11555 bfd_boolean tinsn_has_fixup
=
11556 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
11557 vinsn
->slotbuf
[slot
]);
11559 xtensa_format_set_slot (isa
, fmt
, slot
,
11560 insnbuf
, vinsn
->slotbuf
[slot
]);
11561 if (tinsn_has_fixup
)
11564 xtensa_opcode opcode
= tinsn
->opcode
;
11565 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11568 for (i
= 0; i
< noperands
; i
++)
11570 expressionS
* expr
= &tinsn
->tok
[i
];
11571 switch (expr
->X_op
)
11576 if (get_relaxable_immed (opcode
) == i
)
11578 /* Add a fix record for the instruction, except if this
11579 function is being called prior to relaxation, i.e.,
11580 if record_fixup is false, and the instruction might
11581 be relaxed later. */
11583 || tinsn
->is_specific_opcode
11584 || !xg_is_relaxable_insn (tinsn
, 0))
11586 xg_add_opcode_fix (tinsn
, i
, fmt
, slot
, expr
, fragP
,
11587 frag_offset
- fragP
->fr_literal
);
11591 if (expr
->X_op
!= O_symbol
)
11592 as_bad (_("invalid operand"));
11593 tinsn
->symbol
= expr
->X_add_symbol
;
11594 tinsn
->offset
= expr
->X_add_number
;
11598 as_bad (_("symbolic operand not allowed"));
11606 as_bad (_("expression too complex"));
11618 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
11620 static xtensa_insnbuf insnbuf
= NULL
;
11621 static xtensa_insnbuf slotbuf
= NULL
;
11624 xtensa_isa isa
= xtensa_default_isa
;
11628 insnbuf
= xtensa_insnbuf_alloc (isa
);
11629 slotbuf
= xtensa_insnbuf_alloc (isa
);
11632 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) f
, 0);
11633 fmt
= xtensa_format_decode (isa
, insnbuf
);
11634 if (fmt
== XTENSA_UNDEFINED
)
11635 as_fatal (_("cannot decode instruction format"));
11636 vinsn
->format
= fmt
;
11637 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
11639 for (i
= 0; i
< vinsn
->num_slots
; i
++)
11641 TInsn
*tinsn
= &vinsn
->slots
[i
];
11642 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
11643 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
11648 /* Expression utilities. */
11650 /* Return TRUE if the expression is an integer constant. */
11653 expr_is_const (const expressionS
*s
)
11655 return (s
->X_op
== O_constant
);
11659 /* Get the expression constant.
11660 Calling this is illegal if expr_is_const () returns TRUE. */
11663 get_expr_const (const expressionS
*s
)
11665 assert (expr_is_const (s
));
11666 return s
->X_add_number
;
11670 /* Set the expression to a constant value. */
11673 set_expr_const (expressionS
*s
, offsetT val
)
11675 s
->X_op
= O_constant
;
11676 s
->X_add_number
= val
;
11677 s
->X_add_symbol
= NULL
;
11678 s
->X_op_symbol
= NULL
;
11683 expr_is_register (const expressionS
*s
)
11685 return (s
->X_op
== O_register
);
11689 /* Get the expression constant.
11690 Calling this is illegal if expr_is_const () returns TRUE. */
11693 get_expr_register (const expressionS
*s
)
11695 assert (expr_is_register (s
));
11696 return s
->X_add_number
;
11700 /* Set the expression to a symbol + constant offset. */
11703 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
11705 s
->X_op
= O_symbol
;
11706 s
->X_add_symbol
= sym
;
11707 s
->X_op_symbol
= NULL
; /* unused */
11708 s
->X_add_number
= offset
;
11712 /* Return TRUE if the two expressions are equal. */
11715 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
11717 if (s1
->X_op
!= s2
->X_op
)
11719 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
11721 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
11723 if (s1
->X_add_number
!= s2
->X_add_number
)
11730 copy_expr (expressionS
*dst
, const expressionS
*src
)
11732 memcpy (dst
, src
, sizeof (expressionS
));
11736 /* Support for the "--rename-section" option. */
11738 struct rename_section_struct
11742 struct rename_section_struct
*next
;
11745 static struct rename_section_struct
*section_rename
;
11748 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
11749 entries to the section_rename list. Note: Specifying multiple
11750 renamings separated by colons is not documented and is retained only
11751 for backward compatibility. */
11754 build_section_rename (const char *arg
)
11756 struct rename_section_struct
*r
;
11757 char *this_arg
= NULL
;
11758 char *next_arg
= NULL
;
11760 for (this_arg
= xstrdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
11762 char *old_name
, *new_name
;
11766 next_arg
= strchr (this_arg
, ':');
11774 old_name
= this_arg
;
11775 new_name
= strchr (this_arg
, '=');
11777 if (*old_name
== '\0')
11779 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
11782 if (!new_name
|| new_name
[1] == '\0')
11784 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
11791 /* Check for invalid section renaming. */
11792 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11794 if (strcmp (r
->old_name
, old_name
) == 0)
11795 as_bad (_("section %s renamed multiple times"), old_name
);
11796 if (strcmp (r
->new_name
, new_name
) == 0)
11797 as_bad (_("multiple sections remapped to output section %s"),
11802 r
= (struct rename_section_struct
*)
11803 xmalloc (sizeof (struct rename_section_struct
));
11804 r
->old_name
= xstrdup (old_name
);
11805 r
->new_name
= xstrdup (new_name
);
11806 r
->next
= section_rename
;
11807 section_rename
= r
;
11813 xtensa_section_rename (char *name
)
11815 struct rename_section_struct
*r
= section_rename
;
11817 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11819 if (strcmp (r
->old_name
, name
) == 0)
11820 return r
->new_name
;