1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright 2003, 2004, 2005 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
25 #include "safe-ctype.h"
26 #include "tc-xtensa.h"
29 #include "xtensa-relax.h"
30 #include "xtensa-istack.h"
31 #include "dwarf2dbg.h"
32 #include "struc-symbol.h"
33 #include "xtensa-config.h"
36 #define uint32 unsigned int
39 #define int32 signed int
44 Naming conventions (used somewhat inconsistently):
45 The xtensa_ functions are exported
46 The xg_ functions are internal
48 We also have a couple of different extensibility mechanisms.
49 1) The idiom replacement:
50 This is used when a line is first parsed to
51 replace an instruction pattern with another instruction
52 It is currently limited to replacements of instructions
53 with constant operands.
54 2) The xtensa-relax.c mechanism that has stronger instruction
55 replacement patterns. When an instruction's immediate field
56 does not fit the next instruction sequence is attempted.
57 In addition, "narrow" opcodes are supported this way. */
60 /* Define characters with special meanings to GAS. */
61 const char comment_chars
[] = "#";
62 const char line_comment_chars
[] = "#";
63 const char line_separator_chars
[] = ";";
64 const char EXP_CHARS
[] = "eE";
65 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
68 /* Flags to indicate whether the hardware supports the density and
69 absolute literals options. */
71 bfd_boolean density_supported
= XCHAL_HAVE_DENSITY
;
72 bfd_boolean absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
74 /* Maximum width we would pad an unreachable frag to get alignment. */
75 #define UNREACHABLE_MAX_WIDTH 8
77 static vliw_insn cur_vinsn
;
79 unsigned xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
81 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
83 /* Some functions are only valid in the front end. This variable
84 allows us to assert that we haven't crossed over into the
86 static bfd_boolean past_xtensa_end
= FALSE
;
88 /* Flags for properties of the last instruction in a segment. */
89 #define FLAG_IS_A0_WRITER 0x1
90 #define FLAG_IS_BAD_LOOPEND 0x2
93 /* We define a special segment names ".literal" to place literals
94 into. The .fini and .init sections are special because they
95 contain code that is moved together by the linker. We give them
96 their own special .fini.literal and .init.literal sections. */
98 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
99 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
100 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
101 #define INIT_SECTION_NAME xtensa_section_rename (".init")
102 #define FINI_LITERAL_SECTION_NAME xtensa_section_rename (".fini.literal")
103 #define INIT_LITERAL_SECTION_NAME xtensa_section_rename (".init.literal")
106 /* This type is used for the directive_stack to keep track of the
107 state of the literal collection pools. */
109 typedef struct lit_state_struct
111 const char *lit_seg_name
;
112 const char *lit4_seg_name
;
113 const char *init_lit_seg_name
;
114 const char *fini_lit_seg_name
;
121 static lit_state default_lit_sections
;
124 /* We keep lists of literal segments. The seg_list type is the node
125 for such a list. The *_literal_head locals are the heads of the
126 various lists. All of these lists have a dummy node at the start. */
128 typedef struct seg_list_struct
130 struct seg_list_struct
*next
;
134 static seg_list literal_head_h
;
135 static seg_list
*literal_head
= &literal_head_h
;
136 static seg_list init_literal_head_h
;
137 static seg_list
*init_literal_head
= &init_literal_head_h
;
138 static seg_list fini_literal_head_h
;
139 static seg_list
*fini_literal_head
= &fini_literal_head_h
;
142 /* Lists of symbols. We keep a list of symbols that label the current
143 instruction, so that we can adjust the symbols when inserting alignment
144 for various instructions. We also keep a list of all the symbols on
145 literals, so that we can fix up those symbols when the literals are
146 later moved into the text sections. */
148 typedef struct sym_list_struct
150 struct sym_list_struct
*next
;
154 static sym_list
*insn_labels
= NULL
;
155 static sym_list
*free_insn_labels
= NULL
;
156 static sym_list
*saved_insn_labels
= NULL
;
158 static sym_list
*literal_syms
;
161 /* Flags to determine whether to prefer const16 or l32r
162 if both options are available. */
163 int prefer_const16
= 0;
166 /* Global flag to indicate when we are emitting literals. */
167 int generating_literals
= 0;
169 /* The following PROPERTY table definitions are copied from
170 <elf/xtensa.h> and must be kept in sync with the code there. */
172 /* Flags in the property tables to specify whether blocks of memory
173 are literals, instructions, data, or unreachable. For
174 instructions, blocks that begin loop targets and branch targets are
175 designated. Blocks that do not allow density, instruction
176 reordering or transformation are also specified. Finally, for
177 branch targets, branch target alignment priority is included.
178 Alignment of the next block is specified in the current block
179 and the size of the current block does not include any fill required
180 to align to the next block. */
182 #define XTENSA_PROP_LITERAL 0x00000001
183 #define XTENSA_PROP_INSN 0x00000002
184 #define XTENSA_PROP_DATA 0x00000004
185 #define XTENSA_PROP_UNREACHABLE 0x00000008
186 /* Instruction only properties at beginning of code. */
187 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
188 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
189 /* Instruction only properties about code. */
190 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
191 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
192 #define XTENSA_PROP_INSN_NO_TRANSFORM 0x00000100
194 /* Branch target alignment information. This transmits information
195 to the linker optimization about the priority of aligning a
196 particular block for branch target alignment: None, low priority,
197 high priority, or required. These only need to be checked in
198 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
201 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
202 case XTENSA_PROP_BT_ALIGN_NONE:
203 case XTENSA_PROP_BT_ALIGN_LOW:
204 case XTENSA_PROP_BT_ALIGN_HIGH:
205 case XTENSA_PROP_BT_ALIGN_REQUIRE:
207 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
209 /* No branch target alignment. */
210 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
211 /* Low priority branch target alignment. */
212 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
213 /* High priority branch target alignment. */
214 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
215 /* Required branch target alignment. */
216 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
218 #define GET_XTENSA_PROP_BT_ALIGN(flag) \
219 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
220 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
221 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
222 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
225 /* Alignment is specified in the block BEFORE the one that needs
226 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
227 get the required alignment specified as a power of 2. Use
228 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
229 alignment. Be careful of side effects since the SET will evaluate
230 flags twice. Also, note that the SIZE of a block in the property
231 table does not include the alignment size, so the alignment fill
232 must be calculated to determine if two blocks are contiguous.
233 TEXT_ALIGN is not currently implemented but is a placeholder for a
234 possible future implementation. */
236 #define XTENSA_PROP_ALIGN 0x00000800
238 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
240 #define GET_XTENSA_PROP_ALIGNMENT(flag) \
241 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
242 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
243 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
244 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
246 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
249 /* Structure for saving instruction and alignment per-fragment data
250 that will be written to the object file. This structure is
251 equivalent to the actual data that will be written out to the file
252 but is easier to use. We provide a conversion to file flags
253 in frag_flags_to_number. */
255 typedef struct frag_flags_struct frag_flags
;
257 struct frag_flags_struct
259 /* is_literal should only be used after xtensa_move_literals.
260 If you need to check if you are generating a literal fragment,
261 then use the generating_literals global. */
263 unsigned is_literal
: 1;
264 unsigned is_insn
: 1;
265 unsigned is_data
: 1;
266 unsigned is_unreachable
: 1;
270 unsigned is_loop_target
: 1;
271 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
272 unsigned bt_align_priority
: 2;
274 unsigned is_no_density
: 1;
275 /* no_longcalls flag does not need to be placed in the object file. */
276 /* is_specific_opcode implies no_transform. */
277 unsigned is_no_transform
: 1;
279 unsigned is_no_reorder
: 1;
281 /* Uses absolute literal addressing for l32r. */
282 unsigned is_abslit
: 1;
284 unsigned is_align
: 1;
285 unsigned alignment
: 5;
289 /* Structure for saving information about a block of property data
290 for frags that have the same flags. */
291 struct xtensa_block_info_struct
297 struct xtensa_block_info_struct
*next
;
301 /* Structure for saving the current state before emitting literals. */
302 typedef struct emit_state_struct
307 int generating_literals
;
311 /* Opcode placement information */
313 typedef unsigned long long bitfield
;
314 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
315 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
316 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
318 #define MAX_FORMATS 32
320 typedef struct op_placement_info_struct
323 /* A number describing how restrictive the issue is for this
324 opcode. For example, an opcode that fits lots of different
325 formats has a high freedom, as does an opcode that fits
326 only one format but many slots in that format. The most
327 restrictive is the opcode that fits only one slot in one
330 /* The single format (i.e., if the op can live in a bundle by itself),
331 narrowest format, and widest format the op can be bundled in
333 xtensa_format single
;
334 xtensa_format narrowest
;
335 xtensa_format widest
;
340 /* formats is a bitfield with the Nth bit set
341 if the opcode fits in the Nth xtensa_format. */
344 /* slots[N]'s Mth bit is set if the op fits in the
345 Mth slot of the Nth xtensa_format. */
346 bitfield slots
[MAX_FORMATS
];
348 /* A count of the number of slots in a given format
349 an op can fit (i.e., the bitcount of the slot field above). */
350 char slots_in_format
[MAX_FORMATS
];
352 } op_placement_info
, *op_placement_info_table
;
354 op_placement_info_table op_placement_table
;
357 /* Extra expression types. */
359 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
360 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
361 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
374 directive_literal_prefix
,
376 directive_absolute_literals
,
377 directive_last_directive
383 bfd_boolean can_be_negated
;
386 const directive_infoS directive_info
[] =
389 { "literal", FALSE
},
391 { "transform", TRUE
},
392 { "freeregs", FALSE
},
393 { "longcalls", TRUE
},
394 { "literal_prefix", FALSE
},
395 { "schedule", TRUE
},
396 { "absolute-literals", TRUE
}
399 bfd_boolean directive_state
[] =
403 #if !XCHAL_HAVE_DENSITY
408 TRUE
, /* transform */
409 FALSE
, /* freeregs */
410 FALSE
, /* longcalls */
411 FALSE
, /* literal_prefix */
413 #if XSHAL_USE_ABSOLUTE_LITERALS
414 TRUE
/* absolute_literals */
416 FALSE
/* absolute_literals */
421 /* Directive functions. */
423 static void xtensa_begin_directive (int);
424 static void xtensa_end_directive (int);
425 static void xtensa_literal_prefix (char const *, int);
426 static void xtensa_literal_position (int);
427 static void xtensa_literal_pseudo (int);
428 static void xtensa_frequency_pseudo (int);
429 static void xtensa_elf_cons (int);
431 /* Parsing and Idiom Translation. */
433 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
435 /* Various Other Internal Functions. */
437 extern bfd_boolean
xg_is_single_relaxable_insn (TInsn
*, TInsn
*, bfd_boolean
);
438 static bfd_boolean
xg_build_to_insn (TInsn
*, TInsn
*, BuildInstr
*);
439 static void xtensa_mark_literal_pool_location (void);
440 static addressT
get_expanded_loop_offset (xtensa_opcode
);
441 static fragS
*get_literal_pool_location (segT
);
442 static void set_literal_pool_location (segT
, fragS
*);
443 static void xtensa_set_frag_assembly_state (fragS
*);
444 static void finish_vinsn (vliw_insn
*);
445 static bfd_boolean
emit_single_op (TInsn
*);
446 static int total_frag_text_expansion (fragS
*);
448 /* Alignment Functions. */
450 static int get_text_align_power (unsigned);
451 static int get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
452 static int branch_align_power (segT
);
454 /* Helpers for xtensa_relax_frag(). */
456 static long relax_frag_add_nop (fragS
*);
458 /* Accessors for additional per-subsegment information. */
460 static unsigned get_last_insn_flags (segT
, subsegT
);
461 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
462 static float get_subseg_total_freq (segT
, subsegT
);
463 static float get_subseg_target_freq (segT
, subsegT
);
464 static void set_subseg_freq (segT
, subsegT
, float, float);
466 /* Segment list functions. */
468 static void xtensa_move_literals (void);
469 static void xtensa_reorder_segments (void);
470 static void xtensa_switch_to_literal_fragment (emit_state
*);
471 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
472 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
473 static void xtensa_restore_emit_state (emit_state
*);
474 static void cache_literal_section
475 (seg_list
*, const char *, segT
*, bfd_boolean
);
477 /* Import from elf32-xtensa.c in BFD library. */
479 extern char *xtensa_get_property_section_name (asection
*, const char *);
481 /* op_placement_info functions. */
483 static void init_op_placement_info_table (void);
484 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
485 static int xg_get_single_size (xtensa_opcode
);
486 static xtensa_format
xg_get_single_format (xtensa_opcode
);
488 /* TInsn and IStack functions. */
490 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
491 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
492 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
493 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
494 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
495 static void tinsn_from_chars (TInsn
*, char *, int);
496 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
497 static int get_num_stack_text_bytes (IStack
*);
498 static int get_num_stack_literal_bytes (IStack
*);
500 /* vliw_insn functions. */
502 static void xg_init_vinsn (vliw_insn
*);
503 static void xg_clear_vinsn (vliw_insn
*);
504 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
505 static void xg_free_vinsn (vliw_insn
*);
506 static bfd_boolean vinsn_to_insnbuf
507 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
508 static void vinsn_from_chars (vliw_insn
*, char *);
510 /* Expression Utilities. */
512 bfd_boolean
expr_is_const (const expressionS
*);
513 offsetT
get_expr_const (const expressionS
*);
514 void set_expr_const (expressionS
*, offsetT
);
515 bfd_boolean
expr_is_register (const expressionS
*);
516 offsetT
get_expr_register (const expressionS
*);
517 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
518 static void set_expr_symbol_offset_diff
519 (expressionS
*, symbolS
*, symbolS
*, offsetT
);
520 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
521 static void copy_expr (expressionS
*, const expressionS
*);
523 /* Section renaming. */
525 static void build_section_rename (const char *);
528 /* ISA imported from bfd. */
529 extern xtensa_isa xtensa_default_isa
;
531 extern int target_big_endian
;
533 static xtensa_opcode xtensa_addi_opcode
;
534 static xtensa_opcode xtensa_addmi_opcode
;
535 static xtensa_opcode xtensa_call0_opcode
;
536 static xtensa_opcode xtensa_call4_opcode
;
537 static xtensa_opcode xtensa_call8_opcode
;
538 static xtensa_opcode xtensa_call12_opcode
;
539 static xtensa_opcode xtensa_callx0_opcode
;
540 static xtensa_opcode xtensa_callx4_opcode
;
541 static xtensa_opcode xtensa_callx8_opcode
;
542 static xtensa_opcode xtensa_callx12_opcode
;
543 static xtensa_opcode xtensa_const16_opcode
;
544 static xtensa_opcode xtensa_entry_opcode
;
545 static xtensa_opcode xtensa_movi_opcode
;
546 static xtensa_opcode xtensa_movi_n_opcode
;
547 static xtensa_opcode xtensa_isync_opcode
;
548 static xtensa_opcode xtensa_jx_opcode
;
549 static xtensa_opcode xtensa_l32r_opcode
;
550 static xtensa_opcode xtensa_loop_opcode
;
551 static xtensa_opcode xtensa_loopnez_opcode
;
552 static xtensa_opcode xtensa_loopgtz_opcode
;
553 static xtensa_opcode xtensa_nop_opcode
;
554 static xtensa_opcode xtensa_nop_n_opcode
;
555 static xtensa_opcode xtensa_or_opcode
;
556 static xtensa_opcode xtensa_ret_opcode
;
557 static xtensa_opcode xtensa_ret_n_opcode
;
558 static xtensa_opcode xtensa_retw_opcode
;
559 static xtensa_opcode xtensa_retw_n_opcode
;
560 static xtensa_opcode xtensa_rsr_lcount_opcode
;
561 static xtensa_opcode xtensa_waiti_opcode
;
564 /* Command-line Options. */
566 bfd_boolean use_literal_section
= TRUE
;
567 static bfd_boolean align_targets
= TRUE
;
568 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
569 static bfd_boolean has_a0_b_retw
= FALSE
;
570 static bfd_boolean workaround_a0_b_retw
= FALSE
;
571 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
572 static bfd_boolean workaround_short_loop
= FALSE
;
573 static bfd_boolean maybe_has_short_loop
= FALSE
;
574 static bfd_boolean workaround_close_loop_end
= FALSE
;
575 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
577 /* When workaround_short_loops is TRUE, all loops with early exits must
578 have at least 3 instructions. workaround_all_short_loops is a modifier
579 to the workaround_short_loop flag. In addition to the
580 workaround_short_loop actions, all straightline loopgtz and loopnez
581 must have at least 3 instructions. */
583 static bfd_boolean workaround_all_short_loops
= FALSE
;
587 xtensa_setup_hw_workarounds (int earliest
, int latest
)
589 if (earliest
> latest
)
590 as_fatal (_("illegal range of target hardware versions"));
592 /* Enable all workarounds for pre-T1050.0 hardware. */
593 if (earliest
< 105000 || latest
< 105000)
595 workaround_a0_b_retw
|= TRUE
;
596 workaround_b_j_loop_end
|= TRUE
;
597 workaround_short_loop
|= TRUE
;
598 workaround_close_loop_end
|= TRUE
;
599 workaround_all_short_loops
|= TRUE
;
606 option_density
= OPTION_MD_BASE
,
613 option_no_link_relax
,
621 option_text_section_literals
,
622 option_no_text_section_literals
,
624 option_absolute_literals
,
625 option_no_absolute_literals
,
627 option_align_targets
,
628 option_no_align_targets
,
630 option_warn_unaligned_targets
,
635 option_workaround_a0_b_retw
,
636 option_no_workaround_a0_b_retw
,
638 option_workaround_b_j_loop_end
,
639 option_no_workaround_b_j_loop_end
,
641 option_workaround_short_loop
,
642 option_no_workaround_short_loop
,
644 option_workaround_all_short_loops
,
645 option_no_workaround_all_short_loops
,
647 option_workaround_close_loop_end
,
648 option_no_workaround_close_loop_end
,
650 option_no_workarounds
,
652 option_rename_section_name
,
655 option_prefer_const16
,
657 option_target_hardware
660 const char *md_shortopts
= "";
662 struct option md_longopts
[] =
664 { "density", no_argument
, NULL
, option_density
},
665 { "no-density", no_argument
, NULL
, option_no_density
},
667 /* Both "relax" and "generics" are deprecated and treated as equivalent
668 to the "transform" option. */
669 { "relax", no_argument
, NULL
, option_relax
},
670 { "no-relax", no_argument
, NULL
, option_no_relax
},
671 { "generics", no_argument
, NULL
, option_generics
},
672 { "no-generics", no_argument
, NULL
, option_no_generics
},
674 { "transform", no_argument
, NULL
, option_transform
},
675 { "no-transform", no_argument
, NULL
, option_no_transform
},
676 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
677 { "no-text-section-literals", no_argument
, NULL
,
678 option_no_text_section_literals
},
679 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
680 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
681 /* This option was changed from -align-target to -target-align
682 because it conflicted with the "-al" option. */
683 { "target-align", no_argument
, NULL
, option_align_targets
},
684 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
685 { "warn-unaligned-targets", no_argument
, NULL
,
686 option_warn_unaligned_targets
},
687 { "longcalls", no_argument
, NULL
, option_longcalls
},
688 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
690 { "no-workaround-a0-b-retw", no_argument
, NULL
,
691 option_no_workaround_a0_b_retw
},
692 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
694 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
695 option_no_workaround_b_j_loop_end
},
696 { "workaround-b-j-loop-end", no_argument
, NULL
,
697 option_workaround_b_j_loop_end
},
699 { "no-workaround-short-loops", no_argument
, NULL
,
700 option_no_workaround_short_loop
},
701 { "workaround-short-loops", no_argument
, NULL
,
702 option_workaround_short_loop
},
704 { "no-workaround-all-short-loops", no_argument
, NULL
,
705 option_no_workaround_all_short_loops
},
706 { "workaround-all-short-loop", no_argument
, NULL
,
707 option_workaround_all_short_loops
},
709 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
710 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
712 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
714 { "no-workaround-close-loop-end", no_argument
, NULL
,
715 option_no_workaround_close_loop_end
},
716 { "workaround-close-loop-end", no_argument
, NULL
,
717 option_workaround_close_loop_end
},
719 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
721 { "link-relax", no_argument
, NULL
, option_link_relax
},
722 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
724 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
726 { NULL
, no_argument
, NULL
, 0 }
729 size_t md_longopts_size
= sizeof md_longopts
;
733 md_parse_option (int c
, char *arg
)
738 as_warn (_("--density option is ignored"));
740 case option_no_density
:
741 as_warn (_("--no-density option is ignored"));
743 case option_link_relax
:
746 case option_no_link_relax
:
749 case option_generics
:
750 as_warn (_("--generics is deprecated; use --transform instead"));
751 return md_parse_option (option_transform
, arg
);
752 case option_no_generics
:
753 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
754 return md_parse_option (option_no_transform
, arg
);
756 as_warn (_("--relax is deprecated; use --transform instead"));
757 return md_parse_option (option_transform
, arg
);
758 case option_no_relax
:
759 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
760 return md_parse_option (option_no_transform
, arg
);
761 case option_longcalls
:
762 directive_state
[directive_longcalls
] = TRUE
;
764 case option_no_longcalls
:
765 directive_state
[directive_longcalls
] = FALSE
;
767 case option_text_section_literals
:
768 use_literal_section
= FALSE
;
770 case option_no_text_section_literals
:
771 use_literal_section
= TRUE
;
773 case option_absolute_literals
:
774 if (!absolute_literals_supported
)
776 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
779 directive_state
[directive_absolute_literals
] = TRUE
;
781 case option_no_absolute_literals
:
782 directive_state
[directive_absolute_literals
] = FALSE
;
785 case option_workaround_a0_b_retw
:
786 workaround_a0_b_retw
= TRUE
;
788 case option_no_workaround_a0_b_retw
:
789 workaround_a0_b_retw
= FALSE
;
791 case option_workaround_b_j_loop_end
:
792 workaround_b_j_loop_end
= TRUE
;
794 case option_no_workaround_b_j_loop_end
:
795 workaround_b_j_loop_end
= FALSE
;
798 case option_workaround_short_loop
:
799 workaround_short_loop
= TRUE
;
801 case option_no_workaround_short_loop
:
802 workaround_short_loop
= FALSE
;
805 case option_workaround_all_short_loops
:
806 workaround_all_short_loops
= TRUE
;
808 case option_no_workaround_all_short_loops
:
809 workaround_all_short_loops
= FALSE
;
812 case option_workaround_close_loop_end
:
813 workaround_close_loop_end
= TRUE
;
815 case option_no_workaround_close_loop_end
:
816 workaround_close_loop_end
= FALSE
;
819 case option_no_workarounds
:
820 workaround_a0_b_retw
= FALSE
;
821 workaround_b_j_loop_end
= FALSE
;
822 workaround_short_loop
= FALSE
;
823 workaround_all_short_loops
= FALSE
;
824 workaround_close_loop_end
= FALSE
;
827 case option_align_targets
:
828 align_targets
= TRUE
;
830 case option_no_align_targets
:
831 align_targets
= FALSE
;
834 case option_warn_unaligned_targets
:
835 warn_unaligned_branch_targets
= TRUE
;
838 case option_rename_section_name
:
839 build_section_rename (arg
);
843 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
844 should be emitted or not. FIXME: Not implemented. */
847 case option_prefer_l32r
:
849 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
853 case option_prefer_const16
:
855 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
859 case option_target_hardware
:
861 int earliest
, latest
= 0;
862 if (*arg
== 0 || *arg
== '-')
863 as_fatal (_("invalid target hardware version"));
865 earliest
= strtol (arg
, &arg
, 0);
869 else if (*arg
== '-')
872 as_fatal (_("invalid target hardware version"));
873 latest
= strtol (arg
, &arg
, 0);
876 as_fatal (_("invalid target hardware version"));
878 xtensa_setup_hw_workarounds (earliest
, latest
);
882 case option_transform
:
883 /* This option has no affect other than to use the defaults,
884 which are already set. */
887 case option_no_transform
:
888 /* This option turns off all transformations of any kind.
889 However, because we want to preserve the state of other
890 directives, we only change its own field. Thus, before
891 you perform any transformation, always check if transform
892 is available. If you use the functions we provide for this
893 purpose, you will be ok. */
894 directive_state
[directive_transform
] = FALSE
;
904 md_show_usage (FILE *stream
)
908 --[no-]text-section-literals\n\
909 [Do not] put literals in the text section\n\
910 --[no-]absolute-literals\n\
911 [Do not] default to use non-PC-relative literals\n\
912 --[no-]target-align [Do not] try to align branch targets\n\
913 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
914 --[no-]transform [Do not] transform instructions\n\
915 --rename-section old=new Rename section 'old' to 'new'\n", stream
);
919 /* Functions related to the list of current label symbols. */
922 xtensa_add_insn_label (symbolS
*sym
)
926 if (!free_insn_labels
)
927 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
930 l
= free_insn_labels
;
931 free_insn_labels
= l
->next
;
935 l
->next
= insn_labels
;
941 xtensa_clear_insn_labels (void)
945 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
952 /* The "loops_ok" argument is provided to allow ignoring labels that
953 define loop ends. This fixes a bug where the NOPs to align a
954 loop opcode were included in a previous zero-cost loop:
973 This argument is used to prevent moving the NOP to before the
974 loop-end label, which is what you want in this special case. */
977 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
, bfd_boolean loops_ok
)
981 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
983 symbolS
*lit_sym
= lit
->sym
;
984 if (loops_ok
|| ! symbol_get_tc (lit_sym
)->is_loop_target
)
986 S_SET_VALUE (lit_sym
, new_offset
);
987 symbol_set_frag (lit_sym
, new_frag
);
993 /* Directive data and functions. */
995 typedef struct state_stackS_struct
997 directiveE directive
;
999 bfd_boolean old_state
;
1003 struct state_stackS_struct
*prev
;
1006 state_stackS
*directive_state_stack
;
1008 const pseudo_typeS md_pseudo_table
[] =
1010 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
1011 { "literal_position", xtensa_literal_position
, 0 },
1012 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
1013 { "long", xtensa_elf_cons
, 4 },
1014 { "word", xtensa_elf_cons
, 4 },
1015 { "short", xtensa_elf_cons
, 2 },
1016 { "begin", xtensa_begin_directive
, 0 },
1017 { "end", xtensa_end_directive
, 0 },
1018 { "literal", xtensa_literal_pseudo
, 0 },
1019 { "frequency", xtensa_frequency_pseudo
, 0 },
1025 use_transform (void)
1027 /* After md_end, you should be checking frag by frag, rather
1028 than state directives. */
1029 assert (!past_xtensa_end
);
1030 return directive_state
[directive_transform
];
1035 do_align_targets (void)
1037 /* Do not use this function after md_end; just look at align_targets
1038 instead. There is no target-align directive, so alignment is either
1039 enabled for all frags or not done at all. */
1040 assert (!past_xtensa_end
);
1041 return align_targets
&& use_transform ();
1046 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1050 state_stackS
*stack
= (state_stackS
*) xmalloc (sizeof (state_stackS
));
1052 as_where (&file
, &line
);
1054 stack
->directive
= directive
;
1055 stack
->negated
= negated
;
1056 stack
->old_state
= directive_state
[directive
];
1059 stack
->datum
= datum
;
1060 stack
->prev
= directive_state_stack
;
1061 directive_state_stack
= stack
;
1063 directive_state
[directive
] = !negated
;
1068 directive_pop (directiveE
*directive
,
1069 bfd_boolean
*negated
,
1074 state_stackS
*top
= directive_state_stack
;
1076 if (!directive_state_stack
)
1078 as_bad (_("unmatched end directive"));
1079 *directive
= directive_none
;
1083 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1084 *directive
= top
->directive
;
1085 *negated
= top
->negated
;
1088 *datum
= top
->datum
;
1089 directive_state_stack
= top
->prev
;
1095 directive_balance (void)
1097 while (directive_state_stack
)
1099 directiveE directive
;
1100 bfd_boolean negated
;
1105 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1106 as_warn_where ((char *) file
, line
,
1107 _(".begin directive with no matching .end directive"));
1113 inside_directive (directiveE dir
)
1115 state_stackS
*top
= directive_state_stack
;
1117 while (top
&& top
->directive
!= dir
)
1120 return (top
!= NULL
);
1125 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1129 char *directive_string
;
1131 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1136 input_line_pointer
+= 3;
1139 len
= strspn (input_line_pointer
,
1140 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1142 /* This code is a hack to make .begin [no-][generics|relax] exactly
1143 equivalent to .begin [no-]transform. We should remove it when
1144 we stop accepting those options. */
1146 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1148 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1149 directive_string
= "transform";
1151 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1153 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1154 directive_string
= "transform";
1157 directive_string
= input_line_pointer
;
1159 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1161 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1163 input_line_pointer
+= len
;
1164 *directive
= (directiveE
) i
;
1165 if (*negated
&& !directive_info
[i
].can_be_negated
)
1166 as_bad (_("directive %s cannot be negated"),
1167 directive_info
[i
].name
);
1172 as_bad (_("unknown directive"));
1173 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1178 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1180 directiveE directive
;
1181 bfd_boolean negated
;
1186 get_directive (&directive
, &negated
);
1187 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1189 discard_rest_of_line ();
1193 if (cur_vinsn
.inside_bundle
)
1194 as_bad (_("directives are not valid inside bundles"));
1198 case directive_literal
:
1199 if (!inside_directive (directive_literal
))
1201 /* Previous labels go with whatever follows this directive, not with
1202 the literal, so save them now. */
1203 saved_insn_labels
= insn_labels
;
1206 as_warn (_(".begin literal is deprecated; use .literal instead"));
1207 state
= (emit_state
*) xmalloc (sizeof (emit_state
));
1208 xtensa_switch_to_literal_fragment (state
);
1209 directive_push (directive_literal
, negated
, state
);
1212 case directive_literal_prefix
:
1213 /* Have to flush pending output because a movi relaxed to an l32r
1214 might produce a literal. */
1215 md_flush_pending_output ();
1216 /* Check to see if the current fragment is a literal
1217 fragment. If it is, then this operation is not allowed. */
1218 if (generating_literals
)
1220 as_bad (_("cannot set literal_prefix inside literal fragment"));
1224 /* Allocate the literal state for this section and push
1225 onto the directive stack. */
1226 ls
= xmalloc (sizeof (lit_state
));
1229 *ls
= default_lit_sections
;
1231 directive_push (directive_literal_prefix
, negated
, ls
);
1233 /* Parse the new prefix from the input_line_pointer. */
1235 len
= strspn (input_line_pointer
,
1236 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1237 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1239 /* Process the new prefix. */
1240 xtensa_literal_prefix (input_line_pointer
, len
);
1242 /* Skip the name in the input line. */
1243 input_line_pointer
+= len
;
1246 case directive_freeregs
:
1247 /* This information is currently unused, but we'll accept the statement
1248 and just discard the rest of the line. This won't check the syntax,
1249 but it will accept every correct freeregs directive. */
1250 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1251 directive_push (directive_freeregs
, negated
, 0);
1254 case directive_schedule
:
1255 md_flush_pending_output ();
1256 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1257 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1258 directive_push (directive_schedule
, negated
, 0);
1259 xtensa_set_frag_assembly_state (frag_now
);
1262 case directive_density
:
1263 as_warn (_(".begin [no-]density is ignored"));
1266 case directive_absolute_literals
:
1267 md_flush_pending_output ();
1268 if (!absolute_literals_supported
&& !negated
)
1270 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1273 xtensa_set_frag_assembly_state (frag_now
);
1274 directive_push (directive
, negated
, 0);
1278 md_flush_pending_output ();
1279 xtensa_set_frag_assembly_state (frag_now
);
1280 directive_push (directive
, negated
, 0);
1284 demand_empty_rest_of_line ();
1289 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1291 directiveE begin_directive
, end_directive
;
1292 bfd_boolean begin_negated
, end_negated
;
1296 emit_state
**state_ptr
;
1299 if (cur_vinsn
.inside_bundle
)
1300 as_bad (_("directives are not valid inside bundles"));
1302 get_directive (&end_directive
, &end_negated
);
1304 md_flush_pending_output ();
1306 switch (end_directive
)
1308 case (directiveE
) XTENSA_UNDEFINED
:
1309 discard_rest_of_line ();
1312 case directive_density
:
1313 as_warn (_(".end [no-]density is ignored"));
1314 demand_empty_rest_of_line ();
1317 case directive_absolute_literals
:
1318 if (!absolute_literals_supported
&& !end_negated
)
1320 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1321 demand_empty_rest_of_line ();
1330 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1331 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1332 (const void **) state_ptr
);
1334 if (begin_directive
!= directive_none
)
1336 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1338 as_bad (_("does not match begin %s%s at %s:%d"),
1339 begin_negated
? "no-" : "",
1340 directive_info
[begin_directive
].name
, file
, line
);
1344 switch (end_directive
)
1346 case directive_literal
:
1347 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1348 xtensa_restore_emit_state (state
);
1349 xtensa_set_frag_assembly_state (frag_now
);
1351 if (!inside_directive (directive_literal
))
1353 /* Restore the list of current labels. */
1354 xtensa_clear_insn_labels ();
1355 insn_labels
= saved_insn_labels
;
1359 case directive_literal_prefix
:
1360 /* Restore the default collection sections from saved state. */
1361 s
= (lit_state
*) state
;
1364 if (use_literal_section
)
1365 default_lit_sections
= *s
;
1367 /* free the state storage */
1371 case directive_schedule
:
1372 case directive_freeregs
:
1376 xtensa_set_frag_assembly_state (frag_now
);
1382 demand_empty_rest_of_line ();
1386 /* Place an aligned literal fragment at the current location. */
1389 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1391 md_flush_pending_output ();
1393 if (inside_directive (directive_literal
))
1394 as_warn (_(".literal_position inside literal directive; ignoring"));
1395 xtensa_mark_literal_pool_location ();
1397 demand_empty_rest_of_line ();
1398 xtensa_clear_insn_labels ();
1402 /* Support .literal label, expr, ... */
1405 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1408 char *p
, *base_name
;
1412 if (inside_directive (directive_literal
))
1414 as_bad (_(".literal not allowed inside .begin literal region"));
1415 ignore_rest_of_line ();
1419 md_flush_pending_output ();
1421 /* Previous labels go with whatever follows this directive, not with
1422 the literal, so save them now. */
1423 saved_insn_labels
= insn_labels
;
1426 /* If we are using text-section literals, then this is the right value... */
1429 base_name
= input_line_pointer
;
1431 xtensa_switch_to_literal_fragment (&state
);
1433 /* ...but if we aren't using text-section-literals, then we
1434 need to put them in the section we just switched to. */
1435 if (use_literal_section
|| directive_state
[directive_absolute_literals
])
1438 /* All literals are aligned to four-byte boundaries. */
1439 frag_align (2, 0, 0);
1440 record_alignment (now_seg
, 2);
1442 c
= get_symbol_end ();
1443 /* Just after name is now '\0'. */
1444 p
= input_line_pointer
;
1448 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1450 as_bad (_("expected comma or colon after symbol name; "
1451 "rest of line ignored"));
1452 ignore_rest_of_line ();
1453 xtensa_restore_emit_state (&state
);
1461 input_line_pointer
++; /* skip ',' or ':' */
1463 xtensa_elf_cons (4);
1465 xtensa_restore_emit_state (&state
);
1467 /* Restore the list of current labels. */
1468 xtensa_clear_insn_labels ();
1469 insn_labels
= saved_insn_labels
;
1474 xtensa_literal_prefix (char const *start
, int len
)
1476 char *name
, *linkonce_suffix
;
1477 char *newname
, *newname4
;
1478 size_t linkonce_len
;
1480 /* Get a null-terminated copy of the name. */
1481 name
= xmalloc (len
+ 1);
1484 strncpy (name
, start
, len
);
1487 /* Allocate the sections (interesting note: the memory pointing to
1488 the name is actually used for the name by the new section). */
1490 newname
= xmalloc (len
+ strlen (".literal") + 1);
1491 newname4
= xmalloc (len
+ strlen (".lit4") + 1);
1493 linkonce_len
= sizeof (".gnu.linkonce.") - 1;
1494 if (strncmp (name
, ".gnu.linkonce.", linkonce_len
) == 0
1495 && (linkonce_suffix
= strchr (name
+ linkonce_len
, '.')) != 0)
1497 strcpy (newname
, ".gnu.linkonce.literal");
1498 strcpy (newname4
, ".gnu.linkonce.lit4");
1500 strcat (newname
, linkonce_suffix
);
1501 strcat (newname4
, linkonce_suffix
);
1505 int suffix_pos
= len
;
1507 /* If the section name ends with ".text", then replace that suffix
1508 instead of appending an additional suffix. */
1509 if (len
>= 5 && strcmp (name
+ len
- 5, ".text") == 0)
1512 strcpy (newname
, name
);
1513 strcpy (newname4
, name
);
1515 strcpy (newname
+ suffix_pos
, ".literal");
1516 strcpy (newname4
+ suffix_pos
, ".lit4");
1519 /* Note that cache_literal_section does not create a segment if
1520 it already exists. */
1521 default_lit_sections
.lit_seg
= NULL
;
1522 default_lit_sections
.lit4_seg
= NULL
;
1524 /* Canonicalizing section names allows renaming literal
1525 sections to occur correctly. */
1526 default_lit_sections
.lit_seg_name
= tc_canonicalize_symbol_name (newname
);
1527 default_lit_sections
.lit4_seg_name
= tc_canonicalize_symbol_name (newname4
);
1533 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1536 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1538 float fall_through_f
, target_f
;
1540 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1541 if (fall_through_f
< 0)
1543 as_bad (_("fall through frequency must be greater than 0"));
1544 ignore_rest_of_line ();
1548 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1551 as_bad (_("branch target frequency must be greater than 0"));
1552 ignore_rest_of_line ();
1556 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1558 demand_empty_rest_of_line ();
1562 /* Like normal .long/.short/.word, except support @plt, etc.
1563 Clobbers input_line_pointer, checks end-of-line. */
1566 xtensa_elf_cons (int nbytes
)
1569 bfd_reloc_code_real_type reloc
;
1571 md_flush_pending_output ();
1573 if (cur_vinsn
.inside_bundle
)
1574 as_bad (_("directives are not valid inside bundles"));
1576 if (is_it_end_of_statement ())
1578 demand_empty_rest_of_line ();
1585 if (exp
.X_op
== O_symbol
1586 && *input_line_pointer
== '@'
1587 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1590 reloc_howto_type
*reloc_howto
=
1591 bfd_reloc_type_lookup (stdoutput
, reloc
);
1593 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1594 as_bad (_("unsupported relocation"));
1595 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1596 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1597 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1598 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1599 as_bad (_("opcode-specific %s relocation used outside "
1600 "an instruction"), reloc_howto
->name
);
1601 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1602 as_bad (_("%s relocations do not fit in %d bytes"),
1603 reloc_howto
->name
, nbytes
);
1606 char *p
= frag_more ((int) nbytes
);
1607 xtensa_set_frag_assembly_state (frag_now
);
1608 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1609 nbytes
, &exp
, 0, reloc
);
1613 emit_expr (&exp
, (unsigned int) nbytes
);
1615 while (*input_line_pointer
++ == ',');
1617 input_line_pointer
--; /* Put terminator back into stream. */
1618 demand_empty_rest_of_line ();
1622 /* Parsing and Idiom Translation. */
1624 /* Parse @plt, etc. and return the desired relocation. */
1625 static bfd_reloc_code_real_type
1626 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1632 bfd_reloc_code_real_type reloc
;
1640 struct map_bfd
*ptr
;
1642 #define MAP(str,reloc) { str, sizeof (str) - 1, reloc }
1644 static struct map_bfd mapping
[] =
1646 MAP ("l", BFD_RELOC_LO16
),
1647 MAP ("h", BFD_RELOC_HI16
),
1648 MAP ("plt", BFD_RELOC_XTENSA_PLT
),
1649 { (char *) 0, 0, BFD_RELOC_UNUSED
}
1653 return BFD_RELOC_NONE
;
1655 for (ch
= *str
, str2
= ident
;
1656 (str2
< ident
+ sizeof (ident
) - 1
1657 && (ISALNUM (ch
) || ch
== '@'));
1660 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1667 for (ptr
= &mapping
[0]; ptr
->length
> 0; ptr
++)
1668 if (ch
== ptr
->string
[0]
1669 && len
== ptr
->length
1670 && memcmp (ident
, ptr
->string
, ptr
->length
) == 0)
1672 /* Now check for "identifier@suffix+constant". */
1673 if (*str
== '-' || *str
== '+')
1675 char *orig_line
= input_line_pointer
;
1676 expressionS new_exp
;
1678 input_line_pointer
= str
;
1679 expression (&new_exp
);
1680 if (new_exp
.X_op
== O_constant
)
1682 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1683 str
= input_line_pointer
;
1686 if (&input_line_pointer
!= str_p
)
1687 input_line_pointer
= orig_line
;
1694 return BFD_RELOC_UNUSED
;
1699 expression_end (const char *name
)
1722 #define ERROR_REG_NUM ((unsigned) -1)
1725 tc_get_register (const char *prefix
)
1728 const char *next_expr
;
1729 const char *old_line_pointer
;
1732 old_line_pointer
= input_line_pointer
;
1734 if (*input_line_pointer
== '$')
1735 ++input_line_pointer
;
1737 /* Accept "sp" as a synonym for "a1". */
1738 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1739 && expression_end (input_line_pointer
+ 2))
1741 input_line_pointer
+= 2;
1742 return 1; /* AR[1] */
1745 while (*input_line_pointer
++ == *prefix
++)
1747 --input_line_pointer
;
1752 as_bad (_("bad register name: %s"), old_line_pointer
);
1753 return ERROR_REG_NUM
;
1756 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1758 as_bad (_("bad register number: %s"), input_line_pointer
);
1759 return ERROR_REG_NUM
;
1764 while (ISDIGIT ((int) *input_line_pointer
))
1765 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1767 if (!(next_expr
= expression_end (input_line_pointer
)))
1769 as_bad (_("bad register name: %s"), old_line_pointer
);
1770 return ERROR_REG_NUM
;
1773 input_line_pointer
= (char *) next_expr
;
1780 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1782 xtensa_isa isa
= xtensa_default_isa
;
1784 /* Check if this is an immediate operand. */
1785 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1787 bfd_reloc_code_real_type reloc
;
1788 segT t
= expression (tok
);
1789 if (t
== absolute_section
1790 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1792 assert (tok
->X_op
== O_constant
);
1793 tok
->X_op
= O_symbol
;
1794 tok
->X_add_symbol
= &abs_symbol
;
1797 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1798 && (reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1799 && (reloc
!= BFD_RELOC_NONE
))
1804 case BFD_RELOC_UNUSED
:
1805 as_bad (_("unsupported relocation"));
1808 case BFD_RELOC_XTENSA_PLT
:
1809 tok
->X_op
= O_pltrel
;
1812 case BFD_RELOC_LO16
:
1813 if (tok
->X_op
== O_constant
)
1814 tok
->X_add_number
&= 0xffff;
1819 case BFD_RELOC_HI16
:
1820 if (tok
->X_op
== O_constant
)
1821 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1830 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1831 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1833 if (reg
!= ERROR_REG_NUM
) /* Already errored */
1836 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
1837 as_bad (_("register number out of range"));
1840 tok
->X_op
= O_register
;
1841 tok
->X_add_symbol
= 0;
1842 tok
->X_add_number
= reg
;
1847 /* Split up the arguments for an opcode or pseudo-op. */
1850 tokenize_arguments (char **args
, char *str
)
1852 char *old_input_line_pointer
;
1853 bfd_boolean saw_comma
= FALSE
;
1854 bfd_boolean saw_arg
= FALSE
;
1855 bfd_boolean saw_colon
= FALSE
;
1857 char *arg_end
, *arg
;
1860 /* Save and restore input_line_pointer around this function. */
1861 old_input_line_pointer
= input_line_pointer
;
1862 input_line_pointer
= str
;
1864 while (*input_line_pointer
)
1867 switch (*input_line_pointer
)
1874 input_line_pointer
++;
1875 if (saw_comma
|| saw_colon
|| !saw_arg
)
1881 input_line_pointer
++;
1882 if (saw_comma
|| saw_colon
|| !saw_arg
)
1888 if (!saw_comma
&& !saw_colon
&& saw_arg
)
1891 arg_end
= input_line_pointer
+ 1;
1892 while (!expression_end (arg_end
))
1895 arg_len
= arg_end
- input_line_pointer
;
1896 arg
= (char *) xmalloc ((saw_colon
? 1 : 0) + arg_len
+ 1);
1897 args
[num_args
] = arg
;
1901 strncpy (arg
, input_line_pointer
, arg_len
);
1902 arg
[arg_len
] = '\0';
1904 input_line_pointer
= arg_end
;
1914 if (saw_comma
|| saw_colon
)
1916 input_line_pointer
= old_input_line_pointer
;
1921 as_bad (_("extra comma"));
1923 as_bad (_("extra colon"));
1925 as_bad (_("missing argument"));
1927 as_bad (_("missing comma or colon"));
1928 input_line_pointer
= old_input_line_pointer
;
1933 /* Parse the arguments to an opcode. Return TRUE on error. */
1936 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
1938 expressionS
*tok
, *last_tok
;
1939 xtensa_opcode opcode
= insn
->opcode
;
1940 bfd_boolean had_error
= TRUE
;
1941 xtensa_isa isa
= xtensa_default_isa
;
1942 int n
, num_regs
= 0;
1943 int opcode_operand_count
;
1944 int opnd_cnt
, last_opnd_cnt
;
1945 unsigned int next_reg
= 0;
1946 char *old_input_line_pointer
;
1948 if (insn
->insn_type
== ITYPE_LITERAL
)
1949 opcode_operand_count
= 1;
1951 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
1954 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
1956 /* Save and restore input_line_pointer around this function. */
1957 old_input_line_pointer
= input_line_pointer
;
1963 /* Skip invisible operands. */
1964 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
1970 for (n
= 0; n
< num_args
; n
++)
1972 input_line_pointer
= arg_strings
[n
];
1973 if (*input_line_pointer
== ':')
1975 xtensa_regfile opnd_rf
;
1976 input_line_pointer
++;
1979 assert (opnd_cnt
> 0);
1981 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
1983 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
1984 as_warn (_("incorrect register number, ignoring"));
1989 if (opnd_cnt
>= opcode_operand_count
)
1991 as_warn (_("too many arguments"));
1994 assert (opnd_cnt
< MAX_INSN_ARGS
);
1996 expression_maybe_register (opcode
, opnd_cnt
, tok
);
1997 next_reg
= tok
->X_add_number
+ 1;
1999 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
2001 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
2003 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
2004 /* minus 1 because we are seeing one right now */
2010 last_opnd_cnt
= opnd_cnt
;
2017 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
2021 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
2024 insn
->ntok
= tok
- insn
->tok
;
2028 input_line_pointer
= old_input_line_pointer
;
2034 get_invisible_operands (TInsn
*insn
)
2036 xtensa_isa isa
= xtensa_default_isa
;
2037 static xtensa_insnbuf slotbuf
= NULL
;
2039 xtensa_opcode opc
= insn
->opcode
;
2040 int slot
, opnd
, fmt_found
;
2044 slotbuf
= xtensa_insnbuf_alloc (isa
);
2046 /* Find format/slot where this can be encoded. */
2049 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2051 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2053 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2059 if (fmt_found
) break;
2064 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2068 /* First encode all the visible operands
2069 (to deal with shared field operands). */
2070 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2072 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2073 && (insn
->tok
[opnd
].X_op
== O_register
2074 || insn
->tok
[opnd
].X_op
== O_constant
))
2076 val
= insn
->tok
[opnd
].X_add_number
;
2077 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2078 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2082 /* Then pull out the values for the invisible ones. */
2083 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2085 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2087 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2088 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2089 insn
->tok
[opnd
].X_add_number
= val
;
2090 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2091 insn
->tok
[opnd
].X_op
= O_register
;
2093 insn
->tok
[opnd
].X_op
= O_constant
;
2102 xg_reverse_shift_count (char **cnt_argp
)
2104 char *cnt_arg
, *new_arg
;
2105 cnt_arg
= *cnt_argp
;
2107 /* replace the argument with "31-(argument)" */
2108 new_arg
= (char *) xmalloc (strlen (cnt_arg
) + 6);
2109 sprintf (new_arg
, "31-(%s)", cnt_arg
);
2112 *cnt_argp
= new_arg
;
2116 /* If "arg" is a constant expression, return non-zero with the value
2120 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2123 char *save_ptr
= input_line_pointer
;
2125 input_line_pointer
= arg
;
2127 input_line_pointer
= save_ptr
;
2129 if (exp
.X_op
== O_constant
)
2131 *valp
= exp
.X_add_number
;
2140 xg_replace_opname (char **popname
, char *newop
)
2143 *popname
= (char *) xmalloc (strlen (newop
) + 1);
2144 strcpy (*popname
, newop
);
2149 xg_check_num_args (int *pnum_args
,
2154 int num_args
= *pnum_args
;
2156 if (num_args
< expected_num
)
2158 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2159 num_args
, opname
, expected_num
);
2163 if (num_args
> expected_num
)
2165 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2166 num_args
, opname
, expected_num
);
2167 while (num_args
-- > expected_num
)
2169 free (arg_strings
[num_args
]);
2170 arg_strings
[num_args
] = 0;
2172 *pnum_args
= expected_num
;
2180 /* If the register is not specified as part of the opcode,
2181 then get it from the operand and move it to the opcode. */
2184 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2186 xtensa_isa isa
= xtensa_default_isa
;
2188 char *opname
, *new_opname
;
2189 const char *sr_name
;
2190 int is_user
, is_write
;
2191 bfd_boolean has_underbar
= FALSE
;
2196 has_underbar
= TRUE
;
2199 is_user
= (opname
[1] == 'u');
2200 is_write
= (opname
[0] == 'w');
2202 /* Opname == [rw]ur or [rwx]sr... */
2204 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2207 /* Check if the argument is a symbolic register name. */
2208 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2209 /* Handle WSR to "INTSET" as a special case. */
2210 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2211 && !strcasecmp (arg_strings
[1], "intset"))
2212 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2213 if (sr
== XTENSA_UNDEFINED
2214 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2216 /* Maybe it's a register number.... */
2218 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2220 as_bad (_("invalid register '%s' for '%s' instruction"),
2221 arg_strings
[1], opname
);
2224 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2225 if (sr
== XTENSA_UNDEFINED
)
2227 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2228 (long) val
, opname
);
2233 /* Remove the last argument, which is now part of the opcode. */
2234 free (arg_strings
[1]);
2238 /* Translate the opcode. */
2239 sr_name
= xtensa_sysreg_name (isa
, sr
);
2240 /* Another special case for "WSR.INTSET".... */
2241 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2243 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2244 sprintf (new_opname
, "%s%s.%s", (has_underbar
? "_" : ""),
2247 *popname
= new_opname
;
2254 xtensa_translate_old_userreg_ops (char **popname
)
2256 xtensa_isa isa
= xtensa_default_isa
;
2258 char *opname
, *new_opname
;
2259 const char *sr_name
;
2260 bfd_boolean has_underbar
= FALSE
;
2263 if (opname
[0] == '_')
2265 has_underbar
= TRUE
;
2269 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2270 if (sr
!= XTENSA_UNDEFINED
)
2272 /* The new default name ("nnn") is different from the old default
2273 name ("URnnn"). The old default is handled below, and we don't
2274 want to recognize [RW]nnn, so do nothing if the name is the (new)
2276 static char namebuf
[10];
2277 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2278 if (strcmp (namebuf
, opname
+ 1) == 0)
2286 /* Only continue if the reg name is "URnnn". */
2287 if (opname
[1] != 'u' || opname
[2] != 'r')
2289 val
= strtoul (opname
+ 3, &end
, 10);
2293 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2294 if (sr
== XTENSA_UNDEFINED
)
2296 as_bad (_("invalid register number (%ld) for '%s'"),
2297 (long) val
, opname
);
2302 /* Translate the opcode. */
2303 sr_name
= xtensa_sysreg_name (isa
, sr
);
2304 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2305 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2306 opname
[0], sr_name
);
2308 *popname
= new_opname
;
2315 xtensa_translate_zero_immed (char *old_op
,
2325 assert (opname
[0] != '_');
2327 if (strcmp (opname
, old_op
) != 0)
2330 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2332 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2334 xg_replace_opname (popname
, new_op
);
2335 free (arg_strings
[1]);
2336 arg_strings
[1] = arg_strings
[2];
2345 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2346 Returns non-zero if an error was found. */
2349 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2351 char *opname
= *popname
;
2352 bfd_boolean has_underbar
= FALSE
;
2354 if (cur_vinsn
.inside_bundle
)
2359 has_underbar
= TRUE
;
2363 if (strcmp (opname
, "mov") == 0)
2365 if (use_transform () && !has_underbar
&& density_supported
)
2366 xg_replace_opname (popname
, "mov.n");
2369 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2371 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2372 arg_strings
[2] = (char *) xmalloc (strlen (arg_strings
[1]) + 1);
2373 strcpy (arg_strings
[2], arg_strings
[1]);
2379 if (strcmp (opname
, "bbsi.l") == 0)
2381 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2383 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2384 if (target_big_endian
)
2385 xg_reverse_shift_count (&arg_strings
[1]);
2389 if (strcmp (opname
, "bbci.l") == 0)
2391 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2393 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2394 if (target_big_endian
)
2395 xg_reverse_shift_count (&arg_strings
[1]);
2399 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
2400 && strcmp (opname
, "nop") == 0)
2402 if (use_transform () && !has_underbar
&& density_supported
)
2403 xg_replace_opname (popname
, "nop.n");
2406 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2408 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2409 arg_strings
[0] = (char *) xmalloc (3);
2410 arg_strings
[1] = (char *) xmalloc (3);
2411 arg_strings
[2] = (char *) xmalloc (3);
2412 strcpy (arg_strings
[0], "a1");
2413 strcpy (arg_strings
[1], "a1");
2414 strcpy (arg_strings
[2], "a1");
2420 /* Recognize [RW]UR and [RWX]SR. */
2421 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2422 && (opname
[1] == 'u' || opname
[1] == 's'))
2423 || (opname
[0] == 'x' && opname
[1] == 's'))
2425 && opname
[3] == '\0')
2426 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2428 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2429 [RW]<name> if <name> is the non-default name of a user register. */
2430 if ((opname
[0] == 'r' || opname
[0] == 'w')
2431 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2432 return xtensa_translate_old_userreg_ops (popname
);
2434 /* Relax branches that don't allow comparisons against an immediate value
2435 of zero to the corresponding branches with implicit zero immediates. */
2436 if (!has_underbar
&& use_transform ())
2438 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2439 pnum_args
, arg_strings
))
2442 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2443 pnum_args
, arg_strings
))
2446 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2447 pnum_args
, arg_strings
))
2450 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2451 pnum_args
, arg_strings
))
2459 /* Functions for dealing with the Xtensa ISA. */
2461 /* Currently the assembler only allows us to use a single target per
2462 fragment. Because of this, only one operand for a given
2463 instruction may be symbolic. If there is a PC-relative operand,
2464 the last one is chosen. Otherwise, the result is the number of the
2465 last immediate operand, and if there are none of those, we fail and
2469 get_relaxable_immed (xtensa_opcode opcode
)
2471 int last_immed
= -1;
2474 if (opcode
== XTENSA_UNDEFINED
)
2477 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2478 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2480 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2482 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2484 if (last_immed
== -1
2485 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2492 static xtensa_opcode
2493 get_opcode_from_buf (const char *buf
, int slot
)
2495 static xtensa_insnbuf insnbuf
= NULL
;
2496 static xtensa_insnbuf slotbuf
= NULL
;
2497 xtensa_isa isa
= xtensa_default_isa
;
2502 insnbuf
= xtensa_insnbuf_alloc (isa
);
2503 slotbuf
= xtensa_insnbuf_alloc (isa
);
2506 xtensa_insnbuf_from_chars (isa
, insnbuf
, (const unsigned char *) buf
, 0);
2507 fmt
= xtensa_format_decode (isa
, insnbuf
);
2508 if (fmt
== XTENSA_UNDEFINED
)
2509 return XTENSA_UNDEFINED
;
2511 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2512 return XTENSA_UNDEFINED
;
2514 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2515 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2519 #ifdef TENSILICA_DEBUG
2521 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2524 xtensa_print_insn_table (void)
2526 int num_opcodes
, num_operands
;
2527 xtensa_opcode opcode
;
2528 xtensa_isa isa
= xtensa_default_isa
;
2530 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2531 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2534 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2535 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2536 for (opn
= 0; opn
< num_operands
; opn
++)
2538 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2540 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2542 xtensa_regfile opnd_rf
=
2543 xtensa_operand_regfile (isa
, opcode
, opn
);
2544 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2546 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2547 fputs ("[lLr] ", stderr
);
2549 fputs ("i ", stderr
);
2551 fprintf (stderr
, "\n");
2557 print_vliw_insn (xtensa_insnbuf vbuf
)
2559 xtensa_isa isa
= xtensa_default_isa
;
2560 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2561 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2564 fprintf (stderr
, "format = %d\n", f
);
2566 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2568 xtensa_opcode opcode
;
2572 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2573 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2574 opname
= xtensa_opcode_name (isa
, opcode
);
2576 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2577 fprintf (stderr
, " operands = ");
2579 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2583 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2585 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2586 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2587 fprintf (stderr
, "%d ", val
);
2589 fprintf (stderr
, "\n");
2591 xtensa_insnbuf_free (isa
, sbuf
);
2594 #endif /* TENSILICA_DEBUG */
2598 is_direct_call_opcode (xtensa_opcode opcode
)
2600 xtensa_isa isa
= xtensa_default_isa
;
2601 int n
, num_operands
;
2603 if (xtensa_opcode_is_call (isa
, opcode
) == 0)
2606 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2607 for (n
= 0; n
< num_operands
; n
++)
2609 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2610 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2617 /* Convert from BFD relocation type code to slot and operand number.
2618 Returns non-zero on failure. */
2621 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2623 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2624 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2626 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2629 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2630 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2632 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2642 /* Convert from slot number to BFD relocation type code for the
2643 standard PC-relative relocations. Return BFD_RELOC_NONE on
2646 static bfd_reloc_code_real_type
2647 encode_reloc (int slot
)
2649 if (slot
< 0 || slot
> 14)
2650 return BFD_RELOC_NONE
;
2652 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2656 /* Convert from slot numbers to BFD relocation type code for the
2657 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2659 static bfd_reloc_code_real_type
2660 encode_alt_reloc (int slot
)
2662 if (slot
< 0 || slot
> 14)
2663 return BFD_RELOC_NONE
;
2665 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2670 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2673 xtensa_opcode opcode
,
2679 uint32 valbuf
= value
;
2681 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2683 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2685 as_bad_where ((char *) file
, line
,
2686 _("operand %d of '%s' has out of range value '%u'"),
2688 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2691 as_bad_where ((char *) file
, line
,
2692 _("operand %d of '%s' has invalid value '%u'"),
2694 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2699 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2705 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2708 xtensa_opcode opcode
,
2712 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2713 fmt
, slot
, slotbuf
, &val
);
2714 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2719 /* Checks for rules from xtensa-relax tables. */
2721 /* The routine xg_instruction_matches_option_term must return TRUE
2722 when a given option term is true. The meaning of all of the option
2723 terms is given interpretation by this function. This is needed when
2724 an option depends on the state of a directive, but there are no such
2725 options in use right now. */
2728 xg_instruction_matches_option_term (TInsn
*insn ATTRIBUTE_UNUSED
,
2729 const ReqOrOption
*option
)
2731 if (strcmp (option
->option_name
, "realnop") == 0
2732 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2734 /* These conditions were evaluated statically when building the
2735 relaxation table. There's no need to reevaluate them now. */
2740 as_fatal (_("internal error: unknown option name '%s'"),
2741 option
->option_name
);
2747 xg_instruction_matches_or_options (TInsn
*insn
,
2748 const ReqOrOptionList
*or_option
)
2750 const ReqOrOption
*option
;
2751 /* Must match each of the AND terms. */
2752 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2754 if (xg_instruction_matches_option_term (insn
, option
))
2762 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2764 const ReqOption
*req_options
;
2765 /* Must match each of the AND terms. */
2766 for (req_options
= options
;
2767 req_options
!= NULL
;
2768 req_options
= req_options
->next
)
2770 /* Must match one of the OR clauses. */
2771 if (!xg_instruction_matches_or_options (insn
,
2772 req_options
->or_option_terms
))
2779 /* Return the transition rule that matches or NULL if none matches. */
2782 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2784 PreconditionList
*condition_l
;
2786 if (rule
->opcode
!= insn
->opcode
)
2789 for (condition_l
= rule
->conditions
;
2790 condition_l
!= NULL
;
2791 condition_l
= condition_l
->next
)
2795 Precondition
*cond
= condition_l
->precond
;
2800 /* The expression must be the constant. */
2801 assert (cond
->op_num
< insn
->ntok
);
2802 exp1
= &insn
->tok
[cond
->op_num
];
2803 if (expr_is_const (exp1
))
2808 if (get_expr_const (exp1
) != cond
->op_data
)
2812 if (get_expr_const (exp1
) == cond
->op_data
)
2819 else if (expr_is_register (exp1
))
2824 if (get_expr_register (exp1
) != cond
->op_data
)
2828 if (get_expr_register (exp1
) == cond
->op_data
)
2840 assert (cond
->op_num
< insn
->ntok
);
2841 assert (cond
->op_data
< insn
->ntok
);
2842 exp1
= &insn
->tok
[cond
->op_num
];
2843 exp2
= &insn
->tok
[cond
->op_data
];
2848 if (!expr_is_equal (exp1
, exp2
))
2852 if (expr_is_equal (exp1
, exp2
))
2864 if (!xg_instruction_matches_options (insn
, rule
->options
))
2872 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
2874 bfd_boolean a_greater
= FALSE
;
2875 bfd_boolean b_greater
= FALSE
;
2877 ReqOptionList
*l_a
= a
->options
;
2878 ReqOptionList
*l_b
= b
->options
;
2880 /* We only care if they both are the same except for
2881 a const16 vs. an l32r. */
2883 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2885 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
2886 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
2887 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2889 if (l_or_a
->is_true
!= l_or_b
->is_true
)
2891 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
2893 /* This is the case we care about. */
2894 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
2895 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
2902 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
2903 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
2913 l_or_a
= l_or_a
->next
;
2914 l_or_b
= l_or_b
->next
;
2916 if (l_or_a
|| l_or_b
)
2925 /* Incomparable if the substitution was used differently in two cases. */
2926 if (a_greater
&& b_greater
)
2938 static TransitionRule
*
2939 xg_instruction_match (TInsn
*insn
)
2941 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
2943 assert (insn
->opcode
< table
->num_opcodes
);
2945 /* Walk through all of the possible transitions. */
2946 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2948 TransitionRule
*rule
= l
->rule
;
2949 if (xg_instruction_matches_rule (insn
, rule
))
2956 /* Various Other Internal Functions. */
2959 is_unique_insn_expansion (TransitionRule
*r
)
2961 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
2963 if (r
->to_instr
->typ
!= INSTR_INSTR
)
2969 /* Check if there is exactly one relaxation for INSN that converts it to
2970 another instruction of equal or larger size. If so, and if TARG is
2971 non-null, go ahead and generate the relaxed instruction into TARG. If
2972 NARROW_ONLY is true, then only consider relaxations that widen a narrow
2973 instruction, i.e., ignore relaxations that convert to an instruction of
2974 equal size. In some contexts where this function is used, only
2975 a single widening is allowed and the NARROW_ONLY argument is used to
2976 exclude cases like ADDI being "widened" to an ADDMI, which may
2977 later be relaxed to an ADDMI/ADDI pair. */
2980 xg_is_single_relaxable_insn (TInsn
*insn
, TInsn
*targ
, bfd_boolean narrow_only
)
2982 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
2984 TransitionRule
*match
= 0;
2986 assert (insn
->insn_type
== ITYPE_INSN
);
2987 assert (insn
->opcode
< table
->num_opcodes
);
2989 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2991 TransitionRule
*rule
= l
->rule
;
2993 if (xg_instruction_matches_rule (insn
, rule
)
2994 && is_unique_insn_expansion (rule
)
2995 && (xg_get_single_size (insn
->opcode
) + (narrow_only
? 1 : 0)
2996 <= xg_get_single_size (rule
->to_instr
->opcode
)))
3007 xg_build_to_insn (targ
, insn
, match
->to_instr
);
3012 /* Return the maximum number of bytes this opcode can expand to. */
3015 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
3017 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3019 int max_size
= xg_get_single_size (opcode
);
3021 assert (opcode
< table
->num_opcodes
);
3023 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3025 TransitionRule
*rule
= l
->rule
;
3026 BuildInstr
*build_list
;
3031 build_list
= rule
->to_instr
;
3032 if (is_unique_insn_expansion (rule
))
3034 assert (build_list
->typ
== INSTR_INSTR
);
3035 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
3038 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3040 switch (build_list
->typ
)
3043 this_size
+= xg_get_single_size (build_list
->opcode
);
3045 case INSTR_LITERAL_DEF
:
3046 case INSTR_LABEL_DEF
:
3051 if (this_size
> max_size
)
3052 max_size
= this_size
;
3058 /* Return the maximum number of literal bytes this opcode can generate. */
3061 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3063 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3067 assert (opcode
< table
->num_opcodes
);
3069 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3071 TransitionRule
*rule
= l
->rule
;
3072 BuildInstr
*build_list
;
3077 build_list
= rule
->to_instr
;
3078 if (is_unique_insn_expansion (rule
))
3080 assert (build_list
->typ
== INSTR_INSTR
);
3081 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3084 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3086 switch (build_list
->typ
)
3088 case INSTR_LITERAL_DEF
:
3089 /* Hard-coded 4-byte literal. */
3093 case INSTR_LABEL_DEF
:
3098 if (this_size
> max_size
)
3099 max_size
= this_size
;
3106 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3108 int steps_taken
= 0;
3109 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3112 assert (insn
->insn_type
== ITYPE_INSN
);
3113 assert (insn
->opcode
< table
->num_opcodes
);
3115 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3117 TransitionRule
*rule
= l
->rule
;
3119 if (xg_instruction_matches_rule (insn
, rule
))
3121 if (steps_taken
== lateral_steps
)
3131 get_special_literal_symbol (void)
3133 static symbolS
*sym
= NULL
;
3136 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3142 get_special_label_symbol (void)
3144 static symbolS
*sym
= NULL
;
3147 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3153 xg_valid_literal_expression (const expressionS
*exp
)
3170 /* This will check to see if the value can be converted into the
3171 operand type. It will return TRUE if it does not fit. */
3174 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3176 uint32 valbuf
= value
;
3177 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3183 /* Assumes: All immeds are constants. Check that all constants fit
3184 into their immeds; return FALSE if not. */
3187 xg_immeds_fit (const TInsn
*insn
)
3189 xtensa_isa isa
= xtensa_default_isa
;
3193 assert (insn
->insn_type
== ITYPE_INSN
);
3194 for (i
= 0; i
< n
; ++i
)
3196 const expressionS
*expr
= &insn
->tok
[i
];
3197 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3204 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3209 /* The symbol should have a fixup associated with it. */
3218 /* This should only be called after we have an initial
3219 estimate of the addresses. */
3222 xg_symbolic_immeds_fit (const TInsn
*insn
,
3228 xtensa_isa isa
= xtensa_default_isa
;
3236 assert (insn
->insn_type
== ITYPE_INSN
);
3238 for (i
= 0; i
< n
; ++i
)
3240 const expressionS
*expr
= &insn
->tok
[i
];
3241 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3248 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3254 /* Check for the worst case. */
3255 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3260 /* We only allow symbols for PC-relative references.
3261 If pc_frag == 0, then we don't have frag locations yet. */
3263 || xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0)
3266 /* If it is a weak symbol, then assume it won't reach. */
3267 if (S_IS_WEAK (expr
->X_add_symbol
))
3270 if (is_direct_call_opcode (insn
->opcode
)
3271 && ! pc_frag
->tc_frag_data
.use_longcalls
)
3273 /* If callee is undefined or in a different segment, be
3274 optimistic and assume it will be in range. */
3275 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3279 /* Only references within a segment can be known to fit in the
3280 operands at assembly time. */
3281 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3284 symbolP
= expr
->X_add_symbol
;
3285 sym_frag
= symbol_get_frag (symbolP
);
3286 target
= S_GET_VALUE (symbolP
) + expr
->X_add_number
;
3287 pc
= pc_frag
->fr_address
+ pc_offset
;
3289 /* If frag has yet to be reached on this pass, assume it
3290 will move by STRETCH just as we did. If this is not so,
3291 it will be because some frag between grows, and that will
3292 force another pass. Beware zero-length frags. There
3293 should be a faster way to do this. */
3296 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3297 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3302 new_offset
= target
;
3303 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3304 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3309 /* The symbol should have a fixup associated with it. */
3318 /* Return TRUE on success. */
3321 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3326 memset (targ
, 0, sizeof (TInsn
));
3327 targ
->linenum
= insn
->linenum
;
3332 targ
->opcode
= bi
->opcode
;
3333 targ
->insn_type
= ITYPE_INSN
;
3334 targ
->is_specific_opcode
= FALSE
;
3336 for (; op
!= NULL
; op
= op
->next
)
3338 int op_num
= op
->op_num
;
3339 int op_data
= op
->op_data
;
3341 assert (op
->op_num
< MAX_INSN_ARGS
);
3343 if (targ
->ntok
<= op_num
)
3344 targ
->ntok
= op_num
+ 1;
3349 set_expr_const (&targ
->tok
[op_num
], op_data
);
3352 assert (op_data
< insn
->ntok
);
3353 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3356 sym
= get_special_literal_symbol ();
3357 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3360 sym
= get_special_label_symbol ();
3361 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3363 case OP_OPERAND_HI16U
:
3364 case OP_OPERAND_LOW16U
:
3365 assert (op_data
< insn
->ntok
);
3366 if (expr_is_const (&insn
->tok
[op_data
]))
3369 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3370 val
= xg_apply_userdef_op_fn (op
->typ
,
3373 targ
->tok
[op_num
].X_add_number
= val
;
3377 /* For const16 we can create relocations for these. */
3378 if (targ
->opcode
== XTENSA_UNDEFINED
3379 || (targ
->opcode
!= xtensa_const16_opcode
))
3381 assert (op_data
< insn
->ntok
);
3382 /* Need to build a O_lo16 or O_hi16. */
3383 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3384 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3386 if (op
->typ
== OP_OPERAND_HI16U
)
3387 targ
->tok
[op_num
].X_op
= O_hi16
;
3388 else if (op
->typ
== OP_OPERAND_LOW16U
)
3389 targ
->tok
[op_num
].X_op
= O_lo16
;
3396 /* currently handles:
3399 OP_OPERAND_F32MINUS */
3400 if (xg_has_userdef_op_fn (op
->typ
))
3402 assert (op_data
< insn
->ntok
);
3403 if (expr_is_const (&insn
->tok
[op_data
]))
3406 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3407 val
= xg_apply_userdef_op_fn (op
->typ
,
3410 targ
->tok
[op_num
].X_add_number
= val
;
3413 return FALSE
; /* We cannot use a relocation for this. */
3422 case INSTR_LITERAL_DEF
:
3424 targ
->opcode
= XTENSA_UNDEFINED
;
3425 targ
->insn_type
= ITYPE_LITERAL
;
3426 targ
->is_specific_opcode
= FALSE
;
3427 for (; op
!= NULL
; op
= op
->next
)
3429 int op_num
= op
->op_num
;
3430 int op_data
= op
->op_data
;
3431 assert (op
->op_num
< MAX_INSN_ARGS
);
3433 if (targ
->ntok
<= op_num
)
3434 targ
->ntok
= op_num
+ 1;
3439 assert (op_data
< insn
->ntok
);
3440 /* We can only pass resolvable literals through. */
3441 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3443 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3455 case INSTR_LABEL_DEF
:
3457 targ
->opcode
= XTENSA_UNDEFINED
;
3458 targ
->insn_type
= ITYPE_LABEL
;
3459 targ
->is_specific_opcode
= FALSE
;
3460 /* Literal with no ops is a label? */
3461 assert (op
== NULL
);
3472 /* Return TRUE on success. */
3475 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3477 for (; bi
!= NULL
; bi
= bi
->next
)
3479 TInsn
*next_insn
= istack_push_space (istack
);
3481 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3488 /* Return TRUE on valid expansion. */
3491 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3493 int stack_size
= istack
->ninsn
;
3494 int steps_taken
= 0;
3495 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3498 assert (insn
->insn_type
== ITYPE_INSN
);
3499 assert (insn
->opcode
< table
->num_opcodes
);
3501 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3503 TransitionRule
*rule
= l
->rule
;
3505 if (xg_instruction_matches_rule (insn
, rule
))
3507 if (lateral_steps
== steps_taken
)
3511 /* This is it. Expand the rule to the stack. */
3512 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3515 /* Check to see if it fits. */
3516 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3518 TInsn
*insn
= &istack
->insn
[i
];
3520 if (insn
->insn_type
== ITYPE_INSN
3521 && !tinsn_has_symbolic_operands (insn
)
3522 && !xg_immeds_fit (insn
))
3524 istack
->ninsn
= stack_size
;
3537 /* Relax the assembly instruction at least "min_steps".
3538 Return the number of steps taken. */
3541 xg_assembly_relax (IStack
*istack
,
3544 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3545 offsetT pc_offset
, /* offset in fragment */
3546 int min_steps
, /* minimum conversion steps */
3547 long stretch
) /* number of bytes stretched so far */
3549 int steps_taken
= 0;
3551 /* assert (has no symbolic operands)
3552 Some of its immeds don't fit.
3553 Try to build a relaxed version.
3554 This may go through a couple of stages
3555 of single instruction transformations before
3558 TInsn single_target
;
3560 int lateral_steps
= 0;
3561 int istack_size
= istack
->ninsn
;
3563 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3564 && steps_taken
>= min_steps
)
3566 istack_push (istack
, insn
);
3569 current_insn
= *insn
;
3571 /* Walk through all of the single instruction expansions. */
3572 while (xg_is_single_relaxable_insn (¤t_insn
, &single_target
, FALSE
))
3574 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3578 if (steps_taken
>= min_steps
)
3580 istack_push (istack
, &single_target
);
3584 current_insn
= single_target
;
3587 /* Now check for a multi-instruction expansion. */
3588 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3590 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3593 if (steps_taken
>= min_steps
)
3595 istack_push (istack
, ¤t_insn
);
3600 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3602 if (steps_taken
>= min_steps
)
3606 istack
->ninsn
= istack_size
;
3609 /* It's not going to work -- use the original. */
3610 istack_push (istack
, insn
);
3616 xg_force_frag_space (int size
)
3618 /* This may have the side effect of creating a new fragment for the
3619 space to go into. I just do not like the name of the "frag"
3626 xg_finish_frag (char *last_insn
,
3627 enum xtensa_relax_statesE frag_state
,
3628 enum xtensa_relax_statesE slot0_state
,
3630 bfd_boolean is_insn
)
3632 /* Finish off this fragment so that it has at LEAST the desired
3633 max_growth. If it doesn't fit in this fragment, close this one
3634 and start a new one. In either case, return a pointer to the
3635 beginning of the growth area. */
3639 xg_force_frag_space (max_growth
);
3641 old_frag
= frag_now
;
3643 frag_now
->fr_opcode
= last_insn
;
3645 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3647 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3648 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3650 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3651 xtensa_set_frag_assembly_state (frag_now
);
3653 /* Just to make sure that we did not split it up. */
3654 assert (old_frag
->fr_next
== frag_now
);
3658 /* Return TRUE if the target frag is one of the next non-empty frags. */
3661 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3666 for (; fragP
; fragP
= fragP
->fr_next
)
3668 if (fragP
== target
)
3670 if (fragP
->fr_fix
!= 0)
3672 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3674 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3675 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3677 if (fragP
->fr_type
== rs_space
)
3685 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3687 xtensa_isa isa
= xtensa_default_isa
;
3689 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3694 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 0
3695 && xtensa_opcode_is_jump (isa
, insn
->opcode
) == 0)
3698 for (i
= 0; i
< num_ops
; i
++)
3700 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3706 if (target_op
== -1)
3709 if (insn
->ntok
<= target_op
)
3712 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3715 sym
= insn
->tok
[target_op
].X_add_symbol
;
3719 if (insn
->tok
[target_op
].X_add_number
!= 0)
3722 target_frag
= symbol_get_frag (sym
);
3723 if (target_frag
== NULL
)
3726 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3727 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3735 xg_add_branch_and_loop_targets (TInsn
*insn
)
3737 xtensa_isa isa
= xtensa_default_isa
;
3738 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3740 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3743 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3744 && insn
->tok
[i
].X_op
== O_symbol
)
3745 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3749 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3750 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3754 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3756 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3757 && insn
->tok
[i
].X_op
== O_symbol
)
3759 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3760 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3761 if (S_IS_DEFINED (sym
))
3762 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3769 /* Return FALSE if no error. */
3772 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3777 switch (instr_spec
->typ
)
3780 new_insn
->insn_type
= ITYPE_INSN
;
3781 new_insn
->opcode
= instr_spec
->opcode
;
3782 new_insn
->is_specific_opcode
= FALSE
;
3783 new_insn
->linenum
= old_insn
->linenum
;
3785 case INSTR_LITERAL_DEF
:
3786 new_insn
->insn_type
= ITYPE_LITERAL
;
3787 new_insn
->opcode
= XTENSA_UNDEFINED
;
3788 new_insn
->is_specific_opcode
= FALSE
;
3789 new_insn
->linenum
= old_insn
->linenum
;
3791 case INSTR_LABEL_DEF
:
3792 as_bad (_("INSTR_LABEL_DEF not supported yet"));
3796 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3799 const expressionS
*src_exp
;
3805 /* The expression must be the constant. */
3806 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3807 exp
= &new_insn
->tok
[b_op
->op_num
];
3808 set_expr_const (exp
, b_op
->op_data
);
3812 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3813 assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
3814 src_exp
= &old_insn
->tok
[b_op
->op_data
];
3815 exp
= &new_insn
->tok
[b_op
->op_num
];
3816 copy_expr (exp
, src_exp
);
3821 as_bad (_("can't handle generation of literal/labels yet"));
3825 as_bad (_("can't handle undefined OP TYPE"));
3830 new_insn
->ntok
= num_ops
;
3835 /* Return TRUE if it was simplified. */
3838 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
3840 TransitionRule
*rule
;
3841 BuildInstr
*insn_spec
;
3843 if (old_insn
->is_specific_opcode
|| !density_supported
)
3846 rule
= xg_instruction_match (old_insn
);
3850 insn_spec
= rule
->to_instr
;
3851 /* There should only be one. */
3852 assert (insn_spec
!= NULL
);
3853 assert (insn_spec
->next
== NULL
);
3854 if (insn_spec
->next
!= NULL
)
3857 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
3863 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3864 l32i.n. (2) Check the number of operands. (3) Place the instruction
3865 tokens into the stack or relax it and place multiple
3866 instructions/literals onto the stack. Return FALSE if no error. */
3869 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
3873 bfd_boolean do_expand
;
3875 memset (&new_insn
, 0, sizeof (TInsn
));
3877 /* Narrow it if we can. xg_simplify_insn now does all the
3878 appropriate checking (e.g., for the density option). */
3879 if (xg_simplify_insn (orig_insn
, &new_insn
))
3880 orig_insn
= &new_insn
;
3882 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
3884 if (orig_insn
->ntok
< noperands
)
3886 as_bad (_("found %d operands for '%s': Expected %d"),
3888 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3892 if (orig_insn
->ntok
> noperands
)
3893 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
3895 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3898 /* If there are not enough operands, we will assert above. If there
3899 are too many, just cut out the extras here. */
3900 orig_insn
->ntok
= noperands
;
3902 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
3905 /* If the instruction will definitely need to be relaxed, it is better
3906 to expand it now for better scheduling. Decide whether to expand
3908 do_expand
= (!orig_insn
->is_specific_opcode
&& use_transform ());
3910 /* Calls should be expanded to longcalls only in the backend relaxation
3911 so that the assembly scheduler will keep the L32R/CALLX instructions
3913 if (is_direct_call_opcode (orig_insn
->opcode
))
3916 if (tinsn_has_symbolic_operands (orig_insn
))
3918 /* The values of symbolic operands are not known yet, so only expand
3919 now if an operand is "complex" (e.g., difference of symbols) and
3920 will have to be stored as a literal regardless of the value. */
3921 if (!tinsn_has_complex_operands (orig_insn
))
3924 else if (xg_immeds_fit (orig_insn
))
3928 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
3930 istack_push (istack
, orig_insn
);
3936 /* Return TRUE if the section flags are marked linkonce
3937 or the name is .gnu.linkonce*. */
3940 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
3942 flagword flags
, link_once_flags
;
3944 flags
= bfd_get_section_flags (abfd
, sec
);
3945 link_once_flags
= (flags
& SEC_LINK_ONCE
);
3947 /* Flags might not be set yet. */
3948 if (!link_once_flags
)
3950 static size_t len
= sizeof ".gnu.linkonce.t.";
3952 if (strncmp (segment_name (sec
), ".gnu.linkonce.t.", len
- 1) == 0)
3953 link_once_flags
= SEC_LINK_ONCE
;
3955 return (link_once_flags
!= 0);
3960 xtensa_add_literal_sym (symbolS
*sym
)
3964 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
3966 l
->next
= literal_syms
;
3972 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
3974 static int lit_num
= 0;
3975 static char name
[256];
3978 sprintf (name
, ".L_lit_sym%d", lit_num
);
3980 /* Create a local symbol. If it is in a linkonce section, we have to
3981 be careful to make sure that if it is used in a relocation that the
3982 symbol will be in the output file. */
3983 if (get_is_linkonce_section (stdoutput
, sec
))
3985 symbolP
= symbol_new (name
, sec
, 0, frag
);
3986 S_CLEAR_EXTERNAL (symbolP
);
3987 /* symbolP->local = 1; */
3990 symbolP
= symbol_new (name
, sec
, 0, frag
);
3992 xtensa_add_literal_sym (symbolP
);
3994 frag
->tc_frag_data
.is_literal
= TRUE
;
4000 /* Currently all literals that are generated here are 32-bit L32R targets. */
4003 xg_assemble_literal (/* const */ TInsn
*insn
)
4006 symbolS
*lit_sym
= NULL
;
4008 /* size = 4 for L32R. It could easily be larger when we move to
4009 larger constants. Add a parameter later. */
4010 offsetT litsize
= 4;
4011 offsetT litalign
= 2; /* 2^2 = 4 */
4012 expressionS saved_loc
;
4013 expressionS
* emit_val
;
4015 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
4017 assert (insn
->insn_type
== ITYPE_LITERAL
);
4018 assert (insn
->ntok
== 1); /* must be only one token here */
4020 xtensa_switch_to_literal_fragment (&state
);
4022 emit_val
= &insn
->tok
[0];
4023 if (emit_val
->X_op
== O_big
)
4025 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
4028 /* This happens when someone writes a "movi a2, big_number". */
4029 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4030 _("invalid immediate"));
4031 xtensa_restore_emit_state (&state
);
4036 /* Force a 4-byte align here. Note that this opens a new frag, so all
4037 literals done with this function have a frag to themselves. That's
4038 important for the way text section literals work. */
4039 frag_align (litalign
, 0, 0);
4040 record_alignment (now_seg
, litalign
);
4042 if (emit_val
->X_op
== O_pltrel
)
4044 char *p
= frag_more (litsize
);
4045 xtensa_set_frag_assembly_state (frag_now
);
4046 if (emit_val
->X_add_symbol
)
4047 emit_val
->X_op
= O_symbol
;
4049 emit_val
->X_op
= O_constant
;
4050 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
4051 litsize
, emit_val
, 0, BFD_RELOC_XTENSA_PLT
);
4054 emit_expr (emit_val
, litsize
);
4056 assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
4057 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4058 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4059 lit_sym
= frag_now
->fr_symbol
;
4060 frag_now
->tc_frag_data
.is_literal
= TRUE
;
4063 xtensa_restore_emit_state (&state
);
4069 xg_assemble_literal_space (/* const */ int size
, int slot
)
4072 /* We might have to do something about this alignment. It only
4073 takes effect if something is placed here. */
4074 offsetT litalign
= 2; /* 2^2 = 4 */
4075 fragS
*lit_saved_frag
;
4077 assert (size
% 4 == 0);
4079 xtensa_switch_to_literal_fragment (&state
);
4081 /* Force a 4-byte align here. */
4082 frag_align (litalign
, 0, 0);
4083 record_alignment (now_seg
, litalign
);
4085 xg_force_frag_space (size
);
4087 lit_saved_frag
= frag_now
;
4088 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4089 frag_now
->tc_frag_data
.is_literal
= TRUE
;
4090 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4091 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4094 xtensa_restore_emit_state (&state
);
4095 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4099 /* Put in a fixup record based on the opcode.
4100 Return TRUE on success. */
4103 xg_add_opcode_fix (TInsn
*tinsn
,
4111 xtensa_opcode opcode
= tinsn
->opcode
;
4112 bfd_reloc_code_real_type reloc
;
4113 reloc_howto_type
*howto
;
4117 reloc
= BFD_RELOC_NONE
;
4119 /* First try the special cases for "alternate" relocs. */
4120 if (opcode
== xtensa_l32r_opcode
)
4122 if (fragP
->tc_frag_data
.use_absolute_literals
)
4123 reloc
= encode_alt_reloc (slot
);
4125 else if (opcode
== xtensa_const16_opcode
)
4127 if (expr
->X_op
== O_lo16
)
4129 reloc
= encode_reloc (slot
);
4130 expr
->X_op
= O_symbol
;
4132 else if (expr
->X_op
== O_hi16
)
4134 reloc
= encode_alt_reloc (slot
);
4135 expr
->X_op
= O_symbol
;
4139 if (opnum
!= get_relaxable_immed (opcode
))
4141 as_bad (_("invalid relocation for operand %i of '%s'"),
4142 opnum
, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4146 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4147 into the symbol table where the generic portions of the assembler
4148 won't know what to do with them. */
4149 if (expr
->X_op
== O_lo16
|| expr
->X_op
== O_hi16
)
4151 as_bad (_("invalid expression for operand %i of '%s'"),
4152 opnum
, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4156 /* Next try the generic relocs. */
4157 if (reloc
== BFD_RELOC_NONE
)
4158 reloc
= encode_reloc (slot
);
4159 if (reloc
== BFD_RELOC_NONE
)
4161 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4165 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4168 as_bad (_("undefined symbol for opcode \"%s\""),
4169 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4173 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4174 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, expr
,
4175 howto
->pc_relative
, reloc
);
4176 the_fix
->fx_no_overflow
= 1;
4178 if (expr
->X_add_symbol
4179 && (S_IS_EXTERNAL (expr
->X_add_symbol
)
4180 || S_IS_WEAK (expr
->X_add_symbol
)))
4181 the_fix
->fx_plt
= TRUE
;
4183 the_fix
->tc_fix_data
.X_add_symbol
= expr
->X_add_symbol
;
4184 the_fix
->tc_fix_data
.X_add_number
= expr
->X_add_number
;
4185 the_fix
->tc_fix_data
.slot
= slot
;
4192 xg_emit_insn_to_buf (TInsn
*tinsn
,
4197 bfd_boolean build_fix
)
4199 static xtensa_insnbuf insnbuf
= NULL
;
4200 bfd_boolean has_symbolic_immed
= FALSE
;
4201 bfd_boolean ok
= TRUE
;
4203 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4205 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4206 if (has_symbolic_immed
&& build_fix
)
4209 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4210 expressionS
*exp
= &tinsn
->tok
[opnum
];
4212 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, 0, exp
, fragP
, offset
))
4215 fragP
->tc_frag_data
.is_insn
= TRUE
;
4216 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4217 (unsigned char *) buf
, 0);
4223 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4225 symbolS
*sym
= get_special_literal_symbol ();
4229 assert (insn
->insn_type
== ITYPE_INSN
);
4230 for (i
= 0; i
< insn
->ntok
; i
++)
4231 if (insn
->tok
[i
].X_add_symbol
== sym
)
4232 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4238 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4240 symbolS
*sym
= get_special_label_symbol ();
4242 /* assert (!insn->is_literal); */
4243 for (i
= 0; i
< insn
->ntok
; i
++)
4244 if (insn
->tok
[i
].X_add_symbol
== sym
)
4245 insn
->tok
[i
].X_add_symbol
= label_sym
;
4250 /* Return TRUE if the instruction can write to the specified
4251 integer register. */
4254 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4258 xtensa_isa isa
= xtensa_default_isa
;
4260 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4262 for (i
= 0; i
< num_ops
; i
++)
4265 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4266 if ((inout
== 'o' || inout
== 'm')
4267 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4269 xtensa_regfile opnd_rf
=
4270 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4271 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4273 if ((insn
->tok
[i
].X_op
== O_register
)
4274 && (insn
->tok
[i
].X_add_number
== regnum
))
4284 is_bad_loopend_opcode (const TInsn
*tinsn
)
4286 xtensa_opcode opcode
= tinsn
->opcode
;
4288 if (opcode
== XTENSA_UNDEFINED
)
4291 if (opcode
== xtensa_call0_opcode
4292 || opcode
== xtensa_callx0_opcode
4293 || opcode
== xtensa_call4_opcode
4294 || opcode
== xtensa_callx4_opcode
4295 || opcode
== xtensa_call8_opcode
4296 || opcode
== xtensa_callx8_opcode
4297 || opcode
== xtensa_call12_opcode
4298 || opcode
== xtensa_callx12_opcode
4299 || opcode
== xtensa_isync_opcode
4300 || opcode
== xtensa_ret_opcode
4301 || opcode
== xtensa_ret_n_opcode
4302 || opcode
== xtensa_retw_opcode
4303 || opcode
== xtensa_retw_n_opcode
4304 || opcode
== xtensa_waiti_opcode
4305 || opcode
== xtensa_rsr_lcount_opcode
)
4312 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4313 This allows the debugger to add unaligned labels.
4314 Also, the assembler generates stabs labels that need
4315 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4318 is_unaligned_label (symbolS
*sym
)
4320 const char *name
= S_GET_NAME (sym
);
4321 static size_t fake_size
= 0;
4325 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4328 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4330 fake_size
= strlen (FAKE_LABEL_NAME
);
4333 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4334 && (name
[fake_size
] == 'F'
4335 || name
[fake_size
] == 'L'
4336 || (name
[fake_size
] == 'e'
4337 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4345 next_non_empty_frag (const fragS
*fragP
)
4347 fragS
*next_fragP
= fragP
->fr_next
;
4349 /* Sometimes an empty will end up here due storage allocation issues.
4350 So we have to skip until we find something legit. */
4351 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4352 next_fragP
= next_fragP
->fr_next
;
4354 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4362 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4364 xtensa_opcode out_opcode
;
4365 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4367 if (next_fragP
== NULL
)
4370 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4371 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4373 *opcode
= out_opcode
;
4381 frag_format_size (const fragS
*fragP
)
4383 static xtensa_insnbuf insnbuf
= NULL
;
4384 xtensa_isa isa
= xtensa_default_isa
;
4389 insnbuf
= xtensa_insnbuf_alloc (isa
);
4392 return XTENSA_UNDEFINED
;
4394 xtensa_insnbuf_from_chars (isa
, insnbuf
,
4395 (unsigned char *) fragP
->fr_literal
, 0);
4397 fmt
= xtensa_format_decode (isa
, insnbuf
);
4398 if (fmt
== XTENSA_UNDEFINED
)
4399 return XTENSA_UNDEFINED
;
4400 fmt_size
= xtensa_format_length (isa
, fmt
);
4402 /* If the next format won't be changing due to relaxation, just
4403 return the length of the first format. */
4404 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4407 /* If during relaxation we have to pull an instruction out of a
4408 multi-slot instruction, we will return the more conservative
4409 number. This works because alignment on bigger instructions
4410 is more restrictive than alignment on smaller instructions.
4411 This is more conservative than we would like, but it happens
4414 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4417 /* If we aren't doing one of our own relaxations or it isn't
4418 slot-based, then the insn size won't change. */
4419 if (fragP
->fr_type
!= rs_machine_dependent
)
4421 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4424 /* If an instruction is about to grow, return the longer size. */
4425 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4426 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
)
4429 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4430 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4437 next_frag_format_size (const fragS
*fragP
)
4439 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4440 return frag_format_size (next_fragP
);
4444 /* If the next legit fragment is an end-of-loop marker,
4445 switch its state so it will instantiate a NOP. */
4448 update_next_frag_state (fragS
*fragP
)
4450 fragS
*next_fragP
= fragP
->fr_next
;
4451 fragS
*new_target
= NULL
;
4455 /* We are guaranteed there will be one of these... */
4456 while (!(next_fragP
->fr_type
== rs_machine_dependent
4457 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4458 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4459 next_fragP
= next_fragP
->fr_next
;
4461 assert (next_fragP
->fr_type
== rs_machine_dependent
4462 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4463 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4465 /* ...and one of these. */
4466 new_target
= next_fragP
->fr_next
;
4467 while (!(new_target
->fr_type
== rs_machine_dependent
4468 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4469 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4470 new_target
= new_target
->fr_next
;
4472 assert (new_target
->fr_type
== rs_machine_dependent
4473 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4474 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4477 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4479 if (next_fragP
->fr_type
== rs_machine_dependent
4480 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4482 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4486 next_fragP
= next_fragP
->fr_next
;
4492 next_frag_is_branch_target (const fragS
*fragP
)
4494 /* Sometimes an empty will end up here due to storage allocation issues,
4495 so we have to skip until we find something legit. */
4496 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4498 if (fragP
->tc_frag_data
.is_branch_target
)
4500 if (fragP
->fr_fix
!= 0)
4508 next_frag_is_loop_target (const fragS
*fragP
)
4510 /* Sometimes an empty will end up here due storage allocation issues.
4511 So we have to skip until we find something legit. */
4512 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4514 if (fragP
->tc_frag_data
.is_loop_target
)
4516 if (fragP
->fr_fix
!= 0)
4524 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4526 const fragS
*next_fragp
= fragp
->fr_next
;
4527 xtensa_opcode next_opcode
;
4529 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4532 /* Sometimes an empty will end up here due to storage allocation issues,
4533 so we have to skip until we find something legit. */
4534 while (next_fragp
->fr_fix
== 0)
4535 next_fragp
= next_fragp
->fr_next
;
4537 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4540 /* There is some implicit knowledge encoded in here.
4541 The LOOP instructions that are NOT RELAX_IMMED have
4542 been relaxed. Note that we can assume that the LOOP
4543 instruction is in slot 0 because loops aren't bundleable. */
4544 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4545 return get_expanded_loop_offset (next_opcode
);
4551 /* Mark a location where we can later insert literal frags. Update
4552 the section's literal_pool_loc, so subsequent literals can be
4553 placed nearest to their use. */
4556 xtensa_mark_literal_pool_location (void)
4558 /* Any labels pointing to the current location need
4559 to be adjusted to after the literal pool. */
4561 fragS
*pool_location
;
4563 if (use_literal_section
&& !directive_state
[directive_absolute_literals
])
4566 frag_align (2, 0, 0);
4567 record_alignment (now_seg
, 2);
4569 /* We stash info in these frags so we can later move the literal's
4570 fixes into this frchain's fix list. */
4571 pool_location
= frag_now
;
4572 frag_now
->tc_frag_data
.lit_frchain
= frchain_now
;
4573 frag_variant (rs_machine_dependent
, 0, 0,
4574 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4575 xtensa_set_frag_assembly_state (frag_now
);
4576 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
4577 frag_variant (rs_machine_dependent
, 0, 0,
4578 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4579 xtensa_set_frag_assembly_state (frag_now
);
4581 /* Now put a frag into the literal pool that points to this location. */
4582 set_literal_pool_location (now_seg
, pool_location
);
4583 xtensa_switch_to_non_abs_literal_fragment (&s
);
4584 frag_align (2, 0, 0);
4585 record_alignment (now_seg
, 2);
4587 /* Close whatever frag is there. */
4588 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4589 xtensa_set_frag_assembly_state (frag_now
);
4590 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
4591 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4592 xtensa_restore_emit_state (&s
);
4593 xtensa_set_frag_assembly_state (frag_now
);
4597 /* Build a nop of the correct size into tinsn. */
4600 build_nop (TInsn
*tinsn
, int size
)
4606 tinsn
->opcode
= xtensa_nop_n_opcode
;
4608 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4609 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4613 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4615 tinsn
->opcode
= xtensa_or_opcode
;
4616 set_expr_const (&tinsn
->tok
[0], 1);
4617 set_expr_const (&tinsn
->tok
[1], 1);
4618 set_expr_const (&tinsn
->tok
[2], 1);
4622 tinsn
->opcode
= xtensa_nop_opcode
;
4624 assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4629 /* Assemble a NOP of the requested size in the buffer. User must have
4630 allocated "buf" with at least "size" bytes. */
4633 assemble_nop (int size
, char *buf
)
4635 static xtensa_insnbuf insnbuf
= NULL
;
4638 build_nop (&tinsn
, size
);
4641 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4643 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4644 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4645 (unsigned char *) buf
, 0);
4649 /* Return the number of bytes for the offset of the expanded loop
4650 instruction. This should be incorporated into the relaxation
4651 specification but is hard-coded here. This is used to auto-align
4652 the loop instruction. It is invalid to call this function if the
4653 configuration does not have loops or if the opcode is not a loop
4657 get_expanded_loop_offset (xtensa_opcode opcode
)
4659 /* This is the OFFSET of the loop instruction in the expanded loop.
4660 This MUST correspond directly to the specification of the loop
4661 expansion. It will be validated on fragment conversion. */
4662 assert (opcode
!= XTENSA_UNDEFINED
);
4663 if (opcode
== xtensa_loop_opcode
)
4665 if (opcode
== xtensa_loopnez_opcode
)
4667 if (opcode
== xtensa_loopgtz_opcode
)
4669 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4675 get_literal_pool_location (segT seg
)
4677 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4682 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4684 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4688 /* Set frag assembly state should be called when a new frag is
4689 opened and after a frag has been closed. */
4692 xtensa_set_frag_assembly_state (fragS
*fragP
)
4694 if (!density_supported
)
4695 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4697 /* This function is called from subsegs_finish, which is called
4698 after xtensa_end, so we can't use "use_transform" or
4699 "use_schedule" here. */
4700 if (!directive_state
[directive_transform
])
4701 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4702 if (directive_state
[directive_longcalls
])
4703 fragP
->tc_frag_data
.use_longcalls
= TRUE
;
4704 fragP
->tc_frag_data
.use_absolute_literals
=
4705 directive_state
[directive_absolute_literals
];
4706 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4711 relaxable_section (asection
*sec
)
4713 return (sec
->flags
& SEC_DEBUGGING
) == 0;
4718 xtensa_find_unmarked_state_frags (void)
4722 /* Walk over each fragment of all of the current segments. For each
4723 unmarked fragment, mark it with the same info as the previous
4725 for (seclist
= &stdoutput
->sections
;
4726 seclist
&& *seclist
;
4727 seclist
= &(*seclist
)->next
)
4729 segT sec
= *seclist
;
4730 segment_info_type
*seginfo
;
4733 flags
= bfd_get_section_flags (stdoutput
, sec
);
4734 if (flags
& SEC_DEBUGGING
)
4736 if (!(flags
& SEC_ALLOC
))
4739 seginfo
= seg_info (sec
);
4740 if (seginfo
&& seginfo
->frchainP
)
4742 fragS
*last_fragP
= 0;
4743 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4744 fragP
= fragP
->fr_next
)
4746 if (fragP
->fr_fix
!= 0
4747 && !fragP
->tc_frag_data
.is_assembly_state_set
)
4749 if (last_fragP
== 0)
4751 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
4752 _("assembly state not set for first frag in section %s"),
4757 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4758 fragP
->tc_frag_data
.is_no_density
=
4759 last_fragP
->tc_frag_data
.is_no_density
;
4760 fragP
->tc_frag_data
.is_no_transform
=
4761 last_fragP
->tc_frag_data
.is_no_transform
;
4762 fragP
->tc_frag_data
.use_longcalls
=
4763 last_fragP
->tc_frag_data
.use_longcalls
;
4764 fragP
->tc_frag_data
.use_absolute_literals
=
4765 last_fragP
->tc_frag_data
.use_absolute_literals
;
4768 if (fragP
->tc_frag_data
.is_assembly_state_set
)
4777 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
4779 void *unused ATTRIBUTE_UNUSED
)
4781 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4782 segment_info_type
*seginfo
= seg_info (sec
);
4783 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4785 if (flags
& SEC_CODE
)
4787 xtensa_isa isa
= xtensa_default_isa
;
4788 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4789 while (frag
!= NULL
)
4791 if (frag
->tc_frag_data
.is_branch_target
)
4794 addressT branch_align
, frag_addr
;
4797 xtensa_insnbuf_from_chars
4798 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4799 fmt
= xtensa_format_decode (isa
, insnbuf
);
4800 op_size
= xtensa_format_length (isa
, fmt
);
4801 branch_align
= 1 << branch_align_power (sec
);
4802 frag_addr
= frag
->fr_address
% branch_align
;
4803 if (frag_addr
+ op_size
> branch_align
)
4804 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4805 _("unaligned branch target: %d bytes at 0x%lx"),
4806 op_size
, (long) frag
->fr_address
);
4808 frag
= frag
->fr_next
;
4810 xtensa_insnbuf_free (isa
, insnbuf
);
4816 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
4818 void *unused ATTRIBUTE_UNUSED
)
4820 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4821 segment_info_type
*seginfo
= seg_info (sec
);
4822 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4823 xtensa_isa isa
= xtensa_default_isa
;
4825 if (flags
& SEC_CODE
)
4827 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4828 while (frag
!= NULL
)
4830 if (frag
->tc_frag_data
.is_first_loop_insn
)
4836 xtensa_insnbuf_from_chars
4837 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4838 fmt
= xtensa_format_decode (isa
, insnbuf
);
4839 op_size
= xtensa_format_length (isa
, fmt
);
4840 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
4842 if (frag_addr
+ op_size
> xtensa_fetch_width
)
4843 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4844 _("unaligned loop: %d bytes at 0x%lx"),
4845 op_size
, (long) frag
->fr_address
);
4847 frag
= frag
->fr_next
;
4849 xtensa_insnbuf_free (isa
, insnbuf
);
4855 xg_apply_fix_value (fixS
*fixP
, valueT val
)
4857 xtensa_isa isa
= xtensa_default_isa
;
4858 static xtensa_insnbuf insnbuf
= NULL
;
4859 static xtensa_insnbuf slotbuf
= NULL
;
4862 bfd_boolean alt_reloc
;
4863 xtensa_opcode opcode
;
4864 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
4866 (void) decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
);
4868 as_fatal (_("unexpected fix"));
4872 insnbuf
= xtensa_insnbuf_alloc (isa
);
4873 slotbuf
= xtensa_insnbuf_alloc (isa
);
4876 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4877 fmt
= xtensa_format_decode (isa
, insnbuf
);
4878 if (fmt
== XTENSA_UNDEFINED
)
4879 as_fatal (_("undecodable fix"));
4880 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4881 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
4882 if (opcode
== XTENSA_UNDEFINED
)
4883 as_fatal (_("undecodable fix"));
4885 /* CONST16 immediates are not PC-relative, despite the fact that we
4886 reuse the normal PC-relative operand relocations for the low part
4887 of a CONST16 operand. */
4888 if (opcode
== xtensa_const16_opcode
)
4891 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
4892 get_relaxable_immed (opcode
), val
,
4893 fixP
->fx_file
, fixP
->fx_line
);
4895 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4896 xtensa_insnbuf_to_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4902 /* External Functions and Other GAS Hooks. */
4905 xtensa_target_format (void)
4907 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
4912 xtensa_file_arch_init (bfd
*abfd
)
4914 bfd_set_private_flags (abfd
, 0x100 | 0x200);
4919 md_number_to_chars (char *buf
, valueT val
, int n
)
4921 if (target_big_endian
)
4922 number_to_chars_bigendian (buf
, val
, n
);
4924 number_to_chars_littleendian (buf
, val
, n
);
4928 /* This function is called once, at assembler startup time. It should
4929 set up all the tables, etc. that the MD part of the assembler will
4935 segT current_section
= now_seg
;
4936 int current_subsec
= now_subseg
;
4939 xtensa_default_isa
= xtensa_isa_init (0, 0);
4940 isa
= xtensa_default_isa
;
4944 /* Set up the .literal, .fini.literal and .init.literal sections. */
4945 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
4946 default_lit_sections
.init_lit_seg_name
= INIT_LITERAL_SECTION_NAME
;
4947 default_lit_sections
.fini_lit_seg_name
= FINI_LITERAL_SECTION_NAME
;
4948 default_lit_sections
.lit_seg_name
= LITERAL_SECTION_NAME
;
4949 default_lit_sections
.lit4_seg_name
= LIT4_SECTION_NAME
;
4951 subseg_set (current_section
, current_subsec
);
4953 xg_init_vinsn (&cur_vinsn
);
4955 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
4956 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
4957 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
4958 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
4959 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
4960 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
4961 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
4962 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
4963 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
4964 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
4965 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
4966 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
4967 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
4968 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
4969 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
4970 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
4971 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
4972 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
4973 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
4974 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
4975 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
4976 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
4977 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
4978 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
4979 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
4980 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
4981 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
4982 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
4983 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
4985 init_op_placement_info_table ();
4987 /* Set up the assembly state. */
4988 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
4989 xtensa_set_frag_assembly_state (frag_now
);
4993 /* TC_INIT_FIX_DATA hook */
4996 xtensa_init_fix_data (fixS
*x
)
4998 x
->tc_fix_data
.slot
= 0;
4999 x
->tc_fix_data
.X_add_symbol
= NULL
;
5000 x
->tc_fix_data
.X_add_number
= 0;
5004 /* tc_frob_label hook */
5007 xtensa_frob_label (symbolS
*sym
)
5011 if (cur_vinsn
.inside_bundle
)
5013 as_bad (_("labels are not valid inside bundles"));
5017 freq
= get_subseg_target_freq (now_seg
, now_subseg
);
5019 /* Since the label was already attached to a frag associated with the
5020 previous basic block, it now needs to be reset to the current frag. */
5021 symbol_set_frag (sym
, frag_now
);
5022 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5024 if (generating_literals
)
5025 xtensa_add_literal_sym (sym
);
5027 xtensa_add_insn_label (sym
);
5029 if (symbol_get_tc (sym
)->is_loop_target
)
5031 if ((get_last_insn_flags (now_seg
, now_subseg
)
5032 & FLAG_IS_BAD_LOOPEND
) != 0)
5033 as_bad (_("invalid last instruction for a zero-overhead loop"));
5035 xtensa_set_frag_assembly_state (frag_now
);
5036 frag_var (rs_machine_dependent
, 4, 4, RELAX_LOOP_END
,
5037 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5039 xtensa_set_frag_assembly_state (frag_now
);
5040 xtensa_move_labels (frag_now
, 0, TRUE
);
5043 /* No target aligning in the absolute section. */
5044 if (now_seg
!= absolute_section
5045 && do_align_targets ()
5046 && !is_unaligned_label (sym
)
5047 && !generating_literals
)
5049 xtensa_set_frag_assembly_state (frag_now
);
5051 frag_var (rs_machine_dependent
,
5053 RELAX_DESIRE_ALIGN_IF_TARGET
,
5054 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5055 xtensa_set_frag_assembly_state (frag_now
);
5056 xtensa_move_labels (frag_now
, 0, TRUE
);
5059 /* We need to mark the following properties even if we aren't aligning. */
5061 /* If the label is already known to be a branch target, i.e., a
5062 forward branch, mark the frag accordingly. Backward branches
5063 are handled by xg_add_branch_and_loop_targets. */
5064 if (symbol_get_tc (sym
)->is_branch_target
)
5065 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5067 /* Loops only go forward, so they can be identified here. */
5068 if (symbol_get_tc (sym
)->is_loop_target
)
5069 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5071 dwarf2_emit_label (sym
);
5075 /* tc_unrecognized_line hook */
5078 xtensa_unrecognized_line (int ch
)
5083 if (cur_vinsn
.inside_bundle
== 0)
5085 /* PR8110: Cannot emit line number info inside a FLIX bundle
5086 when using --gstabs. Temporarily disable debug info. */
5087 generate_lineno_debug ();
5088 if (debug_type
== DEBUG_STABS
)
5090 xt_saved_debug_type
= debug_type
;
5091 debug_type
= DEBUG_NONE
;
5094 cur_vinsn
.inside_bundle
= 1;
5098 as_bad (_("extra opening brace"));
5104 if (cur_vinsn
.inside_bundle
)
5105 finish_vinsn (&cur_vinsn
);
5108 as_bad (_("extra closing brace"));
5113 as_bad (_("syntax error"));
5120 /* md_flush_pending_output hook */
5123 xtensa_flush_pending_output (void)
5125 if (cur_vinsn
.inside_bundle
)
5126 as_bad (_("missing closing brace"));
5128 /* If there is a non-zero instruction fragment, close it. */
5129 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5131 frag_wane (frag_now
);
5133 xtensa_set_frag_assembly_state (frag_now
);
5135 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5137 xtensa_clear_insn_labels ();
5141 /* We had an error while parsing an instruction. The string might look
5142 like this: "insn arg1, arg2 }". If so, we need to see the closing
5143 brace and reset some fields. Otherwise, the vinsn never gets closed
5144 and the num_slots field will grow past the end of the array of slots,
5145 and bad things happen. */
5148 error_reset_cur_vinsn (void)
5150 if (cur_vinsn
.inside_bundle
)
5152 if (*input_line_pointer
== '}'
5153 || *(input_line_pointer
- 1) == '}'
5154 || *(input_line_pointer
- 2) == '}')
5155 xg_clear_vinsn (&cur_vinsn
);
5161 md_assemble (char *str
)
5163 xtensa_isa isa
= xtensa_default_isa
;
5164 char *opname
, *file_name
;
5166 bfd_boolean has_underbar
= FALSE
;
5167 char *arg_strings
[MAX_INSN_ARGS
];
5169 TInsn orig_insn
; /* Original instruction from the input. */
5171 tinsn_init (&orig_insn
);
5173 /* Split off the opcode. */
5174 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5175 opname
= xmalloc (opnamelen
+ 1);
5176 memcpy (opname
, str
, opnamelen
);
5177 opname
[opnamelen
] = '\0';
5179 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5182 as_bad (_("syntax error"));
5186 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5189 /* Check for an underbar prefix. */
5192 has_underbar
= TRUE
;
5196 orig_insn
.insn_type
= ITYPE_INSN
;
5198 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5200 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5201 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5203 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5204 if (fmt
== XTENSA_UNDEFINED
)
5206 as_bad (_("unknown opcode or format name '%s'"), opname
);
5207 error_reset_cur_vinsn ();
5210 if (!cur_vinsn
.inside_bundle
)
5212 as_bad (_("format names only valid inside bundles"));
5213 error_reset_cur_vinsn ();
5216 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5217 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5219 cur_vinsn
.format
= fmt
;
5220 free (has_underbar
? opname
- 1 : opname
);
5221 error_reset_cur_vinsn ();
5225 /* Parse the arguments. */
5226 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5228 as_bad (_("syntax error"));
5229 error_reset_cur_vinsn ();
5233 /* Free the opcode and argument strings, now that they've been parsed. */
5234 free (has_underbar
? opname
- 1 : opname
);
5236 while (num_args
-- > 0)
5237 free (arg_strings
[num_args
]);
5239 /* Get expressions for invisible operands. */
5240 if (get_invisible_operands (&orig_insn
))
5242 error_reset_cur_vinsn ();
5246 /* Check for the right number and type of arguments. */
5247 if (tinsn_check_arguments (&orig_insn
))
5249 error_reset_cur_vinsn ();
5253 /* A FLIX bundle may be spread across multiple input lines. We want to
5254 report the first such line in the debug information. Record the line
5255 number for each TInsn (assume the file name doesn't change), so the
5256 first line can be found later. */
5257 as_where (&file_name
, &orig_insn
.linenum
);
5259 xg_add_branch_and_loop_targets (&orig_insn
);
5261 /* Special-case for "entry" instruction. */
5262 if (orig_insn
.opcode
== xtensa_entry_opcode
)
5264 /* Check that the third opcode (#2) is >= 16. */
5265 if (orig_insn
.ntok
>= 3)
5267 expressionS
*exp
= &orig_insn
.tok
[2];
5271 if (exp
->X_add_number
< 16)
5272 as_warn (_("entry instruction with stack decrement < 16"));
5276 as_warn (_("entry instruction with non-constant decrement"));
5282 assemble_tokens (opcode, tok, ntok);
5283 expand the tokens from the orig_insn into the
5284 stack of instructions that will not expand
5285 unless required at relaxation time. */
5287 if (!cur_vinsn
.inside_bundle
)
5288 emit_single_op (&orig_insn
);
5289 else /* We are inside a bundle. */
5291 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5292 cur_vinsn
.num_slots
++;
5293 if (*input_line_pointer
== '}'
5294 || *(input_line_pointer
- 1) == '}'
5295 || *(input_line_pointer
- 2) == '}')
5296 finish_vinsn (&cur_vinsn
);
5299 /* We've just emitted a new instruction so clear the list of labels. */
5300 xtensa_clear_insn_labels ();
5304 /* HANDLE_ALIGN hook */
5306 /* For a .align directive, we mark the previous block with the alignment
5307 information. This will be placed in the object file in the
5308 property section corresponding to this section. */
5311 xtensa_handle_align (fragS
*fragP
)
5314 && ! fragP
->tc_frag_data
.is_literal
5315 && (fragP
->fr_type
== rs_align
5316 || fragP
->fr_type
== rs_align_code
)
5317 && fragP
->fr_address
+ fragP
->fr_fix
> 0
5318 && fragP
->fr_offset
> 0
5319 && now_seg
!= bss_section
)
5321 fragP
->tc_frag_data
.is_align
= TRUE
;
5322 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5325 if (fragP
->fr_type
== rs_align_test
)
5328 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5330 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5331 _("unaligned entry instruction"));
5336 /* TC_FRAG_INIT hook */
5339 xtensa_frag_init (fragS
*frag
)
5341 xtensa_set_frag_assembly_state (frag
);
5346 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5352 /* Round up a section size to the appropriate boundary. */
5355 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5357 return size
; /* Byte alignment is fine. */
5362 md_pcrel_from (fixS
*fixP
)
5365 static xtensa_insnbuf insnbuf
= NULL
;
5366 static xtensa_insnbuf slotbuf
= NULL
;
5369 xtensa_opcode opcode
;
5372 xtensa_isa isa
= xtensa_default_isa
;
5373 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5374 bfd_boolean alt_reloc
;
5376 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5381 insnbuf
= xtensa_insnbuf_alloc (isa
);
5382 slotbuf
= xtensa_insnbuf_alloc (isa
);
5385 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5386 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) insn_p
, 0);
5387 fmt
= xtensa_format_decode (isa
, insnbuf
);
5389 if (fmt
== XTENSA_UNDEFINED
)
5390 as_fatal (_("bad instruction format"));
5392 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5393 as_fatal (_("invalid relocation"));
5395 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5396 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5398 /* Check for "alternate" relocations (operand not specified). None
5399 of the current uses for these are really PC-relative. */
5400 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5402 if (opcode
!= xtensa_l32r_opcode
5403 && opcode
!= xtensa_const16_opcode
)
5404 as_fatal (_("invalid relocation for '%s' instruction"),
5405 xtensa_opcode_name (isa
, opcode
));
5409 opnum
= get_relaxable_immed (opcode
);
5411 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5412 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5414 as_bad_where (fixP
->fx_file
,
5416 _("invalid relocation for operand %d of '%s'"),
5417 opnum
, xtensa_opcode_name (isa
, opcode
));
5420 return 0 - opnd_value
;
5424 /* TC_FORCE_RELOCATION hook */
5427 xtensa_force_relocation (fixS
*fix
)
5429 switch (fix
->fx_r_type
)
5431 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5432 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5433 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5434 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5435 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5436 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5437 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5438 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5439 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5440 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5441 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5442 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5443 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5444 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5445 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5446 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5452 if (linkrelax
&& fix
->fx_addsy
5453 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5456 return generic_force_reloc (fix
);
5460 /* TC_VALIDATE_FIX_SUB hook */
5463 xtensa_validate_fix_sub (fixS
*fix
)
5465 segT add_symbol_segment
, sub_symbol_segment
;
5467 /* The difference of two symbols should be resolved by the assembler when
5468 linkrelax is not set. If the linker may relax the section containing
5469 the symbols, then an Xtensa DIFF relocation must be generated so that
5470 the linker knows to adjust the difference value. */
5471 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
5474 /* Make sure both symbols are in the same segment, and that segment is
5475 "normal" and relaxable. If the segment is not "normal", then the
5476 fix is not valid. If the segment is not "relaxable", then the fix
5477 should have been handled earlier. */
5478 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
5479 if (! SEG_NORMAL (add_symbol_segment
) ||
5480 ! relaxable_section (add_symbol_segment
))
5482 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
5483 return (sub_symbol_segment
== add_symbol_segment
);
5487 /* NO_PSEUDO_DOT hook */
5489 /* This function has nothing to do with pseudo dots, but this is the
5490 nearest macro to where the check needs to take place. FIXME: This
5494 xtensa_check_inside_bundle (void)
5496 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5497 as_bad (_("directives are not valid inside bundles"));
5499 /* This function must always return FALSE because it is called via a
5500 macro that has nothing to do with bundling. */
5505 /* md_elf_section_change_hook */
5508 xtensa_elf_section_change_hook (void)
5510 /* Set up the assembly state. */
5511 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5512 xtensa_set_frag_assembly_state (frag_now
);
5516 /* tc_fix_adjustable hook */
5519 xtensa_fix_adjustable (fixS
*fixP
)
5521 /* An offset is not allowed in combination with the difference of two
5522 symbols, but that cannot be easily detected after a local symbol
5523 has been adjusted to a (section+offset) form. Return 0 so that such
5524 an fix will not be adjusted. */
5525 if (fixP
->fx_subsy
&& fixP
->fx_addsy
&& fixP
->fx_offset
5526 && relaxable_section (S_GET_SEGMENT (fixP
->fx_subsy
)))
5529 /* We need the symbol name for the VTABLE entries. */
5530 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5531 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5539 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg
)
5541 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5544 switch (fixP
->fx_r_type
)
5549 if (linkrelax
&& fixP
->fx_subsy
)
5551 switch (fixP
->fx_r_type
)
5554 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF8
;
5557 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF16
;
5560 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF32
;
5566 /* An offset is only allowed when it results from adjusting a
5567 local symbol into a section-relative offset. If the offset
5568 came from the original expression, tc_fix_adjustable will have
5569 prevented the fix from being converted to a section-relative
5570 form so that we can flag the error here. */
5571 if (fixP
->fx_offset
!= 0 && !symbol_section_p (fixP
->fx_addsy
))
5572 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5573 _("cannot represent subtraction with an offset"));
5575 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5576 - S_GET_VALUE (fixP
->fx_subsy
));
5578 /* The difference value gets written out, and the DIFF reloc
5579 identifies the address of the subtracted symbol (i.e., the one
5580 with the lowest address). */
5582 fixP
->fx_offset
-= val
;
5583 fixP
->fx_subsy
= NULL
;
5585 else if (! fixP
->fx_addsy
)
5592 md_number_to_chars (fixpos
, val
, fixP
->fx_size
);
5593 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5596 case BFD_RELOC_XTENSA_SLOT0_OP
:
5597 case BFD_RELOC_XTENSA_SLOT1_OP
:
5598 case BFD_RELOC_XTENSA_SLOT2_OP
:
5599 case BFD_RELOC_XTENSA_SLOT3_OP
:
5600 case BFD_RELOC_XTENSA_SLOT4_OP
:
5601 case BFD_RELOC_XTENSA_SLOT5_OP
:
5602 case BFD_RELOC_XTENSA_SLOT6_OP
:
5603 case BFD_RELOC_XTENSA_SLOT7_OP
:
5604 case BFD_RELOC_XTENSA_SLOT8_OP
:
5605 case BFD_RELOC_XTENSA_SLOT9_OP
:
5606 case BFD_RELOC_XTENSA_SLOT10_OP
:
5607 case BFD_RELOC_XTENSA_SLOT11_OP
:
5608 case BFD_RELOC_XTENSA_SLOT12_OP
:
5609 case BFD_RELOC_XTENSA_SLOT13_OP
:
5610 case BFD_RELOC_XTENSA_SLOT14_OP
:
5613 /* Write the tentative value of a PC-relative relocation to a
5614 local symbol into the instruction. The value will be ignored
5615 by the linker, and it makes the object file disassembly
5616 readable when all branch targets are encoded in relocations. */
5618 assert (fixP
->fx_addsy
);
5619 if (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
&& !fixP
->fx_plt
5620 && !S_FORCE_RELOC (fixP
->fx_addsy
, 1))
5622 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5623 - md_pcrel_from (fixP
));
5624 (void) xg_apply_fix_value (fixP
, val
);
5627 else if (! fixP
->fx_addsy
)
5630 if (xg_apply_fix_value (fixP
, val
))
5635 case BFD_RELOC_XTENSA_PLT
:
5636 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5637 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5638 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5639 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5640 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5641 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5642 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5643 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5644 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5645 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5646 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5647 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5648 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5649 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5650 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5651 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5652 /* These all need to be resolved at link-time. Do nothing now. */
5655 case BFD_RELOC_VTABLE_INHERIT
:
5656 case BFD_RELOC_VTABLE_ENTRY
:
5661 as_bad (_("unhandled local relocation fix %s"),
5662 bfd_get_reloc_code_name (fixP
->fx_r_type
));
5668 md_atof (int type
, char *litP
, int *sizeP
)
5671 LITTLENUM_TYPE words
[4];
5687 return "bad call to md_atof";
5690 t
= atof_ieee (input_line_pointer
, type
, words
);
5692 input_line_pointer
= t
;
5696 for (i
= prec
- 1; i
>= 0; i
--)
5699 if (target_big_endian
)
5700 idx
= (prec
- 1 - i
);
5702 md_number_to_chars (litP
, (valueT
) words
[idx
], 2);
5711 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
5713 return total_frag_text_expansion (fragP
);
5717 /* Translate internal representation of relocation info to BFD target
5721 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
5725 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
5726 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5727 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5728 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5730 /* Make sure none of our internal relocations make it this far.
5731 They'd better have been fully resolved by this point. */
5732 assert ((int) fixp
->fx_r_type
> 0);
5734 reloc
->addend
= fixp
->fx_offset
;
5736 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
5737 if (reloc
->howto
== NULL
)
5739 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5740 _("cannot represent `%s' relocation in object file"),
5741 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5742 free (reloc
->sym_ptr_ptr
);
5747 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
5748 as_fatal (_("internal error? cannot generate `%s' relocation"),
5749 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5755 /* Checks for resource conflicts between instructions. */
5757 /* The func unit stuff could be implemented as bit-vectors rather
5758 than the iterative approach here. If it ends up being too
5759 slow, we will switch it. */
5762 new_resource_table (void *data
,
5765 unit_num_copies_func uncf
,
5766 opcode_num_units_func onuf
,
5767 opcode_funcUnit_use_unit_func ouuf
,
5768 opcode_funcUnit_use_stage_func ousf
)
5771 resource_table
*rt
= (resource_table
*) xmalloc (sizeof (resource_table
));
5773 rt
->cycles
= cycles
;
5774 rt
->allocated_cycles
= cycles
;
5776 rt
->unit_num_copies
= uncf
;
5777 rt
->opcode_num_units
= onuf
;
5778 rt
->opcode_unit_use
= ouuf
;
5779 rt
->opcode_unit_stage
= ousf
;
5781 rt
->units
= (unsigned char **) xcalloc (cycles
, sizeof (unsigned char *));
5782 for (i
= 0; i
< cycles
; i
++)
5783 rt
->units
[i
] = (unsigned char *) xcalloc (nu
, sizeof (unsigned char));
5790 clear_resource_table (resource_table
*rt
)
5793 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
5794 for (j
= 0; j
< rt
->num_units
; j
++)
5795 rt
->units
[i
][j
] = 0;
5799 /* We never shrink it, just fake it into thinking so. */
5802 resize_resource_table (resource_table
*rt
, int cycles
)
5806 rt
->cycles
= cycles
;
5807 if (cycles
<= rt
->allocated_cycles
)
5810 old_cycles
= rt
->allocated_cycles
;
5811 rt
->allocated_cycles
= cycles
;
5813 rt
->units
= xrealloc (rt
->units
,
5814 rt
->allocated_cycles
* sizeof (unsigned char *));
5815 for (i
= 0; i
< old_cycles
; i
++)
5816 rt
->units
[i
] = xrealloc (rt
->units
[i
],
5817 rt
->num_units
* sizeof (unsigned char));
5818 for (i
= old_cycles
; i
< cycles
; i
++)
5819 rt
->units
[i
] = xcalloc (rt
->num_units
, sizeof (unsigned char));
5824 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5827 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5829 for (i
= 0; i
< uses
; i
++)
5831 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5832 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5833 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
5834 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
5835 if (copies_in_use
>= copies
)
5843 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5846 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5848 for (i
= 0; i
< uses
; i
++)
5850 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5851 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5852 /* Note that this allows resources to be oversubscribed. That's
5853 essential to the way the optional scheduler works.
5854 resources_available reports when a resource is over-subscribed,
5855 so it's easy to tell. */
5856 rt
->units
[stage
+ cycle
][unit
]++;
5862 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5865 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5867 for (i
= 0; i
< uses
; i
++)
5869 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5870 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5871 assert (rt
->units
[stage
+ cycle
][unit
] > 0);
5872 rt
->units
[stage
+ cycle
][unit
]--;
5877 /* Wrapper functions make parameterized resource reservation
5881 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
5883 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5889 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
5891 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5896 /* Note that this function does not check issue constraints, but
5897 solely whether the hardware is available to execute the given
5898 instructions together. It also doesn't check if the tinsns
5899 write the same state, or access the same tieports. That is
5900 checked by check_t1_t2_reads_and_writes. */
5903 resources_conflict (vliw_insn
*vinsn
)
5906 static resource_table
*rt
= NULL
;
5908 /* This is the most common case by far. Optimize it. */
5909 if (vinsn
->num_slots
== 1)
5914 xtensa_isa isa
= xtensa_default_isa
;
5915 rt
= new_resource_table
5916 (isa
, xtensa_isa_num_pipe_stages (isa
),
5917 xtensa_isa_num_funcUnits (isa
),
5918 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
5919 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
5920 opcode_funcUnit_use_unit
,
5921 opcode_funcUnit_use_stage
);
5924 clear_resource_table (rt
);
5926 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5928 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
5930 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
5937 /* finish_vinsn, emit_single_op and helper functions. */
5939 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
5940 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
5941 static void bundle_single_op (TInsn
*);
5942 static void xg_assemble_vliw_tokens (vliw_insn
*);
5945 /* We have reached the end of a bundle; emit into the frag. */
5948 finish_vinsn (vliw_insn
*vinsn
)
5955 if (find_vinsn_conflicts (vinsn
))
5957 xg_clear_vinsn (vinsn
);
5961 /* First, find a format that works. */
5962 if (vinsn
->format
== XTENSA_UNDEFINED
)
5963 vinsn
->format
= xg_find_narrowest_format (vinsn
);
5965 if (vinsn
->format
== XTENSA_UNDEFINED
)
5967 as_where (&file_name
, &line
);
5968 as_bad_where (file_name
, line
,
5969 _("couldn't find a valid instruction format"));
5970 fprintf (stderr
, _(" ops were: "));
5971 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5972 fprintf (stderr
, _(" %s;"),
5973 xtensa_opcode_name (xtensa_default_isa
,
5974 vinsn
->slots
[i
].opcode
));
5975 fprintf (stderr
, _("\n"));
5976 xg_clear_vinsn (vinsn
);
5980 if (vinsn
->num_slots
5981 != xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
))
5983 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
5984 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
5985 xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
),
5987 xg_clear_vinsn (vinsn
);
5991 if (resources_conflict (vinsn
))
5993 as_where (&file_name
, &line
);
5994 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
5995 fprintf (stderr
, " ops were: ");
5996 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5997 fprintf (stderr
, " %s;",
5998 xtensa_opcode_name (xtensa_default_isa
,
5999 vinsn
->slots
[i
].opcode
));
6000 fprintf (stderr
, "\n");
6001 xg_clear_vinsn (vinsn
);
6005 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6007 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
6009 symbolS
*lit_sym
= NULL
;
6011 bfd_boolean e
= FALSE
;
6012 bfd_boolean saved_density
= density_supported
;
6014 /* We don't want to narrow ops inside multi-slot bundles. */
6015 if (vinsn
->num_slots
> 1)
6016 density_supported
= FALSE
;
6018 istack_init (&slotstack
);
6019 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
6021 vinsn
->slots
[i
].opcode
=
6022 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6024 vinsn
->slots
[i
].ntok
= 0;
6027 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
6033 density_supported
= saved_density
;
6037 xg_clear_vinsn (vinsn
);
6041 for (j
= 0; j
< slotstack
.ninsn
; j
++)
6043 TInsn
*insn
= &slotstack
.insn
[j
];
6044 if (insn
->insn_type
== ITYPE_LITERAL
)
6046 assert (lit_sym
== NULL
);
6047 lit_sym
= xg_assemble_literal (insn
);
6051 assert (insn
->insn_type
== ITYPE_INSN
);
6053 xg_resolve_literals (insn
, lit_sym
);
6054 if (j
!= slotstack
.ninsn
- 1)
6055 emit_single_op (insn
);
6059 if (vinsn
->num_slots
> 1)
6061 if (opcode_fits_format_slot
6062 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6065 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6069 bundle_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6070 if (vinsn
->format
== XTENSA_UNDEFINED
)
6071 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6073 vinsn
->slots
[i
].opcode
6074 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6077 vinsn
->slots
[i
].ntok
= 0;
6082 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6083 vinsn
->format
= XTENSA_UNDEFINED
;
6088 /* Now check resource conflicts on the modified bundle. */
6089 if (resources_conflict (vinsn
))
6091 as_where (&file_name
, &line
);
6092 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6093 fprintf (stderr
, " ops were: ");
6094 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6095 fprintf (stderr
, " %s;",
6096 xtensa_opcode_name (xtensa_default_isa
,
6097 vinsn
->slots
[i
].opcode
));
6098 fprintf (stderr
, "\n");
6099 xg_clear_vinsn (vinsn
);
6103 /* First, find a format that works. */
6104 if (vinsn
->format
== XTENSA_UNDEFINED
)
6105 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6107 xg_assemble_vliw_tokens (vinsn
);
6109 xg_clear_vinsn (vinsn
);
6113 /* Given an vliw instruction, what conflicts are there in register
6114 usage and in writes to states and queues?
6116 This function does two things:
6117 1. Reports an error when a vinsn contains illegal combinations
6118 of writes to registers states or queues.
6119 2. Marks individual tinsns as not relaxable if the combination
6120 contains antidependencies.
6122 Job 2 handles things like swap semantics in instructions that need
6123 to be relaxed. For example,
6127 normally would be relaxed to
6132 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6134 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6136 then we can't relax it into
6139 { add a0, a1, a0 ; add a2, a0, a4 ; }
6141 because the value of a0 is trashed before the second add can read it. */
6143 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6146 find_vinsn_conflicts (vliw_insn
*vinsn
)
6150 xtensa_isa isa
= xtensa_default_isa
;
6152 assert (!past_xtensa_end
);
6154 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6156 TInsn
*op1
= &vinsn
->slots
[i
];
6157 if (op1
->is_specific_opcode
)
6158 op1
->keep_wide
= TRUE
;
6160 op1
->keep_wide
= FALSE
;
6163 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6165 TInsn
*op1
= &vinsn
->slots
[i
];
6167 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6170 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6174 TInsn
*op2
= &vinsn
->slots
[j
];
6175 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6176 switch (conflict_type
)
6179 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6180 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6181 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6184 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6185 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6186 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6189 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same queue"),
6190 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6191 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6194 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile queue accesses"),
6195 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6196 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6199 /* Everything is OK. */
6202 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6203 || conflict_type
== 'a');
6210 as_bad (_("multiple branches or jumps in the same bundle"));
6218 /* Check how the state used by t1 and t2 relate.
6221 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6222 case B: no relationship between what is read and written (both could
6223 read the same reg though)
6224 case C: t1 writes a register t2 writes (a register conflict within a
6226 case D: t1 writes a state that t2 also writes
6227 case E: t1 writes a tie queue that t2 also writes
6228 case F: two volatile queue accesses
6232 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6234 xtensa_isa isa
= xtensa_default_isa
;
6235 xtensa_regfile t1_regfile
, t2_regfile
;
6237 int t1_base_reg
, t1_last_reg
;
6238 int t2_base_reg
, t2_last_reg
;
6239 char t1_inout
, t2_inout
;
6241 char conflict
= 'b';
6246 bfd_boolean t1_volatile
= FALSE
;
6247 bfd_boolean t2_volatile
= FALSE
;
6249 /* Check registers. */
6250 for (j
= 0; j
< t2
->ntok
; j
++)
6252 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6255 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6256 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6257 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6259 for (i
= 0; i
< t1
->ntok
; i
++)
6261 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6264 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6266 if (t1_regfile
!= t2_regfile
)
6269 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6270 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6272 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6273 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6275 if (t1_inout
== 'm' || t1_inout
== 'o'
6276 || t2_inout
== 'm' || t2_inout
== 'o')
6283 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6284 t1_last_reg
= (t1_base_reg
6285 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6287 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6289 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6291 if (t1_reg
!= t2_reg
)
6294 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6300 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6306 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6314 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6315 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6316 for (j
= 0; j
< t2_states
; j
++)
6318 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6319 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6320 for (i
= 0; i
< t1_states
; i
++)
6322 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6323 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6327 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6333 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6339 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6344 /* Check tieports. */
6345 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6346 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6347 for (j
= 0; j
< t2_interfaces
; j
++)
6349 xtensa_interface t2_int
6350 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6351 int t2_class
= xtensa_interface_class_id (isa
, t2_int
);
6353 t2_inout
= xtensa_interface_inout (isa
, j
);
6354 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1)
6357 for (i
= 0; i
< t1_interfaces
; i
++)
6359 xtensa_interface t1_int
6360 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6361 int t1_class
= xtensa_interface_class_id (isa
, t1_int
);
6363 t1_inout
= xtensa_interface_inout (isa
, i
);
6364 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1)
6367 if (t1_volatile
&& t2_volatile
&& (t1_class
== t2_class
))
6370 if (t1_int
!= t2_int
)
6373 if (t2_inout
== 'i' && t1_inout
== 'o')
6379 if (t1_inout
== 'i' && t2_inout
== 'o')
6385 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6394 static xtensa_format
6395 xg_find_narrowest_format (vliw_insn
*vinsn
)
6397 /* Right now we assume that the ops within the vinsn are properly
6398 ordered for the slots that the programmer wanted them in. In
6399 other words, we don't rearrange the ops in hopes of finding a
6400 better format. The scheduler handles that. */
6402 xtensa_isa isa
= xtensa_default_isa
;
6403 xtensa_format format
;
6404 vliw_insn v_copy
= *vinsn
;
6405 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6407 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6410 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6414 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6416 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6418 v_copy
.slots
[slot
].opcode
=
6419 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6420 v_copy
.slots
[slot
].ntok
= 0;
6423 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6426 else if (v_copy
.num_slots
> 1)
6429 /* Try the widened version. */
6430 if (!v_copy
.slots
[slot
].keep_wide
6431 && !v_copy
.slots
[slot
].is_specific_opcode
6432 && xg_is_single_relaxable_insn (&v_copy
.slots
[slot
],
6434 && opcode_fits_format_slot (widened
.opcode
,
6437 v_copy
.slots
[slot
] = widened
;
6442 if (fit
== v_copy
.num_slots
)
6445 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6446 vinsn
->format
= format
;
6452 if (format
== xtensa_isa_num_formats (isa
))
6453 return XTENSA_UNDEFINED
;
6459 /* Return the additional space needed in a frag
6460 for possible relaxations of any ops in a VLIW insn.
6461 Also fill out the relaxations that might be required of
6462 each tinsn in the vinsn. */
6465 relaxation_requirements (vliw_insn
*vinsn
)
6467 int extra_space
= 0;
6470 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6472 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6473 if (!tinsn_has_symbolic_operands (tinsn
))
6475 /* A narrow instruction could be widened later to help
6476 alignment issues. */
6477 if (xg_is_single_relaxable_insn (tinsn
, 0, TRUE
)
6478 && !tinsn
->is_specific_opcode
6479 && vinsn
->num_slots
== 1)
6481 /* Difference in bytes between narrow and wide insns... */
6483 tinsn
->subtype
= RELAX_NARROW
;
6484 tinsn
->record_fix
= TRUE
;
6489 tinsn
->record_fix
= FALSE
;
6490 /* No extra_space needed. */
6495 if (workaround_b_j_loop_end
6496 && tinsn
->opcode
== xtensa_jx_opcode
6497 && use_transform ())
6499 /* Add 2 of these. */
6500 extra_space
+= 3; /* for the nop size */
6501 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6504 /* Need to assemble it with space for the relocation. */
6505 if (xg_is_relaxable_insn (tinsn
, 0)
6506 && !tinsn
->is_specific_opcode
)
6508 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6509 int max_literal_size
=
6510 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6512 tinsn
->literal_space
= max_literal_size
;
6514 tinsn
->subtype
= RELAX_IMMED
;
6515 tinsn
->record_fix
= FALSE
;
6516 extra_space
+= max_size
;
6520 tinsn
->record_fix
= TRUE
;
6521 /* No extra space needed. */
6530 bundle_single_op (TInsn
*orig_insn
)
6532 xtensa_isa isa
= xtensa_default_isa
;
6537 v
.format
= op_placement_table
[orig_insn
->opcode
].narrowest
;
6538 assert (v
.format
!= XTENSA_UNDEFINED
);
6539 v
.num_slots
= xtensa_format_num_slots (isa
, v
.format
);
6542 !opcode_fits_format_slot (orig_insn
->opcode
, v
.format
, slot
);
6545 v
.slots
[slot
].opcode
=
6546 xtensa_format_slot_nop_opcode (isa
, v
.format
, slot
);
6547 v
.slots
[slot
].ntok
= 0;
6548 v
.slots
[slot
].insn_type
= ITYPE_INSN
;
6551 v
.slots
[slot
] = *orig_insn
;
6554 for ( ; slot
< v
.num_slots
; slot
++)
6556 v
.slots
[slot
].opcode
=
6557 xtensa_format_slot_nop_opcode (isa
, v
.format
, slot
);
6558 v
.slots
[slot
].ntok
= 0;
6559 v
.slots
[slot
].insn_type
= ITYPE_INSN
;
6568 emit_single_op (TInsn
*orig_insn
)
6571 IStack istack
; /* put instructions into here */
6572 symbolS
*lit_sym
= NULL
;
6573 symbolS
*label_sym
= NULL
;
6575 istack_init (&istack
);
6577 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6578 Because the scheduling and bundling characteristics of movi and
6579 l32r or const16 are so different, we can do much better if we relax
6580 it prior to scheduling and bundling, rather than after. */
6581 if ((orig_insn
->opcode
== xtensa_movi_opcode
6582 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
6583 && !cur_vinsn
.inside_bundle
6584 && (orig_insn
->tok
[1].X_op
== O_symbol
6585 || orig_insn
->tok
[1].X_op
== O_pltrel
))
6586 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
6588 if (xg_expand_assembly_insn (&istack
, orig_insn
))
6591 for (i
= 0; i
< istack
.ninsn
; i
++)
6593 TInsn
*insn
= &istack
.insn
[i
];
6594 switch (insn
->insn_type
)
6597 assert (lit_sym
== NULL
);
6598 lit_sym
= xg_assemble_literal (insn
);
6602 static int relaxed_sym_idx
= 0;
6603 char *label
= xmalloc (strlen (FAKE_LABEL_NAME
) + 12);
6604 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
6606 assert (label_sym
== NULL
);
6607 label_sym
= symbol_find_or_make (label
);
6614 xg_resolve_literals (insn
, lit_sym
);
6616 xg_resolve_labels (insn
, label_sym
);
6617 bundle_single_op (insn
);
6629 total_frag_text_expansion (fragS
*fragP
)
6632 int total_expansion
= 0;
6634 for (slot
= 0; slot
< MAX_SLOTS
; slot
++)
6635 total_expansion
+= fragP
->tc_frag_data
.text_expansion
[slot
];
6637 return total_expansion
;
6641 /* Emit a vliw instruction to the current fragment. */
6644 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
6646 bfd_boolean finish_frag
= FALSE
;
6647 bfd_boolean is_jump
= FALSE
;
6648 bfd_boolean is_branch
= FALSE
;
6649 xtensa_isa isa
= xtensa_default_isa
;
6655 unsigned current_line
, best_linenum
;
6658 best_linenum
= UINT_MAX
;
6660 if (generating_literals
)
6662 static int reported
= 0;
6664 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
6665 _("cannot assemble into a literal fragment"));
6672 if (frag_now_fix () != 0
6673 && (! frag_now
->tc_frag_data
.is_insn
6674 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6675 || !use_transform () != frag_now
->tc_frag_data
.is_no_transform
6676 || (directive_state
[directive_longcalls
]
6677 != frag_now
->tc_frag_data
.use_longcalls
)
6678 || (directive_state
[directive_absolute_literals
]
6679 != frag_now
->tc_frag_data
.use_absolute_literals
)))
6681 frag_wane (frag_now
);
6683 xtensa_set_frag_assembly_state (frag_now
);
6686 if (workaround_a0_b_retw
6687 && vinsn
->num_slots
== 1
6688 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
6689 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
6690 && use_transform ())
6692 has_a0_b_retw
= TRUE
;
6694 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
6695 After the first assembly pass we will check all of them and
6696 add a nop if needed. */
6697 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6698 frag_var (rs_machine_dependent
, 4, 4,
6699 RELAX_ADD_NOP_IF_A0_B_RETW
,
6700 frag_now
->fr_symbol
,
6701 frag_now
->fr_offset
,
6703 xtensa_set_frag_assembly_state (frag_now
);
6704 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6705 frag_var (rs_machine_dependent
, 4, 4,
6706 RELAX_ADD_NOP_IF_A0_B_RETW
,
6707 frag_now
->fr_symbol
,
6708 frag_now
->fr_offset
,
6710 xtensa_set_frag_assembly_state (frag_now
);
6713 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6715 /* See if the instruction implies an aligned section. */
6716 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[i
].opcode
) == 1)
6717 record_alignment (now_seg
, 2);
6719 /* Also determine the best line number for debug info. */
6720 best_linenum
= vinsn
->slots
[i
].linenum
< best_linenum
6721 ? vinsn
->slots
[i
].linenum
: best_linenum
;
6724 /* Special cases for instructions that force an alignment... */
6725 /* None of these opcodes are bundle-able. */
6726 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
6730 xtensa_set_frag_assembly_state (frag_now
);
6731 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6733 max_fill
= get_text_align_max_fill_size
6734 (get_text_align_power (xtensa_fetch_width
),
6735 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
6737 if (use_transform ())
6738 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
6739 RELAX_ALIGN_NEXT_OPCODE
,
6740 frag_now
->fr_symbol
,
6741 frag_now
->fr_offset
,
6744 frag_var (rs_machine_dependent
, 0, 0,
6745 RELAX_CHECK_ALIGN_NEXT_OPCODE
, 0, 0, NULL
);
6746 xtensa_set_frag_assembly_state (frag_now
);
6748 xtensa_move_labels (frag_now
, 0, FALSE
);
6751 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
6752 && !vinsn
->slots
[0].is_specific_opcode
)
6754 xtensa_mark_literal_pool_location ();
6755 xtensa_move_labels (frag_now
, 0, TRUE
);
6756 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
6759 if (vinsn
->num_slots
== 1)
6761 if (workaround_a0_b_retw
&& use_transform ())
6762 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
6763 is_register_writer (&vinsn
->slots
[0], "a", 0));
6765 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
6766 is_bad_loopend_opcode (&vinsn
->slots
[0]));
6769 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
6771 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
6773 extra_space
= relaxation_requirements (vinsn
);
6775 /* vinsn_to_insnbuf will produce the error. */
6776 if (vinsn
->format
!= XTENSA_UNDEFINED
)
6778 f
= frag_more (insn_size
+ extra_space
);
6779 xtensa_set_frag_assembly_state (frag_now
);
6780 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6783 vinsn_to_insnbuf (vinsn
, f
, frag_now
, TRUE
);
6784 if (vinsn
->format
== XTENSA_UNDEFINED
)
6787 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, (unsigned char *) f
, 0);
6789 /* Temporarily set the logical line number to the one we want to appear
6790 in the debug information. */
6791 as_where (¤t_file
, ¤t_line
);
6792 new_logical_line (current_file
, best_linenum
);
6793 dwarf2_emit_insn (insn_size
+ extra_space
);
6794 new_logical_line (current_file
, current_line
);
6796 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6798 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6799 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
6800 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
6801 frag_now
->tc_frag_data
.slot_sub_symbols
[slot
] = tinsn
->sub_symbol
;
6802 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
6803 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
6804 if (tinsn
->literal_space
!= 0)
6805 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
6807 if (tinsn
->subtype
== RELAX_NARROW
)
6808 assert (vinsn
->num_slots
== 1);
6809 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
6811 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
6814 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->record_fix
6815 || tinsn
->offset
|| tinsn
->literal_frag
|| is_jump
|| is_branch
)
6819 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6820 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
6824 frag_variant (rs_machine_dependent
,
6825 extra_space
, extra_space
, RELAX_SLOTS
,
6826 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
6827 xtensa_set_frag_assembly_state (frag_now
);
6830 /* Special cases for loops:
6831 close_loop_end should be inserted AFTER short_loop.
6832 Make sure that CLOSE loops are processed BEFORE short_loops
6833 when converting them. */
6835 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
6836 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
)
6837 && !vinsn
->slots
[0].is_specific_opcode
)
6839 if (workaround_short_loop
&& use_transform ())
6841 maybe_has_short_loop
= TRUE
;
6842 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6843 frag_var (rs_machine_dependent
, 4, 4,
6844 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6845 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6846 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6847 frag_var (rs_machine_dependent
, 4, 4,
6848 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6849 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6852 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
6853 loop at least 12 bytes away from another loop's end. */
6854 if (workaround_close_loop_end
&& use_transform ())
6856 maybe_has_close_loop_end
= TRUE
;
6857 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6858 frag_var (rs_machine_dependent
, 12, 12,
6859 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
6860 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6864 if (use_transform ())
6868 assert (finish_frag
);
6869 frag_var (rs_machine_dependent
,
6870 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6872 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6873 xtensa_set_frag_assembly_state (frag_now
);
6875 else if (is_branch
&& do_align_targets ())
6877 assert (finish_frag
);
6878 frag_var (rs_machine_dependent
,
6879 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6880 RELAX_MAYBE_UNREACHABLE
,
6881 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6882 xtensa_set_frag_assembly_state (frag_now
);
6883 frag_var (rs_machine_dependent
,
6885 RELAX_MAYBE_DESIRE_ALIGN
,
6886 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6887 xtensa_set_frag_assembly_state (frag_now
);
6891 /* Now, if the original opcode was a call... */
6892 if (do_align_targets ()
6893 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
6895 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
6896 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6897 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
6898 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6899 xtensa_set_frag_assembly_state (frag_now
);
6902 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6904 frag_wane (frag_now
);
6906 xtensa_set_frag_assembly_state (frag_now
);
6911 /* xtensa_end and helper functions. */
6913 static void xtensa_cleanup_align_frags (void);
6914 static void xtensa_fix_target_frags (void);
6915 static void xtensa_mark_narrow_branches (void);
6916 static void xtensa_mark_zcl_first_insns (void);
6917 static void xtensa_fix_a0_b_retw_frags (void);
6918 static void xtensa_fix_b_j_loop_end_frags (void);
6919 static void xtensa_fix_close_loop_end_frags (void);
6920 static void xtensa_fix_short_loop_frags (void);
6921 static void xtensa_sanity_check (void);
6926 directive_balance ();
6927 xtensa_flush_pending_output ();
6929 past_xtensa_end
= TRUE
;
6931 xtensa_move_literals ();
6933 xtensa_reorder_segments ();
6934 xtensa_cleanup_align_frags ();
6935 xtensa_fix_target_frags ();
6936 if (workaround_a0_b_retw
&& has_a0_b_retw
)
6937 xtensa_fix_a0_b_retw_frags ();
6938 if (workaround_b_j_loop_end
)
6939 xtensa_fix_b_j_loop_end_frags ();
6941 /* "close_loop_end" should be processed BEFORE "short_loop". */
6942 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
6943 xtensa_fix_close_loop_end_frags ();
6945 if (workaround_short_loop
&& maybe_has_short_loop
)
6946 xtensa_fix_short_loop_frags ();
6947 xtensa_mark_narrow_branches ();
6948 xtensa_mark_zcl_first_insns ();
6950 xtensa_sanity_check ();
6955 xtensa_cleanup_align_frags (void)
6959 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
6962 /* Walk over all of the fragments in a subsection. */
6963 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
6965 if ((fragP
->fr_type
== rs_align
6966 || fragP
->fr_type
== rs_align_code
6967 || (fragP
->fr_type
== rs_machine_dependent
6968 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
6969 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
6970 && fragP
->fr_fix
== 0)
6972 fragS
*next
= fragP
->fr_next
;
6975 && next
->fr_fix
== 0
6976 && next
->fr_type
== rs_machine_dependent
6977 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
6980 next
= next
->fr_next
;
6983 /* If we don't widen branch targets, then they
6984 will be easier to align. */
6985 if (fragP
->tc_frag_data
.is_branch_target
6986 && fragP
->fr_opcode
== fragP
->fr_literal
6987 && fragP
->fr_type
== rs_machine_dependent
6988 && fragP
->fr_subtype
== RELAX_SLOTS
6989 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
6991 if (fragP
->fr_type
== rs_machine_dependent
6992 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
6993 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
6999 /* Re-process all of the fragments looking to convert all of the
7000 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
7001 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7002 Otherwise, convert to a .fill 0. */
7005 xtensa_fix_target_frags (void)
7009 /* When this routine is called, all of the subsections are still intact
7010 so we walk over subsections instead of sections. */
7011 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7015 /* Walk over all of the fragments in a subsection. */
7016 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7018 if (fragP
->fr_type
== rs_machine_dependent
7019 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7021 if (next_frag_is_branch_target (fragP
))
7022 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7031 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
7034 xtensa_mark_narrow_branches (void)
7038 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7041 /* Walk over all of the fragments in a subsection. */
7042 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7044 if (fragP
->fr_type
== rs_machine_dependent
7045 && fragP
->fr_subtype
== RELAX_SLOTS
7046 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7049 const expressionS
*expr
;
7052 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7053 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
7055 expr
= &vinsn
.slots
[0].tok
[1];
7056 symbolP
= expr
->X_add_symbol
;
7058 if (vinsn
.num_slots
== 1
7059 && xtensa_opcode_is_branch (xtensa_default_isa
,
7060 vinsn
.slots
[0].opcode
)
7061 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
7062 && is_narrow_branch_guaranteed_in_range (fragP
,
7065 fragP
->fr_subtype
= RELAX_SLOTS
;
7066 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
7074 /* A branch is typically widened only when its target is out of
7075 range. However, we would like to widen them to align a subsequent
7076 branch target when possible.
7078 Because the branch relaxation code is so convoluted, the optimal solution
7079 (combining the two cases) is difficult to get right in all circumstances.
7080 We therefore go with an "almost as good" solution, where we only
7081 use for alignment narrow branches that definitely will not expand to a
7082 jump and a branch. These functions find and mark these cases. */
7084 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
7085 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7086 We start counting beginning with the frag after the 2-byte branch, so the
7087 maximum offset is (4 - 2) + 63 = 65. */
7088 #define MAX_IMMED6 65
7090 static offsetT
unrelaxed_frag_max_size (fragS
*);
7093 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
7095 const expressionS
*expr
= &tinsn
->tok
[1];
7096 symbolS
*symbolP
= expr
->X_add_symbol
;
7097 fragS
*target_frag
= symbol_get_frag (symbolP
);
7098 offsetT max_distance
= expr
->X_add_number
;
7099 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
7100 if (is_branch_jmp_to_next (tinsn
, fragP
))
7103 /* The branch doesn't branch over it's own frag,
7104 but over the subsequent ones. */
7105 fragP
= fragP
->fr_next
;
7106 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
7108 max_distance
+= unrelaxed_frag_max_size (fragP
);
7109 fragP
= fragP
->fr_next
;
7111 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
7118 xtensa_mark_zcl_first_insns (void)
7122 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7125 /* Walk over all of the fragments in a subsection. */
7126 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7128 if (fragP
->fr_type
== rs_machine_dependent
7129 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7130 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7132 /* Find the loop frag. */
7133 fragS
*targ_frag
= next_non_empty_frag (fragP
);
7134 /* Find the first insn frag. */
7135 targ_frag
= next_non_empty_frag (targ_frag
);
7137 /* Of course, sometimes (mostly for toy test cases) a
7138 zero-cost loop instruction is the last in a section. */
7140 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
7141 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
7149 /* Re-process all of the fragments looking to convert all of the
7150 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7151 conditional branch or a retw/retw.n, convert this frag to one that
7152 will generate a NOP. In any case close it off with a .fill 0. */
7154 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
7157 xtensa_fix_a0_b_retw_frags (void)
7161 /* When this routine is called, all of the subsections are still intact
7162 so we walk over subsections instead of sections. */
7163 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7167 /* Walk over all of the fragments in a subsection. */
7168 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7170 if (fragP
->fr_type
== rs_machine_dependent
7171 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
7173 if (next_instrs_are_b_retw (fragP
))
7175 if (fragP
->tc_frag_data
.is_no_transform
)
7176 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7178 relax_frag_add_nop (fragP
);
7188 next_instrs_are_b_retw (fragS
*fragP
)
7190 xtensa_opcode opcode
;
7192 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
7193 static xtensa_insnbuf insnbuf
= NULL
;
7194 static xtensa_insnbuf slotbuf
= NULL
;
7195 xtensa_isa isa
= xtensa_default_isa
;
7198 bfd_boolean branch_seen
= FALSE
;
7202 insnbuf
= xtensa_insnbuf_alloc (isa
);
7203 slotbuf
= xtensa_insnbuf_alloc (isa
);
7206 if (next_fragP
== NULL
)
7209 /* Check for the conditional branch. */
7210 xtensa_insnbuf_from_chars
7211 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7212 fmt
= xtensa_format_decode (isa
, insnbuf
);
7213 if (fmt
== XTENSA_UNDEFINED
)
7216 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7218 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
7219 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
7221 branch_seen
= (branch_seen
7222 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
7228 offset
+= xtensa_format_length (isa
, fmt
);
7229 if (offset
== next_fragP
->fr_fix
)
7231 next_fragP
= next_non_empty_frag (next_fragP
);
7235 if (next_fragP
== NULL
)
7238 /* Check for the retw/retw.n. */
7239 xtensa_insnbuf_from_chars
7240 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7241 fmt
= xtensa_format_decode (isa
, insnbuf
);
7243 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
7244 have no problems. */
7245 if (fmt
== XTENSA_UNDEFINED
7246 || xtensa_format_num_slots (isa
, fmt
) != 1)
7249 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
7250 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
7252 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
7259 /* Re-process all of the fragments looking to convert all of the
7260 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
7261 loop end label, convert this frag to one that will generate a NOP.
7262 In any case close it off with a .fill 0. */
7264 static bfd_boolean
next_instr_is_loop_end (fragS
*);
7267 xtensa_fix_b_j_loop_end_frags (void)
7271 /* When this routine is called, all of the subsections are still intact
7272 so we walk over subsections instead of sections. */
7273 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7277 /* Walk over all of the fragments in a subsection. */
7278 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7280 if (fragP
->fr_type
== rs_machine_dependent
7281 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
7283 if (next_instr_is_loop_end (fragP
))
7285 if (fragP
->tc_frag_data
.is_no_transform
)
7286 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
7288 relax_frag_add_nop (fragP
);
7298 next_instr_is_loop_end (fragS
*fragP
)
7300 const fragS
*next_fragP
;
7302 if (next_frag_is_loop_target (fragP
))
7305 next_fragP
= next_non_empty_frag (fragP
);
7306 if (next_fragP
== NULL
)
7309 if (!next_frag_is_loop_target (next_fragP
))
7312 /* If the size is >= 3 then there is more than one instruction here.
7313 The hardware bug will not fire. */
7314 if (next_fragP
->fr_fix
> 3)
7321 /* Re-process all of the fragments looking to convert all of the
7322 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
7323 not MY loop's loop end within 12 bytes, add enough nops here to
7324 make it at least 12 bytes away. In any case close it off with a
7327 static offsetT min_bytes_to_other_loop_end
7328 (fragS
*, fragS
*, offsetT
, offsetT
);
7331 xtensa_fix_close_loop_end_frags (void)
7335 /* When this routine is called, all of the subsections are still intact
7336 so we walk over subsections instead of sections. */
7337 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7341 fragS
*current_target
= NULL
;
7342 offsetT current_offset
= 0;
7344 /* Walk over all of the fragments in a subsection. */
7345 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7347 if (fragP
->fr_type
== rs_machine_dependent
7348 && ((fragP
->fr_subtype
== RELAX_IMMED
)
7349 || ((fragP
->fr_subtype
== RELAX_SLOTS
)
7350 && (fragP
->tc_frag_data
.slot_subtypes
[0]
7353 /* Read it. If the instruction is a loop, get the target. */
7355 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7356 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7357 t_insn
.opcode
) == 1)
7359 /* Get the current fragment target. */
7360 if (fragP
->tc_frag_data
.slot_symbols
[0])
7362 symbolS
*sym
= fragP
->tc_frag_data
.slot_symbols
[0];
7363 current_target
= symbol_get_frag (sym
);
7364 current_offset
= fragP
->fr_offset
;
7370 && fragP
->fr_type
== rs_machine_dependent
7371 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
7374 int bytes_added
= 0;
7376 #define REQUIRED_LOOP_DIVIDING_BYTES 12
7377 /* Max out at 12. */
7378 min_bytes
= min_bytes_to_other_loop_end
7379 (fragP
->fr_next
, current_target
, current_offset
,
7380 REQUIRED_LOOP_DIVIDING_BYTES
);
7382 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
7384 if (fragP
->tc_frag_data
.is_no_transform
)
7385 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
7388 while (min_bytes
+ bytes_added
7389 < REQUIRED_LOOP_DIVIDING_BYTES
)
7393 if (fragP
->fr_var
< length
)
7394 as_fatal (_("fr_var %lu < length %d"),
7395 (long) fragP
->fr_var
, length
);
7398 assemble_nop (length
,
7399 fragP
->fr_literal
+ fragP
->fr_fix
);
7400 fragP
->fr_fix
+= length
;
7401 fragP
->fr_var
-= length
;
7403 bytes_added
+= length
;
7409 assert (fragP
->fr_type
!= rs_machine_dependent
7410 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
7416 static offsetT
unrelaxed_frag_min_size (fragS
*);
7419 min_bytes_to_other_loop_end (fragS
*fragP
,
7420 fragS
*current_target
,
7421 offsetT current_offset
,
7425 fragS
*current_fragP
;
7427 for (current_fragP
= fragP
;
7429 current_fragP
= current_fragP
->fr_next
)
7431 if (current_fragP
->tc_frag_data
.is_loop_target
7432 && current_fragP
!= current_target
)
7433 return offset
+ current_offset
;
7435 offset
+= unrelaxed_frag_min_size (current_fragP
);
7437 if (offset
+ current_offset
>= max_size
)
7445 unrelaxed_frag_min_size (fragS
*fragP
)
7447 offsetT size
= fragP
->fr_fix
;
7449 /* Add fill size. */
7450 if (fragP
->fr_type
== rs_fill
)
7451 size
+= fragP
->fr_offset
;
7458 unrelaxed_frag_max_size (fragS
*fragP
)
7460 offsetT size
= fragP
->fr_fix
;
7461 switch (fragP
->fr_type
)
7464 /* Empty frags created by the obstack allocation scheme
7465 end up with type 0. */
7470 size
+= fragP
->fr_offset
;
7478 /* No further adjustments needed. */
7480 case rs_machine_dependent
:
7481 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
7482 size
+= fragP
->fr_var
;
7485 /* We had darn well better know how big it is. */
7494 /* Re-process all of the fragments looking to convert all
7495 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
7498 1) the instruction size count to the loop end label
7499 is too short (<= 2 instructions),
7500 2) loop has a jump or branch in it
7503 1) workaround_all_short_loops is TRUE
7504 2) The generating loop was a 'loopgtz' or 'loopnez'
7505 3) the instruction size count to the loop end label is too short
7507 then convert this frag (and maybe the next one) to generate a NOP.
7508 In any case close it off with a .fill 0. */
7510 static int count_insns_to_loop_end (fragS
*, bfd_boolean
, int);
7511 static bfd_boolean
branch_before_loop_end (fragS
*);
7514 xtensa_fix_short_loop_frags (void)
7518 /* When this routine is called, all of the subsections are still intact
7519 so we walk over subsections instead of sections. */
7520 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7523 fragS
*current_target
= NULL
;
7524 offsetT current_offset
= 0;
7525 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
7527 /* Walk over all of the fragments in a subsection. */
7528 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7530 /* Check on the current loop. */
7531 if (fragP
->fr_type
== rs_machine_dependent
7532 && ((fragP
->fr_subtype
== RELAX_IMMED
)
7533 || ((fragP
->fr_subtype
== RELAX_SLOTS
)
7534 && (fragP
->tc_frag_data
.slot_subtypes
[0]
7539 /* Read it. If the instruction is a loop, get the target. */
7540 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7541 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7542 t_insn
.opcode
) == 1)
7544 /* Get the current fragment target. */
7545 if (fragP
->tc_frag_data
.slot_symbols
[0])
7547 symbolS
*sym
= fragP
->tc_frag_data
.slot_symbols
[0];
7548 current_target
= symbol_get_frag (sym
);
7549 current_offset
= fragP
->fr_offset
;
7550 current_opcode
= t_insn
.opcode
;
7555 if (fragP
->fr_type
== rs_machine_dependent
7556 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7558 if (count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3) < 3
7559 && (branch_before_loop_end (fragP
->fr_next
)
7560 || (workaround_all_short_loops
7561 && current_opcode
!= XTENSA_UNDEFINED
7562 && current_opcode
!= xtensa_loop_opcode
)))
7564 if (fragP
->tc_frag_data
.is_no_transform
)
7565 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
7567 relax_frag_add_nop (fragP
);
7576 static int unrelaxed_frag_min_insn_count (fragS
*);
7579 count_insns_to_loop_end (fragS
*base_fragP
,
7580 bfd_boolean count_relax_add
,
7583 fragS
*fragP
= NULL
;
7588 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
7590 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
7591 if (insn_count
>= max_count
)
7594 if (count_relax_add
)
7596 if (fragP
->fr_type
== rs_machine_dependent
7597 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7599 /* In order to add the appropriate number of
7600 NOPs, we count an instruction for downstream
7603 if (insn_count
>= max_count
)
7613 unrelaxed_frag_min_insn_count (fragS
*fragP
)
7615 xtensa_isa isa
= xtensa_default_isa
;
7616 static xtensa_insnbuf insnbuf
= NULL
;
7620 if (!fragP
->tc_frag_data
.is_insn
)
7624 insnbuf
= xtensa_insnbuf_alloc (isa
);
7626 /* Decode the fixed instructions. */
7627 while (offset
< fragP
->fr_fix
)
7631 xtensa_insnbuf_from_chars
7632 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7633 fmt
= xtensa_format_decode (isa
, insnbuf
);
7635 if (fmt
== XTENSA_UNDEFINED
)
7637 as_fatal (_("undecodable instruction in instruction frag"));
7640 offset
+= xtensa_format_length (isa
, fmt
);
7648 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
7651 branch_before_loop_end (fragS
*base_fragP
)
7655 for (fragP
= base_fragP
;
7656 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
7657 fragP
= fragP
->fr_next
)
7659 if (unrelaxed_frag_has_b_j (fragP
))
7667 unrelaxed_frag_has_b_j (fragS
*fragP
)
7669 static xtensa_insnbuf insnbuf
= NULL
;
7670 xtensa_isa isa
= xtensa_default_isa
;
7673 if (!fragP
->tc_frag_data
.is_insn
)
7677 insnbuf
= xtensa_insnbuf_alloc (isa
);
7679 /* Decode the fixed instructions. */
7680 while (offset
< fragP
->fr_fix
)
7685 xtensa_insnbuf_from_chars
7686 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7687 fmt
= xtensa_format_decode (isa
, insnbuf
);
7688 if (fmt
== XTENSA_UNDEFINED
)
7691 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7693 xtensa_opcode opcode
=
7694 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
7695 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
7696 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
7699 offset
+= xtensa_format_length (isa
, fmt
);
7705 /* Checks to be made after initial assembly but before relaxation. */
7707 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
7708 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
7711 xtensa_sanity_check (void)
7718 as_where (&file_name
, &line
);
7719 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7723 /* Walk over all of the fragments in a subsection. */
7724 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7726 /* Currently we only check for empty loops here. */
7727 if (fragP
->fr_type
== rs_machine_dependent
7728 && fragP
->fr_subtype
== RELAX_IMMED
)
7730 static xtensa_insnbuf insnbuf
= NULL
;
7733 if (fragP
->fr_opcode
!= NULL
)
7736 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7737 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7738 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
7740 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7741 t_insn
.opcode
) == 1)
7743 if (is_empty_loop (&t_insn
, fragP
))
7745 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7746 as_bad (_("invalid empty loop"));
7748 if (!is_local_forward_loop (&t_insn
, fragP
))
7750 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7751 as_bad (_("loop target does not follow "
7752 "loop instruction in section"));
7759 new_logical_line (file_name
, line
);
7763 #define LOOP_IMMED_OPN 1
7765 /* Return TRUE if the loop target is the next non-zero fragment. */
7768 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
7770 const expressionS
*expr
;
7774 if (insn
->insn_type
!= ITYPE_INSN
)
7777 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
7780 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7783 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7785 if (expr
->X_op
!= O_symbol
)
7788 symbolP
= expr
->X_add_symbol
;
7792 if (symbol_get_frag (symbolP
) == NULL
)
7795 if (S_GET_VALUE (symbolP
) != 0)
7798 /* Walk through the zero-size fragments from this one. If we find
7799 the target fragment, then this is a zero-size loop. */
7801 for (next_fragP
= fragP
->fr_next
;
7803 next_fragP
= next_fragP
->fr_next
)
7805 if (next_fragP
== symbol_get_frag (symbolP
))
7807 if (next_fragP
->fr_fix
!= 0)
7815 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
7817 const expressionS
*expr
;
7821 if (insn
->insn_type
!= ITYPE_INSN
)
7824 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) == 0)
7827 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7830 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7832 if (expr
->X_op
!= O_symbol
)
7835 symbolP
= expr
->X_add_symbol
;
7839 if (symbol_get_frag (symbolP
) == NULL
)
7842 /* Walk through fragments until we find the target.
7843 If we do not find the target, then this is an invalid loop. */
7845 for (next_fragP
= fragP
->fr_next
;
7847 next_fragP
= next_fragP
->fr_next
)
7849 if (next_fragP
== symbol_get_frag (symbolP
))
7857 /* Alignment Functions. */
7860 get_text_align_power (unsigned target_size
)
7865 assert (target_size
<= INT_MAX
);
7866 while (target_size
> power
)
7876 get_text_align_max_fill_size (int align_pow
,
7877 bfd_boolean use_nops
,
7878 bfd_boolean use_no_density
)
7881 return (1 << align_pow
);
7883 return 3 * (1 << align_pow
);
7885 return 1 + (1 << align_pow
);
7889 /* Calculate the minimum bytes of fill needed at "address" to align a
7890 target instruction of size "target_size" so that it does not cross a
7891 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE,
7892 the fill can be an arbitrary number of bytes. Otherwise, the space must
7893 be filled by NOP instructions. */
7896 get_text_align_fill_size (addressT address
,
7899 bfd_boolean use_nops
,
7900 bfd_boolean use_no_density
)
7902 addressT alignment
, fill
, fill_limit
, fill_step
;
7903 bfd_boolean skip_one
= FALSE
;
7905 alignment
= (1 << align_pow
);
7906 assert (target_size
> 0 && alignment
>= (addressT
) target_size
);
7910 fill_limit
= alignment
;
7913 else if (!use_no_density
)
7915 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */
7916 fill_limit
= alignment
* 2;
7922 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */
7923 fill_limit
= alignment
* 3;
7927 /* Try all fill sizes until finding one that works. */
7928 for (fill
= 0; fill
< fill_limit
; fill
+= fill_step
)
7930 if (skip_one
&& fill
== 1)
7932 if ((address
+ fill
) >> align_pow
7933 == (address
+ fill
+ target_size
- 1) >> align_pow
)
7942 branch_align_power (segT sec
)
7944 /* If the Xtensa processor has a fetch width of 8 bytes, and the section
7945 is aligned to at least an 8-byte boundary, then a branch target need
7946 only fit within an 8-byte aligned block of memory to avoid a stall.
7947 Otherwise, try to fit branch targets within 4-byte aligned blocks
7948 (which may be insufficient, e.g., if the section has no alignment, but
7949 it's good enough). */
7950 if (xtensa_fetch_width
== 8)
7952 if (get_recorded_alignment (sec
) >= 3)
7956 assert (xtensa_fetch_width
== 4);
7962 /* This will assert if it is not possible. */
7965 get_text_align_nop_count (offsetT fill_size
, bfd_boolean use_no_density
)
7971 assert (fill_size
% 3 == 0);
7972 return (fill_size
/ 3);
7975 assert (fill_size
!= 1); /* Bad argument. */
7977 while (fill_size
> 1)
7980 if (fill_size
== 2 || fill_size
== 4)
7982 fill_size
-= insn_size
;
7985 assert (fill_size
!= 1); /* Bad algorithm. */
7991 get_text_align_nth_nop_size (offsetT fill_size
,
7993 bfd_boolean use_no_density
)
8000 assert (fill_size
!= 1); /* Bad argument. */
8002 while (fill_size
> 1)
8005 if (fill_size
== 2 || fill_size
== 4)
8007 fill_size
-= insn_size
;
8017 /* For the given fragment, find the appropriate address
8018 for it to begin at if we are using NOPs to align it. */
8021 get_noop_aligned_address (fragS
*fragP
, addressT address
)
8023 /* The rule is: get next fragment's FIRST instruction. Find
8024 the smallest number of bytes that need to be added to
8025 ensure that the next fragment's FIRST instruction will fit
8028 E.G., 2 bytes : 0, 1, 2 mod 4
8031 If the FIRST instruction MIGHT be relaxed,
8032 assume that it will become a 3-byte instruction.
8034 Note again here that LOOP instructions are not bundleable,
8035 and this relaxation only applies to LOOP opcodes. */
8038 int first_insn_size
;
8040 addressT pre_opcode_bytes
;
8043 xtensa_opcode opcode
;
8044 bfd_boolean is_loop
;
8046 assert (fragP
->fr_type
== rs_machine_dependent
);
8047 assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
8049 /* Find the loop frag. */
8050 first_insn
= next_non_empty_frag (fragP
);
8051 /* Now find the first insn frag. */
8052 first_insn
= next_non_empty_frag (first_insn
);
8054 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
8056 loop_insn_size
= xg_get_single_size (opcode
);
8058 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
8059 pre_opcode_bytes
+= loop_insn_size
;
8061 /* For loops, the alignment depends on the size of the
8062 instruction following the loop, not the LOOP instruction. */
8064 if (first_insn
== NULL
)
8067 assert (first_insn
->tc_frag_data
.is_first_loop_insn
);
8069 first_insn_size
= frag_format_size (first_insn
);
8071 if (first_insn_size
== 2 || first_insn_size
== XTENSA_UNDEFINED
)
8072 first_insn_size
= 3; /* ISA specifies this */
8074 /* If it was 8, then we'll need a larger alignment for the section. */
8075 align_power
= get_text_align_power (first_insn_size
);
8076 record_alignment (now_seg
, align_power
);
8078 fill_size
= get_text_align_fill_size
8079 (address
+ pre_opcode_bytes
, align_power
, first_insn_size
, TRUE
,
8080 fragP
->tc_frag_data
.is_no_density
);
8082 return address
+ fill_size
;
8086 /* 3 mechanisms for relaxing an alignment:
8088 Align to a power of 2.
8089 Align so the next fragment's instruction does not cross a word boundary.
8090 Align the current instruction so that if the next instruction
8091 were 3 bytes, it would not cross a word boundary.
8095 zeros - This is easy; always insert zeros.
8096 nops - 3-byte and 2-byte instructions
8100 >=5 : 3-byte instruction + fn (n-3)
8101 widening - widen previous instructions. */
8104 get_aligned_diff (fragS
*fragP
, addressT address
, offsetT
*max_diff
)
8106 addressT target_address
, loop_insn_offset
;
8108 xtensa_opcode loop_opcode
;
8109 bfd_boolean is_loop
;
8112 offsetT branch_align
;
8114 assert (fragP
->fr_type
== rs_machine_dependent
);
8115 switch (fragP
->fr_subtype
)
8117 case RELAX_DESIRE_ALIGN
:
8118 target_size
= next_frag_format_size (fragP
);
8119 if (target_size
== XTENSA_UNDEFINED
)
8121 align_power
= branch_align_power (now_seg
);
8122 branch_align
= 1 << align_power
;
8123 /* Don't count on the section alignment being as large as the target. */
8124 if (target_size
> branch_align
)
8125 target_size
= branch_align
;
8126 opt_diff
= get_text_align_fill_size (address
, align_power
,
8127 target_size
, FALSE
, FALSE
);
8129 *max_diff
= (opt_diff
+ branch_align
8130 - (target_size
+ ((address
+ opt_diff
) % branch_align
)));
8131 assert (*max_diff
>= opt_diff
);
8134 case RELAX_ALIGN_NEXT_OPCODE
:
8135 target_size
= next_frag_format_size (fragP
);
8136 loop_insn_offset
= 0;
8137 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
8140 /* If the loop has been expanded then the LOOP instruction
8141 could be at an offset from this fragment. */
8142 if (next_non_empty_frag(fragP
)->tc_frag_data
.slot_subtypes
[0]
8144 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
8146 if (target_size
== 2)
8147 target_size
= 3; /* ISA specifies this */
8149 /* In an ideal world, which is what we are shooting for here,
8150 we wouldn't need to use any NOPs immediately prior to the
8151 LOOP instruction. If this approach fails, relax_frag_loop_align
8152 will call get_noop_aligned_address. */
8154 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
8155 align_power
= get_text_align_power (target_size
),
8156 opt_diff
= get_text_align_fill_size (target_address
, align_power
,
8157 target_size
, FALSE
, FALSE
);
8159 *max_diff
= xtensa_fetch_width
8160 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
8161 - target_size
+ opt_diff
;
8162 assert (*max_diff
>= opt_diff
);
8173 /* md_relax_frag Hook and Helper Functions. */
8175 static long relax_frag_loop_align (fragS
*, long);
8176 static long relax_frag_for_align (fragS
*, long);
8177 static long relax_frag_immed
8178 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
8181 /* Return the number of bytes added to this fragment, given that the
8182 input has been stretched already by "stretch". */
8185 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
8187 xtensa_isa isa
= xtensa_default_isa
;
8188 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
8189 long new_stretch
= 0;
8193 static xtensa_insnbuf vbuf
= NULL
;
8194 int slot
, num_slots
;
8197 as_where (&file_name
, &line
);
8198 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8200 fragP
->tc_frag_data
.unreported_expansion
= 0;
8202 switch (fragP
->fr_subtype
)
8204 case RELAX_ALIGN_NEXT_OPCODE
:
8205 /* Always convert. */
8206 if (fragP
->tc_frag_data
.relax_seen
)
8207 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
8210 case RELAX_LOOP_END
:
8214 case RELAX_LOOP_END_ADD_NOP
:
8215 /* Add a NOP and switch to .fill 0. */
8216 new_stretch
= relax_frag_add_nop (fragP
);
8220 case RELAX_DESIRE_ALIGN
:
8221 /* Do nothing. The narrowing before this frag will either align
8226 case RELAX_LITERAL_FINAL
:
8229 case RELAX_LITERAL_NR
:
8231 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
8232 assert (unreported
== lit_size
);
8233 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
8234 fragP
->fr_var
-= lit_size
;
8235 fragP
->fr_fix
+= lit_size
;
8241 vbuf
= xtensa_insnbuf_alloc (isa
);
8243 xtensa_insnbuf_from_chars
8244 (isa
, vbuf
, (unsigned char *) fragP
->fr_opcode
, 0);
8245 fmt
= xtensa_format_decode (isa
, vbuf
);
8246 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8248 for (slot
= 0; slot
< num_slots
; slot
++)
8250 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
8253 if (fragP
->tc_frag_data
.relax_seen
)
8254 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8258 case RELAX_IMMED_STEP1
:
8259 case RELAX_IMMED_STEP2
:
8260 /* Place the immediate. */
8261 new_stretch
+= relax_frag_immed
8262 (now_seg
, fragP
, stretch
,
8263 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8264 fmt
, slot
, stretched_p
, FALSE
);
8268 /* This is OK; see the note in xg_assemble_vliw_tokens. */
8274 case RELAX_LITERAL_POOL_BEGIN
:
8275 case RELAX_LITERAL_POOL_END
:
8276 case RELAX_MAYBE_UNREACHABLE
:
8277 case RELAX_MAYBE_DESIRE_ALIGN
:
8278 /* No relaxation required. */
8281 case RELAX_FILL_NOP
:
8282 case RELAX_UNREACHABLE
:
8283 if (fragP
->tc_frag_data
.relax_seen
)
8284 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8288 as_bad (_("bad relaxation state"));
8291 /* Tell gas we need another relaxation pass. */
8292 if (! fragP
->tc_frag_data
.relax_seen
)
8294 fragP
->tc_frag_data
.relax_seen
= TRUE
;
8298 new_logical_line (file_name
, line
);
8304 relax_frag_loop_align (fragS
*fragP
, long stretch
)
8306 addressT old_address
, old_next_address
, old_size
;
8307 addressT new_address
, new_next_address
, new_size
;
8310 /* All the frags with relax_frag_for_alignment prior to this one in the
8311 section have been done, hopefully eliminating the need for a NOP here.
8312 But, this will put it in if necessary. */
8314 /* Calculate the old address of this fragment and the next fragment. */
8315 old_address
= fragP
->fr_address
- stretch
;
8316 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
8317 fragP
->tc_frag_data
.text_expansion
[0]);
8318 old_size
= old_next_address
- old_address
;
8320 /* Calculate the new address of this fragment and the next fragment. */
8321 new_address
= fragP
->fr_address
;
8323 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
8324 new_size
= new_next_address
- new_address
;
8326 growth
= new_size
- old_size
;
8328 /* Fix up the text_expansion field and return the new growth. */
8329 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
8334 /* Add a NOP instruction. */
8337 relax_frag_add_nop (fragS
*fragP
)
8339 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
8340 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
8341 assemble_nop (length
, nop_buf
);
8342 fragP
->tc_frag_data
.is_insn
= TRUE
;
8344 if (fragP
->fr_var
< length
)
8346 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP
->fr_var
, length
);
8350 fragP
->fr_fix
+= length
;
8351 fragP
->fr_var
-= length
;
8356 static long future_alignment_required (fragS
*, long);
8359 relax_frag_for_align (fragS
*fragP
, long stretch
)
8361 /* Overview of the relaxation procedure for alignment:
8362 We can widen with NOPs or by widening instructions or by filling
8363 bytes after jump instructions. Find the opportune places and widen
8364 them if necessary. */
8369 assert (fragP
->fr_subtype
== RELAX_FILL_NOP
8370 || fragP
->fr_subtype
== RELAX_UNREACHABLE
8371 || (fragP
->fr_subtype
== RELAX_SLOTS
8372 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
8374 stretch_me
= future_alignment_required (fragP
, stretch
);
8375 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
8381 /* We expanded on a previous pass. Can we shrink now? */
8382 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
8383 if (shrink
<= stretch
&& stretch
> 0)
8385 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8391 /* Below here, diff > 0. */
8392 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8398 /* Return the address of the next frag that should be aligned.
8400 By "address" we mean the address it _would_ be at if there
8401 is no action taken to align it between here and the target frag.
8402 In other words, if no narrows and no fill nops are used between
8403 here and the frag to align, _even_if_ some of the frags we use
8404 to align targets have already expanded on a previous relaxation
8407 Also, count each frag that may be used to help align the target.
8409 Return 0 if there are no frags left in the chain that need to be
8413 find_address_of_next_align_frag (fragS
**fragPP
,
8417 bfd_boolean
*paddable
)
8419 fragS
*fragP
= *fragPP
;
8420 addressT address
= fragP
->fr_address
;
8422 /* Do not reset the counts to 0. */
8426 /* Limit this to a small search. */
8432 address
+= fragP
->fr_fix
;
8434 if (fragP
->fr_type
== rs_fill
)
8435 address
+= fragP
->fr_offset
* fragP
->fr_var
;
8436 else if (fragP
->fr_type
== rs_machine_dependent
)
8438 switch (fragP
->fr_subtype
)
8440 case RELAX_UNREACHABLE
:
8444 case RELAX_FILL_NOP
:
8446 if (!fragP
->tc_frag_data
.is_no_density
)
8451 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8456 address
+= total_frag_text_expansion (fragP
);;
8460 address
+= fragP
->tc_frag_data
.text_expansion
[0];
8463 case RELAX_ALIGN_NEXT_OPCODE
:
8464 case RELAX_DESIRE_ALIGN
:
8468 case RELAX_MAYBE_UNREACHABLE
:
8469 case RELAX_MAYBE_DESIRE_ALIGN
:
8474 /* Just punt if we don't know the type. */
8481 /* Just punt if we don't know the type. */
8485 fragP
= fragP
->fr_next
;
8493 static long bytes_to_stretch (fragS
*, int, int, int, int);
8496 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
8498 fragS
*this_frag
= fragP
;
8502 int narrow_nops
= 0;
8503 bfd_boolean paddable
= FALSE
;
8504 offsetT local_opt_diff
;
8507 int stretch_amount
= 0;
8508 int local_stretch_amount
;
8509 int global_stretch_amount
;
8511 address
= find_address_of_next_align_frag
8512 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
8516 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
8517 opt_diff
= local_opt_diff
;
8518 assert (opt_diff
>= 0);
8519 assert (max_diff
>= opt_diff
);
8524 fragP
= fragP
->fr_next
;
8526 while (fragP
&& opt_diff
< max_diff
&& address
)
8528 /* We only use these to determine if we can exit early
8529 because there will be plenty of ways to align future
8531 int glob_widens
= 0;
8534 bfd_boolean glob_pad
= 0;
8535 address
= find_address_of_next_align_frag
8536 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
8537 /* If there is a padable portion, then skip. */
8538 if (glob_pad
|| glob_widens
>= (1 << branch_align_power (now_seg
)))
8543 offsetT next_m_diff
;
8544 offsetT next_o_diff
;
8546 /* Downrange frags haven't had stretch added to them yet. */
8549 /* The address also includes any text expansion from this
8550 frag in a previous pass, but we don't want that. */
8551 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
8553 /* Assume we are going to move at least opt_diff. In
8554 reality, we might not be able to, but assuming that
8555 we will helps catch cases where moving opt_diff pushes
8556 the next target from aligned to unaligned. */
8557 address
+= opt_diff
;
8559 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
8561 /* Now cleanup for the adjustments to address. */
8562 next_o_diff
+= opt_diff
;
8563 next_m_diff
+= opt_diff
;
8564 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
8565 opt_diff
= next_o_diff
;
8566 if (next_m_diff
< max_diff
)
8567 max_diff
= next_m_diff
;
8568 fragP
= fragP
->fr_next
;
8572 /* If there are enough wideners in between, do it. */
8575 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
8577 assert (opt_diff
<= UNREACHABLE_MAX_WIDTH
);
8582 local_stretch_amount
8583 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8584 num_widens
, local_opt_diff
);
8585 global_stretch_amount
8586 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8587 num_widens
, opt_diff
);
8588 /* If the condition below is true, then the frag couldn't
8589 stretch the correct amount for the global case, so we just
8590 optimize locally. We'll rely on the subsequent frags to get
8591 the correct alignment in the global case. */
8592 if (global_stretch_amount
< local_stretch_amount
)
8593 stretch_amount
= local_stretch_amount
;
8595 stretch_amount
= global_stretch_amount
;
8597 if (this_frag
->fr_subtype
== RELAX_SLOTS
8598 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8599 assert (stretch_amount
<= 1);
8600 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8602 if (this_frag
->tc_frag_data
.is_no_density
)
8603 assert (stretch_amount
== 3 || stretch_amount
== 0);
8605 assert (stretch_amount
<= 3);
8608 return stretch_amount
;
8612 /* The idea: widen everything you can to get a target or loop aligned,
8613 then start using NOPs.
8615 When we must have a NOP, here is a table of how we decide
8616 (so you don't have to fight through the control flow below):
8618 wide_nops = the number of wide NOPs available for aligning
8619 narrow_nops = the number of narrow NOPs available for aligning
8620 (a subset of wide_nops)
8621 widens = the number of narrow instructions that should be widened
8628 b 0 1 1 (case 3a makes this case unnecessary)
8631 c 0 1 2 (case 4a makes this case unnecessary)
8634 c 0 2 1 (case 5b makes this case unnecessary)
8637 c 0 1 4 (case 6b makes this case unneccesary)
8638 d 1 1 1 (case 6a makes this case unnecessary)
8639 e 0 2 2 (case 6a makes this case unnecessary)
8640 f 0 3 0 (case 6a makes this case unnecessary)
8643 c 1 1 2 (case 7b makes this case unnecessary)
8644 d 0 1 5 (case 7a makes this case unnecessary)
8645 e 0 2 3 (case 7b makes this case unnecessary)
8646 f 0 3 1 (case 7b makes this case unnecessary)
8647 g 1 2 1 (case 7b makes this case unnecessary)
8651 bytes_to_stretch (fragS
*this_frag
,
8657 int bytes_short
= desired_diff
- num_widens
;
8659 assert (desired_diff
>= 0 && desired_diff
< 8);
8660 if (desired_diff
== 0)
8663 assert (wide_nops
> 0 || num_widens
> 0);
8665 /* Always prefer widening to NOP-filling. */
8666 if (bytes_short
< 0)
8668 /* There are enough RELAX_NARROW frags after this one
8669 to align the target without widening this frag in any way. */
8673 if (bytes_short
== 0)
8675 /* Widen every narrow between here and the align target
8676 and the align target will be properly aligned. */
8677 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8683 /* From here we will need at least one NOP to get an alignment.
8684 However, we may not be able to align at all, in which case,
8686 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8688 switch (desired_diff
)
8693 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 1)
8694 return 2; /* case 2 */
8700 return 3; /* case 3a */
8702 if (num_widens
>= 1 && wide_nops
== 1)
8703 return 3; /* case 4a */
8704 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 2)
8705 return 2; /* case 4b */
8708 if (num_widens
>= 2 && wide_nops
== 1)
8709 return 3; /* case 5a */
8710 /* We will need two nops. Are there enough nops
8711 between here and the align target? */
8712 if (wide_nops
< 2 || narrow_nops
== 0)
8714 /* Are there other nops closer that can serve instead? */
8715 if (wide_nops
> 2 && narrow_nops
> 1)
8717 /* Take the density one first, because there might not be
8718 another density one available. */
8719 if (!this_frag
->tc_frag_data
.is_no_density
)
8720 return 2; /* case 5b narrow */
8722 return 3; /* case 5b wide */
8726 return 3; /* case 6a */
8727 else if (num_widens
>= 3 && wide_nops
== 1)
8728 return 3; /* case 6b */
8731 if (wide_nops
== 1 && num_widens
>= 4)
8732 return 3; /* case 7a */
8733 else if (wide_nops
== 2 && num_widens
>= 1)
8734 return 3; /* case 7b */
8742 /* We will need a NOP no matter what, but should we widen
8743 this instruction to help?
8745 This is a RELAX_FRAG_NARROW frag. */
8746 switch (desired_diff
)
8755 if (wide_nops
>= 1 && num_widens
== 1)
8756 return 1; /* case 4a */
8759 if (wide_nops
>= 1 && num_widens
== 2)
8760 return 1; /* case 5a */
8764 return 0; /* case 6a */
8765 else if (wide_nops
>= 1 && num_widens
== 3)
8766 return 1; /* case 6b */
8769 if (wide_nops
>= 1 && num_widens
== 4)
8770 return 1; /* case 7a */
8771 else if (wide_nops
>= 2 && num_widens
== 1)
8772 return 1; /* case 7b */
8785 relax_frag_immed (segT segP
,
8792 bfd_boolean estimate_only
)
8795 vliw_insn orig_vinsn
;
8797 bfd_boolean negatable_branch
= FALSE
;
8798 bfd_boolean branch_jmp_to_next
= FALSE
;
8799 bfd_boolean wide_insn
= FALSE
;
8800 xtensa_isa isa
= xtensa_default_isa
;
8802 offsetT frag_offset
;
8805 int num_text_bytes
, num_literal_bytes
;
8806 int literal_diff
, total_text_diff
, this_text_diff
, first
;
8808 assert (fragP
->fr_opcode
!= NULL
);
8810 xg_init_vinsn (&orig_vinsn
);
8811 vinsn_from_chars (&orig_vinsn
, fragP
->fr_opcode
);
8812 if (xtensa_format_num_slots (isa
, fmt
) > 1)
8815 tinsn
= orig_vinsn
.slots
[slot
];
8816 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
8818 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
))
8821 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
8822 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
8824 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
8826 old_size
= xtensa_format_length (isa
, fmt
);
8828 /* Special case: replace a branch to the next instruction with a NOP.
8829 This is required to work around a hardware bug in T1040.0 and also
8830 serves as an optimization. */
8832 if (branch_jmp_to_next
8833 && ((old_size
== 2) || (old_size
== 3))
8834 && !next_frag_is_loop_target (fragP
))
8837 /* Here is the fun stuff: Get the immediate field from this
8838 instruction. If it fits, we are done. If not, find the next
8839 instruction sequence that fits. */
8841 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
8842 istack_init (&istack
);
8843 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
8844 min_steps
, stretch
);
8845 if (num_steps
< min_steps
)
8847 as_fatal (_("internal error: relaxation failed"));
8851 if (num_steps
> RELAX_IMMED_MAXSTEPS
)
8853 as_fatal (_("internal error: relaxation requires too many steps"));
8857 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
8859 /* Figure out the number of bytes needed. */
8861 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
8863 num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
8865 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
8867 num_text_bytes
= get_num_stack_text_bytes (&istack
);
8870 num_text_bytes
+= old_size
;
8871 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
8872 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
8874 total_text_diff
= num_text_bytes
- old_size
;
8875 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
8877 /* It MUST get larger. If not, we could get an infinite loop. */
8878 assert (num_text_bytes
>= 0);
8879 assert (literal_diff
>= 0);
8880 assert (total_text_diff
>= 0);
8882 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
8883 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
8884 assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
8885 assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
8887 /* Find the associated expandable literal for this. */
8888 if (literal_diff
!= 0)
8890 lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
8893 assert (literal_diff
== 4);
8894 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
8896 /* We expect that the literal section state has NOT been
8898 assert (lit_fragP
->fr_type
== rs_machine_dependent
8899 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
8900 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
8902 /* We need to mark this section for another iteration
8908 if (negatable_branch
&& istack
.ninsn
> 1)
8909 update_next_frag_state (fragP
);
8911 return this_text_diff
;
8915 /* md_convert_frag Hook and Helper Functions. */
8917 static void convert_frag_align_next_opcode (fragS
*);
8918 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
8919 static void convert_frag_fill_nop (fragS
*);
8920 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
8923 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
8925 static xtensa_insnbuf vbuf
= NULL
;
8926 xtensa_isa isa
= xtensa_default_isa
;
8933 as_where (&file_name
, &line
);
8934 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
8936 switch (fragp
->fr_subtype
)
8938 case RELAX_ALIGN_NEXT_OPCODE
:
8939 /* Always convert. */
8940 convert_frag_align_next_opcode (fragp
);
8943 case RELAX_DESIRE_ALIGN
:
8944 /* Do nothing. If not aligned already, too bad. */
8948 case RELAX_LITERAL_FINAL
:
8953 vbuf
= xtensa_insnbuf_alloc (isa
);
8955 xtensa_insnbuf_from_chars
8956 (isa
, vbuf
, (unsigned char *) fragp
->fr_opcode
, 0);
8957 fmt
= xtensa_format_decode (isa
, vbuf
);
8958 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8960 for (slot
= 0; slot
< num_slots
; slot
++)
8962 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
8965 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
8969 case RELAX_IMMED_STEP1
:
8970 case RELAX_IMMED_STEP2
:
8971 /* Place the immediate. */
8974 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8979 /* This is OK because some slots could have
8980 relaxations and others have none. */
8986 case RELAX_UNREACHABLE
:
8987 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
8988 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
8989 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
8993 case RELAX_MAYBE_UNREACHABLE
:
8994 case RELAX_MAYBE_DESIRE_ALIGN
:
8998 case RELAX_FILL_NOP
:
8999 convert_frag_fill_nop (fragp
);
9002 case RELAX_LITERAL_NR
:
9003 if (use_literal_section
)
9005 /* This should have been handled during relaxation. When
9006 relaxing a code segment, literals sometimes need to be
9007 added to the corresponding literal segment. If that
9008 literal segment has already been relaxed, then we end up
9009 in this situation. Marking the literal segments as data
9010 would make this happen less often (since GAS always relaxes
9011 code before data), but we could still get into trouble if
9012 there are instructions in a segment that is not marked as
9013 containing code. Until we can implement a better solution,
9014 cheat and adjust the addresses of all the following frags.
9015 This could break subsequent alignments, but the linker's
9016 literal coalescing will do that anyway. */
9019 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
9020 assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
9021 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
9024 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
9028 as_bad (_("invalid relaxation fragment result"));
9033 new_logical_line (file_name
, line
);
9038 convert_frag_align_next_opcode (fragS
*fragp
)
9040 char *nop_buf
; /* Location for Writing. */
9041 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
9042 addressT aligned_address
;
9046 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
9048 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
9049 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
9050 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
9052 for (nop
= 0; nop
< nop_count
; nop
++)
9055 nop_size
= get_text_align_nth_nop_size (fill_size
, nop
, use_no_density
);
9057 assemble_nop (nop_size
, nop_buf
);
9058 nop_buf
+= nop_size
;
9061 fragp
->fr_fix
+= fill_size
;
9062 fragp
->fr_var
-= fill_size
;
9067 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
9069 TInsn tinsn
, single_target
;
9070 xtensa_format single_fmt
;
9071 int size
, old_size
, diff
;
9072 offsetT frag_offset
;
9075 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
9077 if (xtensa_opcode_is_branch (xtensa_default_isa
, tinsn
.opcode
) == 1)
9079 assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
9080 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
9081 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
9086 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
9088 /* No conversion. */
9093 assert (fragP
->fr_opcode
!= NULL
);
9095 /* Frags in this relaxation state should only contain
9096 single instruction bundles. */
9097 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
9099 /* Just convert it to a wide form.... */
9101 old_size
= xg_get_single_size (tinsn
.opcode
);
9103 tinsn_init (&single_target
);
9104 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9106 if (! xg_is_single_relaxable_insn (&tinsn
, &single_target
, FALSE
))
9108 as_bad (_("unable to widen instruction"));
9112 size
= xg_get_single_size (single_target
.opcode
);
9113 single_fmt
= xg_get_single_format (single_target
.opcode
);
9115 xg_emit_insn_to_buf (&single_target
, single_fmt
, fragP
->fr_opcode
,
9116 fragP
, frag_offset
, TRUE
);
9118 diff
= size
- old_size
;
9120 assert (diff
<= fragP
->fr_var
);
9121 fragP
->fr_var
-= diff
;
9122 fragP
->fr_fix
+= diff
;
9130 convert_frag_fill_nop (fragS
*fragP
)
9132 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
9133 int size
= fragP
->tc_frag_data
.text_expansion
[0];
9134 assert ((unsigned) size
== (fragP
->fr_next
->fr_address
9135 - fragP
->fr_address
- fragP
->fr_fix
));
9138 /* No conversion. */
9142 assemble_nop (size
, loc
);
9143 fragP
->tc_frag_data
.is_insn
= TRUE
;
9144 fragP
->fr_var
-= size
;
9145 fragP
->fr_fix
+= size
;
9150 static fixS
*fix_new_exp_in_seg
9151 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
9152 bfd_reloc_code_real_type
);
9153 static void convert_frag_immed_finish_loop (segT
, fragS
*, TInsn
*);
9156 convert_frag_immed (segT segP
,
9162 char *immed_instr
= fragP
->fr_opcode
;
9164 bfd_boolean expanded
= FALSE
;
9165 bfd_boolean branch_jmp_to_next
= FALSE
;
9166 char *fr_opcode
= fragP
->fr_opcode
;
9167 vliw_insn orig_vinsn
;
9168 xtensa_isa isa
= xtensa_default_isa
;
9169 bfd_boolean wide_insn
= FALSE
;
9171 bfd_boolean is_loop
;
9173 assert (fr_opcode
!= NULL
);
9175 xg_init_vinsn (&orig_vinsn
);
9177 vinsn_from_chars (&orig_vinsn
, fr_opcode
);
9178 if (xtensa_format_num_slots (isa
, fmt
) > 1)
9181 orig_tinsn
= orig_vinsn
.slots
[slot
];
9182 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
9184 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
9186 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9187 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
9189 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
9191 /* Conversion just inserts a NOP and marks the fix as completed. */
9192 bytes
= xtensa_format_length (isa
, fmt
);
9195 orig_vinsn
.slots
[slot
].opcode
=
9196 xtensa_format_slot_nop_opcode (isa
, orig_vinsn
.format
, slot
);
9197 orig_vinsn
.slots
[slot
].ntok
= 0;
9201 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
9202 assert (bytes
== 2 || bytes
== 3);
9203 build_nop (&orig_vinsn
.slots
[0], bytes
);
9204 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
9206 vinsn_to_insnbuf (&orig_vinsn
, fr_opcode
, frag_now
, FALSE
);
9207 xtensa_insnbuf_to_chars
9208 (isa
, orig_vinsn
.insnbuf
, (unsigned char *) fr_opcode
, 0);
9213 /* Here is the fun stuff: Get the immediate field from this
9214 instruction. If it fits, we're done. If not, find the next
9215 instruction sequence that fits. */
9219 symbolS
*lit_sym
= NULL
;
9221 int target_offset
= 0;
9224 symbolS
*gen_label
= NULL
;
9225 offsetT frag_offset
;
9226 bfd_boolean first
= TRUE
;
9227 bfd_boolean last_is_jump
;
9229 /* It does not fit. Find something that does and
9230 convert immediately. */
9231 frag_offset
= fr_opcode
- fragP
->fr_literal
;
9232 istack_init (&istack
);
9233 xg_assembly_relax (&istack
, &orig_tinsn
,
9234 segP
, fragP
, frag_offset
, min_steps
, 0);
9236 old_size
= xtensa_format_length (isa
, fmt
);
9238 /* Assemble this right inline. */
9240 /* First, create the mapping from a label name to the REAL label. */
9242 for (i
= 0; i
< istack
.ninsn
; i
++)
9244 TInsn
*tinsn
= &istack
.insn
[i
];
9247 switch (tinsn
->insn_type
)
9250 if (lit_sym
!= NULL
)
9251 as_bad (_("multiple literals in expansion"));
9252 /* First find the appropriate space in the literal pool. */
9253 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9254 if (lit_frag
== NULL
)
9255 as_bad (_("no registered fragment for literal"));
9256 if (tinsn
->ntok
!= 1)
9257 as_bad (_("number of literal tokens != 1"));
9259 /* Set the literal symbol and add a fixup. */
9260 lit_sym
= lit_frag
->fr_symbol
;
9264 if (align_targets
&& !is_loop
)
9266 fragS
*unreach
= fragP
->fr_next
;
9267 while (!(unreach
->fr_type
== rs_machine_dependent
9268 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9269 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
9271 unreach
= unreach
->fr_next
;
9274 assert (unreach
->fr_type
== rs_machine_dependent
9275 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9276 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
9278 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
9280 assert (gen_label
== NULL
);
9281 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
9282 fr_opcode
- fragP
->fr_literal
9283 + target_offset
, fragP
);
9287 if (first
&& wide_insn
)
9289 target_offset
+= xtensa_format_length (isa
, fmt
);
9291 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9292 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9295 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9302 last_is_jump
= FALSE
;
9303 for (i
= 0; i
< istack
.ninsn
; i
++)
9305 TInsn
*tinsn
= &istack
.insn
[i
];
9309 bfd_reloc_code_real_type reloc_type
;
9311 switch (tinsn
->insn_type
)
9314 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9315 /* Already checked. */
9316 assert (lit_frag
!= NULL
);
9317 assert (lit_sym
!= NULL
);
9318 assert (tinsn
->ntok
== 1);
9320 target_seg
= S_GET_SEGMENT (lit_sym
);
9321 assert (target_seg
);
9322 if (tinsn
->tok
[0].X_op
== O_pltrel
)
9323 reloc_type
= BFD_RELOC_XTENSA_PLT
;
9325 reloc_type
= BFD_RELOC_32
;
9326 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
9327 &tinsn
->tok
[0], FALSE
, reloc_type
);
9334 xg_resolve_labels (tinsn
, gen_label
);
9335 xg_resolve_literals (tinsn
, lit_sym
);
9336 if (wide_insn
&& first
)
9339 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9341 tinsn
->record_fix
= TRUE
;
9342 orig_vinsn
.slots
[slot
] = *tinsn
;
9346 orig_vinsn
.slots
[slot
].opcode
=
9347 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
9348 orig_vinsn
.slots
[slot
].ntok
= 0;
9349 orig_vinsn
.slots
[slot
].record_fix
= FALSE
;
9351 vinsn_to_insnbuf (&orig_vinsn
, immed_instr
, fragP
, TRUE
);
9352 xtensa_insnbuf_to_chars (isa
, orig_vinsn
.insnbuf
,
9353 (unsigned char *) immed_instr
, 0);
9354 fragP
->tc_frag_data
.is_insn
= TRUE
;
9355 size
= xtensa_format_length (isa
, fmt
);
9356 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9358 xtensa_format single_fmt
=
9359 xg_get_single_format (tinsn
->opcode
);
9362 (tinsn
, single_fmt
, immed_instr
+ size
, fragP
,
9363 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
9364 size
+= xg_get_single_size (tinsn
->opcode
);
9369 xtensa_format single_format
;
9370 size
= xg_get_single_size (tinsn
->opcode
);
9371 single_format
= xg_get_single_format (tinsn
->opcode
);
9372 xg_emit_insn_to_buf (tinsn
, single_format
, immed_instr
,
9374 immed_instr
- fragP
->fr_literal
, TRUE
);
9376 immed_instr
+= size
;
9382 diff
= total_size
- old_size
;
9386 assert (diff
<= fragP
->fr_var
);
9387 fragP
->fr_var
-= diff
;
9388 fragP
->fr_fix
+= diff
;
9392 xg_free_vinsn (&orig_vinsn
);
9394 /* Check for undefined immediates in LOOP instructions. */
9398 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
9399 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9401 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9404 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
9405 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9407 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9412 if (expanded
&& xtensa_opcode_is_loop (isa
, orig_tinsn
.opcode
) == 1)
9413 convert_frag_immed_finish_loop (segP
, fragP
, &orig_tinsn
);
9415 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
9417 /* Add an expansion note on the expanded instruction. */
9418 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
9419 &orig_tinsn
.tok
[0], TRUE
,
9420 BFD_RELOC_XTENSA_ASM_EXPAND
);
9425 /* Add a new fix expression into the desired segment. We have to
9426 switch to that segment to do this. */
9429 fix_new_exp_in_seg (segT new_seg
,
9436 bfd_reloc_code_real_type r_type
)
9440 subsegT subseg
= now_subseg
;
9442 assert (new_seg
!= 0);
9443 subseg_set (new_seg
, new_subseg
);
9445 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
9446 subseg_set (seg
, subseg
);
9451 /* Relax a loop instruction so that it can span loop >256 bytes.
9457 addi as, as, lo8 (label-.L1)
9458 addmi as, as, mid8 (label-.L1)
9469 convert_frag_immed_finish_loop (segT segP
, fragS
*fragP
, TInsn
*tinsn
)
9474 unsigned long target
;
9475 static xtensa_insnbuf insnbuf
= NULL
;
9476 unsigned int loop_length
, loop_length_hi
, loop_length_lo
;
9477 xtensa_isa isa
= xtensa_default_isa
;
9478 addressT loop_offset
;
9479 addressT addi_offset
= 9;
9480 addressT addmi_offset
= 12;
9485 insnbuf
= xtensa_insnbuf_alloc (isa
);
9487 /* Get the loop offset. */
9488 loop_offset
= get_expanded_loop_offset (tinsn
->opcode
);
9490 /* Validate that there really is a LOOP at the loop_offset. Because
9491 loops are not bundleable, we can assume that the instruction will be
9493 tinsn_from_chars (&loop_insn
, fragP
->fr_opcode
+ loop_offset
, 0);
9494 tinsn_immed_from_frag (&loop_insn
, fragP
, 0);
9496 assert (xtensa_opcode_is_loop (isa
, loop_insn
.opcode
) == 1);
9497 addi_offset
+= loop_offset
;
9498 addmi_offset
+= loop_offset
;
9500 assert (tinsn
->ntok
== 2);
9501 if (tinsn
->tok
[1].X_op
== O_constant
)
9502 target
= tinsn
->tok
[1].X_add_number
;
9503 else if (tinsn
->tok
[1].X_op
== O_symbol
)
9505 /* Find the fragment. */
9506 symbolS
*sym
= tinsn
->tok
[1].X_add_symbol
;
9507 assert (S_GET_SEGMENT (sym
) == segP
9508 || S_GET_SEGMENT (sym
) == absolute_section
);
9509 target
= (S_GET_VALUE (sym
) + tinsn
->tok
[1].X_add_number
);
9513 as_bad (_("invalid expression evaluation type %d"), tinsn
->tok
[1].X_op
);
9518 know (symbolP
->sy_frag
);
9519 know (!(S_GET_SEGMENT (symbolP
) == absolute_section
)
9520 || symbol_get_frag (symbolP
) == &zero_address_frag
);
9522 loop_length
= target
- (fragP
->fr_address
+ fragP
->fr_fix
);
9523 loop_length_hi
= loop_length
& ~0x0ff;
9524 loop_length_lo
= loop_length
& 0x0ff;
9525 if (loop_length_lo
>= 128)
9527 loop_length_lo
-= 256;
9528 loop_length_hi
+= 256;
9531 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
9532 32512. If the loop is larger than that, then we just fail. */
9533 if (loop_length_hi
> 32512)
9534 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9535 _("loop too long for LOOP instruction"));
9537 tinsn_from_chars (&addi_insn
, fragP
->fr_opcode
+ addi_offset
, 0);
9538 assert (addi_insn
.opcode
== xtensa_addi_opcode
);
9540 tinsn_from_chars (&addmi_insn
, fragP
->fr_opcode
+ addmi_offset
, 0);
9541 assert (addmi_insn
.opcode
== xtensa_addmi_opcode
);
9543 set_expr_const (&addi_insn
.tok
[2], loop_length_lo
);
9544 tinsn_to_insnbuf (&addi_insn
, insnbuf
);
9546 fragP
->tc_frag_data
.is_insn
= TRUE
;
9547 xtensa_insnbuf_to_chars
9548 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addi_offset
, 0);
9550 set_expr_const (&addmi_insn
.tok
[2], loop_length_hi
);
9551 tinsn_to_insnbuf (&addmi_insn
, insnbuf
);
9552 xtensa_insnbuf_to_chars
9553 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addmi_offset
, 0);
9555 /* Walk through all of the frags from here to the loop end
9556 and mark them as no_transform to keep them from being modified
9557 by the linker. If we ever have a relocation for the
9558 addi/addmi of the difference of two symbols we can remove this. */
9561 for (next_fragP
= fragP
; next_fragP
!= NULL
;
9562 next_fragP
= next_fragP
->fr_next
)
9564 next_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
9565 if (next_fragP
->tc_frag_data
.is_loop_target
)
9567 if (target_count
== 2)
9573 /* A map that keeps information on a per-subsegment basis. This is
9574 maintained during initial assembly, but is invalid once the
9575 subsegments are smashed together. I.E., it cannot be used during
9578 typedef struct subseg_map_struct
9586 float total_freq
; /* fall-through + branch target frequency */
9587 float target_freq
; /* branch target frequency alone */
9589 struct subseg_map_struct
*next
;
9593 static subseg_map
*sseg_map
= NULL
;
9596 get_subseg_info (segT seg
, subsegT subseg
)
9598 subseg_map
*subseg_e
;
9600 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
9602 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
9610 add_subseg_info (segT seg
, subsegT subseg
)
9612 subseg_map
*subseg_e
= (subseg_map
*) xmalloc (sizeof (subseg_map
));
9613 memset (subseg_e
, 0, sizeof (subseg_map
));
9614 subseg_e
->seg
= seg
;
9615 subseg_e
->subseg
= subseg
;
9616 subseg_e
->flags
= 0;
9617 /* Start off considering every branch target very important. */
9618 subseg_e
->target_freq
= 1.0;
9619 subseg_e
->total_freq
= 1.0;
9620 subseg_e
->next
= sseg_map
;
9621 sseg_map
= subseg_e
;
9627 get_last_insn_flags (segT seg
, subsegT subseg
)
9629 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9631 return subseg_e
->flags
;
9637 set_last_insn_flags (segT seg
,
9642 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9644 subseg_e
= add_subseg_info (seg
, subseg
);
9646 subseg_e
->flags
|= fl
;
9648 subseg_e
->flags
&= ~fl
;
9653 get_subseg_total_freq (segT seg
, subsegT subseg
)
9655 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9657 return subseg_e
->total_freq
;
9663 get_subseg_target_freq (segT seg
, subsegT subseg
)
9665 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9667 return subseg_e
->target_freq
;
9673 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
9675 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9677 subseg_e
= add_subseg_info (seg
, subseg
);
9678 subseg_e
->total_freq
= total_f
;
9679 subseg_e
->target_freq
= target_f
;
9683 /* Segment Lists and emit_state Stuff. */
9686 xtensa_move_seg_list_to_beginning (seg_list
*head
)
9691 segT literal_section
= head
->seg
;
9693 /* Move the literal section to the front of the section list. */
9694 assert (literal_section
);
9695 if (literal_section
!= stdoutput
->sections
)
9697 bfd_section_list_remove (stdoutput
, literal_section
);
9698 bfd_section_list_prepend (stdoutput
, literal_section
);
9705 static void mark_literal_frags (seg_list
*);
9708 xtensa_move_literals (void)
9711 frchainS
*frchain_from
, *frchain_to
;
9712 fragS
*search_frag
, *next_frag
, *last_frag
, *literal_pool
, *insert_after
;
9713 fragS
**frag_splice
;
9716 fixS
*fix
, *next_fix
, **fix_splice
;
9719 mark_literal_frags (literal_head
->next
);
9720 mark_literal_frags (init_literal_head
->next
);
9721 mark_literal_frags (fini_literal_head
->next
);
9723 if (use_literal_section
)
9726 segment
= literal_head
->next
;
9729 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9730 search_frag
= frchain_from
->frch_root
;
9731 literal_pool
= NULL
;
9733 frag_splice
= &(frchain_from
->frch_root
);
9735 while (!search_frag
->tc_frag_data
.literal_frag
)
9737 assert (search_frag
->fr_fix
== 0
9738 || search_frag
->fr_type
== rs_align
);
9739 search_frag
= search_frag
->fr_next
;
9742 assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
9743 == RELAX_LITERAL_POOL_BEGIN
);
9744 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
9746 /* Make sure that all the frags in this series are closed, and
9747 that there is at least one left over of zero-size. This
9748 prevents us from making a segment with an frchain without any
9750 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9751 xtensa_set_frag_assembly_state (frag_now
);
9752 last_frag
= frag_now
;
9753 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9754 xtensa_set_frag_assembly_state (frag_now
);
9756 while (search_frag
!= frag_now
)
9758 next_frag
= search_frag
->fr_next
;
9760 /* First, move the frag out of the literal section and
9761 to the appropriate place. */
9762 if (search_frag
->tc_frag_data
.literal_frag
)
9764 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
9765 assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
9766 frchain_to
= literal_pool
->tc_frag_data
.lit_frchain
;
9767 assert (frchain_to
);
9769 insert_after
= literal_pool
;
9771 while (insert_after
->fr_next
->fr_subtype
!= RELAX_LITERAL_POOL_END
)
9772 insert_after
= insert_after
->fr_next
;
9774 dest_seg
= insert_after
->fr_next
->tc_frag_data
.lit_seg
;
9776 *frag_splice
= next_frag
;
9777 search_frag
->fr_next
= insert_after
->fr_next
;
9778 insert_after
->fr_next
= search_frag
;
9779 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
9781 /* Now move any fixups associated with this frag to the
9783 fix
= frchain_from
->fix_root
;
9784 fix_splice
= &(frchain_from
->fix_root
);
9787 next_fix
= fix
->fx_next
;
9788 if (fix
->fx_frag
== search_frag
)
9790 *fix_splice
= next_fix
;
9791 fix
->fx_next
= frchain_to
->fix_root
;
9792 frchain_to
->fix_root
= fix
;
9793 if (frchain_to
->fix_tail
== NULL
)
9794 frchain_to
->fix_tail
= fix
;
9797 fix_splice
= &(fix
->fx_next
);
9800 search_frag
= next_frag
;
9803 if (frchain_from
->fix_root
!= NULL
)
9805 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9806 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
9808 assert (frchain_from
->fix_root
== NULL
);
9810 frchain_from
->fix_tail
= NULL
;
9811 xtensa_restore_emit_state (&state
);
9812 segment
= segment
->next
;
9815 /* Now fix up the SEGMENT value for all the literal symbols. */
9816 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
9818 symbolS
*lit_sym
= lit
->sym
;
9819 segT dest_seg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
9821 S_SET_SEGMENT (lit_sym
, dest_seg
);
9826 /* Walk over all the frags for segments in a list and mark them as
9827 containing literals. As clunky as this is, we can't rely on frag_var
9828 and frag_variant to get called in all situations. */
9831 mark_literal_frags (seg_list
*segment
)
9833 frchainS
*frchain_from
;
9838 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9839 search_frag
= frchain_from
->frch_root
;
9842 search_frag
->tc_frag_data
.is_literal
= TRUE
;
9843 search_frag
= search_frag
->fr_next
;
9845 segment
= segment
->next
;
9851 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
9853 /* Move all of the sections in the section list to come
9854 after "after" in the gnu segment list. */
9859 segT literal_section
= head
->seg
;
9861 /* Move the literal section after "after". */
9862 assert (literal_section
);
9863 if (literal_section
!= after
)
9865 bfd_section_list_remove (stdoutput
, literal_section
);
9866 bfd_section_list_insert_after (stdoutput
, after
, literal_section
);
9874 /* Push all the literal segments to the end of the gnu list. */
9877 xtensa_reorder_segments (void)
9884 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
9890 /* Now that we have the last section, push all the literal
9891 sections to the end. */
9892 xtensa_reorder_seg_list (literal_head
, last_sec
);
9893 xtensa_reorder_seg_list (init_literal_head
, last_sec
);
9894 xtensa_reorder_seg_list (fini_literal_head
, last_sec
);
9896 /* Now perform the final error check. */
9897 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
9899 assert (new_count
== old_count
);
9903 /* Change the emit state (seg, subseg, and frag related stuff) to the
9904 correct location. Return a emit_state which can be passed to
9905 xtensa_restore_emit_state to return to current fragment. */
9908 xtensa_switch_to_literal_fragment (emit_state
*result
)
9910 if (directive_state
[directive_absolute_literals
])
9912 cache_literal_section (0, default_lit_sections
.lit4_seg_name
,
9913 &default_lit_sections
.lit4_seg
, FALSE
);
9914 xtensa_switch_section_emit_state (result
,
9915 default_lit_sections
.lit4_seg
, 0);
9918 xtensa_switch_to_non_abs_literal_fragment (result
);
9920 /* Do a 4-byte align here. */
9921 frag_align (2, 0, 0);
9922 record_alignment (now_seg
, 2);
9927 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
9929 /* When we mark a literal pool location, we want to put a frag in
9930 the literal pool that points to it. But to do that, we want to
9931 switch_to_literal_fragment. But literal sections don't have
9932 literal pools, so their location is always null, so we would
9933 recurse forever. This is kind of hacky, but it works. */
9935 static bfd_boolean recursive
= FALSE
;
9936 fragS
*pool_location
= get_literal_pool_location (now_seg
);
9937 bfd_boolean is_init
=
9938 (now_seg
&& !strcmp (segment_name (now_seg
), INIT_SECTION_NAME
));
9940 bfd_boolean is_fini
=
9941 (now_seg
&& !strcmp (segment_name (now_seg
), FINI_SECTION_NAME
));
9943 if (pool_location
== NULL
9944 && !use_literal_section
9946 && !is_init
&& ! is_fini
)
9948 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
9950 xtensa_mark_literal_pool_location ();
9954 /* Special case: If we are in the ".fini" or ".init" section, then
9955 we will ALWAYS be generating to the ".fini.literal" and
9956 ".init.literal" sections. */
9960 cache_literal_section (init_literal_head
,
9961 default_lit_sections
.init_lit_seg_name
,
9962 &default_lit_sections
.init_lit_seg
, TRUE
);
9963 xtensa_switch_section_emit_state (result
,
9964 default_lit_sections
.init_lit_seg
, 0);
9968 cache_literal_section (fini_literal_head
,
9969 default_lit_sections
.fini_lit_seg_name
,
9970 &default_lit_sections
.fini_lit_seg
, TRUE
);
9971 xtensa_switch_section_emit_state (result
,
9972 default_lit_sections
.fini_lit_seg
, 0);
9976 cache_literal_section (literal_head
,
9977 default_lit_sections
.lit_seg_name
,
9978 &default_lit_sections
.lit_seg
, TRUE
);
9979 xtensa_switch_section_emit_state (result
,
9980 default_lit_sections
.lit_seg
, 0);
9983 if (!use_literal_section
9984 && !is_init
&& !is_fini
9985 && get_literal_pool_location (now_seg
) != pool_location
)
9987 /* Close whatever frag is there. */
9988 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9989 xtensa_set_frag_assembly_state (frag_now
);
9990 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
9991 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9992 xtensa_set_frag_assembly_state (frag_now
);
9997 /* Call this function before emitting data into the literal section.
9998 This is a helper function for xtensa_switch_to_literal_fragment.
9999 This is similar to a .section new_now_seg subseg. */
10002 xtensa_switch_section_emit_state (emit_state
*state
,
10004 subsegT new_now_subseg
)
10006 state
->name
= now_seg
->name
;
10007 state
->now_seg
= now_seg
;
10008 state
->now_subseg
= now_subseg
;
10009 state
->generating_literals
= generating_literals
;
10010 generating_literals
++;
10011 subseg_set (new_now_seg
, new_now_subseg
);
10015 /* Use to restore the emitting into the normal place. */
10018 xtensa_restore_emit_state (emit_state
*state
)
10020 generating_literals
= state
->generating_literals
;
10021 subseg_set (state
->now_seg
, state
->now_subseg
);
10025 /* Get a segment of a given name. If the segment is already
10026 present, return it; otherwise, create a new one. */
10029 cache_literal_section (seg_list
*head
,
10032 bfd_boolean is_code
)
10034 segT current_section
= now_seg
;
10035 int current_subsec
= now_subseg
;
10041 /* Check if the named section exists. */
10042 for (seg
= stdoutput
->sections
; seg
; seg
= seg
->next
)
10044 if (!strcmp (segment_name (seg
), name
))
10050 /* Create a new literal section. */
10051 seg
= subseg_new (name
, (subsegT
) 0);
10054 /* Add the newly created literal segment to the specified list. */
10055 seg_list
*n
= (seg_list
*) xmalloc (sizeof (seg_list
));
10057 n
->next
= head
->next
;
10060 bfd_set_section_flags (stdoutput
, seg
, SEC_HAS_CONTENTS
|
10061 SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
10062 | (is_code
? SEC_CODE
: SEC_DATA
));
10063 bfd_set_section_alignment (stdoutput
, seg
, 2);
10067 subseg_set (current_section
, current_subsec
);
10071 /* Property Tables Stuff. */
10073 #define XTENSA_INSN_SEC_NAME ".xt.insn"
10074 #define XTENSA_LIT_SEC_NAME ".xt.lit"
10075 #define XTENSA_PROP_SEC_NAME ".xt.prop"
10077 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
10078 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
10080 static bfd_boolean
get_frag_is_literal (const fragS
*);
10081 static void xtensa_create_property_segments
10082 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
10083 static void xtensa_create_xproperty_segments
10084 (frag_flags_fn
, const char *, xt_section_type
);
10085 static segment_info_type
*retrieve_segment_info (segT
);
10086 static segT
retrieve_xtensa_section (char *);
10087 static bfd_boolean
section_has_property (segT
, frag_predicate
);
10088 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
10089 static void add_xt_block_frags
10090 (segT
, segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
10091 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
10092 static void xtensa_frag_flags_init (frag_flags
*);
10093 static void get_frag_property_flags (const fragS
*, frag_flags
*);
10094 static bfd_vma
frag_flags_to_number (const frag_flags
*);
10095 static void add_xt_prop_frags
10096 (segT
, segT
, xtensa_block_info
**, frag_flags_fn
);
10098 /* Set up property tables after relaxation. */
10101 xtensa_post_relax_hook (void)
10103 xtensa_move_seg_list_to_beginning (literal_head
);
10104 xtensa_move_seg_list_to_beginning (init_literal_head
);
10105 xtensa_move_seg_list_to_beginning (fini_literal_head
);
10107 xtensa_find_unmarked_state_frags ();
10109 if (use_literal_section
)
10110 xtensa_create_property_segments (get_frag_is_literal
,
10112 XTENSA_LIT_SEC_NAME
,
10114 xtensa_create_xproperty_segments (get_frag_property_flags
,
10115 XTENSA_PROP_SEC_NAME
,
10118 if (warn_unaligned_branch_targets
)
10119 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
10120 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
10124 /* This function is only meaningful after xtensa_move_literals. */
10127 get_frag_is_literal (const fragS
*fragP
)
10129 assert (fragP
!= NULL
);
10130 return fragP
->tc_frag_data
.is_literal
;
10135 xtensa_create_property_segments (frag_predicate property_function
,
10136 frag_predicate end_property_function
,
10137 const char *section_name_base
,
10138 xt_section_type sec_type
)
10142 /* Walk over all of the current segments.
10143 Walk over each fragment
10144 For each non-empty fragment,
10145 Build a property record (append where possible). */
10147 for (seclist
= &stdoutput
->sections
;
10148 seclist
&& *seclist
;
10149 seclist
= &(*seclist
)->next
)
10151 segT sec
= *seclist
;
10154 flags
= bfd_get_section_flags (stdoutput
, sec
);
10155 if (flags
& SEC_DEBUGGING
)
10157 if (!(flags
& SEC_ALLOC
))
10160 if (section_has_property (sec
, property_function
))
10162 char *property_section_name
=
10163 xtensa_get_property_section_name (sec
, section_name_base
);
10164 segT insn_sec
= retrieve_xtensa_section (property_section_name
);
10165 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10166 xtensa_block_info
**xt_blocks
=
10167 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10168 /* Walk over all of the frchains here and add new sections. */
10169 add_xt_block_frags (sec
, insn_sec
, xt_blocks
, property_function
,
10170 end_property_function
);
10174 /* Now we fill them out.... */
10176 for (seclist
= &stdoutput
->sections
;
10177 seclist
&& *seclist
;
10178 seclist
= &(*seclist
)->next
)
10180 segment_info_type
*seginfo
;
10181 xtensa_block_info
*block
;
10182 segT sec
= *seclist
;
10184 seginfo
= seg_info (sec
);
10185 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10189 xtensa_block_info
*cur_block
;
10190 /* This is a section with some data. */
10192 bfd_size_type rec_size
;
10194 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10197 rec_size
= num_recs
* 8;
10198 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10200 /* In order to make this work with the assembler, we have to
10201 build some frags and then build the "fixups" for it. It
10202 would be easier to just set the contents then set the
10207 /* Allocate a fragment and leak it. */
10209 bfd_size_type frag_size
;
10211 frchainS
*frchainP
;
10215 frag_size
= sizeof (fragS
) + rec_size
;
10216 fragP
= (fragS
*) xmalloc (frag_size
);
10218 memset (fragP
, 0, frag_size
);
10219 fragP
->fr_address
= 0;
10220 fragP
->fr_next
= NULL
;
10221 fragP
->fr_fix
= rec_size
;
10223 fragP
->fr_type
= rs_fill
;
10224 /* The rest are zeros. */
10226 frchainP
= seginfo
->frchainP
;
10227 frchainP
->frch_root
= fragP
;
10228 frchainP
->frch_last
= fragP
;
10230 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10231 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10233 seginfo
->fix_root
= fixes
;
10234 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10236 frag_data
= &fragP
->fr_literal
[0];
10237 for (i
= 0; i
< num_recs
; i
++)
10239 fixS
*fix
= &fixes
[i
];
10240 assert (cur_block
);
10242 /* Write the fixup. */
10243 if (i
!= num_recs
- 1)
10244 fix
->fx_next
= &fixes
[i
+ 1];
10246 fix
->fx_next
= NULL
;
10249 fix
->fx_frag
= fragP
;
10250 fix
->fx_where
= i
* 8;
10251 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10252 fix
->fx_offset
= cur_block
->offset
;
10253 fix
->fx_r_type
= BFD_RELOC_32
;
10254 fix
->fx_file
= "Internal Assembly";
10257 /* Write the length. */
10258 md_number_to_chars (&frag_data
[4 + 8 * i
],
10259 cur_block
->size
, 4);
10260 cur_block
= cur_block
->next
;
10269 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
10270 const char *section_name_base
,
10271 xt_section_type sec_type
)
10275 /* Walk over all of the current segments.
10276 Walk over each fragment.
10277 For each fragment that has instructions,
10278 build an instruction record (append where possible). */
10280 for (seclist
= &stdoutput
->sections
;
10281 seclist
&& *seclist
;
10282 seclist
= &(*seclist
)->next
)
10284 segT sec
= *seclist
;
10287 flags
= bfd_get_section_flags (stdoutput
, sec
);
10288 if ((flags
& SEC_DEBUGGING
)
10289 || !(flags
& SEC_ALLOC
)
10290 || (flags
& SEC_MERGE
))
10293 if (section_has_xproperty (sec
, flag_fn
))
10295 char *property_section_name
=
10296 xtensa_get_property_section_name (sec
, section_name_base
);
10297 segT insn_sec
= retrieve_xtensa_section (property_section_name
);
10298 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10299 xtensa_block_info
**xt_blocks
=
10300 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10301 /* Walk over all of the frchains here and add new sections. */
10302 add_xt_prop_frags (sec
, insn_sec
, xt_blocks
, flag_fn
);
10306 /* Now we fill them out.... */
10308 for (seclist
= &stdoutput
->sections
;
10309 seclist
&& *seclist
;
10310 seclist
= &(*seclist
)->next
)
10312 segment_info_type
*seginfo
;
10313 xtensa_block_info
*block
;
10314 segT sec
= *seclist
;
10316 seginfo
= seg_info (sec
);
10317 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10321 xtensa_block_info
*cur_block
;
10322 /* This is a section with some data. */
10324 bfd_size_type rec_size
;
10326 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10329 rec_size
= num_recs
* (8 + 4);
10330 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10332 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
10334 /* In order to make this work with the assembler, we have to build
10335 some frags then build the "fixups" for it. It would be easier to
10336 just set the contents then set the arlents. */
10340 /* Allocate a fragment and (unfortunately) leak it. */
10342 bfd_size_type frag_size
;
10344 frchainS
*frchainP
;
10348 frag_size
= sizeof (fragS
) + rec_size
;
10349 fragP
= (fragS
*) xmalloc (frag_size
);
10351 memset (fragP
, 0, frag_size
);
10352 fragP
->fr_address
= 0;
10353 fragP
->fr_next
= NULL
;
10354 fragP
->fr_fix
= rec_size
;
10356 fragP
->fr_type
= rs_fill
;
10357 /* The rest are zeros. */
10359 frchainP
= seginfo
->frchainP
;
10360 frchainP
->frch_root
= fragP
;
10361 frchainP
->frch_last
= fragP
;
10363 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10364 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10366 seginfo
->fix_root
= fixes
;
10367 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10369 frag_data
= &fragP
->fr_literal
[0];
10370 for (i
= 0; i
< num_recs
; i
++)
10372 fixS
*fix
= &fixes
[i
];
10373 assert (cur_block
);
10375 /* Write the fixup. */
10376 if (i
!= num_recs
- 1)
10377 fix
->fx_next
= &fixes
[i
+ 1];
10379 fix
->fx_next
= NULL
;
10382 fix
->fx_frag
= fragP
;
10383 fix
->fx_where
= i
* (8 + 4);
10384 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10385 fix
->fx_offset
= cur_block
->offset
;
10386 fix
->fx_r_type
= BFD_RELOC_32
;
10387 fix
->fx_file
= "Internal Assembly";
10390 /* Write the length. */
10391 md_number_to_chars (&frag_data
[4 + (8+4) * i
],
10392 cur_block
->size
, 4);
10393 md_number_to_chars (&frag_data
[8 + (8+4) * i
],
10394 frag_flags_to_number (&cur_block
->flags
),
10396 cur_block
= cur_block
->next
;
10404 static segment_info_type
*
10405 retrieve_segment_info (segT seg
)
10407 segment_info_type
*seginfo
;
10408 seginfo
= (segment_info_type
*) bfd_get_section_userdata (stdoutput
, seg
);
10411 frchainS
*frchainP
;
10413 seginfo
= (segment_info_type
*) xmalloc (sizeof (*seginfo
));
10414 memset ((void *) seginfo
, 0, sizeof (*seginfo
));
10415 seginfo
->fix_root
= NULL
;
10416 seginfo
->fix_tail
= NULL
;
10417 seginfo
->bfd_section
= seg
;
10419 /* We will not be dealing with these, only our special ones. */
10420 bfd_set_section_userdata (stdoutput
, seg
, (void *) seginfo
);
10422 frchainP
= (frchainS
*) xmalloc (sizeof (frchainS
));
10423 frchainP
->frch_root
= NULL
;
10424 frchainP
->frch_last
= NULL
;
10425 frchainP
->frch_next
= NULL
;
10426 frchainP
->frch_seg
= seg
;
10427 frchainP
->frch_subseg
= 0;
10428 frchainP
->fix_root
= NULL
;
10429 frchainP
->fix_tail
= NULL
;
10430 /* Do not init the objstack. */
10431 /* obstack_begin (&frchainP->frch_obstack, chunksize); */
10432 /* frchainP->frch_frag_now = fragP; */
10433 frchainP
->frch_frag_now
= NULL
;
10435 seginfo
->frchainP
= frchainP
;
10443 retrieve_xtensa_section (char *sec_name
)
10445 bfd
*abfd
= stdoutput
;
10446 flagword flags
, out_flags
, link_once_flags
;
10449 flags
= bfd_get_section_flags (abfd
, now_seg
);
10450 link_once_flags
= (flags
& SEC_LINK_ONCE
);
10451 if (link_once_flags
)
10452 link_once_flags
|= (flags
& SEC_LINK_DUPLICATES
);
10453 out_flags
= (SEC_RELOC
| SEC_HAS_CONTENTS
| SEC_READONLY
| link_once_flags
);
10455 s
= bfd_make_section_old_way (abfd
, sec_name
);
10457 as_bad (_("could not create section %s"), sec_name
);
10458 if (!bfd_set_section_flags (abfd
, s
, out_flags
))
10459 as_bad (_("invalid flag combination on section %s"), sec_name
);
10466 section_has_property (segT sec
, frag_predicate property_function
)
10468 segment_info_type
*seginfo
= seg_info (sec
);
10471 if (seginfo
&& seginfo
->frchainP
)
10473 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10475 if (property_function (fragP
)
10476 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10485 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
10487 segment_info_type
*seginfo
= seg_info (sec
);
10490 if (seginfo
&& seginfo
->frchainP
)
10492 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10494 frag_flags prop_flags
;
10495 property_function (fragP
, &prop_flags
);
10496 if (!xtensa_frag_flags_is_empty (&prop_flags
))
10504 /* Two types of block sections exist right now: literal and insns. */
10507 add_xt_block_frags (segT sec
,
10509 xtensa_block_info
**xt_block
,
10510 frag_predicate property_function
,
10511 frag_predicate end_property_function
)
10513 segment_info_type
*seg_info
;
10514 segment_info_type
*xt_seg_info
;
10515 bfd_vma seg_offset
;
10518 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
10519 seg_info
= retrieve_segment_info (sec
);
10521 /* Build it if needed. */
10522 while (*xt_block
!= NULL
)
10523 xt_block
= &(*xt_block
)->next
;
10524 /* We are either at NULL at the beginning or at the end. */
10526 /* Walk through the frags. */
10529 if (seg_info
->frchainP
)
10531 for (fragP
= seg_info
->frchainP
->frch_root
;
10533 fragP
= fragP
->fr_next
)
10535 if (property_function (fragP
)
10536 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10538 if (*xt_block
!= NULL
)
10540 if ((*xt_block
)->offset
+ (*xt_block
)->size
10541 == fragP
->fr_address
)
10542 (*xt_block
)->size
+= fragP
->fr_fix
;
10544 xt_block
= &((*xt_block
)->next
);
10546 if (*xt_block
== NULL
)
10548 xtensa_block_info
*new_block
= (xtensa_block_info
*)
10549 xmalloc (sizeof (xtensa_block_info
));
10550 new_block
->sec
= sec
;
10551 new_block
->offset
= fragP
->fr_address
;
10552 new_block
->size
= fragP
->fr_fix
;
10553 new_block
->next
= NULL
;
10554 xtensa_frag_flags_init (&new_block
->flags
);
10555 *xt_block
= new_block
;
10557 if (end_property_function
10558 && end_property_function (fragP
))
10560 xt_block
= &((*xt_block
)->next
);
10568 /* Break the encapsulation of add_xt_prop_frags here. */
10571 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
10573 if (prop_flags
->is_literal
10574 || prop_flags
->is_insn
10575 || prop_flags
->is_data
10576 || prop_flags
->is_unreachable
)
10583 xtensa_frag_flags_init (frag_flags
*prop_flags
)
10585 memset (prop_flags
, 0, sizeof (frag_flags
));
10590 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
10592 xtensa_frag_flags_init (prop_flags
);
10593 if (fragP
->tc_frag_data
.is_literal
)
10594 prop_flags
->is_literal
= TRUE
;
10595 if (fragP
->tc_frag_data
.is_unreachable
)
10596 prop_flags
->is_unreachable
= TRUE
;
10597 else if (fragP
->tc_frag_data
.is_insn
)
10599 prop_flags
->is_insn
= TRUE
;
10600 if (fragP
->tc_frag_data
.is_loop_target
)
10601 prop_flags
->insn
.is_loop_target
= TRUE
;
10602 if (fragP
->tc_frag_data
.is_branch_target
)
10603 prop_flags
->insn
.is_branch_target
= TRUE
;
10604 if (fragP
->tc_frag_data
.is_specific_opcode
10605 || fragP
->tc_frag_data
.is_no_transform
)
10606 prop_flags
->insn
.is_no_transform
= TRUE
;
10607 if (fragP
->tc_frag_data
.is_no_density
)
10608 prop_flags
->insn
.is_no_density
= TRUE
;
10609 if (fragP
->tc_frag_data
.use_absolute_literals
)
10610 prop_flags
->insn
.is_abslit
= TRUE
;
10612 if (fragP
->tc_frag_data
.is_align
)
10614 prop_flags
->is_align
= TRUE
;
10615 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
10616 if (xtensa_frag_flags_is_empty (prop_flags
))
10617 prop_flags
->is_data
= TRUE
;
10623 frag_flags_to_number (const frag_flags
*prop_flags
)
10626 if (prop_flags
->is_literal
)
10627 num
|= XTENSA_PROP_LITERAL
;
10628 if (prop_flags
->is_insn
)
10629 num
|= XTENSA_PROP_INSN
;
10630 if (prop_flags
->is_data
)
10631 num
|= XTENSA_PROP_DATA
;
10632 if (prop_flags
->is_unreachable
)
10633 num
|= XTENSA_PROP_UNREACHABLE
;
10634 if (prop_flags
->insn
.is_loop_target
)
10635 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
10636 if (prop_flags
->insn
.is_branch_target
)
10638 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
10639 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
10642 if (prop_flags
->insn
.is_no_density
)
10643 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
10644 if (prop_flags
->insn
.is_no_transform
)
10645 num
|= XTENSA_PROP_INSN_NO_TRANSFORM
;
10646 if (prop_flags
->insn
.is_no_reorder
)
10647 num
|= XTENSA_PROP_INSN_NO_REORDER
;
10648 if (prop_flags
->insn
.is_abslit
)
10649 num
|= XTENSA_PROP_INSN_ABSLIT
;
10651 if (prop_flags
->is_align
)
10653 num
|= XTENSA_PROP_ALIGN
;
10654 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
10662 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
10663 const frag_flags
*prop_flags_2
)
10665 /* Cannot combine with an end marker. */
10667 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
10669 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
10671 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
10674 if (prop_flags_1
->is_insn
)
10676 /* Properties of the beginning of the frag. */
10677 if (prop_flags_2
->insn
.is_loop_target
)
10679 if (prop_flags_2
->insn
.is_branch_target
)
10681 if (prop_flags_1
->insn
.is_no_density
!=
10682 prop_flags_2
->insn
.is_no_density
)
10684 if (prop_flags_1
->insn
.is_no_transform
!=
10685 prop_flags_2
->insn
.is_no_transform
)
10687 if (prop_flags_1
->insn
.is_no_reorder
!=
10688 prop_flags_2
->insn
.is_no_reorder
)
10690 if (prop_flags_1
->insn
.is_abslit
!=
10691 prop_flags_2
->insn
.is_abslit
)
10695 if (prop_flags_1
->is_align
)
10703 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
10706 unsigned align_bits
;
10708 if (!xt_block
->flags
.is_align
)
10709 return xt_block
->size
;
10711 end_addr
= xt_block
->offset
+ xt_block
->size
;
10712 align_bits
= xt_block
->flags
.alignment
;
10713 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
10714 return end_addr
- xt_block
->offset
;
10719 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
10720 const xtensa_block_info
*xt_block_2
)
10722 if (xt_block
->sec
!= xt_block_2
->sec
)
10724 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
10725 != xt_block_2
->offset
)
10728 if (xt_block_2
->size
== 0
10729 && (!xt_block_2
->flags
.is_unreachable
10730 || xt_block
->flags
.is_unreachable
))
10732 if (xt_block_2
->flags
.is_align
10733 && xt_block
->flags
.is_align
)
10735 /* Nothing needed. */
10736 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
10741 if (xt_block_2
->flags
.is_align
)
10743 /* Push alignment to previous entry. */
10744 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
10745 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10750 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
10751 &xt_block_2
->flags
))
10754 xt_block
->size
+= xt_block_2
->size
;
10756 if (xt_block_2
->flags
.is_align
)
10758 xt_block
->flags
.is_align
= TRUE
;
10759 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10767 add_xt_prop_frags (segT sec
,
10769 xtensa_block_info
**xt_block
,
10770 frag_flags_fn property_function
)
10772 segment_info_type
*seg_info
;
10773 segment_info_type
*xt_seg_info
;
10774 bfd_vma seg_offset
;
10777 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
10778 seg_info
= retrieve_segment_info (sec
);
10779 /* Build it if needed. */
10780 while (*xt_block
!= NULL
)
10782 xt_block
= &(*xt_block
)->next
;
10784 /* We are either at NULL at the beginning or at the end. */
10786 /* Walk through the frags. */
10789 if (seg_info
->frchainP
)
10791 for (fragP
= seg_info
->frchainP
->frch_root
; fragP
;
10792 fragP
= fragP
->fr_next
)
10794 xtensa_block_info tmp_block
;
10795 tmp_block
.sec
= sec
;
10796 tmp_block
.offset
= fragP
->fr_address
;
10797 tmp_block
.size
= fragP
->fr_fix
;
10798 tmp_block
.next
= NULL
;
10799 property_function (fragP
, &tmp_block
.flags
);
10801 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
10802 /* && fragP->fr_fix != 0) */
10804 if ((*xt_block
) == NULL
10805 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
10807 xtensa_block_info
*new_block
;
10808 if ((*xt_block
) != NULL
)
10809 xt_block
= &(*xt_block
)->next
;
10810 new_block
= (xtensa_block_info
*)
10811 xmalloc (sizeof (xtensa_block_info
));
10812 *new_block
= tmp_block
;
10813 *xt_block
= new_block
;
10821 /* op_placement_info_table */
10823 /* op_placement_info makes it easier to determine which
10824 ops can go in which slots. */
10827 init_op_placement_info_table (void)
10829 xtensa_isa isa
= xtensa_default_isa
;
10830 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
10831 xtensa_opcode opcode
;
10834 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
10836 op_placement_table
= (op_placement_info_table
)
10837 xmalloc (sizeof (op_placement_info
) * num_opcodes
);
10838 assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
10840 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
10842 op_placement_info
*opi
= &op_placement_table
[opcode
];
10843 /* FIXME: Make tinsn allocation dynamic. */
10844 if (xtensa_opcode_num_operands (isa
, opcode
) >= MAX_INSN_ARGS
)
10845 as_fatal (_("too many operands in instruction"));
10846 opi
->single
= XTENSA_UNDEFINED
;
10847 opi
->single_size
= 0;
10848 opi
->widest
= XTENSA_UNDEFINED
;
10849 opi
->widest_size
= 0;
10850 opi
->narrowest
= XTENSA_UNDEFINED
;
10851 opi
->narrowest_size
= 0x7F;
10853 opi
->num_formats
= 0;
10855 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
10857 opi
->slots
[fmt
] = 0;
10858 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
10860 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
10862 int fmt_length
= xtensa_format_length (isa
, fmt
);
10864 set_bit (fmt
, opi
->formats
);
10865 set_bit (slot
, opi
->slots
[fmt
]);
10866 /* opi->slot_count[fmt]++; */
10867 if (fmt_length
< opi
->narrowest_size
)
10869 opi
->narrowest
= fmt
;
10870 opi
->narrowest_size
= fmt_length
;
10872 if (fmt_length
> opi
->widest_size
)
10875 opi
->widest_size
= fmt_length
;
10877 if (xtensa_format_num_slots (isa
, fmt
) == 1)
10879 if (opi
->single_size
== 0
10880 || fmt_length
< opi
->single_size
)
10883 opi
->single_size
= fmt_length
;
10889 opi
->num_formats
++;
10892 xtensa_insnbuf_free (isa
, ibuf
);
10897 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
10899 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
10903 /* If the opcode is available in a single slot format, return its size. */
10906 xg_get_single_size (xtensa_opcode opcode
)
10908 assert (op_placement_table
[opcode
].single
!= XTENSA_UNDEFINED
);
10909 return op_placement_table
[opcode
].single_size
;
10913 static xtensa_format
10914 xg_get_single_format (xtensa_opcode opcode
)
10916 return op_placement_table
[opcode
].single
;
10920 /* Instruction Stack Functions (from "xtensa-istack.h"). */
10923 istack_init (IStack
*stack
)
10925 memset (stack
, 0, sizeof (IStack
));
10931 istack_empty (IStack
*stack
)
10933 return (stack
->ninsn
== 0);
10938 istack_full (IStack
*stack
)
10940 return (stack
->ninsn
== MAX_ISTACK
);
10944 /* Return a pointer to the top IStack entry.
10945 It is an error to call this if istack_empty () is TRUE. */
10948 istack_top (IStack
*stack
)
10950 int rec
= stack
->ninsn
- 1;
10951 assert (!istack_empty (stack
));
10952 return &stack
->insn
[rec
];
10956 /* Add a new TInsn to an IStack.
10957 It is an error to call this if istack_full () is TRUE. */
10960 istack_push (IStack
*stack
, TInsn
*insn
)
10962 int rec
= stack
->ninsn
;
10963 assert (!istack_full (stack
));
10964 stack
->insn
[rec
] = *insn
;
10969 /* Clear space for the next TInsn on the IStack and return a pointer
10970 to it. It is an error to call this if istack_full () is TRUE. */
10973 istack_push_space (IStack
*stack
)
10975 int rec
= stack
->ninsn
;
10977 assert (!istack_full (stack
));
10978 insn
= &stack
->insn
[rec
];
10979 memset (insn
, 0, sizeof (TInsn
));
10985 /* Remove the last pushed instruction. It is an error to call this if
10986 istack_empty () returns TRUE. */
10989 istack_pop (IStack
*stack
)
10991 int rec
= stack
->ninsn
- 1;
10992 assert (!istack_empty (stack
));
10994 memset (&stack
->insn
[rec
], 0, sizeof (TInsn
));
10998 /* TInsn functions. */
11001 tinsn_init (TInsn
*dst
)
11003 memset (dst
, 0, sizeof (TInsn
));
11007 /* Get the ``num''th token of the TInsn.
11008 It is illegal to call this if num > insn->ntoks. */
11011 tinsn_get_tok (TInsn
*insn
, int num
)
11013 assert (num
< insn
->ntok
);
11014 return &insn
->tok
[num
];
11018 /* Return TRUE if ANY of the operands in the insn are symbolic. */
11021 tinsn_has_symbolic_operands (const TInsn
*insn
)
11024 int n
= insn
->ntok
;
11026 assert (insn
->insn_type
== ITYPE_INSN
);
11028 for (i
= 0; i
< n
; ++i
)
11030 switch (insn
->tok
[i
].X_op
)
11044 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
11046 xtensa_isa isa
= xtensa_default_isa
;
11048 int n
= insn
->ntok
;
11050 assert (insn
->insn_type
== ITYPE_INSN
);
11052 for (i
= 0; i
< n
; ++i
)
11054 switch (insn
->tok
[i
].X_op
)
11062 /* Errors for these types are caught later. */
11067 /* Symbolic immediates are only allowed on the last immediate
11068 operand. At this time, CONST16 is the only opcode where we
11069 support non-PC-relative relocations. (It isn't necessary
11070 to complain about non-PC-relative relocations here, but
11071 otherwise, no error is reported until the relocations are
11072 generated, and the assembler won't get that far if there
11073 are any other errors. It's nice to see all the problems
11075 if (i
!= get_relaxable_immed (insn
->opcode
)
11076 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
11077 && insn
->opcode
!= xtensa_const16_opcode
))
11079 as_bad (_("invalid symbolic operand %d on '%s'"),
11080 i
, xtensa_opcode_name (isa
, insn
->opcode
));
11089 /* For assembly code with complex expressions (e.g. subtraction),
11090 we have to build them in the literal pool so that
11091 their results are calculated correctly after relaxation.
11092 The relaxation only handles expressions that
11093 boil down to SYMBOL + OFFSET. */
11096 tinsn_has_complex_operands (const TInsn
*insn
)
11099 int n
= insn
->ntok
;
11100 assert (insn
->insn_type
== ITYPE_INSN
);
11101 for (i
= 0; i
< n
; ++i
)
11103 switch (insn
->tok
[i
].X_op
)
11119 /* Convert the constant operands in the tinsn to insnbuf.
11120 Return TRUE if there is a symbol in the immediate field.
11122 Before this is called,
11123 1) the number of operands are correct
11124 2) the tinsn is a ITYPE_INSN
11125 3) ONLY the relaxable_ is built
11126 4) All operands are O_constant, O_symbol. All constants fit
11127 The return value tells whether there are any remaining O_symbols. */
11130 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
11132 static xtensa_insnbuf slotbuf
= 0;
11133 xtensa_isa isa
= xtensa_default_isa
;
11134 xtensa_opcode opcode
= tinsn
->opcode
;
11135 xtensa_format fmt
= xg_get_single_format (opcode
);
11136 bfd_boolean has_fixup
= FALSE
;
11137 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11144 slotbuf
= xtensa_insnbuf_alloc (isa
);
11146 assert (tinsn
->insn_type
== ITYPE_INSN
);
11147 if (noperands
!= tinsn
->ntok
)
11148 as_fatal (_("operand number mismatch"));
11150 if (xtensa_opcode_encode (isa
, fmt
, 0, slotbuf
, opcode
))
11151 as_fatal (_("cannot encode opcode"));
11153 for (i
= 0; i
< noperands
; ++i
)
11155 expressionS
*expr
= &tinsn
->tok
[i
];
11156 switch (expr
->X_op
)
11159 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11161 /* The register number has already been checked in
11162 expression_maybe_register, so we don't need to check here. */
11163 opnd_value
= expr
->X_add_number
;
11164 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11165 xtensa_operand_set_field (isa
, opcode
, i
, fmt
, 0,
11166 slotbuf
, opnd_value
);
11170 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11172 as_where (&file_name
, &line
);
11173 /* It is a constant and we called this function,
11174 then we have to try to fit it. */
11175 xtensa_insnbuf_set_operand (slotbuf
, fmt
, 0, opcode
, i
,
11176 expr
->X_add_number
, file_name
, line
);
11185 xtensa_format_encode (isa
, fmt
, insnbuf
);
11186 xtensa_format_set_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
11192 /* Convert the constant operands in the tinsn to slotbuf.
11193 Return TRUE if there is a symbol in the immediate field.
11194 (Eventually this should replace tinsn_to_insnbuf.) */
11196 /* Before this is called,
11197 1) the number of operands are correct
11198 2) the tinsn is a ITYPE_INSN
11199 3) ONLY the relaxable_ is built
11200 4) All operands are
11201 O_constant, O_symbol
11204 The return value tells whether there are any remaining O_symbols. */
11207 tinsn_to_slotbuf (xtensa_format fmt
,
11210 xtensa_insnbuf slotbuf
)
11212 xtensa_isa isa
= xtensa_default_isa
;
11213 xtensa_opcode opcode
= tinsn
->opcode
;
11214 bfd_boolean has_fixup
= FALSE
;
11215 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11218 *((int *) &slotbuf
[0]) = 0;
11219 *((int *) &slotbuf
[1]) = 0;
11220 assert (tinsn
->insn_type
== ITYPE_INSN
);
11221 if (noperands
!= tinsn
->ntok
)
11222 as_fatal (_("operand number mismatch"));
11224 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
11226 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
11227 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
11231 for (i
= 0; i
< noperands
; i
++)
11233 expressionS
*expr
= &tinsn
->tok
[i
];
11239 switch (expr
->X_op
)
11242 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11244 /* The register number has already been checked in
11245 expression_maybe_register, so we don't need to check here. */
11246 opnd_value
= expr
->X_add_number
;
11247 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11248 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
11251 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
11255 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11257 as_where (&file_name
, &line
);
11258 /* It is a constant and we called this function
11259 then we have to try to fit it. */
11260 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
11261 expr
->X_add_number
, file_name
, line
);
11274 /* Check the instruction arguments. Return TRUE on failure. */
11277 tinsn_check_arguments (const TInsn
*insn
)
11279 xtensa_isa isa
= xtensa_default_isa
;
11280 xtensa_opcode opcode
= insn
->opcode
;
11282 if (opcode
== XTENSA_UNDEFINED
)
11284 as_bad (_("invalid opcode"));
11288 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
11290 as_bad (_("too few operands"));
11294 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
11296 as_bad (_("too many operands"));
11303 /* Load an instruction from its encoded form. */
11306 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
11310 xg_init_vinsn (&vinsn
);
11311 vinsn_from_chars (&vinsn
, f
);
11313 *tinsn
= vinsn
.slots
[slot
];
11314 xg_free_vinsn (&vinsn
);
11319 tinsn_from_insnbuf (TInsn
*tinsn
,
11320 xtensa_insnbuf slotbuf
,
11325 xtensa_isa isa
= xtensa_default_isa
;
11327 /* Find the immed. */
11328 tinsn_init (tinsn
);
11329 tinsn
->insn_type
= ITYPE_INSN
;
11330 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
11331 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
11332 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
11333 for (i
= 0; i
< tinsn
->ntok
; i
++)
11335 set_expr_const (&tinsn
->tok
[i
],
11336 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
11337 tinsn
->opcode
, i
));
11342 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
11345 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
11347 xtensa_opcode opcode
= tinsn
->opcode
;
11350 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
11352 opnum
= get_relaxable_immed (opcode
);
11353 assert (opnum
>= 0);
11354 if (fragP
->tc_frag_data
.slot_sub_symbols
[slot
])
11356 set_expr_symbol_offset_diff
11357 (&tinsn
->tok
[opnum
],
11358 fragP
->tc_frag_data
.slot_symbols
[slot
],
11359 fragP
->tc_frag_data
.slot_sub_symbols
[slot
],
11360 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11364 set_expr_symbol_offset
11365 (&tinsn
->tok
[opnum
],
11366 fragP
->tc_frag_data
.slot_symbols
[slot
],
11367 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11374 get_num_stack_text_bytes (IStack
*istack
)
11377 int text_bytes
= 0;
11379 for (i
= 0; i
< istack
->ninsn
; i
++)
11381 TInsn
*tinsn
= &istack
->insn
[i
];
11382 if (tinsn
->insn_type
== ITYPE_INSN
)
11383 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
11390 get_num_stack_literal_bytes (IStack
*istack
)
11395 for (i
= 0; i
< istack
->ninsn
; i
++)
11397 TInsn
*tinsn
= &istack
->insn
[i
];
11398 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
11405 /* vliw_insn functions. */
11408 xg_init_vinsn (vliw_insn
*v
)
11411 xtensa_isa isa
= xtensa_default_isa
;
11413 xg_clear_vinsn (v
);
11415 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
11416 if (v
->insnbuf
== NULL
)
11417 as_fatal (_("out of memory"));
11419 for (i
= 0; i
< MAX_SLOTS
; i
++)
11421 tinsn_init (&v
->slots
[i
]);
11422 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
11423 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
11424 if (v
->slotbuf
[i
] == NULL
)
11425 as_fatal (_("out of memory"));
11431 xg_clear_vinsn (vliw_insn
*v
)
11434 v
->format
= XTENSA_UNDEFINED
;
11436 v
->inside_bundle
= FALSE
;
11438 if (xt_saved_debug_type
!= DEBUG_NONE
)
11439 debug_type
= xt_saved_debug_type
;
11441 for (i
= 0; i
< MAX_SLOTS
; i
++)
11443 memset (&v
->slots
[i
], 0, sizeof (TInsn
));
11444 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
11450 vinsn_has_specific_opcodes (vliw_insn
*v
)
11454 for (i
= 0; i
< v
->num_slots
; i
++)
11456 if (v
->slots
[i
].is_specific_opcode
)
11464 xg_free_vinsn (vliw_insn
*v
)
11467 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
11468 for (i
= 0; i
< MAX_SLOTS
; i
++)
11469 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
11473 /* Before this is called, we should have
11474 filled out the following fields:
11476 1) the number of operands for each opcode are correct
11477 2) the tinsn in the slots are ITYPE_INSN
11478 3) ONLY the relaxable_ is built
11479 4) All operands are
11480 O_constant, O_symbol
11483 The return value tells whether there are any remaining O_symbols. */
11486 vinsn_to_insnbuf (vliw_insn
*vinsn
,
11489 bfd_boolean record_fixup
)
11491 xtensa_isa isa
= xtensa_default_isa
;
11492 xtensa_format fmt
= vinsn
->format
;
11493 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
11495 bfd_boolean has_fixup
= FALSE
;
11497 xtensa_format_encode (isa
, fmt
, insnbuf
);
11499 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
11501 TInsn
*tinsn
= &vinsn
->slots
[slot
];
11502 bfd_boolean tinsn_has_fixup
=
11503 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
11504 vinsn
->slotbuf
[slot
]);
11506 xtensa_format_set_slot (isa
, fmt
, slot
,
11507 insnbuf
, vinsn
->slotbuf
[slot
]);
11508 /* tinsn_has_fixup tracks if there is a fixup at all.
11509 record_fixup controls globally. I.E., we use this
11510 function from several places, some of which are after
11511 fixups have already been recorded. Finally,
11512 tinsn->record_fixup controls based on the individual ops,
11513 which may or may not need it based on the relaxation
11515 if (tinsn_has_fixup
&& record_fixup
)
11518 xtensa_opcode opcode
= tinsn
->opcode
;
11519 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11522 for (i
= 0; i
< noperands
; i
++)
11524 expressionS
* expr
= &tinsn
->tok
[i
];
11525 switch (expr
->X_op
)
11530 if (get_relaxable_immed (opcode
) == i
)
11532 if (tinsn
->record_fix
|| expr
->X_op
!= O_symbol
)
11534 if (!xg_add_opcode_fix
11535 (tinsn
, i
, fmt
, slot
, expr
, fragP
,
11536 frag_offset
- fragP
->fr_literal
))
11537 as_bad (_("instruction with constant operands does not fit"));
11541 tinsn
->symbol
= expr
->X_add_symbol
;
11542 tinsn
->offset
= expr
->X_add_number
;
11546 as_bad (_("invalid operand %d on '%s'"),
11547 i
, xtensa_opcode_name (isa
, opcode
));
11555 if (get_relaxable_immed (opcode
) == i
)
11557 if (tinsn
->record_fix
)
11558 as_bad (_("invalid subtract operand"));
11561 tinsn
->symbol
= expr
->X_add_symbol
;
11562 tinsn
->sub_symbol
= expr
->X_op_symbol
;
11563 tinsn
->offset
= expr
->X_add_number
;
11567 as_bad (_("invalid operand %d on '%s'"),
11568 i
, xtensa_opcode_name (isa
, opcode
));
11572 as_bad (_("invalid expression for operand %d on '%s'"),
11573 i
, xtensa_opcode_name (isa
, opcode
));
11585 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
11587 static xtensa_insnbuf insnbuf
= NULL
;
11588 static xtensa_insnbuf slotbuf
= NULL
;
11591 xtensa_isa isa
= xtensa_default_isa
;
11595 insnbuf
= xtensa_insnbuf_alloc (isa
);
11596 slotbuf
= xtensa_insnbuf_alloc (isa
);
11599 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) f
, 0);
11600 fmt
= xtensa_format_decode (isa
, insnbuf
);
11601 if (fmt
== XTENSA_UNDEFINED
)
11602 as_fatal (_("cannot decode instruction format"));
11603 vinsn
->format
= fmt
;
11604 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
11606 for (i
= 0; i
< vinsn
->num_slots
; i
++)
11608 TInsn
*tinsn
= &vinsn
->slots
[i
];
11609 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
11610 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
11615 /* Expression utilities. */
11617 /* Return TRUE if the expression is an integer constant. */
11620 expr_is_const (const expressionS
*s
)
11622 return (s
->X_op
== O_constant
);
11626 /* Get the expression constant.
11627 Calling this is illegal if expr_is_const () returns TRUE. */
11630 get_expr_const (const expressionS
*s
)
11632 assert (expr_is_const (s
));
11633 return s
->X_add_number
;
11637 /* Set the expression to a constant value. */
11640 set_expr_const (expressionS
*s
, offsetT val
)
11642 s
->X_op
= O_constant
;
11643 s
->X_add_number
= val
;
11644 s
->X_add_symbol
= NULL
;
11645 s
->X_op_symbol
= NULL
;
11650 expr_is_register (const expressionS
*s
)
11652 return (s
->X_op
== O_register
);
11656 /* Get the expression constant.
11657 Calling this is illegal if expr_is_const () returns TRUE. */
11660 get_expr_register (const expressionS
*s
)
11662 assert (expr_is_register (s
));
11663 return s
->X_add_number
;
11667 /* Set the expression to a symbol + constant offset. */
11670 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
11672 s
->X_op
= O_symbol
;
11673 s
->X_add_symbol
= sym
;
11674 s
->X_op_symbol
= NULL
; /* unused */
11675 s
->X_add_number
= offset
;
11679 /* Set the expression to symbol - minus_sym + offset. */
11682 set_expr_symbol_offset_diff (expressionS
*s
,
11684 symbolS
*minus_sym
,
11687 s
->X_op
= O_subtract
;
11688 s
->X_add_symbol
= sym
;
11689 s
->X_op_symbol
= minus_sym
; /* unused */
11690 s
->X_add_number
= offset
;
11694 /* Return TRUE if the two expressions are equal. */
11697 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
11699 if (s1
->X_op
!= s2
->X_op
)
11701 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
11703 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
11705 if (s1
->X_add_number
!= s2
->X_add_number
)
11712 copy_expr (expressionS
*dst
, const expressionS
*src
)
11714 memcpy (dst
, src
, sizeof (expressionS
));
11718 /* Support for the "--rename-section" option. */
11720 struct rename_section_struct
11724 struct rename_section_struct
*next
;
11727 static struct rename_section_struct
*section_rename
;
11730 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
11731 entries to the section_rename list. Note: Specifying multiple
11732 renamings separated by colons is not documented and is retained only
11733 for backward compatibility. */
11736 build_section_rename (const char *arg
)
11738 struct rename_section_struct
*r
;
11739 char *this_arg
= NULL
;
11740 char *next_arg
= NULL
;
11742 for (this_arg
= xstrdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
11744 char *old_name
, *new_name
;
11748 next_arg
= strchr (this_arg
, ':');
11756 old_name
= this_arg
;
11757 new_name
= strchr (this_arg
, '=');
11759 if (*old_name
== '\0')
11761 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
11764 if (!new_name
|| new_name
[1] == '\0')
11766 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
11773 /* Check for invalid section renaming. */
11774 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11776 if (strcmp (r
->old_name
, old_name
) == 0)
11777 as_bad (_("section %s renamed multiple times"), old_name
);
11778 if (strcmp (r
->new_name
, new_name
) == 0)
11779 as_bad (_("multiple sections remapped to output section %s"),
11784 r
= (struct rename_section_struct
*)
11785 xmalloc (sizeof (struct rename_section_struct
));
11786 r
->old_name
= xstrdup (old_name
);
11787 r
->new_name
= xstrdup (new_name
);
11788 r
->next
= section_rename
;
11789 section_rename
= r
;
11795 xtensa_section_rename (char *name
)
11797 struct rename_section_struct
*r
= section_rename
;
11799 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11801 if (strcmp (r
->old_name
, name
) == 0)
11802 return r
->new_name
;