1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
24 #include "safe-ctype.h"
25 #include "tc-xtensa.h"
27 #include "xtensa-relax.h"
28 #include "dwarf2dbg.h"
29 #include "xtensa-istack.h"
30 #include "struc-symbol.h"
31 #include "xtensa-config.h"
33 /* Provide default values for new configuration settings. */
39 #define uint32 unsigned int
42 #define int32 signed int
47 Naming conventions (used somewhat inconsistently):
48 The xtensa_ functions are exported
49 The xg_ functions are internal
51 We also have a couple of different extensibility mechanisms.
52 1) The idiom replacement:
53 This is used when a line is first parsed to
54 replace an instruction pattern with another instruction
55 It is currently limited to replacements of instructions
56 with constant operands.
57 2) The xtensa-relax.c mechanism that has stronger instruction
58 replacement patterns. When an instruction's immediate field
59 does not fit the next instruction sequence is attempted.
60 In addition, "narrow" opcodes are supported this way. */
63 /* Define characters with special meanings to GAS. */
64 const char comment_chars
[] = "#";
65 const char line_comment_chars
[] = "#";
66 const char line_separator_chars
[] = ";";
67 const char EXP_CHARS
[] = "eE";
68 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
71 /* Flags to indicate whether the hardware supports the density and
72 absolute literals options. */
74 bfd_boolean density_supported
= XCHAL_HAVE_DENSITY
;
75 bfd_boolean absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
77 /* Maximum width we would pad an unreachable frag to get alignment. */
78 #define UNREACHABLE_MAX_WIDTH 8
80 static vliw_insn cur_vinsn
;
82 unsigned xtensa_num_pipe_stages
;
83 unsigned xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
85 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
87 /* Some functions are only valid in the front end. This variable
88 allows us to assert that we haven't crossed over into the
90 static bfd_boolean past_xtensa_end
= FALSE
;
92 /* Flags for properties of the last instruction in a segment. */
93 #define FLAG_IS_A0_WRITER 0x1
94 #define FLAG_IS_BAD_LOOPEND 0x2
97 /* We define a special segment names ".literal" to place literals
98 into. The .fini and .init sections are special because they
99 contain code that is moved together by the linker. We give them
100 their own special .fini.literal and .init.literal sections. */
102 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
103 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
104 #define INIT_SECTION_NAME xtensa_section_rename (".init")
105 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
108 /* This type is used for the directive_stack to keep track of the
109 state of the literal collection pools. If lit_prefix is set, it is
110 used to determine the literal section names; otherwise, the literal
111 sections are determined based on the current text section. The
112 lit_seg and lit4_seg fields cache these literal sections, with the
113 current_text_seg field used a tag to indicate whether the cached
116 typedef struct lit_state_struct
119 segT current_text_seg
;
124 static lit_state default_lit_sections
;
127 /* We keep a list of literal segments. The seg_list type is the node
128 for this list. The literal_head pointer is the head of the list,
129 with the literal_head_h dummy node at the start. */
131 typedef struct seg_list_struct
133 struct seg_list_struct
*next
;
137 static seg_list literal_head_h
;
138 static seg_list
*literal_head
= &literal_head_h
;
141 /* Lists of symbols. We keep a list of symbols that label the current
142 instruction, so that we can adjust the symbols when inserting alignment
143 for various instructions. We also keep a list of all the symbols on
144 literals, so that we can fix up those symbols when the literals are
145 later moved into the text sections. */
147 typedef struct sym_list_struct
149 struct sym_list_struct
*next
;
153 static sym_list
*insn_labels
= NULL
;
154 static sym_list
*free_insn_labels
= NULL
;
155 static sym_list
*saved_insn_labels
= NULL
;
157 static sym_list
*literal_syms
;
160 /* Flags to determine whether to prefer const16 or l32r
161 if both options are available. */
162 int prefer_const16
= 0;
165 /* Global flag to indicate when we are emitting literals. */
166 int generating_literals
= 0;
168 /* The following PROPERTY table definitions are copied from
169 <elf/xtensa.h> and must be kept in sync with the code there. */
171 /* Flags in the property tables to specify whether blocks of memory
172 are literals, instructions, data, or unreachable. For
173 instructions, blocks that begin loop targets and branch targets are
174 designated. Blocks that do not allow density, instruction
175 reordering or transformation are also specified. Finally, for
176 branch targets, branch target alignment priority is included.
177 Alignment of the next block is specified in the current block
178 and the size of the current block does not include any fill required
179 to align to the next block. */
181 #define XTENSA_PROP_LITERAL 0x00000001
182 #define XTENSA_PROP_INSN 0x00000002
183 #define XTENSA_PROP_DATA 0x00000004
184 #define XTENSA_PROP_UNREACHABLE 0x00000008
185 /* Instruction only properties at beginning of code. */
186 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
187 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
188 /* Instruction only properties about code. */
189 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
190 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
191 /* Historically, NO_TRANSFORM was a property of instructions,
192 but it should apply to literals under certain circumstances. */
193 #define XTENSA_PROP_NO_TRANSFORM 0x00000100
195 /* Branch target alignment information. This transmits information
196 to the linker optimization about the priority of aligning a
197 particular block for branch target alignment: None, low priority,
198 high priority, or required. These only need to be checked in
199 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
202 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
203 case XTENSA_PROP_BT_ALIGN_NONE:
204 case XTENSA_PROP_BT_ALIGN_LOW:
205 case XTENSA_PROP_BT_ALIGN_HIGH:
206 case XTENSA_PROP_BT_ALIGN_REQUIRE:
208 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
210 /* No branch target alignment. */
211 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
212 /* Low priority branch target alignment. */
213 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
214 /* High priority branch target alignment. */
215 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
216 /* Required branch target alignment. */
217 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
219 #define GET_XTENSA_PROP_BT_ALIGN(flag) \
220 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
221 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
222 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
223 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
226 /* Alignment is specified in the block BEFORE the one that needs
227 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
228 get the required alignment specified as a power of 2. Use
229 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
230 alignment. Be careful of side effects since the SET will evaluate
231 flags twice. Also, note that the SIZE of a block in the property
232 table does not include the alignment size, so the alignment fill
233 must be calculated to determine if two blocks are contiguous.
234 TEXT_ALIGN is not currently implemented but is a placeholder for a
235 possible future implementation. */
237 #define XTENSA_PROP_ALIGN 0x00000800
239 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
241 #define GET_XTENSA_PROP_ALIGNMENT(flag) \
242 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
243 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
244 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
245 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
247 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
250 /* Structure for saving instruction and alignment per-fragment data
251 that will be written to the object file. This structure is
252 equivalent to the actual data that will be written out to the file
253 but is easier to use. We provide a conversion to file flags
254 in frag_flags_to_number. */
256 typedef struct frag_flags_struct frag_flags
;
258 struct frag_flags_struct
260 /* is_literal should only be used after xtensa_move_literals.
261 If you need to check if you are generating a literal fragment,
262 then use the generating_literals global. */
264 unsigned is_literal
: 1;
265 unsigned is_insn
: 1;
266 unsigned is_data
: 1;
267 unsigned is_unreachable
: 1;
269 /* is_specific_opcode implies no_transform. */
270 unsigned is_no_transform
: 1;
274 unsigned is_loop_target
: 1;
275 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
276 unsigned bt_align_priority
: 2;
278 unsigned is_no_density
: 1;
279 /* no_longcalls flag does not need to be placed in the object file. */
281 unsigned is_no_reorder
: 1;
283 /* Uses absolute literal addressing for l32r. */
284 unsigned is_abslit
: 1;
286 unsigned is_align
: 1;
287 unsigned alignment
: 5;
291 /* Structure for saving information about a block of property data
292 for frags that have the same flags. */
293 struct xtensa_block_info_struct
299 struct xtensa_block_info_struct
*next
;
303 /* Structure for saving the current state before emitting literals. */
304 typedef struct emit_state_struct
309 int generating_literals
;
313 /* Opcode placement information */
315 typedef unsigned long long bitfield
;
316 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
317 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
318 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
320 #define MAX_FORMATS 32
322 typedef struct op_placement_info_struct
325 /* A number describing how restrictive the issue is for this
326 opcode. For example, an opcode that fits lots of different
327 formats has a high freedom, as does an opcode that fits
328 only one format but many slots in that format. The most
329 restrictive is the opcode that fits only one slot in one
332 xtensa_format narrowest
;
336 /* formats is a bitfield with the Nth bit set
337 if the opcode fits in the Nth xtensa_format. */
340 /* slots[N]'s Mth bit is set if the op fits in the
341 Mth slot of the Nth xtensa_format. */
342 bitfield slots
[MAX_FORMATS
];
344 /* A count of the number of slots in a given format
345 an op can fit (i.e., the bitcount of the slot field above). */
346 char slots_in_format
[MAX_FORMATS
];
348 } op_placement_info
, *op_placement_info_table
;
350 op_placement_info_table op_placement_table
;
353 /* Extra expression types. */
355 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
356 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
357 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
358 #define O_pcrel O_md4 /* value is a PC-relative offset */
359 #define O_tlsfunc O_md5 /* TLS_FUNC/TLSDESC_FN relocation */
360 #define O_tlsarg O_md6 /* TLS_ARG/TLSDESC_ARG relocation */
361 #define O_tlscall O_md7 /* TLS_CALL relocation */
362 #define O_tpoff O_md8 /* TPOFF relocation */
363 #define O_dtpoff O_md9 /* DTPOFF relocation */
365 struct suffix_reloc_map
369 bfd_reloc_code_real_type reloc
;
370 unsigned char operator;
373 #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op }
375 static struct suffix_reloc_map suffix_relocs
[] =
377 SUFFIX_MAP ("l", BFD_RELOC_LO16
, O_lo16
),
378 SUFFIX_MAP ("h", BFD_RELOC_HI16
, O_hi16
),
379 SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT
, O_pltrel
),
380 SUFFIX_MAP ("pcrel", BFD_RELOC_32_PCREL
, O_pcrel
),
381 SUFFIX_MAP ("tlsfunc", BFD_RELOC_XTENSA_TLS_FUNC
, O_tlsfunc
),
382 SUFFIX_MAP ("tlsarg", BFD_RELOC_XTENSA_TLS_ARG
, O_tlsarg
),
383 SUFFIX_MAP ("tlscall", BFD_RELOC_XTENSA_TLS_CALL
, O_tlscall
),
384 SUFFIX_MAP ("tpoff", BFD_RELOC_XTENSA_TLS_TPOFF
, O_tpoff
),
385 SUFFIX_MAP ("dtpoff", BFD_RELOC_XTENSA_TLS_DTPOFF
, O_dtpoff
),
386 { (char *) 0, 0, BFD_RELOC_UNUSED
, 0 }
400 directive_literal_prefix
,
402 directive_absolute_literals
,
403 directive_last_directive
409 bfd_boolean can_be_negated
;
412 const directive_infoS directive_info
[] =
415 { "literal", FALSE
},
417 { "transform", TRUE
},
418 { "freeregs", FALSE
},
419 { "longcalls", TRUE
},
420 { "literal_prefix", FALSE
},
421 { "schedule", TRUE
},
422 { "absolute-literals", TRUE
}
425 bfd_boolean directive_state
[] =
429 #if !XCHAL_HAVE_DENSITY
434 TRUE
, /* transform */
435 FALSE
, /* freeregs */
436 FALSE
, /* longcalls */
437 FALSE
, /* literal_prefix */
438 FALSE
, /* schedule */
439 #if XSHAL_USE_ABSOLUTE_LITERALS
440 TRUE
/* absolute_literals */
442 FALSE
/* absolute_literals */
447 /* Directive functions. */
449 static void xtensa_begin_directive (int);
450 static void xtensa_end_directive (int);
451 static void xtensa_literal_prefix (void);
452 static void xtensa_literal_position (int);
453 static void xtensa_literal_pseudo (int);
454 static void xtensa_frequency_pseudo (int);
455 static void xtensa_elf_cons (int);
456 static void xtensa_leb128 (int);
458 /* Parsing and Idiom Translation. */
460 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
462 /* Various Other Internal Functions. */
464 extern bfd_boolean
xg_is_single_relaxable_insn (TInsn
*, TInsn
*, bfd_boolean
);
465 static bfd_boolean
xg_build_to_insn (TInsn
*, TInsn
*, BuildInstr
*);
466 static void xtensa_mark_literal_pool_location (void);
467 static addressT
get_expanded_loop_offset (xtensa_opcode
);
468 static fragS
*get_literal_pool_location (segT
);
469 static void set_literal_pool_location (segT
, fragS
*);
470 static void xtensa_set_frag_assembly_state (fragS
*);
471 static void finish_vinsn (vliw_insn
*);
472 static bfd_boolean
emit_single_op (TInsn
*);
473 static int total_frag_text_expansion (fragS
*);
475 /* Alignment Functions. */
477 static int get_text_align_power (unsigned);
478 static int get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
479 static int branch_align_power (segT
);
481 /* Helpers for xtensa_relax_frag(). */
483 static long relax_frag_add_nop (fragS
*);
485 /* Accessors for additional per-subsegment information. */
487 static unsigned get_last_insn_flags (segT
, subsegT
);
488 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
489 static float get_subseg_total_freq (segT
, subsegT
);
490 static float get_subseg_target_freq (segT
, subsegT
);
491 static void set_subseg_freq (segT
, subsegT
, float, float);
493 /* Segment list functions. */
495 static void xtensa_move_literals (void);
496 static void xtensa_reorder_segments (void);
497 static void xtensa_switch_to_literal_fragment (emit_state
*);
498 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
499 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
500 static void xtensa_restore_emit_state (emit_state
*);
501 static segT
cache_literal_section (bfd_boolean
);
503 /* Import from elf32-xtensa.c in BFD library. */
505 extern asection
*xtensa_make_property_section (asection
*, const char *);
507 /* op_placement_info functions. */
509 static void init_op_placement_info_table (void);
510 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
511 static int xg_get_single_size (xtensa_opcode
);
512 static xtensa_format
xg_get_single_format (xtensa_opcode
);
513 static int xg_get_single_slot (xtensa_opcode
);
515 /* TInsn and IStack functions. */
517 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
518 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
519 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
520 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
521 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
522 static void tinsn_from_chars (TInsn
*, char *, int);
523 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
524 static int get_num_stack_text_bytes (IStack
*);
525 static int get_num_stack_literal_bytes (IStack
*);
527 /* vliw_insn functions. */
529 static void xg_init_vinsn (vliw_insn
*);
530 static void xg_clear_vinsn (vliw_insn
*);
531 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
532 static void xg_free_vinsn (vliw_insn
*);
533 static bfd_boolean vinsn_to_insnbuf
534 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
535 static void vinsn_from_chars (vliw_insn
*, char *);
537 /* Expression Utilities. */
539 bfd_boolean
expr_is_const (const expressionS
*);
540 offsetT
get_expr_const (const expressionS
*);
541 void set_expr_const (expressionS
*, offsetT
);
542 bfd_boolean
expr_is_register (const expressionS
*);
543 offsetT
get_expr_register (const expressionS
*);
544 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
545 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
546 static void copy_expr (expressionS
*, const expressionS
*);
548 /* Section renaming. */
550 static void build_section_rename (const char *);
553 /* ISA imported from bfd. */
554 extern xtensa_isa xtensa_default_isa
;
556 extern int target_big_endian
;
558 static xtensa_opcode xtensa_addi_opcode
;
559 static xtensa_opcode xtensa_addmi_opcode
;
560 static xtensa_opcode xtensa_call0_opcode
;
561 static xtensa_opcode xtensa_call4_opcode
;
562 static xtensa_opcode xtensa_call8_opcode
;
563 static xtensa_opcode xtensa_call12_opcode
;
564 static xtensa_opcode xtensa_callx0_opcode
;
565 static xtensa_opcode xtensa_callx4_opcode
;
566 static xtensa_opcode xtensa_callx8_opcode
;
567 static xtensa_opcode xtensa_callx12_opcode
;
568 static xtensa_opcode xtensa_const16_opcode
;
569 static xtensa_opcode xtensa_entry_opcode
;
570 static xtensa_opcode xtensa_extui_opcode
;
571 static xtensa_opcode xtensa_movi_opcode
;
572 static xtensa_opcode xtensa_movi_n_opcode
;
573 static xtensa_opcode xtensa_isync_opcode
;
574 static xtensa_opcode xtensa_j_opcode
;
575 static xtensa_opcode xtensa_jx_opcode
;
576 static xtensa_opcode xtensa_l32r_opcode
;
577 static xtensa_opcode xtensa_loop_opcode
;
578 static xtensa_opcode xtensa_loopnez_opcode
;
579 static xtensa_opcode xtensa_loopgtz_opcode
;
580 static xtensa_opcode xtensa_nop_opcode
;
581 static xtensa_opcode xtensa_nop_n_opcode
;
582 static xtensa_opcode xtensa_or_opcode
;
583 static xtensa_opcode xtensa_ret_opcode
;
584 static xtensa_opcode xtensa_ret_n_opcode
;
585 static xtensa_opcode xtensa_retw_opcode
;
586 static xtensa_opcode xtensa_retw_n_opcode
;
587 static xtensa_opcode xtensa_rsr_lcount_opcode
;
588 static xtensa_opcode xtensa_waiti_opcode
;
591 /* Command-line Options. */
593 bfd_boolean use_literal_section
= TRUE
;
594 enum flix_level produce_flix
= FLIX_ALL
;
595 static bfd_boolean align_targets
= TRUE
;
596 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
597 static bfd_boolean has_a0_b_retw
= FALSE
;
598 static bfd_boolean workaround_a0_b_retw
= FALSE
;
599 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
600 static bfd_boolean workaround_short_loop
= FALSE
;
601 static bfd_boolean maybe_has_short_loop
= FALSE
;
602 static bfd_boolean workaround_close_loop_end
= FALSE
;
603 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
604 static bfd_boolean enforce_three_byte_loop_align
= FALSE
;
606 /* When workaround_short_loops is TRUE, all loops with early exits must
607 have at least 3 instructions. workaround_all_short_loops is a modifier
608 to the workaround_short_loop flag. In addition to the
609 workaround_short_loop actions, all straightline loopgtz and loopnez
610 must have at least 3 instructions. */
612 static bfd_boolean workaround_all_short_loops
= FALSE
;
616 xtensa_setup_hw_workarounds (int earliest
, int latest
)
618 if (earliest
> latest
)
619 as_fatal (_("illegal range of target hardware versions"));
621 /* Enable all workarounds for pre-T1050.0 hardware. */
622 if (earliest
< 105000 || latest
< 105000)
624 workaround_a0_b_retw
|= TRUE
;
625 workaround_b_j_loop_end
|= TRUE
;
626 workaround_short_loop
|= TRUE
;
627 workaround_close_loop_end
|= TRUE
;
628 workaround_all_short_loops
|= TRUE
;
629 enforce_three_byte_loop_align
= TRUE
;
636 option_density
= OPTION_MD_BASE
,
640 option_no_generate_flix
,
647 option_no_link_relax
,
655 option_text_section_literals
,
656 option_no_text_section_literals
,
658 option_absolute_literals
,
659 option_no_absolute_literals
,
661 option_align_targets
,
662 option_no_align_targets
,
664 option_warn_unaligned_targets
,
669 option_workaround_a0_b_retw
,
670 option_no_workaround_a0_b_retw
,
672 option_workaround_b_j_loop_end
,
673 option_no_workaround_b_j_loop_end
,
675 option_workaround_short_loop
,
676 option_no_workaround_short_loop
,
678 option_workaround_all_short_loops
,
679 option_no_workaround_all_short_loops
,
681 option_workaround_close_loop_end
,
682 option_no_workaround_close_loop_end
,
684 option_no_workarounds
,
686 option_rename_section_name
,
689 option_prefer_const16
,
691 option_target_hardware
694 const char *md_shortopts
= "";
696 struct option md_longopts
[] =
698 { "density", no_argument
, NULL
, option_density
},
699 { "no-density", no_argument
, NULL
, option_no_density
},
701 { "flix", no_argument
, NULL
, option_flix
},
702 { "no-generate-flix", no_argument
, NULL
, option_no_generate_flix
},
703 { "no-allow-flix", no_argument
, NULL
, option_no_flix
},
705 /* Both "relax" and "generics" are deprecated and treated as equivalent
706 to the "transform" option. */
707 { "relax", no_argument
, NULL
, option_relax
},
708 { "no-relax", no_argument
, NULL
, option_no_relax
},
709 { "generics", no_argument
, NULL
, option_generics
},
710 { "no-generics", no_argument
, NULL
, option_no_generics
},
712 { "transform", no_argument
, NULL
, option_transform
},
713 { "no-transform", no_argument
, NULL
, option_no_transform
},
714 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
715 { "no-text-section-literals", no_argument
, NULL
,
716 option_no_text_section_literals
},
717 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
718 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
719 /* This option was changed from -align-target to -target-align
720 because it conflicted with the "-al" option. */
721 { "target-align", no_argument
, NULL
, option_align_targets
},
722 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
723 { "warn-unaligned-targets", no_argument
, NULL
,
724 option_warn_unaligned_targets
},
725 { "longcalls", no_argument
, NULL
, option_longcalls
},
726 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
728 { "no-workaround-a0-b-retw", no_argument
, NULL
,
729 option_no_workaround_a0_b_retw
},
730 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
732 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
733 option_no_workaround_b_j_loop_end
},
734 { "workaround-b-j-loop-end", no_argument
, NULL
,
735 option_workaround_b_j_loop_end
},
737 { "no-workaround-short-loops", no_argument
, NULL
,
738 option_no_workaround_short_loop
},
739 { "workaround-short-loops", no_argument
, NULL
,
740 option_workaround_short_loop
},
742 { "no-workaround-all-short-loops", no_argument
, NULL
,
743 option_no_workaround_all_short_loops
},
744 { "workaround-all-short-loop", no_argument
, NULL
,
745 option_workaround_all_short_loops
},
747 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
748 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
750 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
752 { "no-workaround-close-loop-end", no_argument
, NULL
,
753 option_no_workaround_close_loop_end
},
754 { "workaround-close-loop-end", no_argument
, NULL
,
755 option_workaround_close_loop_end
},
757 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
759 { "link-relax", no_argument
, NULL
, option_link_relax
},
760 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
762 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
764 { NULL
, no_argument
, NULL
, 0 }
767 size_t md_longopts_size
= sizeof md_longopts
;
771 md_parse_option (int c
, char *arg
)
776 as_warn (_("--density option is ignored"));
778 case option_no_density
:
779 as_warn (_("--no-density option is ignored"));
781 case option_link_relax
:
784 case option_no_link_relax
:
788 produce_flix
= FLIX_ALL
;
790 case option_no_generate_flix
:
791 produce_flix
= FLIX_NO_GENERATE
;
794 produce_flix
= FLIX_NONE
;
796 case option_generics
:
797 as_warn (_("--generics is deprecated; use --transform instead"));
798 return md_parse_option (option_transform
, arg
);
799 case option_no_generics
:
800 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
801 return md_parse_option (option_no_transform
, arg
);
803 as_warn (_("--relax is deprecated; use --transform instead"));
804 return md_parse_option (option_transform
, arg
);
805 case option_no_relax
:
806 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
807 return md_parse_option (option_no_transform
, arg
);
808 case option_longcalls
:
809 directive_state
[directive_longcalls
] = TRUE
;
811 case option_no_longcalls
:
812 directive_state
[directive_longcalls
] = FALSE
;
814 case option_text_section_literals
:
815 use_literal_section
= FALSE
;
817 case option_no_text_section_literals
:
818 use_literal_section
= TRUE
;
820 case option_absolute_literals
:
821 if (!absolute_literals_supported
)
823 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
826 directive_state
[directive_absolute_literals
] = TRUE
;
828 case option_no_absolute_literals
:
829 directive_state
[directive_absolute_literals
] = FALSE
;
832 case option_workaround_a0_b_retw
:
833 workaround_a0_b_retw
= TRUE
;
835 case option_no_workaround_a0_b_retw
:
836 workaround_a0_b_retw
= FALSE
;
838 case option_workaround_b_j_loop_end
:
839 workaround_b_j_loop_end
= TRUE
;
841 case option_no_workaround_b_j_loop_end
:
842 workaround_b_j_loop_end
= FALSE
;
845 case option_workaround_short_loop
:
846 workaround_short_loop
= TRUE
;
848 case option_no_workaround_short_loop
:
849 workaround_short_loop
= FALSE
;
852 case option_workaround_all_short_loops
:
853 workaround_all_short_loops
= TRUE
;
855 case option_no_workaround_all_short_loops
:
856 workaround_all_short_loops
= FALSE
;
859 case option_workaround_close_loop_end
:
860 workaround_close_loop_end
= TRUE
;
862 case option_no_workaround_close_loop_end
:
863 workaround_close_loop_end
= FALSE
;
866 case option_no_workarounds
:
867 workaround_a0_b_retw
= FALSE
;
868 workaround_b_j_loop_end
= FALSE
;
869 workaround_short_loop
= FALSE
;
870 workaround_all_short_loops
= FALSE
;
871 workaround_close_loop_end
= FALSE
;
874 case option_align_targets
:
875 align_targets
= TRUE
;
877 case option_no_align_targets
:
878 align_targets
= FALSE
;
881 case option_warn_unaligned_targets
:
882 warn_unaligned_branch_targets
= TRUE
;
885 case option_rename_section_name
:
886 build_section_rename (arg
);
890 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
891 should be emitted or not. FIXME: Not implemented. */
894 case option_prefer_l32r
:
896 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
900 case option_prefer_const16
:
902 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
906 case option_target_hardware
:
908 int earliest
, latest
= 0;
909 if (*arg
== 0 || *arg
== '-')
910 as_fatal (_("invalid target hardware version"));
912 earliest
= strtol (arg
, &arg
, 0);
916 else if (*arg
== '-')
919 as_fatal (_("invalid target hardware version"));
920 latest
= strtol (arg
, &arg
, 0);
923 as_fatal (_("invalid target hardware version"));
925 xtensa_setup_hw_workarounds (earliest
, latest
);
929 case option_transform
:
930 /* This option has no affect other than to use the defaults,
931 which are already set. */
934 case option_no_transform
:
935 /* This option turns off all transformations of any kind.
936 However, because we want to preserve the state of other
937 directives, we only change its own field. Thus, before
938 you perform any transformation, always check if transform
939 is available. If you use the functions we provide for this
940 purpose, you will be ok. */
941 directive_state
[directive_transform
] = FALSE
;
951 md_show_usage (FILE *stream
)
955 --[no-]text-section-literals\n\
956 [Do not] put literals in the text section\n\
957 --[no-]absolute-literals\n\
958 [Do not] default to use non-PC-relative literals\n\
959 --[no-]target-align [Do not] try to align branch targets\n\
960 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
961 --[no-]transform [Do not] transform instructions\n\
962 --flix both allow hand-written and generate flix bundles\n\
963 --no-generate-flix allow hand-written but do not generate\n\
965 --no-allow-flix neither allow hand-written nor generate\n\
967 --rename-section old=new Rename section 'old' to 'new'\n", stream
);
971 /* Functions related to the list of current label symbols. */
974 xtensa_add_insn_label (symbolS
*sym
)
978 if (!free_insn_labels
)
979 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
982 l
= free_insn_labels
;
983 free_insn_labels
= l
->next
;
987 l
->next
= insn_labels
;
993 xtensa_clear_insn_labels (void)
997 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1005 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
)
1009 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
1011 symbolS
*lit_sym
= lit
->sym
;
1012 S_SET_VALUE (lit_sym
, new_offset
);
1013 symbol_set_frag (lit_sym
, new_frag
);
1018 /* Directive data and functions. */
1020 typedef struct state_stackS_struct
1022 directiveE directive
;
1023 bfd_boolean negated
;
1024 bfd_boolean old_state
;
1028 struct state_stackS_struct
*prev
;
1031 state_stackS
*directive_state_stack
;
1033 const pseudo_typeS md_pseudo_table
[] =
1035 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
1036 { "literal_position", xtensa_literal_position
, 0 },
1037 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
1038 { "long", xtensa_elf_cons
, 4 },
1039 { "word", xtensa_elf_cons
, 4 },
1040 { "4byte", xtensa_elf_cons
, 4 },
1041 { "short", xtensa_elf_cons
, 2 },
1042 { "2byte", xtensa_elf_cons
, 2 },
1043 { "sleb128", xtensa_leb128
, 1},
1044 { "uleb128", xtensa_leb128
, 0},
1045 { "begin", xtensa_begin_directive
, 0 },
1046 { "end", xtensa_end_directive
, 0 },
1047 { "literal", xtensa_literal_pseudo
, 0 },
1048 { "frequency", xtensa_frequency_pseudo
, 0 },
1054 use_transform (void)
1056 /* After md_end, you should be checking frag by frag, rather
1057 than state directives. */
1058 gas_assert (!past_xtensa_end
);
1059 return directive_state
[directive_transform
];
1064 do_align_targets (void)
1066 /* Do not use this function after md_end; just look at align_targets
1067 instead. There is no target-align directive, so alignment is either
1068 enabled for all frags or not done at all. */
1069 gas_assert (!past_xtensa_end
);
1070 return align_targets
&& use_transform ();
1075 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1079 state_stackS
*stack
= (state_stackS
*) xmalloc (sizeof (state_stackS
));
1081 as_where (&file
, &line
);
1083 stack
->directive
= directive
;
1084 stack
->negated
= negated
;
1085 stack
->old_state
= directive_state
[directive
];
1088 stack
->datum
= datum
;
1089 stack
->prev
= directive_state_stack
;
1090 directive_state_stack
= stack
;
1092 directive_state
[directive
] = !negated
;
1097 directive_pop (directiveE
*directive
,
1098 bfd_boolean
*negated
,
1103 state_stackS
*top
= directive_state_stack
;
1105 if (!directive_state_stack
)
1107 as_bad (_("unmatched end directive"));
1108 *directive
= directive_none
;
1112 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1113 *directive
= top
->directive
;
1114 *negated
= top
->negated
;
1117 *datum
= top
->datum
;
1118 directive_state_stack
= top
->prev
;
1124 directive_balance (void)
1126 while (directive_state_stack
)
1128 directiveE directive
;
1129 bfd_boolean negated
;
1134 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1135 as_warn_where ((char *) file
, line
,
1136 _(".begin directive with no matching .end directive"));
1142 inside_directive (directiveE dir
)
1144 state_stackS
*top
= directive_state_stack
;
1146 while (top
&& top
->directive
!= dir
)
1149 return (top
!= NULL
);
1154 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1158 char *directive_string
;
1160 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1165 input_line_pointer
+= 3;
1168 len
= strspn (input_line_pointer
,
1169 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1171 /* This code is a hack to make .begin [no-][generics|relax] exactly
1172 equivalent to .begin [no-]transform. We should remove it when
1173 we stop accepting those options. */
1175 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1177 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1178 directive_string
= "transform";
1180 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1182 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1183 directive_string
= "transform";
1186 directive_string
= input_line_pointer
;
1188 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1190 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1192 input_line_pointer
+= len
;
1193 *directive
= (directiveE
) i
;
1194 if (*negated
&& !directive_info
[i
].can_be_negated
)
1195 as_bad (_("directive %s cannot be negated"),
1196 directive_info
[i
].name
);
1201 as_bad (_("unknown directive"));
1202 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1207 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1209 directiveE directive
;
1210 bfd_boolean negated
;
1214 get_directive (&directive
, &negated
);
1215 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1217 discard_rest_of_line ();
1221 if (cur_vinsn
.inside_bundle
)
1222 as_bad (_("directives are not valid inside bundles"));
1226 case directive_literal
:
1227 if (!inside_directive (directive_literal
))
1229 /* Previous labels go with whatever follows this directive, not with
1230 the literal, so save them now. */
1231 saved_insn_labels
= insn_labels
;
1234 as_warn (_(".begin literal is deprecated; use .literal instead"));
1235 state
= (emit_state
*) xmalloc (sizeof (emit_state
));
1236 xtensa_switch_to_literal_fragment (state
);
1237 directive_push (directive_literal
, negated
, state
);
1240 case directive_literal_prefix
:
1241 /* Have to flush pending output because a movi relaxed to an l32r
1242 might produce a literal. */
1243 md_flush_pending_output ();
1244 /* Check to see if the current fragment is a literal
1245 fragment. If it is, then this operation is not allowed. */
1246 if (generating_literals
)
1248 as_bad (_("cannot set literal_prefix inside literal fragment"));
1252 /* Allocate the literal state for this section and push
1253 onto the directive stack. */
1254 ls
= xmalloc (sizeof (lit_state
));
1257 *ls
= default_lit_sections
;
1258 directive_push (directive_literal_prefix
, negated
, ls
);
1260 /* Process the new prefix. */
1261 xtensa_literal_prefix ();
1264 case directive_freeregs
:
1265 /* This information is currently unused, but we'll accept the statement
1266 and just discard the rest of the line. This won't check the syntax,
1267 but it will accept every correct freeregs directive. */
1268 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1269 directive_push (directive_freeregs
, negated
, 0);
1272 case directive_schedule
:
1273 md_flush_pending_output ();
1274 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1275 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1276 directive_push (directive_schedule
, negated
, 0);
1277 xtensa_set_frag_assembly_state (frag_now
);
1280 case directive_density
:
1281 as_warn (_(".begin [no-]density is ignored"));
1284 case directive_absolute_literals
:
1285 md_flush_pending_output ();
1286 if (!absolute_literals_supported
&& !negated
)
1288 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1291 xtensa_set_frag_assembly_state (frag_now
);
1292 directive_push (directive
, negated
, 0);
1296 md_flush_pending_output ();
1297 xtensa_set_frag_assembly_state (frag_now
);
1298 directive_push (directive
, negated
, 0);
1302 demand_empty_rest_of_line ();
1307 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1309 directiveE begin_directive
, end_directive
;
1310 bfd_boolean begin_negated
, end_negated
;
1314 emit_state
**state_ptr
;
1317 if (cur_vinsn
.inside_bundle
)
1318 as_bad (_("directives are not valid inside bundles"));
1320 get_directive (&end_directive
, &end_negated
);
1322 md_flush_pending_output ();
1324 switch (end_directive
)
1326 case (directiveE
) XTENSA_UNDEFINED
:
1327 discard_rest_of_line ();
1330 case directive_density
:
1331 as_warn (_(".end [no-]density is ignored"));
1332 demand_empty_rest_of_line ();
1335 case directive_absolute_literals
:
1336 if (!absolute_literals_supported
&& !end_negated
)
1338 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1339 demand_empty_rest_of_line ();
1348 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1349 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1350 (const void **) state_ptr
);
1352 if (begin_directive
!= directive_none
)
1354 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1356 as_bad (_("does not match begin %s%s at %s:%d"),
1357 begin_negated
? "no-" : "",
1358 directive_info
[begin_directive
].name
, file
, line
);
1362 switch (end_directive
)
1364 case directive_literal
:
1365 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1366 xtensa_restore_emit_state (state
);
1367 xtensa_set_frag_assembly_state (frag_now
);
1369 if (!inside_directive (directive_literal
))
1371 /* Restore the list of current labels. */
1372 xtensa_clear_insn_labels ();
1373 insn_labels
= saved_insn_labels
;
1377 case directive_literal_prefix
:
1378 /* Restore the default collection sections from saved state. */
1379 s
= (lit_state
*) state
;
1381 default_lit_sections
= *s
;
1383 /* Free the state storage. */
1384 free (s
->lit_prefix
);
1388 case directive_schedule
:
1389 case directive_freeregs
:
1393 xtensa_set_frag_assembly_state (frag_now
);
1399 demand_empty_rest_of_line ();
1403 /* Place an aligned literal fragment at the current location. */
1406 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1408 md_flush_pending_output ();
1410 if (inside_directive (directive_literal
))
1411 as_warn (_(".literal_position inside literal directive; ignoring"));
1412 xtensa_mark_literal_pool_location ();
1414 demand_empty_rest_of_line ();
1415 xtensa_clear_insn_labels ();
1419 /* Support .literal label, expr, ... */
1422 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1425 char *p
, *base_name
;
1429 if (inside_directive (directive_literal
))
1431 as_bad (_(".literal not allowed inside .begin literal region"));
1432 ignore_rest_of_line ();
1436 md_flush_pending_output ();
1438 /* Previous labels go with whatever follows this directive, not with
1439 the literal, so save them now. */
1440 saved_insn_labels
= insn_labels
;
1443 /* If we are using text-section literals, then this is the right value... */
1446 base_name
= input_line_pointer
;
1448 xtensa_switch_to_literal_fragment (&state
);
1450 /* ...but if we aren't using text-section-literals, then we
1451 need to put them in the section we just switched to. */
1452 if (use_literal_section
|| directive_state
[directive_absolute_literals
])
1455 /* All literals are aligned to four-byte boundaries. */
1456 frag_align (2, 0, 0);
1457 record_alignment (now_seg
, 2);
1459 c
= get_symbol_end ();
1460 /* Just after name is now '\0'. */
1461 p
= input_line_pointer
;
1465 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1467 as_bad (_("expected comma or colon after symbol name; "
1468 "rest of line ignored"));
1469 ignore_rest_of_line ();
1470 xtensa_restore_emit_state (&state
);
1478 input_line_pointer
++; /* skip ',' or ':' */
1480 xtensa_elf_cons (4);
1482 xtensa_restore_emit_state (&state
);
1484 /* Restore the list of current labels. */
1485 xtensa_clear_insn_labels ();
1486 insn_labels
= saved_insn_labels
;
1491 xtensa_literal_prefix (void)
1496 /* Parse the new prefix from the input_line_pointer. */
1498 len
= strspn (input_line_pointer
,
1499 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1500 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1502 /* Get a null-terminated copy of the name. */
1503 name
= xmalloc (len
+ 1);
1505 strncpy (name
, input_line_pointer
, len
);
1508 /* Skip the name in the input line. */
1509 input_line_pointer
+= len
;
1511 default_lit_sections
.lit_prefix
= name
;
1513 /* Clear cached literal sections, since the prefix has changed. */
1514 default_lit_sections
.lit_seg
= NULL
;
1515 default_lit_sections
.lit4_seg
= NULL
;
1519 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1522 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1524 float fall_through_f
, target_f
;
1526 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1527 if (fall_through_f
< 0)
1529 as_bad (_("fall through frequency must be greater than 0"));
1530 ignore_rest_of_line ();
1534 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1537 as_bad (_("branch target frequency must be greater than 0"));
1538 ignore_rest_of_line ();
1542 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1544 demand_empty_rest_of_line ();
1548 /* Like normal .long/.short/.word, except support @plt, etc.
1549 Clobbers input_line_pointer, checks end-of-line. */
1552 xtensa_elf_cons (int nbytes
)
1555 bfd_reloc_code_real_type reloc
;
1557 md_flush_pending_output ();
1559 if (cur_vinsn
.inside_bundle
)
1560 as_bad (_("directives are not valid inside bundles"));
1562 if (is_it_end_of_statement ())
1564 demand_empty_rest_of_line ();
1571 if (exp
.X_op
== O_symbol
1572 && *input_line_pointer
== '@'
1573 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1576 reloc_howto_type
*reloc_howto
=
1577 bfd_reloc_type_lookup (stdoutput
, reloc
);
1579 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1580 as_bad (_("unsupported relocation"));
1581 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1582 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1583 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1584 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1585 as_bad (_("opcode-specific %s relocation used outside "
1586 "an instruction"), reloc_howto
->name
);
1587 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1588 as_bad (_("%s relocations do not fit in %d bytes"),
1589 reloc_howto
->name
, nbytes
);
1590 else if (reloc
== BFD_RELOC_XTENSA_TLS_FUNC
1591 || reloc
== BFD_RELOC_XTENSA_TLS_ARG
1592 || reloc
== BFD_RELOC_XTENSA_TLS_CALL
)
1593 as_bad (_("invalid use of %s relocation"), reloc_howto
->name
);
1596 char *p
= frag_more ((int) nbytes
);
1597 xtensa_set_frag_assembly_state (frag_now
);
1598 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1599 nbytes
, &exp
, reloc_howto
->pc_relative
, reloc
);
1604 xtensa_set_frag_assembly_state (frag_now
);
1605 emit_expr (&exp
, (unsigned int) nbytes
);
1608 while (*input_line_pointer
++ == ',');
1610 input_line_pointer
--; /* Put terminator back into stream. */
1611 demand_empty_rest_of_line ();
1614 static bfd_boolean is_leb128_expr
;
1617 xtensa_leb128 (int sign
)
1619 is_leb128_expr
= TRUE
;
1621 is_leb128_expr
= FALSE
;
1625 /* Parsing and Idiom Translation. */
1627 /* Parse @plt, etc. and return the desired relocation. */
1628 static bfd_reloc_code_real_type
1629 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1636 struct suffix_reloc_map
*ptr
;
1639 return BFD_RELOC_NONE
;
1641 for (ch
= *str
, str2
= ident
;
1642 (str2
< ident
+ sizeof (ident
) - 1
1643 && (ISALNUM (ch
) || ch
== '@'));
1646 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1653 for (ptr
= &suffix_relocs
[0]; ptr
->length
> 0; ptr
++)
1654 if (ch
== ptr
->suffix
[0]
1655 && len
== ptr
->length
1656 && memcmp (ident
, ptr
->suffix
, ptr
->length
) == 0)
1658 /* Now check for "identifier@suffix+constant". */
1659 if (*str
== '-' || *str
== '+')
1661 char *orig_line
= input_line_pointer
;
1662 expressionS new_exp
;
1664 input_line_pointer
= str
;
1665 expression (&new_exp
);
1666 if (new_exp
.X_op
== O_constant
)
1668 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1669 str
= input_line_pointer
;
1672 if (&input_line_pointer
!= str_p
)
1673 input_line_pointer
= orig_line
;
1680 return BFD_RELOC_UNUSED
;
1684 /* Find the matching operator type. */
1685 static unsigned char
1686 map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc
)
1688 struct suffix_reloc_map
*sfx
;
1689 unsigned char operator = (unsigned char) -1;
1691 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1693 if (sfx
->reloc
== reloc
)
1695 operator = sfx
->operator;
1699 gas_assert (operator != (unsigned char) -1);
1704 /* Find the matching reloc type. */
1705 static bfd_reloc_code_real_type
1706 map_operator_to_reloc (unsigned char operator, bfd_boolean is_literal
)
1708 struct suffix_reloc_map
*sfx
;
1709 bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
1711 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1713 if (sfx
->operator == operator)
1722 if (reloc
== BFD_RELOC_XTENSA_TLS_FUNC
)
1723 return BFD_RELOC_XTENSA_TLSDESC_FN
;
1724 else if (reloc
== BFD_RELOC_XTENSA_TLS_ARG
)
1725 return BFD_RELOC_XTENSA_TLSDESC_ARG
;
1728 if (reloc
== BFD_RELOC_UNUSED
)
1729 return BFD_RELOC_32
;
1736 expression_end (const char *name
)
1759 #define ERROR_REG_NUM ((unsigned) -1)
1762 tc_get_register (const char *prefix
)
1765 const char *next_expr
;
1766 const char *old_line_pointer
;
1769 old_line_pointer
= input_line_pointer
;
1771 if (*input_line_pointer
== '$')
1772 ++input_line_pointer
;
1774 /* Accept "sp" as a synonym for "a1". */
1775 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1776 && expression_end (input_line_pointer
+ 2))
1778 input_line_pointer
+= 2;
1779 return 1; /* AR[1] */
1782 while (*input_line_pointer
++ == *prefix
++)
1784 --input_line_pointer
;
1789 as_bad (_("bad register name: %s"), old_line_pointer
);
1790 return ERROR_REG_NUM
;
1793 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1795 as_bad (_("bad register number: %s"), input_line_pointer
);
1796 return ERROR_REG_NUM
;
1801 while (ISDIGIT ((int) *input_line_pointer
))
1802 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1804 if (!(next_expr
= expression_end (input_line_pointer
)))
1806 as_bad (_("bad register name: %s"), old_line_pointer
);
1807 return ERROR_REG_NUM
;
1810 input_line_pointer
= (char *) next_expr
;
1817 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1819 xtensa_isa isa
= xtensa_default_isa
;
1821 /* Check if this is an immediate operand. */
1822 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1824 bfd_reloc_code_real_type reloc
;
1825 segT t
= expression (tok
);
1826 if (t
== absolute_section
1827 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1829 gas_assert (tok
->X_op
== O_constant
);
1830 tok
->X_op
= O_symbol
;
1831 tok
->X_add_symbol
= &abs_symbol
;
1834 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1835 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1840 case BFD_RELOC_LO16
:
1841 if (tok
->X_op
== O_constant
)
1843 tok
->X_add_number
&= 0xffff;
1847 case BFD_RELOC_HI16
:
1848 if (tok
->X_op
== O_constant
)
1850 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1854 case BFD_RELOC_UNUSED
:
1855 as_bad (_("unsupported relocation"));
1857 case BFD_RELOC_32_PCREL
:
1858 as_bad (_("pcrel relocation not allowed in an instruction"));
1863 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
1868 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1869 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1871 if (reg
!= ERROR_REG_NUM
) /* Already errored */
1874 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
1875 as_bad (_("register number out of range"));
1878 tok
->X_op
= O_register
;
1879 tok
->X_add_symbol
= 0;
1880 tok
->X_add_number
= reg
;
1885 /* Split up the arguments for an opcode or pseudo-op. */
1888 tokenize_arguments (char **args
, char *str
)
1890 char *old_input_line_pointer
;
1891 bfd_boolean saw_comma
= FALSE
;
1892 bfd_boolean saw_arg
= FALSE
;
1893 bfd_boolean saw_colon
= FALSE
;
1895 char *arg_end
, *arg
;
1898 /* Save and restore input_line_pointer around this function. */
1899 old_input_line_pointer
= input_line_pointer
;
1900 input_line_pointer
= str
;
1902 while (*input_line_pointer
)
1905 switch (*input_line_pointer
)
1912 input_line_pointer
++;
1913 if (saw_comma
|| saw_colon
|| !saw_arg
)
1919 input_line_pointer
++;
1920 if (saw_comma
|| saw_colon
|| !saw_arg
)
1926 if (!saw_comma
&& !saw_colon
&& saw_arg
)
1929 arg_end
= input_line_pointer
+ 1;
1930 while (!expression_end (arg_end
))
1933 arg_len
= arg_end
- input_line_pointer
;
1934 arg
= (char *) xmalloc ((saw_colon
? 1 : 0) + arg_len
+ 1);
1935 args
[num_args
] = arg
;
1939 strncpy (arg
, input_line_pointer
, arg_len
);
1940 arg
[arg_len
] = '\0';
1942 input_line_pointer
= arg_end
;
1952 if (saw_comma
|| saw_colon
)
1954 input_line_pointer
= old_input_line_pointer
;
1959 as_bad (_("extra comma"));
1961 as_bad (_("extra colon"));
1963 as_bad (_("missing argument"));
1965 as_bad (_("missing comma or colon"));
1966 input_line_pointer
= old_input_line_pointer
;
1971 /* Parse the arguments to an opcode. Return TRUE on error. */
1974 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
1976 expressionS
*tok
, *last_tok
;
1977 xtensa_opcode opcode
= insn
->opcode
;
1978 bfd_boolean had_error
= TRUE
;
1979 xtensa_isa isa
= xtensa_default_isa
;
1980 int n
, num_regs
= 0;
1981 int opcode_operand_count
;
1982 int opnd_cnt
, last_opnd_cnt
;
1983 unsigned int next_reg
= 0;
1984 char *old_input_line_pointer
;
1986 if (insn
->insn_type
== ITYPE_LITERAL
)
1987 opcode_operand_count
= 1;
1989 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
1992 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
1994 /* Save and restore input_line_pointer around this function. */
1995 old_input_line_pointer
= input_line_pointer
;
2001 /* Skip invisible operands. */
2002 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
2008 for (n
= 0; n
< num_args
; n
++)
2010 input_line_pointer
= arg_strings
[n
];
2011 if (*input_line_pointer
== ':')
2013 xtensa_regfile opnd_rf
;
2014 input_line_pointer
++;
2017 gas_assert (opnd_cnt
> 0);
2019 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
2021 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
2022 as_warn (_("incorrect register number, ignoring"));
2027 if (opnd_cnt
>= opcode_operand_count
)
2029 as_warn (_("too many arguments"));
2032 gas_assert (opnd_cnt
< MAX_INSN_ARGS
);
2034 expression_maybe_register (opcode
, opnd_cnt
, tok
);
2035 next_reg
= tok
->X_add_number
+ 1;
2037 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
2039 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
2041 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
2042 /* minus 1 because we are seeing one right now */
2048 last_opnd_cnt
= opnd_cnt
;
2049 demand_empty_rest_of_line ();
2056 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
2060 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
2063 insn
->ntok
= tok
- insn
->tok
;
2067 input_line_pointer
= old_input_line_pointer
;
2073 get_invisible_operands (TInsn
*insn
)
2075 xtensa_isa isa
= xtensa_default_isa
;
2076 static xtensa_insnbuf slotbuf
= NULL
;
2078 xtensa_opcode opc
= insn
->opcode
;
2079 int slot
, opnd
, fmt_found
;
2083 slotbuf
= xtensa_insnbuf_alloc (isa
);
2085 /* Find format/slot where this can be encoded. */
2088 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2090 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2092 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2098 if (fmt_found
) break;
2103 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2107 /* First encode all the visible operands
2108 (to deal with shared field operands). */
2109 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2111 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2112 && (insn
->tok
[opnd
].X_op
== O_register
2113 || insn
->tok
[opnd
].X_op
== O_constant
))
2115 val
= insn
->tok
[opnd
].X_add_number
;
2116 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2117 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2121 /* Then pull out the values for the invisible ones. */
2122 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2124 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2126 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2127 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2128 insn
->tok
[opnd
].X_add_number
= val
;
2129 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2130 insn
->tok
[opnd
].X_op
= O_register
;
2132 insn
->tok
[opnd
].X_op
= O_constant
;
2141 xg_reverse_shift_count (char **cnt_argp
)
2143 char *cnt_arg
, *new_arg
;
2144 cnt_arg
= *cnt_argp
;
2146 /* replace the argument with "31-(argument)" */
2147 new_arg
= (char *) xmalloc (strlen (cnt_arg
) + 6);
2148 sprintf (new_arg
, "31-(%s)", cnt_arg
);
2151 *cnt_argp
= new_arg
;
2155 /* If "arg" is a constant expression, return non-zero with the value
2159 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2162 char *save_ptr
= input_line_pointer
;
2164 input_line_pointer
= arg
;
2166 input_line_pointer
= save_ptr
;
2168 if (exp
.X_op
== O_constant
)
2170 *valp
= exp
.X_add_number
;
2179 xg_replace_opname (char **popname
, char *newop
)
2182 *popname
= (char *) xmalloc (strlen (newop
) + 1);
2183 strcpy (*popname
, newop
);
2188 xg_check_num_args (int *pnum_args
,
2193 int num_args
= *pnum_args
;
2195 if (num_args
< expected_num
)
2197 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2198 num_args
, opname
, expected_num
);
2202 if (num_args
> expected_num
)
2204 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2205 num_args
, opname
, expected_num
);
2206 while (num_args
-- > expected_num
)
2208 free (arg_strings
[num_args
]);
2209 arg_strings
[num_args
] = 0;
2211 *pnum_args
= expected_num
;
2219 /* If the register is not specified as part of the opcode,
2220 then get it from the operand and move it to the opcode. */
2223 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2225 xtensa_isa isa
= xtensa_default_isa
;
2227 char *opname
, *new_opname
;
2228 const char *sr_name
;
2229 int is_user
, is_write
;
2234 is_user
= (opname
[1] == 'u');
2235 is_write
= (opname
[0] == 'w');
2237 /* Opname == [rw]ur or [rwx]sr... */
2239 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2242 /* Check if the argument is a symbolic register name. */
2243 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2244 /* Handle WSR to "INTSET" as a special case. */
2245 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2246 && !strcasecmp (arg_strings
[1], "intset"))
2247 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2248 if (sr
== XTENSA_UNDEFINED
2249 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2251 /* Maybe it's a register number.... */
2253 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2255 as_bad (_("invalid register '%s' for '%s' instruction"),
2256 arg_strings
[1], opname
);
2259 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2260 if (sr
== XTENSA_UNDEFINED
)
2262 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2263 (long) val
, opname
);
2268 /* Remove the last argument, which is now part of the opcode. */
2269 free (arg_strings
[1]);
2273 /* Translate the opcode. */
2274 sr_name
= xtensa_sysreg_name (isa
, sr
);
2275 /* Another special case for "WSR.INTSET".... */
2276 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2278 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2279 sprintf (new_opname
, "%s.%s", *popname
, sr_name
);
2281 *popname
= new_opname
;
2288 xtensa_translate_old_userreg_ops (char **popname
)
2290 xtensa_isa isa
= xtensa_default_isa
;
2292 char *opname
, *new_opname
;
2293 const char *sr_name
;
2294 bfd_boolean has_underbar
= FALSE
;
2297 if (opname
[0] == '_')
2299 has_underbar
= TRUE
;
2303 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2304 if (sr
!= XTENSA_UNDEFINED
)
2306 /* The new default name ("nnn") is different from the old default
2307 name ("URnnn"). The old default is handled below, and we don't
2308 want to recognize [RW]nnn, so do nothing if the name is the (new)
2310 static char namebuf
[10];
2311 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2312 if (strcmp (namebuf
, opname
+ 1) == 0)
2320 /* Only continue if the reg name is "URnnn". */
2321 if (opname
[1] != 'u' || opname
[2] != 'r')
2323 val
= strtoul (opname
+ 3, &end
, 10);
2327 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2328 if (sr
== XTENSA_UNDEFINED
)
2330 as_bad (_("invalid register number (%ld) for '%s'"),
2331 (long) val
, opname
);
2336 /* Translate the opcode. */
2337 sr_name
= xtensa_sysreg_name (isa
, sr
);
2338 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2339 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2340 opname
[0], sr_name
);
2342 *popname
= new_opname
;
2349 xtensa_translate_zero_immed (char *old_op
,
2359 gas_assert (opname
[0] != '_');
2361 if (strcmp (opname
, old_op
) != 0)
2364 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2366 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2368 xg_replace_opname (popname
, new_op
);
2369 free (arg_strings
[1]);
2370 arg_strings
[1] = arg_strings
[2];
2379 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2380 Returns non-zero if an error was found. */
2383 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2385 char *opname
= *popname
;
2386 bfd_boolean has_underbar
= FALSE
;
2390 has_underbar
= TRUE
;
2394 if (strcmp (opname
, "mov") == 0)
2396 if (use_transform () && !has_underbar
&& density_supported
)
2397 xg_replace_opname (popname
, "mov.n");
2400 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2402 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2403 arg_strings
[2] = (char *) xmalloc (strlen (arg_strings
[1]) + 1);
2404 strcpy (arg_strings
[2], arg_strings
[1]);
2410 if (strcmp (opname
, "bbsi.l") == 0)
2412 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2414 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2415 if (target_big_endian
)
2416 xg_reverse_shift_count (&arg_strings
[1]);
2420 if (strcmp (opname
, "bbci.l") == 0)
2422 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2424 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2425 if (target_big_endian
)
2426 xg_reverse_shift_count (&arg_strings
[1]);
2430 /* Don't do anything special with NOPs inside FLIX instructions. They
2431 are handled elsewhere. Real NOP instructions are always available
2432 in configurations with FLIX, so this should never be an issue but
2433 check for it anyway. */
2434 if (!cur_vinsn
.inside_bundle
&& xtensa_nop_opcode
== XTENSA_UNDEFINED
2435 && strcmp (opname
, "nop") == 0)
2437 if (use_transform () && !has_underbar
&& density_supported
)
2438 xg_replace_opname (popname
, "nop.n");
2441 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2443 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2444 arg_strings
[0] = (char *) xmalloc (3);
2445 arg_strings
[1] = (char *) xmalloc (3);
2446 arg_strings
[2] = (char *) xmalloc (3);
2447 strcpy (arg_strings
[0], "a1");
2448 strcpy (arg_strings
[1], "a1");
2449 strcpy (arg_strings
[2], "a1");
2455 /* Recognize [RW]UR and [RWX]SR. */
2456 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2457 && (opname
[1] == 'u' || opname
[1] == 's'))
2458 || (opname
[0] == 'x' && opname
[1] == 's'))
2460 && opname
[3] == '\0')
2461 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2463 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2464 [RW]<name> if <name> is the non-default name of a user register. */
2465 if ((opname
[0] == 'r' || opname
[0] == 'w')
2466 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2467 return xtensa_translate_old_userreg_ops (popname
);
2469 /* Relax branches that don't allow comparisons against an immediate value
2470 of zero to the corresponding branches with implicit zero immediates. */
2471 if (!has_underbar
&& use_transform ())
2473 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2474 pnum_args
, arg_strings
))
2477 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2478 pnum_args
, arg_strings
))
2481 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2482 pnum_args
, arg_strings
))
2485 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2486 pnum_args
, arg_strings
))
2494 /* Functions for dealing with the Xtensa ISA. */
2496 /* Currently the assembler only allows us to use a single target per
2497 fragment. Because of this, only one operand for a given
2498 instruction may be symbolic. If there is a PC-relative operand,
2499 the last one is chosen. Otherwise, the result is the number of the
2500 last immediate operand, and if there are none of those, we fail and
2504 get_relaxable_immed (xtensa_opcode opcode
)
2506 int last_immed
= -1;
2509 if (opcode
== XTENSA_UNDEFINED
)
2512 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2513 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2515 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2517 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2519 if (last_immed
== -1
2520 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2527 static xtensa_opcode
2528 get_opcode_from_buf (const char *buf
, int slot
)
2530 static xtensa_insnbuf insnbuf
= NULL
;
2531 static xtensa_insnbuf slotbuf
= NULL
;
2532 xtensa_isa isa
= xtensa_default_isa
;
2537 insnbuf
= xtensa_insnbuf_alloc (isa
);
2538 slotbuf
= xtensa_insnbuf_alloc (isa
);
2541 xtensa_insnbuf_from_chars (isa
, insnbuf
, (const unsigned char *) buf
, 0);
2542 fmt
= xtensa_format_decode (isa
, insnbuf
);
2543 if (fmt
== XTENSA_UNDEFINED
)
2544 return XTENSA_UNDEFINED
;
2546 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2547 return XTENSA_UNDEFINED
;
2549 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2550 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2554 #ifdef TENSILICA_DEBUG
2556 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2559 xtensa_print_insn_table (void)
2561 int num_opcodes
, num_operands
;
2562 xtensa_opcode opcode
;
2563 xtensa_isa isa
= xtensa_default_isa
;
2565 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2566 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2569 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2570 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2571 for (opn
= 0; opn
< num_operands
; opn
++)
2573 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2575 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2577 xtensa_regfile opnd_rf
=
2578 xtensa_operand_regfile (isa
, opcode
, opn
);
2579 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2581 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2582 fputs ("[lLr] ", stderr
);
2584 fputs ("i ", stderr
);
2586 fprintf (stderr
, "\n");
2592 print_vliw_insn (xtensa_insnbuf vbuf
)
2594 xtensa_isa isa
= xtensa_default_isa
;
2595 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2596 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2599 fprintf (stderr
, "format = %d\n", f
);
2601 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2603 xtensa_opcode opcode
;
2607 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2608 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2609 opname
= xtensa_opcode_name (isa
, opcode
);
2611 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2612 fprintf (stderr
, " operands = ");
2614 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2618 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2620 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2621 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2622 fprintf (stderr
, "%d ", val
);
2624 fprintf (stderr
, "\n");
2626 xtensa_insnbuf_free (isa
, sbuf
);
2629 #endif /* TENSILICA_DEBUG */
2633 is_direct_call_opcode (xtensa_opcode opcode
)
2635 xtensa_isa isa
= xtensa_default_isa
;
2636 int n
, num_operands
;
2638 if (xtensa_opcode_is_call (isa
, opcode
) != 1)
2641 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2642 for (n
= 0; n
< num_operands
; n
++)
2644 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2645 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2652 /* Convert from BFD relocation type code to slot and operand number.
2653 Returns non-zero on failure. */
2656 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2658 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2659 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2661 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2664 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2665 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2667 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2677 /* Convert from slot number to BFD relocation type code for the
2678 standard PC-relative relocations. Return BFD_RELOC_NONE on
2681 static bfd_reloc_code_real_type
2682 encode_reloc (int slot
)
2684 if (slot
< 0 || slot
> 14)
2685 return BFD_RELOC_NONE
;
2687 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2691 /* Convert from slot numbers to BFD relocation type code for the
2692 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2694 static bfd_reloc_code_real_type
2695 encode_alt_reloc (int slot
)
2697 if (slot
< 0 || slot
> 14)
2698 return BFD_RELOC_NONE
;
2700 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2705 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2708 xtensa_opcode opcode
,
2714 uint32 valbuf
= value
;
2716 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2718 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2720 as_bad_where ((char *) file
, line
,
2721 _("operand %d of '%s' has out of range value '%u'"),
2723 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2726 as_bad_where ((char *) file
, line
,
2727 _("operand %d of '%s' has invalid value '%u'"),
2729 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2734 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2740 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2743 xtensa_opcode opcode
,
2747 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2748 fmt
, slot
, slotbuf
, &val
);
2749 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2754 /* Checks for rules from xtensa-relax tables. */
2756 /* The routine xg_instruction_matches_option_term must return TRUE
2757 when a given option term is true. The meaning of all of the option
2758 terms is given interpretation by this function. */
2761 xg_instruction_matches_option_term (TInsn
*insn
, const ReqOrOption
*option
)
2763 if (strcmp (option
->option_name
, "realnop") == 0
2764 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2766 /* These conditions were evaluated statically when building the
2767 relaxation table. There's no need to reevaluate them now. */
2770 else if (strcmp (option
->option_name
, "FREEREG") == 0)
2771 return insn
->extra_arg
.X_op
== O_register
;
2774 as_fatal (_("internal error: unknown option name '%s'"),
2775 option
->option_name
);
2781 xg_instruction_matches_or_options (TInsn
*insn
,
2782 const ReqOrOptionList
*or_option
)
2784 const ReqOrOption
*option
;
2785 /* Must match each of the AND terms. */
2786 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2788 if (xg_instruction_matches_option_term (insn
, option
))
2796 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2798 const ReqOption
*req_options
;
2799 /* Must match each of the AND terms. */
2800 for (req_options
= options
;
2801 req_options
!= NULL
;
2802 req_options
= req_options
->next
)
2804 /* Must match one of the OR clauses. */
2805 if (!xg_instruction_matches_or_options (insn
,
2806 req_options
->or_option_terms
))
2813 /* Return the transition rule that matches or NULL if none matches. */
2816 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2818 PreconditionList
*condition_l
;
2820 if (rule
->opcode
!= insn
->opcode
)
2823 for (condition_l
= rule
->conditions
;
2824 condition_l
!= NULL
;
2825 condition_l
= condition_l
->next
)
2829 Precondition
*cond
= condition_l
->precond
;
2834 /* The expression must be the constant. */
2835 gas_assert (cond
->op_num
< insn
->ntok
);
2836 exp1
= &insn
->tok
[cond
->op_num
];
2837 if (expr_is_const (exp1
))
2842 if (get_expr_const (exp1
) != cond
->op_data
)
2846 if (get_expr_const (exp1
) == cond
->op_data
)
2853 else if (expr_is_register (exp1
))
2858 if (get_expr_register (exp1
) != cond
->op_data
)
2862 if (get_expr_register (exp1
) == cond
->op_data
)
2874 gas_assert (cond
->op_num
< insn
->ntok
);
2875 gas_assert (cond
->op_data
< insn
->ntok
);
2876 exp1
= &insn
->tok
[cond
->op_num
];
2877 exp2
= &insn
->tok
[cond
->op_data
];
2882 if (!expr_is_equal (exp1
, exp2
))
2886 if (expr_is_equal (exp1
, exp2
))
2898 if (!xg_instruction_matches_options (insn
, rule
->options
))
2906 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
2908 bfd_boolean a_greater
= FALSE
;
2909 bfd_boolean b_greater
= FALSE
;
2911 ReqOptionList
*l_a
= a
->options
;
2912 ReqOptionList
*l_b
= b
->options
;
2914 /* We only care if they both are the same except for
2915 a const16 vs. an l32r. */
2917 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2919 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
2920 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
2921 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2923 if (l_or_a
->is_true
!= l_or_b
->is_true
)
2925 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
2927 /* This is the case we care about. */
2928 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
2929 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
2936 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
2937 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
2947 l_or_a
= l_or_a
->next
;
2948 l_or_b
= l_or_b
->next
;
2950 if (l_or_a
|| l_or_b
)
2959 /* Incomparable if the substitution was used differently in two cases. */
2960 if (a_greater
&& b_greater
)
2972 static TransitionRule
*
2973 xg_instruction_match (TInsn
*insn
)
2975 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
2977 gas_assert (insn
->opcode
< table
->num_opcodes
);
2979 /* Walk through all of the possible transitions. */
2980 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2982 TransitionRule
*rule
= l
->rule
;
2983 if (xg_instruction_matches_rule (insn
, rule
))
2990 /* Various Other Internal Functions. */
2993 is_unique_insn_expansion (TransitionRule
*r
)
2995 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
2997 if (r
->to_instr
->typ
!= INSTR_INSTR
)
3003 /* Check if there is exactly one relaxation for INSN that converts it to
3004 another instruction of equal or larger size. If so, and if TARG is
3005 non-null, go ahead and generate the relaxed instruction into TARG. If
3006 NARROW_ONLY is true, then only consider relaxations that widen a narrow
3007 instruction, i.e., ignore relaxations that convert to an instruction of
3008 equal size. In some contexts where this function is used, only
3009 a single widening is allowed and the NARROW_ONLY argument is used to
3010 exclude cases like ADDI being "widened" to an ADDMI, which may
3011 later be relaxed to an ADDMI/ADDI pair. */
3014 xg_is_single_relaxable_insn (TInsn
*insn
, TInsn
*targ
, bfd_boolean narrow_only
)
3016 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3018 TransitionRule
*match
= 0;
3020 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3021 gas_assert (insn
->opcode
< table
->num_opcodes
);
3023 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3025 TransitionRule
*rule
= l
->rule
;
3027 if (xg_instruction_matches_rule (insn
, rule
)
3028 && is_unique_insn_expansion (rule
)
3029 && (xg_get_single_size (insn
->opcode
) + (narrow_only
? 1 : 0)
3030 <= xg_get_single_size (rule
->to_instr
->opcode
)))
3041 xg_build_to_insn (targ
, insn
, match
->to_instr
);
3046 /* Return the maximum number of bytes this opcode can expand to. */
3049 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
3051 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3053 int max_size
= xg_get_single_size (opcode
);
3055 gas_assert (opcode
< table
->num_opcodes
);
3057 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3059 TransitionRule
*rule
= l
->rule
;
3060 BuildInstr
*build_list
;
3065 build_list
= rule
->to_instr
;
3066 if (is_unique_insn_expansion (rule
))
3068 gas_assert (build_list
->typ
== INSTR_INSTR
);
3069 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
3072 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3074 switch (build_list
->typ
)
3077 this_size
+= xg_get_single_size (build_list
->opcode
);
3079 case INSTR_LITERAL_DEF
:
3080 case INSTR_LABEL_DEF
:
3085 if (this_size
> max_size
)
3086 max_size
= this_size
;
3092 /* Return the maximum number of literal bytes this opcode can generate. */
3095 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3097 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3101 gas_assert (opcode
< table
->num_opcodes
);
3103 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3105 TransitionRule
*rule
= l
->rule
;
3106 BuildInstr
*build_list
;
3111 build_list
= rule
->to_instr
;
3112 if (is_unique_insn_expansion (rule
))
3114 gas_assert (build_list
->typ
== INSTR_INSTR
);
3115 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3118 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3120 switch (build_list
->typ
)
3122 case INSTR_LITERAL_DEF
:
3123 /* Hard-coded 4-byte literal. */
3127 case INSTR_LABEL_DEF
:
3132 if (this_size
> max_size
)
3133 max_size
= this_size
;
3140 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3142 int steps_taken
= 0;
3143 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3146 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3147 gas_assert (insn
->opcode
< table
->num_opcodes
);
3149 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3151 TransitionRule
*rule
= l
->rule
;
3153 if (xg_instruction_matches_rule (insn
, rule
))
3155 if (steps_taken
== lateral_steps
)
3165 get_special_literal_symbol (void)
3167 static symbolS
*sym
= NULL
;
3170 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3176 get_special_label_symbol (void)
3178 static symbolS
*sym
= NULL
;
3181 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3187 xg_valid_literal_expression (const expressionS
*exp
)
3209 /* This will check to see if the value can be converted into the
3210 operand type. It will return TRUE if it does not fit. */
3213 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3215 uint32 valbuf
= value
;
3216 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3222 /* Assumes: All immeds are constants. Check that all constants fit
3223 into their immeds; return FALSE if not. */
3226 xg_immeds_fit (const TInsn
*insn
)
3228 xtensa_isa isa
= xtensa_default_isa
;
3232 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3233 for (i
= 0; i
< n
; ++i
)
3235 const expressionS
*expr
= &insn
->tok
[i
];
3236 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3243 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3248 /* The symbol should have a fixup associated with it. */
3257 /* This should only be called after we have an initial
3258 estimate of the addresses. */
3261 xg_symbolic_immeds_fit (const TInsn
*insn
,
3267 xtensa_isa isa
= xtensa_default_isa
;
3275 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3277 for (i
= 0; i
< n
; ++i
)
3279 const expressionS
*expr
= &insn
->tok
[i
];
3280 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3287 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3293 /* Check for the worst case. */
3294 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3299 /* We only allow symbols for PC-relative references.
3300 If pc_frag == 0, then we don't have frag locations yet. */
3302 || xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0)
3305 /* If it is a weak symbol or a symbol in a different section,
3306 it cannot be known to fit at assembly time. */
3307 if (S_IS_WEAK (expr
->X_add_symbol
)
3308 || S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3310 /* For a direct call with --no-longcalls, be optimistic and
3311 assume it will be in range. If the symbol is weak and
3312 undefined, it may remain undefined at link-time, in which
3313 case it will have a zero value and almost certainly be out
3314 of range for a direct call; thus, relax for undefined weak
3315 symbols even if longcalls is not enabled. */
3316 if (is_direct_call_opcode (insn
->opcode
)
3317 && ! pc_frag
->tc_frag_data
.use_longcalls
3318 && (! S_IS_WEAK (expr
->X_add_symbol
)
3319 || S_IS_DEFINED (expr
->X_add_symbol
)))
3325 symbolP
= expr
->X_add_symbol
;
3326 sym_frag
= symbol_get_frag (symbolP
);
3327 target
= S_GET_VALUE (symbolP
) + expr
->X_add_number
;
3328 pc
= pc_frag
->fr_address
+ pc_offset
;
3330 /* If frag has yet to be reached on this pass, assume it
3331 will move by STRETCH just as we did. If this is not so,
3332 it will be because some frag between grows, and that will
3333 force another pass. Beware zero-length frags. There
3334 should be a faster way to do this. */
3337 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3338 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3343 new_offset
= target
;
3344 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3345 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3350 /* The symbol should have a fixup associated with it. */
3359 /* Return TRUE on success. */
3362 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3368 targ
->debug_line
= insn
->debug_line
;
3369 targ
->loc_directive_seen
= insn
->loc_directive_seen
;
3374 targ
->opcode
= bi
->opcode
;
3375 targ
->insn_type
= ITYPE_INSN
;
3376 targ
->is_specific_opcode
= FALSE
;
3378 for (; op
!= NULL
; op
= op
->next
)
3380 int op_num
= op
->op_num
;
3381 int op_data
= op
->op_data
;
3383 gas_assert (op
->op_num
< MAX_INSN_ARGS
);
3385 if (targ
->ntok
<= op_num
)
3386 targ
->ntok
= op_num
+ 1;
3391 set_expr_const (&targ
->tok
[op_num
], op_data
);
3394 gas_assert (op_data
< insn
->ntok
);
3395 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3398 if (insn
->extra_arg
.X_op
!= O_register
)
3400 copy_expr (&targ
->tok
[op_num
], &insn
->extra_arg
);
3403 sym
= get_special_literal_symbol ();
3404 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3405 if (insn
->tok
[op_data
].X_op
== O_tlsfunc
3406 || insn
->tok
[op_data
].X_op
== O_tlsarg
)
3407 copy_expr (&targ
->extra_arg
, &insn
->tok
[op_data
]);
3410 sym
= get_special_label_symbol ();
3411 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3413 case OP_OPERAND_HI16U
:
3414 case OP_OPERAND_LOW16U
:
3415 gas_assert (op_data
< insn
->ntok
);
3416 if (expr_is_const (&insn
->tok
[op_data
]))
3419 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3420 val
= xg_apply_userdef_op_fn (op
->typ
,
3423 targ
->tok
[op_num
].X_add_number
= val
;
3427 /* For const16 we can create relocations for these. */
3428 if (targ
->opcode
== XTENSA_UNDEFINED
3429 || (targ
->opcode
!= xtensa_const16_opcode
))
3431 gas_assert (op_data
< insn
->ntok
);
3432 /* Need to build a O_lo16 or O_hi16. */
3433 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3434 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3436 if (op
->typ
== OP_OPERAND_HI16U
)
3437 targ
->tok
[op_num
].X_op
= O_hi16
;
3438 else if (op
->typ
== OP_OPERAND_LOW16U
)
3439 targ
->tok
[op_num
].X_op
= O_lo16
;
3446 /* currently handles:
3449 OP_OPERAND_F32MINUS */
3450 if (xg_has_userdef_op_fn (op
->typ
))
3452 gas_assert (op_data
< insn
->ntok
);
3453 if (expr_is_const (&insn
->tok
[op_data
]))
3456 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3457 val
= xg_apply_userdef_op_fn (op
->typ
,
3460 targ
->tok
[op_num
].X_add_number
= val
;
3463 return FALSE
; /* We cannot use a relocation for this. */
3472 case INSTR_LITERAL_DEF
:
3474 targ
->opcode
= XTENSA_UNDEFINED
;
3475 targ
->insn_type
= ITYPE_LITERAL
;
3476 targ
->is_specific_opcode
= FALSE
;
3477 for (; op
!= NULL
; op
= op
->next
)
3479 int op_num
= op
->op_num
;
3480 int op_data
= op
->op_data
;
3481 gas_assert (op
->op_num
< MAX_INSN_ARGS
);
3483 if (targ
->ntok
<= op_num
)
3484 targ
->ntok
= op_num
+ 1;
3489 gas_assert (op_data
< insn
->ntok
);
3490 /* We can only pass resolvable literals through. */
3491 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3493 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3505 case INSTR_LABEL_DEF
:
3507 targ
->opcode
= XTENSA_UNDEFINED
;
3508 targ
->insn_type
= ITYPE_LABEL
;
3509 targ
->is_specific_opcode
= FALSE
;
3510 /* Literal with no ops is a label? */
3511 gas_assert (op
== NULL
);
3522 /* Return TRUE on success. */
3525 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3527 for (; bi
!= NULL
; bi
= bi
->next
)
3529 TInsn
*next_insn
= istack_push_space (istack
);
3531 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3538 /* Return TRUE on valid expansion. */
3541 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3543 int stack_size
= istack
->ninsn
;
3544 int steps_taken
= 0;
3545 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3548 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3549 gas_assert (insn
->opcode
< table
->num_opcodes
);
3551 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3553 TransitionRule
*rule
= l
->rule
;
3555 if (xg_instruction_matches_rule (insn
, rule
))
3557 if (lateral_steps
== steps_taken
)
3561 /* This is it. Expand the rule to the stack. */
3562 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3565 /* Check to see if it fits. */
3566 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3568 TInsn
*insn
= &istack
->insn
[i
];
3570 if (insn
->insn_type
== ITYPE_INSN
3571 && !tinsn_has_symbolic_operands (insn
)
3572 && !xg_immeds_fit (insn
))
3574 istack
->ninsn
= stack_size
;
3587 /* Relax the assembly instruction at least "min_steps".
3588 Return the number of steps taken.
3590 For relaxation to correctly terminate, every relaxation chain must
3591 terminate in one of two ways:
3593 1. If the chain from one instruction to the next consists entirely of
3594 single instructions, then the chain *must* handle all possible
3595 immediates without failing. It must not ever fail because an
3596 immediate is out of range. The MOVI.N -> MOVI -> L32R relaxation
3597 chain is one example. L32R loads 32 bits, and there cannot be an
3598 immediate larger than 32 bits, so it satisfies this condition.
3599 Single instruction relaxation chains are as defined by
3600 xg_is_single_relaxable_instruction.
3602 2. Otherwise, the chain must end in a multi-instruction expansion: e.g.,
3603 BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J
3605 Strictly speaking, in most cases you can violate condition 1 and be OK
3606 -- in particular when the last two instructions have the same single
3607 size. But nevertheless, you should guarantee the above two conditions.
3609 We could fix this so that single-instruction expansions correctly
3610 terminate when they can't handle the range, but the error messages are
3611 worse, and it actually turns out that in every case but one (18-bit wide
3612 branches), you need a multi-instruction expansion to get the full range
3613 anyway. And because 18-bit branches are handled identically to 15-bit
3614 branches, there isn't any point in changing it. */
3617 xg_assembly_relax (IStack
*istack
,
3620 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3621 offsetT pc_offset
, /* offset in fragment */
3622 int min_steps
, /* minimum conversion steps */
3623 long stretch
) /* number of bytes stretched so far */
3625 int steps_taken
= 0;
3627 /* Some of its immeds don't fit. Try to build a relaxed version.
3628 This may go through a couple of stages of single instruction
3629 transformations before we get there. */
3631 TInsn single_target
;
3633 int lateral_steps
= 0;
3634 int istack_size
= istack
->ninsn
;
3636 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3637 && steps_taken
>= min_steps
)
3639 istack_push (istack
, insn
);
3642 current_insn
= *insn
;
3644 /* Walk through all of the single instruction expansions. */
3645 while (xg_is_single_relaxable_insn (¤t_insn
, &single_target
, FALSE
))
3648 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3651 if (steps_taken
>= min_steps
)
3653 istack_push (istack
, &single_target
);
3657 current_insn
= single_target
;
3660 /* Now check for a multi-instruction expansion. */
3661 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3663 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3666 if (steps_taken
>= min_steps
)
3668 istack_push (istack
, ¤t_insn
);
3673 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3675 if (steps_taken
>= min_steps
)
3679 istack
->ninsn
= istack_size
;
3682 /* It's not going to work -- use the original. */
3683 istack_push (istack
, insn
);
3689 xg_finish_frag (char *last_insn
,
3690 enum xtensa_relax_statesE frag_state
,
3691 enum xtensa_relax_statesE slot0_state
,
3693 bfd_boolean is_insn
)
3695 /* Finish off this fragment so that it has at LEAST the desired
3696 max_growth. If it doesn't fit in this fragment, close this one
3697 and start a new one. In either case, return a pointer to the
3698 beginning of the growth area. */
3702 frag_grow (max_growth
);
3703 old_frag
= frag_now
;
3705 frag_now
->fr_opcode
= last_insn
;
3707 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3709 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3710 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3712 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3713 xtensa_set_frag_assembly_state (frag_now
);
3715 /* Just to make sure that we did not split it up. */
3716 gas_assert (old_frag
->fr_next
== frag_now
);
3720 /* Return TRUE if the target frag is one of the next non-empty frags. */
3723 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3728 for (; fragP
; fragP
= fragP
->fr_next
)
3730 if (fragP
== target
)
3732 if (fragP
->fr_fix
!= 0)
3734 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3736 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3737 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3739 if (fragP
->fr_type
== rs_space
)
3747 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3749 xtensa_isa isa
= xtensa_default_isa
;
3751 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3756 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) != 1
3757 && xtensa_opcode_is_jump (isa
, insn
->opcode
) != 1)
3760 for (i
= 0; i
< num_ops
; i
++)
3762 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3768 if (target_op
== -1)
3771 if (insn
->ntok
<= target_op
)
3774 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3777 sym
= insn
->tok
[target_op
].X_add_symbol
;
3781 if (insn
->tok
[target_op
].X_add_number
!= 0)
3784 target_frag
= symbol_get_frag (sym
);
3785 if (target_frag
== NULL
)
3788 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3789 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3797 xg_add_branch_and_loop_targets (TInsn
*insn
)
3799 xtensa_isa isa
= xtensa_default_isa
;
3800 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3802 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3805 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3806 && insn
->tok
[i
].X_op
== O_symbol
)
3807 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3811 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3812 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3816 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3818 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3819 && insn
->tok
[i
].X_op
== O_symbol
)
3821 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3822 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3823 if (S_IS_DEFINED (sym
))
3824 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3831 /* Return FALSE if no error. */
3834 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3839 switch (instr_spec
->typ
)
3842 new_insn
->insn_type
= ITYPE_INSN
;
3843 new_insn
->opcode
= instr_spec
->opcode
;
3845 case INSTR_LITERAL_DEF
:
3846 new_insn
->insn_type
= ITYPE_LITERAL
;
3847 new_insn
->opcode
= XTENSA_UNDEFINED
;
3849 case INSTR_LABEL_DEF
:
3852 new_insn
->is_specific_opcode
= FALSE
;
3853 new_insn
->debug_line
= old_insn
->debug_line
;
3854 new_insn
->loc_directive_seen
= old_insn
->loc_directive_seen
;
3856 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3859 const expressionS
*src_exp
;
3865 /* The expression must be the constant. */
3866 gas_assert (b_op
->op_num
< MAX_INSN_ARGS
);
3867 exp
= &new_insn
->tok
[b_op
->op_num
];
3868 set_expr_const (exp
, b_op
->op_data
);
3872 gas_assert (b_op
->op_num
< MAX_INSN_ARGS
);
3873 gas_assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
3874 src_exp
= &old_insn
->tok
[b_op
->op_data
];
3875 exp
= &new_insn
->tok
[b_op
->op_num
];
3876 copy_expr (exp
, src_exp
);
3881 as_bad (_("can't handle generation of literal/labels yet"));
3885 as_bad (_("can't handle undefined OP TYPE"));
3890 new_insn
->ntok
= num_ops
;
3895 /* Return TRUE if it was simplified. */
3898 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
3900 TransitionRule
*rule
;
3901 BuildInstr
*insn_spec
;
3903 if (old_insn
->is_specific_opcode
|| !density_supported
)
3906 rule
= xg_instruction_match (old_insn
);
3910 insn_spec
= rule
->to_instr
;
3911 /* There should only be one. */
3912 gas_assert (insn_spec
!= NULL
);
3913 gas_assert (insn_spec
->next
== NULL
);
3914 if (insn_spec
->next
!= NULL
)
3917 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
3923 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3924 l32i.n. (2) Check the number of operands. (3) Place the instruction
3925 tokens into the stack or relax it and place multiple
3926 instructions/literals onto the stack. Return FALSE if no error. */
3929 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
3933 bfd_boolean do_expand
;
3935 tinsn_init (&new_insn
);
3937 /* Narrow it if we can. xg_simplify_insn now does all the
3938 appropriate checking (e.g., for the density option). */
3939 if (xg_simplify_insn (orig_insn
, &new_insn
))
3940 orig_insn
= &new_insn
;
3942 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
3944 if (orig_insn
->ntok
< noperands
)
3946 as_bad (_("found %d operands for '%s': Expected %d"),
3948 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3952 if (orig_insn
->ntok
> noperands
)
3953 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
3955 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3958 /* If there are not enough operands, we will assert above. If there
3959 are too many, just cut out the extras here. */
3960 orig_insn
->ntok
= noperands
;
3962 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
3965 /* Special case for extui opcode which has constraints not handled
3966 by the ordinary operand encoding checks. The number of operands
3967 and related syntax issues have already been checked. */
3968 if (orig_insn
->opcode
== xtensa_extui_opcode
)
3970 int shiftimm
= orig_insn
->tok
[2].X_add_number
;
3971 int maskimm
= orig_insn
->tok
[3].X_add_number
;
3972 if (shiftimm
+ maskimm
> 32)
3974 as_bad (_("immediate operands sum to greater than 32"));
3979 /* If the instruction will definitely need to be relaxed, it is better
3980 to expand it now for better scheduling. Decide whether to expand
3982 do_expand
= (!orig_insn
->is_specific_opcode
&& use_transform ());
3984 /* Calls should be expanded to longcalls only in the backend relaxation
3985 so that the assembly scheduler will keep the L32R/CALLX instructions
3987 if (is_direct_call_opcode (orig_insn
->opcode
))
3990 if (tinsn_has_symbolic_operands (orig_insn
))
3992 /* The values of symbolic operands are not known yet, so only expand
3993 now if an operand is "complex" (e.g., difference of symbols) and
3994 will have to be stored as a literal regardless of the value. */
3995 if (!tinsn_has_complex_operands (orig_insn
))
3998 else if (xg_immeds_fit (orig_insn
))
4002 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
4004 istack_push (istack
, orig_insn
);
4010 /* Return TRUE if the section flags are marked linkonce
4011 or the name is .gnu.linkonce.*. */
4013 static int linkonce_len
= sizeof (".gnu.linkonce.") - 1;
4016 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
4018 flagword flags
, link_once_flags
;
4020 flags
= bfd_get_section_flags (abfd
, sec
);
4021 link_once_flags
= (flags
& SEC_LINK_ONCE
);
4023 /* Flags might not be set yet. */
4024 if (!link_once_flags
4025 && strncmp (segment_name (sec
), ".gnu.linkonce.", linkonce_len
) == 0)
4026 link_once_flags
= SEC_LINK_ONCE
;
4028 return (link_once_flags
!= 0);
4033 xtensa_add_literal_sym (symbolS
*sym
)
4037 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
4039 l
->next
= literal_syms
;
4045 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
4047 static int lit_num
= 0;
4048 static char name
[256];
4051 sprintf (name
, ".L_lit_sym%d", lit_num
);
4053 /* Create a local symbol. If it is in a linkonce section, we have to
4054 be careful to make sure that if it is used in a relocation that the
4055 symbol will be in the output file. */
4056 if (get_is_linkonce_section (stdoutput
, sec
))
4058 symbolP
= symbol_new (name
, sec
, 0, frag
);
4059 S_CLEAR_EXTERNAL (symbolP
);
4060 /* symbolP->local = 1; */
4063 symbolP
= symbol_new (name
, sec
, 0, frag
);
4065 xtensa_add_literal_sym (symbolP
);
4072 /* Currently all literals that are generated here are 32-bit L32R targets. */
4075 xg_assemble_literal (/* const */ TInsn
*insn
)
4078 symbolS
*lit_sym
= NULL
;
4079 bfd_reloc_code_real_type reloc
;
4080 bfd_boolean pcrel
= FALSE
;
4083 /* size = 4 for L32R. It could easily be larger when we move to
4084 larger constants. Add a parameter later. */
4085 offsetT litsize
= 4;
4086 offsetT litalign
= 2; /* 2^2 = 4 */
4087 expressionS saved_loc
;
4088 expressionS
* emit_val
;
4090 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
4092 gas_assert (insn
->insn_type
== ITYPE_LITERAL
);
4093 gas_assert (insn
->ntok
== 1); /* must be only one token here */
4095 xtensa_switch_to_literal_fragment (&state
);
4097 emit_val
= &insn
->tok
[0];
4098 if (emit_val
->X_op
== O_big
)
4100 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
4103 /* This happens when someone writes a "movi a2, big_number". */
4104 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4105 _("invalid immediate"));
4106 xtensa_restore_emit_state (&state
);
4111 /* Force a 4-byte align here. Note that this opens a new frag, so all
4112 literals done with this function have a frag to themselves. That's
4113 important for the way text section literals work. */
4114 frag_align (litalign
, 0, 0);
4115 record_alignment (now_seg
, litalign
);
4117 switch (emit_val
->X_op
)
4127 p
= frag_more (litsize
);
4128 xtensa_set_frag_assembly_state (frag_now
);
4129 reloc
= map_operator_to_reloc (emit_val
->X_op
, TRUE
);
4130 if (emit_val
->X_add_symbol
)
4131 emit_val
->X_op
= O_symbol
;
4133 emit_val
->X_op
= O_constant
;
4134 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
4135 litsize
, emit_val
, pcrel
, reloc
);
4139 emit_expr (emit_val
, litsize
);
4143 gas_assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
4144 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4145 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4146 lit_sym
= frag_now
->fr_symbol
;
4149 xtensa_restore_emit_state (&state
);
4155 xg_assemble_literal_space (/* const */ int size
, int slot
)
4158 /* We might have to do something about this alignment. It only
4159 takes effect if something is placed here. */
4160 offsetT litalign
= 2; /* 2^2 = 4 */
4161 fragS
*lit_saved_frag
;
4163 gas_assert (size
% 4 == 0);
4165 xtensa_switch_to_literal_fragment (&state
);
4167 /* Force a 4-byte align here. */
4168 frag_align (litalign
, 0, 0);
4169 record_alignment (now_seg
, litalign
);
4173 lit_saved_frag
= frag_now
;
4174 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4175 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4176 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4179 xtensa_restore_emit_state (&state
);
4180 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4184 /* Put in a fixup record based on the opcode.
4185 Return TRUE on success. */
4188 xg_add_opcode_fix (TInsn
*tinsn
,
4196 xtensa_opcode opcode
= tinsn
->opcode
;
4197 bfd_reloc_code_real_type reloc
;
4198 reloc_howto_type
*howto
;
4202 reloc
= BFD_RELOC_NONE
;
4204 /* First try the special cases for "alternate" relocs. */
4205 if (opcode
== xtensa_l32r_opcode
)
4207 if (fragP
->tc_frag_data
.use_absolute_literals
)
4208 reloc
= encode_alt_reloc (slot
);
4210 else if (opcode
== xtensa_const16_opcode
)
4212 if (expr
->X_op
== O_lo16
)
4214 reloc
= encode_reloc (slot
);
4215 expr
->X_op
= O_symbol
;
4217 else if (expr
->X_op
== O_hi16
)
4219 reloc
= encode_alt_reloc (slot
);
4220 expr
->X_op
= O_symbol
;
4224 if (opnum
!= get_relaxable_immed (opcode
))
4226 as_bad (_("invalid relocation for operand %i of '%s'"),
4227 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4231 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4232 into the symbol table where the generic portions of the assembler
4233 won't know what to do with them. */
4234 if (expr
->X_op
== O_lo16
|| expr
->X_op
== O_hi16
)
4236 as_bad (_("invalid expression for operand %i of '%s'"),
4237 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4241 /* Next try the generic relocs. */
4242 if (reloc
== BFD_RELOC_NONE
)
4243 reloc
= encode_reloc (slot
);
4244 if (reloc
== BFD_RELOC_NONE
)
4246 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4250 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4253 as_bad (_("undefined symbol for opcode \"%s\""),
4254 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4258 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4259 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, expr
,
4260 howto
->pc_relative
, reloc
);
4261 the_fix
->fx_no_overflow
= 1;
4262 the_fix
->tc_fix_data
.X_add_symbol
= expr
->X_add_symbol
;
4263 the_fix
->tc_fix_data
.X_add_number
= expr
->X_add_number
;
4264 the_fix
->tc_fix_data
.slot
= slot
;
4271 xg_emit_insn_to_buf (TInsn
*tinsn
,
4275 bfd_boolean build_fix
)
4277 static xtensa_insnbuf insnbuf
= NULL
;
4278 bfd_boolean has_symbolic_immed
= FALSE
;
4279 bfd_boolean ok
= TRUE
;
4282 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4284 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4285 if (has_symbolic_immed
&& build_fix
)
4288 xtensa_format fmt
= xg_get_single_format (tinsn
->opcode
);
4289 int slot
= xg_get_single_slot (tinsn
->opcode
);
4290 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4291 expressionS
*exp
= &tinsn
->tok
[opnum
];
4293 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, slot
, exp
, fragP
, offset
))
4296 fragP
->tc_frag_data
.is_insn
= TRUE
;
4297 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4298 (unsigned char *) buf
, 0);
4304 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4306 symbolS
*sym
= get_special_literal_symbol ();
4310 gas_assert (insn
->insn_type
== ITYPE_INSN
);
4311 for (i
= 0; i
< insn
->ntok
; i
++)
4312 if (insn
->tok
[i
].X_add_symbol
== sym
)
4313 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4319 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4321 symbolS
*sym
= get_special_label_symbol ();
4323 for (i
= 0; i
< insn
->ntok
; i
++)
4324 if (insn
->tok
[i
].X_add_symbol
== sym
)
4325 insn
->tok
[i
].X_add_symbol
= label_sym
;
4330 /* Return TRUE if the instruction can write to the specified
4331 integer register. */
4334 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4338 xtensa_isa isa
= xtensa_default_isa
;
4340 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4342 for (i
= 0; i
< num_ops
; i
++)
4345 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4346 if ((inout
== 'o' || inout
== 'm')
4347 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4349 xtensa_regfile opnd_rf
=
4350 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4351 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4353 if ((insn
->tok
[i
].X_op
== O_register
)
4354 && (insn
->tok
[i
].X_add_number
== regnum
))
4364 is_bad_loopend_opcode (const TInsn
*tinsn
)
4366 xtensa_opcode opcode
= tinsn
->opcode
;
4368 if (opcode
== XTENSA_UNDEFINED
)
4371 if (opcode
== xtensa_call0_opcode
4372 || opcode
== xtensa_callx0_opcode
4373 || opcode
== xtensa_call4_opcode
4374 || opcode
== xtensa_callx4_opcode
4375 || opcode
== xtensa_call8_opcode
4376 || opcode
== xtensa_callx8_opcode
4377 || opcode
== xtensa_call12_opcode
4378 || opcode
== xtensa_callx12_opcode
4379 || opcode
== xtensa_isync_opcode
4380 || opcode
== xtensa_ret_opcode
4381 || opcode
== xtensa_ret_n_opcode
4382 || opcode
== xtensa_retw_opcode
4383 || opcode
== xtensa_retw_n_opcode
4384 || opcode
== xtensa_waiti_opcode
4385 || opcode
== xtensa_rsr_lcount_opcode
)
4392 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4393 This allows the debugger to add unaligned labels.
4394 Also, the assembler generates stabs labels that need
4395 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4398 is_unaligned_label (symbolS
*sym
)
4400 const char *name
= S_GET_NAME (sym
);
4401 static size_t fake_size
= 0;
4405 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4408 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4410 fake_size
= strlen (FAKE_LABEL_NAME
);
4413 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4414 && (name
[fake_size
] == 'F'
4415 || name
[fake_size
] == 'L'
4416 || (name
[fake_size
] == 'e'
4417 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4425 next_non_empty_frag (const fragS
*fragP
)
4427 fragS
*next_fragP
= fragP
->fr_next
;
4429 /* Sometimes an empty will end up here due storage allocation issues.
4430 So we have to skip until we find something legit. */
4431 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4432 next_fragP
= next_fragP
->fr_next
;
4434 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4442 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4444 xtensa_opcode out_opcode
;
4445 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4447 if (next_fragP
== NULL
)
4450 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4451 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4453 *opcode
= out_opcode
;
4461 frag_format_size (const fragS
*fragP
)
4463 static xtensa_insnbuf insnbuf
= NULL
;
4464 xtensa_isa isa
= xtensa_default_isa
;
4469 insnbuf
= xtensa_insnbuf_alloc (isa
);
4472 return XTENSA_UNDEFINED
;
4474 xtensa_insnbuf_from_chars (isa
, insnbuf
,
4475 (unsigned char *) fragP
->fr_literal
, 0);
4477 fmt
= xtensa_format_decode (isa
, insnbuf
);
4478 if (fmt
== XTENSA_UNDEFINED
)
4479 return XTENSA_UNDEFINED
;
4480 fmt_size
= xtensa_format_length (isa
, fmt
);
4482 /* If the next format won't be changing due to relaxation, just
4483 return the length of the first format. */
4484 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4487 /* If during relaxation we have to pull an instruction out of a
4488 multi-slot instruction, we will return the more conservative
4489 number. This works because alignment on bigger instructions
4490 is more restrictive than alignment on smaller instructions.
4491 This is more conservative than we would like, but it happens
4494 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4497 /* If we aren't doing one of our own relaxations or it isn't
4498 slot-based, then the insn size won't change. */
4499 if (fragP
->fr_type
!= rs_machine_dependent
)
4501 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4504 /* If an instruction is about to grow, return the longer size. */
4505 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4506 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
4507 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP3
)
4509 /* For most frags at RELAX_IMMED_STEPX, with X > 0, the first
4510 instruction in the relaxed version is of length 3. (The case
4511 where we have to pull the instruction out of a FLIX bundle
4512 is handled conservatively above.) However, frags with opcodes
4513 that are expanding to wide branches end up having formats that
4514 are not determinable by the RELAX_IMMED_STEPX enumeration, and
4515 we can't tell directly what format the relaxer picked. This
4516 is a wart in the design of the relaxer that should someday be
4517 fixed, but would require major changes, or at least should
4518 be accompanied by major changes to make use of that data.
4520 In any event, we can tell that we are expanding from a single-slot
4521 three-byte format to a wider one with the logic below. */
4523 if (fmt_size
<= 3 && fragP
->tc_frag_data
.text_expansion
[0] != 3)
4524 return 3 + fragP
->tc_frag_data
.text_expansion
[0];
4529 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4530 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4537 next_frag_format_size (const fragS
*fragP
)
4539 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4540 return frag_format_size (next_fragP
);
4544 /* In early Xtensa Processors, for reasons that are unclear, the ISA
4545 required two-byte instructions to be treated as three-byte instructions
4546 for loop instruction alignment. This restriction was removed beginning
4547 with Xtensa LX. Now the only requirement on loop instruction alignment
4548 is that the first instruction of the loop must appear at an address that
4549 does not cross a fetch boundary. */
4552 get_loop_align_size (int insn_size
)
4554 if (insn_size
== XTENSA_UNDEFINED
)
4555 return xtensa_fetch_width
;
4557 if (enforce_three_byte_loop_align
&& insn_size
== 2)
4564 /* If the next legit fragment is an end-of-loop marker,
4565 switch its state so it will instantiate a NOP. */
4568 update_next_frag_state (fragS
*fragP
)
4570 fragS
*next_fragP
= fragP
->fr_next
;
4571 fragS
*new_target
= NULL
;
4575 /* We are guaranteed there will be one of these... */
4576 while (!(next_fragP
->fr_type
== rs_machine_dependent
4577 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4578 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4579 next_fragP
= next_fragP
->fr_next
;
4581 gas_assert (next_fragP
->fr_type
== rs_machine_dependent
4582 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4583 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4585 /* ...and one of these. */
4586 new_target
= next_fragP
->fr_next
;
4587 while (!(new_target
->fr_type
== rs_machine_dependent
4588 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4589 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4590 new_target
= new_target
->fr_next
;
4592 gas_assert (new_target
->fr_type
== rs_machine_dependent
4593 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4594 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4597 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4599 if (next_fragP
->fr_type
== rs_machine_dependent
4600 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4602 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4606 next_fragP
= next_fragP
->fr_next
;
4612 next_frag_is_branch_target (const fragS
*fragP
)
4614 /* Sometimes an empty will end up here due to storage allocation issues,
4615 so we have to skip until we find something legit. */
4616 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4618 if (fragP
->tc_frag_data
.is_branch_target
)
4620 if (fragP
->fr_fix
!= 0)
4628 next_frag_is_loop_target (const fragS
*fragP
)
4630 /* Sometimes an empty will end up here due storage allocation issues.
4631 So we have to skip until we find something legit. */
4632 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4634 if (fragP
->tc_frag_data
.is_loop_target
)
4636 if (fragP
->fr_fix
!= 0)
4644 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4646 const fragS
*next_fragp
= fragp
->fr_next
;
4647 xtensa_opcode next_opcode
;
4649 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4652 /* Sometimes an empty will end up here due to storage allocation issues,
4653 so we have to skip until we find something legit. */
4654 while (next_fragp
->fr_fix
== 0)
4655 next_fragp
= next_fragp
->fr_next
;
4657 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4660 /* There is some implicit knowledge encoded in here.
4661 The LOOP instructions that are NOT RELAX_IMMED have
4662 been relaxed. Note that we can assume that the LOOP
4663 instruction is in slot 0 because loops aren't bundleable. */
4664 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4665 return get_expanded_loop_offset (next_opcode
);
4671 /* Mark a location where we can later insert literal frags. Update
4672 the section's literal_pool_loc, so subsequent literals can be
4673 placed nearest to their use. */
4676 xtensa_mark_literal_pool_location (void)
4678 /* Any labels pointing to the current location need
4679 to be adjusted to after the literal pool. */
4681 fragS
*pool_location
;
4683 if (use_literal_section
)
4686 /* We stash info in these frags so we can later move the literal's
4687 fixes into this frchain's fix list. */
4688 pool_location
= frag_now
;
4689 frag_now
->tc_frag_data
.lit_frchain
= frchain_now
;
4690 frag_now
->tc_frag_data
.literal_frag
= frag_now
;
4691 frag_variant (rs_machine_dependent
, 0, 0,
4692 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4693 xtensa_set_frag_assembly_state (frag_now
);
4694 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
4695 frag_variant (rs_machine_dependent
, 0, 0,
4696 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4697 xtensa_set_frag_assembly_state (frag_now
);
4699 /* Now put a frag into the literal pool that points to this location. */
4700 set_literal_pool_location (now_seg
, pool_location
);
4701 xtensa_switch_to_non_abs_literal_fragment (&s
);
4702 frag_align (2, 0, 0);
4703 record_alignment (now_seg
, 2);
4705 /* Close whatever frag is there. */
4706 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4707 xtensa_set_frag_assembly_state (frag_now
);
4708 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
4709 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4710 xtensa_restore_emit_state (&s
);
4711 xtensa_set_frag_assembly_state (frag_now
);
4715 /* Build a nop of the correct size into tinsn. */
4718 build_nop (TInsn
*tinsn
, int size
)
4724 tinsn
->opcode
= xtensa_nop_n_opcode
;
4726 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4727 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4731 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4733 tinsn
->opcode
= xtensa_or_opcode
;
4734 set_expr_const (&tinsn
->tok
[0], 1);
4735 set_expr_const (&tinsn
->tok
[1], 1);
4736 set_expr_const (&tinsn
->tok
[2], 1);
4740 tinsn
->opcode
= xtensa_nop_opcode
;
4742 gas_assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4747 /* Assemble a NOP of the requested size in the buffer. User must have
4748 allocated "buf" with at least "size" bytes. */
4751 assemble_nop (int size
, char *buf
)
4753 static xtensa_insnbuf insnbuf
= NULL
;
4756 build_nop (&tinsn
, size
);
4759 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4761 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4762 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4763 (unsigned char *) buf
, 0);
4767 /* Return the number of bytes for the offset of the expanded loop
4768 instruction. This should be incorporated into the relaxation
4769 specification but is hard-coded here. This is used to auto-align
4770 the loop instruction. It is invalid to call this function if the
4771 configuration does not have loops or if the opcode is not a loop
4775 get_expanded_loop_offset (xtensa_opcode opcode
)
4777 /* This is the OFFSET of the loop instruction in the expanded loop.
4778 This MUST correspond directly to the specification of the loop
4779 expansion. It will be validated on fragment conversion. */
4780 gas_assert (opcode
!= XTENSA_UNDEFINED
);
4781 if (opcode
== xtensa_loop_opcode
)
4783 if (opcode
== xtensa_loopnez_opcode
)
4785 if (opcode
== xtensa_loopgtz_opcode
)
4787 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4793 get_literal_pool_location (segT seg
)
4795 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4800 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4802 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4806 /* Set frag assembly state should be called when a new frag is
4807 opened and after a frag has been closed. */
4810 xtensa_set_frag_assembly_state (fragS
*fragP
)
4812 if (!density_supported
)
4813 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4815 /* This function is called from subsegs_finish, which is called
4816 after xtensa_end, so we can't use "use_transform" or
4817 "use_schedule" here. */
4818 if (!directive_state
[directive_transform
])
4819 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4820 if (directive_state
[directive_longcalls
])
4821 fragP
->tc_frag_data
.use_longcalls
= TRUE
;
4822 fragP
->tc_frag_data
.use_absolute_literals
=
4823 directive_state
[directive_absolute_literals
];
4824 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4829 relaxable_section (asection
*sec
)
4831 return ((sec
->flags
& SEC_DEBUGGING
) == 0
4832 && strcmp (sec
->name
, ".eh_frame") != 0);
4837 xtensa_mark_frags_for_org (void)
4841 /* Walk over each fragment of all of the current segments. If we find
4842 a .org frag in any of the segments, mark all frags prior to it as
4843 "no transform", which will prevent linker optimizations from messing
4844 up the .org distance. This should be done after
4845 xtensa_find_unmarked_state_frags, because we don't want to worry here
4846 about that function trashing the data we save here. */
4848 for (seclist
= &stdoutput
->sections
;
4849 seclist
&& *seclist
;
4850 seclist
= &(*seclist
)->next
)
4852 segT sec
= *seclist
;
4853 segment_info_type
*seginfo
;
4856 flags
= bfd_get_section_flags (stdoutput
, sec
);
4857 if (flags
& SEC_DEBUGGING
)
4859 if (!(flags
& SEC_ALLOC
))
4862 seginfo
= seg_info (sec
);
4863 if (seginfo
&& seginfo
->frchainP
)
4865 fragS
*last_fragP
= seginfo
->frchainP
->frch_root
;
4866 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4867 fragP
= fragP
->fr_next
)
4869 /* cvt_frag_to_fill has changed the fr_type of org frags to
4870 rs_fill, so use the value as cached in rs_subtype here. */
4871 if (fragP
->fr_subtype
== RELAX_ORG
)
4873 while (last_fragP
!= fragP
->fr_next
)
4875 last_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4876 last_fragP
= last_fragP
->fr_next
;
4886 xtensa_find_unmarked_state_frags (void)
4890 /* Walk over each fragment of all of the current segments. For each
4891 unmarked fragment, mark it with the same info as the previous
4893 for (seclist
= &stdoutput
->sections
;
4894 seclist
&& *seclist
;
4895 seclist
= &(*seclist
)->next
)
4897 segT sec
= *seclist
;
4898 segment_info_type
*seginfo
;
4901 flags
= bfd_get_section_flags (stdoutput
, sec
);
4902 if (flags
& SEC_DEBUGGING
)
4904 if (!(flags
& SEC_ALLOC
))
4907 seginfo
= seg_info (sec
);
4908 if (seginfo
&& seginfo
->frchainP
)
4910 fragS
*last_fragP
= 0;
4911 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4912 fragP
= fragP
->fr_next
)
4914 if (fragP
->fr_fix
!= 0
4915 && !fragP
->tc_frag_data
.is_assembly_state_set
)
4917 if (last_fragP
== 0)
4919 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
4920 _("assembly state not set for first frag in section %s"),
4925 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4926 fragP
->tc_frag_data
.is_no_density
=
4927 last_fragP
->tc_frag_data
.is_no_density
;
4928 fragP
->tc_frag_data
.is_no_transform
=
4929 last_fragP
->tc_frag_data
.is_no_transform
;
4930 fragP
->tc_frag_data
.use_longcalls
=
4931 last_fragP
->tc_frag_data
.use_longcalls
;
4932 fragP
->tc_frag_data
.use_absolute_literals
=
4933 last_fragP
->tc_frag_data
.use_absolute_literals
;
4936 if (fragP
->tc_frag_data
.is_assembly_state_set
)
4945 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
4947 void *unused ATTRIBUTE_UNUSED
)
4949 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4950 segment_info_type
*seginfo
= seg_info (sec
);
4951 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4953 if (flags
& SEC_CODE
)
4955 xtensa_isa isa
= xtensa_default_isa
;
4956 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4957 while (frag
!= NULL
)
4959 if (frag
->tc_frag_data
.is_branch_target
)
4962 addressT branch_align
, frag_addr
;
4965 xtensa_insnbuf_from_chars
4966 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4967 fmt
= xtensa_format_decode (isa
, insnbuf
);
4968 op_size
= xtensa_format_length (isa
, fmt
);
4969 branch_align
= 1 << branch_align_power (sec
);
4970 frag_addr
= frag
->fr_address
% branch_align
;
4971 if (frag_addr
+ op_size
> branch_align
)
4972 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4973 _("unaligned branch target: %d bytes at 0x%lx"),
4974 op_size
, (long) frag
->fr_address
);
4976 frag
= frag
->fr_next
;
4978 xtensa_insnbuf_free (isa
, insnbuf
);
4984 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
4986 void *unused ATTRIBUTE_UNUSED
)
4988 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4989 segment_info_type
*seginfo
= seg_info (sec
);
4990 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4991 xtensa_isa isa
= xtensa_default_isa
;
4993 if (flags
& SEC_CODE
)
4995 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4996 while (frag
!= NULL
)
4998 if (frag
->tc_frag_data
.is_first_loop_insn
)
5004 xtensa_insnbuf_from_chars
5005 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
5006 fmt
= xtensa_format_decode (isa
, insnbuf
);
5007 op_size
= xtensa_format_length (isa
, fmt
);
5008 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
5010 if (frag_addr
+ op_size
> xtensa_fetch_width
)
5011 as_warn_where (frag
->fr_file
, frag
->fr_line
,
5012 _("unaligned loop: %d bytes at 0x%lx"),
5013 op_size
, (long) frag
->fr_address
);
5015 frag
= frag
->fr_next
;
5017 xtensa_insnbuf_free (isa
, insnbuf
);
5023 xg_apply_fix_value (fixS
*fixP
, valueT val
)
5025 xtensa_isa isa
= xtensa_default_isa
;
5026 static xtensa_insnbuf insnbuf
= NULL
;
5027 static xtensa_insnbuf slotbuf
= NULL
;
5030 bfd_boolean alt_reloc
;
5031 xtensa_opcode opcode
;
5032 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5034 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
)
5036 as_fatal (_("unexpected fix"));
5040 insnbuf
= xtensa_insnbuf_alloc (isa
);
5041 slotbuf
= xtensa_insnbuf_alloc (isa
);
5044 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
5045 fmt
= xtensa_format_decode (isa
, insnbuf
);
5046 if (fmt
== XTENSA_UNDEFINED
)
5047 as_fatal (_("undecodable fix"));
5048 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5049 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5050 if (opcode
== XTENSA_UNDEFINED
)
5051 as_fatal (_("undecodable fix"));
5053 /* CONST16 immediates are not PC-relative, despite the fact that we
5054 reuse the normal PC-relative operand relocations for the low part
5055 of a CONST16 operand. */
5056 if (opcode
== xtensa_const16_opcode
)
5059 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
5060 get_relaxable_immed (opcode
), val
,
5061 fixP
->fx_file
, fixP
->fx_line
);
5063 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5064 xtensa_insnbuf_to_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
5070 /* External Functions and Other GAS Hooks. */
5073 xtensa_target_format (void)
5075 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
5080 xtensa_file_arch_init (bfd
*abfd
)
5082 bfd_set_private_flags (abfd
, 0x100 | 0x200);
5087 md_number_to_chars (char *buf
, valueT val
, int n
)
5089 if (target_big_endian
)
5090 number_to_chars_bigendian (buf
, val
, n
);
5092 number_to_chars_littleendian (buf
, val
, n
);
5096 /* This function is called once, at assembler startup time. It should
5097 set up all the tables, etc. that the MD part of the assembler will
5103 segT current_section
= now_seg
;
5104 int current_subsec
= now_subseg
;
5107 xtensa_default_isa
= xtensa_isa_init (0, 0);
5108 isa
= xtensa_default_isa
;
5112 /* Set up the literal sections. */
5113 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
5115 subseg_set (current_section
, current_subsec
);
5117 xg_init_vinsn (&cur_vinsn
);
5119 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
5120 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
5121 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
5122 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
5123 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
5124 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
5125 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
5126 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
5127 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
5128 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
5129 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
5130 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
5131 xtensa_extui_opcode
= xtensa_opcode_lookup (isa
, "extui");
5132 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
5133 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
5134 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
5135 xtensa_j_opcode
= xtensa_opcode_lookup (isa
, "j");
5136 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
5137 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
5138 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
5139 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
5140 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
5141 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
5142 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
5143 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
5144 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
5145 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
5146 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
5147 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
5148 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
5149 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
5151 xtensa_num_pipe_stages
= xtensa_isa_num_pipe_stages (isa
);
5153 init_op_placement_info_table ();
5155 /* Set up the assembly state. */
5156 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5157 xtensa_set_frag_assembly_state (frag_now
);
5161 /* TC_INIT_FIX_DATA hook */
5164 xtensa_init_fix_data (fixS
*x
)
5166 x
->tc_fix_data
.slot
= 0;
5167 x
->tc_fix_data
.X_add_symbol
= NULL
;
5168 x
->tc_fix_data
.X_add_number
= 0;
5172 /* tc_frob_label hook */
5175 xtensa_frob_label (symbolS
*sym
)
5179 if (cur_vinsn
.inside_bundle
)
5181 as_bad (_("labels are not valid inside bundles"));
5185 freq
= get_subseg_target_freq (now_seg
, now_subseg
);
5187 /* Since the label was already attached to a frag associated with the
5188 previous basic block, it now needs to be reset to the current frag. */
5189 symbol_set_frag (sym
, frag_now
);
5190 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5192 if (generating_literals
)
5193 xtensa_add_literal_sym (sym
);
5195 xtensa_add_insn_label (sym
);
5197 if (symbol_get_tc (sym
)->is_loop_target
)
5199 if ((get_last_insn_flags (now_seg
, now_subseg
)
5200 & FLAG_IS_BAD_LOOPEND
) != 0)
5201 as_bad (_("invalid last instruction for a zero-overhead loop"));
5203 xtensa_set_frag_assembly_state (frag_now
);
5204 frag_var (rs_machine_dependent
, 4, 4, RELAX_LOOP_END
,
5205 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5207 xtensa_set_frag_assembly_state (frag_now
);
5208 xtensa_move_labels (frag_now
, 0);
5211 /* No target aligning in the absolute section. */
5212 if (now_seg
!= absolute_section
5213 && do_align_targets ()
5214 && !is_unaligned_label (sym
)
5215 && !generating_literals
)
5217 xtensa_set_frag_assembly_state (frag_now
);
5219 frag_var (rs_machine_dependent
,
5221 RELAX_DESIRE_ALIGN_IF_TARGET
,
5222 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5223 xtensa_set_frag_assembly_state (frag_now
);
5224 xtensa_move_labels (frag_now
, 0);
5227 /* We need to mark the following properties even if we aren't aligning. */
5229 /* If the label is already known to be a branch target, i.e., a
5230 forward branch, mark the frag accordingly. Backward branches
5231 are handled by xg_add_branch_and_loop_targets. */
5232 if (symbol_get_tc (sym
)->is_branch_target
)
5233 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5235 /* Loops only go forward, so they can be identified here. */
5236 if (symbol_get_tc (sym
)->is_loop_target
)
5237 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5239 dwarf2_emit_label (sym
);
5243 /* tc_unrecognized_line hook */
5246 xtensa_unrecognized_line (int ch
)
5251 if (cur_vinsn
.inside_bundle
== 0)
5253 /* PR8110: Cannot emit line number info inside a FLIX bundle
5254 when using --gstabs. Temporarily disable debug info. */
5255 generate_lineno_debug ();
5256 if (debug_type
== DEBUG_STABS
)
5258 xt_saved_debug_type
= debug_type
;
5259 debug_type
= DEBUG_NONE
;
5262 cur_vinsn
.inside_bundle
= 1;
5266 as_bad (_("extra opening brace"));
5272 if (cur_vinsn
.inside_bundle
)
5273 finish_vinsn (&cur_vinsn
);
5276 as_bad (_("extra closing brace"));
5281 as_bad (_("syntax error"));
5288 /* md_flush_pending_output hook */
5291 xtensa_flush_pending_output (void)
5293 /* This line fixes a bug where automatically generated gstabs info
5294 separates a function label from its entry instruction, ending up
5295 with the literal position between the function label and the entry
5296 instruction and crashing code. It only happens with --gstabs and
5297 --text-section-literals, and when several other obscure relaxation
5298 conditions are met. */
5299 if (outputting_stabs_line_debug
)
5302 if (cur_vinsn
.inside_bundle
)
5303 as_bad (_("missing closing brace"));
5305 /* If there is a non-zero instruction fragment, close it. */
5306 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5308 frag_wane (frag_now
);
5310 xtensa_set_frag_assembly_state (frag_now
);
5312 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5314 xtensa_clear_insn_labels ();
5318 /* We had an error while parsing an instruction. The string might look
5319 like this: "insn arg1, arg2 }". If so, we need to see the closing
5320 brace and reset some fields. Otherwise, the vinsn never gets closed
5321 and the num_slots field will grow past the end of the array of slots,
5322 and bad things happen. */
5325 error_reset_cur_vinsn (void)
5327 if (cur_vinsn
.inside_bundle
)
5329 if (*input_line_pointer
== '}'
5330 || *(input_line_pointer
- 1) == '}'
5331 || *(input_line_pointer
- 2) == '}')
5332 xg_clear_vinsn (&cur_vinsn
);
5338 md_assemble (char *str
)
5340 xtensa_isa isa
= xtensa_default_isa
;
5343 bfd_boolean has_underbar
= FALSE
;
5344 char *arg_strings
[MAX_INSN_ARGS
];
5346 TInsn orig_insn
; /* Original instruction from the input. */
5348 tinsn_init (&orig_insn
);
5350 /* Split off the opcode. */
5351 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5352 opname
= xmalloc (opnamelen
+ 1);
5353 memcpy (opname
, str
, opnamelen
);
5354 opname
[opnamelen
] = '\0';
5356 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5359 as_bad (_("syntax error"));
5363 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5366 /* Check for an underbar prefix. */
5369 has_underbar
= TRUE
;
5373 orig_insn
.insn_type
= ITYPE_INSN
;
5375 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5376 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5378 /* Special case: Check for "CALLXn.TLS" psuedo op. If found, grab its
5379 extra argument and set the opcode to "CALLXn". */
5380 if (orig_insn
.opcode
== XTENSA_UNDEFINED
5381 && strncasecmp (opname
, "callx", 5) == 0)
5383 unsigned long window_size
;
5386 window_size
= strtoul (opname
+ 5, &suffix
, 10);
5387 if (suffix
!= opname
+ 5
5388 && (window_size
== 0
5391 || window_size
== 12)
5392 && strcasecmp (suffix
, ".tls") == 0)
5394 switch (window_size
)
5396 case 0: orig_insn
.opcode
= xtensa_callx0_opcode
; break;
5397 case 4: orig_insn
.opcode
= xtensa_callx4_opcode
; break;
5398 case 8: orig_insn
.opcode
= xtensa_callx8_opcode
; break;
5399 case 12: orig_insn
.opcode
= xtensa_callx12_opcode
; break;
5403 as_bad (_("wrong number of operands for '%s'"), opname
);
5406 bfd_reloc_code_real_type reloc
;
5407 char *old_input_line_pointer
;
5408 expressionS
*tok
= &orig_insn
.extra_arg
;
5411 old_input_line_pointer
= input_line_pointer
;
5412 input_line_pointer
= arg_strings
[num_args
- 1];
5414 t
= expression (tok
);
5415 if (tok
->X_op
== O_symbol
5416 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
5417 == BFD_RELOC_XTENSA_TLS_CALL
))
5418 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
5420 as_bad (_("bad relocation expression for '%s'"), opname
);
5422 input_line_pointer
= old_input_line_pointer
;
5428 /* Special case: Check for "j.l" psuedo op. */
5429 if (orig_insn
.opcode
== XTENSA_UNDEFINED
5430 && strncasecmp (opname
, "j.l", 3) == 0)
5433 as_bad (_("wrong number of operands for '%s'"), opname
);
5436 char *old_input_line_pointer
;
5437 expressionS
*tok
= &orig_insn
.extra_arg
;
5439 old_input_line_pointer
= input_line_pointer
;
5440 input_line_pointer
= arg_strings
[num_args
- 1];
5442 expression_maybe_register (xtensa_jx_opcode
, 0, tok
);
5443 input_line_pointer
= old_input_line_pointer
;
5446 orig_insn
.opcode
= xtensa_j_opcode
;
5450 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5452 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5453 if (fmt
== XTENSA_UNDEFINED
)
5455 as_bad (_("unknown opcode or format name '%s'"), opname
);
5456 error_reset_cur_vinsn ();
5459 if (!cur_vinsn
.inside_bundle
)
5461 as_bad (_("format names only valid inside bundles"));
5462 error_reset_cur_vinsn ();
5465 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5466 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5468 cur_vinsn
.format
= fmt
;
5469 free (has_underbar
? opname
- 1 : opname
);
5470 error_reset_cur_vinsn ();
5474 /* Parse the arguments. */
5475 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5477 as_bad (_("syntax error"));
5478 error_reset_cur_vinsn ();
5482 /* Free the opcode and argument strings, now that they've been parsed. */
5483 free (has_underbar
? opname
- 1 : opname
);
5485 while (num_args
-- > 0)
5486 free (arg_strings
[num_args
]);
5488 /* Get expressions for invisible operands. */
5489 if (get_invisible_operands (&orig_insn
))
5491 error_reset_cur_vinsn ();
5495 /* Check for the right number and type of arguments. */
5496 if (tinsn_check_arguments (&orig_insn
))
5498 error_reset_cur_vinsn ();
5502 /* Record the line number for each TInsn, because a FLIX bundle may be
5503 spread across multiple input lines and individual instructions may be
5504 moved around in some cases. */
5505 orig_insn
.loc_directive_seen
= dwarf2_loc_directive_seen
;
5506 dwarf2_where (&orig_insn
.debug_line
);
5507 dwarf2_consume_line_info ();
5509 xg_add_branch_and_loop_targets (&orig_insn
);
5511 /* Check that immediate value for ENTRY is >= 16. */
5512 if (orig_insn
.opcode
== xtensa_entry_opcode
&& orig_insn
.ntok
>= 3)
5514 expressionS
*exp
= &orig_insn
.tok
[2];
5515 if (exp
->X_op
== O_constant
&& exp
->X_add_number
< 16)
5516 as_warn (_("entry instruction with stack decrement < 16"));
5520 assemble_tokens (opcode, tok, ntok);
5521 expand the tokens from the orig_insn into the
5522 stack of instructions that will not expand
5523 unless required at relaxation time. */
5525 if (!cur_vinsn
.inside_bundle
)
5526 emit_single_op (&orig_insn
);
5527 else /* We are inside a bundle. */
5529 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5530 cur_vinsn
.num_slots
++;
5531 if (*input_line_pointer
== '}'
5532 || *(input_line_pointer
- 1) == '}'
5533 || *(input_line_pointer
- 2) == '}')
5534 finish_vinsn (&cur_vinsn
);
5537 /* We've just emitted a new instruction so clear the list of labels. */
5538 xtensa_clear_insn_labels ();
5542 /* HANDLE_ALIGN hook */
5544 /* For a .align directive, we mark the previous block with the alignment
5545 information. This will be placed in the object file in the
5546 property section corresponding to this section. */
5549 xtensa_handle_align (fragS
*fragP
)
5552 && ! fragP
->tc_frag_data
.is_literal
5553 && (fragP
->fr_type
== rs_align
5554 || fragP
->fr_type
== rs_align_code
)
5555 && fragP
->fr_address
+ fragP
->fr_fix
> 0
5556 && fragP
->fr_offset
> 0
5557 && now_seg
!= bss_section
)
5559 fragP
->tc_frag_data
.is_align
= TRUE
;
5560 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5563 if (fragP
->fr_type
== rs_align_test
)
5566 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5568 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5569 _("unaligned entry instruction"));
5572 if (linkrelax
&& fragP
->fr_type
== rs_org
)
5573 fragP
->fr_subtype
= RELAX_ORG
;
5577 /* TC_FRAG_INIT hook */
5580 xtensa_frag_init (fragS
*frag
)
5582 xtensa_set_frag_assembly_state (frag
);
5587 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5593 /* Round up a section size to the appropriate boundary. */
5596 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5598 return size
; /* Byte alignment is fine. */
5603 md_pcrel_from (fixS
*fixP
)
5606 static xtensa_insnbuf insnbuf
= NULL
;
5607 static xtensa_insnbuf slotbuf
= NULL
;
5610 xtensa_opcode opcode
;
5613 xtensa_isa isa
= xtensa_default_isa
;
5614 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5615 bfd_boolean alt_reloc
;
5617 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5620 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
5625 insnbuf
= xtensa_insnbuf_alloc (isa
);
5626 slotbuf
= xtensa_insnbuf_alloc (isa
);
5629 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5630 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) insn_p
, 0);
5631 fmt
= xtensa_format_decode (isa
, insnbuf
);
5633 if (fmt
== XTENSA_UNDEFINED
)
5634 as_fatal (_("bad instruction format"));
5636 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5637 as_fatal (_("invalid relocation"));
5639 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5640 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5642 /* Check for "alternate" relocations (operand not specified). None
5643 of the current uses for these are really PC-relative. */
5644 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5646 if (opcode
!= xtensa_l32r_opcode
5647 && opcode
!= xtensa_const16_opcode
)
5648 as_fatal (_("invalid relocation for '%s' instruction"),
5649 xtensa_opcode_name (isa
, opcode
));
5653 opnum
= get_relaxable_immed (opcode
);
5655 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5656 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5658 as_bad_where (fixP
->fx_file
,
5660 _("invalid relocation for operand %d of '%s'"),
5661 opnum
, xtensa_opcode_name (isa
, opcode
));
5664 return 0 - opnd_value
;
5668 /* TC_FORCE_RELOCATION hook */
5671 xtensa_force_relocation (fixS
*fix
)
5673 switch (fix
->fx_r_type
)
5675 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5676 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5677 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5678 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5679 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5680 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5681 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5682 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5683 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5684 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5685 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5686 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5687 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5688 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5689 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5690 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5696 if (linkrelax
&& fix
->fx_addsy
5697 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5700 return generic_force_reloc (fix
);
5704 /* TC_VALIDATE_FIX_SUB hook */
5707 xtensa_validate_fix_sub (fixS
*fix
)
5709 segT add_symbol_segment
, sub_symbol_segment
;
5711 /* The difference of two symbols should be resolved by the assembler when
5712 linkrelax is not set. If the linker may relax the section containing
5713 the symbols, then an Xtensa DIFF relocation must be generated so that
5714 the linker knows to adjust the difference value. */
5715 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
5718 /* Make sure both symbols are in the same segment, and that segment is
5719 "normal" and relaxable. If the segment is not "normal", then the
5720 fix is not valid. If the segment is not "relaxable", then the fix
5721 should have been handled earlier. */
5722 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
5723 if (! SEG_NORMAL (add_symbol_segment
) ||
5724 ! relaxable_section (add_symbol_segment
))
5726 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
5727 return (sub_symbol_segment
== add_symbol_segment
);
5731 /* NO_PSEUDO_DOT hook */
5733 /* This function has nothing to do with pseudo dots, but this is the
5734 nearest macro to where the check needs to take place. FIXME: This
5738 xtensa_check_inside_bundle (void)
5740 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5741 as_bad (_("directives are not valid inside bundles"));
5743 /* This function must always return FALSE because it is called via a
5744 macro that has nothing to do with bundling. */
5749 /* md_elf_section_change_hook */
5752 xtensa_elf_section_change_hook (void)
5754 /* Set up the assembly state. */
5755 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5756 xtensa_set_frag_assembly_state (frag_now
);
5760 /* tc_fix_adjustable hook */
5763 xtensa_fix_adjustable (fixS
*fixP
)
5765 /* An offset is not allowed in combination with the difference of two
5766 symbols, but that cannot be easily detected after a local symbol
5767 has been adjusted to a (section+offset) form. Return 0 so that such
5768 an fix will not be adjusted. */
5769 if (fixP
->fx_subsy
&& fixP
->fx_addsy
&& fixP
->fx_offset
5770 && relaxable_section (S_GET_SEGMENT (fixP
->fx_subsy
)))
5773 /* We need the symbol name for the VTABLE entries. */
5774 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5775 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5782 /* tc_symbol_new_hook */
5784 symbolS
*expr_symbols
= NULL
;
5787 xtensa_symbol_new_hook (symbolS
*sym
)
5789 if (is_leb128_expr
&& S_GET_SEGMENT (sym
) == expr_section
)
5791 symbol_get_tc (sym
)->next_expr_symbol
= expr_symbols
;
5798 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg
)
5800 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5803 /* Subtracted symbols are only allowed for a few relocation types, and
5804 unless linkrelax is enabled, they should not make it to this point. */
5805 if (fixP
->fx_subsy
&& !(linkrelax
&& (fixP
->fx_r_type
== BFD_RELOC_32
5806 || fixP
->fx_r_type
== BFD_RELOC_16
5807 || fixP
->fx_r_type
== BFD_RELOC_8
)))
5808 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("expression too complex"));
5810 switch (fixP
->fx_r_type
)
5812 case BFD_RELOC_32_PCREL
:
5818 switch (fixP
->fx_r_type
)
5821 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF8
;
5824 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF16
;
5827 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF32
;
5833 /* An offset is only allowed when it results from adjusting a
5834 local symbol into a section-relative offset. If the offset
5835 came from the original expression, tc_fix_adjustable will have
5836 prevented the fix from being converted to a section-relative
5837 form so that we can flag the error here. */
5838 if (fixP
->fx_offset
!= 0 && !symbol_section_p (fixP
->fx_addsy
))
5839 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5840 _("cannot represent subtraction with an offset"));
5842 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5843 - S_GET_VALUE (fixP
->fx_subsy
));
5845 /* The difference value gets written out, and the DIFF reloc
5846 identifies the address of the subtracted symbol (i.e., the one
5847 with the lowest address). */
5849 fixP
->fx_offset
-= val
;
5850 fixP
->fx_subsy
= NULL
;
5852 else if (! fixP
->fx_addsy
)
5859 case BFD_RELOC_XTENSA_PLT
:
5860 md_number_to_chars (fixpos
, val
, fixP
->fx_size
);
5861 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5864 case BFD_RELOC_XTENSA_TLSDESC_FN
:
5865 case BFD_RELOC_XTENSA_TLSDESC_ARG
:
5866 case BFD_RELOC_XTENSA_TLS_TPOFF
:
5867 case BFD_RELOC_XTENSA_TLS_DTPOFF
:
5868 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
5869 md_number_to_chars (fixpos
, 0, fixP
->fx_size
);
5870 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5873 case BFD_RELOC_XTENSA_SLOT0_OP
:
5874 case BFD_RELOC_XTENSA_SLOT1_OP
:
5875 case BFD_RELOC_XTENSA_SLOT2_OP
:
5876 case BFD_RELOC_XTENSA_SLOT3_OP
:
5877 case BFD_RELOC_XTENSA_SLOT4_OP
:
5878 case BFD_RELOC_XTENSA_SLOT5_OP
:
5879 case BFD_RELOC_XTENSA_SLOT6_OP
:
5880 case BFD_RELOC_XTENSA_SLOT7_OP
:
5881 case BFD_RELOC_XTENSA_SLOT8_OP
:
5882 case BFD_RELOC_XTENSA_SLOT9_OP
:
5883 case BFD_RELOC_XTENSA_SLOT10_OP
:
5884 case BFD_RELOC_XTENSA_SLOT11_OP
:
5885 case BFD_RELOC_XTENSA_SLOT12_OP
:
5886 case BFD_RELOC_XTENSA_SLOT13_OP
:
5887 case BFD_RELOC_XTENSA_SLOT14_OP
:
5890 /* Write the tentative value of a PC-relative relocation to a
5891 local symbol into the instruction. The value will be ignored
5892 by the linker, and it makes the object file disassembly
5893 readable when all branch targets are encoded in relocations. */
5895 gas_assert (fixP
->fx_addsy
);
5896 if (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
5897 && !S_FORCE_RELOC (fixP
->fx_addsy
, 1))
5899 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5900 - md_pcrel_from (fixP
));
5901 (void) xg_apply_fix_value (fixP
, val
);
5904 else if (! fixP
->fx_addsy
)
5907 if (xg_apply_fix_value (fixP
, val
))
5912 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5913 case BFD_RELOC_XTENSA_TLS_FUNC
:
5914 case BFD_RELOC_XTENSA_TLS_ARG
:
5915 case BFD_RELOC_XTENSA_TLS_CALL
:
5916 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5917 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5918 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5919 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5920 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5921 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5922 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5923 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5924 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5925 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5926 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5927 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5928 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5929 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5930 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5931 /* These all need to be resolved at link-time. Do nothing now. */
5934 case BFD_RELOC_VTABLE_INHERIT
:
5935 case BFD_RELOC_VTABLE_ENTRY
:
5940 as_bad (_("unhandled local relocation fix %s"),
5941 bfd_get_reloc_code_name (fixP
->fx_r_type
));
5947 md_atof (int type
, char *litP
, int *sizeP
)
5949 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
5954 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
5956 return total_frag_text_expansion (fragP
);
5960 /* Translate internal representation of relocation info to BFD target
5964 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
5968 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
5969 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5970 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5971 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5973 /* Make sure none of our internal relocations make it this far.
5974 They'd better have been fully resolved by this point. */
5975 gas_assert ((int) fixp
->fx_r_type
> 0);
5977 reloc
->addend
= fixp
->fx_offset
;
5979 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
5980 if (reloc
->howto
== NULL
)
5982 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5983 _("cannot represent `%s' relocation in object file"),
5984 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5985 free (reloc
->sym_ptr_ptr
);
5990 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
5991 as_fatal (_("internal error; cannot generate `%s' relocation"),
5992 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5998 /* Checks for resource conflicts between instructions. */
6000 /* The func unit stuff could be implemented as bit-vectors rather
6001 than the iterative approach here. If it ends up being too
6002 slow, we will switch it. */
6005 new_resource_table (void *data
,
6008 unit_num_copies_func uncf
,
6009 opcode_num_units_func onuf
,
6010 opcode_funcUnit_use_unit_func ouuf
,
6011 opcode_funcUnit_use_stage_func ousf
)
6014 resource_table
*rt
= (resource_table
*) xmalloc (sizeof (resource_table
));
6016 rt
->cycles
= cycles
;
6017 rt
->allocated_cycles
= cycles
;
6019 rt
->unit_num_copies
= uncf
;
6020 rt
->opcode_num_units
= onuf
;
6021 rt
->opcode_unit_use
= ouuf
;
6022 rt
->opcode_unit_stage
= ousf
;
6024 rt
->units
= (unsigned char **) xcalloc (cycles
, sizeof (unsigned char *));
6025 for (i
= 0; i
< cycles
; i
++)
6026 rt
->units
[i
] = (unsigned char *) xcalloc (nu
, sizeof (unsigned char));
6033 clear_resource_table (resource_table
*rt
)
6036 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
6037 for (j
= 0; j
< rt
->num_units
; j
++)
6038 rt
->units
[i
][j
] = 0;
6042 /* We never shrink it, just fake it into thinking so. */
6045 resize_resource_table (resource_table
*rt
, int cycles
)
6049 rt
->cycles
= cycles
;
6050 if (cycles
<= rt
->allocated_cycles
)
6053 old_cycles
= rt
->allocated_cycles
;
6054 rt
->allocated_cycles
= cycles
;
6056 rt
->units
= xrealloc (rt
->units
,
6057 rt
->allocated_cycles
* sizeof (unsigned char *));
6058 for (i
= 0; i
< old_cycles
; i
++)
6059 rt
->units
[i
] = xrealloc (rt
->units
[i
],
6060 rt
->num_units
* sizeof (unsigned char));
6061 for (i
= old_cycles
; i
< cycles
; i
++)
6062 rt
->units
[i
] = xcalloc (rt
->num_units
, sizeof (unsigned char));
6067 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6070 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6072 for (i
= 0; i
< uses
; i
++)
6074 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6075 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6076 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
6077 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
6078 if (copies_in_use
>= copies
)
6086 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6089 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6091 for (i
= 0; i
< uses
; i
++)
6093 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6094 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6095 /* Note that this allows resources to be oversubscribed. That's
6096 essential to the way the optional scheduler works.
6097 resources_available reports when a resource is over-subscribed,
6098 so it's easy to tell. */
6099 rt
->units
[stage
+ cycle
][unit
]++;
6105 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6108 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6110 for (i
= 0; i
< uses
; i
++)
6112 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6113 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6114 gas_assert (rt
->units
[stage
+ cycle
][unit
] > 0);
6115 rt
->units
[stage
+ cycle
][unit
]--;
6120 /* Wrapper functions make parameterized resource reservation
6124 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
6126 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
6132 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
6134 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
6139 /* Note that this function does not check issue constraints, but
6140 solely whether the hardware is available to execute the given
6141 instructions together. It also doesn't check if the tinsns
6142 write the same state, or access the same tieports. That is
6143 checked by check_t1_t2_reads_and_writes. */
6146 resources_conflict (vliw_insn
*vinsn
)
6149 static resource_table
*rt
= NULL
;
6151 /* This is the most common case by far. Optimize it. */
6152 if (vinsn
->num_slots
== 1)
6157 xtensa_isa isa
= xtensa_default_isa
;
6158 rt
= new_resource_table
6159 (isa
, xtensa_num_pipe_stages
,
6160 xtensa_isa_num_funcUnits (isa
),
6161 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
6162 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
6163 opcode_funcUnit_use_unit
,
6164 opcode_funcUnit_use_stage
);
6167 clear_resource_table (rt
);
6169 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6171 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
6173 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
6180 /* finish_vinsn, emit_single_op and helper functions. */
6182 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
6183 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
6184 static void xg_assemble_vliw_tokens (vliw_insn
*);
6187 /* We have reached the end of a bundle; emit into the frag. */
6190 finish_vinsn (vliw_insn
*vinsn
)
6197 if (find_vinsn_conflicts (vinsn
))
6199 xg_clear_vinsn (vinsn
);
6203 /* First, find a format that works. */
6204 if (vinsn
->format
== XTENSA_UNDEFINED
)
6205 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6207 if (xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
) > 1
6208 && produce_flix
== FLIX_NONE
)
6210 as_bad (_("The option \"--no-allow-flix\" prohibits multi-slot flix."));
6211 xg_clear_vinsn (vinsn
);
6215 if (vinsn
->format
== XTENSA_UNDEFINED
)
6217 as_where (&file_name
, &line
);
6218 as_bad_where (file_name
, line
,
6219 _("couldn't find a valid instruction format"));
6220 fprintf (stderr
, _(" ops were: "));
6221 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6222 fprintf (stderr
, _(" %s;"),
6223 xtensa_opcode_name (xtensa_default_isa
,
6224 vinsn
->slots
[i
].opcode
));
6225 fprintf (stderr
, _("\n"));
6226 xg_clear_vinsn (vinsn
);
6230 if (vinsn
->num_slots
6231 != xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
))
6233 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
6234 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
6235 xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
),
6237 xg_clear_vinsn (vinsn
);
6241 if (resources_conflict (vinsn
))
6243 as_where (&file_name
, &line
);
6244 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6245 fprintf (stderr
, " ops were: ");
6246 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6247 fprintf (stderr
, " %s;",
6248 xtensa_opcode_name (xtensa_default_isa
,
6249 vinsn
->slots
[i
].opcode
));
6250 fprintf (stderr
, "\n");
6251 xg_clear_vinsn (vinsn
);
6255 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6257 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
6259 symbolS
*lit_sym
= NULL
;
6261 bfd_boolean e
= FALSE
;
6262 bfd_boolean saved_density
= density_supported
;
6264 /* We don't want to narrow ops inside multi-slot bundles. */
6265 if (vinsn
->num_slots
> 1)
6266 density_supported
= FALSE
;
6268 istack_init (&slotstack
);
6269 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
6271 vinsn
->slots
[i
].opcode
=
6272 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6274 vinsn
->slots
[i
].ntok
= 0;
6277 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
6283 density_supported
= saved_density
;
6287 xg_clear_vinsn (vinsn
);
6291 for (j
= 0; j
< slotstack
.ninsn
; j
++)
6293 TInsn
*insn
= &slotstack
.insn
[j
];
6294 if (insn
->insn_type
== ITYPE_LITERAL
)
6296 gas_assert (lit_sym
== NULL
);
6297 lit_sym
= xg_assemble_literal (insn
);
6301 gas_assert (insn
->insn_type
== ITYPE_INSN
);
6303 xg_resolve_literals (insn
, lit_sym
);
6304 if (j
!= slotstack
.ninsn
- 1)
6305 emit_single_op (insn
);
6309 if (vinsn
->num_slots
> 1)
6311 if (opcode_fits_format_slot
6312 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6315 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6319 emit_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6320 if (vinsn
->format
== XTENSA_UNDEFINED
)
6321 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6323 vinsn
->slots
[i
].opcode
6324 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6327 vinsn
->slots
[i
].ntok
= 0;
6332 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6333 vinsn
->format
= XTENSA_UNDEFINED
;
6338 /* Now check resource conflicts on the modified bundle. */
6339 if (resources_conflict (vinsn
))
6341 as_where (&file_name
, &line
);
6342 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6343 fprintf (stderr
, " ops were: ");
6344 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6345 fprintf (stderr
, " %s;",
6346 xtensa_opcode_name (xtensa_default_isa
,
6347 vinsn
->slots
[i
].opcode
));
6348 fprintf (stderr
, "\n");
6349 xg_clear_vinsn (vinsn
);
6353 /* First, find a format that works. */
6354 if (vinsn
->format
== XTENSA_UNDEFINED
)
6355 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6357 xg_assemble_vliw_tokens (vinsn
);
6359 xg_clear_vinsn (vinsn
);
6363 /* Given an vliw instruction, what conflicts are there in register
6364 usage and in writes to states and queues?
6366 This function does two things:
6367 1. Reports an error when a vinsn contains illegal combinations
6368 of writes to registers states or queues.
6369 2. Marks individual tinsns as not relaxable if the combination
6370 contains antidependencies.
6372 Job 2 handles things like swap semantics in instructions that need
6373 to be relaxed. For example,
6377 normally would be relaxed to
6382 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6384 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6386 then we can't relax it into
6389 { add a0, a1, a0 ; add a2, a0, a4 ; }
6391 because the value of a0 is trashed before the second add can read it. */
6393 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6396 find_vinsn_conflicts (vliw_insn
*vinsn
)
6400 xtensa_isa isa
= xtensa_default_isa
;
6402 gas_assert (!past_xtensa_end
);
6404 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6406 TInsn
*op1
= &vinsn
->slots
[i
];
6407 if (op1
->is_specific_opcode
)
6408 op1
->keep_wide
= TRUE
;
6410 op1
->keep_wide
= FALSE
;
6413 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6415 TInsn
*op1
= &vinsn
->slots
[i
];
6417 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6420 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6424 TInsn
*op2
= &vinsn
->slots
[j
];
6425 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6426 switch (conflict_type
)
6429 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6430 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6431 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6434 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6435 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6436 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6439 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"),
6440 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6441 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6444 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"),
6445 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6446 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6449 /* Everything is OK. */
6452 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6453 || conflict_type
== 'a');
6460 as_bad (_("multiple branches or jumps in the same bundle"));
6468 /* Check how the state used by t1 and t2 relate.
6471 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6472 case B: no relationship between what is read and written (both could
6473 read the same reg though)
6474 case C: t1 writes a register t2 writes (a register conflict within a
6476 case D: t1 writes a state that t2 also writes
6477 case E: t1 writes a tie queue that t2 also writes
6478 case F: two volatile queue accesses
6482 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6484 xtensa_isa isa
= xtensa_default_isa
;
6485 xtensa_regfile t1_regfile
, t2_regfile
;
6487 int t1_base_reg
, t1_last_reg
;
6488 int t2_base_reg
, t2_last_reg
;
6489 char t1_inout
, t2_inout
;
6491 char conflict
= 'b';
6496 bfd_boolean t1_volatile
= FALSE
;
6497 bfd_boolean t2_volatile
= FALSE
;
6499 /* Check registers. */
6500 for (j
= 0; j
< t2
->ntok
; j
++)
6502 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6505 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6506 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6507 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6509 for (i
= 0; i
< t1
->ntok
; i
++)
6511 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6514 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6516 if (t1_regfile
!= t2_regfile
)
6519 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6520 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6522 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6523 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6525 if (t1_inout
== 'm' || t1_inout
== 'o'
6526 || t2_inout
== 'm' || t2_inout
== 'o')
6533 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6534 t1_last_reg
= (t1_base_reg
6535 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6537 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6539 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6541 if (t1_reg
!= t2_reg
)
6544 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6550 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6556 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6564 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6565 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6566 for (j
= 0; j
< t2_states
; j
++)
6568 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6569 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6570 for (i
= 0; i
< t1_states
; i
++)
6572 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6573 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6574 if (t1_so
!= t2_so
|| xtensa_state_is_shared_or (isa
, t1_so
) == 1)
6577 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6583 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6589 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6594 /* Check tieports. */
6595 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6596 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6597 for (j
= 0; j
< t2_interfaces
; j
++)
6599 xtensa_interface t2_int
6600 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6601 int t2_class
= xtensa_interface_class_id (isa
, t2_int
);
6603 t2_inout
= xtensa_interface_inout (isa
, t2_int
);
6604 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1)
6607 for (i
= 0; i
< t1_interfaces
; i
++)
6609 xtensa_interface t1_int
6610 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6611 int t1_class
= xtensa_interface_class_id (isa
, t1_int
);
6613 t1_inout
= xtensa_interface_inout (isa
, t1_int
);
6614 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1)
6617 if (t1_volatile
&& t2_volatile
&& (t1_class
== t2_class
))
6620 if (t1_int
!= t2_int
)
6623 if (t2_inout
== 'i' && t1_inout
== 'o')
6629 if (t1_inout
== 'i' && t2_inout
== 'o')
6635 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6644 static xtensa_format
6645 xg_find_narrowest_format (vliw_insn
*vinsn
)
6647 /* Right now we assume that the ops within the vinsn are properly
6648 ordered for the slots that the programmer wanted them in. In
6649 other words, we don't rearrange the ops in hopes of finding a
6650 better format. The scheduler handles that. */
6652 xtensa_isa isa
= xtensa_default_isa
;
6653 xtensa_format format
;
6654 vliw_insn v_copy
= *vinsn
;
6655 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6657 if (vinsn
->num_slots
== 1)
6658 return xg_get_single_format (vinsn
->slots
[0].opcode
);
6660 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6663 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6667 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6669 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6671 v_copy
.slots
[slot
].opcode
=
6672 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6673 v_copy
.slots
[slot
].ntok
= 0;
6676 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6679 else if (v_copy
.num_slots
> 1)
6682 /* Try the widened version. */
6683 if (!v_copy
.slots
[slot
].keep_wide
6684 && !v_copy
.slots
[slot
].is_specific_opcode
6685 && xg_is_single_relaxable_insn (&v_copy
.slots
[slot
],
6687 && opcode_fits_format_slot (widened
.opcode
,
6690 v_copy
.slots
[slot
] = widened
;
6695 if (fit
== v_copy
.num_slots
)
6698 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6699 vinsn
->format
= format
;
6705 if (format
== xtensa_isa_num_formats (isa
))
6706 return XTENSA_UNDEFINED
;
6712 /* Return the additional space needed in a frag
6713 for possible relaxations of any ops in a VLIW insn.
6714 Also fill out the relaxations that might be required of
6715 each tinsn in the vinsn. */
6718 relaxation_requirements (vliw_insn
*vinsn
, bfd_boolean
*pfinish_frag
)
6720 bfd_boolean finish_frag
= FALSE
;
6721 int extra_space
= 0;
6724 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6726 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6727 if (!tinsn_has_symbolic_operands (tinsn
))
6729 /* A narrow instruction could be widened later to help
6730 alignment issues. */
6731 if (xg_is_single_relaxable_insn (tinsn
, 0, TRUE
)
6732 && !tinsn
->is_specific_opcode
6733 && vinsn
->num_slots
== 1)
6735 /* Difference in bytes between narrow and wide insns... */
6737 tinsn
->subtype
= RELAX_NARROW
;
6742 if (workaround_b_j_loop_end
6743 && tinsn
->opcode
== xtensa_jx_opcode
6744 && use_transform ())
6746 /* Add 2 of these. */
6747 extra_space
+= 3; /* for the nop size */
6748 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6751 /* Need to assemble it with space for the relocation. */
6752 if (xg_is_relaxable_insn (tinsn
, 0)
6753 && !tinsn
->is_specific_opcode
)
6755 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6756 int max_literal_size
=
6757 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6759 tinsn
->literal_space
= max_literal_size
;
6761 tinsn
->subtype
= RELAX_IMMED
;
6762 extra_space
+= max_size
;
6766 /* A fix record will be added for this instruction prior
6767 to relaxation, so make it end the frag. */
6772 *pfinish_frag
= finish_frag
;
6778 bundle_tinsn (TInsn
*tinsn
, vliw_insn
*vinsn
)
6780 xtensa_isa isa
= xtensa_default_isa
;
6781 int slot
, chosen_slot
;
6783 vinsn
->format
= xg_get_single_format (tinsn
->opcode
);
6784 gas_assert (vinsn
->format
!= XTENSA_UNDEFINED
);
6785 vinsn
->num_slots
= xtensa_format_num_slots (isa
, vinsn
->format
);
6787 chosen_slot
= xg_get_single_slot (tinsn
->opcode
);
6788 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6790 if (slot
== chosen_slot
)
6791 vinsn
->slots
[slot
] = *tinsn
;
6794 vinsn
->slots
[slot
].opcode
=
6795 xtensa_format_slot_nop_opcode (isa
, vinsn
->format
, slot
);
6796 vinsn
->slots
[slot
].ntok
= 0;
6797 vinsn
->slots
[slot
].insn_type
= ITYPE_INSN
;
6804 emit_single_op (TInsn
*orig_insn
)
6807 IStack istack
; /* put instructions into here */
6808 symbolS
*lit_sym
= NULL
;
6809 symbolS
*label_sym
= NULL
;
6811 istack_init (&istack
);
6813 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6814 Because the scheduling and bundling characteristics of movi and
6815 l32r or const16 are so different, we can do much better if we relax
6816 it prior to scheduling and bundling, rather than after. */
6817 if ((orig_insn
->opcode
== xtensa_movi_opcode
6818 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
6819 && !cur_vinsn
.inside_bundle
6820 && (orig_insn
->tok
[1].X_op
== O_symbol
6821 || orig_insn
->tok
[1].X_op
== O_pltrel
6822 || orig_insn
->tok
[1].X_op
== O_tlsfunc
6823 || orig_insn
->tok
[1].X_op
== O_tlsarg
6824 || orig_insn
->tok
[1].X_op
== O_tpoff
6825 || orig_insn
->tok
[1].X_op
== O_dtpoff
)
6826 && !orig_insn
->is_specific_opcode
&& use_transform ())
6827 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
6829 if (xg_expand_assembly_insn (&istack
, orig_insn
))
6832 for (i
= 0; i
< istack
.ninsn
; i
++)
6834 TInsn
*insn
= &istack
.insn
[i
];
6835 switch (insn
->insn_type
)
6838 gas_assert (lit_sym
== NULL
);
6839 lit_sym
= xg_assemble_literal (insn
);
6843 static int relaxed_sym_idx
= 0;
6844 char *label
= xmalloc (strlen (FAKE_LABEL_NAME
) + 12);
6845 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
6847 gas_assert (label_sym
== NULL
);
6848 label_sym
= symbol_find_or_make (label
);
6849 gas_assert (label_sym
);
6857 xg_resolve_literals (insn
, lit_sym
);
6859 xg_resolve_labels (insn
, label_sym
);
6861 bundle_tinsn (insn
, &v
);
6876 total_frag_text_expansion (fragS
*fragP
)
6879 int total_expansion
= 0;
6881 for (slot
= 0; slot
< MAX_SLOTS
; slot
++)
6882 total_expansion
+= fragP
->tc_frag_data
.text_expansion
[slot
];
6884 return total_expansion
;
6888 /* Emit a vliw instruction to the current fragment. */
6891 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
6893 bfd_boolean finish_frag
;
6894 bfd_boolean is_jump
= FALSE
;
6895 bfd_boolean is_branch
= FALSE
;
6896 xtensa_isa isa
= xtensa_default_isa
;
6901 struct dwarf2_line_info debug_line
;
6902 bfd_boolean loc_directive_seen
= FALSE
;
6905 memset (&debug_line
, 0, sizeof (struct dwarf2_line_info
));
6907 if (generating_literals
)
6909 static int reported
= 0;
6911 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
6912 _("cannot assemble into a literal fragment"));
6919 if (frag_now_fix () != 0
6920 && (! frag_now
->tc_frag_data
.is_insn
6921 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6922 || !use_transform () != frag_now
->tc_frag_data
.is_no_transform
6923 || (directive_state
[directive_longcalls
]
6924 != frag_now
->tc_frag_data
.use_longcalls
)
6925 || (directive_state
[directive_absolute_literals
]
6926 != frag_now
->tc_frag_data
.use_absolute_literals
)))
6928 frag_wane (frag_now
);
6930 xtensa_set_frag_assembly_state (frag_now
);
6933 if (workaround_a0_b_retw
6934 && vinsn
->num_slots
== 1
6935 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
6936 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
6937 && use_transform ())
6939 has_a0_b_retw
= TRUE
;
6941 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
6942 After the first assembly pass we will check all of them and
6943 add a nop if needed. */
6944 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6945 frag_var (rs_machine_dependent
, 4, 4,
6946 RELAX_ADD_NOP_IF_A0_B_RETW
,
6947 frag_now
->fr_symbol
,
6948 frag_now
->fr_offset
,
6950 xtensa_set_frag_assembly_state (frag_now
);
6951 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6952 frag_var (rs_machine_dependent
, 4, 4,
6953 RELAX_ADD_NOP_IF_A0_B_RETW
,
6954 frag_now
->fr_symbol
,
6955 frag_now
->fr_offset
,
6957 xtensa_set_frag_assembly_state (frag_now
);
6960 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6962 tinsn
= &vinsn
->slots
[slot
];
6964 /* See if the instruction implies an aligned section. */
6965 if (xtensa_opcode_is_loop (isa
, tinsn
->opcode
) == 1)
6966 record_alignment (now_seg
, 2);
6968 /* Determine the best line number for debug info. */
6969 if ((tinsn
->loc_directive_seen
|| !loc_directive_seen
)
6970 && (tinsn
->debug_line
.filenum
!= debug_line
.filenum
6971 || tinsn
->debug_line
.line
< debug_line
.line
6972 || tinsn
->debug_line
.column
< debug_line
.column
))
6973 debug_line
= tinsn
->debug_line
;
6974 if (tinsn
->loc_directive_seen
)
6975 loc_directive_seen
= TRUE
;
6978 /* Special cases for instructions that force an alignment... */
6979 /* None of these opcodes are bundle-able. */
6980 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
6984 /* Remember the symbol that marks the end of the loop in the frag
6985 that marks the start of the loop. This way we can easily find
6986 the end of the loop at the beginning, without adding special code
6987 to mark the loop instructions themselves. */
6988 symbolS
*target_sym
= NULL
;
6989 if (vinsn
->slots
[0].tok
[1].X_op
== O_symbol
)
6990 target_sym
= vinsn
->slots
[0].tok
[1].X_add_symbol
;
6992 xtensa_set_frag_assembly_state (frag_now
);
6993 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6995 max_fill
= get_text_align_max_fill_size
6996 (get_text_align_power (xtensa_fetch_width
),
6997 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
6999 if (use_transform ())
7000 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
7001 RELAX_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
7003 frag_var (rs_machine_dependent
, 0, 0,
7004 RELAX_CHECK_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
7005 xtensa_set_frag_assembly_state (frag_now
);
7008 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
7009 && !vinsn
->slots
[0].is_specific_opcode
)
7011 xtensa_mark_literal_pool_location ();
7012 xtensa_move_labels (frag_now
, 0);
7013 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
7016 if (vinsn
->num_slots
== 1)
7018 if (workaround_a0_b_retw
&& use_transform ())
7019 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
7020 is_register_writer (&vinsn
->slots
[0], "a", 0));
7022 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
7023 is_bad_loopend_opcode (&vinsn
->slots
[0]));
7026 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
7028 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
7030 extra_space
= relaxation_requirements (vinsn
, &finish_frag
);
7032 /* vinsn_to_insnbuf will produce the error. */
7033 if (vinsn
->format
!= XTENSA_UNDEFINED
)
7035 f
= frag_more (insn_size
+ extra_space
);
7036 xtensa_set_frag_assembly_state (frag_now
);
7037 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7040 vinsn_to_insnbuf (vinsn
, f
, frag_now
, FALSE
);
7041 if (vinsn
->format
== XTENSA_UNDEFINED
)
7044 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, (unsigned char *) f
, 0);
7046 if (debug_type
== DEBUG_DWARF2
|| loc_directive_seen
)
7047 dwarf2_gen_line_info (frag_now_fix () - (insn_size
+ extra_space
),
7050 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
7052 tinsn
= &vinsn
->slots
[slot
];
7053 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
7054 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
7055 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
7056 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
7057 if (tinsn
->literal_space
!= 0)
7058 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
7059 frag_now
->tc_frag_data
.free_reg
[slot
] = tinsn
->extra_arg
;
7061 if (tinsn
->subtype
== RELAX_NARROW
)
7062 gas_assert (vinsn
->num_slots
== 1);
7063 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
7065 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
7068 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->offset
7069 || tinsn
->literal_frag
|| is_jump
|| is_branch
)
7073 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7074 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
7078 frag_variant (rs_machine_dependent
,
7079 extra_space
, extra_space
, RELAX_SLOTS
,
7080 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
7081 xtensa_set_frag_assembly_state (frag_now
);
7084 /* Special cases for loops:
7085 close_loop_end should be inserted AFTER short_loop.
7086 Make sure that CLOSE loops are processed BEFORE short_loops
7087 when converting them. */
7089 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
7090 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1
7091 && !vinsn
->slots
[0].is_specific_opcode
)
7093 if (workaround_short_loop
&& use_transform ())
7095 maybe_has_short_loop
= TRUE
;
7096 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7097 frag_var (rs_machine_dependent
, 4, 4,
7098 RELAX_ADD_NOP_IF_SHORT_LOOP
,
7099 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7100 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7101 frag_var (rs_machine_dependent
, 4, 4,
7102 RELAX_ADD_NOP_IF_SHORT_LOOP
,
7103 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7106 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
7107 loop at least 12 bytes away from another loop's end. */
7108 if (workaround_close_loop_end
&& use_transform ())
7110 maybe_has_close_loop_end
= TRUE
;
7111 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7112 frag_var (rs_machine_dependent
, 12, 12,
7113 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
7114 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7118 if (use_transform ())
7122 gas_assert (finish_frag
);
7123 frag_var (rs_machine_dependent
,
7124 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
7126 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7127 xtensa_set_frag_assembly_state (frag_now
);
7129 else if (is_branch
&& do_align_targets ())
7131 gas_assert (finish_frag
);
7132 frag_var (rs_machine_dependent
,
7133 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
7134 RELAX_MAYBE_UNREACHABLE
,
7135 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7136 xtensa_set_frag_assembly_state (frag_now
);
7137 frag_var (rs_machine_dependent
,
7139 RELAX_MAYBE_DESIRE_ALIGN
,
7140 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7141 xtensa_set_frag_assembly_state (frag_now
);
7145 /* Now, if the original opcode was a call... */
7146 if (do_align_targets ()
7147 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
7149 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
7150 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7151 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
7152 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7153 xtensa_set_frag_assembly_state (frag_now
);
7156 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7158 frag_wane (frag_now
);
7160 xtensa_set_frag_assembly_state (frag_now
);
7165 /* xtensa_end and helper functions. */
7167 static void xtensa_cleanup_align_frags (void);
7168 static void xtensa_fix_target_frags (void);
7169 static void xtensa_mark_narrow_branches (void);
7170 static void xtensa_mark_zcl_first_insns (void);
7171 static void xtensa_mark_difference_of_two_symbols (void);
7172 static void xtensa_fix_a0_b_retw_frags (void);
7173 static void xtensa_fix_b_j_loop_end_frags (void);
7174 static void xtensa_fix_close_loop_end_frags (void);
7175 static void xtensa_fix_short_loop_frags (void);
7176 static void xtensa_sanity_check (void);
7177 static void xtensa_add_config_info (void);
7182 directive_balance ();
7183 xtensa_flush_pending_output ();
7185 past_xtensa_end
= TRUE
;
7187 xtensa_move_literals ();
7189 xtensa_reorder_segments ();
7190 xtensa_cleanup_align_frags ();
7191 xtensa_fix_target_frags ();
7192 if (workaround_a0_b_retw
&& has_a0_b_retw
)
7193 xtensa_fix_a0_b_retw_frags ();
7194 if (workaround_b_j_loop_end
)
7195 xtensa_fix_b_j_loop_end_frags ();
7197 /* "close_loop_end" should be processed BEFORE "short_loop". */
7198 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
7199 xtensa_fix_close_loop_end_frags ();
7201 if (workaround_short_loop
&& maybe_has_short_loop
)
7202 xtensa_fix_short_loop_frags ();
7204 xtensa_mark_narrow_branches ();
7205 xtensa_mark_zcl_first_insns ();
7207 xtensa_sanity_check ();
7209 xtensa_add_config_info ();
7214 xtensa_cleanup_align_frags (void)
7219 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7220 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7223 /* Walk over all of the fragments in a subsection. */
7224 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7226 if ((fragP
->fr_type
== rs_align
7227 || fragP
->fr_type
== rs_align_code
7228 || (fragP
->fr_type
== rs_machine_dependent
7229 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
7230 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
7231 && fragP
->fr_fix
== 0)
7233 fragS
*next
= fragP
->fr_next
;
7236 && next
->fr_fix
== 0
7237 && next
->fr_type
== rs_machine_dependent
7238 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7241 next
= next
->fr_next
;
7244 /* If we don't widen branch targets, then they
7245 will be easier to align. */
7246 if (fragP
->tc_frag_data
.is_branch_target
7247 && fragP
->fr_opcode
== fragP
->fr_literal
7248 && fragP
->fr_type
== rs_machine_dependent
7249 && fragP
->fr_subtype
== RELAX_SLOTS
7250 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
7252 if (fragP
->fr_type
== rs_machine_dependent
7253 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
7254 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
7260 /* Re-process all of the fragments looking to convert all of the
7261 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
7262 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7263 Otherwise, convert to a .fill 0. */
7266 xtensa_fix_target_frags (void)
7271 /* When this routine is called, all of the subsections are still intact
7272 so we walk over subsections instead of sections. */
7273 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7274 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7278 /* Walk over all of the fragments in a subsection. */
7279 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7281 if (fragP
->fr_type
== rs_machine_dependent
7282 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7284 if (next_frag_is_branch_target (fragP
))
7285 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7294 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
7297 xtensa_mark_narrow_branches (void)
7302 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7303 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7306 /* Walk over all of the fragments in a subsection. */
7307 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7309 if (fragP
->fr_type
== rs_machine_dependent
7310 && fragP
->fr_subtype
== RELAX_SLOTS
7311 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7315 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7316 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
7318 if (vinsn
.num_slots
== 1
7319 && xtensa_opcode_is_branch (xtensa_default_isa
,
7320 vinsn
.slots
[0].opcode
) == 1
7321 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
7322 && is_narrow_branch_guaranteed_in_range (fragP
,
7325 fragP
->fr_subtype
= RELAX_SLOTS
;
7326 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
7327 fragP
->tc_frag_data
.is_aligning_branch
= 1;
7335 /* A branch is typically widened only when its target is out of
7336 range. However, we would like to widen them to align a subsequent
7337 branch target when possible.
7339 Because the branch relaxation code is so convoluted, the optimal solution
7340 (combining the two cases) is difficult to get right in all circumstances.
7341 We therefore go with an "almost as good" solution, where we only
7342 use for alignment narrow branches that definitely will not expand to a
7343 jump and a branch. These functions find and mark these cases. */
7345 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
7346 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7347 We start counting beginning with the frag after the 2-byte branch, so the
7348 maximum offset is (4 - 2) + 63 = 65. */
7349 #define MAX_IMMED6 65
7351 static offsetT
unrelaxed_frag_max_size (fragS
*);
7354 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
7356 const expressionS
*expr
= &tinsn
->tok
[1];
7357 symbolS
*symbolP
= expr
->X_add_symbol
;
7358 offsetT max_distance
= expr
->X_add_number
;
7361 if (expr
->X_op
!= O_symbol
)
7364 target_frag
= symbol_get_frag (symbolP
);
7366 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
7367 if (is_branch_jmp_to_next (tinsn
, fragP
))
7370 /* The branch doesn't branch over it's own frag,
7371 but over the subsequent ones. */
7372 fragP
= fragP
->fr_next
;
7373 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
7375 max_distance
+= unrelaxed_frag_max_size (fragP
);
7376 fragP
= fragP
->fr_next
;
7378 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
7385 xtensa_mark_zcl_first_insns (void)
7390 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7391 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7394 /* Walk over all of the fragments in a subsection. */
7395 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7397 if (fragP
->fr_type
== rs_machine_dependent
7398 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7399 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7401 /* Find the loop frag. */
7402 fragS
*targ_frag
= next_non_empty_frag (fragP
);
7403 /* Find the first insn frag. */
7404 targ_frag
= next_non_empty_frag (targ_frag
);
7406 /* Of course, sometimes (mostly for toy test cases) a
7407 zero-cost loop instruction is the last in a section. */
7410 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
7411 /* Do not widen a frag that is the first instruction of a
7412 zero-cost loop. It makes that loop harder to align. */
7413 if (targ_frag
->fr_type
== rs_machine_dependent
7414 && targ_frag
->fr_subtype
== RELAX_SLOTS
7415 && (targ_frag
->tc_frag_data
.slot_subtypes
[0]
7418 if (targ_frag
->tc_frag_data
.is_aligning_branch
)
7419 targ_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
7422 frag_wane (targ_frag
);
7423 targ_frag
->tc_frag_data
.slot_subtypes
[0] = 0;
7427 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
7435 /* When a difference-of-symbols expression is encoded as a uleb128 or
7436 sleb128 value, the linker is unable to adjust that value to account for
7437 link-time relaxation. Mark all the code between such symbols so that
7438 its size cannot be changed by linker relaxation. */
7441 xtensa_mark_difference_of_two_symbols (void)
7445 for (expr_sym
= expr_symbols
; expr_sym
;
7446 expr_sym
= symbol_get_tc (expr_sym
)->next_expr_symbol
)
7448 expressionS
*expr
= symbol_get_value_expression (expr_sym
);
7450 if (expr
->X_op
== O_subtract
)
7452 symbolS
*left
= expr
->X_add_symbol
;
7453 symbolS
*right
= expr
->X_op_symbol
;
7455 /* Difference of two symbols not in the same section
7456 are handled with relocations in the linker. */
7457 if (S_GET_SEGMENT (left
) == S_GET_SEGMENT (right
))
7462 if (symbol_get_frag (left
)->fr_address
7463 <= symbol_get_frag (right
)->fr_address
)
7465 start
= symbol_get_frag (left
);
7466 end
= symbol_get_frag (right
);
7470 start
= symbol_get_frag (right
);
7471 end
= symbol_get_frag (left
);
7475 start
->tc_frag_data
.is_no_transform
= 1;
7476 start
= start
->fr_next
;
7478 while (start
&& start
->fr_address
< end
->fr_address
);
7485 /* Re-process all of the fragments looking to convert all of the
7486 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7487 conditional branch or a retw/retw.n, convert this frag to one that
7488 will generate a NOP. In any case close it off with a .fill 0. */
7490 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
7493 xtensa_fix_a0_b_retw_frags (void)
7498 /* When this routine is called, all of the subsections are still intact
7499 so we walk over subsections instead of sections. */
7500 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7501 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7505 /* Walk over all of the fragments in a subsection. */
7506 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7508 if (fragP
->fr_type
== rs_machine_dependent
7509 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
7511 if (next_instrs_are_b_retw (fragP
))
7513 if (fragP
->tc_frag_data
.is_no_transform
)
7514 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7516 relax_frag_add_nop (fragP
);
7526 next_instrs_are_b_retw (fragS
*fragP
)
7528 xtensa_opcode opcode
;
7530 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
7531 static xtensa_insnbuf insnbuf
= NULL
;
7532 static xtensa_insnbuf slotbuf
= NULL
;
7533 xtensa_isa isa
= xtensa_default_isa
;
7536 bfd_boolean branch_seen
= FALSE
;
7540 insnbuf
= xtensa_insnbuf_alloc (isa
);
7541 slotbuf
= xtensa_insnbuf_alloc (isa
);
7544 if (next_fragP
== NULL
)
7547 /* Check for the conditional branch. */
7548 xtensa_insnbuf_from_chars
7549 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7550 fmt
= xtensa_format_decode (isa
, insnbuf
);
7551 if (fmt
== XTENSA_UNDEFINED
)
7554 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7556 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
7557 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
7559 branch_seen
= (branch_seen
7560 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
7566 offset
+= xtensa_format_length (isa
, fmt
);
7567 if (offset
== next_fragP
->fr_fix
)
7569 next_fragP
= next_non_empty_frag (next_fragP
);
7573 if (next_fragP
== NULL
)
7576 /* Check for the retw/retw.n. */
7577 xtensa_insnbuf_from_chars
7578 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7579 fmt
= xtensa_format_decode (isa
, insnbuf
);
7581 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
7582 have no problems. */
7583 if (fmt
== XTENSA_UNDEFINED
7584 || xtensa_format_num_slots (isa
, fmt
) != 1)
7587 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
7588 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
7590 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
7597 /* Re-process all of the fragments looking to convert all of the
7598 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
7599 loop end label, convert this frag to one that will generate a NOP.
7600 In any case close it off with a .fill 0. */
7602 static bfd_boolean
next_instr_is_loop_end (fragS
*);
7605 xtensa_fix_b_j_loop_end_frags (void)
7610 /* When this routine is called, all of the subsections are still intact
7611 so we walk over subsections instead of sections. */
7612 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7613 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7617 /* Walk over all of the fragments in a subsection. */
7618 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7620 if (fragP
->fr_type
== rs_machine_dependent
7621 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
7623 if (next_instr_is_loop_end (fragP
))
7625 if (fragP
->tc_frag_data
.is_no_transform
)
7626 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
7628 relax_frag_add_nop (fragP
);
7638 next_instr_is_loop_end (fragS
*fragP
)
7640 const fragS
*next_fragP
;
7642 if (next_frag_is_loop_target (fragP
))
7645 next_fragP
= next_non_empty_frag (fragP
);
7646 if (next_fragP
== NULL
)
7649 if (!next_frag_is_loop_target (next_fragP
))
7652 /* If the size is >= 3 then there is more than one instruction here.
7653 The hardware bug will not fire. */
7654 if (next_fragP
->fr_fix
> 3)
7661 /* Re-process all of the fragments looking to convert all of the
7662 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
7663 not MY loop's loop end within 12 bytes, add enough nops here to
7664 make it at least 12 bytes away. In any case close it off with a
7667 static offsetT min_bytes_to_other_loop_end
7668 (fragS
*, fragS
*, offsetT
);
7671 xtensa_fix_close_loop_end_frags (void)
7676 /* When this routine is called, all of the subsections are still intact
7677 so we walk over subsections instead of sections. */
7678 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7679 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7683 fragS
*current_target
= NULL
;
7685 /* Walk over all of the fragments in a subsection. */
7686 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7688 if (fragP
->fr_type
== rs_machine_dependent
7689 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7690 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7691 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7694 && fragP
->fr_type
== rs_machine_dependent
7695 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
7698 int bytes_added
= 0;
7700 #define REQUIRED_LOOP_DIVIDING_BYTES 12
7701 /* Max out at 12. */
7702 min_bytes
= min_bytes_to_other_loop_end
7703 (fragP
->fr_next
, current_target
, REQUIRED_LOOP_DIVIDING_BYTES
);
7705 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
7707 if (fragP
->tc_frag_data
.is_no_transform
)
7708 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
7711 while (min_bytes
+ bytes_added
7712 < REQUIRED_LOOP_DIVIDING_BYTES
)
7716 if (fragP
->fr_var
< length
)
7717 as_fatal (_("fr_var %lu < length %d"),
7718 (long) fragP
->fr_var
, length
);
7721 assemble_nop (length
,
7722 fragP
->fr_literal
+ fragP
->fr_fix
);
7723 fragP
->fr_fix
+= length
;
7724 fragP
->fr_var
-= length
;
7726 bytes_added
+= length
;
7732 gas_assert (fragP
->fr_type
!= rs_machine_dependent
7733 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
7739 static offsetT
unrelaxed_frag_min_size (fragS
*);
7742 min_bytes_to_other_loop_end (fragS
*fragP
,
7743 fragS
*current_target
,
7747 fragS
*current_fragP
;
7749 for (current_fragP
= fragP
;
7751 current_fragP
= current_fragP
->fr_next
)
7753 if (current_fragP
->tc_frag_data
.is_loop_target
7754 && current_fragP
!= current_target
)
7757 offset
+= unrelaxed_frag_min_size (current_fragP
);
7759 if (offset
>= max_size
)
7767 unrelaxed_frag_min_size (fragS
*fragP
)
7769 offsetT size
= fragP
->fr_fix
;
7771 /* Add fill size. */
7772 if (fragP
->fr_type
== rs_fill
)
7773 size
+= fragP
->fr_offset
;
7780 unrelaxed_frag_max_size (fragS
*fragP
)
7782 offsetT size
= fragP
->fr_fix
;
7783 switch (fragP
->fr_type
)
7786 /* Empty frags created by the obstack allocation scheme
7787 end up with type 0. */
7792 size
+= fragP
->fr_offset
;
7800 /* No further adjustments needed. */
7802 case rs_machine_dependent
:
7803 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
7804 size
+= fragP
->fr_var
;
7807 /* We had darn well better know how big it is. */
7816 /* Re-process all of the fragments looking to convert all
7817 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
7820 1) the instruction size count to the loop end label
7821 is too short (<= 2 instructions),
7822 2) loop has a jump or branch in it
7825 1) workaround_all_short_loops is TRUE
7826 2) The generating loop was a 'loopgtz' or 'loopnez'
7827 3) the instruction size count to the loop end label is too short
7829 then convert this frag (and maybe the next one) to generate a NOP.
7830 In any case close it off with a .fill 0. */
7832 static int count_insns_to_loop_end (fragS
*, bfd_boolean
, int);
7833 static bfd_boolean
branch_before_loop_end (fragS
*);
7836 xtensa_fix_short_loop_frags (void)
7841 /* When this routine is called, all of the subsections are still intact
7842 so we walk over subsections instead of sections. */
7843 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7844 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7847 fragS
*current_target
= NULL
;
7848 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
7850 /* Walk over all of the fragments in a subsection. */
7851 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7853 if (fragP
->fr_type
== rs_machine_dependent
7854 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7855 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7858 fragS
*loop_frag
= next_non_empty_frag (fragP
);
7859 tinsn_from_chars (&t_insn
, loop_frag
->fr_opcode
, 0);
7860 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7861 current_opcode
= t_insn
.opcode
;
7862 gas_assert (xtensa_opcode_is_loop (xtensa_default_isa
,
7863 current_opcode
) == 1);
7866 if (fragP
->fr_type
== rs_machine_dependent
7867 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7869 if (count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3) < 3
7870 && (branch_before_loop_end (fragP
->fr_next
)
7871 || (workaround_all_short_loops
7872 && current_opcode
!= XTENSA_UNDEFINED
7873 && current_opcode
!= xtensa_loop_opcode
)))
7875 if (fragP
->tc_frag_data
.is_no_transform
)
7876 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
7878 relax_frag_add_nop (fragP
);
7887 static int unrelaxed_frag_min_insn_count (fragS
*);
7890 count_insns_to_loop_end (fragS
*base_fragP
,
7891 bfd_boolean count_relax_add
,
7894 fragS
*fragP
= NULL
;
7899 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
7901 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
7902 if (insn_count
>= max_count
)
7905 if (count_relax_add
)
7907 if (fragP
->fr_type
== rs_machine_dependent
7908 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7910 /* In order to add the appropriate number of
7911 NOPs, we count an instruction for downstream
7914 if (insn_count
>= max_count
)
7924 unrelaxed_frag_min_insn_count (fragS
*fragP
)
7926 xtensa_isa isa
= xtensa_default_isa
;
7927 static xtensa_insnbuf insnbuf
= NULL
;
7931 if (!fragP
->tc_frag_data
.is_insn
)
7935 insnbuf
= xtensa_insnbuf_alloc (isa
);
7937 /* Decode the fixed instructions. */
7938 while (offset
< fragP
->fr_fix
)
7942 xtensa_insnbuf_from_chars
7943 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7944 fmt
= xtensa_format_decode (isa
, insnbuf
);
7946 if (fmt
== XTENSA_UNDEFINED
)
7948 as_fatal (_("undecodable instruction in instruction frag"));
7951 offset
+= xtensa_format_length (isa
, fmt
);
7959 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
7962 branch_before_loop_end (fragS
*base_fragP
)
7966 for (fragP
= base_fragP
;
7967 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
7968 fragP
= fragP
->fr_next
)
7970 if (unrelaxed_frag_has_b_j (fragP
))
7978 unrelaxed_frag_has_b_j (fragS
*fragP
)
7980 static xtensa_insnbuf insnbuf
= NULL
;
7981 xtensa_isa isa
= xtensa_default_isa
;
7984 if (!fragP
->tc_frag_data
.is_insn
)
7988 insnbuf
= xtensa_insnbuf_alloc (isa
);
7990 /* Decode the fixed instructions. */
7991 while (offset
< fragP
->fr_fix
)
7996 xtensa_insnbuf_from_chars
7997 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7998 fmt
= xtensa_format_decode (isa
, insnbuf
);
7999 if (fmt
== XTENSA_UNDEFINED
)
8002 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
8004 xtensa_opcode opcode
=
8005 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
8006 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
8007 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
8010 offset
+= xtensa_format_length (isa
, fmt
);
8016 /* Checks to be made after initial assembly but before relaxation. */
8018 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
8019 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
8022 xtensa_sanity_check (void)
8029 as_where (&file_name
, &line
);
8030 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8031 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8035 /* Walk over all of the fragments in a subsection. */
8036 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8038 if (fragP
->fr_type
== rs_machine_dependent
8039 && fragP
->fr_subtype
== RELAX_SLOTS
8040 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
8042 static xtensa_insnbuf insnbuf
= NULL
;
8045 if (fragP
->fr_opcode
!= NULL
)
8048 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
8049 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
8050 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
8052 if (xtensa_opcode_is_loop (xtensa_default_isa
,
8053 t_insn
.opcode
) == 1)
8055 if (is_empty_loop (&t_insn
, fragP
))
8057 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8058 as_bad (_("invalid empty loop"));
8060 if (!is_local_forward_loop (&t_insn
, fragP
))
8062 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8063 as_bad (_("loop target does not follow "
8064 "loop instruction in section"));
8071 new_logical_line (file_name
, line
);
8075 #define LOOP_IMMED_OPN 1
8077 /* Return TRUE if the loop target is the next non-zero fragment. */
8080 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
8082 const expressionS
*expr
;
8086 if (insn
->insn_type
!= ITYPE_INSN
)
8089 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
8092 if (insn
->ntok
<= LOOP_IMMED_OPN
)
8095 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
8097 if (expr
->X_op
!= O_symbol
)
8100 symbolP
= expr
->X_add_symbol
;
8104 if (symbol_get_frag (symbolP
) == NULL
)
8107 if (S_GET_VALUE (symbolP
) != 0)
8110 /* Walk through the zero-size fragments from this one. If we find
8111 the target fragment, then this is a zero-size loop. */
8113 for (next_fragP
= fragP
->fr_next
;
8115 next_fragP
= next_fragP
->fr_next
)
8117 if (next_fragP
== symbol_get_frag (symbolP
))
8119 if (next_fragP
->fr_fix
!= 0)
8127 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
8129 const expressionS
*expr
;
8133 if (insn
->insn_type
!= ITYPE_INSN
)
8136 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
8139 if (insn
->ntok
<= LOOP_IMMED_OPN
)
8142 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
8144 if (expr
->X_op
!= O_symbol
)
8147 symbolP
= expr
->X_add_symbol
;
8151 if (symbol_get_frag (symbolP
) == NULL
)
8154 /* Walk through fragments until we find the target.
8155 If we do not find the target, then this is an invalid loop. */
8157 for (next_fragP
= fragP
->fr_next
;
8159 next_fragP
= next_fragP
->fr_next
)
8161 if (next_fragP
== symbol_get_frag (symbolP
))
8169 #define XTINFO_NAME "Xtensa_Info"
8170 #define XTINFO_NAMESZ 12
8171 #define XTINFO_TYPE 1
8174 xtensa_add_config_info (void)
8180 info_sec
= subseg_new (".xtensa.info", 0);
8181 bfd_set_section_flags (stdoutput
, info_sec
, SEC_HAS_CONTENTS
| SEC_READONLY
);
8183 data
= xmalloc (100);
8184 sprintf (data
, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n",
8185 XSHAL_USE_ABSOLUTE_LITERALS
, XSHAL_ABI
);
8186 sz
= strlen (data
) + 1;
8188 /* Add enough null terminators to pad to a word boundary. */
8191 while ((sz
& 3) != 0);
8193 /* Follow the standard note section layout:
8194 First write the length of the name string. */
8196 md_number_to_chars (p
, (valueT
) XTINFO_NAMESZ
, 4);
8198 /* Next comes the length of the "descriptor", i.e., the actual data. */
8200 md_number_to_chars (p
, (valueT
) sz
, 4);
8202 /* Write the note type. */
8204 md_number_to_chars (p
, (valueT
) XTINFO_TYPE
, 4);
8206 /* Write the name field. */
8207 p
= frag_more (XTINFO_NAMESZ
);
8208 memcpy (p
, XTINFO_NAME
, XTINFO_NAMESZ
);
8210 /* Finally, write the descriptor. */
8212 memcpy (p
, data
, sz
);
8218 /* Alignment Functions. */
8221 get_text_align_power (unsigned target_size
)
8223 if (target_size
<= 4)
8225 gas_assert (target_size
== 8);
8231 get_text_align_max_fill_size (int align_pow
,
8232 bfd_boolean use_nops
,
8233 bfd_boolean use_no_density
)
8236 return (1 << align_pow
);
8238 return 3 * (1 << align_pow
);
8240 return 1 + (1 << align_pow
);
8244 /* Calculate the minimum bytes of fill needed at "address" to align a
8245 target instruction of size "target_size" so that it does not cross a
8246 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE,
8247 the fill can be an arbitrary number of bytes. Otherwise, the space must
8248 be filled by NOP instructions. */
8251 get_text_align_fill_size (addressT address
,
8254 bfd_boolean use_nops
,
8255 bfd_boolean use_no_density
)
8257 addressT alignment
, fill
, fill_limit
, fill_step
;
8258 bfd_boolean skip_one
= FALSE
;
8260 alignment
= (1 << align_pow
);
8261 gas_assert (target_size
> 0 && alignment
>= (addressT
) target_size
);
8265 fill_limit
= alignment
;
8268 else if (!use_no_density
)
8270 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */
8271 fill_limit
= alignment
* 2;
8277 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */
8278 fill_limit
= alignment
* 3;
8282 /* Try all fill sizes until finding one that works. */
8283 for (fill
= 0; fill
< fill_limit
; fill
+= fill_step
)
8285 if (skip_one
&& fill
== 1)
8287 if ((address
+ fill
) >> align_pow
8288 == (address
+ fill
+ target_size
- 1) >> align_pow
)
8297 branch_align_power (segT sec
)
8299 /* If the Xtensa processor has a fetch width of 8 bytes, and the section
8300 is aligned to at least an 8-byte boundary, then a branch target need
8301 only fit within an 8-byte aligned block of memory to avoid a stall.
8302 Otherwise, try to fit branch targets within 4-byte aligned blocks
8303 (which may be insufficient, e.g., if the section has no alignment, but
8304 it's good enough). */
8305 if (xtensa_fetch_width
== 8)
8307 if (get_recorded_alignment (sec
) >= 3)
8311 gas_assert (xtensa_fetch_width
== 4);
8317 /* This will assert if it is not possible. */
8320 get_text_align_nop_count (offsetT fill_size
, bfd_boolean use_no_density
)
8326 gas_assert (fill_size
% 3 == 0);
8327 return (fill_size
/ 3);
8330 gas_assert (fill_size
!= 1); /* Bad argument. */
8332 while (fill_size
> 1)
8335 if (fill_size
== 2 || fill_size
== 4)
8337 fill_size
-= insn_size
;
8340 gas_assert (fill_size
!= 1); /* Bad algorithm. */
8346 get_text_align_nth_nop_size (offsetT fill_size
,
8348 bfd_boolean use_no_density
)
8355 gas_assert (fill_size
!= 1); /* Bad argument. */
8357 while (fill_size
> 1)
8360 if (fill_size
== 2 || fill_size
== 4)
8362 fill_size
-= insn_size
;
8372 /* For the given fragment, find the appropriate address
8373 for it to begin at if we are using NOPs to align it. */
8376 get_noop_aligned_address (fragS
*fragP
, addressT address
)
8378 /* The rule is: get next fragment's FIRST instruction. Find
8379 the smallest number of bytes that need to be added to
8380 ensure that the next fragment's FIRST instruction will fit
8383 E.G., 2 bytes : 0, 1, 2 mod 4
8386 If the FIRST instruction MIGHT be relaxed,
8387 assume that it will become a 3-byte instruction.
8389 Note again here that LOOP instructions are not bundleable,
8390 and this relaxation only applies to LOOP opcodes. */
8393 int first_insn_size
;
8395 addressT pre_opcode_bytes
;
8398 xtensa_opcode opcode
;
8399 bfd_boolean is_loop
;
8401 gas_assert (fragP
->fr_type
== rs_machine_dependent
);
8402 gas_assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
8404 /* Find the loop frag. */
8405 first_insn
= next_non_empty_frag (fragP
);
8406 /* Now find the first insn frag. */
8407 first_insn
= next_non_empty_frag (first_insn
);
8409 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
8410 gas_assert (is_loop
);
8411 loop_insn_size
= xg_get_single_size (opcode
);
8413 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
8414 pre_opcode_bytes
+= loop_insn_size
;
8416 /* For loops, the alignment depends on the size of the
8417 instruction following the loop, not the LOOP instruction. */
8419 if (first_insn
== NULL
)
8420 first_insn_size
= xtensa_fetch_width
;
8422 first_insn_size
= get_loop_align_size (frag_format_size (first_insn
));
8424 /* If it was 8, then we'll need a larger alignment for the section. */
8425 align_power
= get_text_align_power (first_insn_size
);
8426 record_alignment (now_seg
, align_power
);
8428 fill_size
= get_text_align_fill_size
8429 (address
+ pre_opcode_bytes
, align_power
, first_insn_size
, TRUE
,
8430 fragP
->tc_frag_data
.is_no_density
);
8432 return address
+ fill_size
;
8436 /* 3 mechanisms for relaxing an alignment:
8438 Align to a power of 2.
8439 Align so the next fragment's instruction does not cross a word boundary.
8440 Align the current instruction so that if the next instruction
8441 were 3 bytes, it would not cross a word boundary.
8445 zeros - This is easy; always insert zeros.
8446 nops - 3-byte and 2-byte instructions
8450 >=5 : 3-byte instruction + fn (n-3)
8451 widening - widen previous instructions. */
8454 get_aligned_diff (fragS
*fragP
, addressT address
, offsetT
*max_diff
)
8456 addressT target_address
, loop_insn_offset
;
8458 xtensa_opcode loop_opcode
;
8459 bfd_boolean is_loop
;
8462 offsetT branch_align
;
8465 gas_assert (fragP
->fr_type
== rs_machine_dependent
);
8466 switch (fragP
->fr_subtype
)
8468 case RELAX_DESIRE_ALIGN
:
8469 target_size
= next_frag_format_size (fragP
);
8470 if (target_size
== XTENSA_UNDEFINED
)
8472 align_power
= branch_align_power (now_seg
);
8473 branch_align
= 1 << align_power
;
8474 /* Don't count on the section alignment being as large as the target. */
8475 if (target_size
> branch_align
)
8476 target_size
= branch_align
;
8477 opt_diff
= get_text_align_fill_size (address
, align_power
,
8478 target_size
, FALSE
, FALSE
);
8480 *max_diff
= (opt_diff
+ branch_align
8481 - (target_size
+ ((address
+ opt_diff
) % branch_align
)));
8482 gas_assert (*max_diff
>= opt_diff
);
8485 case RELAX_ALIGN_NEXT_OPCODE
:
8486 /* The next non-empty frag after this one holds the LOOP instruction
8487 that needs to be aligned. The required alignment depends on the
8488 size of the next non-empty frag after the loop frag, i.e., the
8489 first instruction in the loop. */
8490 loop_frag
= next_non_empty_frag (fragP
);
8491 target_size
= get_loop_align_size (next_frag_format_size (loop_frag
));
8492 loop_insn_offset
= 0;
8493 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
8494 gas_assert (is_loop
);
8496 /* If the loop has been expanded then the LOOP instruction
8497 could be at an offset from this fragment. */
8498 if (loop_frag
->tc_frag_data
.slot_subtypes
[0] != RELAX_IMMED
)
8499 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
8501 /* In an ideal world, which is what we are shooting for here,
8502 we wouldn't need to use any NOPs immediately prior to the
8503 LOOP instruction. If this approach fails, relax_frag_loop_align
8504 will call get_noop_aligned_address. */
8506 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
8507 align_power
= get_text_align_power (target_size
);
8508 opt_diff
= get_text_align_fill_size (target_address
, align_power
,
8509 target_size
, FALSE
, FALSE
);
8511 *max_diff
= xtensa_fetch_width
8512 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
8513 - target_size
+ opt_diff
;
8514 gas_assert (*max_diff
>= opt_diff
);
8525 /* md_relax_frag Hook and Helper Functions. */
8527 static long relax_frag_loop_align (fragS
*, long);
8528 static long relax_frag_for_align (fragS
*, long);
8529 static long relax_frag_immed
8530 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
8533 /* Return the number of bytes added to this fragment, given that the
8534 input has been stretched already by "stretch". */
8537 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
8539 xtensa_isa isa
= xtensa_default_isa
;
8540 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
8541 long new_stretch
= 0;
8545 static xtensa_insnbuf vbuf
= NULL
;
8546 int slot
, num_slots
;
8549 as_where (&file_name
, &line
);
8550 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8552 fragP
->tc_frag_data
.unreported_expansion
= 0;
8554 switch (fragP
->fr_subtype
)
8556 case RELAX_ALIGN_NEXT_OPCODE
:
8557 /* Always convert. */
8558 if (fragP
->tc_frag_data
.relax_seen
)
8559 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
8562 case RELAX_LOOP_END
:
8566 case RELAX_LOOP_END_ADD_NOP
:
8567 /* Add a NOP and switch to .fill 0. */
8568 new_stretch
= relax_frag_add_nop (fragP
);
8572 case RELAX_DESIRE_ALIGN
:
8573 /* Do nothing. The narrowing before this frag will either align
8578 case RELAX_LITERAL_FINAL
:
8581 case RELAX_LITERAL_NR
:
8583 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
8584 gas_assert (unreported
== lit_size
);
8585 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
8586 fragP
->fr_var
-= lit_size
;
8587 fragP
->fr_fix
+= lit_size
;
8593 vbuf
= xtensa_insnbuf_alloc (isa
);
8595 xtensa_insnbuf_from_chars
8596 (isa
, vbuf
, (unsigned char *) fragP
->fr_opcode
, 0);
8597 fmt
= xtensa_format_decode (isa
, vbuf
);
8598 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8600 for (slot
= 0; slot
< num_slots
; slot
++)
8602 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
8605 if (fragP
->tc_frag_data
.relax_seen
)
8606 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8610 case RELAX_IMMED_STEP1
:
8611 case RELAX_IMMED_STEP2
:
8612 case RELAX_IMMED_STEP3
:
8613 /* Place the immediate. */
8614 new_stretch
+= relax_frag_immed
8615 (now_seg
, fragP
, stretch
,
8616 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8617 fmt
, slot
, stretched_p
, FALSE
);
8621 /* This is OK; see the note in xg_assemble_vliw_tokens. */
8627 case RELAX_LITERAL_POOL_BEGIN
:
8628 case RELAX_LITERAL_POOL_END
:
8629 case RELAX_MAYBE_UNREACHABLE
:
8630 case RELAX_MAYBE_DESIRE_ALIGN
:
8631 /* No relaxation required. */
8634 case RELAX_FILL_NOP
:
8635 case RELAX_UNREACHABLE
:
8636 if (fragP
->tc_frag_data
.relax_seen
)
8637 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8641 as_bad (_("bad relaxation state"));
8644 /* Tell gas we need another relaxation pass. */
8645 if (! fragP
->tc_frag_data
.relax_seen
)
8647 fragP
->tc_frag_data
.relax_seen
= TRUE
;
8651 new_logical_line (file_name
, line
);
8657 relax_frag_loop_align (fragS
*fragP
, long stretch
)
8659 addressT old_address
, old_next_address
, old_size
;
8660 addressT new_address
, new_next_address
, new_size
;
8663 /* All the frags with relax_frag_for_alignment prior to this one in the
8664 section have been done, hopefully eliminating the need for a NOP here.
8665 But, this will put it in if necessary. */
8667 /* Calculate the old address of this fragment and the next fragment. */
8668 old_address
= fragP
->fr_address
- stretch
;
8669 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
8670 fragP
->tc_frag_data
.text_expansion
[0]);
8671 old_size
= old_next_address
- old_address
;
8673 /* Calculate the new address of this fragment and the next fragment. */
8674 new_address
= fragP
->fr_address
;
8676 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
8677 new_size
= new_next_address
- new_address
;
8679 growth
= new_size
- old_size
;
8681 /* Fix up the text_expansion field and return the new growth. */
8682 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
8687 /* Add a NOP instruction. */
8690 relax_frag_add_nop (fragS
*fragP
)
8692 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
8693 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
8694 assemble_nop (length
, nop_buf
);
8695 fragP
->tc_frag_data
.is_insn
= TRUE
;
8697 if (fragP
->fr_var
< length
)
8699 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP
->fr_var
, length
);
8703 fragP
->fr_fix
+= length
;
8704 fragP
->fr_var
-= length
;
8709 static long future_alignment_required (fragS
*, long);
8712 relax_frag_for_align (fragS
*fragP
, long stretch
)
8714 /* Overview of the relaxation procedure for alignment:
8715 We can widen with NOPs or by widening instructions or by filling
8716 bytes after jump instructions. Find the opportune places and widen
8717 them if necessary. */
8722 gas_assert (fragP
->fr_subtype
== RELAX_FILL_NOP
8723 || fragP
->fr_subtype
== RELAX_UNREACHABLE
8724 || (fragP
->fr_subtype
== RELAX_SLOTS
8725 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
8727 stretch_me
= future_alignment_required (fragP
, stretch
);
8728 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
8734 /* We expanded on a previous pass. Can we shrink now? */
8735 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
8736 if (shrink
<= stretch
&& stretch
> 0)
8738 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8744 /* Below here, diff > 0. */
8745 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8751 /* Return the address of the next frag that should be aligned.
8753 By "address" we mean the address it _would_ be at if there
8754 is no action taken to align it between here and the target frag.
8755 In other words, if no narrows and no fill nops are used between
8756 here and the frag to align, _even_if_ some of the frags we use
8757 to align targets have already expanded on a previous relaxation
8760 Also, count each frag that may be used to help align the target.
8762 Return 0 if there are no frags left in the chain that need to be
8766 find_address_of_next_align_frag (fragS
**fragPP
,
8770 bfd_boolean
*paddable
)
8772 fragS
*fragP
= *fragPP
;
8773 addressT address
= fragP
->fr_address
;
8775 /* Do not reset the counts to 0. */
8779 /* Limit this to a small search. */
8780 if (*widens
>= (int) xtensa_fetch_width
)
8785 address
+= fragP
->fr_fix
;
8787 if (fragP
->fr_type
== rs_fill
)
8788 address
+= fragP
->fr_offset
* fragP
->fr_var
;
8789 else if (fragP
->fr_type
== rs_machine_dependent
)
8791 switch (fragP
->fr_subtype
)
8793 case RELAX_UNREACHABLE
:
8797 case RELAX_FILL_NOP
:
8799 if (!fragP
->tc_frag_data
.is_no_density
)
8804 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8809 address
+= total_frag_text_expansion (fragP
);;
8813 address
+= fragP
->tc_frag_data
.text_expansion
[0];
8816 case RELAX_ALIGN_NEXT_OPCODE
:
8817 case RELAX_DESIRE_ALIGN
:
8821 case RELAX_MAYBE_UNREACHABLE
:
8822 case RELAX_MAYBE_DESIRE_ALIGN
:
8827 /* Just punt if we don't know the type. */
8834 /* Just punt if we don't know the type. */
8838 fragP
= fragP
->fr_next
;
8846 static long bytes_to_stretch (fragS
*, int, int, int, int);
8849 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
8851 fragS
*this_frag
= fragP
;
8855 int narrow_nops
= 0;
8856 bfd_boolean paddable
= FALSE
;
8857 offsetT local_opt_diff
;
8860 int stretch_amount
= 0;
8861 int local_stretch_amount
;
8862 int global_stretch_amount
;
8864 address
= find_address_of_next_align_frag
8865 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
8869 if (this_frag
->tc_frag_data
.is_aligning_branch
)
8870 this_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
8872 frag_wane (this_frag
);
8876 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
8877 opt_diff
= local_opt_diff
;
8878 gas_assert (opt_diff
>= 0);
8879 gas_assert (max_diff
>= opt_diff
);
8884 fragP
= fragP
->fr_next
;
8886 while (fragP
&& opt_diff
< max_diff
&& address
)
8888 /* We only use these to determine if we can exit early
8889 because there will be plenty of ways to align future
8891 int glob_widens
= 0;
8894 bfd_boolean glob_pad
= 0;
8895 address
= find_address_of_next_align_frag
8896 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
8897 /* If there is a padable portion, then skip. */
8898 if (glob_pad
|| glob_widens
>= (1 << branch_align_power (now_seg
)))
8903 offsetT next_m_diff
;
8904 offsetT next_o_diff
;
8906 /* Downrange frags haven't had stretch added to them yet. */
8909 /* The address also includes any text expansion from this
8910 frag in a previous pass, but we don't want that. */
8911 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
8913 /* Assume we are going to move at least opt_diff. In
8914 reality, we might not be able to, but assuming that
8915 we will helps catch cases where moving opt_diff pushes
8916 the next target from aligned to unaligned. */
8917 address
+= opt_diff
;
8919 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
8921 /* Now cleanup for the adjustments to address. */
8922 next_o_diff
+= opt_diff
;
8923 next_m_diff
+= opt_diff
;
8924 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
8925 opt_diff
= next_o_diff
;
8926 if (next_m_diff
< max_diff
)
8927 max_diff
= next_m_diff
;
8928 fragP
= fragP
->fr_next
;
8932 /* If there are enough wideners in between, do it. */
8935 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
8937 gas_assert (opt_diff
<= UNREACHABLE_MAX_WIDTH
);
8942 local_stretch_amount
8943 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8944 num_widens
, local_opt_diff
);
8945 global_stretch_amount
8946 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8947 num_widens
, opt_diff
);
8948 /* If the condition below is true, then the frag couldn't
8949 stretch the correct amount for the global case, so we just
8950 optimize locally. We'll rely on the subsequent frags to get
8951 the correct alignment in the global case. */
8952 if (global_stretch_amount
< local_stretch_amount
)
8953 stretch_amount
= local_stretch_amount
;
8955 stretch_amount
= global_stretch_amount
;
8957 if (this_frag
->fr_subtype
== RELAX_SLOTS
8958 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8959 gas_assert (stretch_amount
<= 1);
8960 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8962 if (this_frag
->tc_frag_data
.is_no_density
)
8963 gas_assert (stretch_amount
== 3 || stretch_amount
== 0);
8965 gas_assert (stretch_amount
<= 3);
8968 return stretch_amount
;
8972 /* The idea: widen everything you can to get a target or loop aligned,
8973 then start using NOPs.
8975 When we must have a NOP, here is a table of how we decide
8976 (so you don't have to fight through the control flow below):
8978 wide_nops = the number of wide NOPs available for aligning
8979 narrow_nops = the number of narrow NOPs available for aligning
8980 (a subset of wide_nops)
8981 widens = the number of narrow instructions that should be widened
8988 b 0 1 1 (case 3a makes this case unnecessary)
8991 c 0 1 2 (case 4a makes this case unnecessary)
8994 c 0 2 1 (case 5b makes this case unnecessary)
8997 c 0 1 4 (case 6b makes this case unnecessary)
8998 d 1 1 1 (case 6a makes this case unnecessary)
8999 e 0 2 2 (case 6a makes this case unnecessary)
9000 f 0 3 0 (case 6a makes this case unnecessary)
9003 c 1 1 2 (case 7b makes this case unnecessary)
9004 d 0 1 5 (case 7a makes this case unnecessary)
9005 e 0 2 3 (case 7b makes this case unnecessary)
9006 f 0 3 1 (case 7b makes this case unnecessary)
9007 g 1 2 1 (case 7b makes this case unnecessary)
9011 bytes_to_stretch (fragS
*this_frag
,
9017 int bytes_short
= desired_diff
- num_widens
;
9019 gas_assert (desired_diff
>= 0 && desired_diff
< 8);
9020 if (desired_diff
== 0)
9023 gas_assert (wide_nops
> 0 || num_widens
> 0);
9025 /* Always prefer widening to NOP-filling. */
9026 if (bytes_short
< 0)
9028 /* There are enough RELAX_NARROW frags after this one
9029 to align the target without widening this frag in any way. */
9033 if (bytes_short
== 0)
9035 /* Widen every narrow between here and the align target
9036 and the align target will be properly aligned. */
9037 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9043 /* From here we will need at least one NOP to get an alignment.
9044 However, we may not be able to align at all, in which case,
9046 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9048 switch (desired_diff
)
9053 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 1)
9054 return 2; /* case 2 */
9060 return 3; /* case 3a */
9062 if (num_widens
>= 1 && wide_nops
== 1)
9063 return 3; /* case 4a */
9064 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 2)
9065 return 2; /* case 4b */
9068 if (num_widens
>= 2 && wide_nops
== 1)
9069 return 3; /* case 5a */
9070 /* We will need two nops. Are there enough nops
9071 between here and the align target? */
9072 if (wide_nops
< 2 || narrow_nops
== 0)
9074 /* Are there other nops closer that can serve instead? */
9075 if (wide_nops
> 2 && narrow_nops
> 1)
9077 /* Take the density one first, because there might not be
9078 another density one available. */
9079 if (!this_frag
->tc_frag_data
.is_no_density
)
9080 return 2; /* case 5b narrow */
9082 return 3; /* case 5b wide */
9086 return 3; /* case 6a */
9087 else if (num_widens
>= 3 && wide_nops
== 1)
9088 return 3; /* case 6b */
9091 if (wide_nops
== 1 && num_widens
>= 4)
9092 return 3; /* case 7a */
9093 else if (wide_nops
== 2 && num_widens
>= 1)
9094 return 3; /* case 7b */
9102 /* We will need a NOP no matter what, but should we widen
9103 this instruction to help?
9105 This is a RELAX_NARROW frag. */
9106 switch (desired_diff
)
9115 if (wide_nops
>= 1 && num_widens
== 1)
9116 return 1; /* case 4a */
9119 if (wide_nops
>= 1 && num_widens
== 2)
9120 return 1; /* case 5a */
9124 return 0; /* case 6a */
9125 else if (wide_nops
>= 1 && num_widens
== 3)
9126 return 1; /* case 6b */
9129 if (wide_nops
>= 1 && num_widens
== 4)
9130 return 1; /* case 7a */
9131 else if (wide_nops
>= 2 && num_widens
== 1)
9132 return 1; /* case 7b */
9145 relax_frag_immed (segT segP
,
9152 bfd_boolean estimate_only
)
9156 bfd_boolean negatable_branch
= FALSE
;
9157 bfd_boolean branch_jmp_to_next
= FALSE
;
9158 bfd_boolean from_wide_insn
= FALSE
;
9159 xtensa_isa isa
= xtensa_default_isa
;
9161 offsetT frag_offset
;
9163 int num_text_bytes
, num_literal_bytes
;
9164 int literal_diff
, total_text_diff
, this_text_diff
;
9166 gas_assert (fragP
->fr_opcode
!= NULL
);
9168 xg_clear_vinsn (&cur_vinsn
);
9169 vinsn_from_chars (&cur_vinsn
, fragP
->fr_opcode
);
9170 if (cur_vinsn
.num_slots
> 1)
9171 from_wide_insn
= TRUE
;
9173 tinsn
= cur_vinsn
.slots
[slot
];
9174 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
9176 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
) == 1)
9179 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9180 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
9182 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
9184 old_size
= xtensa_format_length (isa
, fmt
);
9186 /* Special case: replace a branch to the next instruction with a NOP.
9187 This is required to work around a hardware bug in T1040.0 and also
9188 serves as an optimization. */
9190 if (branch_jmp_to_next
9191 && ((old_size
== 2) || (old_size
== 3))
9192 && !next_frag_is_loop_target (fragP
))
9195 /* Here is the fun stuff: Get the immediate field from this
9196 instruction. If it fits, we are done. If not, find the next
9197 instruction sequence that fits. */
9199 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9200 istack_init (&istack
);
9201 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
9202 min_steps
, stretch
);
9203 gas_assert (num_steps
>= min_steps
&& num_steps
<= RELAX_IMMED_MAXSTEPS
);
9205 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
9207 /* Figure out the number of bytes needed. */
9208 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
9210 = num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
9211 num_text_bytes
= get_num_stack_text_bytes (&istack
);
9216 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
9219 num_text_bytes
+= old_size
;
9220 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
9221 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
9224 /* The first instruction in the relaxed sequence will go after
9225 the current wide instruction, and thus its symbolic immediates
9228 istack_init (&istack
);
9229 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
,
9230 frag_offset
+ old_size
,
9231 min_steps
, stretch
+ old_size
);
9232 gas_assert (num_steps
>= min_steps
&& num_steps
<= RELAX_IMMED_MAXSTEPS
);
9234 fragP
->tc_frag_data
.slot_subtypes
[slot
]
9235 = (int) RELAX_IMMED
+ num_steps
;
9237 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
9239 = num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
9241 num_text_bytes
= get_num_stack_text_bytes (&istack
) + old_size
;
9245 total_text_diff
= num_text_bytes
- old_size
;
9246 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
9248 /* It MUST get larger. If not, we could get an infinite loop. */
9249 gas_assert (num_text_bytes
>= 0);
9250 gas_assert (literal_diff
>= 0);
9251 gas_assert (total_text_diff
>= 0);
9253 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
9254 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
9255 gas_assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
9256 gas_assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
9258 /* Find the associated expandable literal for this. */
9259 if (literal_diff
!= 0)
9261 fragS
*lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
9264 gas_assert (literal_diff
== 4);
9265 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
9267 /* We expect that the literal section state has NOT been
9269 gas_assert (lit_fragP
->fr_type
== rs_machine_dependent
9270 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
9271 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
9273 /* We need to mark this section for another iteration
9279 if (negatable_branch
&& istack
.ninsn
> 1)
9280 update_next_frag_state (fragP
);
9282 return this_text_diff
;
9286 /* md_convert_frag Hook and Helper Functions. */
9288 static void convert_frag_align_next_opcode (fragS
*);
9289 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
9290 static void convert_frag_fill_nop (fragS
*);
9291 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
9294 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
9296 static xtensa_insnbuf vbuf
= NULL
;
9297 xtensa_isa isa
= xtensa_default_isa
;
9304 as_where (&file_name
, &line
);
9305 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
9307 switch (fragp
->fr_subtype
)
9309 case RELAX_ALIGN_NEXT_OPCODE
:
9310 /* Always convert. */
9311 convert_frag_align_next_opcode (fragp
);
9314 case RELAX_DESIRE_ALIGN
:
9315 /* Do nothing. If not aligned already, too bad. */
9319 case RELAX_LITERAL_FINAL
:
9324 vbuf
= xtensa_insnbuf_alloc (isa
);
9326 xtensa_insnbuf_from_chars
9327 (isa
, vbuf
, (unsigned char *) fragp
->fr_opcode
, 0);
9328 fmt
= xtensa_format_decode (isa
, vbuf
);
9329 num_slots
= xtensa_format_num_slots (isa
, fmt
);
9331 for (slot
= 0; slot
< num_slots
; slot
++)
9333 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
9336 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
9340 case RELAX_IMMED_STEP1
:
9341 case RELAX_IMMED_STEP2
:
9342 case RELAX_IMMED_STEP3
:
9343 /* Place the immediate. */
9346 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
9351 /* This is OK because some slots could have
9352 relaxations and others have none. */
9358 case RELAX_UNREACHABLE
:
9359 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
9360 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
9361 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
9365 case RELAX_MAYBE_UNREACHABLE
:
9366 case RELAX_MAYBE_DESIRE_ALIGN
:
9370 case RELAX_FILL_NOP
:
9371 convert_frag_fill_nop (fragp
);
9374 case RELAX_LITERAL_NR
:
9375 if (use_literal_section
)
9377 /* This should have been handled during relaxation. When
9378 relaxing a code segment, literals sometimes need to be
9379 added to the corresponding literal segment. If that
9380 literal segment has already been relaxed, then we end up
9381 in this situation. Marking the literal segments as data
9382 would make this happen less often (since GAS always relaxes
9383 code before data), but we could still get into trouble if
9384 there are instructions in a segment that is not marked as
9385 containing code. Until we can implement a better solution,
9386 cheat and adjust the addresses of all the following frags.
9387 This could break subsequent alignments, but the linker's
9388 literal coalescing will do that anyway. */
9391 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
9392 gas_assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
9393 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
9396 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
9400 as_bad (_("invalid relaxation fragment result"));
9405 new_logical_line (file_name
, line
);
9410 convert_frag_align_next_opcode (fragS
*fragp
)
9412 char *nop_buf
; /* Location for Writing. */
9413 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
9414 addressT aligned_address
;
9418 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
9420 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
9421 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
9422 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
9424 for (nop
= 0; nop
< nop_count
; nop
++)
9427 nop_size
= get_text_align_nth_nop_size (fill_size
, nop
, use_no_density
);
9429 assemble_nop (nop_size
, nop_buf
);
9430 nop_buf
+= nop_size
;
9433 fragp
->fr_fix
+= fill_size
;
9434 fragp
->fr_var
-= fill_size
;
9439 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
9441 TInsn tinsn
, single_target
;
9442 int size
, old_size
, diff
;
9443 offsetT frag_offset
;
9445 gas_assert (slot
== 0);
9446 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
9448 if (fragP
->tc_frag_data
.is_aligning_branch
== 1)
9450 gas_assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
9451 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
9452 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
9457 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
9459 /* No conversion. */
9464 gas_assert (fragP
->fr_opcode
!= NULL
);
9466 /* Frags in this relaxation state should only contain
9467 single instruction bundles. */
9468 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
9470 /* Just convert it to a wide form.... */
9472 old_size
= xg_get_single_size (tinsn
.opcode
);
9474 tinsn_init (&single_target
);
9475 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9477 if (! xg_is_single_relaxable_insn (&tinsn
, &single_target
, FALSE
))
9479 as_bad (_("unable to widen instruction"));
9483 size
= xg_get_single_size (single_target
.opcode
);
9484 xg_emit_insn_to_buf (&single_target
, fragP
->fr_opcode
, fragP
,
9487 diff
= size
- old_size
;
9488 gas_assert (diff
>= 0);
9489 gas_assert (diff
<= fragP
->fr_var
);
9490 fragP
->fr_var
-= diff
;
9491 fragP
->fr_fix
+= diff
;
9499 convert_frag_fill_nop (fragS
*fragP
)
9501 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
9502 int size
= fragP
->tc_frag_data
.text_expansion
[0];
9503 gas_assert ((unsigned) size
== (fragP
->fr_next
->fr_address
9504 - fragP
->fr_address
- fragP
->fr_fix
));
9507 /* No conversion. */
9511 assemble_nop (size
, loc
);
9512 fragP
->tc_frag_data
.is_insn
= TRUE
;
9513 fragP
->fr_var
-= size
;
9514 fragP
->fr_fix
+= size
;
9519 static fixS
*fix_new_exp_in_seg
9520 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
9521 bfd_reloc_code_real_type
);
9522 static void convert_frag_immed_finish_loop (segT
, fragS
*, TInsn
*);
9525 convert_frag_immed (segT segP
,
9531 char *immed_instr
= fragP
->fr_opcode
;
9533 bfd_boolean expanded
= FALSE
;
9534 bfd_boolean branch_jmp_to_next
= FALSE
;
9535 char *fr_opcode
= fragP
->fr_opcode
;
9536 xtensa_isa isa
= xtensa_default_isa
;
9537 bfd_boolean from_wide_insn
= FALSE
;
9539 bfd_boolean is_loop
;
9541 gas_assert (fr_opcode
!= NULL
);
9543 xg_clear_vinsn (&cur_vinsn
);
9545 vinsn_from_chars (&cur_vinsn
, fr_opcode
);
9546 if (cur_vinsn
.num_slots
> 1)
9547 from_wide_insn
= TRUE
;
9549 orig_tinsn
= cur_vinsn
.slots
[slot
];
9550 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
9552 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
9554 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9555 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
9557 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
9559 /* Conversion just inserts a NOP and marks the fix as completed. */
9560 bytes
= xtensa_format_length (isa
, fmt
);
9563 cur_vinsn
.slots
[slot
].opcode
=
9564 xtensa_format_slot_nop_opcode (isa
, cur_vinsn
.format
, slot
);
9565 cur_vinsn
.slots
[slot
].ntok
= 0;
9569 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
9570 gas_assert (bytes
== 2 || bytes
== 3);
9571 build_nop (&cur_vinsn
.slots
[0], bytes
);
9572 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
9574 vinsn_to_insnbuf (&cur_vinsn
, fr_opcode
, frag_now
, TRUE
);
9575 xtensa_insnbuf_to_chars
9576 (isa
, cur_vinsn
.insnbuf
, (unsigned char *) fr_opcode
, 0);
9581 /* Here is the fun stuff: Get the immediate field from this
9582 instruction. If it fits, we're done. If not, find the next
9583 instruction sequence that fits. */
9587 symbolS
*lit_sym
= NULL
;
9589 int target_offset
= 0;
9592 symbolS
*gen_label
= NULL
;
9593 offsetT frag_offset
;
9594 bfd_boolean first
= TRUE
;
9595 bfd_boolean last_is_jump
;
9597 /* It does not fit. Find something that does and
9598 convert immediately. */
9599 frag_offset
= fr_opcode
- fragP
->fr_literal
;
9600 istack_init (&istack
);
9601 xg_assembly_relax (&istack
, &orig_tinsn
,
9602 segP
, fragP
, frag_offset
, min_steps
, 0);
9604 old_size
= xtensa_format_length (isa
, fmt
);
9606 /* Assemble this right inline. */
9608 /* First, create the mapping from a label name to the REAL label. */
9610 for (i
= 0; i
< istack
.ninsn
; i
++)
9612 TInsn
*tinsn
= &istack
.insn
[i
];
9615 switch (tinsn
->insn_type
)
9618 if (lit_sym
!= NULL
)
9619 as_bad (_("multiple literals in expansion"));
9620 /* First find the appropriate space in the literal pool. */
9621 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9622 if (lit_frag
== NULL
)
9623 as_bad (_("no registered fragment for literal"));
9624 if (tinsn
->ntok
!= 1)
9625 as_bad (_("number of literal tokens != 1"));
9627 /* Set the literal symbol and add a fixup. */
9628 lit_sym
= lit_frag
->fr_symbol
;
9632 if (align_targets
&& !is_loop
)
9634 fragS
*unreach
= fragP
->fr_next
;
9635 while (!(unreach
->fr_type
== rs_machine_dependent
9636 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9637 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
9639 unreach
= unreach
->fr_next
;
9642 gas_assert (unreach
->fr_type
== rs_machine_dependent
9643 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9644 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
9646 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
9648 gas_assert (gen_label
== NULL
);
9649 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
9650 fr_opcode
- fragP
->fr_literal
9651 + target_offset
, fragP
);
9655 if (first
&& from_wide_insn
)
9657 target_offset
+= xtensa_format_length (isa
, fmt
);
9659 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9660 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9663 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9670 last_is_jump
= FALSE
;
9671 for (i
= 0; i
< istack
.ninsn
; i
++)
9673 TInsn
*tinsn
= &istack
.insn
[i
];
9677 bfd_reloc_code_real_type reloc_type
;
9679 switch (tinsn
->insn_type
)
9682 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9683 /* Already checked. */
9684 gas_assert (lit_frag
!= NULL
);
9685 gas_assert (lit_sym
!= NULL
);
9686 gas_assert (tinsn
->ntok
== 1);
9688 target_seg
= S_GET_SEGMENT (lit_sym
);
9689 gas_assert (target_seg
);
9690 reloc_type
= map_operator_to_reloc (tinsn
->tok
[0].X_op
, TRUE
);
9691 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
9692 &tinsn
->tok
[0], FALSE
, reloc_type
);
9699 xg_resolve_labels (tinsn
, gen_label
);
9700 xg_resolve_literals (tinsn
, lit_sym
);
9701 if (from_wide_insn
&& first
)
9704 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9706 cur_vinsn
.slots
[slot
] = *tinsn
;
9710 cur_vinsn
.slots
[slot
].opcode
=
9711 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
9712 cur_vinsn
.slots
[slot
].ntok
= 0;
9714 vinsn_to_insnbuf (&cur_vinsn
, immed_instr
, fragP
, TRUE
);
9715 xtensa_insnbuf_to_chars (isa
, cur_vinsn
.insnbuf
,
9716 (unsigned char *) immed_instr
, 0);
9717 fragP
->tc_frag_data
.is_insn
= TRUE
;
9718 size
= xtensa_format_length (isa
, fmt
);
9719 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9722 (tinsn
, immed_instr
+ size
, fragP
,
9723 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
9724 size
+= xg_get_single_size (tinsn
->opcode
);
9729 size
= xg_get_single_size (tinsn
->opcode
);
9730 xg_emit_insn_to_buf (tinsn
, immed_instr
, fragP
,
9731 immed_instr
- fragP
->fr_literal
, TRUE
);
9733 immed_instr
+= size
;
9739 diff
= total_size
- old_size
;
9740 gas_assert (diff
>= 0);
9743 gas_assert (diff
<= fragP
->fr_var
);
9744 fragP
->fr_var
-= diff
;
9745 fragP
->fr_fix
+= diff
;
9748 /* Check for undefined immediates in LOOP instructions. */
9752 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
9753 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9755 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9758 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
9759 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9761 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9766 if (expanded
&& xtensa_opcode_is_loop (isa
, orig_tinsn
.opcode
) == 1)
9767 convert_frag_immed_finish_loop (segP
, fragP
, &orig_tinsn
);
9769 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
9771 /* Add an expansion note on the expanded instruction. */
9772 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
9773 &orig_tinsn
.tok
[0], TRUE
,
9774 BFD_RELOC_XTENSA_ASM_EXPAND
);
9779 /* Add a new fix expression into the desired segment. We have to
9780 switch to that segment to do this. */
9783 fix_new_exp_in_seg (segT new_seg
,
9790 bfd_reloc_code_real_type r_type
)
9794 subsegT subseg
= now_subseg
;
9796 gas_assert (new_seg
!= 0);
9797 subseg_set (new_seg
, new_subseg
);
9799 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
9800 subseg_set (seg
, subseg
);
9805 /* Relax a loop instruction so that it can span loop >256 bytes.
9811 addi as, as, lo8 (label-.L1)
9812 addmi as, as, mid8 (label-.L1)
9823 convert_frag_immed_finish_loop (segT segP
, fragS
*fragP
, TInsn
*tinsn
)
9828 unsigned long target
;
9829 static xtensa_insnbuf insnbuf
= NULL
;
9830 unsigned int loop_length
, loop_length_hi
, loop_length_lo
;
9831 xtensa_isa isa
= xtensa_default_isa
;
9832 addressT loop_offset
;
9833 addressT addi_offset
= 9;
9834 addressT addmi_offset
= 12;
9839 insnbuf
= xtensa_insnbuf_alloc (isa
);
9841 /* Get the loop offset. */
9842 loop_offset
= get_expanded_loop_offset (tinsn
->opcode
);
9844 /* Validate that there really is a LOOP at the loop_offset. Because
9845 loops are not bundleable, we can assume that the instruction will be
9847 tinsn_from_chars (&loop_insn
, fragP
->fr_opcode
+ loop_offset
, 0);
9848 tinsn_immed_from_frag (&loop_insn
, fragP
, 0);
9850 gas_assert (xtensa_opcode_is_loop (isa
, loop_insn
.opcode
) == 1);
9851 addi_offset
+= loop_offset
;
9852 addmi_offset
+= loop_offset
;
9854 gas_assert (tinsn
->ntok
== 2);
9855 if (tinsn
->tok
[1].X_op
== O_constant
)
9856 target
= tinsn
->tok
[1].X_add_number
;
9857 else if (tinsn
->tok
[1].X_op
== O_symbol
)
9859 /* Find the fragment. */
9860 symbolS
*sym
= tinsn
->tok
[1].X_add_symbol
;
9861 gas_assert (S_GET_SEGMENT (sym
) == segP
9862 || S_GET_SEGMENT (sym
) == absolute_section
);
9863 target
= (S_GET_VALUE (sym
) + tinsn
->tok
[1].X_add_number
);
9867 as_bad (_("invalid expression evaluation type %d"), tinsn
->tok
[1].X_op
);
9871 loop_length
= target
- (fragP
->fr_address
+ fragP
->fr_fix
);
9872 loop_length_hi
= loop_length
& ~0x0ff;
9873 loop_length_lo
= loop_length
& 0x0ff;
9874 if (loop_length_lo
>= 128)
9876 loop_length_lo
-= 256;
9877 loop_length_hi
+= 256;
9880 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
9881 32512. If the loop is larger than that, then we just fail. */
9882 if (loop_length_hi
> 32512)
9883 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9884 _("loop too long for LOOP instruction"));
9886 tinsn_from_chars (&addi_insn
, fragP
->fr_opcode
+ addi_offset
, 0);
9887 gas_assert (addi_insn
.opcode
== xtensa_addi_opcode
);
9889 tinsn_from_chars (&addmi_insn
, fragP
->fr_opcode
+ addmi_offset
, 0);
9890 gas_assert (addmi_insn
.opcode
== xtensa_addmi_opcode
);
9892 set_expr_const (&addi_insn
.tok
[2], loop_length_lo
);
9893 tinsn_to_insnbuf (&addi_insn
, insnbuf
);
9895 fragP
->tc_frag_data
.is_insn
= TRUE
;
9896 xtensa_insnbuf_to_chars
9897 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addi_offset
, 0);
9899 set_expr_const (&addmi_insn
.tok
[2], loop_length_hi
);
9900 tinsn_to_insnbuf (&addmi_insn
, insnbuf
);
9901 xtensa_insnbuf_to_chars
9902 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addmi_offset
, 0);
9904 /* Walk through all of the frags from here to the loop end
9905 and mark them as no_transform to keep them from being modified
9906 by the linker. If we ever have a relocation for the
9907 addi/addmi of the difference of two symbols we can remove this. */
9910 for (next_fragP
= fragP
; next_fragP
!= NULL
;
9911 next_fragP
= next_fragP
->fr_next
)
9913 next_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
9914 if (next_fragP
->tc_frag_data
.is_loop_target
)
9916 if (target_count
== 2)
9922 /* A map that keeps information on a per-subsegment basis. This is
9923 maintained during initial assembly, but is invalid once the
9924 subsegments are smashed together. I.E., it cannot be used during
9927 typedef struct subseg_map_struct
9935 float total_freq
; /* fall-through + branch target frequency */
9936 float target_freq
; /* branch target frequency alone */
9938 struct subseg_map_struct
*next
;
9942 static subseg_map
*sseg_map
= NULL
;
9945 get_subseg_info (segT seg
, subsegT subseg
)
9947 subseg_map
*subseg_e
;
9949 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
9951 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
9959 add_subseg_info (segT seg
, subsegT subseg
)
9961 subseg_map
*subseg_e
= (subseg_map
*) xmalloc (sizeof (subseg_map
));
9962 memset (subseg_e
, 0, sizeof (subseg_map
));
9963 subseg_e
->seg
= seg
;
9964 subseg_e
->subseg
= subseg
;
9965 subseg_e
->flags
= 0;
9966 /* Start off considering every branch target very important. */
9967 subseg_e
->target_freq
= 1.0;
9968 subseg_e
->total_freq
= 1.0;
9969 subseg_e
->next
= sseg_map
;
9970 sseg_map
= subseg_e
;
9976 get_last_insn_flags (segT seg
, subsegT subseg
)
9978 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9980 return subseg_e
->flags
;
9986 set_last_insn_flags (segT seg
,
9991 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9993 subseg_e
= add_subseg_info (seg
, subseg
);
9995 subseg_e
->flags
|= fl
;
9997 subseg_e
->flags
&= ~fl
;
10002 get_subseg_total_freq (segT seg
, subsegT subseg
)
10004 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
10006 return subseg_e
->total_freq
;
10012 get_subseg_target_freq (segT seg
, subsegT subseg
)
10014 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
10016 return subseg_e
->target_freq
;
10022 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
10024 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
10026 subseg_e
= add_subseg_info (seg
, subseg
);
10027 subseg_e
->total_freq
= total_f
;
10028 subseg_e
->target_freq
= target_f
;
10032 /* Segment Lists and emit_state Stuff. */
10035 xtensa_move_seg_list_to_beginning (seg_list
*head
)
10040 segT literal_section
= head
->seg
;
10042 /* Move the literal section to the front of the section list. */
10043 gas_assert (literal_section
);
10044 if (literal_section
!= stdoutput
->sections
)
10046 bfd_section_list_remove (stdoutput
, literal_section
);
10047 bfd_section_list_prepend (stdoutput
, literal_section
);
10054 static void mark_literal_frags (seg_list
*);
10057 xtensa_move_literals (void)
10060 frchainS
*frchain_from
, *frchain_to
;
10061 fragS
*search_frag
, *next_frag
, *last_frag
, *literal_pool
, *insert_after
;
10062 fragS
**frag_splice
;
10065 fixS
*fix
, *next_fix
, **fix_splice
;
10068 mark_literal_frags (literal_head
->next
);
10070 if (use_literal_section
)
10073 for (segment
= literal_head
->next
; segment
; segment
= segment
->next
)
10075 /* Keep the literals for .init and .fini in separate sections. */
10076 if (!strcmp (segment_name (segment
->seg
), INIT_SECTION_NAME
)
10077 || !strcmp (segment_name (segment
->seg
), FINI_SECTION_NAME
))
10080 frchain_from
= seg_info (segment
->seg
)->frchainP
;
10081 search_frag
= frchain_from
->frch_root
;
10082 literal_pool
= NULL
;
10084 frag_splice
= &(frchain_from
->frch_root
);
10086 while (!search_frag
->tc_frag_data
.literal_frag
)
10088 gas_assert (search_frag
->fr_fix
== 0
10089 || search_frag
->fr_type
== rs_align
);
10090 search_frag
= search_frag
->fr_next
;
10093 gas_assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
10094 == RELAX_LITERAL_POOL_BEGIN
);
10095 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
10097 /* Make sure that all the frags in this series are closed, and
10098 that there is at least one left over of zero-size. This
10099 prevents us from making a segment with an frchain without any
10101 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10102 xtensa_set_frag_assembly_state (frag_now
);
10103 last_frag
= frag_now
;
10104 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10105 xtensa_set_frag_assembly_state (frag_now
);
10107 while (search_frag
!= frag_now
)
10109 next_frag
= search_frag
->fr_next
;
10111 /* First, move the frag out of the literal section and
10112 to the appropriate place. */
10113 if (search_frag
->tc_frag_data
.literal_frag
)
10115 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
10116 gas_assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
10117 frchain_to
= literal_pool
->tc_frag_data
.lit_frchain
;
10118 gas_assert (frchain_to
);
10120 insert_after
= literal_pool
->tc_frag_data
.literal_frag
;
10121 dest_seg
= insert_after
->fr_next
->tc_frag_data
.lit_seg
;
10123 *frag_splice
= next_frag
;
10124 search_frag
->fr_next
= insert_after
->fr_next
;
10125 insert_after
->fr_next
= search_frag
;
10126 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
10127 literal_pool
->tc_frag_data
.literal_frag
= search_frag
;
10129 /* Now move any fixups associated with this frag to the
10131 fix
= frchain_from
->fix_root
;
10132 fix_splice
= &(frchain_from
->fix_root
);
10135 next_fix
= fix
->fx_next
;
10136 if (fix
->fx_frag
== search_frag
)
10138 *fix_splice
= next_fix
;
10139 fix
->fx_next
= frchain_to
->fix_root
;
10140 frchain_to
->fix_root
= fix
;
10141 if (frchain_to
->fix_tail
== NULL
)
10142 frchain_to
->fix_tail
= fix
;
10145 fix_splice
= &(fix
->fx_next
);
10148 search_frag
= next_frag
;
10151 if (frchain_from
->fix_root
!= NULL
)
10153 frchain_from
= seg_info (segment
->seg
)->frchainP
;
10154 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
10156 gas_assert (frchain_from
->fix_root
== NULL
);
10158 frchain_from
->fix_tail
= NULL
;
10159 xtensa_restore_emit_state (&state
);
10162 /* Now fix up the SEGMENT value for all the literal symbols. */
10163 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
10165 symbolS
*lit_sym
= lit
->sym
;
10166 segT dest_seg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
10168 S_SET_SEGMENT (lit_sym
, dest_seg
);
10173 /* Walk over all the frags for segments in a list and mark them as
10174 containing literals. As clunky as this is, we can't rely on frag_var
10175 and frag_variant to get called in all situations. */
10178 mark_literal_frags (seg_list
*segment
)
10180 frchainS
*frchain_from
;
10181 fragS
*search_frag
;
10185 frchain_from
= seg_info (segment
->seg
)->frchainP
;
10186 search_frag
= frchain_from
->frch_root
;
10187 while (search_frag
)
10189 search_frag
->tc_frag_data
.is_literal
= TRUE
;
10190 search_frag
= search_frag
->fr_next
;
10192 segment
= segment
->next
;
10198 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
10200 /* Move all of the sections in the section list to come
10201 after "after" in the gnu segment list. */
10206 segT literal_section
= head
->seg
;
10208 /* Move the literal section after "after". */
10209 gas_assert (literal_section
);
10210 if (literal_section
!= after
)
10212 bfd_section_list_remove (stdoutput
, literal_section
);
10213 bfd_section_list_insert_after (stdoutput
, after
, literal_section
);
10221 /* Push all the literal segments to the end of the gnu list. */
10224 xtensa_reorder_segments (void)
10231 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
10237 /* Now that we have the last section, push all the literal
10238 sections to the end. */
10239 xtensa_reorder_seg_list (literal_head
, last_sec
);
10241 /* Now perform the final error check. */
10242 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
10244 gas_assert (new_count
== old_count
);
10248 /* Change the emit state (seg, subseg, and frag related stuff) to the
10249 correct location. Return a emit_state which can be passed to
10250 xtensa_restore_emit_state to return to current fragment. */
10253 xtensa_switch_to_literal_fragment (emit_state
*result
)
10255 if (directive_state
[directive_absolute_literals
])
10257 segT lit4_seg
= cache_literal_section (TRUE
);
10258 xtensa_switch_section_emit_state (result
, lit4_seg
, 0);
10261 xtensa_switch_to_non_abs_literal_fragment (result
);
10263 /* Do a 4-byte align here. */
10264 frag_align (2, 0, 0);
10265 record_alignment (now_seg
, 2);
10270 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
10272 static bfd_boolean recursive
= FALSE
;
10273 fragS
*pool_location
= get_literal_pool_location (now_seg
);
10275 bfd_boolean is_init
=
10276 (now_seg
&& !strcmp (segment_name (now_seg
), INIT_SECTION_NAME
));
10277 bfd_boolean is_fini
=
10278 (now_seg
&& !strcmp (segment_name (now_seg
), FINI_SECTION_NAME
));
10280 if (pool_location
== NULL
10281 && !use_literal_section
10283 && !is_init
&& ! is_fini
)
10285 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
10287 /* When we mark a literal pool location, we want to put a frag in
10288 the literal pool that points to it. But to do that, we want to
10289 switch_to_literal_fragment. But literal sections don't have
10290 literal pools, so their location is always null, so we would
10291 recurse forever. This is kind of hacky, but it works. */
10294 xtensa_mark_literal_pool_location ();
10298 lit_seg
= cache_literal_section (FALSE
);
10299 xtensa_switch_section_emit_state (result
, lit_seg
, 0);
10301 if (!use_literal_section
10302 && !is_init
&& !is_fini
10303 && get_literal_pool_location (now_seg
) != pool_location
)
10305 /* Close whatever frag is there. */
10306 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10307 xtensa_set_frag_assembly_state (frag_now
);
10308 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
10309 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10310 xtensa_set_frag_assembly_state (frag_now
);
10315 /* Call this function before emitting data into the literal section.
10316 This is a helper function for xtensa_switch_to_literal_fragment.
10317 This is similar to a .section new_now_seg subseg. */
10320 xtensa_switch_section_emit_state (emit_state
*state
,
10322 subsegT new_now_subseg
)
10324 state
->name
= now_seg
->name
;
10325 state
->now_seg
= now_seg
;
10326 state
->now_subseg
= now_subseg
;
10327 state
->generating_literals
= generating_literals
;
10328 generating_literals
++;
10329 subseg_set (new_now_seg
, new_now_subseg
);
10333 /* Use to restore the emitting into the normal place. */
10336 xtensa_restore_emit_state (emit_state
*state
)
10338 generating_literals
= state
->generating_literals
;
10339 subseg_set (state
->now_seg
, state
->now_subseg
);
10343 /* Predicate function used to look up a section in a particular group. */
10346 match_section_group (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
, void *inf
)
10348 const char *gname
= inf
;
10349 const char *group_name
= elf_group_name (sec
);
10351 return (group_name
== gname
10352 || (group_name
!= NULL
10354 && strcmp (group_name
, gname
) == 0));
10358 /* Get the literal section to be used for the current text section.
10359 The result may be cached in the default_lit_sections structure. */
10362 cache_literal_section (bfd_boolean use_abs_literals
)
10364 const char *text_name
, *group_name
= 0;
10365 char *base_name
, *name
, *suffix
;
10367 segT seg
, current_section
;
10368 int current_subsec
;
10369 bfd_boolean linkonce
= FALSE
;
10371 /* Save the current section/subsection. */
10372 current_section
= now_seg
;
10373 current_subsec
= now_subseg
;
10375 /* Clear the cached values if they are no longer valid. */
10376 if (now_seg
!= default_lit_sections
.current_text_seg
)
10378 default_lit_sections
.current_text_seg
= now_seg
;
10379 default_lit_sections
.lit_seg
= NULL
;
10380 default_lit_sections
.lit4_seg
= NULL
;
10383 /* Check if the literal section is already cached. */
10384 if (use_abs_literals
)
10385 pcached
= &default_lit_sections
.lit4_seg
;
10387 pcached
= &default_lit_sections
.lit_seg
;
10392 text_name
= default_lit_sections
.lit_prefix
;
10393 if (! text_name
|| ! *text_name
)
10395 text_name
= segment_name (current_section
);
10396 group_name
= elf_group_name (current_section
);
10397 linkonce
= (current_section
->flags
& SEC_LINK_ONCE
) != 0;
10400 base_name
= use_abs_literals
? ".lit4" : ".literal";
10403 name
= xmalloc (strlen (base_name
) + strlen (group_name
) + 2);
10404 sprintf (name
, "%s.%s", base_name
, group_name
);
10406 else if (strncmp (text_name
, ".gnu.linkonce.", linkonce_len
) == 0)
10408 suffix
= strchr (text_name
+ linkonce_len
, '.');
10410 name
= xmalloc (linkonce_len
+ strlen (base_name
) + 1
10411 + (suffix
? strlen (suffix
) : 0));
10412 strcpy (name
, ".gnu.linkonce");
10413 strcat (name
, base_name
);
10415 strcat (name
, suffix
);
10420 /* If the section name ends with ".text", then replace that suffix
10421 instead of appending an additional suffix. */
10422 size_t len
= strlen (text_name
);
10423 if (len
>= 5 && strcmp (text_name
+ len
- 5, ".text") == 0)
10426 name
= xmalloc (len
+ strlen (base_name
) + 1);
10427 strcpy (name
, text_name
);
10428 strcpy (name
+ len
, base_name
);
10431 /* Canonicalize section names to allow renaming literal sections.
10432 The group name, if any, came from the current text section and
10433 has already been canonicalized. */
10434 name
= tc_canonicalize_symbol_name (name
);
10436 seg
= bfd_get_section_by_name_if (stdoutput
, name
, match_section_group
,
10437 (void *) group_name
);
10442 seg
= subseg_force_new (name
, 0);
10444 if (! use_abs_literals
)
10446 /* Add the newly created literal segment to the list. */
10447 seg_list
*n
= (seg_list
*) xmalloc (sizeof (seg_list
));
10449 n
->next
= literal_head
->next
;
10450 literal_head
->next
= n
;
10453 flags
= (SEC_HAS_CONTENTS
| SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
10454 | (linkonce
? (SEC_LINK_ONCE
| SEC_LINK_DUPLICATES_DISCARD
) : 0)
10455 | (use_abs_literals
? SEC_DATA
: SEC_CODE
));
10457 elf_group_name (seg
) = group_name
;
10459 bfd_set_section_flags (stdoutput
, seg
, flags
);
10460 bfd_set_section_alignment (stdoutput
, seg
, 2);
10464 subseg_set (current_section
, current_subsec
);
10469 /* Property Tables Stuff. */
10471 #define XTENSA_INSN_SEC_NAME ".xt.insn"
10472 #define XTENSA_LIT_SEC_NAME ".xt.lit"
10473 #define XTENSA_PROP_SEC_NAME ".xt.prop"
10475 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
10476 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
10478 static bfd_boolean
get_frag_is_literal (const fragS
*);
10479 static void xtensa_create_property_segments
10480 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
10481 static void xtensa_create_xproperty_segments
10482 (frag_flags_fn
, const char *, xt_section_type
);
10483 static bfd_boolean
exclude_section_from_property_tables (segT
);
10484 static bfd_boolean
section_has_property (segT
, frag_predicate
);
10485 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
10486 static void add_xt_block_frags
10487 (segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
10488 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
10489 static void xtensa_frag_flags_init (frag_flags
*);
10490 static void get_frag_property_flags (const fragS
*, frag_flags
*);
10491 static bfd_vma
frag_flags_to_number (const frag_flags
*);
10492 static void add_xt_prop_frags (segT
, xtensa_block_info
**, frag_flags_fn
);
10494 /* Set up property tables after relaxation. */
10497 xtensa_post_relax_hook (void)
10499 xtensa_move_seg_list_to_beginning (literal_head
);
10501 xtensa_find_unmarked_state_frags ();
10502 xtensa_mark_frags_for_org ();
10503 xtensa_mark_difference_of_two_symbols ();
10505 xtensa_create_property_segments (get_frag_is_literal
,
10507 XTENSA_LIT_SEC_NAME
,
10509 xtensa_create_xproperty_segments (get_frag_property_flags
,
10510 XTENSA_PROP_SEC_NAME
,
10513 if (warn_unaligned_branch_targets
)
10514 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
10515 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
10519 /* This function is only meaningful after xtensa_move_literals. */
10522 get_frag_is_literal (const fragS
*fragP
)
10524 gas_assert (fragP
!= NULL
);
10525 return fragP
->tc_frag_data
.is_literal
;
10530 xtensa_create_property_segments (frag_predicate property_function
,
10531 frag_predicate end_property_function
,
10532 const char *section_name_base
,
10533 xt_section_type sec_type
)
10537 /* Walk over all of the current segments.
10538 Walk over each fragment
10539 For each non-empty fragment,
10540 Build a property record (append where possible). */
10542 for (seclist
= &stdoutput
->sections
;
10543 seclist
&& *seclist
;
10544 seclist
= &(*seclist
)->next
)
10546 segT sec
= *seclist
;
10548 if (exclude_section_from_property_tables (sec
))
10551 if (section_has_property (sec
, property_function
))
10553 segment_info_type
*xt_seg_info
;
10554 xtensa_block_info
**xt_blocks
;
10555 segT prop_sec
= xtensa_make_property_section (sec
, section_name_base
);
10557 prop_sec
->output_section
= prop_sec
;
10558 subseg_set (prop_sec
, 0);
10559 xt_seg_info
= seg_info (prop_sec
);
10560 xt_blocks
= &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10562 /* Walk over all of the frchains here and add new sections. */
10563 add_xt_block_frags (sec
, xt_blocks
, property_function
,
10564 end_property_function
);
10568 /* Now we fill them out.... */
10570 for (seclist
= &stdoutput
->sections
;
10571 seclist
&& *seclist
;
10572 seclist
= &(*seclist
)->next
)
10574 segment_info_type
*seginfo
;
10575 xtensa_block_info
*block
;
10576 segT sec
= *seclist
;
10578 seginfo
= seg_info (sec
);
10579 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10583 xtensa_block_info
*cur_block
;
10585 bfd_size_type rec_size
;
10587 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10590 rec_size
= num_recs
* 8;
10591 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10598 subseg_set (sec
, 0);
10599 frag_data
= frag_more (rec_size
);
10601 for (i
= 0; i
< num_recs
; i
++)
10605 /* Write the fixup. */
10606 gas_assert (cur_block
);
10607 fix
= fix_new (frag_now
, i
* 8, 4,
10608 section_symbol (cur_block
->sec
),
10610 FALSE
, BFD_RELOC_32
);
10611 fix
->fx_file
= "<internal>";
10614 /* Write the length. */
10615 md_number_to_chars (&frag_data
[4 + i
* 8],
10616 cur_block
->size
, 4);
10617 cur_block
= cur_block
->next
;
10619 frag_wane (frag_now
);
10621 frag_wane (frag_now
);
10629 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
10630 const char *section_name_base
,
10631 xt_section_type sec_type
)
10635 /* Walk over all of the current segments.
10636 Walk over each fragment.
10637 For each fragment that has instructions,
10638 build an instruction record (append where possible). */
10640 for (seclist
= &stdoutput
->sections
;
10641 seclist
&& *seclist
;
10642 seclist
= &(*seclist
)->next
)
10644 segT sec
= *seclist
;
10646 if (exclude_section_from_property_tables (sec
))
10649 if (section_has_xproperty (sec
, flag_fn
))
10651 segment_info_type
*xt_seg_info
;
10652 xtensa_block_info
**xt_blocks
;
10653 segT prop_sec
= xtensa_make_property_section (sec
, section_name_base
);
10655 prop_sec
->output_section
= prop_sec
;
10656 subseg_set (prop_sec
, 0);
10657 xt_seg_info
= seg_info (prop_sec
);
10658 xt_blocks
= &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10660 /* Walk over all of the frchains here and add new sections. */
10661 add_xt_prop_frags (sec
, xt_blocks
, flag_fn
);
10665 /* Now we fill them out.... */
10667 for (seclist
= &stdoutput
->sections
;
10668 seclist
&& *seclist
;
10669 seclist
= &(*seclist
)->next
)
10671 segment_info_type
*seginfo
;
10672 xtensa_block_info
*block
;
10673 segT sec
= *seclist
;
10675 seginfo
= seg_info (sec
);
10676 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10680 xtensa_block_info
*cur_block
;
10682 bfd_size_type rec_size
;
10684 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10687 rec_size
= num_recs
* (8 + 4);
10688 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10689 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
10696 subseg_set (sec
, 0);
10697 frag_data
= frag_more (rec_size
);
10699 for (i
= 0; i
< num_recs
; i
++)
10703 /* Write the fixup. */
10704 gas_assert (cur_block
);
10705 fix
= fix_new (frag_now
, i
* 12, 4,
10706 section_symbol (cur_block
->sec
),
10708 FALSE
, BFD_RELOC_32
);
10709 fix
->fx_file
= "<internal>";
10712 /* Write the length. */
10713 md_number_to_chars (&frag_data
[4 + i
* 12],
10714 cur_block
->size
, 4);
10715 md_number_to_chars (&frag_data
[8 + i
* 12],
10716 frag_flags_to_number (&cur_block
->flags
),
10718 cur_block
= cur_block
->next
;
10720 frag_wane (frag_now
);
10722 frag_wane (frag_now
);
10730 exclude_section_from_property_tables (segT sec
)
10732 flagword flags
= bfd_get_section_flags (stdoutput
, sec
);
10734 /* Sections that don't contribute to the memory footprint are excluded. */
10735 if ((flags
& SEC_DEBUGGING
)
10736 || !(flags
& SEC_ALLOC
)
10737 || (flags
& SEC_MERGE
))
10740 /* Linker cie and fde optimizations mess up property entries for
10741 eh_frame sections, but there is nothing inside them relevant to
10742 property tables anyway. */
10743 if (strcmp (sec
->name
, ".eh_frame") == 0)
10751 section_has_property (segT sec
, frag_predicate property_function
)
10753 segment_info_type
*seginfo
= seg_info (sec
);
10756 if (seginfo
&& seginfo
->frchainP
)
10758 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10760 if (property_function (fragP
)
10761 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10770 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
10772 segment_info_type
*seginfo
= seg_info (sec
);
10775 if (seginfo
&& seginfo
->frchainP
)
10777 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10779 frag_flags prop_flags
;
10780 property_function (fragP
, &prop_flags
);
10781 if (!xtensa_frag_flags_is_empty (&prop_flags
))
10789 /* Two types of block sections exist right now: literal and insns. */
10792 add_xt_block_frags (segT sec
,
10793 xtensa_block_info
**xt_block
,
10794 frag_predicate property_function
,
10795 frag_predicate end_property_function
)
10797 bfd_vma seg_offset
;
10800 /* Build it if needed. */
10801 while (*xt_block
!= NULL
)
10802 xt_block
= &(*xt_block
)->next
;
10803 /* We are either at NULL at the beginning or at the end. */
10805 /* Walk through the frags. */
10808 if (seg_info (sec
)->frchainP
)
10810 for (fragP
= seg_info (sec
)->frchainP
->frch_root
;
10812 fragP
= fragP
->fr_next
)
10814 if (property_function (fragP
)
10815 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10817 if (*xt_block
!= NULL
)
10819 if ((*xt_block
)->offset
+ (*xt_block
)->size
10820 == fragP
->fr_address
)
10821 (*xt_block
)->size
+= fragP
->fr_fix
;
10823 xt_block
= &((*xt_block
)->next
);
10825 if (*xt_block
== NULL
)
10827 xtensa_block_info
*new_block
= (xtensa_block_info
*)
10828 xmalloc (sizeof (xtensa_block_info
));
10829 new_block
->sec
= sec
;
10830 new_block
->offset
= fragP
->fr_address
;
10831 new_block
->size
= fragP
->fr_fix
;
10832 new_block
->next
= NULL
;
10833 xtensa_frag_flags_init (&new_block
->flags
);
10834 *xt_block
= new_block
;
10836 if (end_property_function
10837 && end_property_function (fragP
))
10839 xt_block
= &((*xt_block
)->next
);
10847 /* Break the encapsulation of add_xt_prop_frags here. */
10850 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
10852 if (prop_flags
->is_literal
10853 || prop_flags
->is_insn
10854 || prop_flags
->is_data
10855 || prop_flags
->is_unreachable
)
10862 xtensa_frag_flags_init (frag_flags
*prop_flags
)
10864 memset (prop_flags
, 0, sizeof (frag_flags
));
10869 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
10871 xtensa_frag_flags_init (prop_flags
);
10872 if (fragP
->tc_frag_data
.is_literal
)
10873 prop_flags
->is_literal
= TRUE
;
10874 if (fragP
->tc_frag_data
.is_specific_opcode
10875 || fragP
->tc_frag_data
.is_no_transform
)
10877 prop_flags
->is_no_transform
= TRUE
;
10878 if (xtensa_frag_flags_is_empty (prop_flags
))
10879 prop_flags
->is_data
= TRUE
;
10881 if (fragP
->tc_frag_data
.is_unreachable
)
10882 prop_flags
->is_unreachable
= TRUE
;
10883 else if (fragP
->tc_frag_data
.is_insn
)
10885 prop_flags
->is_insn
= TRUE
;
10886 if (fragP
->tc_frag_data
.is_loop_target
)
10887 prop_flags
->insn
.is_loop_target
= TRUE
;
10888 if (fragP
->tc_frag_data
.is_branch_target
)
10889 prop_flags
->insn
.is_branch_target
= TRUE
;
10890 if (fragP
->tc_frag_data
.is_no_density
)
10891 prop_flags
->insn
.is_no_density
= TRUE
;
10892 if (fragP
->tc_frag_data
.use_absolute_literals
)
10893 prop_flags
->insn
.is_abslit
= TRUE
;
10895 if (fragP
->tc_frag_data
.is_align
)
10897 prop_flags
->is_align
= TRUE
;
10898 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
10899 if (xtensa_frag_flags_is_empty (prop_flags
))
10900 prop_flags
->is_data
= TRUE
;
10906 frag_flags_to_number (const frag_flags
*prop_flags
)
10909 if (prop_flags
->is_literal
)
10910 num
|= XTENSA_PROP_LITERAL
;
10911 if (prop_flags
->is_insn
)
10912 num
|= XTENSA_PROP_INSN
;
10913 if (prop_flags
->is_data
)
10914 num
|= XTENSA_PROP_DATA
;
10915 if (prop_flags
->is_unreachable
)
10916 num
|= XTENSA_PROP_UNREACHABLE
;
10917 if (prop_flags
->insn
.is_loop_target
)
10918 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
10919 if (prop_flags
->insn
.is_branch_target
)
10921 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
10922 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
10925 if (prop_flags
->insn
.is_no_density
)
10926 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
10927 if (prop_flags
->is_no_transform
)
10928 num
|= XTENSA_PROP_NO_TRANSFORM
;
10929 if (prop_flags
->insn
.is_no_reorder
)
10930 num
|= XTENSA_PROP_INSN_NO_REORDER
;
10931 if (prop_flags
->insn
.is_abslit
)
10932 num
|= XTENSA_PROP_INSN_ABSLIT
;
10934 if (prop_flags
->is_align
)
10936 num
|= XTENSA_PROP_ALIGN
;
10937 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
10945 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
10946 const frag_flags
*prop_flags_2
)
10948 /* Cannot combine with an end marker. */
10950 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
10952 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
10954 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
10957 if (prop_flags_1
->is_insn
)
10959 /* Properties of the beginning of the frag. */
10960 if (prop_flags_2
->insn
.is_loop_target
)
10962 if (prop_flags_2
->insn
.is_branch_target
)
10964 if (prop_flags_1
->insn
.is_no_density
!=
10965 prop_flags_2
->insn
.is_no_density
)
10967 if (prop_flags_1
->is_no_transform
!=
10968 prop_flags_2
->is_no_transform
)
10970 if (prop_flags_1
->insn
.is_no_reorder
!=
10971 prop_flags_2
->insn
.is_no_reorder
)
10973 if (prop_flags_1
->insn
.is_abslit
!=
10974 prop_flags_2
->insn
.is_abslit
)
10978 if (prop_flags_1
->is_align
)
10986 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
10989 unsigned align_bits
;
10991 if (!xt_block
->flags
.is_align
)
10992 return xt_block
->size
;
10994 end_addr
= xt_block
->offset
+ xt_block
->size
;
10995 align_bits
= xt_block
->flags
.alignment
;
10996 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
10997 return end_addr
- xt_block
->offset
;
11002 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
11003 const xtensa_block_info
*xt_block_2
)
11005 if (xt_block
->sec
!= xt_block_2
->sec
)
11007 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
11008 != xt_block_2
->offset
)
11011 if (xt_block_2
->size
== 0
11012 && (!xt_block_2
->flags
.is_unreachable
11013 || xt_block
->flags
.is_unreachable
))
11015 if (xt_block_2
->flags
.is_align
11016 && xt_block
->flags
.is_align
)
11018 /* Nothing needed. */
11019 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
11024 if (xt_block_2
->flags
.is_align
)
11026 /* Push alignment to previous entry. */
11027 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
11028 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
11033 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
11034 &xt_block_2
->flags
))
11037 xt_block
->size
+= xt_block_2
->size
;
11039 if (xt_block_2
->flags
.is_align
)
11041 xt_block
->flags
.is_align
= TRUE
;
11042 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
11050 add_xt_prop_frags (segT sec
,
11051 xtensa_block_info
**xt_block
,
11052 frag_flags_fn property_function
)
11054 bfd_vma seg_offset
;
11057 /* Build it if needed. */
11058 while (*xt_block
!= NULL
)
11060 xt_block
= &(*xt_block
)->next
;
11062 /* We are either at NULL at the beginning or at the end. */
11064 /* Walk through the frags. */
11067 if (seg_info (sec
)->frchainP
)
11069 for (fragP
= seg_info (sec
)->frchainP
->frch_root
; fragP
;
11070 fragP
= fragP
->fr_next
)
11072 xtensa_block_info tmp_block
;
11073 tmp_block
.sec
= sec
;
11074 tmp_block
.offset
= fragP
->fr_address
;
11075 tmp_block
.size
= fragP
->fr_fix
;
11076 tmp_block
.next
= NULL
;
11077 property_function (fragP
, &tmp_block
.flags
);
11079 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
11080 /* && fragP->fr_fix != 0) */
11082 if ((*xt_block
) == NULL
11083 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
11085 xtensa_block_info
*new_block
;
11086 if ((*xt_block
) != NULL
)
11087 xt_block
= &(*xt_block
)->next
;
11088 new_block
= (xtensa_block_info
*)
11089 xmalloc (sizeof (xtensa_block_info
));
11090 *new_block
= tmp_block
;
11091 *xt_block
= new_block
;
11099 /* op_placement_info_table */
11101 /* op_placement_info makes it easier to determine which
11102 ops can go in which slots. */
11105 init_op_placement_info_table (void)
11107 xtensa_isa isa
= xtensa_default_isa
;
11108 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
11109 xtensa_opcode opcode
;
11112 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
11114 op_placement_table
= (op_placement_info_table
)
11115 xmalloc (sizeof (op_placement_info
) * num_opcodes
);
11116 gas_assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
11118 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
11120 op_placement_info
*opi
= &op_placement_table
[opcode
];
11121 /* FIXME: Make tinsn allocation dynamic. */
11122 if (xtensa_opcode_num_operands (isa
, opcode
) > MAX_INSN_ARGS
)
11123 as_fatal (_("too many operands in instruction"));
11124 opi
->narrowest
= XTENSA_UNDEFINED
;
11125 opi
->narrowest_size
= 0x7F;
11126 opi
->narrowest_slot
= 0;
11128 opi
->num_formats
= 0;
11130 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
11132 opi
->slots
[fmt
] = 0;
11133 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
11135 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
11137 int fmt_length
= xtensa_format_length (isa
, fmt
);
11139 set_bit (fmt
, opi
->formats
);
11140 set_bit (slot
, opi
->slots
[fmt
]);
11141 if (fmt_length
< opi
->narrowest_size
11142 || (fmt_length
== opi
->narrowest_size
11143 && (xtensa_format_num_slots (isa
, fmt
)
11144 < xtensa_format_num_slots (isa
,
11147 opi
->narrowest
= fmt
;
11148 opi
->narrowest_size
= fmt_length
;
11149 opi
->narrowest_slot
= slot
;
11154 opi
->num_formats
++;
11157 xtensa_insnbuf_free (isa
, ibuf
);
11162 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
11164 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
11168 /* If the opcode is available in a single slot format, return its size. */
11171 xg_get_single_size (xtensa_opcode opcode
)
11173 return op_placement_table
[opcode
].narrowest_size
;
11177 static xtensa_format
11178 xg_get_single_format (xtensa_opcode opcode
)
11180 return op_placement_table
[opcode
].narrowest
;
11185 xg_get_single_slot (xtensa_opcode opcode
)
11187 return op_placement_table
[opcode
].narrowest_slot
;
11191 /* Instruction Stack Functions (from "xtensa-istack.h"). */
11194 istack_init (IStack
*stack
)
11196 memset (stack
, 0, sizeof (IStack
));
11202 istack_empty (IStack
*stack
)
11204 return (stack
->ninsn
== 0);
11209 istack_full (IStack
*stack
)
11211 return (stack
->ninsn
== MAX_ISTACK
);
11215 /* Return a pointer to the top IStack entry.
11216 It is an error to call this if istack_empty () is TRUE. */
11219 istack_top (IStack
*stack
)
11221 int rec
= stack
->ninsn
- 1;
11222 gas_assert (!istack_empty (stack
));
11223 return &stack
->insn
[rec
];
11227 /* Add a new TInsn to an IStack.
11228 It is an error to call this if istack_full () is TRUE. */
11231 istack_push (IStack
*stack
, TInsn
*insn
)
11233 int rec
= stack
->ninsn
;
11234 gas_assert (!istack_full (stack
));
11235 stack
->insn
[rec
] = *insn
;
11240 /* Clear space for the next TInsn on the IStack and return a pointer
11241 to it. It is an error to call this if istack_full () is TRUE. */
11244 istack_push_space (IStack
*stack
)
11246 int rec
= stack
->ninsn
;
11248 gas_assert (!istack_full (stack
));
11249 insn
= &stack
->insn
[rec
];
11256 /* Remove the last pushed instruction. It is an error to call this if
11257 istack_empty () returns TRUE. */
11260 istack_pop (IStack
*stack
)
11262 int rec
= stack
->ninsn
- 1;
11263 gas_assert (!istack_empty (stack
));
11265 tinsn_init (&stack
->insn
[rec
]);
11269 /* TInsn functions. */
11272 tinsn_init (TInsn
*dst
)
11274 memset (dst
, 0, sizeof (TInsn
));
11278 /* Return TRUE if ANY of the operands in the insn are symbolic. */
11281 tinsn_has_symbolic_operands (const TInsn
*insn
)
11284 int n
= insn
->ntok
;
11286 gas_assert (insn
->insn_type
== ITYPE_INSN
);
11288 for (i
= 0; i
< n
; ++i
)
11290 switch (insn
->tok
[i
].X_op
)
11304 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
11306 xtensa_isa isa
= xtensa_default_isa
;
11308 int n
= insn
->ntok
;
11310 gas_assert (insn
->insn_type
== ITYPE_INSN
);
11312 for (i
= 0; i
< n
; ++i
)
11314 switch (insn
->tok
[i
].X_op
)
11322 /* Errors for these types are caught later. */
11327 /* Symbolic immediates are only allowed on the last immediate
11328 operand. At this time, CONST16 is the only opcode where we
11329 support non-PC-relative relocations. */
11330 if (i
!= get_relaxable_immed (insn
->opcode
)
11331 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
11332 && insn
->opcode
!= xtensa_const16_opcode
))
11334 as_bad (_("invalid symbolic operand"));
11343 /* For assembly code with complex expressions (e.g. subtraction),
11344 we have to build them in the literal pool so that
11345 their results are calculated correctly after relaxation.
11346 The relaxation only handles expressions that
11347 boil down to SYMBOL + OFFSET. */
11350 tinsn_has_complex_operands (const TInsn
*insn
)
11353 int n
= insn
->ntok
;
11354 gas_assert (insn
->insn_type
== ITYPE_INSN
);
11355 for (i
= 0; i
< n
; ++i
)
11357 switch (insn
->tok
[i
].X_op
)
11373 /* Encode a TInsn opcode and its constant operands into slotbuf.
11374 Return TRUE if there is a symbol in the immediate field. This
11375 function assumes that:
11376 1) The number of operands are correct.
11377 2) The insn_type is ITYPE_INSN.
11378 3) The opcode can be encoded in the specified format and slot.
11379 4) Operands are either O_constant or O_symbol, and all constants fit. */
11382 tinsn_to_slotbuf (xtensa_format fmt
,
11385 xtensa_insnbuf slotbuf
)
11387 xtensa_isa isa
= xtensa_default_isa
;
11388 xtensa_opcode opcode
= tinsn
->opcode
;
11389 bfd_boolean has_fixup
= FALSE
;
11390 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11393 gas_assert (tinsn
->insn_type
== ITYPE_INSN
);
11394 if (noperands
!= tinsn
->ntok
)
11395 as_fatal (_("operand number mismatch"));
11397 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
11399 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
11400 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
11404 for (i
= 0; i
< noperands
; i
++)
11406 expressionS
*expr
= &tinsn
->tok
[i
];
11412 switch (expr
->X_op
)
11415 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11417 /* The register number has already been checked in
11418 expression_maybe_register, so we don't need to check here. */
11419 opnd_value
= expr
->X_add_number
;
11420 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11421 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
11424 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
11428 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11430 as_where (&file_name
, &line
);
11431 /* It is a constant and we called this function
11432 then we have to try to fit it. */
11433 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
11434 expr
->X_add_number
, file_name
, line
);
11447 /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded
11448 into a multi-slot instruction, fill the other slots with NOPs.
11449 Return TRUE if there is a symbol in the immediate field. See also the
11450 assumptions listed for tinsn_to_slotbuf. */
11453 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
11455 static xtensa_insnbuf slotbuf
= 0;
11456 static vliw_insn vinsn
;
11457 xtensa_isa isa
= xtensa_default_isa
;
11458 bfd_boolean has_fixup
= FALSE
;
11463 slotbuf
= xtensa_insnbuf_alloc (isa
);
11464 xg_init_vinsn (&vinsn
);
11467 xg_clear_vinsn (&vinsn
);
11469 bundle_tinsn (tinsn
, &vinsn
);
11471 xtensa_format_encode (isa
, vinsn
.format
, insnbuf
);
11473 for (i
= 0; i
< vinsn
.num_slots
; i
++)
11475 /* Only one slot may have a fix-up because the rest contains NOPs. */
11477 tinsn_to_slotbuf (vinsn
.format
, i
, &vinsn
.slots
[i
], vinsn
.slotbuf
[i
]);
11478 xtensa_format_set_slot (isa
, vinsn
.format
, i
, insnbuf
, vinsn
.slotbuf
[i
]);
11485 /* Check the instruction arguments. Return TRUE on failure. */
11488 tinsn_check_arguments (const TInsn
*insn
)
11490 xtensa_isa isa
= xtensa_default_isa
;
11491 xtensa_opcode opcode
= insn
->opcode
;
11492 xtensa_regfile t1_regfile
, t2_regfile
;
11493 int t1_reg
, t2_reg
;
11494 int t1_base_reg
, t1_last_reg
;
11495 int t2_base_reg
, t2_last_reg
;
11496 char t1_inout
, t2_inout
;
11499 if (opcode
== XTENSA_UNDEFINED
)
11501 as_bad (_("invalid opcode"));
11505 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
11507 as_bad (_("too few operands"));
11511 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
11513 as_bad (_("too many operands"));
11517 /* Check registers. */
11518 for (j
= 0; j
< insn
->ntok
; j
++)
11520 if (xtensa_operand_is_register (isa
, insn
->opcode
, j
) != 1)
11523 t2_regfile
= xtensa_operand_regfile (isa
, insn
->opcode
, j
);
11524 t2_base_reg
= insn
->tok
[j
].X_add_number
;
11526 = t2_base_reg
+ xtensa_operand_num_regs (isa
, insn
->opcode
, j
);
11528 for (i
= 0; i
< insn
->ntok
; i
++)
11533 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) != 1)
11536 t1_regfile
= xtensa_operand_regfile (isa
, insn
->opcode
, i
);
11538 if (t1_regfile
!= t2_regfile
)
11541 t1_inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
11542 t2_inout
= xtensa_operand_inout (isa
, insn
->opcode
, j
);
11544 t1_base_reg
= insn
->tok
[i
].X_add_number
;
11545 t1_last_reg
= (t1_base_reg
11546 + xtensa_operand_num_regs (isa
, insn
->opcode
, i
));
11548 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
11550 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
11552 if (t1_reg
!= t2_reg
)
11555 if (t1_inout
!= 'i' && t2_inout
!= 'i')
11557 as_bad (_("multiple writes to the same register"));
11568 /* Load an instruction from its encoded form. */
11571 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
11575 xg_init_vinsn (&vinsn
);
11576 vinsn_from_chars (&vinsn
, f
);
11578 *tinsn
= vinsn
.slots
[slot
];
11579 xg_free_vinsn (&vinsn
);
11584 tinsn_from_insnbuf (TInsn
*tinsn
,
11585 xtensa_insnbuf slotbuf
,
11590 xtensa_isa isa
= xtensa_default_isa
;
11592 /* Find the immed. */
11593 tinsn_init (tinsn
);
11594 tinsn
->insn_type
= ITYPE_INSN
;
11595 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
11596 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
11597 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
11598 for (i
= 0; i
< tinsn
->ntok
; i
++)
11600 set_expr_const (&tinsn
->tok
[i
],
11601 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
11602 tinsn
->opcode
, i
));
11607 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
11610 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
11612 xtensa_opcode opcode
= tinsn
->opcode
;
11615 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
11617 opnum
= get_relaxable_immed (opcode
);
11618 gas_assert (opnum
>= 0);
11619 set_expr_symbol_offset (&tinsn
->tok
[opnum
],
11620 fragP
->tc_frag_data
.slot_symbols
[slot
],
11621 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11623 tinsn
->extra_arg
= fragP
->tc_frag_data
.free_reg
[slot
];
11628 get_num_stack_text_bytes (IStack
*istack
)
11631 int text_bytes
= 0;
11633 for (i
= 0; i
< istack
->ninsn
; i
++)
11635 TInsn
*tinsn
= &istack
->insn
[i
];
11636 if (tinsn
->insn_type
== ITYPE_INSN
)
11637 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
11644 get_num_stack_literal_bytes (IStack
*istack
)
11649 for (i
= 0; i
< istack
->ninsn
; i
++)
11651 TInsn
*tinsn
= &istack
->insn
[i
];
11652 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
11659 /* vliw_insn functions. */
11662 xg_init_vinsn (vliw_insn
*v
)
11665 xtensa_isa isa
= xtensa_default_isa
;
11667 xg_clear_vinsn (v
);
11669 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
11670 if (v
->insnbuf
== NULL
)
11671 as_fatal (_("out of memory"));
11673 for (i
= 0; i
< MAX_SLOTS
; i
++)
11675 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
11676 if (v
->slotbuf
[i
] == NULL
)
11677 as_fatal (_("out of memory"));
11683 xg_clear_vinsn (vliw_insn
*v
)
11687 memset (v
, 0, offsetof (vliw_insn
, insnbuf
));
11689 v
->format
= XTENSA_UNDEFINED
;
11691 v
->inside_bundle
= FALSE
;
11693 if (xt_saved_debug_type
!= DEBUG_NONE
)
11694 debug_type
= xt_saved_debug_type
;
11696 for (i
= 0; i
< MAX_SLOTS
; i
++)
11697 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
11702 vinsn_has_specific_opcodes (vliw_insn
*v
)
11706 for (i
= 0; i
< v
->num_slots
; i
++)
11708 if (v
->slots
[i
].is_specific_opcode
)
11716 xg_free_vinsn (vliw_insn
*v
)
11719 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
11720 for (i
= 0; i
< MAX_SLOTS
; i
++)
11721 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
11725 /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic
11726 operands. See also the assumptions listed for tinsn_to_slotbuf. */
11729 vinsn_to_insnbuf (vliw_insn
*vinsn
,
11732 bfd_boolean record_fixup
)
11734 xtensa_isa isa
= xtensa_default_isa
;
11735 xtensa_format fmt
= vinsn
->format
;
11736 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
11738 bfd_boolean has_fixup
= FALSE
;
11740 xtensa_format_encode (isa
, fmt
, insnbuf
);
11742 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
11744 TInsn
*tinsn
= &vinsn
->slots
[slot
];
11745 expressionS
*extra_arg
= &tinsn
->extra_arg
;
11746 bfd_boolean tinsn_has_fixup
=
11747 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
11748 vinsn
->slotbuf
[slot
]);
11750 xtensa_format_set_slot (isa
, fmt
, slot
,
11751 insnbuf
, vinsn
->slotbuf
[slot
]);
11752 if (extra_arg
->X_op
!= O_illegal
&& extra_arg
->X_op
!= O_register
)
11754 if (vinsn
->num_slots
!= 1)
11755 as_bad (_("TLS relocation not allowed in FLIX bundle"));
11756 else if (record_fixup
)
11757 /* Instructions that generate TLS relocations should always be
11758 relaxed in the front-end. If "record_fixup" is set, then this
11759 function is being called during back-end relaxation, so flag
11760 the unexpected behavior as an error. */
11761 as_bad (_("unexpected TLS relocation"));
11763 fix_new (fragP
, frag_offset
- fragP
->fr_literal
,
11764 xtensa_format_length (isa
, fmt
),
11765 extra_arg
->X_add_symbol
, extra_arg
->X_add_number
,
11766 FALSE
, map_operator_to_reloc (extra_arg
->X_op
, FALSE
));
11768 if (tinsn_has_fixup
)
11771 xtensa_opcode opcode
= tinsn
->opcode
;
11772 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11775 for (i
= 0; i
< noperands
; i
++)
11777 expressionS
* expr
= &tinsn
->tok
[i
];
11778 switch (expr
->X_op
)
11783 if (get_relaxable_immed (opcode
) == i
)
11785 /* Add a fix record for the instruction, except if this
11786 function is being called prior to relaxation, i.e.,
11787 if record_fixup is false, and the instruction might
11788 be relaxed later. */
11790 || tinsn
->is_specific_opcode
11791 || !xg_is_relaxable_insn (tinsn
, 0))
11793 xg_add_opcode_fix (tinsn
, i
, fmt
, slot
, expr
, fragP
,
11794 frag_offset
- fragP
->fr_literal
);
11798 if (expr
->X_op
!= O_symbol
)
11799 as_bad (_("invalid operand"));
11800 tinsn
->symbol
= expr
->X_add_symbol
;
11801 tinsn
->offset
= expr
->X_add_number
;
11805 as_bad (_("symbolic operand not allowed"));
11813 as_bad (_("expression too complex"));
11825 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
11827 static xtensa_insnbuf insnbuf
= NULL
;
11828 static xtensa_insnbuf slotbuf
= NULL
;
11831 xtensa_isa isa
= xtensa_default_isa
;
11835 insnbuf
= xtensa_insnbuf_alloc (isa
);
11836 slotbuf
= xtensa_insnbuf_alloc (isa
);
11839 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) f
, 0);
11840 fmt
= xtensa_format_decode (isa
, insnbuf
);
11841 if (fmt
== XTENSA_UNDEFINED
)
11842 as_fatal (_("cannot decode instruction format"));
11843 vinsn
->format
= fmt
;
11844 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
11846 for (i
= 0; i
< vinsn
->num_slots
; i
++)
11848 TInsn
*tinsn
= &vinsn
->slots
[i
];
11849 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
11850 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
11855 /* Expression utilities. */
11857 /* Return TRUE if the expression is an integer constant. */
11860 expr_is_const (const expressionS
*s
)
11862 return (s
->X_op
== O_constant
);
11866 /* Get the expression constant.
11867 Calling this is illegal if expr_is_const () returns TRUE. */
11870 get_expr_const (const expressionS
*s
)
11872 gas_assert (expr_is_const (s
));
11873 return s
->X_add_number
;
11877 /* Set the expression to a constant value. */
11880 set_expr_const (expressionS
*s
, offsetT val
)
11882 s
->X_op
= O_constant
;
11883 s
->X_add_number
= val
;
11884 s
->X_add_symbol
= NULL
;
11885 s
->X_op_symbol
= NULL
;
11890 expr_is_register (const expressionS
*s
)
11892 return (s
->X_op
== O_register
);
11896 /* Get the expression constant.
11897 Calling this is illegal if expr_is_const () returns TRUE. */
11900 get_expr_register (const expressionS
*s
)
11902 gas_assert (expr_is_register (s
));
11903 return s
->X_add_number
;
11907 /* Set the expression to a symbol + constant offset. */
11910 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
11912 s
->X_op
= O_symbol
;
11913 s
->X_add_symbol
= sym
;
11914 s
->X_op_symbol
= NULL
; /* unused */
11915 s
->X_add_number
= offset
;
11919 /* Return TRUE if the two expressions are equal. */
11922 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
11924 if (s1
->X_op
!= s2
->X_op
)
11926 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
11928 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
11930 if (s1
->X_add_number
!= s2
->X_add_number
)
11937 copy_expr (expressionS
*dst
, const expressionS
*src
)
11939 memcpy (dst
, src
, sizeof (expressionS
));
11943 /* Support for the "--rename-section" option. */
11945 struct rename_section_struct
11949 struct rename_section_struct
*next
;
11952 static struct rename_section_struct
*section_rename
;
11955 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
11956 entries to the section_rename list. Note: Specifying multiple
11957 renamings separated by colons is not documented and is retained only
11958 for backward compatibility. */
11961 build_section_rename (const char *arg
)
11963 struct rename_section_struct
*r
;
11964 char *this_arg
= NULL
;
11965 char *next_arg
= NULL
;
11967 for (this_arg
= xstrdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
11969 char *old_name
, *new_name
;
11973 next_arg
= strchr (this_arg
, ':');
11981 old_name
= this_arg
;
11982 new_name
= strchr (this_arg
, '=');
11984 if (*old_name
== '\0')
11986 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
11989 if (!new_name
|| new_name
[1] == '\0')
11991 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
11998 /* Check for invalid section renaming. */
11999 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
12001 if (strcmp (r
->old_name
, old_name
) == 0)
12002 as_bad (_("section %s renamed multiple times"), old_name
);
12003 if (strcmp (r
->new_name
, new_name
) == 0)
12004 as_bad (_("multiple sections remapped to output section %s"),
12009 r
= (struct rename_section_struct
*)
12010 xmalloc (sizeof (struct rename_section_struct
));
12011 r
->old_name
= xstrdup (old_name
);
12012 r
->new_name
= xstrdup (new_name
);
12013 r
->next
= section_rename
;
12014 section_rename
= r
;
12020 xtensa_section_rename (char *name
)
12022 struct rename_section_struct
*r
= section_rename
;
12024 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
12026 if (strcmp (r
->old_name
, name
) == 0)
12027 return r
->new_name
;