1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
24 #include "safe-ctype.h"
25 #include "tc-xtensa.h"
27 #include "xtensa-relax.h"
28 #include "xtensa-istack.h"
29 #include "dwarf2dbg.h"
30 #include "struc-symbol.h"
31 #include "xtensa-config.h"
33 /* Provide default values for new configuration settings. */
39 #define uint32 unsigned int
42 #define int32 signed int
47 Naming conventions (used somewhat inconsistently):
48 The xtensa_ functions are exported
49 The xg_ functions are internal
51 We also have a couple of different extensibility mechanisms.
52 1) The idiom replacement:
53 This is used when a line is first parsed to
54 replace an instruction pattern with another instruction
55 It is currently limited to replacements of instructions
56 with constant operands.
57 2) The xtensa-relax.c mechanism that has stronger instruction
58 replacement patterns. When an instruction's immediate field
59 does not fit the next instruction sequence is attempted.
60 In addition, "narrow" opcodes are supported this way. */
63 /* Define characters with special meanings to GAS. */
64 const char comment_chars
[] = "#";
65 const char line_comment_chars
[] = "#";
66 const char line_separator_chars
[] = ";";
67 const char EXP_CHARS
[] = "eE";
68 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
71 /* Flags to indicate whether the hardware supports the density and
72 absolute literals options. */
74 bfd_boolean density_supported
= XCHAL_HAVE_DENSITY
;
75 bfd_boolean absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
77 /* Maximum width we would pad an unreachable frag to get alignment. */
78 #define UNREACHABLE_MAX_WIDTH 8
80 static vliw_insn cur_vinsn
;
82 unsigned xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
84 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
86 /* Some functions are only valid in the front end. This variable
87 allows us to assert that we haven't crossed over into the
89 static bfd_boolean past_xtensa_end
= FALSE
;
91 /* Flags for properties of the last instruction in a segment. */
92 #define FLAG_IS_A0_WRITER 0x1
93 #define FLAG_IS_BAD_LOOPEND 0x2
96 /* We define a special segment names ".literal" to place literals
97 into. The .fini and .init sections are special because they
98 contain code that is moved together by the linker. We give them
99 their own special .fini.literal and .init.literal sections. */
101 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
102 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
103 #define INIT_SECTION_NAME xtensa_section_rename (".init")
104 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
107 /* This type is used for the directive_stack to keep track of the
108 state of the literal collection pools. If lit_prefix is set, it is
109 used to determine the literal section names; otherwise, the literal
110 sections are determined based on the current text section. The
111 lit_seg and lit4_seg fields cache these literal sections, with the
112 current_text_seg field used a tag to indicate whether the cached
115 typedef struct lit_state_struct
118 segT current_text_seg
;
123 static lit_state default_lit_sections
;
126 /* We keep a list of literal segments. The seg_list type is the node
127 for this list. The literal_head pointer is the head of the list,
128 with the literal_head_h dummy node at the start. */
130 typedef struct seg_list_struct
132 struct seg_list_struct
*next
;
136 static seg_list literal_head_h
;
137 static seg_list
*literal_head
= &literal_head_h
;
140 /* Lists of symbols. We keep a list of symbols that label the current
141 instruction, so that we can adjust the symbols when inserting alignment
142 for various instructions. We also keep a list of all the symbols on
143 literals, so that we can fix up those symbols when the literals are
144 later moved into the text sections. */
146 typedef struct sym_list_struct
148 struct sym_list_struct
*next
;
152 static sym_list
*insn_labels
= NULL
;
153 static sym_list
*free_insn_labels
= NULL
;
154 static sym_list
*saved_insn_labels
= NULL
;
156 static sym_list
*literal_syms
;
159 /* Flags to determine whether to prefer const16 or l32r
160 if both options are available. */
161 int prefer_const16
= 0;
164 /* Global flag to indicate when we are emitting literals. */
165 int generating_literals
= 0;
167 /* The following PROPERTY table definitions are copied from
168 <elf/xtensa.h> and must be kept in sync with the code there. */
170 /* Flags in the property tables to specify whether blocks of memory
171 are literals, instructions, data, or unreachable. For
172 instructions, blocks that begin loop targets and branch targets are
173 designated. Blocks that do not allow density, instruction
174 reordering or transformation are also specified. Finally, for
175 branch targets, branch target alignment priority is included.
176 Alignment of the next block is specified in the current block
177 and the size of the current block does not include any fill required
178 to align to the next block. */
180 #define XTENSA_PROP_LITERAL 0x00000001
181 #define XTENSA_PROP_INSN 0x00000002
182 #define XTENSA_PROP_DATA 0x00000004
183 #define XTENSA_PROP_UNREACHABLE 0x00000008
184 /* Instruction only properties at beginning of code. */
185 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
186 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
187 /* Instruction only properties about code. */
188 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
189 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
190 #define XTENSA_PROP_INSN_NO_TRANSFORM 0x00000100
192 /* Branch target alignment information. This transmits information
193 to the linker optimization about the priority of aligning a
194 particular block for branch target alignment: None, low priority,
195 high priority, or required. These only need to be checked in
196 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
199 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
200 case XTENSA_PROP_BT_ALIGN_NONE:
201 case XTENSA_PROP_BT_ALIGN_LOW:
202 case XTENSA_PROP_BT_ALIGN_HIGH:
203 case XTENSA_PROP_BT_ALIGN_REQUIRE:
205 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
207 /* No branch target alignment. */
208 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
209 /* Low priority branch target alignment. */
210 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
211 /* High priority branch target alignment. */
212 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
213 /* Required branch target alignment. */
214 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
216 #define GET_XTENSA_PROP_BT_ALIGN(flag) \
217 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
218 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
219 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
220 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
223 /* Alignment is specified in the block BEFORE the one that needs
224 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
225 get the required alignment specified as a power of 2. Use
226 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
227 alignment. Be careful of side effects since the SET will evaluate
228 flags twice. Also, note that the SIZE of a block in the property
229 table does not include the alignment size, so the alignment fill
230 must be calculated to determine if two blocks are contiguous.
231 TEXT_ALIGN is not currently implemented but is a placeholder for a
232 possible future implementation. */
234 #define XTENSA_PROP_ALIGN 0x00000800
236 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
238 #define GET_XTENSA_PROP_ALIGNMENT(flag) \
239 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
240 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
241 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
242 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
244 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
247 /* Structure for saving instruction and alignment per-fragment data
248 that will be written to the object file. This structure is
249 equivalent to the actual data that will be written out to the file
250 but is easier to use. We provide a conversion to file flags
251 in frag_flags_to_number. */
253 typedef struct frag_flags_struct frag_flags
;
255 struct frag_flags_struct
257 /* is_literal should only be used after xtensa_move_literals.
258 If you need to check if you are generating a literal fragment,
259 then use the generating_literals global. */
261 unsigned is_literal
: 1;
262 unsigned is_insn
: 1;
263 unsigned is_data
: 1;
264 unsigned is_unreachable
: 1;
268 unsigned is_loop_target
: 1;
269 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
270 unsigned bt_align_priority
: 2;
272 unsigned is_no_density
: 1;
273 /* no_longcalls flag does not need to be placed in the object file. */
274 /* is_specific_opcode implies no_transform. */
275 unsigned is_no_transform
: 1;
277 unsigned is_no_reorder
: 1;
279 /* Uses absolute literal addressing for l32r. */
280 unsigned is_abslit
: 1;
282 unsigned is_align
: 1;
283 unsigned alignment
: 5;
287 /* Structure for saving information about a block of property data
288 for frags that have the same flags. */
289 struct xtensa_block_info_struct
295 struct xtensa_block_info_struct
*next
;
299 /* Structure for saving the current state before emitting literals. */
300 typedef struct emit_state_struct
305 int generating_literals
;
309 /* Opcode placement information */
311 typedef unsigned long long bitfield
;
312 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
313 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
314 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
316 #define MAX_FORMATS 32
318 typedef struct op_placement_info_struct
321 /* A number describing how restrictive the issue is for this
322 opcode. For example, an opcode that fits lots of different
323 formats has a high freedom, as does an opcode that fits
324 only one format but many slots in that format. The most
325 restrictive is the opcode that fits only one slot in one
328 xtensa_format narrowest
;
332 /* formats is a bitfield with the Nth bit set
333 if the opcode fits in the Nth xtensa_format. */
336 /* slots[N]'s Mth bit is set if the op fits in the
337 Mth slot of the Nth xtensa_format. */
338 bitfield slots
[MAX_FORMATS
];
340 /* A count of the number of slots in a given format
341 an op can fit (i.e., the bitcount of the slot field above). */
342 char slots_in_format
[MAX_FORMATS
];
344 } op_placement_info
, *op_placement_info_table
;
346 op_placement_info_table op_placement_table
;
349 /* Extra expression types. */
351 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
352 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
353 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
366 directive_literal_prefix
,
368 directive_absolute_literals
,
369 directive_last_directive
375 bfd_boolean can_be_negated
;
378 const directive_infoS directive_info
[] =
381 { "literal", FALSE
},
383 { "transform", TRUE
},
384 { "freeregs", FALSE
},
385 { "longcalls", TRUE
},
386 { "literal_prefix", FALSE
},
387 { "schedule", TRUE
},
388 { "absolute-literals", TRUE
}
391 bfd_boolean directive_state
[] =
395 #if !XCHAL_HAVE_DENSITY
400 TRUE
, /* transform */
401 FALSE
, /* freeregs */
402 FALSE
, /* longcalls */
403 FALSE
, /* literal_prefix */
404 FALSE
, /* schedule */
405 #if XSHAL_USE_ABSOLUTE_LITERALS
406 TRUE
/* absolute_literals */
408 FALSE
/* absolute_literals */
413 /* Directive functions. */
415 static void xtensa_begin_directive (int);
416 static void xtensa_end_directive (int);
417 static void xtensa_literal_prefix (void);
418 static void xtensa_literal_position (int);
419 static void xtensa_literal_pseudo (int);
420 static void xtensa_frequency_pseudo (int);
421 static void xtensa_elf_cons (int);
423 /* Parsing and Idiom Translation. */
425 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
427 /* Various Other Internal Functions. */
429 extern bfd_boolean
xg_is_single_relaxable_insn (TInsn
*, TInsn
*, bfd_boolean
);
430 static bfd_boolean
xg_build_to_insn (TInsn
*, TInsn
*, BuildInstr
*);
431 static void xtensa_mark_literal_pool_location (void);
432 static addressT
get_expanded_loop_offset (xtensa_opcode
);
433 static fragS
*get_literal_pool_location (segT
);
434 static void set_literal_pool_location (segT
, fragS
*);
435 static void xtensa_set_frag_assembly_state (fragS
*);
436 static void finish_vinsn (vliw_insn
*);
437 static bfd_boolean
emit_single_op (TInsn
*);
438 static int total_frag_text_expansion (fragS
*);
440 /* Alignment Functions. */
442 static int get_text_align_power (unsigned);
443 static int get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
444 static int branch_align_power (segT
);
446 /* Helpers for xtensa_relax_frag(). */
448 static long relax_frag_add_nop (fragS
*);
450 /* Accessors for additional per-subsegment information. */
452 static unsigned get_last_insn_flags (segT
, subsegT
);
453 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
454 static float get_subseg_total_freq (segT
, subsegT
);
455 static float get_subseg_target_freq (segT
, subsegT
);
456 static void set_subseg_freq (segT
, subsegT
, float, float);
458 /* Segment list functions. */
460 static void xtensa_move_literals (void);
461 static void xtensa_reorder_segments (void);
462 static void xtensa_switch_to_literal_fragment (emit_state
*);
463 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
464 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
465 static void xtensa_restore_emit_state (emit_state
*);
466 static segT
cache_literal_section (bfd_boolean
);
468 /* Import from elf32-xtensa.c in BFD library. */
470 extern asection
*xtensa_get_property_section (asection
*, const char *);
472 /* op_placement_info functions. */
474 static void init_op_placement_info_table (void);
475 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
476 static int xg_get_single_size (xtensa_opcode
);
477 static xtensa_format
xg_get_single_format (xtensa_opcode
);
478 static int xg_get_single_slot (xtensa_opcode
);
480 /* TInsn and IStack functions. */
482 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
483 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
484 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
485 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
486 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
487 static void tinsn_from_chars (TInsn
*, char *, int);
488 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
489 static int get_num_stack_text_bytes (IStack
*);
490 static int get_num_stack_literal_bytes (IStack
*);
492 /* vliw_insn functions. */
494 static void xg_init_vinsn (vliw_insn
*);
495 static void xg_clear_vinsn (vliw_insn
*);
496 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
497 static void xg_free_vinsn (vliw_insn
*);
498 static bfd_boolean vinsn_to_insnbuf
499 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
500 static void vinsn_from_chars (vliw_insn
*, char *);
502 /* Expression Utilities. */
504 bfd_boolean
expr_is_const (const expressionS
*);
505 offsetT
get_expr_const (const expressionS
*);
506 void set_expr_const (expressionS
*, offsetT
);
507 bfd_boolean
expr_is_register (const expressionS
*);
508 offsetT
get_expr_register (const expressionS
*);
509 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
510 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
511 static void copy_expr (expressionS
*, const expressionS
*);
513 /* Section renaming. */
515 static void build_section_rename (const char *);
518 /* ISA imported from bfd. */
519 extern xtensa_isa xtensa_default_isa
;
521 extern int target_big_endian
;
523 static xtensa_opcode xtensa_addi_opcode
;
524 static xtensa_opcode xtensa_addmi_opcode
;
525 static xtensa_opcode xtensa_call0_opcode
;
526 static xtensa_opcode xtensa_call4_opcode
;
527 static xtensa_opcode xtensa_call8_opcode
;
528 static xtensa_opcode xtensa_call12_opcode
;
529 static xtensa_opcode xtensa_callx0_opcode
;
530 static xtensa_opcode xtensa_callx4_opcode
;
531 static xtensa_opcode xtensa_callx8_opcode
;
532 static xtensa_opcode xtensa_callx12_opcode
;
533 static xtensa_opcode xtensa_const16_opcode
;
534 static xtensa_opcode xtensa_entry_opcode
;
535 static xtensa_opcode xtensa_movi_opcode
;
536 static xtensa_opcode xtensa_movi_n_opcode
;
537 static xtensa_opcode xtensa_isync_opcode
;
538 static xtensa_opcode xtensa_jx_opcode
;
539 static xtensa_opcode xtensa_l32r_opcode
;
540 static xtensa_opcode xtensa_loop_opcode
;
541 static xtensa_opcode xtensa_loopnez_opcode
;
542 static xtensa_opcode xtensa_loopgtz_opcode
;
543 static xtensa_opcode xtensa_nop_opcode
;
544 static xtensa_opcode xtensa_nop_n_opcode
;
545 static xtensa_opcode xtensa_or_opcode
;
546 static xtensa_opcode xtensa_ret_opcode
;
547 static xtensa_opcode xtensa_ret_n_opcode
;
548 static xtensa_opcode xtensa_retw_opcode
;
549 static xtensa_opcode xtensa_retw_n_opcode
;
550 static xtensa_opcode xtensa_rsr_lcount_opcode
;
551 static xtensa_opcode xtensa_waiti_opcode
;
554 /* Command-line Options. */
556 bfd_boolean use_literal_section
= TRUE
;
557 static bfd_boolean align_targets
= TRUE
;
558 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
559 static bfd_boolean has_a0_b_retw
= FALSE
;
560 static bfd_boolean workaround_a0_b_retw
= FALSE
;
561 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
562 static bfd_boolean workaround_short_loop
= FALSE
;
563 static bfd_boolean maybe_has_short_loop
= FALSE
;
564 static bfd_boolean workaround_close_loop_end
= FALSE
;
565 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
566 static bfd_boolean enforce_three_byte_loop_align
= FALSE
;
568 /* When workaround_short_loops is TRUE, all loops with early exits must
569 have at least 3 instructions. workaround_all_short_loops is a modifier
570 to the workaround_short_loop flag. In addition to the
571 workaround_short_loop actions, all straightline loopgtz and loopnez
572 must have at least 3 instructions. */
574 static bfd_boolean workaround_all_short_loops
= FALSE
;
578 xtensa_setup_hw_workarounds (int earliest
, int latest
)
580 if (earliest
> latest
)
581 as_fatal (_("illegal range of target hardware versions"));
583 /* Enable all workarounds for pre-T1050.0 hardware. */
584 if (earliest
< 105000 || latest
< 105000)
586 workaround_a0_b_retw
|= TRUE
;
587 workaround_b_j_loop_end
|= TRUE
;
588 workaround_short_loop
|= TRUE
;
589 workaround_close_loop_end
|= TRUE
;
590 workaround_all_short_loops
|= TRUE
;
591 enforce_three_byte_loop_align
= TRUE
;
598 option_density
= OPTION_MD_BASE
,
605 option_no_link_relax
,
613 option_text_section_literals
,
614 option_no_text_section_literals
,
616 option_absolute_literals
,
617 option_no_absolute_literals
,
619 option_align_targets
,
620 option_no_align_targets
,
622 option_warn_unaligned_targets
,
627 option_workaround_a0_b_retw
,
628 option_no_workaround_a0_b_retw
,
630 option_workaround_b_j_loop_end
,
631 option_no_workaround_b_j_loop_end
,
633 option_workaround_short_loop
,
634 option_no_workaround_short_loop
,
636 option_workaround_all_short_loops
,
637 option_no_workaround_all_short_loops
,
639 option_workaround_close_loop_end
,
640 option_no_workaround_close_loop_end
,
642 option_no_workarounds
,
644 option_rename_section_name
,
647 option_prefer_const16
,
649 option_target_hardware
652 const char *md_shortopts
= "";
654 struct option md_longopts
[] =
656 { "density", no_argument
, NULL
, option_density
},
657 { "no-density", no_argument
, NULL
, option_no_density
},
659 /* Both "relax" and "generics" are deprecated and treated as equivalent
660 to the "transform" option. */
661 { "relax", no_argument
, NULL
, option_relax
},
662 { "no-relax", no_argument
, NULL
, option_no_relax
},
663 { "generics", no_argument
, NULL
, option_generics
},
664 { "no-generics", no_argument
, NULL
, option_no_generics
},
666 { "transform", no_argument
, NULL
, option_transform
},
667 { "no-transform", no_argument
, NULL
, option_no_transform
},
668 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
669 { "no-text-section-literals", no_argument
, NULL
,
670 option_no_text_section_literals
},
671 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
672 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
673 /* This option was changed from -align-target to -target-align
674 because it conflicted with the "-al" option. */
675 { "target-align", no_argument
, NULL
, option_align_targets
},
676 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
677 { "warn-unaligned-targets", no_argument
, NULL
,
678 option_warn_unaligned_targets
},
679 { "longcalls", no_argument
, NULL
, option_longcalls
},
680 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
682 { "no-workaround-a0-b-retw", no_argument
, NULL
,
683 option_no_workaround_a0_b_retw
},
684 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
686 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
687 option_no_workaround_b_j_loop_end
},
688 { "workaround-b-j-loop-end", no_argument
, NULL
,
689 option_workaround_b_j_loop_end
},
691 { "no-workaround-short-loops", no_argument
, NULL
,
692 option_no_workaround_short_loop
},
693 { "workaround-short-loops", no_argument
, NULL
,
694 option_workaround_short_loop
},
696 { "no-workaround-all-short-loops", no_argument
, NULL
,
697 option_no_workaround_all_short_loops
},
698 { "workaround-all-short-loop", no_argument
, NULL
,
699 option_workaround_all_short_loops
},
701 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
702 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
704 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
706 { "no-workaround-close-loop-end", no_argument
, NULL
,
707 option_no_workaround_close_loop_end
},
708 { "workaround-close-loop-end", no_argument
, NULL
,
709 option_workaround_close_loop_end
},
711 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
713 { "link-relax", no_argument
, NULL
, option_link_relax
},
714 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
716 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
718 { NULL
, no_argument
, NULL
, 0 }
721 size_t md_longopts_size
= sizeof md_longopts
;
725 md_parse_option (int c
, char *arg
)
730 as_warn (_("--density option is ignored"));
732 case option_no_density
:
733 as_warn (_("--no-density option is ignored"));
735 case option_link_relax
:
738 case option_no_link_relax
:
741 case option_generics
:
742 as_warn (_("--generics is deprecated; use --transform instead"));
743 return md_parse_option (option_transform
, arg
);
744 case option_no_generics
:
745 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
746 return md_parse_option (option_no_transform
, arg
);
748 as_warn (_("--relax is deprecated; use --transform instead"));
749 return md_parse_option (option_transform
, arg
);
750 case option_no_relax
:
751 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
752 return md_parse_option (option_no_transform
, arg
);
753 case option_longcalls
:
754 directive_state
[directive_longcalls
] = TRUE
;
756 case option_no_longcalls
:
757 directive_state
[directive_longcalls
] = FALSE
;
759 case option_text_section_literals
:
760 use_literal_section
= FALSE
;
762 case option_no_text_section_literals
:
763 use_literal_section
= TRUE
;
765 case option_absolute_literals
:
766 if (!absolute_literals_supported
)
768 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
771 directive_state
[directive_absolute_literals
] = TRUE
;
773 case option_no_absolute_literals
:
774 directive_state
[directive_absolute_literals
] = FALSE
;
777 case option_workaround_a0_b_retw
:
778 workaround_a0_b_retw
= TRUE
;
780 case option_no_workaround_a0_b_retw
:
781 workaround_a0_b_retw
= FALSE
;
783 case option_workaround_b_j_loop_end
:
784 workaround_b_j_loop_end
= TRUE
;
786 case option_no_workaround_b_j_loop_end
:
787 workaround_b_j_loop_end
= FALSE
;
790 case option_workaround_short_loop
:
791 workaround_short_loop
= TRUE
;
793 case option_no_workaround_short_loop
:
794 workaround_short_loop
= FALSE
;
797 case option_workaround_all_short_loops
:
798 workaround_all_short_loops
= TRUE
;
800 case option_no_workaround_all_short_loops
:
801 workaround_all_short_loops
= FALSE
;
804 case option_workaround_close_loop_end
:
805 workaround_close_loop_end
= TRUE
;
807 case option_no_workaround_close_loop_end
:
808 workaround_close_loop_end
= FALSE
;
811 case option_no_workarounds
:
812 workaround_a0_b_retw
= FALSE
;
813 workaround_b_j_loop_end
= FALSE
;
814 workaround_short_loop
= FALSE
;
815 workaround_all_short_loops
= FALSE
;
816 workaround_close_loop_end
= FALSE
;
819 case option_align_targets
:
820 align_targets
= TRUE
;
822 case option_no_align_targets
:
823 align_targets
= FALSE
;
826 case option_warn_unaligned_targets
:
827 warn_unaligned_branch_targets
= TRUE
;
830 case option_rename_section_name
:
831 build_section_rename (arg
);
835 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
836 should be emitted or not. FIXME: Not implemented. */
839 case option_prefer_l32r
:
841 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
845 case option_prefer_const16
:
847 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
851 case option_target_hardware
:
853 int earliest
, latest
= 0;
854 if (*arg
== 0 || *arg
== '-')
855 as_fatal (_("invalid target hardware version"));
857 earliest
= strtol (arg
, &arg
, 0);
861 else if (*arg
== '-')
864 as_fatal (_("invalid target hardware version"));
865 latest
= strtol (arg
, &arg
, 0);
868 as_fatal (_("invalid target hardware version"));
870 xtensa_setup_hw_workarounds (earliest
, latest
);
874 case option_transform
:
875 /* This option has no affect other than to use the defaults,
876 which are already set. */
879 case option_no_transform
:
880 /* This option turns off all transformations of any kind.
881 However, because we want to preserve the state of other
882 directives, we only change its own field. Thus, before
883 you perform any transformation, always check if transform
884 is available. If you use the functions we provide for this
885 purpose, you will be ok. */
886 directive_state
[directive_transform
] = FALSE
;
896 md_show_usage (FILE *stream
)
900 --[no-]text-section-literals\n\
901 [Do not] put literals in the text section\n\
902 --[no-]absolute-literals\n\
903 [Do not] default to use non-PC-relative literals\n\
904 --[no-]target-align [Do not] try to align branch targets\n\
905 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
906 --[no-]transform [Do not] transform instructions\n\
907 --rename-section old=new Rename section 'old' to 'new'\n", stream
);
911 /* Functions related to the list of current label symbols. */
914 xtensa_add_insn_label (symbolS
*sym
)
918 if (!free_insn_labels
)
919 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
922 l
= free_insn_labels
;
923 free_insn_labels
= l
->next
;
927 l
->next
= insn_labels
;
933 xtensa_clear_insn_labels (void)
937 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
944 /* The "loops_ok" argument is provided to allow ignoring labels that
945 define loop ends. This fixes a bug where the NOPs to align a
946 loop opcode were included in a previous zero-cost loop:
965 This argument is used to prevent moving the NOP to before the
966 loop-end label, which is what you want in this special case. */
969 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
, bfd_boolean loops_ok
)
973 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
975 symbolS
*lit_sym
= lit
->sym
;
976 if (loops_ok
|| ! symbol_get_tc (lit_sym
)->is_loop_target
)
978 S_SET_VALUE (lit_sym
, new_offset
);
979 symbol_set_frag (lit_sym
, new_frag
);
985 /* Directive data and functions. */
987 typedef struct state_stackS_struct
989 directiveE directive
;
991 bfd_boolean old_state
;
995 struct state_stackS_struct
*prev
;
998 state_stackS
*directive_state_stack
;
1000 const pseudo_typeS md_pseudo_table
[] =
1002 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
1003 { "literal_position", xtensa_literal_position
, 0 },
1004 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
1005 { "long", xtensa_elf_cons
, 4 },
1006 { "word", xtensa_elf_cons
, 4 },
1007 { "short", xtensa_elf_cons
, 2 },
1008 { "begin", xtensa_begin_directive
, 0 },
1009 { "end", xtensa_end_directive
, 0 },
1010 { "literal", xtensa_literal_pseudo
, 0 },
1011 { "frequency", xtensa_frequency_pseudo
, 0 },
1017 use_transform (void)
1019 /* After md_end, you should be checking frag by frag, rather
1020 than state directives. */
1021 assert (!past_xtensa_end
);
1022 return directive_state
[directive_transform
];
1027 do_align_targets (void)
1029 /* Do not use this function after md_end; just look at align_targets
1030 instead. There is no target-align directive, so alignment is either
1031 enabled for all frags or not done at all. */
1032 assert (!past_xtensa_end
);
1033 return align_targets
&& use_transform ();
1038 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1042 state_stackS
*stack
= (state_stackS
*) xmalloc (sizeof (state_stackS
));
1044 as_where (&file
, &line
);
1046 stack
->directive
= directive
;
1047 stack
->negated
= negated
;
1048 stack
->old_state
= directive_state
[directive
];
1051 stack
->datum
= datum
;
1052 stack
->prev
= directive_state_stack
;
1053 directive_state_stack
= stack
;
1055 directive_state
[directive
] = !negated
;
1060 directive_pop (directiveE
*directive
,
1061 bfd_boolean
*negated
,
1066 state_stackS
*top
= directive_state_stack
;
1068 if (!directive_state_stack
)
1070 as_bad (_("unmatched end directive"));
1071 *directive
= directive_none
;
1075 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1076 *directive
= top
->directive
;
1077 *negated
= top
->negated
;
1080 *datum
= top
->datum
;
1081 directive_state_stack
= top
->prev
;
1087 directive_balance (void)
1089 while (directive_state_stack
)
1091 directiveE directive
;
1092 bfd_boolean negated
;
1097 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1098 as_warn_where ((char *) file
, line
,
1099 _(".begin directive with no matching .end directive"));
1105 inside_directive (directiveE dir
)
1107 state_stackS
*top
= directive_state_stack
;
1109 while (top
&& top
->directive
!= dir
)
1112 return (top
!= NULL
);
1117 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1121 char *directive_string
;
1123 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1128 input_line_pointer
+= 3;
1131 len
= strspn (input_line_pointer
,
1132 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1134 /* This code is a hack to make .begin [no-][generics|relax] exactly
1135 equivalent to .begin [no-]transform. We should remove it when
1136 we stop accepting those options. */
1138 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1140 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1141 directive_string
= "transform";
1143 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1145 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1146 directive_string
= "transform";
1149 directive_string
= input_line_pointer
;
1151 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1153 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1155 input_line_pointer
+= len
;
1156 *directive
= (directiveE
) i
;
1157 if (*negated
&& !directive_info
[i
].can_be_negated
)
1158 as_bad (_("directive %s cannot be negated"),
1159 directive_info
[i
].name
);
1164 as_bad (_("unknown directive"));
1165 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1170 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1172 directiveE directive
;
1173 bfd_boolean negated
;
1177 get_directive (&directive
, &negated
);
1178 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1180 discard_rest_of_line ();
1184 if (cur_vinsn
.inside_bundle
)
1185 as_bad (_("directives are not valid inside bundles"));
1189 case directive_literal
:
1190 if (!inside_directive (directive_literal
))
1192 /* Previous labels go with whatever follows this directive, not with
1193 the literal, so save them now. */
1194 saved_insn_labels
= insn_labels
;
1197 as_warn (_(".begin literal is deprecated; use .literal instead"));
1198 state
= (emit_state
*) xmalloc (sizeof (emit_state
));
1199 xtensa_switch_to_literal_fragment (state
);
1200 directive_push (directive_literal
, negated
, state
);
1203 case directive_literal_prefix
:
1204 /* Have to flush pending output because a movi relaxed to an l32r
1205 might produce a literal. */
1206 md_flush_pending_output ();
1207 /* Check to see if the current fragment is a literal
1208 fragment. If it is, then this operation is not allowed. */
1209 if (generating_literals
)
1211 as_bad (_("cannot set literal_prefix inside literal fragment"));
1215 /* Allocate the literal state for this section and push
1216 onto the directive stack. */
1217 ls
= xmalloc (sizeof (lit_state
));
1220 *ls
= default_lit_sections
;
1221 directive_push (directive_literal_prefix
, negated
, ls
);
1223 /* Process the new prefix. */
1224 xtensa_literal_prefix ();
1227 case directive_freeregs
:
1228 /* This information is currently unused, but we'll accept the statement
1229 and just discard the rest of the line. This won't check the syntax,
1230 but it will accept every correct freeregs directive. */
1231 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1232 directive_push (directive_freeregs
, negated
, 0);
1235 case directive_schedule
:
1236 md_flush_pending_output ();
1237 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1238 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1239 directive_push (directive_schedule
, negated
, 0);
1240 xtensa_set_frag_assembly_state (frag_now
);
1243 case directive_density
:
1244 as_warn (_(".begin [no-]density is ignored"));
1247 case directive_absolute_literals
:
1248 md_flush_pending_output ();
1249 if (!absolute_literals_supported
&& !negated
)
1251 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1254 xtensa_set_frag_assembly_state (frag_now
);
1255 directive_push (directive
, negated
, 0);
1259 md_flush_pending_output ();
1260 xtensa_set_frag_assembly_state (frag_now
);
1261 directive_push (directive
, negated
, 0);
1265 demand_empty_rest_of_line ();
1270 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1272 directiveE begin_directive
, end_directive
;
1273 bfd_boolean begin_negated
, end_negated
;
1277 emit_state
**state_ptr
;
1280 if (cur_vinsn
.inside_bundle
)
1281 as_bad (_("directives are not valid inside bundles"));
1283 get_directive (&end_directive
, &end_negated
);
1285 md_flush_pending_output ();
1287 switch (end_directive
)
1289 case (directiveE
) XTENSA_UNDEFINED
:
1290 discard_rest_of_line ();
1293 case directive_density
:
1294 as_warn (_(".end [no-]density is ignored"));
1295 demand_empty_rest_of_line ();
1298 case directive_absolute_literals
:
1299 if (!absolute_literals_supported
&& !end_negated
)
1301 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1302 demand_empty_rest_of_line ();
1311 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1312 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1313 (const void **) state_ptr
);
1315 if (begin_directive
!= directive_none
)
1317 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1319 as_bad (_("does not match begin %s%s at %s:%d"),
1320 begin_negated
? "no-" : "",
1321 directive_info
[begin_directive
].name
, file
, line
);
1325 switch (end_directive
)
1327 case directive_literal
:
1328 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1329 xtensa_restore_emit_state (state
);
1330 xtensa_set_frag_assembly_state (frag_now
);
1332 if (!inside_directive (directive_literal
))
1334 /* Restore the list of current labels. */
1335 xtensa_clear_insn_labels ();
1336 insn_labels
= saved_insn_labels
;
1340 case directive_literal_prefix
:
1341 /* Restore the default collection sections from saved state. */
1342 s
= (lit_state
*) state
;
1344 default_lit_sections
= *s
;
1346 /* Free the state storage. */
1347 free (s
->lit_prefix
);
1351 case directive_schedule
:
1352 case directive_freeregs
:
1356 xtensa_set_frag_assembly_state (frag_now
);
1362 demand_empty_rest_of_line ();
1366 /* Place an aligned literal fragment at the current location. */
1369 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1371 md_flush_pending_output ();
1373 if (inside_directive (directive_literal
))
1374 as_warn (_(".literal_position inside literal directive; ignoring"));
1375 xtensa_mark_literal_pool_location ();
1377 demand_empty_rest_of_line ();
1378 xtensa_clear_insn_labels ();
1382 /* Support .literal label, expr, ... */
1385 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1388 char *p
, *base_name
;
1392 if (inside_directive (directive_literal
))
1394 as_bad (_(".literal not allowed inside .begin literal region"));
1395 ignore_rest_of_line ();
1399 md_flush_pending_output ();
1401 /* Previous labels go with whatever follows this directive, not with
1402 the literal, so save them now. */
1403 saved_insn_labels
= insn_labels
;
1406 /* If we are using text-section literals, then this is the right value... */
1409 base_name
= input_line_pointer
;
1411 xtensa_switch_to_literal_fragment (&state
);
1413 /* ...but if we aren't using text-section-literals, then we
1414 need to put them in the section we just switched to. */
1415 if (use_literal_section
|| directive_state
[directive_absolute_literals
])
1418 /* All literals are aligned to four-byte boundaries. */
1419 frag_align (2, 0, 0);
1420 record_alignment (now_seg
, 2);
1422 c
= get_symbol_end ();
1423 /* Just after name is now '\0'. */
1424 p
= input_line_pointer
;
1428 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1430 as_bad (_("expected comma or colon after symbol name; "
1431 "rest of line ignored"));
1432 ignore_rest_of_line ();
1433 xtensa_restore_emit_state (&state
);
1441 input_line_pointer
++; /* skip ',' or ':' */
1443 xtensa_elf_cons (4);
1445 xtensa_restore_emit_state (&state
);
1447 /* Restore the list of current labels. */
1448 xtensa_clear_insn_labels ();
1449 insn_labels
= saved_insn_labels
;
1454 xtensa_literal_prefix (void)
1459 /* Parse the new prefix from the input_line_pointer. */
1461 len
= strspn (input_line_pointer
,
1462 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1463 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1465 /* Get a null-terminated copy of the name. */
1466 name
= xmalloc (len
+ 1);
1468 strncpy (name
, input_line_pointer
, len
);
1471 /* Skip the name in the input line. */
1472 input_line_pointer
+= len
;
1474 default_lit_sections
.lit_prefix
= name
;
1476 /* Clear cached literal sections, since the prefix has changed. */
1477 default_lit_sections
.lit_seg
= NULL
;
1478 default_lit_sections
.lit4_seg
= NULL
;
1482 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1485 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1487 float fall_through_f
, target_f
;
1489 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1490 if (fall_through_f
< 0)
1492 as_bad (_("fall through frequency must be greater than 0"));
1493 ignore_rest_of_line ();
1497 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1500 as_bad (_("branch target frequency must be greater than 0"));
1501 ignore_rest_of_line ();
1505 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1507 demand_empty_rest_of_line ();
1511 /* Like normal .long/.short/.word, except support @plt, etc.
1512 Clobbers input_line_pointer, checks end-of-line. */
1515 xtensa_elf_cons (int nbytes
)
1518 bfd_reloc_code_real_type reloc
;
1520 md_flush_pending_output ();
1522 if (cur_vinsn
.inside_bundle
)
1523 as_bad (_("directives are not valid inside bundles"));
1525 if (is_it_end_of_statement ())
1527 demand_empty_rest_of_line ();
1534 if (exp
.X_op
== O_symbol
1535 && *input_line_pointer
== '@'
1536 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1539 reloc_howto_type
*reloc_howto
=
1540 bfd_reloc_type_lookup (stdoutput
, reloc
);
1542 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1543 as_bad (_("unsupported relocation"));
1544 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1545 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1546 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1547 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1548 as_bad (_("opcode-specific %s relocation used outside "
1549 "an instruction"), reloc_howto
->name
);
1550 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1551 as_bad (_("%s relocations do not fit in %d bytes"),
1552 reloc_howto
->name
, nbytes
);
1555 char *p
= frag_more ((int) nbytes
);
1556 xtensa_set_frag_assembly_state (frag_now
);
1557 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1558 nbytes
, &exp
, 0, reloc
);
1562 emit_expr (&exp
, (unsigned int) nbytes
);
1564 while (*input_line_pointer
++ == ',');
1566 input_line_pointer
--; /* Put terminator back into stream. */
1567 demand_empty_rest_of_line ();
1571 /* Parsing and Idiom Translation. */
1573 /* Parse @plt, etc. and return the desired relocation. */
1574 static bfd_reloc_code_real_type
1575 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1581 bfd_reloc_code_real_type reloc
;
1589 struct map_bfd
*ptr
;
1591 #define MAP(str,reloc) { str, sizeof (str) - 1, reloc }
1593 static struct map_bfd mapping
[] =
1595 MAP ("l", BFD_RELOC_LO16
),
1596 MAP ("h", BFD_RELOC_HI16
),
1597 MAP ("plt", BFD_RELOC_XTENSA_PLT
),
1598 { (char *) 0, 0, BFD_RELOC_UNUSED
}
1602 return BFD_RELOC_NONE
;
1604 for (ch
= *str
, str2
= ident
;
1605 (str2
< ident
+ sizeof (ident
) - 1
1606 && (ISALNUM (ch
) || ch
== '@'));
1609 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1616 for (ptr
= &mapping
[0]; ptr
->length
> 0; ptr
++)
1617 if (ch
== ptr
->string
[0]
1618 && len
== ptr
->length
1619 && memcmp (ident
, ptr
->string
, ptr
->length
) == 0)
1621 /* Now check for "identifier@suffix+constant". */
1622 if (*str
== '-' || *str
== '+')
1624 char *orig_line
= input_line_pointer
;
1625 expressionS new_exp
;
1627 input_line_pointer
= str
;
1628 expression (&new_exp
);
1629 if (new_exp
.X_op
== O_constant
)
1631 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1632 str
= input_line_pointer
;
1635 if (&input_line_pointer
!= str_p
)
1636 input_line_pointer
= orig_line
;
1643 return BFD_RELOC_UNUSED
;
1648 expression_end (const char *name
)
1671 #define ERROR_REG_NUM ((unsigned) -1)
1674 tc_get_register (const char *prefix
)
1677 const char *next_expr
;
1678 const char *old_line_pointer
;
1681 old_line_pointer
= input_line_pointer
;
1683 if (*input_line_pointer
== '$')
1684 ++input_line_pointer
;
1686 /* Accept "sp" as a synonym for "a1". */
1687 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1688 && expression_end (input_line_pointer
+ 2))
1690 input_line_pointer
+= 2;
1691 return 1; /* AR[1] */
1694 while (*input_line_pointer
++ == *prefix
++)
1696 --input_line_pointer
;
1701 as_bad (_("bad register name: %s"), old_line_pointer
);
1702 return ERROR_REG_NUM
;
1705 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1707 as_bad (_("bad register number: %s"), input_line_pointer
);
1708 return ERROR_REG_NUM
;
1713 while (ISDIGIT ((int) *input_line_pointer
))
1714 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1716 if (!(next_expr
= expression_end (input_line_pointer
)))
1718 as_bad (_("bad register name: %s"), old_line_pointer
);
1719 return ERROR_REG_NUM
;
1722 input_line_pointer
= (char *) next_expr
;
1729 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1731 xtensa_isa isa
= xtensa_default_isa
;
1733 /* Check if this is an immediate operand. */
1734 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1736 bfd_reloc_code_real_type reloc
;
1737 segT t
= expression (tok
);
1738 if (t
== absolute_section
1739 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1741 assert (tok
->X_op
== O_constant
);
1742 tok
->X_op
= O_symbol
;
1743 tok
->X_add_symbol
= &abs_symbol
;
1746 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1747 && (reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1748 && (reloc
!= BFD_RELOC_NONE
))
1753 case BFD_RELOC_UNUSED
:
1754 as_bad (_("unsupported relocation"));
1757 case BFD_RELOC_XTENSA_PLT
:
1758 tok
->X_op
= O_pltrel
;
1761 case BFD_RELOC_LO16
:
1762 if (tok
->X_op
== O_constant
)
1763 tok
->X_add_number
&= 0xffff;
1768 case BFD_RELOC_HI16
:
1769 if (tok
->X_op
== O_constant
)
1770 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1779 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1780 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1782 if (reg
!= ERROR_REG_NUM
) /* Already errored */
1785 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
1786 as_bad (_("register number out of range"));
1789 tok
->X_op
= O_register
;
1790 tok
->X_add_symbol
= 0;
1791 tok
->X_add_number
= reg
;
1796 /* Split up the arguments for an opcode or pseudo-op. */
1799 tokenize_arguments (char **args
, char *str
)
1801 char *old_input_line_pointer
;
1802 bfd_boolean saw_comma
= FALSE
;
1803 bfd_boolean saw_arg
= FALSE
;
1804 bfd_boolean saw_colon
= FALSE
;
1806 char *arg_end
, *arg
;
1809 /* Save and restore input_line_pointer around this function. */
1810 old_input_line_pointer
= input_line_pointer
;
1811 input_line_pointer
= str
;
1813 while (*input_line_pointer
)
1816 switch (*input_line_pointer
)
1823 input_line_pointer
++;
1824 if (saw_comma
|| saw_colon
|| !saw_arg
)
1830 input_line_pointer
++;
1831 if (saw_comma
|| saw_colon
|| !saw_arg
)
1837 if (!saw_comma
&& !saw_colon
&& saw_arg
)
1840 arg_end
= input_line_pointer
+ 1;
1841 while (!expression_end (arg_end
))
1844 arg_len
= arg_end
- input_line_pointer
;
1845 arg
= (char *) xmalloc ((saw_colon
? 1 : 0) + arg_len
+ 1);
1846 args
[num_args
] = arg
;
1850 strncpy (arg
, input_line_pointer
, arg_len
);
1851 arg
[arg_len
] = '\0';
1853 input_line_pointer
= arg_end
;
1863 if (saw_comma
|| saw_colon
)
1865 input_line_pointer
= old_input_line_pointer
;
1870 as_bad (_("extra comma"));
1872 as_bad (_("extra colon"));
1874 as_bad (_("missing argument"));
1876 as_bad (_("missing comma or colon"));
1877 input_line_pointer
= old_input_line_pointer
;
1882 /* Parse the arguments to an opcode. Return TRUE on error. */
1885 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
1887 expressionS
*tok
, *last_tok
;
1888 xtensa_opcode opcode
= insn
->opcode
;
1889 bfd_boolean had_error
= TRUE
;
1890 xtensa_isa isa
= xtensa_default_isa
;
1891 int n
, num_regs
= 0;
1892 int opcode_operand_count
;
1893 int opnd_cnt
, last_opnd_cnt
;
1894 unsigned int next_reg
= 0;
1895 char *old_input_line_pointer
;
1897 if (insn
->insn_type
== ITYPE_LITERAL
)
1898 opcode_operand_count
= 1;
1900 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
1903 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
1905 /* Save and restore input_line_pointer around this function. */
1906 old_input_line_pointer
= input_line_pointer
;
1912 /* Skip invisible operands. */
1913 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
1919 for (n
= 0; n
< num_args
; n
++)
1921 input_line_pointer
= arg_strings
[n
];
1922 if (*input_line_pointer
== ':')
1924 xtensa_regfile opnd_rf
;
1925 input_line_pointer
++;
1928 assert (opnd_cnt
> 0);
1930 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
1932 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
1933 as_warn (_("incorrect register number, ignoring"));
1938 if (opnd_cnt
>= opcode_operand_count
)
1940 as_warn (_("too many arguments"));
1943 assert (opnd_cnt
< MAX_INSN_ARGS
);
1945 expression_maybe_register (opcode
, opnd_cnt
, tok
);
1946 next_reg
= tok
->X_add_number
+ 1;
1948 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
1950 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
1952 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
1953 /* minus 1 because we are seeing one right now */
1959 last_opnd_cnt
= opnd_cnt
;
1966 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
1970 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
1973 insn
->ntok
= tok
- insn
->tok
;
1977 input_line_pointer
= old_input_line_pointer
;
1983 get_invisible_operands (TInsn
*insn
)
1985 xtensa_isa isa
= xtensa_default_isa
;
1986 static xtensa_insnbuf slotbuf
= NULL
;
1988 xtensa_opcode opc
= insn
->opcode
;
1989 int slot
, opnd
, fmt_found
;
1993 slotbuf
= xtensa_insnbuf_alloc (isa
);
1995 /* Find format/slot where this can be encoded. */
1998 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2000 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2002 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2008 if (fmt_found
) break;
2013 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2017 /* First encode all the visible operands
2018 (to deal with shared field operands). */
2019 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2021 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2022 && (insn
->tok
[opnd
].X_op
== O_register
2023 || insn
->tok
[opnd
].X_op
== O_constant
))
2025 val
= insn
->tok
[opnd
].X_add_number
;
2026 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2027 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2031 /* Then pull out the values for the invisible ones. */
2032 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2034 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2036 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2037 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2038 insn
->tok
[opnd
].X_add_number
= val
;
2039 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2040 insn
->tok
[opnd
].X_op
= O_register
;
2042 insn
->tok
[opnd
].X_op
= O_constant
;
2051 xg_reverse_shift_count (char **cnt_argp
)
2053 char *cnt_arg
, *new_arg
;
2054 cnt_arg
= *cnt_argp
;
2056 /* replace the argument with "31-(argument)" */
2057 new_arg
= (char *) xmalloc (strlen (cnt_arg
) + 6);
2058 sprintf (new_arg
, "31-(%s)", cnt_arg
);
2061 *cnt_argp
= new_arg
;
2065 /* If "arg" is a constant expression, return non-zero with the value
2069 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2072 char *save_ptr
= input_line_pointer
;
2074 input_line_pointer
= arg
;
2076 input_line_pointer
= save_ptr
;
2078 if (exp
.X_op
== O_constant
)
2080 *valp
= exp
.X_add_number
;
2089 xg_replace_opname (char **popname
, char *newop
)
2092 *popname
= (char *) xmalloc (strlen (newop
) + 1);
2093 strcpy (*popname
, newop
);
2098 xg_check_num_args (int *pnum_args
,
2103 int num_args
= *pnum_args
;
2105 if (num_args
< expected_num
)
2107 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2108 num_args
, opname
, expected_num
);
2112 if (num_args
> expected_num
)
2114 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2115 num_args
, opname
, expected_num
);
2116 while (num_args
-- > expected_num
)
2118 free (arg_strings
[num_args
]);
2119 arg_strings
[num_args
] = 0;
2121 *pnum_args
= expected_num
;
2129 /* If the register is not specified as part of the opcode,
2130 then get it from the operand and move it to the opcode. */
2133 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2135 xtensa_isa isa
= xtensa_default_isa
;
2137 char *opname
, *new_opname
;
2138 const char *sr_name
;
2139 int is_user
, is_write
;
2144 is_user
= (opname
[1] == 'u');
2145 is_write
= (opname
[0] == 'w');
2147 /* Opname == [rw]ur or [rwx]sr... */
2149 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2152 /* Check if the argument is a symbolic register name. */
2153 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2154 /* Handle WSR to "INTSET" as a special case. */
2155 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2156 && !strcasecmp (arg_strings
[1], "intset"))
2157 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2158 if (sr
== XTENSA_UNDEFINED
2159 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2161 /* Maybe it's a register number.... */
2163 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2165 as_bad (_("invalid register '%s' for '%s' instruction"),
2166 arg_strings
[1], opname
);
2169 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2170 if (sr
== XTENSA_UNDEFINED
)
2172 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2173 (long) val
, opname
);
2178 /* Remove the last argument, which is now part of the opcode. */
2179 free (arg_strings
[1]);
2183 /* Translate the opcode. */
2184 sr_name
= xtensa_sysreg_name (isa
, sr
);
2185 /* Another special case for "WSR.INTSET".... */
2186 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2188 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2189 sprintf (new_opname
, "%s.%s", *popname
, sr_name
);
2191 *popname
= new_opname
;
2198 xtensa_translate_old_userreg_ops (char **popname
)
2200 xtensa_isa isa
= xtensa_default_isa
;
2202 char *opname
, *new_opname
;
2203 const char *sr_name
;
2204 bfd_boolean has_underbar
= FALSE
;
2207 if (opname
[0] == '_')
2209 has_underbar
= TRUE
;
2213 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2214 if (sr
!= XTENSA_UNDEFINED
)
2216 /* The new default name ("nnn") is different from the old default
2217 name ("URnnn"). The old default is handled below, and we don't
2218 want to recognize [RW]nnn, so do nothing if the name is the (new)
2220 static char namebuf
[10];
2221 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2222 if (strcmp (namebuf
, opname
+ 1) == 0)
2230 /* Only continue if the reg name is "URnnn". */
2231 if (opname
[1] != 'u' || opname
[2] != 'r')
2233 val
= strtoul (opname
+ 3, &end
, 10);
2237 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2238 if (sr
== XTENSA_UNDEFINED
)
2240 as_bad (_("invalid register number (%ld) for '%s'"),
2241 (long) val
, opname
);
2246 /* Translate the opcode. */
2247 sr_name
= xtensa_sysreg_name (isa
, sr
);
2248 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2249 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2250 opname
[0], sr_name
);
2252 *popname
= new_opname
;
2259 xtensa_translate_zero_immed (char *old_op
,
2269 assert (opname
[0] != '_');
2271 if (strcmp (opname
, old_op
) != 0)
2274 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2276 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2278 xg_replace_opname (popname
, new_op
);
2279 free (arg_strings
[1]);
2280 arg_strings
[1] = arg_strings
[2];
2289 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2290 Returns non-zero if an error was found. */
2293 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2295 char *opname
= *popname
;
2296 bfd_boolean has_underbar
= FALSE
;
2298 if (cur_vinsn
.inside_bundle
)
2303 has_underbar
= TRUE
;
2307 if (strcmp (opname
, "mov") == 0)
2309 if (use_transform () && !has_underbar
&& density_supported
)
2310 xg_replace_opname (popname
, "mov.n");
2313 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2315 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2316 arg_strings
[2] = (char *) xmalloc (strlen (arg_strings
[1]) + 1);
2317 strcpy (arg_strings
[2], arg_strings
[1]);
2323 if (strcmp (opname
, "bbsi.l") == 0)
2325 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2327 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2328 if (target_big_endian
)
2329 xg_reverse_shift_count (&arg_strings
[1]);
2333 if (strcmp (opname
, "bbci.l") == 0)
2335 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2337 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2338 if (target_big_endian
)
2339 xg_reverse_shift_count (&arg_strings
[1]);
2343 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
2344 && strcmp (opname
, "nop") == 0)
2346 if (use_transform () && !has_underbar
&& density_supported
)
2347 xg_replace_opname (popname
, "nop.n");
2350 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2352 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2353 arg_strings
[0] = (char *) xmalloc (3);
2354 arg_strings
[1] = (char *) xmalloc (3);
2355 arg_strings
[2] = (char *) xmalloc (3);
2356 strcpy (arg_strings
[0], "a1");
2357 strcpy (arg_strings
[1], "a1");
2358 strcpy (arg_strings
[2], "a1");
2364 /* Recognize [RW]UR and [RWX]SR. */
2365 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2366 && (opname
[1] == 'u' || opname
[1] == 's'))
2367 || (opname
[0] == 'x' && opname
[1] == 's'))
2369 && opname
[3] == '\0')
2370 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2372 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2373 [RW]<name> if <name> is the non-default name of a user register. */
2374 if ((opname
[0] == 'r' || opname
[0] == 'w')
2375 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2376 return xtensa_translate_old_userreg_ops (popname
);
2378 /* Relax branches that don't allow comparisons against an immediate value
2379 of zero to the corresponding branches with implicit zero immediates. */
2380 if (!has_underbar
&& use_transform ())
2382 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2383 pnum_args
, arg_strings
))
2386 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2387 pnum_args
, arg_strings
))
2390 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2391 pnum_args
, arg_strings
))
2394 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2395 pnum_args
, arg_strings
))
2403 /* Functions for dealing with the Xtensa ISA. */
2405 /* Currently the assembler only allows us to use a single target per
2406 fragment. Because of this, only one operand for a given
2407 instruction may be symbolic. If there is a PC-relative operand,
2408 the last one is chosen. Otherwise, the result is the number of the
2409 last immediate operand, and if there are none of those, we fail and
2413 get_relaxable_immed (xtensa_opcode opcode
)
2415 int last_immed
= -1;
2418 if (opcode
== XTENSA_UNDEFINED
)
2421 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2422 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2424 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2426 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2428 if (last_immed
== -1
2429 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2436 static xtensa_opcode
2437 get_opcode_from_buf (const char *buf
, int slot
)
2439 static xtensa_insnbuf insnbuf
= NULL
;
2440 static xtensa_insnbuf slotbuf
= NULL
;
2441 xtensa_isa isa
= xtensa_default_isa
;
2446 insnbuf
= xtensa_insnbuf_alloc (isa
);
2447 slotbuf
= xtensa_insnbuf_alloc (isa
);
2450 xtensa_insnbuf_from_chars (isa
, insnbuf
, (const unsigned char *) buf
, 0);
2451 fmt
= xtensa_format_decode (isa
, insnbuf
);
2452 if (fmt
== XTENSA_UNDEFINED
)
2453 return XTENSA_UNDEFINED
;
2455 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2456 return XTENSA_UNDEFINED
;
2458 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2459 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2463 #ifdef TENSILICA_DEBUG
2465 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2468 xtensa_print_insn_table (void)
2470 int num_opcodes
, num_operands
;
2471 xtensa_opcode opcode
;
2472 xtensa_isa isa
= xtensa_default_isa
;
2474 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2475 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2478 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2479 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2480 for (opn
= 0; opn
< num_operands
; opn
++)
2482 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2484 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2486 xtensa_regfile opnd_rf
=
2487 xtensa_operand_regfile (isa
, opcode
, opn
);
2488 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2490 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2491 fputs ("[lLr] ", stderr
);
2493 fputs ("i ", stderr
);
2495 fprintf (stderr
, "\n");
2501 print_vliw_insn (xtensa_insnbuf vbuf
)
2503 xtensa_isa isa
= xtensa_default_isa
;
2504 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2505 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2508 fprintf (stderr
, "format = %d\n", f
);
2510 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2512 xtensa_opcode opcode
;
2516 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2517 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2518 opname
= xtensa_opcode_name (isa
, opcode
);
2520 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2521 fprintf (stderr
, " operands = ");
2523 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2527 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2529 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2530 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2531 fprintf (stderr
, "%d ", val
);
2533 fprintf (stderr
, "\n");
2535 xtensa_insnbuf_free (isa
, sbuf
);
2538 #endif /* TENSILICA_DEBUG */
2542 is_direct_call_opcode (xtensa_opcode opcode
)
2544 xtensa_isa isa
= xtensa_default_isa
;
2545 int n
, num_operands
;
2547 if (xtensa_opcode_is_call (isa
, opcode
) != 1)
2550 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2551 for (n
= 0; n
< num_operands
; n
++)
2553 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2554 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2561 /* Convert from BFD relocation type code to slot and operand number.
2562 Returns non-zero on failure. */
2565 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2567 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2568 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2570 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2573 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2574 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2576 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2586 /* Convert from slot number to BFD relocation type code for the
2587 standard PC-relative relocations. Return BFD_RELOC_NONE on
2590 static bfd_reloc_code_real_type
2591 encode_reloc (int slot
)
2593 if (slot
< 0 || slot
> 14)
2594 return BFD_RELOC_NONE
;
2596 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2600 /* Convert from slot numbers to BFD relocation type code for the
2601 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2603 static bfd_reloc_code_real_type
2604 encode_alt_reloc (int slot
)
2606 if (slot
< 0 || slot
> 14)
2607 return BFD_RELOC_NONE
;
2609 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2614 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2617 xtensa_opcode opcode
,
2623 uint32 valbuf
= value
;
2625 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2627 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2629 as_bad_where ((char *) file
, line
,
2630 _("operand %d of '%s' has out of range value '%u'"),
2632 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2635 as_bad_where ((char *) file
, line
,
2636 _("operand %d of '%s' has invalid value '%u'"),
2638 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2643 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2649 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2652 xtensa_opcode opcode
,
2656 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2657 fmt
, slot
, slotbuf
, &val
);
2658 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2663 /* Checks for rules from xtensa-relax tables. */
2665 /* The routine xg_instruction_matches_option_term must return TRUE
2666 when a given option term is true. The meaning of all of the option
2667 terms is given interpretation by this function. This is needed when
2668 an option depends on the state of a directive, but there are no such
2669 options in use right now. */
2672 xg_instruction_matches_option_term (TInsn
*insn ATTRIBUTE_UNUSED
,
2673 const ReqOrOption
*option
)
2675 if (strcmp (option
->option_name
, "realnop") == 0
2676 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2678 /* These conditions were evaluated statically when building the
2679 relaxation table. There's no need to reevaluate them now. */
2684 as_fatal (_("internal error: unknown option name '%s'"),
2685 option
->option_name
);
2691 xg_instruction_matches_or_options (TInsn
*insn
,
2692 const ReqOrOptionList
*or_option
)
2694 const ReqOrOption
*option
;
2695 /* Must match each of the AND terms. */
2696 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2698 if (xg_instruction_matches_option_term (insn
, option
))
2706 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2708 const ReqOption
*req_options
;
2709 /* Must match each of the AND terms. */
2710 for (req_options
= options
;
2711 req_options
!= NULL
;
2712 req_options
= req_options
->next
)
2714 /* Must match one of the OR clauses. */
2715 if (!xg_instruction_matches_or_options (insn
,
2716 req_options
->or_option_terms
))
2723 /* Return the transition rule that matches or NULL if none matches. */
2726 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2728 PreconditionList
*condition_l
;
2730 if (rule
->opcode
!= insn
->opcode
)
2733 for (condition_l
= rule
->conditions
;
2734 condition_l
!= NULL
;
2735 condition_l
= condition_l
->next
)
2739 Precondition
*cond
= condition_l
->precond
;
2744 /* The expression must be the constant. */
2745 assert (cond
->op_num
< insn
->ntok
);
2746 exp1
= &insn
->tok
[cond
->op_num
];
2747 if (expr_is_const (exp1
))
2752 if (get_expr_const (exp1
) != cond
->op_data
)
2756 if (get_expr_const (exp1
) == cond
->op_data
)
2763 else if (expr_is_register (exp1
))
2768 if (get_expr_register (exp1
) != cond
->op_data
)
2772 if (get_expr_register (exp1
) == cond
->op_data
)
2784 assert (cond
->op_num
< insn
->ntok
);
2785 assert (cond
->op_data
< insn
->ntok
);
2786 exp1
= &insn
->tok
[cond
->op_num
];
2787 exp2
= &insn
->tok
[cond
->op_data
];
2792 if (!expr_is_equal (exp1
, exp2
))
2796 if (expr_is_equal (exp1
, exp2
))
2808 if (!xg_instruction_matches_options (insn
, rule
->options
))
2816 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
2818 bfd_boolean a_greater
= FALSE
;
2819 bfd_boolean b_greater
= FALSE
;
2821 ReqOptionList
*l_a
= a
->options
;
2822 ReqOptionList
*l_b
= b
->options
;
2824 /* We only care if they both are the same except for
2825 a const16 vs. an l32r. */
2827 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2829 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
2830 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
2831 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2833 if (l_or_a
->is_true
!= l_or_b
->is_true
)
2835 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
2837 /* This is the case we care about. */
2838 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
2839 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
2846 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
2847 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
2857 l_or_a
= l_or_a
->next
;
2858 l_or_b
= l_or_b
->next
;
2860 if (l_or_a
|| l_or_b
)
2869 /* Incomparable if the substitution was used differently in two cases. */
2870 if (a_greater
&& b_greater
)
2882 static TransitionRule
*
2883 xg_instruction_match (TInsn
*insn
)
2885 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
2887 assert (insn
->opcode
< table
->num_opcodes
);
2889 /* Walk through all of the possible transitions. */
2890 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2892 TransitionRule
*rule
= l
->rule
;
2893 if (xg_instruction_matches_rule (insn
, rule
))
2900 /* Various Other Internal Functions. */
2903 is_unique_insn_expansion (TransitionRule
*r
)
2905 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
2907 if (r
->to_instr
->typ
!= INSTR_INSTR
)
2913 /* Check if there is exactly one relaxation for INSN that converts it to
2914 another instruction of equal or larger size. If so, and if TARG is
2915 non-null, go ahead and generate the relaxed instruction into TARG. If
2916 NARROW_ONLY is true, then only consider relaxations that widen a narrow
2917 instruction, i.e., ignore relaxations that convert to an instruction of
2918 equal size. In some contexts where this function is used, only
2919 a single widening is allowed and the NARROW_ONLY argument is used to
2920 exclude cases like ADDI being "widened" to an ADDMI, which may
2921 later be relaxed to an ADDMI/ADDI pair. */
2924 xg_is_single_relaxable_insn (TInsn
*insn
, TInsn
*targ
, bfd_boolean narrow_only
)
2926 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
2928 TransitionRule
*match
= 0;
2930 assert (insn
->insn_type
== ITYPE_INSN
);
2931 assert (insn
->opcode
< table
->num_opcodes
);
2933 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2935 TransitionRule
*rule
= l
->rule
;
2937 if (xg_instruction_matches_rule (insn
, rule
)
2938 && is_unique_insn_expansion (rule
)
2939 && (xg_get_single_size (insn
->opcode
) + (narrow_only
? 1 : 0)
2940 <= xg_get_single_size (rule
->to_instr
->opcode
)))
2951 xg_build_to_insn (targ
, insn
, match
->to_instr
);
2956 /* Return the maximum number of bytes this opcode can expand to. */
2959 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
2961 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
2963 int max_size
= xg_get_single_size (opcode
);
2965 assert (opcode
< table
->num_opcodes
);
2967 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
2969 TransitionRule
*rule
= l
->rule
;
2970 BuildInstr
*build_list
;
2975 build_list
= rule
->to_instr
;
2976 if (is_unique_insn_expansion (rule
))
2978 assert (build_list
->typ
== INSTR_INSTR
);
2979 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
2982 for (; build_list
!= NULL
; build_list
= build_list
->next
)
2984 switch (build_list
->typ
)
2987 this_size
+= xg_get_single_size (build_list
->opcode
);
2989 case INSTR_LITERAL_DEF
:
2990 case INSTR_LABEL_DEF
:
2995 if (this_size
> max_size
)
2996 max_size
= this_size
;
3002 /* Return the maximum number of literal bytes this opcode can generate. */
3005 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3007 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3011 assert (opcode
< table
->num_opcodes
);
3013 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3015 TransitionRule
*rule
= l
->rule
;
3016 BuildInstr
*build_list
;
3021 build_list
= rule
->to_instr
;
3022 if (is_unique_insn_expansion (rule
))
3024 assert (build_list
->typ
== INSTR_INSTR
);
3025 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3028 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3030 switch (build_list
->typ
)
3032 case INSTR_LITERAL_DEF
:
3033 /* Hard-coded 4-byte literal. */
3037 case INSTR_LABEL_DEF
:
3042 if (this_size
> max_size
)
3043 max_size
= this_size
;
3050 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3052 int steps_taken
= 0;
3053 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3056 assert (insn
->insn_type
== ITYPE_INSN
);
3057 assert (insn
->opcode
< table
->num_opcodes
);
3059 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3061 TransitionRule
*rule
= l
->rule
;
3063 if (xg_instruction_matches_rule (insn
, rule
))
3065 if (steps_taken
== lateral_steps
)
3075 get_special_literal_symbol (void)
3077 static symbolS
*sym
= NULL
;
3080 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3086 get_special_label_symbol (void)
3088 static symbolS
*sym
= NULL
;
3091 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3097 xg_valid_literal_expression (const expressionS
*exp
)
3114 /* This will check to see if the value can be converted into the
3115 operand type. It will return TRUE if it does not fit. */
3118 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3120 uint32 valbuf
= value
;
3121 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3127 /* Assumes: All immeds are constants. Check that all constants fit
3128 into their immeds; return FALSE if not. */
3131 xg_immeds_fit (const TInsn
*insn
)
3133 xtensa_isa isa
= xtensa_default_isa
;
3137 assert (insn
->insn_type
== ITYPE_INSN
);
3138 for (i
= 0; i
< n
; ++i
)
3140 const expressionS
*expr
= &insn
->tok
[i
];
3141 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3148 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3153 /* The symbol should have a fixup associated with it. */
3162 /* This should only be called after we have an initial
3163 estimate of the addresses. */
3166 xg_symbolic_immeds_fit (const TInsn
*insn
,
3172 xtensa_isa isa
= xtensa_default_isa
;
3180 assert (insn
->insn_type
== ITYPE_INSN
);
3182 for (i
= 0; i
< n
; ++i
)
3184 const expressionS
*expr
= &insn
->tok
[i
];
3185 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3192 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3198 /* Check for the worst case. */
3199 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3204 /* We only allow symbols for PC-relative references.
3205 If pc_frag == 0, then we don't have frag locations yet. */
3207 || xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0)
3210 /* If it is a weak symbol, then assume it won't reach. */
3211 if (S_IS_WEAK (expr
->X_add_symbol
))
3214 if (is_direct_call_opcode (insn
->opcode
)
3215 && ! pc_frag
->tc_frag_data
.use_longcalls
)
3217 /* If callee is undefined or in a different segment, be
3218 optimistic and assume it will be in range. */
3219 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3223 /* Only references within a segment can be known to fit in the
3224 operands at assembly time. */
3225 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3228 symbolP
= expr
->X_add_symbol
;
3229 sym_frag
= symbol_get_frag (symbolP
);
3230 target
= S_GET_VALUE (symbolP
) + expr
->X_add_number
;
3231 pc
= pc_frag
->fr_address
+ pc_offset
;
3233 /* If frag has yet to be reached on this pass, assume it
3234 will move by STRETCH just as we did. If this is not so,
3235 it will be because some frag between grows, and that will
3236 force another pass. Beware zero-length frags. There
3237 should be a faster way to do this. */
3240 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3241 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3246 new_offset
= target
;
3247 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3248 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3253 /* The symbol should have a fixup associated with it. */
3262 /* Return TRUE on success. */
3265 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3270 memset (targ
, 0, sizeof (TInsn
));
3271 targ
->linenum
= insn
->linenum
;
3276 targ
->opcode
= bi
->opcode
;
3277 targ
->insn_type
= ITYPE_INSN
;
3278 targ
->is_specific_opcode
= FALSE
;
3280 for (; op
!= NULL
; op
= op
->next
)
3282 int op_num
= op
->op_num
;
3283 int op_data
= op
->op_data
;
3285 assert (op
->op_num
< MAX_INSN_ARGS
);
3287 if (targ
->ntok
<= op_num
)
3288 targ
->ntok
= op_num
+ 1;
3293 set_expr_const (&targ
->tok
[op_num
], op_data
);
3296 assert (op_data
< insn
->ntok
);
3297 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3300 sym
= get_special_literal_symbol ();
3301 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3304 sym
= get_special_label_symbol ();
3305 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3307 case OP_OPERAND_HI16U
:
3308 case OP_OPERAND_LOW16U
:
3309 assert (op_data
< insn
->ntok
);
3310 if (expr_is_const (&insn
->tok
[op_data
]))
3313 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3314 val
= xg_apply_userdef_op_fn (op
->typ
,
3317 targ
->tok
[op_num
].X_add_number
= val
;
3321 /* For const16 we can create relocations for these. */
3322 if (targ
->opcode
== XTENSA_UNDEFINED
3323 || (targ
->opcode
!= xtensa_const16_opcode
))
3325 assert (op_data
< insn
->ntok
);
3326 /* Need to build a O_lo16 or O_hi16. */
3327 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3328 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3330 if (op
->typ
== OP_OPERAND_HI16U
)
3331 targ
->tok
[op_num
].X_op
= O_hi16
;
3332 else if (op
->typ
== OP_OPERAND_LOW16U
)
3333 targ
->tok
[op_num
].X_op
= O_lo16
;
3340 /* currently handles:
3343 OP_OPERAND_F32MINUS */
3344 if (xg_has_userdef_op_fn (op
->typ
))
3346 assert (op_data
< insn
->ntok
);
3347 if (expr_is_const (&insn
->tok
[op_data
]))
3350 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3351 val
= xg_apply_userdef_op_fn (op
->typ
,
3354 targ
->tok
[op_num
].X_add_number
= val
;
3357 return FALSE
; /* We cannot use a relocation for this. */
3366 case INSTR_LITERAL_DEF
:
3368 targ
->opcode
= XTENSA_UNDEFINED
;
3369 targ
->insn_type
= ITYPE_LITERAL
;
3370 targ
->is_specific_opcode
= FALSE
;
3371 for (; op
!= NULL
; op
= op
->next
)
3373 int op_num
= op
->op_num
;
3374 int op_data
= op
->op_data
;
3375 assert (op
->op_num
< MAX_INSN_ARGS
);
3377 if (targ
->ntok
<= op_num
)
3378 targ
->ntok
= op_num
+ 1;
3383 assert (op_data
< insn
->ntok
);
3384 /* We can only pass resolvable literals through. */
3385 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3387 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3399 case INSTR_LABEL_DEF
:
3401 targ
->opcode
= XTENSA_UNDEFINED
;
3402 targ
->insn_type
= ITYPE_LABEL
;
3403 targ
->is_specific_opcode
= FALSE
;
3404 /* Literal with no ops is a label? */
3405 assert (op
== NULL
);
3416 /* Return TRUE on success. */
3419 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3421 for (; bi
!= NULL
; bi
= bi
->next
)
3423 TInsn
*next_insn
= istack_push_space (istack
);
3425 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3432 /* Return TRUE on valid expansion. */
3435 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3437 int stack_size
= istack
->ninsn
;
3438 int steps_taken
= 0;
3439 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3442 assert (insn
->insn_type
== ITYPE_INSN
);
3443 assert (insn
->opcode
< table
->num_opcodes
);
3445 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3447 TransitionRule
*rule
= l
->rule
;
3449 if (xg_instruction_matches_rule (insn
, rule
))
3451 if (lateral_steps
== steps_taken
)
3455 /* This is it. Expand the rule to the stack. */
3456 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3459 /* Check to see if it fits. */
3460 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3462 TInsn
*insn
= &istack
->insn
[i
];
3464 if (insn
->insn_type
== ITYPE_INSN
3465 && !tinsn_has_symbolic_operands (insn
)
3466 && !xg_immeds_fit (insn
))
3468 istack
->ninsn
= stack_size
;
3481 /* Relax the assembly instruction at least "min_steps".
3482 Return the number of steps taken. */
3485 xg_assembly_relax (IStack
*istack
,
3488 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3489 offsetT pc_offset
, /* offset in fragment */
3490 int min_steps
, /* minimum conversion steps */
3491 long stretch
) /* number of bytes stretched so far */
3493 int steps_taken
= 0;
3495 /* assert (has no symbolic operands)
3496 Some of its immeds don't fit.
3497 Try to build a relaxed version.
3498 This may go through a couple of stages
3499 of single instruction transformations before
3502 TInsn single_target
;
3504 int lateral_steps
= 0;
3505 int istack_size
= istack
->ninsn
;
3507 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3508 && steps_taken
>= min_steps
)
3510 istack_push (istack
, insn
);
3513 current_insn
= *insn
;
3515 /* Walk through all of the single instruction expansions. */
3516 while (xg_is_single_relaxable_insn (¤t_insn
, &single_target
, FALSE
))
3519 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3522 if (steps_taken
>= min_steps
)
3524 istack_push (istack
, &single_target
);
3528 current_insn
= single_target
;
3531 /* Now check for a multi-instruction expansion. */
3532 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3534 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3537 if (steps_taken
>= min_steps
)
3539 istack_push (istack
, ¤t_insn
);
3544 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3546 if (steps_taken
>= min_steps
)
3550 istack
->ninsn
= istack_size
;
3553 /* It's not going to work -- use the original. */
3554 istack_push (istack
, insn
);
3560 xg_force_frag_space (int size
)
3562 /* This may have the side effect of creating a new fragment for the
3563 space to go into. I just do not like the name of the "frag"
3570 xg_finish_frag (char *last_insn
,
3571 enum xtensa_relax_statesE frag_state
,
3572 enum xtensa_relax_statesE slot0_state
,
3574 bfd_boolean is_insn
)
3576 /* Finish off this fragment so that it has at LEAST the desired
3577 max_growth. If it doesn't fit in this fragment, close this one
3578 and start a new one. In either case, return a pointer to the
3579 beginning of the growth area. */
3583 xg_force_frag_space (max_growth
);
3585 old_frag
= frag_now
;
3587 frag_now
->fr_opcode
= last_insn
;
3589 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3591 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3592 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3594 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3595 xtensa_set_frag_assembly_state (frag_now
);
3597 /* Just to make sure that we did not split it up. */
3598 assert (old_frag
->fr_next
== frag_now
);
3602 /* Return TRUE if the target frag is one of the next non-empty frags. */
3605 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3610 for (; fragP
; fragP
= fragP
->fr_next
)
3612 if (fragP
== target
)
3614 if (fragP
->fr_fix
!= 0)
3616 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3618 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3619 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3621 if (fragP
->fr_type
== rs_space
)
3629 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3631 xtensa_isa isa
= xtensa_default_isa
;
3633 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3638 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) != 1
3639 && xtensa_opcode_is_jump (isa
, insn
->opcode
) != 1)
3642 for (i
= 0; i
< num_ops
; i
++)
3644 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3650 if (target_op
== -1)
3653 if (insn
->ntok
<= target_op
)
3656 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3659 sym
= insn
->tok
[target_op
].X_add_symbol
;
3663 if (insn
->tok
[target_op
].X_add_number
!= 0)
3666 target_frag
= symbol_get_frag (sym
);
3667 if (target_frag
== NULL
)
3670 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3671 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3679 xg_add_branch_and_loop_targets (TInsn
*insn
)
3681 xtensa_isa isa
= xtensa_default_isa
;
3682 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3684 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3687 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3688 && insn
->tok
[i
].X_op
== O_symbol
)
3689 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3693 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3694 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3698 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3700 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3701 && insn
->tok
[i
].X_op
== O_symbol
)
3703 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3704 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3705 if (S_IS_DEFINED (sym
))
3706 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3713 /* Return FALSE if no error. */
3716 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3721 switch (instr_spec
->typ
)
3724 new_insn
->insn_type
= ITYPE_INSN
;
3725 new_insn
->opcode
= instr_spec
->opcode
;
3726 new_insn
->is_specific_opcode
= FALSE
;
3727 new_insn
->linenum
= old_insn
->linenum
;
3729 case INSTR_LITERAL_DEF
:
3730 new_insn
->insn_type
= ITYPE_LITERAL
;
3731 new_insn
->opcode
= XTENSA_UNDEFINED
;
3732 new_insn
->is_specific_opcode
= FALSE
;
3733 new_insn
->linenum
= old_insn
->linenum
;
3735 case INSTR_LABEL_DEF
:
3736 as_bad (_("INSTR_LABEL_DEF not supported yet"));
3740 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3743 const expressionS
*src_exp
;
3749 /* The expression must be the constant. */
3750 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3751 exp
= &new_insn
->tok
[b_op
->op_num
];
3752 set_expr_const (exp
, b_op
->op_data
);
3756 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3757 assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
3758 src_exp
= &old_insn
->tok
[b_op
->op_data
];
3759 exp
= &new_insn
->tok
[b_op
->op_num
];
3760 copy_expr (exp
, src_exp
);
3765 as_bad (_("can't handle generation of literal/labels yet"));
3769 as_bad (_("can't handle undefined OP TYPE"));
3774 new_insn
->ntok
= num_ops
;
3779 /* Return TRUE if it was simplified. */
3782 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
3784 TransitionRule
*rule
;
3785 BuildInstr
*insn_spec
;
3787 if (old_insn
->is_specific_opcode
|| !density_supported
)
3790 rule
= xg_instruction_match (old_insn
);
3794 insn_spec
= rule
->to_instr
;
3795 /* There should only be one. */
3796 assert (insn_spec
!= NULL
);
3797 assert (insn_spec
->next
== NULL
);
3798 if (insn_spec
->next
!= NULL
)
3801 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
3807 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3808 l32i.n. (2) Check the number of operands. (3) Place the instruction
3809 tokens into the stack or relax it and place multiple
3810 instructions/literals onto the stack. Return FALSE if no error. */
3813 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
3817 bfd_boolean do_expand
;
3819 memset (&new_insn
, 0, sizeof (TInsn
));
3821 /* Narrow it if we can. xg_simplify_insn now does all the
3822 appropriate checking (e.g., for the density option). */
3823 if (xg_simplify_insn (orig_insn
, &new_insn
))
3824 orig_insn
= &new_insn
;
3826 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
3828 if (orig_insn
->ntok
< noperands
)
3830 as_bad (_("found %d operands for '%s': Expected %d"),
3832 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3836 if (orig_insn
->ntok
> noperands
)
3837 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
3839 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3842 /* If there are not enough operands, we will assert above. If there
3843 are too many, just cut out the extras here. */
3844 orig_insn
->ntok
= noperands
;
3846 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
3849 /* If the instruction will definitely need to be relaxed, it is better
3850 to expand it now for better scheduling. Decide whether to expand
3852 do_expand
= (!orig_insn
->is_specific_opcode
&& use_transform ());
3854 /* Calls should be expanded to longcalls only in the backend relaxation
3855 so that the assembly scheduler will keep the L32R/CALLX instructions
3857 if (is_direct_call_opcode (orig_insn
->opcode
))
3860 if (tinsn_has_symbolic_operands (orig_insn
))
3862 /* The values of symbolic operands are not known yet, so only expand
3863 now if an operand is "complex" (e.g., difference of symbols) and
3864 will have to be stored as a literal regardless of the value. */
3865 if (!tinsn_has_complex_operands (orig_insn
))
3868 else if (xg_immeds_fit (orig_insn
))
3872 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
3874 istack_push (istack
, orig_insn
);
3880 /* Return TRUE if the section flags are marked linkonce
3881 or the name is .gnu.linkonce.*. */
3883 static int linkonce_len
= sizeof (".gnu.linkonce.") - 1;
3886 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
3888 flagword flags
, link_once_flags
;
3890 flags
= bfd_get_section_flags (abfd
, sec
);
3891 link_once_flags
= (flags
& SEC_LINK_ONCE
);
3893 /* Flags might not be set yet. */
3894 if (!link_once_flags
3895 && strncmp (segment_name (sec
), ".gnu.linkonce.", linkonce_len
) == 0)
3896 link_once_flags
= SEC_LINK_ONCE
;
3898 return (link_once_flags
!= 0);
3903 xtensa_add_literal_sym (symbolS
*sym
)
3907 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
3909 l
->next
= literal_syms
;
3915 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
3917 static int lit_num
= 0;
3918 static char name
[256];
3921 sprintf (name
, ".L_lit_sym%d", lit_num
);
3923 /* Create a local symbol. If it is in a linkonce section, we have to
3924 be careful to make sure that if it is used in a relocation that the
3925 symbol will be in the output file. */
3926 if (get_is_linkonce_section (stdoutput
, sec
))
3928 symbolP
= symbol_new (name
, sec
, 0, frag
);
3929 S_CLEAR_EXTERNAL (symbolP
);
3930 /* symbolP->local = 1; */
3933 symbolP
= symbol_new (name
, sec
, 0, frag
);
3935 xtensa_add_literal_sym (symbolP
);
3942 /* Currently all literals that are generated here are 32-bit L32R targets. */
3945 xg_assemble_literal (/* const */ TInsn
*insn
)
3948 symbolS
*lit_sym
= NULL
;
3950 /* size = 4 for L32R. It could easily be larger when we move to
3951 larger constants. Add a parameter later. */
3952 offsetT litsize
= 4;
3953 offsetT litalign
= 2; /* 2^2 = 4 */
3954 expressionS saved_loc
;
3955 expressionS
* emit_val
;
3957 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
3959 assert (insn
->insn_type
== ITYPE_LITERAL
);
3960 assert (insn
->ntok
== 1); /* must be only one token here */
3962 xtensa_switch_to_literal_fragment (&state
);
3964 emit_val
= &insn
->tok
[0];
3965 if (emit_val
->X_op
== O_big
)
3967 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
3970 /* This happens when someone writes a "movi a2, big_number". */
3971 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
3972 _("invalid immediate"));
3973 xtensa_restore_emit_state (&state
);
3978 /* Force a 4-byte align here. Note that this opens a new frag, so all
3979 literals done with this function have a frag to themselves. That's
3980 important for the way text section literals work. */
3981 frag_align (litalign
, 0, 0);
3982 record_alignment (now_seg
, litalign
);
3984 if (emit_val
->X_op
== O_pltrel
)
3986 char *p
= frag_more (litsize
);
3987 xtensa_set_frag_assembly_state (frag_now
);
3988 if (emit_val
->X_add_symbol
)
3989 emit_val
->X_op
= O_symbol
;
3991 emit_val
->X_op
= O_constant
;
3992 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
3993 litsize
, emit_val
, 0, BFD_RELOC_XTENSA_PLT
);
3996 emit_expr (emit_val
, litsize
);
3998 assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
3999 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4000 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4001 lit_sym
= frag_now
->fr_symbol
;
4004 xtensa_restore_emit_state (&state
);
4010 xg_assemble_literal_space (/* const */ int size
, int slot
)
4013 /* We might have to do something about this alignment. It only
4014 takes effect if something is placed here. */
4015 offsetT litalign
= 2; /* 2^2 = 4 */
4016 fragS
*lit_saved_frag
;
4018 assert (size
% 4 == 0);
4020 xtensa_switch_to_literal_fragment (&state
);
4022 /* Force a 4-byte align here. */
4023 frag_align (litalign
, 0, 0);
4024 record_alignment (now_seg
, litalign
);
4026 xg_force_frag_space (size
);
4028 lit_saved_frag
= frag_now
;
4029 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4030 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4031 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4034 xtensa_restore_emit_state (&state
);
4035 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4039 /* Put in a fixup record based on the opcode.
4040 Return TRUE on success. */
4043 xg_add_opcode_fix (TInsn
*tinsn
,
4051 xtensa_opcode opcode
= tinsn
->opcode
;
4052 bfd_reloc_code_real_type reloc
;
4053 reloc_howto_type
*howto
;
4057 reloc
= BFD_RELOC_NONE
;
4059 /* First try the special cases for "alternate" relocs. */
4060 if (opcode
== xtensa_l32r_opcode
)
4062 if (fragP
->tc_frag_data
.use_absolute_literals
)
4063 reloc
= encode_alt_reloc (slot
);
4065 else if (opcode
== xtensa_const16_opcode
)
4067 if (expr
->X_op
== O_lo16
)
4069 reloc
= encode_reloc (slot
);
4070 expr
->X_op
= O_symbol
;
4072 else if (expr
->X_op
== O_hi16
)
4074 reloc
= encode_alt_reloc (slot
);
4075 expr
->X_op
= O_symbol
;
4079 if (opnum
!= get_relaxable_immed (opcode
))
4081 as_bad (_("invalid relocation for operand %i of '%s'"),
4082 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4086 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4087 into the symbol table where the generic portions of the assembler
4088 won't know what to do with them. */
4089 if (expr
->X_op
== O_lo16
|| expr
->X_op
== O_hi16
)
4091 as_bad (_("invalid expression for operand %i of '%s'"),
4092 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4096 /* Next try the generic relocs. */
4097 if (reloc
== BFD_RELOC_NONE
)
4098 reloc
= encode_reloc (slot
);
4099 if (reloc
== BFD_RELOC_NONE
)
4101 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4105 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4108 as_bad (_("undefined symbol for opcode \"%s\""),
4109 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4113 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4114 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, expr
,
4115 howto
->pc_relative
, reloc
);
4116 the_fix
->fx_no_overflow
= 1;
4117 the_fix
->tc_fix_data
.X_add_symbol
= expr
->X_add_symbol
;
4118 the_fix
->tc_fix_data
.X_add_number
= expr
->X_add_number
;
4119 the_fix
->tc_fix_data
.slot
= slot
;
4126 xg_emit_insn_to_buf (TInsn
*tinsn
,
4130 bfd_boolean build_fix
)
4132 static xtensa_insnbuf insnbuf
= NULL
;
4133 bfd_boolean has_symbolic_immed
= FALSE
;
4134 bfd_boolean ok
= TRUE
;
4137 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4139 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4140 if (has_symbolic_immed
&& build_fix
)
4143 xtensa_format fmt
= xg_get_single_format (tinsn
->opcode
);
4144 int slot
= xg_get_single_slot (tinsn
->opcode
);
4145 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4146 expressionS
*exp
= &tinsn
->tok
[opnum
];
4148 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, slot
, exp
, fragP
, offset
))
4151 fragP
->tc_frag_data
.is_insn
= TRUE
;
4152 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4153 (unsigned char *) buf
, 0);
4159 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4161 symbolS
*sym
= get_special_literal_symbol ();
4165 assert (insn
->insn_type
== ITYPE_INSN
);
4166 for (i
= 0; i
< insn
->ntok
; i
++)
4167 if (insn
->tok
[i
].X_add_symbol
== sym
)
4168 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4174 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4176 symbolS
*sym
= get_special_label_symbol ();
4178 for (i
= 0; i
< insn
->ntok
; i
++)
4179 if (insn
->tok
[i
].X_add_symbol
== sym
)
4180 insn
->tok
[i
].X_add_symbol
= label_sym
;
4185 /* Return TRUE if the instruction can write to the specified
4186 integer register. */
4189 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4193 xtensa_isa isa
= xtensa_default_isa
;
4195 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4197 for (i
= 0; i
< num_ops
; i
++)
4200 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4201 if ((inout
== 'o' || inout
== 'm')
4202 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4204 xtensa_regfile opnd_rf
=
4205 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4206 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4208 if ((insn
->tok
[i
].X_op
== O_register
)
4209 && (insn
->tok
[i
].X_add_number
== regnum
))
4219 is_bad_loopend_opcode (const TInsn
*tinsn
)
4221 xtensa_opcode opcode
= tinsn
->opcode
;
4223 if (opcode
== XTENSA_UNDEFINED
)
4226 if (opcode
== xtensa_call0_opcode
4227 || opcode
== xtensa_callx0_opcode
4228 || opcode
== xtensa_call4_opcode
4229 || opcode
== xtensa_callx4_opcode
4230 || opcode
== xtensa_call8_opcode
4231 || opcode
== xtensa_callx8_opcode
4232 || opcode
== xtensa_call12_opcode
4233 || opcode
== xtensa_callx12_opcode
4234 || opcode
== xtensa_isync_opcode
4235 || opcode
== xtensa_ret_opcode
4236 || opcode
== xtensa_ret_n_opcode
4237 || opcode
== xtensa_retw_opcode
4238 || opcode
== xtensa_retw_n_opcode
4239 || opcode
== xtensa_waiti_opcode
4240 || opcode
== xtensa_rsr_lcount_opcode
)
4247 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4248 This allows the debugger to add unaligned labels.
4249 Also, the assembler generates stabs labels that need
4250 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4253 is_unaligned_label (symbolS
*sym
)
4255 const char *name
= S_GET_NAME (sym
);
4256 static size_t fake_size
= 0;
4260 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4263 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4265 fake_size
= strlen (FAKE_LABEL_NAME
);
4268 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4269 && (name
[fake_size
] == 'F'
4270 || name
[fake_size
] == 'L'
4271 || (name
[fake_size
] == 'e'
4272 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4280 next_non_empty_frag (const fragS
*fragP
)
4282 fragS
*next_fragP
= fragP
->fr_next
;
4284 /* Sometimes an empty will end up here due storage allocation issues.
4285 So we have to skip until we find something legit. */
4286 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4287 next_fragP
= next_fragP
->fr_next
;
4289 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4297 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4299 xtensa_opcode out_opcode
;
4300 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4302 if (next_fragP
== NULL
)
4305 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4306 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4308 *opcode
= out_opcode
;
4316 frag_format_size (const fragS
*fragP
)
4318 static xtensa_insnbuf insnbuf
= NULL
;
4319 xtensa_isa isa
= xtensa_default_isa
;
4324 insnbuf
= xtensa_insnbuf_alloc (isa
);
4327 return XTENSA_UNDEFINED
;
4329 xtensa_insnbuf_from_chars (isa
, insnbuf
,
4330 (unsigned char *) fragP
->fr_literal
, 0);
4332 fmt
= xtensa_format_decode (isa
, insnbuf
);
4333 if (fmt
== XTENSA_UNDEFINED
)
4334 return XTENSA_UNDEFINED
;
4335 fmt_size
= xtensa_format_length (isa
, fmt
);
4337 /* If the next format won't be changing due to relaxation, just
4338 return the length of the first format. */
4339 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4342 /* If during relaxation we have to pull an instruction out of a
4343 multi-slot instruction, we will return the more conservative
4344 number. This works because alignment on bigger instructions
4345 is more restrictive than alignment on smaller instructions.
4346 This is more conservative than we would like, but it happens
4349 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4352 /* If we aren't doing one of our own relaxations or it isn't
4353 slot-based, then the insn size won't change. */
4354 if (fragP
->fr_type
!= rs_machine_dependent
)
4356 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4359 /* If an instruction is about to grow, return the longer size. */
4360 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4361 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
)
4364 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4365 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4372 next_frag_format_size (const fragS
*fragP
)
4374 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4375 return frag_format_size (next_fragP
);
4379 /* In early Xtensa Processors, for reasons that are unclear, the ISA
4380 required two-byte instructions to be treated as three-byte instructions
4381 for loop instruction alignment. This restriction was removed beginning
4382 with Xtensa LX. Now the only requirement on loop instruction alignment
4383 is that the first instruction of the loop must appear at an address that
4384 does not cross a fetch boundary. */
4387 get_loop_align_size (int insn_size
)
4389 if (insn_size
== XTENSA_UNDEFINED
)
4390 return xtensa_fetch_width
;
4392 if (enforce_three_byte_loop_align
&& insn_size
== 2)
4399 /* If the next legit fragment is an end-of-loop marker,
4400 switch its state so it will instantiate a NOP. */
4403 update_next_frag_state (fragS
*fragP
)
4405 fragS
*next_fragP
= fragP
->fr_next
;
4406 fragS
*new_target
= NULL
;
4410 /* We are guaranteed there will be one of these... */
4411 while (!(next_fragP
->fr_type
== rs_machine_dependent
4412 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4413 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4414 next_fragP
= next_fragP
->fr_next
;
4416 assert (next_fragP
->fr_type
== rs_machine_dependent
4417 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4418 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4420 /* ...and one of these. */
4421 new_target
= next_fragP
->fr_next
;
4422 while (!(new_target
->fr_type
== rs_machine_dependent
4423 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4424 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4425 new_target
= new_target
->fr_next
;
4427 assert (new_target
->fr_type
== rs_machine_dependent
4428 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4429 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4432 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4434 if (next_fragP
->fr_type
== rs_machine_dependent
4435 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4437 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4441 next_fragP
= next_fragP
->fr_next
;
4447 next_frag_is_branch_target (const fragS
*fragP
)
4449 /* Sometimes an empty will end up here due to storage allocation issues,
4450 so we have to skip until we find something legit. */
4451 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4453 if (fragP
->tc_frag_data
.is_branch_target
)
4455 if (fragP
->fr_fix
!= 0)
4463 next_frag_is_loop_target (const fragS
*fragP
)
4465 /* Sometimes an empty will end up here due storage allocation issues.
4466 So we have to skip until we find something legit. */
4467 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4469 if (fragP
->tc_frag_data
.is_loop_target
)
4471 if (fragP
->fr_fix
!= 0)
4479 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4481 const fragS
*next_fragp
= fragp
->fr_next
;
4482 xtensa_opcode next_opcode
;
4484 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4487 /* Sometimes an empty will end up here due to storage allocation issues,
4488 so we have to skip until we find something legit. */
4489 while (next_fragp
->fr_fix
== 0)
4490 next_fragp
= next_fragp
->fr_next
;
4492 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4495 /* There is some implicit knowledge encoded in here.
4496 The LOOP instructions that are NOT RELAX_IMMED have
4497 been relaxed. Note that we can assume that the LOOP
4498 instruction is in slot 0 because loops aren't bundleable. */
4499 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4500 return get_expanded_loop_offset (next_opcode
);
4506 /* Mark a location where we can later insert literal frags. Update
4507 the section's literal_pool_loc, so subsequent literals can be
4508 placed nearest to their use. */
4511 xtensa_mark_literal_pool_location (void)
4513 /* Any labels pointing to the current location need
4514 to be adjusted to after the literal pool. */
4516 fragS
*pool_location
;
4518 if (use_literal_section
)
4521 /* We stash info in these frags so we can later move the literal's
4522 fixes into this frchain's fix list. */
4523 pool_location
= frag_now
;
4524 frag_now
->tc_frag_data
.lit_frchain
= frchain_now
;
4525 frag_variant (rs_machine_dependent
, 0, 0,
4526 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4527 xtensa_set_frag_assembly_state (frag_now
);
4528 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
4529 frag_variant (rs_machine_dependent
, 0, 0,
4530 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4531 xtensa_set_frag_assembly_state (frag_now
);
4533 /* Now put a frag into the literal pool that points to this location. */
4534 set_literal_pool_location (now_seg
, pool_location
);
4535 xtensa_switch_to_non_abs_literal_fragment (&s
);
4536 frag_align (2, 0, 0);
4537 record_alignment (now_seg
, 2);
4539 /* Close whatever frag is there. */
4540 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4541 xtensa_set_frag_assembly_state (frag_now
);
4542 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
4543 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4544 xtensa_restore_emit_state (&s
);
4545 xtensa_set_frag_assembly_state (frag_now
);
4549 /* Build a nop of the correct size into tinsn. */
4552 build_nop (TInsn
*tinsn
, int size
)
4558 tinsn
->opcode
= xtensa_nop_n_opcode
;
4560 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4561 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4565 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4567 tinsn
->opcode
= xtensa_or_opcode
;
4568 set_expr_const (&tinsn
->tok
[0], 1);
4569 set_expr_const (&tinsn
->tok
[1], 1);
4570 set_expr_const (&tinsn
->tok
[2], 1);
4574 tinsn
->opcode
= xtensa_nop_opcode
;
4576 assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4581 /* Assemble a NOP of the requested size in the buffer. User must have
4582 allocated "buf" with at least "size" bytes. */
4585 assemble_nop (int size
, char *buf
)
4587 static xtensa_insnbuf insnbuf
= NULL
;
4590 build_nop (&tinsn
, size
);
4593 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4595 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4596 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4597 (unsigned char *) buf
, 0);
4601 /* Return the number of bytes for the offset of the expanded loop
4602 instruction. This should be incorporated into the relaxation
4603 specification but is hard-coded here. This is used to auto-align
4604 the loop instruction. It is invalid to call this function if the
4605 configuration does not have loops or if the opcode is not a loop
4609 get_expanded_loop_offset (xtensa_opcode opcode
)
4611 /* This is the OFFSET of the loop instruction in the expanded loop.
4612 This MUST correspond directly to the specification of the loop
4613 expansion. It will be validated on fragment conversion. */
4614 assert (opcode
!= XTENSA_UNDEFINED
);
4615 if (opcode
== xtensa_loop_opcode
)
4617 if (opcode
== xtensa_loopnez_opcode
)
4619 if (opcode
== xtensa_loopgtz_opcode
)
4621 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4627 get_literal_pool_location (segT seg
)
4629 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4634 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4636 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4640 /* Set frag assembly state should be called when a new frag is
4641 opened and after a frag has been closed. */
4644 xtensa_set_frag_assembly_state (fragS
*fragP
)
4646 if (!density_supported
)
4647 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4649 /* This function is called from subsegs_finish, which is called
4650 after xtensa_end, so we can't use "use_transform" or
4651 "use_schedule" here. */
4652 if (!directive_state
[directive_transform
])
4653 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4654 if (directive_state
[directive_longcalls
])
4655 fragP
->tc_frag_data
.use_longcalls
= TRUE
;
4656 fragP
->tc_frag_data
.use_absolute_literals
=
4657 directive_state
[directive_absolute_literals
];
4658 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4663 relaxable_section (asection
*sec
)
4665 return (sec
->flags
& SEC_DEBUGGING
) == 0;
4670 xtensa_find_unmarked_state_frags (void)
4674 /* Walk over each fragment of all of the current segments. For each
4675 unmarked fragment, mark it with the same info as the previous
4677 for (seclist
= &stdoutput
->sections
;
4678 seclist
&& *seclist
;
4679 seclist
= &(*seclist
)->next
)
4681 segT sec
= *seclist
;
4682 segment_info_type
*seginfo
;
4685 flags
= bfd_get_section_flags (stdoutput
, sec
);
4686 if (flags
& SEC_DEBUGGING
)
4688 if (!(flags
& SEC_ALLOC
))
4691 seginfo
= seg_info (sec
);
4692 if (seginfo
&& seginfo
->frchainP
)
4694 fragS
*last_fragP
= 0;
4695 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4696 fragP
= fragP
->fr_next
)
4698 if (fragP
->fr_fix
!= 0
4699 && !fragP
->tc_frag_data
.is_assembly_state_set
)
4701 if (last_fragP
== 0)
4703 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
4704 _("assembly state not set for first frag in section %s"),
4709 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4710 fragP
->tc_frag_data
.is_no_density
=
4711 last_fragP
->tc_frag_data
.is_no_density
;
4712 fragP
->tc_frag_data
.is_no_transform
=
4713 last_fragP
->tc_frag_data
.is_no_transform
;
4714 fragP
->tc_frag_data
.use_longcalls
=
4715 last_fragP
->tc_frag_data
.use_longcalls
;
4716 fragP
->tc_frag_data
.use_absolute_literals
=
4717 last_fragP
->tc_frag_data
.use_absolute_literals
;
4720 if (fragP
->tc_frag_data
.is_assembly_state_set
)
4729 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
4731 void *unused ATTRIBUTE_UNUSED
)
4733 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4734 segment_info_type
*seginfo
= seg_info (sec
);
4735 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4737 if (flags
& SEC_CODE
)
4739 xtensa_isa isa
= xtensa_default_isa
;
4740 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4741 while (frag
!= NULL
)
4743 if (frag
->tc_frag_data
.is_branch_target
)
4746 addressT branch_align
, frag_addr
;
4749 xtensa_insnbuf_from_chars
4750 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4751 fmt
= xtensa_format_decode (isa
, insnbuf
);
4752 op_size
= xtensa_format_length (isa
, fmt
);
4753 branch_align
= 1 << branch_align_power (sec
);
4754 frag_addr
= frag
->fr_address
% branch_align
;
4755 if (frag_addr
+ op_size
> branch_align
)
4756 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4757 _("unaligned branch target: %d bytes at 0x%lx"),
4758 op_size
, (long) frag
->fr_address
);
4760 frag
= frag
->fr_next
;
4762 xtensa_insnbuf_free (isa
, insnbuf
);
4768 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
4770 void *unused ATTRIBUTE_UNUSED
)
4772 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4773 segment_info_type
*seginfo
= seg_info (sec
);
4774 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4775 xtensa_isa isa
= xtensa_default_isa
;
4777 if (flags
& SEC_CODE
)
4779 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4780 while (frag
!= NULL
)
4782 if (frag
->tc_frag_data
.is_first_loop_insn
)
4788 xtensa_insnbuf_from_chars
4789 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4790 fmt
= xtensa_format_decode (isa
, insnbuf
);
4791 op_size
= xtensa_format_length (isa
, fmt
);
4792 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
4794 if (frag_addr
+ op_size
> xtensa_fetch_width
)
4795 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4796 _("unaligned loop: %d bytes at 0x%lx"),
4797 op_size
, (long) frag
->fr_address
);
4799 frag
= frag
->fr_next
;
4801 xtensa_insnbuf_free (isa
, insnbuf
);
4807 xg_apply_fix_value (fixS
*fixP
, valueT val
)
4809 xtensa_isa isa
= xtensa_default_isa
;
4810 static xtensa_insnbuf insnbuf
= NULL
;
4811 static xtensa_insnbuf slotbuf
= NULL
;
4814 bfd_boolean alt_reloc
;
4815 xtensa_opcode opcode
;
4816 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
4818 (void) decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
);
4820 as_fatal (_("unexpected fix"));
4824 insnbuf
= xtensa_insnbuf_alloc (isa
);
4825 slotbuf
= xtensa_insnbuf_alloc (isa
);
4828 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4829 fmt
= xtensa_format_decode (isa
, insnbuf
);
4830 if (fmt
== XTENSA_UNDEFINED
)
4831 as_fatal (_("undecodable fix"));
4832 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4833 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
4834 if (opcode
== XTENSA_UNDEFINED
)
4835 as_fatal (_("undecodable fix"));
4837 /* CONST16 immediates are not PC-relative, despite the fact that we
4838 reuse the normal PC-relative operand relocations for the low part
4839 of a CONST16 operand. */
4840 if (opcode
== xtensa_const16_opcode
)
4843 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
4844 get_relaxable_immed (opcode
), val
,
4845 fixP
->fx_file
, fixP
->fx_line
);
4847 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4848 xtensa_insnbuf_to_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4854 /* External Functions and Other GAS Hooks. */
4857 xtensa_target_format (void)
4859 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
4864 xtensa_file_arch_init (bfd
*abfd
)
4866 bfd_set_private_flags (abfd
, 0x100 | 0x200);
4871 md_number_to_chars (char *buf
, valueT val
, int n
)
4873 if (target_big_endian
)
4874 number_to_chars_bigendian (buf
, val
, n
);
4876 number_to_chars_littleendian (buf
, val
, n
);
4880 /* This function is called once, at assembler startup time. It should
4881 set up all the tables, etc. that the MD part of the assembler will
4887 segT current_section
= now_seg
;
4888 int current_subsec
= now_subseg
;
4891 xtensa_default_isa
= xtensa_isa_init (0, 0);
4892 isa
= xtensa_default_isa
;
4896 /* Set up the literal sections. */
4897 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
4899 subseg_set (current_section
, current_subsec
);
4901 xg_init_vinsn (&cur_vinsn
);
4903 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
4904 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
4905 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
4906 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
4907 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
4908 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
4909 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
4910 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
4911 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
4912 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
4913 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
4914 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
4915 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
4916 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
4917 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
4918 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
4919 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
4920 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
4921 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
4922 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
4923 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
4924 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
4925 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
4926 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
4927 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
4928 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
4929 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
4930 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
4931 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
4933 init_op_placement_info_table ();
4935 /* Set up the assembly state. */
4936 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
4937 xtensa_set_frag_assembly_state (frag_now
);
4941 /* TC_INIT_FIX_DATA hook */
4944 xtensa_init_fix_data (fixS
*x
)
4946 x
->tc_fix_data
.slot
= 0;
4947 x
->tc_fix_data
.X_add_symbol
= NULL
;
4948 x
->tc_fix_data
.X_add_number
= 0;
4952 /* tc_frob_label hook */
4955 xtensa_frob_label (symbolS
*sym
)
4959 if (cur_vinsn
.inside_bundle
)
4961 as_bad (_("labels are not valid inside bundles"));
4965 freq
= get_subseg_target_freq (now_seg
, now_subseg
);
4967 /* Since the label was already attached to a frag associated with the
4968 previous basic block, it now needs to be reset to the current frag. */
4969 symbol_set_frag (sym
, frag_now
);
4970 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
4972 if (generating_literals
)
4973 xtensa_add_literal_sym (sym
);
4975 xtensa_add_insn_label (sym
);
4977 if (symbol_get_tc (sym
)->is_loop_target
)
4979 if ((get_last_insn_flags (now_seg
, now_subseg
)
4980 & FLAG_IS_BAD_LOOPEND
) != 0)
4981 as_bad (_("invalid last instruction for a zero-overhead loop"));
4983 xtensa_set_frag_assembly_state (frag_now
);
4984 frag_var (rs_machine_dependent
, 4, 4, RELAX_LOOP_END
,
4985 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
4987 xtensa_set_frag_assembly_state (frag_now
);
4988 xtensa_move_labels (frag_now
, 0, TRUE
);
4991 /* No target aligning in the absolute section. */
4992 if (now_seg
!= absolute_section
4993 && do_align_targets ()
4994 && !is_unaligned_label (sym
)
4995 && !generating_literals
)
4997 xtensa_set_frag_assembly_state (frag_now
);
4999 frag_var (rs_machine_dependent
,
5001 RELAX_DESIRE_ALIGN_IF_TARGET
,
5002 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5003 xtensa_set_frag_assembly_state (frag_now
);
5004 xtensa_move_labels (frag_now
, 0, TRUE
);
5007 /* We need to mark the following properties even if we aren't aligning. */
5009 /* If the label is already known to be a branch target, i.e., a
5010 forward branch, mark the frag accordingly. Backward branches
5011 are handled by xg_add_branch_and_loop_targets. */
5012 if (symbol_get_tc (sym
)->is_branch_target
)
5013 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5015 /* Loops only go forward, so they can be identified here. */
5016 if (symbol_get_tc (sym
)->is_loop_target
)
5017 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5019 dwarf2_emit_label (sym
);
5023 /* tc_unrecognized_line hook */
5026 xtensa_unrecognized_line (int ch
)
5031 if (cur_vinsn
.inside_bundle
== 0)
5033 /* PR8110: Cannot emit line number info inside a FLIX bundle
5034 when using --gstabs. Temporarily disable debug info. */
5035 generate_lineno_debug ();
5036 if (debug_type
== DEBUG_STABS
)
5038 xt_saved_debug_type
= debug_type
;
5039 debug_type
= DEBUG_NONE
;
5042 cur_vinsn
.inside_bundle
= 1;
5046 as_bad (_("extra opening brace"));
5052 if (cur_vinsn
.inside_bundle
)
5053 finish_vinsn (&cur_vinsn
);
5056 as_bad (_("extra closing brace"));
5061 as_bad (_("syntax error"));
5068 /* md_flush_pending_output hook */
5071 xtensa_flush_pending_output (void)
5073 if (cur_vinsn
.inside_bundle
)
5074 as_bad (_("missing closing brace"));
5076 /* If there is a non-zero instruction fragment, close it. */
5077 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5079 frag_wane (frag_now
);
5081 xtensa_set_frag_assembly_state (frag_now
);
5083 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5085 xtensa_clear_insn_labels ();
5089 /* We had an error while parsing an instruction. The string might look
5090 like this: "insn arg1, arg2 }". If so, we need to see the closing
5091 brace and reset some fields. Otherwise, the vinsn never gets closed
5092 and the num_slots field will grow past the end of the array of slots,
5093 and bad things happen. */
5096 error_reset_cur_vinsn (void)
5098 if (cur_vinsn
.inside_bundle
)
5100 if (*input_line_pointer
== '}'
5101 || *(input_line_pointer
- 1) == '}'
5102 || *(input_line_pointer
- 2) == '}')
5103 xg_clear_vinsn (&cur_vinsn
);
5109 md_assemble (char *str
)
5111 xtensa_isa isa
= xtensa_default_isa
;
5112 char *opname
, *file_name
;
5114 bfd_boolean has_underbar
= FALSE
;
5115 char *arg_strings
[MAX_INSN_ARGS
];
5117 TInsn orig_insn
; /* Original instruction from the input. */
5119 tinsn_init (&orig_insn
);
5121 /* Split off the opcode. */
5122 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5123 opname
= xmalloc (opnamelen
+ 1);
5124 memcpy (opname
, str
, opnamelen
);
5125 opname
[opnamelen
] = '\0';
5127 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5130 as_bad (_("syntax error"));
5134 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5137 /* Check for an underbar prefix. */
5140 has_underbar
= TRUE
;
5144 orig_insn
.insn_type
= ITYPE_INSN
;
5146 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5148 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5149 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5151 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5152 if (fmt
== XTENSA_UNDEFINED
)
5154 as_bad (_("unknown opcode or format name '%s'"), opname
);
5155 error_reset_cur_vinsn ();
5158 if (!cur_vinsn
.inside_bundle
)
5160 as_bad (_("format names only valid inside bundles"));
5161 error_reset_cur_vinsn ();
5164 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5165 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5167 cur_vinsn
.format
= fmt
;
5168 free (has_underbar
? opname
- 1 : opname
);
5169 error_reset_cur_vinsn ();
5173 /* Parse the arguments. */
5174 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5176 as_bad (_("syntax error"));
5177 error_reset_cur_vinsn ();
5181 /* Free the opcode and argument strings, now that they've been parsed. */
5182 free (has_underbar
? opname
- 1 : opname
);
5184 while (num_args
-- > 0)
5185 free (arg_strings
[num_args
]);
5187 /* Get expressions for invisible operands. */
5188 if (get_invisible_operands (&orig_insn
))
5190 error_reset_cur_vinsn ();
5194 /* Check for the right number and type of arguments. */
5195 if (tinsn_check_arguments (&orig_insn
))
5197 error_reset_cur_vinsn ();
5201 /* A FLIX bundle may be spread across multiple input lines. We want to
5202 report the first such line in the debug information. Record the line
5203 number for each TInsn (assume the file name doesn't change), so the
5204 first line can be found later. */
5205 as_where (&file_name
, &orig_insn
.linenum
);
5207 xg_add_branch_and_loop_targets (&orig_insn
);
5209 /* Check that immediate value for ENTRY is >= 16. */
5210 if (orig_insn
.opcode
== xtensa_entry_opcode
&& orig_insn
.ntok
>= 3)
5212 expressionS
*exp
= &orig_insn
.tok
[2];
5213 if (exp
->X_op
== O_constant
&& exp
->X_add_number
< 16)
5214 as_warn (_("entry instruction with stack decrement < 16"));
5218 assemble_tokens (opcode, tok, ntok);
5219 expand the tokens from the orig_insn into the
5220 stack of instructions that will not expand
5221 unless required at relaxation time. */
5223 if (!cur_vinsn
.inside_bundle
)
5224 emit_single_op (&orig_insn
);
5225 else /* We are inside a bundle. */
5227 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5228 cur_vinsn
.num_slots
++;
5229 if (*input_line_pointer
== '}'
5230 || *(input_line_pointer
- 1) == '}'
5231 || *(input_line_pointer
- 2) == '}')
5232 finish_vinsn (&cur_vinsn
);
5235 /* We've just emitted a new instruction so clear the list of labels. */
5236 xtensa_clear_insn_labels ();
5240 /* HANDLE_ALIGN hook */
5242 /* For a .align directive, we mark the previous block with the alignment
5243 information. This will be placed in the object file in the
5244 property section corresponding to this section. */
5247 xtensa_handle_align (fragS
*fragP
)
5250 && ! fragP
->tc_frag_data
.is_literal
5251 && (fragP
->fr_type
== rs_align
5252 || fragP
->fr_type
== rs_align_code
)
5253 && fragP
->fr_address
+ fragP
->fr_fix
> 0
5254 && fragP
->fr_offset
> 0
5255 && now_seg
!= bss_section
)
5257 fragP
->tc_frag_data
.is_align
= TRUE
;
5258 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5261 if (fragP
->fr_type
== rs_align_test
)
5264 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5266 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5267 _("unaligned entry instruction"));
5272 /* TC_FRAG_INIT hook */
5275 xtensa_frag_init (fragS
*frag
)
5277 xtensa_set_frag_assembly_state (frag
);
5282 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5288 /* Round up a section size to the appropriate boundary. */
5291 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5293 return size
; /* Byte alignment is fine. */
5298 md_pcrel_from (fixS
*fixP
)
5301 static xtensa_insnbuf insnbuf
= NULL
;
5302 static xtensa_insnbuf slotbuf
= NULL
;
5305 xtensa_opcode opcode
;
5308 xtensa_isa isa
= xtensa_default_isa
;
5309 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5310 bfd_boolean alt_reloc
;
5312 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5317 insnbuf
= xtensa_insnbuf_alloc (isa
);
5318 slotbuf
= xtensa_insnbuf_alloc (isa
);
5321 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5322 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) insn_p
, 0);
5323 fmt
= xtensa_format_decode (isa
, insnbuf
);
5325 if (fmt
== XTENSA_UNDEFINED
)
5326 as_fatal (_("bad instruction format"));
5328 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5329 as_fatal (_("invalid relocation"));
5331 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5332 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5334 /* Check for "alternate" relocations (operand not specified). None
5335 of the current uses for these are really PC-relative. */
5336 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5338 if (opcode
!= xtensa_l32r_opcode
5339 && opcode
!= xtensa_const16_opcode
)
5340 as_fatal (_("invalid relocation for '%s' instruction"),
5341 xtensa_opcode_name (isa
, opcode
));
5345 opnum
= get_relaxable_immed (opcode
);
5347 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5348 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5350 as_bad_where (fixP
->fx_file
,
5352 _("invalid relocation for operand %d of '%s'"),
5353 opnum
, xtensa_opcode_name (isa
, opcode
));
5356 return 0 - opnd_value
;
5360 /* TC_FORCE_RELOCATION hook */
5363 xtensa_force_relocation (fixS
*fix
)
5365 switch (fix
->fx_r_type
)
5367 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5368 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5369 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5370 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5371 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5372 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5373 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5374 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5375 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5376 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5377 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5378 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5379 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5380 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5381 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5382 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5388 if (linkrelax
&& fix
->fx_addsy
5389 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5392 return generic_force_reloc (fix
);
5396 /* TC_VALIDATE_FIX_SUB hook */
5399 xtensa_validate_fix_sub (fixS
*fix
)
5401 segT add_symbol_segment
, sub_symbol_segment
;
5403 /* The difference of two symbols should be resolved by the assembler when
5404 linkrelax is not set. If the linker may relax the section containing
5405 the symbols, then an Xtensa DIFF relocation must be generated so that
5406 the linker knows to adjust the difference value. */
5407 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
5410 /* Make sure both symbols are in the same segment, and that segment is
5411 "normal" and relaxable. If the segment is not "normal", then the
5412 fix is not valid. If the segment is not "relaxable", then the fix
5413 should have been handled earlier. */
5414 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
5415 if (! SEG_NORMAL (add_symbol_segment
) ||
5416 ! relaxable_section (add_symbol_segment
))
5418 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
5419 return (sub_symbol_segment
== add_symbol_segment
);
5423 /* NO_PSEUDO_DOT hook */
5425 /* This function has nothing to do with pseudo dots, but this is the
5426 nearest macro to where the check needs to take place. FIXME: This
5430 xtensa_check_inside_bundle (void)
5432 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5433 as_bad (_("directives are not valid inside bundles"));
5435 /* This function must always return FALSE because it is called via a
5436 macro that has nothing to do with bundling. */
5441 /* md_elf_section_change_hook */
5444 xtensa_elf_section_change_hook (void)
5446 /* Set up the assembly state. */
5447 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5448 xtensa_set_frag_assembly_state (frag_now
);
5452 /* tc_fix_adjustable hook */
5455 xtensa_fix_adjustable (fixS
*fixP
)
5457 /* An offset is not allowed in combination with the difference of two
5458 symbols, but that cannot be easily detected after a local symbol
5459 has been adjusted to a (section+offset) form. Return 0 so that such
5460 an fix will not be adjusted. */
5461 if (fixP
->fx_subsy
&& fixP
->fx_addsy
&& fixP
->fx_offset
5462 && relaxable_section (S_GET_SEGMENT (fixP
->fx_subsy
)))
5465 /* We need the symbol name for the VTABLE entries. */
5466 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5467 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5475 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg
)
5477 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5480 /* Subtracted symbols are only allowed for a few relocation types, and
5481 unless linkrelax is enabled, they should not make it to this point. */
5482 if (fixP
->fx_subsy
&& !(linkrelax
&& (fixP
->fx_r_type
== BFD_RELOC_32
5483 || fixP
->fx_r_type
== BFD_RELOC_16
5484 || fixP
->fx_r_type
== BFD_RELOC_8
)))
5485 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("expression too complex"));
5487 switch (fixP
->fx_r_type
)
5494 switch (fixP
->fx_r_type
)
5497 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF8
;
5500 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF16
;
5503 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF32
;
5509 /* An offset is only allowed when it results from adjusting a
5510 local symbol into a section-relative offset. If the offset
5511 came from the original expression, tc_fix_adjustable will have
5512 prevented the fix from being converted to a section-relative
5513 form so that we can flag the error here. */
5514 if (fixP
->fx_offset
!= 0 && !symbol_section_p (fixP
->fx_addsy
))
5515 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5516 _("cannot represent subtraction with an offset"));
5518 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5519 - S_GET_VALUE (fixP
->fx_subsy
));
5521 /* The difference value gets written out, and the DIFF reloc
5522 identifies the address of the subtracted symbol (i.e., the one
5523 with the lowest address). */
5525 fixP
->fx_offset
-= val
;
5526 fixP
->fx_subsy
= NULL
;
5528 else if (! fixP
->fx_addsy
)
5535 case BFD_RELOC_XTENSA_PLT
:
5536 md_number_to_chars (fixpos
, val
, fixP
->fx_size
);
5537 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5540 case BFD_RELOC_XTENSA_SLOT0_OP
:
5541 case BFD_RELOC_XTENSA_SLOT1_OP
:
5542 case BFD_RELOC_XTENSA_SLOT2_OP
:
5543 case BFD_RELOC_XTENSA_SLOT3_OP
:
5544 case BFD_RELOC_XTENSA_SLOT4_OP
:
5545 case BFD_RELOC_XTENSA_SLOT5_OP
:
5546 case BFD_RELOC_XTENSA_SLOT6_OP
:
5547 case BFD_RELOC_XTENSA_SLOT7_OP
:
5548 case BFD_RELOC_XTENSA_SLOT8_OP
:
5549 case BFD_RELOC_XTENSA_SLOT9_OP
:
5550 case BFD_RELOC_XTENSA_SLOT10_OP
:
5551 case BFD_RELOC_XTENSA_SLOT11_OP
:
5552 case BFD_RELOC_XTENSA_SLOT12_OP
:
5553 case BFD_RELOC_XTENSA_SLOT13_OP
:
5554 case BFD_RELOC_XTENSA_SLOT14_OP
:
5557 /* Write the tentative value of a PC-relative relocation to a
5558 local symbol into the instruction. The value will be ignored
5559 by the linker, and it makes the object file disassembly
5560 readable when all branch targets are encoded in relocations. */
5562 assert (fixP
->fx_addsy
);
5563 if (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
5564 && !S_FORCE_RELOC (fixP
->fx_addsy
, 1))
5566 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5567 - md_pcrel_from (fixP
));
5568 (void) xg_apply_fix_value (fixP
, val
);
5571 else if (! fixP
->fx_addsy
)
5574 if (xg_apply_fix_value (fixP
, val
))
5579 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5580 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5581 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5582 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5583 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5584 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5585 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5586 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5587 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5588 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5589 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5590 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5591 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5592 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5593 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5594 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5595 /* These all need to be resolved at link-time. Do nothing now. */
5598 case BFD_RELOC_VTABLE_INHERIT
:
5599 case BFD_RELOC_VTABLE_ENTRY
:
5604 as_bad (_("unhandled local relocation fix %s"),
5605 bfd_get_reloc_code_name (fixP
->fx_r_type
));
5611 md_atof (int type
, char *litP
, int *sizeP
)
5614 LITTLENUM_TYPE words
[4];
5630 return "bad call to md_atof";
5633 t
= atof_ieee (input_line_pointer
, type
, words
);
5635 input_line_pointer
= t
;
5639 for (i
= prec
- 1; i
>= 0; i
--)
5642 if (target_big_endian
)
5643 idx
= (prec
- 1 - i
);
5645 md_number_to_chars (litP
, (valueT
) words
[idx
], 2);
5654 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
5656 return total_frag_text_expansion (fragP
);
5660 /* Translate internal representation of relocation info to BFD target
5664 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
5668 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
5669 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5670 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5671 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5673 /* Make sure none of our internal relocations make it this far.
5674 They'd better have been fully resolved by this point. */
5675 assert ((int) fixp
->fx_r_type
> 0);
5677 reloc
->addend
= fixp
->fx_offset
;
5679 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
5680 if (reloc
->howto
== NULL
)
5682 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5683 _("cannot represent `%s' relocation in object file"),
5684 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5685 free (reloc
->sym_ptr_ptr
);
5690 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
5691 as_fatal (_("internal error? cannot generate `%s' relocation"),
5692 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5698 /* Checks for resource conflicts between instructions. */
5700 /* The func unit stuff could be implemented as bit-vectors rather
5701 than the iterative approach here. If it ends up being too
5702 slow, we will switch it. */
5705 new_resource_table (void *data
,
5708 unit_num_copies_func uncf
,
5709 opcode_num_units_func onuf
,
5710 opcode_funcUnit_use_unit_func ouuf
,
5711 opcode_funcUnit_use_stage_func ousf
)
5714 resource_table
*rt
= (resource_table
*) xmalloc (sizeof (resource_table
));
5716 rt
->cycles
= cycles
;
5717 rt
->allocated_cycles
= cycles
;
5719 rt
->unit_num_copies
= uncf
;
5720 rt
->opcode_num_units
= onuf
;
5721 rt
->opcode_unit_use
= ouuf
;
5722 rt
->opcode_unit_stage
= ousf
;
5724 rt
->units
= (unsigned char **) xcalloc (cycles
, sizeof (unsigned char *));
5725 for (i
= 0; i
< cycles
; i
++)
5726 rt
->units
[i
] = (unsigned char *) xcalloc (nu
, sizeof (unsigned char));
5733 clear_resource_table (resource_table
*rt
)
5736 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
5737 for (j
= 0; j
< rt
->num_units
; j
++)
5738 rt
->units
[i
][j
] = 0;
5742 /* We never shrink it, just fake it into thinking so. */
5745 resize_resource_table (resource_table
*rt
, int cycles
)
5749 rt
->cycles
= cycles
;
5750 if (cycles
<= rt
->allocated_cycles
)
5753 old_cycles
= rt
->allocated_cycles
;
5754 rt
->allocated_cycles
= cycles
;
5756 rt
->units
= xrealloc (rt
->units
,
5757 rt
->allocated_cycles
* sizeof (unsigned char *));
5758 for (i
= 0; i
< old_cycles
; i
++)
5759 rt
->units
[i
] = xrealloc (rt
->units
[i
],
5760 rt
->num_units
* sizeof (unsigned char));
5761 for (i
= old_cycles
; i
< cycles
; i
++)
5762 rt
->units
[i
] = xcalloc (rt
->num_units
, sizeof (unsigned char));
5767 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5770 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5772 for (i
= 0; i
< uses
; i
++)
5774 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5775 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5776 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
5777 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
5778 if (copies_in_use
>= copies
)
5786 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5789 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5791 for (i
= 0; i
< uses
; i
++)
5793 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5794 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5795 /* Note that this allows resources to be oversubscribed. That's
5796 essential to the way the optional scheduler works.
5797 resources_available reports when a resource is over-subscribed,
5798 so it's easy to tell. */
5799 rt
->units
[stage
+ cycle
][unit
]++;
5805 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5808 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5810 for (i
= 0; i
< uses
; i
++)
5812 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5813 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5814 assert (rt
->units
[stage
+ cycle
][unit
] > 0);
5815 rt
->units
[stage
+ cycle
][unit
]--;
5820 /* Wrapper functions make parameterized resource reservation
5824 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
5826 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5832 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
5834 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5839 /* Note that this function does not check issue constraints, but
5840 solely whether the hardware is available to execute the given
5841 instructions together. It also doesn't check if the tinsns
5842 write the same state, or access the same tieports. That is
5843 checked by check_t1_t2_reads_and_writes. */
5846 resources_conflict (vliw_insn
*vinsn
)
5849 static resource_table
*rt
= NULL
;
5851 /* This is the most common case by far. Optimize it. */
5852 if (vinsn
->num_slots
== 1)
5857 xtensa_isa isa
= xtensa_default_isa
;
5858 rt
= new_resource_table
5859 (isa
, xtensa_isa_num_pipe_stages (isa
),
5860 xtensa_isa_num_funcUnits (isa
),
5861 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
5862 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
5863 opcode_funcUnit_use_unit
,
5864 opcode_funcUnit_use_stage
);
5867 clear_resource_table (rt
);
5869 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5871 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
5873 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
5880 /* finish_vinsn, emit_single_op and helper functions. */
5882 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
5883 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
5884 static void xg_assemble_vliw_tokens (vliw_insn
*);
5887 /* We have reached the end of a bundle; emit into the frag. */
5890 finish_vinsn (vliw_insn
*vinsn
)
5897 if (find_vinsn_conflicts (vinsn
))
5899 xg_clear_vinsn (vinsn
);
5903 /* First, find a format that works. */
5904 if (vinsn
->format
== XTENSA_UNDEFINED
)
5905 vinsn
->format
= xg_find_narrowest_format (vinsn
);
5907 if (vinsn
->format
== XTENSA_UNDEFINED
)
5909 as_where (&file_name
, &line
);
5910 as_bad_where (file_name
, line
,
5911 _("couldn't find a valid instruction format"));
5912 fprintf (stderr
, _(" ops were: "));
5913 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5914 fprintf (stderr
, _(" %s;"),
5915 xtensa_opcode_name (xtensa_default_isa
,
5916 vinsn
->slots
[i
].opcode
));
5917 fprintf (stderr
, _("\n"));
5918 xg_clear_vinsn (vinsn
);
5922 if (vinsn
->num_slots
5923 != xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
))
5925 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
5926 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
5927 xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
),
5929 xg_clear_vinsn (vinsn
);
5933 if (resources_conflict (vinsn
))
5935 as_where (&file_name
, &line
);
5936 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
5937 fprintf (stderr
, " ops were: ");
5938 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5939 fprintf (stderr
, " %s;",
5940 xtensa_opcode_name (xtensa_default_isa
,
5941 vinsn
->slots
[i
].opcode
));
5942 fprintf (stderr
, "\n");
5943 xg_clear_vinsn (vinsn
);
5947 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5949 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
5951 symbolS
*lit_sym
= NULL
;
5953 bfd_boolean e
= FALSE
;
5954 bfd_boolean saved_density
= density_supported
;
5956 /* We don't want to narrow ops inside multi-slot bundles. */
5957 if (vinsn
->num_slots
> 1)
5958 density_supported
= FALSE
;
5960 istack_init (&slotstack
);
5961 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
5963 vinsn
->slots
[i
].opcode
=
5964 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
5966 vinsn
->slots
[i
].ntok
= 0;
5969 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
5975 density_supported
= saved_density
;
5979 xg_clear_vinsn (vinsn
);
5983 for (j
= 0; j
< slotstack
.ninsn
; j
++)
5985 TInsn
*insn
= &slotstack
.insn
[j
];
5986 if (insn
->insn_type
== ITYPE_LITERAL
)
5988 assert (lit_sym
== NULL
);
5989 lit_sym
= xg_assemble_literal (insn
);
5993 assert (insn
->insn_type
== ITYPE_INSN
);
5995 xg_resolve_literals (insn
, lit_sym
);
5996 if (j
!= slotstack
.ninsn
- 1)
5997 emit_single_op (insn
);
6001 if (vinsn
->num_slots
> 1)
6003 if (opcode_fits_format_slot
6004 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6007 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6011 emit_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6012 if (vinsn
->format
== XTENSA_UNDEFINED
)
6013 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6015 vinsn
->slots
[i
].opcode
6016 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6019 vinsn
->slots
[i
].ntok
= 0;
6024 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6025 vinsn
->format
= XTENSA_UNDEFINED
;
6030 /* Now check resource conflicts on the modified bundle. */
6031 if (resources_conflict (vinsn
))
6033 as_where (&file_name
, &line
);
6034 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6035 fprintf (stderr
, " ops were: ");
6036 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6037 fprintf (stderr
, " %s;",
6038 xtensa_opcode_name (xtensa_default_isa
,
6039 vinsn
->slots
[i
].opcode
));
6040 fprintf (stderr
, "\n");
6041 xg_clear_vinsn (vinsn
);
6045 /* First, find a format that works. */
6046 if (vinsn
->format
== XTENSA_UNDEFINED
)
6047 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6049 xg_assemble_vliw_tokens (vinsn
);
6051 xg_clear_vinsn (vinsn
);
6055 /* Given an vliw instruction, what conflicts are there in register
6056 usage and in writes to states and queues?
6058 This function does two things:
6059 1. Reports an error when a vinsn contains illegal combinations
6060 of writes to registers states or queues.
6061 2. Marks individual tinsns as not relaxable if the combination
6062 contains antidependencies.
6064 Job 2 handles things like swap semantics in instructions that need
6065 to be relaxed. For example,
6069 normally would be relaxed to
6074 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6076 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6078 then we can't relax it into
6081 { add a0, a1, a0 ; add a2, a0, a4 ; }
6083 because the value of a0 is trashed before the second add can read it. */
6085 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6088 find_vinsn_conflicts (vliw_insn
*vinsn
)
6092 xtensa_isa isa
= xtensa_default_isa
;
6094 assert (!past_xtensa_end
);
6096 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6098 TInsn
*op1
= &vinsn
->slots
[i
];
6099 if (op1
->is_specific_opcode
)
6100 op1
->keep_wide
= TRUE
;
6102 op1
->keep_wide
= FALSE
;
6105 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6107 TInsn
*op1
= &vinsn
->slots
[i
];
6109 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6112 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6116 TInsn
*op2
= &vinsn
->slots
[j
];
6117 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6118 switch (conflict_type
)
6121 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6122 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6123 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6126 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6127 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6128 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6131 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"),
6132 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6133 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6136 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"),
6137 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6138 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6141 /* Everything is OK. */
6144 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6145 || conflict_type
== 'a');
6152 as_bad (_("multiple branches or jumps in the same bundle"));
6160 /* Check how the state used by t1 and t2 relate.
6163 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6164 case B: no relationship between what is read and written (both could
6165 read the same reg though)
6166 case C: t1 writes a register t2 writes (a register conflict within a
6168 case D: t1 writes a state that t2 also writes
6169 case E: t1 writes a tie queue that t2 also writes
6170 case F: two volatile queue accesses
6174 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6176 xtensa_isa isa
= xtensa_default_isa
;
6177 xtensa_regfile t1_regfile
, t2_regfile
;
6179 int t1_base_reg
, t1_last_reg
;
6180 int t2_base_reg
, t2_last_reg
;
6181 char t1_inout
, t2_inout
;
6183 char conflict
= 'b';
6188 bfd_boolean t1_volatile
= FALSE
;
6189 bfd_boolean t2_volatile
= FALSE
;
6191 /* Check registers. */
6192 for (j
= 0; j
< t2
->ntok
; j
++)
6194 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6197 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6198 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6199 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6201 for (i
= 0; i
< t1
->ntok
; i
++)
6203 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6206 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6208 if (t1_regfile
!= t2_regfile
)
6211 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6212 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6214 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6215 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6217 if (t1_inout
== 'm' || t1_inout
== 'o'
6218 || t2_inout
== 'm' || t2_inout
== 'o')
6225 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6226 t1_last_reg
= (t1_base_reg
6227 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6229 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6231 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6233 if (t1_reg
!= t2_reg
)
6236 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6242 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6248 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6256 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6257 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6258 for (j
= 0; j
< t2_states
; j
++)
6260 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6261 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6262 for (i
= 0; i
< t1_states
; i
++)
6264 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6265 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6269 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6275 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6281 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6286 /* Check tieports. */
6287 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6288 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6289 for (j
= 0; j
< t2_interfaces
; j
++)
6291 xtensa_interface t2_int
6292 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6293 int t2_class
= xtensa_interface_class_id (isa
, t2_int
);
6295 t2_inout
= xtensa_interface_inout (isa
, t2_int
);
6296 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1)
6299 for (i
= 0; i
< t1_interfaces
; i
++)
6301 xtensa_interface t1_int
6302 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6303 int t1_class
= xtensa_interface_class_id (isa
, t1_int
);
6305 t1_inout
= xtensa_interface_inout (isa
, t1_int
);
6306 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1)
6309 if (t1_volatile
&& t2_volatile
&& (t1_class
== t2_class
))
6312 if (t1_int
!= t2_int
)
6315 if (t2_inout
== 'i' && t1_inout
== 'o')
6321 if (t1_inout
== 'i' && t2_inout
== 'o')
6327 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6336 static xtensa_format
6337 xg_find_narrowest_format (vliw_insn
*vinsn
)
6339 /* Right now we assume that the ops within the vinsn are properly
6340 ordered for the slots that the programmer wanted them in. In
6341 other words, we don't rearrange the ops in hopes of finding a
6342 better format. The scheduler handles that. */
6344 xtensa_isa isa
= xtensa_default_isa
;
6345 xtensa_format format
;
6346 vliw_insn v_copy
= *vinsn
;
6347 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6349 if (vinsn
->num_slots
== 1)
6350 return xg_get_single_format (vinsn
->slots
[0].opcode
);
6352 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6355 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6359 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6361 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6363 v_copy
.slots
[slot
].opcode
=
6364 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6365 v_copy
.slots
[slot
].ntok
= 0;
6368 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6371 else if (v_copy
.num_slots
> 1)
6374 /* Try the widened version. */
6375 if (!v_copy
.slots
[slot
].keep_wide
6376 && !v_copy
.slots
[slot
].is_specific_opcode
6377 && xg_is_single_relaxable_insn (&v_copy
.slots
[slot
],
6379 && opcode_fits_format_slot (widened
.opcode
,
6382 v_copy
.slots
[slot
] = widened
;
6387 if (fit
== v_copy
.num_slots
)
6390 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6391 vinsn
->format
= format
;
6397 if (format
== xtensa_isa_num_formats (isa
))
6398 return XTENSA_UNDEFINED
;
6404 /* Return the additional space needed in a frag
6405 for possible relaxations of any ops in a VLIW insn.
6406 Also fill out the relaxations that might be required of
6407 each tinsn in the vinsn. */
6410 relaxation_requirements (vliw_insn
*vinsn
, bfd_boolean
*pfinish_frag
)
6412 bfd_boolean finish_frag
= FALSE
;
6413 int extra_space
= 0;
6416 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6418 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6419 if (!tinsn_has_symbolic_operands (tinsn
))
6421 /* A narrow instruction could be widened later to help
6422 alignment issues. */
6423 if (xg_is_single_relaxable_insn (tinsn
, 0, TRUE
)
6424 && !tinsn
->is_specific_opcode
6425 && vinsn
->num_slots
== 1)
6427 /* Difference in bytes between narrow and wide insns... */
6429 tinsn
->subtype
= RELAX_NARROW
;
6434 if (workaround_b_j_loop_end
6435 && tinsn
->opcode
== xtensa_jx_opcode
6436 && use_transform ())
6438 /* Add 2 of these. */
6439 extra_space
+= 3; /* for the nop size */
6440 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6443 /* Need to assemble it with space for the relocation. */
6444 if (xg_is_relaxable_insn (tinsn
, 0)
6445 && !tinsn
->is_specific_opcode
)
6447 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6448 int max_literal_size
=
6449 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6451 tinsn
->literal_space
= max_literal_size
;
6453 tinsn
->subtype
= RELAX_IMMED
;
6454 extra_space
+= max_size
;
6458 /* A fix record will be added for this instruction prior
6459 to relaxation, so make it end the frag. */
6464 *pfinish_frag
= finish_frag
;
6470 bundle_tinsn (TInsn
*tinsn
, vliw_insn
*vinsn
)
6472 xtensa_isa isa
= xtensa_default_isa
;
6473 int slot
, chosen_slot
;
6475 vinsn
->format
= xg_get_single_format (tinsn
->opcode
);
6476 assert (vinsn
->format
!= XTENSA_UNDEFINED
);
6477 vinsn
->num_slots
= xtensa_format_num_slots (isa
, vinsn
->format
);
6479 chosen_slot
= xg_get_single_slot (tinsn
->opcode
);
6480 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6482 if (slot
== chosen_slot
)
6483 vinsn
->slots
[slot
] = *tinsn
;
6486 vinsn
->slots
[slot
].opcode
=
6487 xtensa_format_slot_nop_opcode (isa
, vinsn
->format
, slot
);
6488 vinsn
->slots
[slot
].ntok
= 0;
6489 vinsn
->slots
[slot
].insn_type
= ITYPE_INSN
;
6496 emit_single_op (TInsn
*orig_insn
)
6499 IStack istack
; /* put instructions into here */
6500 symbolS
*lit_sym
= NULL
;
6501 symbolS
*label_sym
= NULL
;
6503 istack_init (&istack
);
6505 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6506 Because the scheduling and bundling characteristics of movi and
6507 l32r or const16 are so different, we can do much better if we relax
6508 it prior to scheduling and bundling, rather than after. */
6509 if ((orig_insn
->opcode
== xtensa_movi_opcode
6510 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
6511 && !cur_vinsn
.inside_bundle
6512 && (orig_insn
->tok
[1].X_op
== O_symbol
6513 || orig_insn
->tok
[1].X_op
== O_pltrel
)
6514 && !orig_insn
->is_specific_opcode
&& use_transform ())
6515 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
6517 if (xg_expand_assembly_insn (&istack
, orig_insn
))
6520 for (i
= 0; i
< istack
.ninsn
; i
++)
6522 TInsn
*insn
= &istack
.insn
[i
];
6523 switch (insn
->insn_type
)
6526 assert (lit_sym
== NULL
);
6527 lit_sym
= xg_assemble_literal (insn
);
6531 static int relaxed_sym_idx
= 0;
6532 char *label
= xmalloc (strlen (FAKE_LABEL_NAME
) + 12);
6533 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
6535 assert (label_sym
== NULL
);
6536 label_sym
= symbol_find_or_make (label
);
6545 xg_resolve_literals (insn
, lit_sym
);
6547 xg_resolve_labels (insn
, label_sym
);
6549 bundle_tinsn (insn
, &v
);
6564 total_frag_text_expansion (fragS
*fragP
)
6567 int total_expansion
= 0;
6569 for (slot
= 0; slot
< MAX_SLOTS
; slot
++)
6570 total_expansion
+= fragP
->tc_frag_data
.text_expansion
[slot
];
6572 return total_expansion
;
6576 /* Emit a vliw instruction to the current fragment. */
6579 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
6581 bfd_boolean finish_frag
;
6582 bfd_boolean is_jump
= FALSE
;
6583 bfd_boolean is_branch
= FALSE
;
6584 xtensa_isa isa
= xtensa_default_isa
;
6590 unsigned current_line
, best_linenum
;
6593 best_linenum
= UINT_MAX
;
6595 if (generating_literals
)
6597 static int reported
= 0;
6599 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
6600 _("cannot assemble into a literal fragment"));
6607 if (frag_now_fix () != 0
6608 && (! frag_now
->tc_frag_data
.is_insn
6609 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6610 || !use_transform () != frag_now
->tc_frag_data
.is_no_transform
6611 || (directive_state
[directive_longcalls
]
6612 != frag_now
->tc_frag_data
.use_longcalls
)
6613 || (directive_state
[directive_absolute_literals
]
6614 != frag_now
->tc_frag_data
.use_absolute_literals
)))
6616 frag_wane (frag_now
);
6618 xtensa_set_frag_assembly_state (frag_now
);
6621 if (workaround_a0_b_retw
6622 && vinsn
->num_slots
== 1
6623 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
6624 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
6625 && use_transform ())
6627 has_a0_b_retw
= TRUE
;
6629 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
6630 After the first assembly pass we will check all of them and
6631 add a nop if needed. */
6632 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6633 frag_var (rs_machine_dependent
, 4, 4,
6634 RELAX_ADD_NOP_IF_A0_B_RETW
,
6635 frag_now
->fr_symbol
,
6636 frag_now
->fr_offset
,
6638 xtensa_set_frag_assembly_state (frag_now
);
6639 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6640 frag_var (rs_machine_dependent
, 4, 4,
6641 RELAX_ADD_NOP_IF_A0_B_RETW
,
6642 frag_now
->fr_symbol
,
6643 frag_now
->fr_offset
,
6645 xtensa_set_frag_assembly_state (frag_now
);
6648 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6650 /* See if the instruction implies an aligned section. */
6651 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[i
].opcode
) == 1)
6652 record_alignment (now_seg
, 2);
6654 /* Also determine the best line number for debug info. */
6655 best_linenum
= vinsn
->slots
[i
].linenum
< best_linenum
6656 ? vinsn
->slots
[i
].linenum
: best_linenum
;
6659 /* Special cases for instructions that force an alignment... */
6660 /* None of these opcodes are bundle-able. */
6661 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
6665 /* Remember the symbol that marks the end of the loop in the frag
6666 that marks the start of the loop. This way we can easily find
6667 the end of the loop at the beginning, without adding special code
6668 to mark the loop instructions themselves. */
6669 symbolS
*target_sym
= NULL
;
6670 if (vinsn
->slots
[0].tok
[1].X_op
== O_symbol
)
6671 target_sym
= vinsn
->slots
[0].tok
[1].X_add_symbol
;
6673 xtensa_set_frag_assembly_state (frag_now
);
6674 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6676 max_fill
= get_text_align_max_fill_size
6677 (get_text_align_power (xtensa_fetch_width
),
6678 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
6680 if (use_transform ())
6681 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
6682 RELAX_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
6684 frag_var (rs_machine_dependent
, 0, 0,
6685 RELAX_CHECK_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
6686 xtensa_set_frag_assembly_state (frag_now
);
6688 xtensa_move_labels (frag_now
, 0, FALSE
);
6691 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
6692 && !vinsn
->slots
[0].is_specific_opcode
)
6694 xtensa_mark_literal_pool_location ();
6695 xtensa_move_labels (frag_now
, 0, TRUE
);
6696 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
6699 if (vinsn
->num_slots
== 1)
6701 if (workaround_a0_b_retw
&& use_transform ())
6702 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
6703 is_register_writer (&vinsn
->slots
[0], "a", 0));
6705 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
6706 is_bad_loopend_opcode (&vinsn
->slots
[0]));
6709 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
6711 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
6713 extra_space
= relaxation_requirements (vinsn
, &finish_frag
);
6715 /* vinsn_to_insnbuf will produce the error. */
6716 if (vinsn
->format
!= XTENSA_UNDEFINED
)
6718 f
= frag_more (insn_size
+ extra_space
);
6719 xtensa_set_frag_assembly_state (frag_now
);
6720 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6723 vinsn_to_insnbuf (vinsn
, f
, frag_now
, FALSE
);
6724 if (vinsn
->format
== XTENSA_UNDEFINED
)
6727 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, (unsigned char *) f
, 0);
6729 /* Temporarily set the logical line number to the one we want to appear
6730 in the debug information. */
6731 as_where (¤t_file
, ¤t_line
);
6732 new_logical_line (current_file
, best_linenum
);
6733 dwarf2_emit_insn (insn_size
+ extra_space
);
6734 new_logical_line (current_file
, current_line
);
6736 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6738 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6739 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
6740 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
6741 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
6742 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
6743 if (tinsn
->literal_space
!= 0)
6744 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
6746 if (tinsn
->subtype
== RELAX_NARROW
)
6747 assert (vinsn
->num_slots
== 1);
6748 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
6750 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
6753 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->offset
6754 || tinsn
->literal_frag
|| is_jump
|| is_branch
)
6758 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6759 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
6763 frag_variant (rs_machine_dependent
,
6764 extra_space
, extra_space
, RELAX_SLOTS
,
6765 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
6766 xtensa_set_frag_assembly_state (frag_now
);
6769 /* Special cases for loops:
6770 close_loop_end should be inserted AFTER short_loop.
6771 Make sure that CLOSE loops are processed BEFORE short_loops
6772 when converting them. */
6774 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
6775 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1
6776 && !vinsn
->slots
[0].is_specific_opcode
)
6778 if (workaround_short_loop
&& use_transform ())
6780 maybe_has_short_loop
= TRUE
;
6781 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6782 frag_var (rs_machine_dependent
, 4, 4,
6783 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6784 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6785 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6786 frag_var (rs_machine_dependent
, 4, 4,
6787 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6788 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6791 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
6792 loop at least 12 bytes away from another loop's end. */
6793 if (workaround_close_loop_end
&& use_transform ())
6795 maybe_has_close_loop_end
= TRUE
;
6796 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6797 frag_var (rs_machine_dependent
, 12, 12,
6798 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
6799 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6803 if (use_transform ())
6807 assert (finish_frag
);
6808 frag_var (rs_machine_dependent
,
6809 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6811 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6812 xtensa_set_frag_assembly_state (frag_now
);
6814 else if (is_branch
&& do_align_targets ())
6816 assert (finish_frag
);
6817 frag_var (rs_machine_dependent
,
6818 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6819 RELAX_MAYBE_UNREACHABLE
,
6820 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6821 xtensa_set_frag_assembly_state (frag_now
);
6822 frag_var (rs_machine_dependent
,
6824 RELAX_MAYBE_DESIRE_ALIGN
,
6825 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6826 xtensa_set_frag_assembly_state (frag_now
);
6830 /* Now, if the original opcode was a call... */
6831 if (do_align_targets ()
6832 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
6834 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
6835 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6836 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
6837 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6838 xtensa_set_frag_assembly_state (frag_now
);
6841 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6843 frag_wane (frag_now
);
6845 xtensa_set_frag_assembly_state (frag_now
);
6850 /* xtensa_end and helper functions. */
6852 static void xtensa_cleanup_align_frags (void);
6853 static void xtensa_fix_target_frags (void);
6854 static void xtensa_mark_narrow_branches (void);
6855 static void xtensa_mark_zcl_first_insns (void);
6856 static void xtensa_fix_a0_b_retw_frags (void);
6857 static void xtensa_fix_b_j_loop_end_frags (void);
6858 static void xtensa_fix_close_loop_end_frags (void);
6859 static void xtensa_fix_short_loop_frags (void);
6860 static void xtensa_sanity_check (void);
6861 static void xtensa_add_config_info (void);
6866 directive_balance ();
6867 xtensa_flush_pending_output ();
6869 past_xtensa_end
= TRUE
;
6871 xtensa_move_literals ();
6873 xtensa_reorder_segments ();
6874 xtensa_cleanup_align_frags ();
6875 xtensa_fix_target_frags ();
6876 if (workaround_a0_b_retw
&& has_a0_b_retw
)
6877 xtensa_fix_a0_b_retw_frags ();
6878 if (workaround_b_j_loop_end
)
6879 xtensa_fix_b_j_loop_end_frags ();
6881 /* "close_loop_end" should be processed BEFORE "short_loop". */
6882 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
6883 xtensa_fix_close_loop_end_frags ();
6885 if (workaround_short_loop
&& maybe_has_short_loop
)
6886 xtensa_fix_short_loop_frags ();
6888 xtensa_mark_narrow_branches ();
6889 xtensa_mark_zcl_first_insns ();
6891 xtensa_sanity_check ();
6893 xtensa_add_config_info ();
6898 xtensa_cleanup_align_frags (void)
6903 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
6904 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
6907 /* Walk over all of the fragments in a subsection. */
6908 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
6910 if ((fragP
->fr_type
== rs_align
6911 || fragP
->fr_type
== rs_align_code
6912 || (fragP
->fr_type
== rs_machine_dependent
6913 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
6914 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
6915 && fragP
->fr_fix
== 0)
6917 fragS
*next
= fragP
->fr_next
;
6920 && next
->fr_fix
== 0
6921 && next
->fr_type
== rs_machine_dependent
6922 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
6925 next
= next
->fr_next
;
6928 /* If we don't widen branch targets, then they
6929 will be easier to align. */
6930 if (fragP
->tc_frag_data
.is_branch_target
6931 && fragP
->fr_opcode
== fragP
->fr_literal
6932 && fragP
->fr_type
== rs_machine_dependent
6933 && fragP
->fr_subtype
== RELAX_SLOTS
6934 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
6936 if (fragP
->fr_type
== rs_machine_dependent
6937 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
6938 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
6944 /* Re-process all of the fragments looking to convert all of the
6945 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
6946 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
6947 Otherwise, convert to a .fill 0. */
6950 xtensa_fix_target_frags (void)
6955 /* When this routine is called, all of the subsections are still intact
6956 so we walk over subsections instead of sections. */
6957 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
6958 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
6962 /* Walk over all of the fragments in a subsection. */
6963 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
6965 if (fragP
->fr_type
== rs_machine_dependent
6966 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
6968 if (next_frag_is_branch_target (fragP
))
6969 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
6978 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
6981 xtensa_mark_narrow_branches (void)
6986 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
6987 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
6990 /* Walk over all of the fragments in a subsection. */
6991 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
6993 if (fragP
->fr_type
== rs_machine_dependent
6994 && fragP
->fr_subtype
== RELAX_SLOTS
6995 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
6999 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7000 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
7002 if (vinsn
.num_slots
== 1
7003 && xtensa_opcode_is_branch (xtensa_default_isa
,
7004 vinsn
.slots
[0].opcode
) == 1
7005 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
7006 && is_narrow_branch_guaranteed_in_range (fragP
,
7009 fragP
->fr_subtype
= RELAX_SLOTS
;
7010 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
7011 fragP
->tc_frag_data
.is_aligning_branch
= 1;
7019 /* A branch is typically widened only when its target is out of
7020 range. However, we would like to widen them to align a subsequent
7021 branch target when possible.
7023 Because the branch relaxation code is so convoluted, the optimal solution
7024 (combining the two cases) is difficult to get right in all circumstances.
7025 We therefore go with an "almost as good" solution, where we only
7026 use for alignment narrow branches that definitely will not expand to a
7027 jump and a branch. These functions find and mark these cases. */
7029 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
7030 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7031 We start counting beginning with the frag after the 2-byte branch, so the
7032 maximum offset is (4 - 2) + 63 = 65. */
7033 #define MAX_IMMED6 65
7035 static offsetT
unrelaxed_frag_max_size (fragS
*);
7038 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
7040 const expressionS
*expr
= &tinsn
->tok
[1];
7041 symbolS
*symbolP
= expr
->X_add_symbol
;
7042 offsetT max_distance
= expr
->X_add_number
;
7045 if (expr
->X_op
!= O_symbol
)
7048 target_frag
= symbol_get_frag (symbolP
);
7050 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
7051 if (is_branch_jmp_to_next (tinsn
, fragP
))
7054 /* The branch doesn't branch over it's own frag,
7055 but over the subsequent ones. */
7056 fragP
= fragP
->fr_next
;
7057 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
7059 max_distance
+= unrelaxed_frag_max_size (fragP
);
7060 fragP
= fragP
->fr_next
;
7062 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
7069 xtensa_mark_zcl_first_insns (void)
7074 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7075 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7078 /* Walk over all of the fragments in a subsection. */
7079 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7081 if (fragP
->fr_type
== rs_machine_dependent
7082 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7083 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7085 /* Find the loop frag. */
7086 fragS
*targ_frag
= next_non_empty_frag (fragP
);
7087 /* Find the first insn frag. */
7088 targ_frag
= next_non_empty_frag (targ_frag
);
7090 /* Of course, sometimes (mostly for toy test cases) a
7091 zero-cost loop instruction is the last in a section. */
7094 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
7095 /* Do not widen a frag that is the first instruction of a
7096 zero-cost loop. It makes that loop harder to align. */
7097 if (targ_frag
->fr_type
== rs_machine_dependent
7098 && targ_frag
->fr_subtype
== RELAX_SLOTS
7099 && (targ_frag
->tc_frag_data
.slot_subtypes
[0]
7102 if (targ_frag
->tc_frag_data
.is_aligning_branch
)
7103 targ_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
7106 frag_wane (targ_frag
);
7107 targ_frag
->tc_frag_data
.slot_subtypes
[0] = 0;
7111 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
7119 /* Re-process all of the fragments looking to convert all of the
7120 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7121 conditional branch or a retw/retw.n, convert this frag to one that
7122 will generate a NOP. In any case close it off with a .fill 0. */
7124 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
7127 xtensa_fix_a0_b_retw_frags (void)
7132 /* When this routine is called, all of the subsections are still intact
7133 so we walk over subsections instead of sections. */
7134 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7135 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7139 /* Walk over all of the fragments in a subsection. */
7140 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7142 if (fragP
->fr_type
== rs_machine_dependent
7143 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
7145 if (next_instrs_are_b_retw (fragP
))
7147 if (fragP
->tc_frag_data
.is_no_transform
)
7148 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7150 relax_frag_add_nop (fragP
);
7160 next_instrs_are_b_retw (fragS
*fragP
)
7162 xtensa_opcode opcode
;
7164 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
7165 static xtensa_insnbuf insnbuf
= NULL
;
7166 static xtensa_insnbuf slotbuf
= NULL
;
7167 xtensa_isa isa
= xtensa_default_isa
;
7170 bfd_boolean branch_seen
= FALSE
;
7174 insnbuf
= xtensa_insnbuf_alloc (isa
);
7175 slotbuf
= xtensa_insnbuf_alloc (isa
);
7178 if (next_fragP
== NULL
)
7181 /* Check for the conditional branch. */
7182 xtensa_insnbuf_from_chars
7183 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7184 fmt
= xtensa_format_decode (isa
, insnbuf
);
7185 if (fmt
== XTENSA_UNDEFINED
)
7188 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7190 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
7191 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
7193 branch_seen
= (branch_seen
7194 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
7200 offset
+= xtensa_format_length (isa
, fmt
);
7201 if (offset
== next_fragP
->fr_fix
)
7203 next_fragP
= next_non_empty_frag (next_fragP
);
7207 if (next_fragP
== NULL
)
7210 /* Check for the retw/retw.n. */
7211 xtensa_insnbuf_from_chars
7212 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7213 fmt
= xtensa_format_decode (isa
, insnbuf
);
7215 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
7216 have no problems. */
7217 if (fmt
== XTENSA_UNDEFINED
7218 || xtensa_format_num_slots (isa
, fmt
) != 1)
7221 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
7222 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
7224 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
7231 /* Re-process all of the fragments looking to convert all of the
7232 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
7233 loop end label, convert this frag to one that will generate a NOP.
7234 In any case close it off with a .fill 0. */
7236 static bfd_boolean
next_instr_is_loop_end (fragS
*);
7239 xtensa_fix_b_j_loop_end_frags (void)
7244 /* When this routine is called, all of the subsections are still intact
7245 so we walk over subsections instead of sections. */
7246 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7247 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7251 /* Walk over all of the fragments in a subsection. */
7252 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7254 if (fragP
->fr_type
== rs_machine_dependent
7255 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
7257 if (next_instr_is_loop_end (fragP
))
7259 if (fragP
->tc_frag_data
.is_no_transform
)
7260 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
7262 relax_frag_add_nop (fragP
);
7272 next_instr_is_loop_end (fragS
*fragP
)
7274 const fragS
*next_fragP
;
7276 if (next_frag_is_loop_target (fragP
))
7279 next_fragP
= next_non_empty_frag (fragP
);
7280 if (next_fragP
== NULL
)
7283 if (!next_frag_is_loop_target (next_fragP
))
7286 /* If the size is >= 3 then there is more than one instruction here.
7287 The hardware bug will not fire. */
7288 if (next_fragP
->fr_fix
> 3)
7295 /* Re-process all of the fragments looking to convert all of the
7296 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
7297 not MY loop's loop end within 12 bytes, add enough nops here to
7298 make it at least 12 bytes away. In any case close it off with a
7301 static offsetT min_bytes_to_other_loop_end
7302 (fragS
*, fragS
*, offsetT
);
7305 xtensa_fix_close_loop_end_frags (void)
7310 /* When this routine is called, all of the subsections are still intact
7311 so we walk over subsections instead of sections. */
7312 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7313 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7317 fragS
*current_target
= NULL
;
7319 /* Walk over all of the fragments in a subsection. */
7320 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7322 if (fragP
->fr_type
== rs_machine_dependent
7323 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7324 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7325 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7328 && fragP
->fr_type
== rs_machine_dependent
7329 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
7332 int bytes_added
= 0;
7334 #define REQUIRED_LOOP_DIVIDING_BYTES 12
7335 /* Max out at 12. */
7336 min_bytes
= min_bytes_to_other_loop_end
7337 (fragP
->fr_next
, current_target
, REQUIRED_LOOP_DIVIDING_BYTES
);
7339 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
7341 if (fragP
->tc_frag_data
.is_no_transform
)
7342 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
7345 while (min_bytes
+ bytes_added
7346 < REQUIRED_LOOP_DIVIDING_BYTES
)
7350 if (fragP
->fr_var
< length
)
7351 as_fatal (_("fr_var %lu < length %d"),
7352 (long) fragP
->fr_var
, length
);
7355 assemble_nop (length
,
7356 fragP
->fr_literal
+ fragP
->fr_fix
);
7357 fragP
->fr_fix
+= length
;
7358 fragP
->fr_var
-= length
;
7360 bytes_added
+= length
;
7366 assert (fragP
->fr_type
!= rs_machine_dependent
7367 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
7373 static offsetT
unrelaxed_frag_min_size (fragS
*);
7376 min_bytes_to_other_loop_end (fragS
*fragP
,
7377 fragS
*current_target
,
7381 fragS
*current_fragP
;
7383 for (current_fragP
= fragP
;
7385 current_fragP
= current_fragP
->fr_next
)
7387 if (current_fragP
->tc_frag_data
.is_loop_target
7388 && current_fragP
!= current_target
)
7391 offset
+= unrelaxed_frag_min_size (current_fragP
);
7393 if (offset
>= max_size
)
7401 unrelaxed_frag_min_size (fragS
*fragP
)
7403 offsetT size
= fragP
->fr_fix
;
7405 /* Add fill size. */
7406 if (fragP
->fr_type
== rs_fill
)
7407 size
+= fragP
->fr_offset
;
7414 unrelaxed_frag_max_size (fragS
*fragP
)
7416 offsetT size
= fragP
->fr_fix
;
7417 switch (fragP
->fr_type
)
7420 /* Empty frags created by the obstack allocation scheme
7421 end up with type 0. */
7426 size
+= fragP
->fr_offset
;
7434 /* No further adjustments needed. */
7436 case rs_machine_dependent
:
7437 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
7438 size
+= fragP
->fr_var
;
7441 /* We had darn well better know how big it is. */
7450 /* Re-process all of the fragments looking to convert all
7451 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
7454 1) the instruction size count to the loop end label
7455 is too short (<= 2 instructions),
7456 2) loop has a jump or branch in it
7459 1) workaround_all_short_loops is TRUE
7460 2) The generating loop was a 'loopgtz' or 'loopnez'
7461 3) the instruction size count to the loop end label is too short
7463 then convert this frag (and maybe the next one) to generate a NOP.
7464 In any case close it off with a .fill 0. */
7466 static int count_insns_to_loop_end (fragS
*, bfd_boolean
, int);
7467 static bfd_boolean
branch_before_loop_end (fragS
*);
7470 xtensa_fix_short_loop_frags (void)
7475 /* When this routine is called, all of the subsections are still intact
7476 so we walk over subsections instead of sections. */
7477 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7478 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7481 fragS
*current_target
= NULL
;
7482 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
7484 /* Walk over all of the fragments in a subsection. */
7485 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7487 if (fragP
->fr_type
== rs_machine_dependent
7488 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7489 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7492 fragS
*loop_frag
= next_non_empty_frag (fragP
);
7493 tinsn_from_chars (&t_insn
, loop_frag
->fr_opcode
, 0);
7494 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7495 current_opcode
= t_insn
.opcode
;
7496 assert (xtensa_opcode_is_loop (xtensa_default_isa
,
7497 current_opcode
) == 1);
7500 if (fragP
->fr_type
== rs_machine_dependent
7501 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7503 if (count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3) < 3
7504 && (branch_before_loop_end (fragP
->fr_next
)
7505 || (workaround_all_short_loops
7506 && current_opcode
!= XTENSA_UNDEFINED
7507 && current_opcode
!= xtensa_loop_opcode
)))
7509 if (fragP
->tc_frag_data
.is_no_transform
)
7510 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
7512 relax_frag_add_nop (fragP
);
7521 static int unrelaxed_frag_min_insn_count (fragS
*);
7524 count_insns_to_loop_end (fragS
*base_fragP
,
7525 bfd_boolean count_relax_add
,
7528 fragS
*fragP
= NULL
;
7533 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
7535 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
7536 if (insn_count
>= max_count
)
7539 if (count_relax_add
)
7541 if (fragP
->fr_type
== rs_machine_dependent
7542 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7544 /* In order to add the appropriate number of
7545 NOPs, we count an instruction for downstream
7548 if (insn_count
>= max_count
)
7558 unrelaxed_frag_min_insn_count (fragS
*fragP
)
7560 xtensa_isa isa
= xtensa_default_isa
;
7561 static xtensa_insnbuf insnbuf
= NULL
;
7565 if (!fragP
->tc_frag_data
.is_insn
)
7569 insnbuf
= xtensa_insnbuf_alloc (isa
);
7571 /* Decode the fixed instructions. */
7572 while (offset
< fragP
->fr_fix
)
7576 xtensa_insnbuf_from_chars
7577 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7578 fmt
= xtensa_format_decode (isa
, insnbuf
);
7580 if (fmt
== XTENSA_UNDEFINED
)
7582 as_fatal (_("undecodable instruction in instruction frag"));
7585 offset
+= xtensa_format_length (isa
, fmt
);
7593 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
7596 branch_before_loop_end (fragS
*base_fragP
)
7600 for (fragP
= base_fragP
;
7601 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
7602 fragP
= fragP
->fr_next
)
7604 if (unrelaxed_frag_has_b_j (fragP
))
7612 unrelaxed_frag_has_b_j (fragS
*fragP
)
7614 static xtensa_insnbuf insnbuf
= NULL
;
7615 xtensa_isa isa
= xtensa_default_isa
;
7618 if (!fragP
->tc_frag_data
.is_insn
)
7622 insnbuf
= xtensa_insnbuf_alloc (isa
);
7624 /* Decode the fixed instructions. */
7625 while (offset
< fragP
->fr_fix
)
7630 xtensa_insnbuf_from_chars
7631 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7632 fmt
= xtensa_format_decode (isa
, insnbuf
);
7633 if (fmt
== XTENSA_UNDEFINED
)
7636 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7638 xtensa_opcode opcode
=
7639 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
7640 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
7641 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
7644 offset
+= xtensa_format_length (isa
, fmt
);
7650 /* Checks to be made after initial assembly but before relaxation. */
7652 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
7653 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
7656 xtensa_sanity_check (void)
7663 as_where (&file_name
, &line
);
7664 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7665 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7669 /* Walk over all of the fragments in a subsection. */
7670 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7672 if (fragP
->fr_type
== rs_machine_dependent
7673 && fragP
->fr_subtype
== RELAX_SLOTS
7674 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7676 static xtensa_insnbuf insnbuf
= NULL
;
7679 if (fragP
->fr_opcode
!= NULL
)
7682 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7683 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7684 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
7686 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7687 t_insn
.opcode
) == 1)
7689 if (is_empty_loop (&t_insn
, fragP
))
7691 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7692 as_bad (_("invalid empty loop"));
7694 if (!is_local_forward_loop (&t_insn
, fragP
))
7696 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7697 as_bad (_("loop target does not follow "
7698 "loop instruction in section"));
7705 new_logical_line (file_name
, line
);
7709 #define LOOP_IMMED_OPN 1
7711 /* Return TRUE if the loop target is the next non-zero fragment. */
7714 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
7716 const expressionS
*expr
;
7720 if (insn
->insn_type
!= ITYPE_INSN
)
7723 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
7726 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7729 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7731 if (expr
->X_op
!= O_symbol
)
7734 symbolP
= expr
->X_add_symbol
;
7738 if (symbol_get_frag (symbolP
) == NULL
)
7741 if (S_GET_VALUE (symbolP
) != 0)
7744 /* Walk through the zero-size fragments from this one. If we find
7745 the target fragment, then this is a zero-size loop. */
7747 for (next_fragP
= fragP
->fr_next
;
7749 next_fragP
= next_fragP
->fr_next
)
7751 if (next_fragP
== symbol_get_frag (symbolP
))
7753 if (next_fragP
->fr_fix
!= 0)
7761 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
7763 const expressionS
*expr
;
7767 if (insn
->insn_type
!= ITYPE_INSN
)
7770 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
7773 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7776 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7778 if (expr
->X_op
!= O_symbol
)
7781 symbolP
= expr
->X_add_symbol
;
7785 if (symbol_get_frag (symbolP
) == NULL
)
7788 /* Walk through fragments until we find the target.
7789 If we do not find the target, then this is an invalid loop. */
7791 for (next_fragP
= fragP
->fr_next
;
7793 next_fragP
= next_fragP
->fr_next
)
7795 if (next_fragP
== symbol_get_frag (symbolP
))
7803 #define XTINFO_NAME "Xtensa_Info"
7804 #define XTINFO_NAMESZ 12
7805 #define XTINFO_TYPE 1
7808 xtensa_add_config_info (void)
7814 info_sec
= subseg_new (".xtensa.info", 0);
7815 bfd_set_section_flags (stdoutput
, info_sec
, SEC_HAS_CONTENTS
| SEC_READONLY
);
7817 data
= xmalloc (100);
7818 sprintf (data
, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n",
7819 XSHAL_USE_ABSOLUTE_LITERALS
, XSHAL_ABI
);
7820 sz
= strlen (data
) + 1;
7822 /* Add enough null terminators to pad to a word boundary. */
7825 while ((sz
& 3) != 0);
7827 /* Follow the standard note section layout:
7828 First write the length of the name string. */
7830 md_number_to_chars (p
, (valueT
) XTINFO_NAMESZ
, 4);
7832 /* Next comes the length of the "descriptor", i.e., the actual data. */
7834 md_number_to_chars (p
, (valueT
) sz
, 4);
7836 /* Write the note type. */
7838 md_number_to_chars (p
, (valueT
) XTINFO_TYPE
, 4);
7840 /* Write the name field. */
7841 p
= frag_more (XTINFO_NAMESZ
);
7842 memcpy (p
, XTINFO_NAME
, XTINFO_NAMESZ
);
7844 /* Finally, write the descriptor. */
7846 memcpy (p
, data
, sz
);
7852 /* Alignment Functions. */
7855 get_text_align_power (unsigned target_size
)
7857 if (target_size
<= 4)
7859 assert (target_size
== 8);
7865 get_text_align_max_fill_size (int align_pow
,
7866 bfd_boolean use_nops
,
7867 bfd_boolean use_no_density
)
7870 return (1 << align_pow
);
7872 return 3 * (1 << align_pow
);
7874 return 1 + (1 << align_pow
);
7878 /* Calculate the minimum bytes of fill needed at "address" to align a
7879 target instruction of size "target_size" so that it does not cross a
7880 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE,
7881 the fill can be an arbitrary number of bytes. Otherwise, the space must
7882 be filled by NOP instructions. */
7885 get_text_align_fill_size (addressT address
,
7888 bfd_boolean use_nops
,
7889 bfd_boolean use_no_density
)
7891 addressT alignment
, fill
, fill_limit
, fill_step
;
7892 bfd_boolean skip_one
= FALSE
;
7894 alignment
= (1 << align_pow
);
7895 assert (target_size
> 0 && alignment
>= (addressT
) target_size
);
7899 fill_limit
= alignment
;
7902 else if (!use_no_density
)
7904 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */
7905 fill_limit
= alignment
* 2;
7911 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */
7912 fill_limit
= alignment
* 3;
7916 /* Try all fill sizes until finding one that works. */
7917 for (fill
= 0; fill
< fill_limit
; fill
+= fill_step
)
7919 if (skip_one
&& fill
== 1)
7921 if ((address
+ fill
) >> align_pow
7922 == (address
+ fill
+ target_size
- 1) >> align_pow
)
7931 branch_align_power (segT sec
)
7933 /* If the Xtensa processor has a fetch width of 8 bytes, and the section
7934 is aligned to at least an 8-byte boundary, then a branch target need
7935 only fit within an 8-byte aligned block of memory to avoid a stall.
7936 Otherwise, try to fit branch targets within 4-byte aligned blocks
7937 (which may be insufficient, e.g., if the section has no alignment, but
7938 it's good enough). */
7939 if (xtensa_fetch_width
== 8)
7941 if (get_recorded_alignment (sec
) >= 3)
7945 assert (xtensa_fetch_width
== 4);
7951 /* This will assert if it is not possible. */
7954 get_text_align_nop_count (offsetT fill_size
, bfd_boolean use_no_density
)
7960 assert (fill_size
% 3 == 0);
7961 return (fill_size
/ 3);
7964 assert (fill_size
!= 1); /* Bad argument. */
7966 while (fill_size
> 1)
7969 if (fill_size
== 2 || fill_size
== 4)
7971 fill_size
-= insn_size
;
7974 assert (fill_size
!= 1); /* Bad algorithm. */
7980 get_text_align_nth_nop_size (offsetT fill_size
,
7982 bfd_boolean use_no_density
)
7989 assert (fill_size
!= 1); /* Bad argument. */
7991 while (fill_size
> 1)
7994 if (fill_size
== 2 || fill_size
== 4)
7996 fill_size
-= insn_size
;
8006 /* For the given fragment, find the appropriate address
8007 for it to begin at if we are using NOPs to align it. */
8010 get_noop_aligned_address (fragS
*fragP
, addressT address
)
8012 /* The rule is: get next fragment's FIRST instruction. Find
8013 the smallest number of bytes that need to be added to
8014 ensure that the next fragment's FIRST instruction will fit
8017 E.G., 2 bytes : 0, 1, 2 mod 4
8020 If the FIRST instruction MIGHT be relaxed,
8021 assume that it will become a 3-byte instruction.
8023 Note again here that LOOP instructions are not bundleable,
8024 and this relaxation only applies to LOOP opcodes. */
8027 int first_insn_size
;
8029 addressT pre_opcode_bytes
;
8032 xtensa_opcode opcode
;
8033 bfd_boolean is_loop
;
8035 assert (fragP
->fr_type
== rs_machine_dependent
);
8036 assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
8038 /* Find the loop frag. */
8039 first_insn
= next_non_empty_frag (fragP
);
8040 /* Now find the first insn frag. */
8041 first_insn
= next_non_empty_frag (first_insn
);
8043 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
8045 loop_insn_size
= xg_get_single_size (opcode
);
8047 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
8048 pre_opcode_bytes
+= loop_insn_size
;
8050 /* For loops, the alignment depends on the size of the
8051 instruction following the loop, not the LOOP instruction. */
8053 if (first_insn
== NULL
)
8054 first_insn_size
= xtensa_fetch_width
;
8056 first_insn_size
= get_loop_align_size (frag_format_size (first_insn
));
8058 /* If it was 8, then we'll need a larger alignment for the section. */
8059 align_power
= get_text_align_power (first_insn_size
);
8060 record_alignment (now_seg
, align_power
);
8062 fill_size
= get_text_align_fill_size
8063 (address
+ pre_opcode_bytes
, align_power
, first_insn_size
, TRUE
,
8064 fragP
->tc_frag_data
.is_no_density
);
8066 return address
+ fill_size
;
8070 /* 3 mechanisms for relaxing an alignment:
8072 Align to a power of 2.
8073 Align so the next fragment's instruction does not cross a word boundary.
8074 Align the current instruction so that if the next instruction
8075 were 3 bytes, it would not cross a word boundary.
8079 zeros - This is easy; always insert zeros.
8080 nops - 3-byte and 2-byte instructions
8084 >=5 : 3-byte instruction + fn (n-3)
8085 widening - widen previous instructions. */
8088 get_aligned_diff (fragS
*fragP
, addressT address
, offsetT
*max_diff
)
8090 addressT target_address
, loop_insn_offset
;
8092 xtensa_opcode loop_opcode
;
8093 bfd_boolean is_loop
;
8096 offsetT branch_align
;
8098 assert (fragP
->fr_type
== rs_machine_dependent
);
8099 switch (fragP
->fr_subtype
)
8101 case RELAX_DESIRE_ALIGN
:
8102 target_size
= next_frag_format_size (fragP
);
8103 if (target_size
== XTENSA_UNDEFINED
)
8105 align_power
= branch_align_power (now_seg
);
8106 branch_align
= 1 << align_power
;
8107 /* Don't count on the section alignment being as large as the target. */
8108 if (target_size
> branch_align
)
8109 target_size
= branch_align
;
8110 opt_diff
= get_text_align_fill_size (address
, align_power
,
8111 target_size
, FALSE
, FALSE
);
8113 *max_diff
= (opt_diff
+ branch_align
8114 - (target_size
+ ((address
+ opt_diff
) % branch_align
)));
8115 assert (*max_diff
>= opt_diff
);
8118 case RELAX_ALIGN_NEXT_OPCODE
:
8119 target_size
= get_loop_align_size (next_frag_format_size (fragP
));
8120 loop_insn_offset
= 0;
8121 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
8124 /* If the loop has been expanded then the LOOP instruction
8125 could be at an offset from this fragment. */
8126 if (next_non_empty_frag(fragP
)->tc_frag_data
.slot_subtypes
[0]
8128 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
8130 /* In an ideal world, which is what we are shooting for here,
8131 we wouldn't need to use any NOPs immediately prior to the
8132 LOOP instruction. If this approach fails, relax_frag_loop_align
8133 will call get_noop_aligned_address. */
8135 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
8136 align_power
= get_text_align_power (target_size
),
8137 opt_diff
= get_text_align_fill_size (target_address
, align_power
,
8138 target_size
, FALSE
, FALSE
);
8140 *max_diff
= xtensa_fetch_width
8141 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
8142 - target_size
+ opt_diff
;
8143 assert (*max_diff
>= opt_diff
);
8154 /* md_relax_frag Hook and Helper Functions. */
8156 static long relax_frag_loop_align (fragS
*, long);
8157 static long relax_frag_for_align (fragS
*, long);
8158 static long relax_frag_immed
8159 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
8162 /* Return the number of bytes added to this fragment, given that the
8163 input has been stretched already by "stretch". */
8166 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
8168 xtensa_isa isa
= xtensa_default_isa
;
8169 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
8170 long new_stretch
= 0;
8174 static xtensa_insnbuf vbuf
= NULL
;
8175 int slot
, num_slots
;
8178 as_where (&file_name
, &line
);
8179 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8181 fragP
->tc_frag_data
.unreported_expansion
= 0;
8183 switch (fragP
->fr_subtype
)
8185 case RELAX_ALIGN_NEXT_OPCODE
:
8186 /* Always convert. */
8187 if (fragP
->tc_frag_data
.relax_seen
)
8188 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
8191 case RELAX_LOOP_END
:
8195 case RELAX_LOOP_END_ADD_NOP
:
8196 /* Add a NOP and switch to .fill 0. */
8197 new_stretch
= relax_frag_add_nop (fragP
);
8201 case RELAX_DESIRE_ALIGN
:
8202 /* Do nothing. The narrowing before this frag will either align
8207 case RELAX_LITERAL_FINAL
:
8210 case RELAX_LITERAL_NR
:
8212 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
8213 assert (unreported
== lit_size
);
8214 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
8215 fragP
->fr_var
-= lit_size
;
8216 fragP
->fr_fix
+= lit_size
;
8222 vbuf
= xtensa_insnbuf_alloc (isa
);
8224 xtensa_insnbuf_from_chars
8225 (isa
, vbuf
, (unsigned char *) fragP
->fr_opcode
, 0);
8226 fmt
= xtensa_format_decode (isa
, vbuf
);
8227 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8229 for (slot
= 0; slot
< num_slots
; slot
++)
8231 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
8234 if (fragP
->tc_frag_data
.relax_seen
)
8235 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8239 case RELAX_IMMED_STEP1
:
8240 case RELAX_IMMED_STEP2
:
8241 /* Place the immediate. */
8242 new_stretch
+= relax_frag_immed
8243 (now_seg
, fragP
, stretch
,
8244 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8245 fmt
, slot
, stretched_p
, FALSE
);
8249 /* This is OK; see the note in xg_assemble_vliw_tokens. */
8255 case RELAX_LITERAL_POOL_BEGIN
:
8256 case RELAX_LITERAL_POOL_END
:
8257 case RELAX_MAYBE_UNREACHABLE
:
8258 case RELAX_MAYBE_DESIRE_ALIGN
:
8259 /* No relaxation required. */
8262 case RELAX_FILL_NOP
:
8263 case RELAX_UNREACHABLE
:
8264 if (fragP
->tc_frag_data
.relax_seen
)
8265 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8269 as_bad (_("bad relaxation state"));
8272 /* Tell gas we need another relaxation pass. */
8273 if (! fragP
->tc_frag_data
.relax_seen
)
8275 fragP
->tc_frag_data
.relax_seen
= TRUE
;
8279 new_logical_line (file_name
, line
);
8285 relax_frag_loop_align (fragS
*fragP
, long stretch
)
8287 addressT old_address
, old_next_address
, old_size
;
8288 addressT new_address
, new_next_address
, new_size
;
8291 /* All the frags with relax_frag_for_alignment prior to this one in the
8292 section have been done, hopefully eliminating the need for a NOP here.
8293 But, this will put it in if necessary. */
8295 /* Calculate the old address of this fragment and the next fragment. */
8296 old_address
= fragP
->fr_address
- stretch
;
8297 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
8298 fragP
->tc_frag_data
.text_expansion
[0]);
8299 old_size
= old_next_address
- old_address
;
8301 /* Calculate the new address of this fragment and the next fragment. */
8302 new_address
= fragP
->fr_address
;
8304 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
8305 new_size
= new_next_address
- new_address
;
8307 growth
= new_size
- old_size
;
8309 /* Fix up the text_expansion field and return the new growth. */
8310 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
8315 /* Add a NOP instruction. */
8318 relax_frag_add_nop (fragS
*fragP
)
8320 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
8321 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
8322 assemble_nop (length
, nop_buf
);
8323 fragP
->tc_frag_data
.is_insn
= TRUE
;
8325 if (fragP
->fr_var
< length
)
8327 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP
->fr_var
, length
);
8331 fragP
->fr_fix
+= length
;
8332 fragP
->fr_var
-= length
;
8337 static long future_alignment_required (fragS
*, long);
8340 relax_frag_for_align (fragS
*fragP
, long stretch
)
8342 /* Overview of the relaxation procedure for alignment:
8343 We can widen with NOPs or by widening instructions or by filling
8344 bytes after jump instructions. Find the opportune places and widen
8345 them if necessary. */
8350 assert (fragP
->fr_subtype
== RELAX_FILL_NOP
8351 || fragP
->fr_subtype
== RELAX_UNREACHABLE
8352 || (fragP
->fr_subtype
== RELAX_SLOTS
8353 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
8355 stretch_me
= future_alignment_required (fragP
, stretch
);
8356 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
8362 /* We expanded on a previous pass. Can we shrink now? */
8363 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
8364 if (shrink
<= stretch
&& stretch
> 0)
8366 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8372 /* Below here, diff > 0. */
8373 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8379 /* Return the address of the next frag that should be aligned.
8381 By "address" we mean the address it _would_ be at if there
8382 is no action taken to align it between here and the target frag.
8383 In other words, if no narrows and no fill nops are used between
8384 here and the frag to align, _even_if_ some of the frags we use
8385 to align targets have already expanded on a previous relaxation
8388 Also, count each frag that may be used to help align the target.
8390 Return 0 if there are no frags left in the chain that need to be
8394 find_address_of_next_align_frag (fragS
**fragPP
,
8398 bfd_boolean
*paddable
)
8400 fragS
*fragP
= *fragPP
;
8401 addressT address
= fragP
->fr_address
;
8403 /* Do not reset the counts to 0. */
8407 /* Limit this to a small search. */
8408 if (*widens
>= (int) xtensa_fetch_width
)
8413 address
+= fragP
->fr_fix
;
8415 if (fragP
->fr_type
== rs_fill
)
8416 address
+= fragP
->fr_offset
* fragP
->fr_var
;
8417 else if (fragP
->fr_type
== rs_machine_dependent
)
8419 switch (fragP
->fr_subtype
)
8421 case RELAX_UNREACHABLE
:
8425 case RELAX_FILL_NOP
:
8427 if (!fragP
->tc_frag_data
.is_no_density
)
8432 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8437 address
+= total_frag_text_expansion (fragP
);;
8441 address
+= fragP
->tc_frag_data
.text_expansion
[0];
8444 case RELAX_ALIGN_NEXT_OPCODE
:
8445 case RELAX_DESIRE_ALIGN
:
8449 case RELAX_MAYBE_UNREACHABLE
:
8450 case RELAX_MAYBE_DESIRE_ALIGN
:
8455 /* Just punt if we don't know the type. */
8462 /* Just punt if we don't know the type. */
8466 fragP
= fragP
->fr_next
;
8474 static long bytes_to_stretch (fragS
*, int, int, int, int);
8477 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
8479 fragS
*this_frag
= fragP
;
8483 int narrow_nops
= 0;
8484 bfd_boolean paddable
= FALSE
;
8485 offsetT local_opt_diff
;
8488 int stretch_amount
= 0;
8489 int local_stretch_amount
;
8490 int global_stretch_amount
;
8492 address
= find_address_of_next_align_frag
8493 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
8497 if (this_frag
->tc_frag_data
.is_aligning_branch
)
8498 this_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
8500 frag_wane (this_frag
);
8504 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
8505 opt_diff
= local_opt_diff
;
8506 assert (opt_diff
>= 0);
8507 assert (max_diff
>= opt_diff
);
8512 fragP
= fragP
->fr_next
;
8514 while (fragP
&& opt_diff
< max_diff
&& address
)
8516 /* We only use these to determine if we can exit early
8517 because there will be plenty of ways to align future
8519 int glob_widens
= 0;
8522 bfd_boolean glob_pad
= 0;
8523 address
= find_address_of_next_align_frag
8524 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
8525 /* If there is a padable portion, then skip. */
8526 if (glob_pad
|| glob_widens
>= (1 << branch_align_power (now_seg
)))
8531 offsetT next_m_diff
;
8532 offsetT next_o_diff
;
8534 /* Downrange frags haven't had stretch added to them yet. */
8537 /* The address also includes any text expansion from this
8538 frag in a previous pass, but we don't want that. */
8539 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
8541 /* Assume we are going to move at least opt_diff. In
8542 reality, we might not be able to, but assuming that
8543 we will helps catch cases where moving opt_diff pushes
8544 the next target from aligned to unaligned. */
8545 address
+= opt_diff
;
8547 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
8549 /* Now cleanup for the adjustments to address. */
8550 next_o_diff
+= opt_diff
;
8551 next_m_diff
+= opt_diff
;
8552 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
8553 opt_diff
= next_o_diff
;
8554 if (next_m_diff
< max_diff
)
8555 max_diff
= next_m_diff
;
8556 fragP
= fragP
->fr_next
;
8560 /* If there are enough wideners in between, do it. */
8563 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
8565 assert (opt_diff
<= UNREACHABLE_MAX_WIDTH
);
8570 local_stretch_amount
8571 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8572 num_widens
, local_opt_diff
);
8573 global_stretch_amount
8574 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8575 num_widens
, opt_diff
);
8576 /* If the condition below is true, then the frag couldn't
8577 stretch the correct amount for the global case, so we just
8578 optimize locally. We'll rely on the subsequent frags to get
8579 the correct alignment in the global case. */
8580 if (global_stretch_amount
< local_stretch_amount
)
8581 stretch_amount
= local_stretch_amount
;
8583 stretch_amount
= global_stretch_amount
;
8585 if (this_frag
->fr_subtype
== RELAX_SLOTS
8586 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8587 assert (stretch_amount
<= 1);
8588 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8590 if (this_frag
->tc_frag_data
.is_no_density
)
8591 assert (stretch_amount
== 3 || stretch_amount
== 0);
8593 assert (stretch_amount
<= 3);
8596 return stretch_amount
;
8600 /* The idea: widen everything you can to get a target or loop aligned,
8601 then start using NOPs.
8603 When we must have a NOP, here is a table of how we decide
8604 (so you don't have to fight through the control flow below):
8606 wide_nops = the number of wide NOPs available for aligning
8607 narrow_nops = the number of narrow NOPs available for aligning
8608 (a subset of wide_nops)
8609 widens = the number of narrow instructions that should be widened
8616 b 0 1 1 (case 3a makes this case unnecessary)
8619 c 0 1 2 (case 4a makes this case unnecessary)
8622 c 0 2 1 (case 5b makes this case unnecessary)
8625 c 0 1 4 (case 6b makes this case unnecessary)
8626 d 1 1 1 (case 6a makes this case unnecessary)
8627 e 0 2 2 (case 6a makes this case unnecessary)
8628 f 0 3 0 (case 6a makes this case unnecessary)
8631 c 1 1 2 (case 7b makes this case unnecessary)
8632 d 0 1 5 (case 7a makes this case unnecessary)
8633 e 0 2 3 (case 7b makes this case unnecessary)
8634 f 0 3 1 (case 7b makes this case unnecessary)
8635 g 1 2 1 (case 7b makes this case unnecessary)
8639 bytes_to_stretch (fragS
*this_frag
,
8645 int bytes_short
= desired_diff
- num_widens
;
8647 assert (desired_diff
>= 0 && desired_diff
< 8);
8648 if (desired_diff
== 0)
8651 assert (wide_nops
> 0 || num_widens
> 0);
8653 /* Always prefer widening to NOP-filling. */
8654 if (bytes_short
< 0)
8656 /* There are enough RELAX_NARROW frags after this one
8657 to align the target without widening this frag in any way. */
8661 if (bytes_short
== 0)
8663 /* Widen every narrow between here and the align target
8664 and the align target will be properly aligned. */
8665 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8671 /* From here we will need at least one NOP to get an alignment.
8672 However, we may not be able to align at all, in which case,
8674 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8676 switch (desired_diff
)
8681 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 1)
8682 return 2; /* case 2 */
8688 return 3; /* case 3a */
8690 if (num_widens
>= 1 && wide_nops
== 1)
8691 return 3; /* case 4a */
8692 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 2)
8693 return 2; /* case 4b */
8696 if (num_widens
>= 2 && wide_nops
== 1)
8697 return 3; /* case 5a */
8698 /* We will need two nops. Are there enough nops
8699 between here and the align target? */
8700 if (wide_nops
< 2 || narrow_nops
== 0)
8702 /* Are there other nops closer that can serve instead? */
8703 if (wide_nops
> 2 && narrow_nops
> 1)
8705 /* Take the density one first, because there might not be
8706 another density one available. */
8707 if (!this_frag
->tc_frag_data
.is_no_density
)
8708 return 2; /* case 5b narrow */
8710 return 3; /* case 5b wide */
8714 return 3; /* case 6a */
8715 else if (num_widens
>= 3 && wide_nops
== 1)
8716 return 3; /* case 6b */
8719 if (wide_nops
== 1 && num_widens
>= 4)
8720 return 3; /* case 7a */
8721 else if (wide_nops
== 2 && num_widens
>= 1)
8722 return 3; /* case 7b */
8730 /* We will need a NOP no matter what, but should we widen
8731 this instruction to help?
8733 This is a RELAX_NARROW frag. */
8734 switch (desired_diff
)
8743 if (wide_nops
>= 1 && num_widens
== 1)
8744 return 1; /* case 4a */
8747 if (wide_nops
>= 1 && num_widens
== 2)
8748 return 1; /* case 5a */
8752 return 0; /* case 6a */
8753 else if (wide_nops
>= 1 && num_widens
== 3)
8754 return 1; /* case 6b */
8757 if (wide_nops
>= 1 && num_widens
== 4)
8758 return 1; /* case 7a */
8759 else if (wide_nops
>= 2 && num_widens
== 1)
8760 return 1; /* case 7b */
8773 relax_frag_immed (segT segP
,
8780 bfd_boolean estimate_only
)
8784 bfd_boolean negatable_branch
= FALSE
;
8785 bfd_boolean branch_jmp_to_next
= FALSE
;
8786 bfd_boolean wide_insn
= FALSE
;
8787 xtensa_isa isa
= xtensa_default_isa
;
8789 offsetT frag_offset
;
8792 int num_text_bytes
, num_literal_bytes
;
8793 int literal_diff
, total_text_diff
, this_text_diff
, first
;
8795 assert (fragP
->fr_opcode
!= NULL
);
8797 xg_clear_vinsn (&cur_vinsn
);
8798 vinsn_from_chars (&cur_vinsn
, fragP
->fr_opcode
);
8799 if (cur_vinsn
.num_slots
> 1)
8802 tinsn
= cur_vinsn
.slots
[slot
];
8803 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
8805 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
) == 1)
8808 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
8809 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
8811 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
8813 old_size
= xtensa_format_length (isa
, fmt
);
8815 /* Special case: replace a branch to the next instruction with a NOP.
8816 This is required to work around a hardware bug in T1040.0 and also
8817 serves as an optimization. */
8819 if (branch_jmp_to_next
8820 && ((old_size
== 2) || (old_size
== 3))
8821 && !next_frag_is_loop_target (fragP
))
8824 /* Here is the fun stuff: Get the immediate field from this
8825 instruction. If it fits, we are done. If not, find the next
8826 instruction sequence that fits. */
8828 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
8829 istack_init (&istack
);
8830 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
8831 min_steps
, stretch
);
8832 if (num_steps
< min_steps
)
8834 as_fatal (_("internal error: relaxation failed"));
8838 if (num_steps
> RELAX_IMMED_MAXSTEPS
)
8840 as_fatal (_("internal error: relaxation requires too many steps"));
8844 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
8846 /* Figure out the number of bytes needed. */
8848 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
8850 num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
8852 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
8854 num_text_bytes
= get_num_stack_text_bytes (&istack
);
8857 num_text_bytes
+= old_size
;
8858 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
8859 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
8861 total_text_diff
= num_text_bytes
- old_size
;
8862 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
8864 /* It MUST get larger. If not, we could get an infinite loop. */
8865 assert (num_text_bytes
>= 0);
8866 assert (literal_diff
>= 0);
8867 assert (total_text_diff
>= 0);
8869 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
8870 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
8871 assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
8872 assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
8874 /* Find the associated expandable literal for this. */
8875 if (literal_diff
!= 0)
8877 lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
8880 assert (literal_diff
== 4);
8881 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
8883 /* We expect that the literal section state has NOT been
8885 assert (lit_fragP
->fr_type
== rs_machine_dependent
8886 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
8887 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
8889 /* We need to mark this section for another iteration
8895 if (negatable_branch
&& istack
.ninsn
> 1)
8896 update_next_frag_state (fragP
);
8898 return this_text_diff
;
8902 /* md_convert_frag Hook and Helper Functions. */
8904 static void convert_frag_align_next_opcode (fragS
*);
8905 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
8906 static void convert_frag_fill_nop (fragS
*);
8907 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
8910 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
8912 static xtensa_insnbuf vbuf
= NULL
;
8913 xtensa_isa isa
= xtensa_default_isa
;
8920 as_where (&file_name
, &line
);
8921 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
8923 switch (fragp
->fr_subtype
)
8925 case RELAX_ALIGN_NEXT_OPCODE
:
8926 /* Always convert. */
8927 convert_frag_align_next_opcode (fragp
);
8930 case RELAX_DESIRE_ALIGN
:
8931 /* Do nothing. If not aligned already, too bad. */
8935 case RELAX_LITERAL_FINAL
:
8940 vbuf
= xtensa_insnbuf_alloc (isa
);
8942 xtensa_insnbuf_from_chars
8943 (isa
, vbuf
, (unsigned char *) fragp
->fr_opcode
, 0);
8944 fmt
= xtensa_format_decode (isa
, vbuf
);
8945 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8947 for (slot
= 0; slot
< num_slots
; slot
++)
8949 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
8952 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
8956 case RELAX_IMMED_STEP1
:
8957 case RELAX_IMMED_STEP2
:
8958 /* Place the immediate. */
8961 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8966 /* This is OK because some slots could have
8967 relaxations and others have none. */
8973 case RELAX_UNREACHABLE
:
8974 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
8975 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
8976 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
8980 case RELAX_MAYBE_UNREACHABLE
:
8981 case RELAX_MAYBE_DESIRE_ALIGN
:
8985 case RELAX_FILL_NOP
:
8986 convert_frag_fill_nop (fragp
);
8989 case RELAX_LITERAL_NR
:
8990 if (use_literal_section
)
8992 /* This should have been handled during relaxation. When
8993 relaxing a code segment, literals sometimes need to be
8994 added to the corresponding literal segment. If that
8995 literal segment has already been relaxed, then we end up
8996 in this situation. Marking the literal segments as data
8997 would make this happen less often (since GAS always relaxes
8998 code before data), but we could still get into trouble if
8999 there are instructions in a segment that is not marked as
9000 containing code. Until we can implement a better solution,
9001 cheat and adjust the addresses of all the following frags.
9002 This could break subsequent alignments, but the linker's
9003 literal coalescing will do that anyway. */
9006 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
9007 assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
9008 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
9011 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
9015 as_bad (_("invalid relaxation fragment result"));
9020 new_logical_line (file_name
, line
);
9025 convert_frag_align_next_opcode (fragS
*fragp
)
9027 char *nop_buf
; /* Location for Writing. */
9028 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
9029 addressT aligned_address
;
9033 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
9035 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
9036 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
9037 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
9039 for (nop
= 0; nop
< nop_count
; nop
++)
9042 nop_size
= get_text_align_nth_nop_size (fill_size
, nop
, use_no_density
);
9044 assemble_nop (nop_size
, nop_buf
);
9045 nop_buf
+= nop_size
;
9048 fragp
->fr_fix
+= fill_size
;
9049 fragp
->fr_var
-= fill_size
;
9054 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
9056 TInsn tinsn
, single_target
;
9057 int size
, old_size
, diff
;
9058 offsetT frag_offset
;
9061 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
9063 if (fragP
->tc_frag_data
.is_aligning_branch
== 1)
9065 assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
9066 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
9067 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
9072 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
9074 /* No conversion. */
9079 assert (fragP
->fr_opcode
!= NULL
);
9081 /* Frags in this relaxation state should only contain
9082 single instruction bundles. */
9083 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
9085 /* Just convert it to a wide form.... */
9087 old_size
= xg_get_single_size (tinsn
.opcode
);
9089 tinsn_init (&single_target
);
9090 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9092 if (! xg_is_single_relaxable_insn (&tinsn
, &single_target
, FALSE
))
9094 as_bad (_("unable to widen instruction"));
9098 size
= xg_get_single_size (single_target
.opcode
);
9099 xg_emit_insn_to_buf (&single_target
, fragP
->fr_opcode
, fragP
,
9102 diff
= size
- old_size
;
9104 assert (diff
<= fragP
->fr_var
);
9105 fragP
->fr_var
-= diff
;
9106 fragP
->fr_fix
+= diff
;
9114 convert_frag_fill_nop (fragS
*fragP
)
9116 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
9117 int size
= fragP
->tc_frag_data
.text_expansion
[0];
9118 assert ((unsigned) size
== (fragP
->fr_next
->fr_address
9119 - fragP
->fr_address
- fragP
->fr_fix
));
9122 /* No conversion. */
9126 assemble_nop (size
, loc
);
9127 fragP
->tc_frag_data
.is_insn
= TRUE
;
9128 fragP
->fr_var
-= size
;
9129 fragP
->fr_fix
+= size
;
9134 static fixS
*fix_new_exp_in_seg
9135 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
9136 bfd_reloc_code_real_type
);
9137 static void convert_frag_immed_finish_loop (segT
, fragS
*, TInsn
*);
9140 convert_frag_immed (segT segP
,
9146 char *immed_instr
= fragP
->fr_opcode
;
9148 bfd_boolean expanded
= FALSE
;
9149 bfd_boolean branch_jmp_to_next
= FALSE
;
9150 char *fr_opcode
= fragP
->fr_opcode
;
9151 xtensa_isa isa
= xtensa_default_isa
;
9152 bfd_boolean wide_insn
= FALSE
;
9154 bfd_boolean is_loop
;
9156 assert (fr_opcode
!= NULL
);
9158 xg_clear_vinsn (&cur_vinsn
);
9160 vinsn_from_chars (&cur_vinsn
, fr_opcode
);
9161 if (cur_vinsn
.num_slots
> 1)
9164 orig_tinsn
= cur_vinsn
.slots
[slot
];
9165 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
9167 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
9169 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9170 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
9172 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
9174 /* Conversion just inserts a NOP and marks the fix as completed. */
9175 bytes
= xtensa_format_length (isa
, fmt
);
9178 cur_vinsn
.slots
[slot
].opcode
=
9179 xtensa_format_slot_nop_opcode (isa
, cur_vinsn
.format
, slot
);
9180 cur_vinsn
.slots
[slot
].ntok
= 0;
9184 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
9185 assert (bytes
== 2 || bytes
== 3);
9186 build_nop (&cur_vinsn
.slots
[0], bytes
);
9187 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
9189 vinsn_to_insnbuf (&cur_vinsn
, fr_opcode
, frag_now
, TRUE
);
9190 xtensa_insnbuf_to_chars
9191 (isa
, cur_vinsn
.insnbuf
, (unsigned char *) fr_opcode
, 0);
9196 /* Here is the fun stuff: Get the immediate field from this
9197 instruction. If it fits, we're done. If not, find the next
9198 instruction sequence that fits. */
9202 symbolS
*lit_sym
= NULL
;
9204 int target_offset
= 0;
9207 symbolS
*gen_label
= NULL
;
9208 offsetT frag_offset
;
9209 bfd_boolean first
= TRUE
;
9210 bfd_boolean last_is_jump
;
9212 /* It does not fit. Find something that does and
9213 convert immediately. */
9214 frag_offset
= fr_opcode
- fragP
->fr_literal
;
9215 istack_init (&istack
);
9216 xg_assembly_relax (&istack
, &orig_tinsn
,
9217 segP
, fragP
, frag_offset
, min_steps
, 0);
9219 old_size
= xtensa_format_length (isa
, fmt
);
9221 /* Assemble this right inline. */
9223 /* First, create the mapping from a label name to the REAL label. */
9225 for (i
= 0; i
< istack
.ninsn
; i
++)
9227 TInsn
*tinsn
= &istack
.insn
[i
];
9230 switch (tinsn
->insn_type
)
9233 if (lit_sym
!= NULL
)
9234 as_bad (_("multiple literals in expansion"));
9235 /* First find the appropriate space in the literal pool. */
9236 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9237 if (lit_frag
== NULL
)
9238 as_bad (_("no registered fragment for literal"));
9239 if (tinsn
->ntok
!= 1)
9240 as_bad (_("number of literal tokens != 1"));
9242 /* Set the literal symbol and add a fixup. */
9243 lit_sym
= lit_frag
->fr_symbol
;
9247 if (align_targets
&& !is_loop
)
9249 fragS
*unreach
= fragP
->fr_next
;
9250 while (!(unreach
->fr_type
== rs_machine_dependent
9251 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9252 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
9254 unreach
= unreach
->fr_next
;
9257 assert (unreach
->fr_type
== rs_machine_dependent
9258 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9259 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
9261 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
9263 assert (gen_label
== NULL
);
9264 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
9265 fr_opcode
- fragP
->fr_literal
9266 + target_offset
, fragP
);
9270 if (first
&& wide_insn
)
9272 target_offset
+= xtensa_format_length (isa
, fmt
);
9274 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9275 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9278 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9285 last_is_jump
= FALSE
;
9286 for (i
= 0; i
< istack
.ninsn
; i
++)
9288 TInsn
*tinsn
= &istack
.insn
[i
];
9292 bfd_reloc_code_real_type reloc_type
;
9294 switch (tinsn
->insn_type
)
9297 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9298 /* Already checked. */
9299 assert (lit_frag
!= NULL
);
9300 assert (lit_sym
!= NULL
);
9301 assert (tinsn
->ntok
== 1);
9303 target_seg
= S_GET_SEGMENT (lit_sym
);
9304 assert (target_seg
);
9305 if (tinsn
->tok
[0].X_op
== O_pltrel
)
9306 reloc_type
= BFD_RELOC_XTENSA_PLT
;
9308 reloc_type
= BFD_RELOC_32
;
9309 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
9310 &tinsn
->tok
[0], FALSE
, reloc_type
);
9317 xg_resolve_labels (tinsn
, gen_label
);
9318 xg_resolve_literals (tinsn
, lit_sym
);
9319 if (wide_insn
&& first
)
9322 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9324 cur_vinsn
.slots
[slot
] = *tinsn
;
9328 cur_vinsn
.slots
[slot
].opcode
=
9329 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
9330 cur_vinsn
.slots
[slot
].ntok
= 0;
9332 vinsn_to_insnbuf (&cur_vinsn
, immed_instr
, fragP
, TRUE
);
9333 xtensa_insnbuf_to_chars (isa
, cur_vinsn
.insnbuf
,
9334 (unsigned char *) immed_instr
, 0);
9335 fragP
->tc_frag_data
.is_insn
= TRUE
;
9336 size
= xtensa_format_length (isa
, fmt
);
9337 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9340 (tinsn
, immed_instr
+ size
, fragP
,
9341 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
9342 size
+= xg_get_single_size (tinsn
->opcode
);
9347 size
= xg_get_single_size (tinsn
->opcode
);
9348 xg_emit_insn_to_buf (tinsn
, immed_instr
, fragP
,
9349 immed_instr
- fragP
->fr_literal
, TRUE
);
9351 immed_instr
+= size
;
9357 diff
= total_size
- old_size
;
9361 assert (diff
<= fragP
->fr_var
);
9362 fragP
->fr_var
-= diff
;
9363 fragP
->fr_fix
+= diff
;
9366 /* Check for undefined immediates in LOOP instructions. */
9370 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
9371 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9373 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9376 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
9377 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9379 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9384 if (expanded
&& xtensa_opcode_is_loop (isa
, orig_tinsn
.opcode
) == 1)
9385 convert_frag_immed_finish_loop (segP
, fragP
, &orig_tinsn
);
9387 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
9389 /* Add an expansion note on the expanded instruction. */
9390 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
9391 &orig_tinsn
.tok
[0], TRUE
,
9392 BFD_RELOC_XTENSA_ASM_EXPAND
);
9397 /* Add a new fix expression into the desired segment. We have to
9398 switch to that segment to do this. */
9401 fix_new_exp_in_seg (segT new_seg
,
9408 bfd_reloc_code_real_type r_type
)
9412 subsegT subseg
= now_subseg
;
9414 assert (new_seg
!= 0);
9415 subseg_set (new_seg
, new_subseg
);
9417 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
9418 subseg_set (seg
, subseg
);
9423 /* Relax a loop instruction so that it can span loop >256 bytes.
9429 addi as, as, lo8 (label-.L1)
9430 addmi as, as, mid8 (label-.L1)
9441 convert_frag_immed_finish_loop (segT segP
, fragS
*fragP
, TInsn
*tinsn
)
9446 unsigned long target
;
9447 static xtensa_insnbuf insnbuf
= NULL
;
9448 unsigned int loop_length
, loop_length_hi
, loop_length_lo
;
9449 xtensa_isa isa
= xtensa_default_isa
;
9450 addressT loop_offset
;
9451 addressT addi_offset
= 9;
9452 addressT addmi_offset
= 12;
9457 insnbuf
= xtensa_insnbuf_alloc (isa
);
9459 /* Get the loop offset. */
9460 loop_offset
= get_expanded_loop_offset (tinsn
->opcode
);
9462 /* Validate that there really is a LOOP at the loop_offset. Because
9463 loops are not bundleable, we can assume that the instruction will be
9465 tinsn_from_chars (&loop_insn
, fragP
->fr_opcode
+ loop_offset
, 0);
9466 tinsn_immed_from_frag (&loop_insn
, fragP
, 0);
9468 assert (xtensa_opcode_is_loop (isa
, loop_insn
.opcode
) == 1);
9469 addi_offset
+= loop_offset
;
9470 addmi_offset
+= loop_offset
;
9472 assert (tinsn
->ntok
== 2);
9473 if (tinsn
->tok
[1].X_op
== O_constant
)
9474 target
= tinsn
->tok
[1].X_add_number
;
9475 else if (tinsn
->tok
[1].X_op
== O_symbol
)
9477 /* Find the fragment. */
9478 symbolS
*sym
= tinsn
->tok
[1].X_add_symbol
;
9479 assert (S_GET_SEGMENT (sym
) == segP
9480 || S_GET_SEGMENT (sym
) == absolute_section
);
9481 target
= (S_GET_VALUE (sym
) + tinsn
->tok
[1].X_add_number
);
9485 as_bad (_("invalid expression evaluation type %d"), tinsn
->tok
[1].X_op
);
9490 know (symbolP
->sy_frag
);
9491 know (!(S_GET_SEGMENT (symbolP
) == absolute_section
)
9492 || symbol_get_frag (symbolP
) == &zero_address_frag
);
9494 loop_length
= target
- (fragP
->fr_address
+ fragP
->fr_fix
);
9495 loop_length_hi
= loop_length
& ~0x0ff;
9496 loop_length_lo
= loop_length
& 0x0ff;
9497 if (loop_length_lo
>= 128)
9499 loop_length_lo
-= 256;
9500 loop_length_hi
+= 256;
9503 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
9504 32512. If the loop is larger than that, then we just fail. */
9505 if (loop_length_hi
> 32512)
9506 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9507 _("loop too long for LOOP instruction"));
9509 tinsn_from_chars (&addi_insn
, fragP
->fr_opcode
+ addi_offset
, 0);
9510 assert (addi_insn
.opcode
== xtensa_addi_opcode
);
9512 tinsn_from_chars (&addmi_insn
, fragP
->fr_opcode
+ addmi_offset
, 0);
9513 assert (addmi_insn
.opcode
== xtensa_addmi_opcode
);
9515 set_expr_const (&addi_insn
.tok
[2], loop_length_lo
);
9516 tinsn_to_insnbuf (&addi_insn
, insnbuf
);
9518 fragP
->tc_frag_data
.is_insn
= TRUE
;
9519 xtensa_insnbuf_to_chars
9520 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addi_offset
, 0);
9522 set_expr_const (&addmi_insn
.tok
[2], loop_length_hi
);
9523 tinsn_to_insnbuf (&addmi_insn
, insnbuf
);
9524 xtensa_insnbuf_to_chars
9525 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addmi_offset
, 0);
9527 /* Walk through all of the frags from here to the loop end
9528 and mark them as no_transform to keep them from being modified
9529 by the linker. If we ever have a relocation for the
9530 addi/addmi of the difference of two symbols we can remove this. */
9533 for (next_fragP
= fragP
; next_fragP
!= NULL
;
9534 next_fragP
= next_fragP
->fr_next
)
9536 next_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
9537 if (next_fragP
->tc_frag_data
.is_loop_target
)
9539 if (target_count
== 2)
9545 /* A map that keeps information on a per-subsegment basis. This is
9546 maintained during initial assembly, but is invalid once the
9547 subsegments are smashed together. I.E., it cannot be used during
9550 typedef struct subseg_map_struct
9558 float total_freq
; /* fall-through + branch target frequency */
9559 float target_freq
; /* branch target frequency alone */
9561 struct subseg_map_struct
*next
;
9565 static subseg_map
*sseg_map
= NULL
;
9568 get_subseg_info (segT seg
, subsegT subseg
)
9570 subseg_map
*subseg_e
;
9572 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
9574 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
9582 add_subseg_info (segT seg
, subsegT subseg
)
9584 subseg_map
*subseg_e
= (subseg_map
*) xmalloc (sizeof (subseg_map
));
9585 memset (subseg_e
, 0, sizeof (subseg_map
));
9586 subseg_e
->seg
= seg
;
9587 subseg_e
->subseg
= subseg
;
9588 subseg_e
->flags
= 0;
9589 /* Start off considering every branch target very important. */
9590 subseg_e
->target_freq
= 1.0;
9591 subseg_e
->total_freq
= 1.0;
9592 subseg_e
->next
= sseg_map
;
9593 sseg_map
= subseg_e
;
9599 get_last_insn_flags (segT seg
, subsegT subseg
)
9601 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9603 return subseg_e
->flags
;
9609 set_last_insn_flags (segT seg
,
9614 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9616 subseg_e
= add_subseg_info (seg
, subseg
);
9618 subseg_e
->flags
|= fl
;
9620 subseg_e
->flags
&= ~fl
;
9625 get_subseg_total_freq (segT seg
, subsegT subseg
)
9627 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9629 return subseg_e
->total_freq
;
9635 get_subseg_target_freq (segT seg
, subsegT subseg
)
9637 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9639 return subseg_e
->target_freq
;
9645 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
9647 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9649 subseg_e
= add_subseg_info (seg
, subseg
);
9650 subseg_e
->total_freq
= total_f
;
9651 subseg_e
->target_freq
= target_f
;
9655 /* Segment Lists and emit_state Stuff. */
9658 xtensa_move_seg_list_to_beginning (seg_list
*head
)
9663 segT literal_section
= head
->seg
;
9665 /* Move the literal section to the front of the section list. */
9666 assert (literal_section
);
9667 if (literal_section
!= stdoutput
->sections
)
9669 bfd_section_list_remove (stdoutput
, literal_section
);
9670 bfd_section_list_prepend (stdoutput
, literal_section
);
9677 static void mark_literal_frags (seg_list
*);
9680 xtensa_move_literals (void)
9683 frchainS
*frchain_from
, *frchain_to
;
9684 fragS
*search_frag
, *next_frag
, *last_frag
, *literal_pool
, *insert_after
;
9685 fragS
**frag_splice
;
9688 fixS
*fix
, *next_fix
, **fix_splice
;
9691 mark_literal_frags (literal_head
->next
);
9693 if (use_literal_section
)
9696 for (segment
= literal_head
->next
; segment
; segment
= segment
->next
)
9698 /* Keep the literals for .init and .fini in separate sections. */
9699 if (!strcmp (segment_name (segment
->seg
), INIT_SECTION_NAME
)
9700 || !strcmp (segment_name (segment
->seg
), FINI_SECTION_NAME
))
9703 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9704 search_frag
= frchain_from
->frch_root
;
9705 literal_pool
= NULL
;
9707 frag_splice
= &(frchain_from
->frch_root
);
9709 while (!search_frag
->tc_frag_data
.literal_frag
)
9711 assert (search_frag
->fr_fix
== 0
9712 || search_frag
->fr_type
== rs_align
);
9713 search_frag
= search_frag
->fr_next
;
9716 assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
9717 == RELAX_LITERAL_POOL_BEGIN
);
9718 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
9720 /* Make sure that all the frags in this series are closed, and
9721 that there is at least one left over of zero-size. This
9722 prevents us from making a segment with an frchain without any
9724 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9725 xtensa_set_frag_assembly_state (frag_now
);
9726 last_frag
= frag_now
;
9727 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9728 xtensa_set_frag_assembly_state (frag_now
);
9730 while (search_frag
!= frag_now
)
9732 next_frag
= search_frag
->fr_next
;
9734 /* First, move the frag out of the literal section and
9735 to the appropriate place. */
9736 if (search_frag
->tc_frag_data
.literal_frag
)
9738 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
9739 assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
9740 frchain_to
= literal_pool
->tc_frag_data
.lit_frchain
;
9741 assert (frchain_to
);
9743 insert_after
= literal_pool
;
9745 while (insert_after
->fr_next
->fr_subtype
!= RELAX_LITERAL_POOL_END
)
9746 insert_after
= insert_after
->fr_next
;
9748 dest_seg
= insert_after
->fr_next
->tc_frag_data
.lit_seg
;
9750 *frag_splice
= next_frag
;
9751 search_frag
->fr_next
= insert_after
->fr_next
;
9752 insert_after
->fr_next
= search_frag
;
9753 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
9755 /* Now move any fixups associated with this frag to the
9757 fix
= frchain_from
->fix_root
;
9758 fix_splice
= &(frchain_from
->fix_root
);
9761 next_fix
= fix
->fx_next
;
9762 if (fix
->fx_frag
== search_frag
)
9764 *fix_splice
= next_fix
;
9765 fix
->fx_next
= frchain_to
->fix_root
;
9766 frchain_to
->fix_root
= fix
;
9767 if (frchain_to
->fix_tail
== NULL
)
9768 frchain_to
->fix_tail
= fix
;
9771 fix_splice
= &(fix
->fx_next
);
9774 search_frag
= next_frag
;
9777 if (frchain_from
->fix_root
!= NULL
)
9779 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9780 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
9782 assert (frchain_from
->fix_root
== NULL
);
9784 frchain_from
->fix_tail
= NULL
;
9785 xtensa_restore_emit_state (&state
);
9788 /* Now fix up the SEGMENT value for all the literal symbols. */
9789 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
9791 symbolS
*lit_sym
= lit
->sym
;
9792 segT dest_seg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
9794 S_SET_SEGMENT (lit_sym
, dest_seg
);
9799 /* Walk over all the frags for segments in a list and mark them as
9800 containing literals. As clunky as this is, we can't rely on frag_var
9801 and frag_variant to get called in all situations. */
9804 mark_literal_frags (seg_list
*segment
)
9806 frchainS
*frchain_from
;
9811 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9812 search_frag
= frchain_from
->frch_root
;
9815 search_frag
->tc_frag_data
.is_literal
= TRUE
;
9816 search_frag
= search_frag
->fr_next
;
9818 segment
= segment
->next
;
9824 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
9826 /* Move all of the sections in the section list to come
9827 after "after" in the gnu segment list. */
9832 segT literal_section
= head
->seg
;
9834 /* Move the literal section after "after". */
9835 assert (literal_section
);
9836 if (literal_section
!= after
)
9838 bfd_section_list_remove (stdoutput
, literal_section
);
9839 bfd_section_list_insert_after (stdoutput
, after
, literal_section
);
9847 /* Push all the literal segments to the end of the gnu list. */
9850 xtensa_reorder_segments (void)
9857 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
9863 /* Now that we have the last section, push all the literal
9864 sections to the end. */
9865 xtensa_reorder_seg_list (literal_head
, last_sec
);
9867 /* Now perform the final error check. */
9868 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
9870 assert (new_count
== old_count
);
9874 /* Change the emit state (seg, subseg, and frag related stuff) to the
9875 correct location. Return a emit_state which can be passed to
9876 xtensa_restore_emit_state to return to current fragment. */
9879 xtensa_switch_to_literal_fragment (emit_state
*result
)
9881 if (directive_state
[directive_absolute_literals
])
9883 segT lit4_seg
= cache_literal_section (TRUE
);
9884 xtensa_switch_section_emit_state (result
, lit4_seg
, 0);
9887 xtensa_switch_to_non_abs_literal_fragment (result
);
9889 /* Do a 4-byte align here. */
9890 frag_align (2, 0, 0);
9891 record_alignment (now_seg
, 2);
9896 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
9898 static bfd_boolean recursive
= FALSE
;
9899 fragS
*pool_location
= get_literal_pool_location (now_seg
);
9901 bfd_boolean is_init
=
9902 (now_seg
&& !strcmp (segment_name (now_seg
), INIT_SECTION_NAME
));
9903 bfd_boolean is_fini
=
9904 (now_seg
&& !strcmp (segment_name (now_seg
), FINI_SECTION_NAME
));
9906 if (pool_location
== NULL
9907 && !use_literal_section
9909 && !is_init
&& ! is_fini
)
9911 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
9913 /* When we mark a literal pool location, we want to put a frag in
9914 the literal pool that points to it. But to do that, we want to
9915 switch_to_literal_fragment. But literal sections don't have
9916 literal pools, so their location is always null, so we would
9917 recurse forever. This is kind of hacky, but it works. */
9920 xtensa_mark_literal_pool_location ();
9924 lit_seg
= cache_literal_section (FALSE
);
9925 xtensa_switch_section_emit_state (result
, lit_seg
, 0);
9927 if (!use_literal_section
9928 && !is_init
&& !is_fini
9929 && get_literal_pool_location (now_seg
) != pool_location
)
9931 /* Close whatever frag is there. */
9932 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9933 xtensa_set_frag_assembly_state (frag_now
);
9934 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
9935 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9936 xtensa_set_frag_assembly_state (frag_now
);
9941 /* Call this function before emitting data into the literal section.
9942 This is a helper function for xtensa_switch_to_literal_fragment.
9943 This is similar to a .section new_now_seg subseg. */
9946 xtensa_switch_section_emit_state (emit_state
*state
,
9948 subsegT new_now_subseg
)
9950 state
->name
= now_seg
->name
;
9951 state
->now_seg
= now_seg
;
9952 state
->now_subseg
= now_subseg
;
9953 state
->generating_literals
= generating_literals
;
9954 generating_literals
++;
9955 subseg_set (new_now_seg
, new_now_subseg
);
9959 /* Use to restore the emitting into the normal place. */
9962 xtensa_restore_emit_state (emit_state
*state
)
9964 generating_literals
= state
->generating_literals
;
9965 subseg_set (state
->now_seg
, state
->now_subseg
);
9969 /* Predicate function used to look up a section in a particular group. */
9972 match_section_group (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
, void *inf
)
9974 const char *gname
= inf
;
9975 const char *group_name
= elf_group_name (sec
);
9977 return (group_name
== gname
9978 || (group_name
!= NULL
9980 && strcmp (group_name
, gname
) == 0));
9984 /* Get the literal section to be used for the current text section.
9985 The result may be cached in the default_lit_sections structure. */
9988 cache_literal_section (bfd_boolean use_abs_literals
)
9990 const char *text_name
, *group_name
= 0;
9991 char *base_name
, *name
, *suffix
;
9993 segT seg
, current_section
;
9995 bfd_boolean linkonce
= FALSE
;
9997 /* Save the current section/subsection. */
9998 current_section
= now_seg
;
9999 current_subsec
= now_subseg
;
10001 /* Clear the cached values if they are no longer valid. */
10002 if (now_seg
!= default_lit_sections
.current_text_seg
)
10004 default_lit_sections
.current_text_seg
= now_seg
;
10005 default_lit_sections
.lit_seg
= NULL
;
10006 default_lit_sections
.lit4_seg
= NULL
;
10009 /* Check if the literal section is already cached. */
10010 if (use_abs_literals
)
10011 pcached
= &default_lit_sections
.lit4_seg
;
10013 pcached
= &default_lit_sections
.lit_seg
;
10018 text_name
= default_lit_sections
.lit_prefix
;
10019 if (! text_name
|| ! *text_name
)
10021 text_name
= segment_name (current_section
);
10022 group_name
= elf_group_name (current_section
);
10023 linkonce
= (current_section
->flags
& SEC_LINK_ONCE
) != 0;
10026 base_name
= use_abs_literals
? ".lit4" : ".literal";
10029 name
= xmalloc (strlen (base_name
) + strlen (group_name
) + 2);
10030 sprintf (name
, "%s.%s", base_name
, group_name
);
10032 else if (strncmp (text_name
, ".gnu.linkonce.", linkonce_len
) == 0)
10034 suffix
= strchr (text_name
+ linkonce_len
, '.');
10036 name
= xmalloc (linkonce_len
+ strlen (base_name
) + 1
10037 + (suffix
? strlen (suffix
) : 0));
10038 strcpy (name
, ".gnu.linkonce");
10039 strcat (name
, base_name
);
10041 strcat (name
, suffix
);
10046 /* If the section name ends with ".text", then replace that suffix
10047 instead of appending an additional suffix. */
10048 size_t len
= strlen (text_name
);
10049 if (len
>= 5 && strcmp (text_name
+ len
- 5, ".text") == 0)
10052 name
= xmalloc (len
+ strlen (base_name
) + 1);
10053 strcpy (name
, text_name
);
10054 strcpy (name
+ len
, base_name
);
10057 /* Canonicalize section names to allow renaming literal sections.
10058 The group name, if any, came from the current text section and
10059 has already been canonicalized. */
10060 name
= tc_canonicalize_symbol_name (name
);
10062 seg
= bfd_get_section_by_name_if (stdoutput
, name
, match_section_group
,
10063 (void *) group_name
);
10068 seg
= subseg_force_new (name
, 0);
10070 if (! use_abs_literals
)
10072 /* Add the newly created literal segment to the list. */
10073 seg_list
*n
= (seg_list
*) xmalloc (sizeof (seg_list
));
10075 n
->next
= literal_head
->next
;
10076 literal_head
->next
= n
;
10079 flags
= (SEC_HAS_CONTENTS
| SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
10080 | (linkonce
? (SEC_LINK_ONCE
| SEC_LINK_DUPLICATES_DISCARD
) : 0)
10081 | (use_abs_literals
? SEC_DATA
: SEC_CODE
));
10083 elf_group_name (seg
) = group_name
;
10085 bfd_set_section_flags (stdoutput
, seg
, flags
);
10086 bfd_set_section_alignment (stdoutput
, seg
, 2);
10090 subseg_set (current_section
, current_subsec
);
10095 /* Property Tables Stuff. */
10097 #define XTENSA_INSN_SEC_NAME ".xt.insn"
10098 #define XTENSA_LIT_SEC_NAME ".xt.lit"
10099 #define XTENSA_PROP_SEC_NAME ".xt.prop"
10101 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
10102 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
10104 static bfd_boolean
get_frag_is_literal (const fragS
*);
10105 static void xtensa_create_property_segments
10106 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
10107 static void xtensa_create_xproperty_segments
10108 (frag_flags_fn
, const char *, xt_section_type
);
10109 static segment_info_type
*retrieve_segment_info (segT
);
10110 static bfd_boolean
section_has_property (segT
, frag_predicate
);
10111 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
10112 static void add_xt_block_frags
10113 (segT
, segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
10114 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
10115 static void xtensa_frag_flags_init (frag_flags
*);
10116 static void get_frag_property_flags (const fragS
*, frag_flags
*);
10117 static bfd_vma
frag_flags_to_number (const frag_flags
*);
10118 static void add_xt_prop_frags
10119 (segT
, segT
, xtensa_block_info
**, frag_flags_fn
);
10121 /* Set up property tables after relaxation. */
10124 xtensa_post_relax_hook (void)
10126 xtensa_move_seg_list_to_beginning (literal_head
);
10128 xtensa_find_unmarked_state_frags ();
10130 xtensa_create_property_segments (get_frag_is_literal
,
10132 XTENSA_LIT_SEC_NAME
,
10134 xtensa_create_xproperty_segments (get_frag_property_flags
,
10135 XTENSA_PROP_SEC_NAME
,
10138 if (warn_unaligned_branch_targets
)
10139 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
10140 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
10144 /* This function is only meaningful after xtensa_move_literals. */
10147 get_frag_is_literal (const fragS
*fragP
)
10149 assert (fragP
!= NULL
);
10150 return fragP
->tc_frag_data
.is_literal
;
10155 xtensa_create_property_segments (frag_predicate property_function
,
10156 frag_predicate end_property_function
,
10157 const char *section_name_base
,
10158 xt_section_type sec_type
)
10162 /* Walk over all of the current segments.
10163 Walk over each fragment
10164 For each non-empty fragment,
10165 Build a property record (append where possible). */
10167 for (seclist
= &stdoutput
->sections
;
10168 seclist
&& *seclist
;
10169 seclist
= &(*seclist
)->next
)
10171 segT sec
= *seclist
;
10174 flags
= bfd_get_section_flags (stdoutput
, sec
);
10175 if (flags
& SEC_DEBUGGING
)
10177 if (!(flags
& SEC_ALLOC
))
10180 if (section_has_property (sec
, property_function
))
10183 xtensa_get_property_section (sec
, section_name_base
);
10184 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10185 xtensa_block_info
**xt_blocks
=
10186 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10187 /* Walk over all of the frchains here and add new sections. */
10188 add_xt_block_frags (sec
, insn_sec
, xt_blocks
, property_function
,
10189 end_property_function
);
10193 /* Now we fill them out.... */
10195 for (seclist
= &stdoutput
->sections
;
10196 seclist
&& *seclist
;
10197 seclist
= &(*seclist
)->next
)
10199 segment_info_type
*seginfo
;
10200 xtensa_block_info
*block
;
10201 segT sec
= *seclist
;
10203 seginfo
= seg_info (sec
);
10204 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10208 xtensa_block_info
*cur_block
;
10209 /* This is a section with some data. */
10211 bfd_size_type rec_size
;
10213 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10216 rec_size
= num_recs
* 8;
10217 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10219 /* In order to make this work with the assembler, we have to
10220 build some frags and then build the "fixups" for it. It
10221 would be easier to just set the contents then set the
10226 /* Allocate a fragment and leak it. */
10228 bfd_size_type frag_size
;
10230 frchainS
*frchainP
;
10234 frag_size
= sizeof (fragS
) + rec_size
;
10235 fragP
= (fragS
*) xmalloc (frag_size
);
10237 memset (fragP
, 0, frag_size
);
10238 fragP
->fr_address
= 0;
10239 fragP
->fr_next
= NULL
;
10240 fragP
->fr_fix
= rec_size
;
10242 fragP
->fr_type
= rs_fill
;
10243 /* The rest are zeros. */
10245 frchainP
= seginfo
->frchainP
;
10246 frchainP
->frch_root
= fragP
;
10247 frchainP
->frch_last
= fragP
;
10249 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10250 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10252 seginfo
->fix_root
= fixes
;
10253 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10255 frag_data
= &fragP
->fr_literal
[0];
10256 for (i
= 0; i
< num_recs
; i
++)
10258 fixS
*fix
= &fixes
[i
];
10259 assert (cur_block
);
10261 /* Write the fixup. */
10262 if (i
!= num_recs
- 1)
10263 fix
->fx_next
= &fixes
[i
+ 1];
10265 fix
->fx_next
= NULL
;
10268 fix
->fx_frag
= fragP
;
10269 fix
->fx_where
= i
* 8;
10270 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10271 fix
->fx_offset
= cur_block
->offset
;
10272 fix
->fx_r_type
= BFD_RELOC_32
;
10273 fix
->fx_file
= "Internal Assembly";
10276 /* Write the length. */
10277 md_number_to_chars (&frag_data
[4 + 8 * i
],
10278 cur_block
->size
, 4);
10279 cur_block
= cur_block
->next
;
10288 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
10289 const char *section_name_base
,
10290 xt_section_type sec_type
)
10294 /* Walk over all of the current segments.
10295 Walk over each fragment.
10296 For each fragment that has instructions,
10297 build an instruction record (append where possible). */
10299 for (seclist
= &stdoutput
->sections
;
10300 seclist
&& *seclist
;
10301 seclist
= &(*seclist
)->next
)
10303 segT sec
= *seclist
;
10306 flags
= bfd_get_section_flags (stdoutput
, sec
);
10307 if ((flags
& SEC_DEBUGGING
)
10308 || !(flags
& SEC_ALLOC
)
10309 || (flags
& SEC_MERGE
))
10312 if (section_has_xproperty (sec
, flag_fn
))
10315 xtensa_get_property_section (sec
, section_name_base
);
10316 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10317 xtensa_block_info
**xt_blocks
=
10318 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10319 /* Walk over all of the frchains here and add new sections. */
10320 add_xt_prop_frags (sec
, insn_sec
, xt_blocks
, flag_fn
);
10324 /* Now we fill them out.... */
10326 for (seclist
= &stdoutput
->sections
;
10327 seclist
&& *seclist
;
10328 seclist
= &(*seclist
)->next
)
10330 segment_info_type
*seginfo
;
10331 xtensa_block_info
*block
;
10332 segT sec
= *seclist
;
10334 seginfo
= seg_info (sec
);
10335 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10339 xtensa_block_info
*cur_block
;
10340 /* This is a section with some data. */
10342 bfd_size_type rec_size
;
10344 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10347 rec_size
= num_recs
* (8 + 4);
10348 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10350 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
10352 /* In order to make this work with the assembler, we have to build
10353 some frags then build the "fixups" for it. It would be easier to
10354 just set the contents then set the arlents. */
10358 /* Allocate a fragment and (unfortunately) leak it. */
10360 bfd_size_type frag_size
;
10362 frchainS
*frchainP
;
10366 frag_size
= sizeof (fragS
) + rec_size
;
10367 fragP
= (fragS
*) xmalloc (frag_size
);
10369 memset (fragP
, 0, frag_size
);
10370 fragP
->fr_address
= 0;
10371 fragP
->fr_next
= NULL
;
10372 fragP
->fr_fix
= rec_size
;
10374 fragP
->fr_type
= rs_fill
;
10375 /* The rest are zeros. */
10377 frchainP
= seginfo
->frchainP
;
10378 frchainP
->frch_root
= fragP
;
10379 frchainP
->frch_last
= fragP
;
10381 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10382 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10384 seginfo
->fix_root
= fixes
;
10385 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10387 frag_data
= &fragP
->fr_literal
[0];
10388 for (i
= 0; i
< num_recs
; i
++)
10390 fixS
*fix
= &fixes
[i
];
10391 assert (cur_block
);
10393 /* Write the fixup. */
10394 if (i
!= num_recs
- 1)
10395 fix
->fx_next
= &fixes
[i
+ 1];
10397 fix
->fx_next
= NULL
;
10400 fix
->fx_frag
= fragP
;
10401 fix
->fx_where
= i
* (8 + 4);
10402 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10403 fix
->fx_offset
= cur_block
->offset
;
10404 fix
->fx_r_type
= BFD_RELOC_32
;
10405 fix
->fx_file
= "Internal Assembly";
10408 /* Write the length. */
10409 md_number_to_chars (&frag_data
[4 + (8+4) * i
],
10410 cur_block
->size
, 4);
10411 md_number_to_chars (&frag_data
[8 + (8+4) * i
],
10412 frag_flags_to_number (&cur_block
->flags
),
10414 cur_block
= cur_block
->next
;
10422 static segment_info_type
*
10423 retrieve_segment_info (segT seg
)
10425 segment_info_type
*seginfo
;
10426 seginfo
= (segment_info_type
*) bfd_get_section_userdata (stdoutput
, seg
);
10429 frchainS
*frchainP
;
10431 seginfo
= (segment_info_type
*) xmalloc (sizeof (*seginfo
));
10432 memset ((void *) seginfo
, 0, sizeof (*seginfo
));
10433 seginfo
->fix_root
= NULL
;
10434 seginfo
->fix_tail
= NULL
;
10435 seginfo
->bfd_section
= seg
;
10437 /* We will not be dealing with these, only our special ones. */
10438 bfd_set_section_userdata (stdoutput
, seg
, (void *) seginfo
);
10440 frchainP
= (frchainS
*) xmalloc (sizeof (frchainS
));
10441 frchainP
->frch_root
= NULL
;
10442 frchainP
->frch_last
= NULL
;
10443 frchainP
->frch_next
= NULL
;
10444 frchainP
->frch_subseg
= 0;
10445 frchainP
->fix_root
= NULL
;
10446 frchainP
->fix_tail
= NULL
;
10447 /* Do not init the objstack. */
10448 /* obstack_begin (&frchainP->frch_obstack, chunksize); */
10449 /* frchainP->frch_frag_now = fragP; */
10450 frchainP
->frch_frag_now
= NULL
;
10452 seginfo
->frchainP
= frchainP
;
10460 section_has_property (segT sec
, frag_predicate property_function
)
10462 segment_info_type
*seginfo
= seg_info (sec
);
10465 if (seginfo
&& seginfo
->frchainP
)
10467 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10469 if (property_function (fragP
)
10470 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10479 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
10481 segment_info_type
*seginfo
= seg_info (sec
);
10484 if (seginfo
&& seginfo
->frchainP
)
10486 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10488 frag_flags prop_flags
;
10489 property_function (fragP
, &prop_flags
);
10490 if (!xtensa_frag_flags_is_empty (&prop_flags
))
10498 /* Two types of block sections exist right now: literal and insns. */
10501 add_xt_block_frags (segT sec
,
10503 xtensa_block_info
**xt_block
,
10504 frag_predicate property_function
,
10505 frag_predicate end_property_function
)
10507 segment_info_type
*seg_info
;
10508 segment_info_type
*xt_seg_info
;
10509 bfd_vma seg_offset
;
10512 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
10513 seg_info
= retrieve_segment_info (sec
);
10515 /* Build it if needed. */
10516 while (*xt_block
!= NULL
)
10517 xt_block
= &(*xt_block
)->next
;
10518 /* We are either at NULL at the beginning or at the end. */
10520 /* Walk through the frags. */
10523 if (seg_info
->frchainP
)
10525 for (fragP
= seg_info
->frchainP
->frch_root
;
10527 fragP
= fragP
->fr_next
)
10529 if (property_function (fragP
)
10530 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10532 if (*xt_block
!= NULL
)
10534 if ((*xt_block
)->offset
+ (*xt_block
)->size
10535 == fragP
->fr_address
)
10536 (*xt_block
)->size
+= fragP
->fr_fix
;
10538 xt_block
= &((*xt_block
)->next
);
10540 if (*xt_block
== NULL
)
10542 xtensa_block_info
*new_block
= (xtensa_block_info
*)
10543 xmalloc (sizeof (xtensa_block_info
));
10544 new_block
->sec
= sec
;
10545 new_block
->offset
= fragP
->fr_address
;
10546 new_block
->size
= fragP
->fr_fix
;
10547 new_block
->next
= NULL
;
10548 xtensa_frag_flags_init (&new_block
->flags
);
10549 *xt_block
= new_block
;
10551 if (end_property_function
10552 && end_property_function (fragP
))
10554 xt_block
= &((*xt_block
)->next
);
10562 /* Break the encapsulation of add_xt_prop_frags here. */
10565 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
10567 if (prop_flags
->is_literal
10568 || prop_flags
->is_insn
10569 || prop_flags
->is_data
10570 || prop_flags
->is_unreachable
)
10577 xtensa_frag_flags_init (frag_flags
*prop_flags
)
10579 memset (prop_flags
, 0, sizeof (frag_flags
));
10584 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
10586 xtensa_frag_flags_init (prop_flags
);
10587 if (fragP
->tc_frag_data
.is_literal
)
10588 prop_flags
->is_literal
= TRUE
;
10589 if (fragP
->tc_frag_data
.is_unreachable
)
10590 prop_flags
->is_unreachable
= TRUE
;
10591 else if (fragP
->tc_frag_data
.is_insn
)
10593 prop_flags
->is_insn
= TRUE
;
10594 if (fragP
->tc_frag_data
.is_loop_target
)
10595 prop_flags
->insn
.is_loop_target
= TRUE
;
10596 if (fragP
->tc_frag_data
.is_branch_target
)
10597 prop_flags
->insn
.is_branch_target
= TRUE
;
10598 if (fragP
->tc_frag_data
.is_specific_opcode
10599 || fragP
->tc_frag_data
.is_no_transform
)
10600 prop_flags
->insn
.is_no_transform
= TRUE
;
10601 if (fragP
->tc_frag_data
.is_no_density
)
10602 prop_flags
->insn
.is_no_density
= TRUE
;
10603 if (fragP
->tc_frag_data
.use_absolute_literals
)
10604 prop_flags
->insn
.is_abslit
= TRUE
;
10606 if (fragP
->tc_frag_data
.is_align
)
10608 prop_flags
->is_align
= TRUE
;
10609 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
10610 if (xtensa_frag_flags_is_empty (prop_flags
))
10611 prop_flags
->is_data
= TRUE
;
10617 frag_flags_to_number (const frag_flags
*prop_flags
)
10620 if (prop_flags
->is_literal
)
10621 num
|= XTENSA_PROP_LITERAL
;
10622 if (prop_flags
->is_insn
)
10623 num
|= XTENSA_PROP_INSN
;
10624 if (prop_flags
->is_data
)
10625 num
|= XTENSA_PROP_DATA
;
10626 if (prop_flags
->is_unreachable
)
10627 num
|= XTENSA_PROP_UNREACHABLE
;
10628 if (prop_flags
->insn
.is_loop_target
)
10629 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
10630 if (prop_flags
->insn
.is_branch_target
)
10632 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
10633 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
10636 if (prop_flags
->insn
.is_no_density
)
10637 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
10638 if (prop_flags
->insn
.is_no_transform
)
10639 num
|= XTENSA_PROP_INSN_NO_TRANSFORM
;
10640 if (prop_flags
->insn
.is_no_reorder
)
10641 num
|= XTENSA_PROP_INSN_NO_REORDER
;
10642 if (prop_flags
->insn
.is_abslit
)
10643 num
|= XTENSA_PROP_INSN_ABSLIT
;
10645 if (prop_flags
->is_align
)
10647 num
|= XTENSA_PROP_ALIGN
;
10648 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
10656 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
10657 const frag_flags
*prop_flags_2
)
10659 /* Cannot combine with an end marker. */
10661 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
10663 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
10665 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
10668 if (prop_flags_1
->is_insn
)
10670 /* Properties of the beginning of the frag. */
10671 if (prop_flags_2
->insn
.is_loop_target
)
10673 if (prop_flags_2
->insn
.is_branch_target
)
10675 if (prop_flags_1
->insn
.is_no_density
!=
10676 prop_flags_2
->insn
.is_no_density
)
10678 if (prop_flags_1
->insn
.is_no_transform
!=
10679 prop_flags_2
->insn
.is_no_transform
)
10681 if (prop_flags_1
->insn
.is_no_reorder
!=
10682 prop_flags_2
->insn
.is_no_reorder
)
10684 if (prop_flags_1
->insn
.is_abslit
!=
10685 prop_flags_2
->insn
.is_abslit
)
10689 if (prop_flags_1
->is_align
)
10697 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
10700 unsigned align_bits
;
10702 if (!xt_block
->flags
.is_align
)
10703 return xt_block
->size
;
10705 end_addr
= xt_block
->offset
+ xt_block
->size
;
10706 align_bits
= xt_block
->flags
.alignment
;
10707 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
10708 return end_addr
- xt_block
->offset
;
10713 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
10714 const xtensa_block_info
*xt_block_2
)
10716 if (xt_block
->sec
!= xt_block_2
->sec
)
10718 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
10719 != xt_block_2
->offset
)
10722 if (xt_block_2
->size
== 0
10723 && (!xt_block_2
->flags
.is_unreachable
10724 || xt_block
->flags
.is_unreachable
))
10726 if (xt_block_2
->flags
.is_align
10727 && xt_block
->flags
.is_align
)
10729 /* Nothing needed. */
10730 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
10735 if (xt_block_2
->flags
.is_align
)
10737 /* Push alignment to previous entry. */
10738 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
10739 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10744 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
10745 &xt_block_2
->flags
))
10748 xt_block
->size
+= xt_block_2
->size
;
10750 if (xt_block_2
->flags
.is_align
)
10752 xt_block
->flags
.is_align
= TRUE
;
10753 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10761 add_xt_prop_frags (segT sec
,
10763 xtensa_block_info
**xt_block
,
10764 frag_flags_fn property_function
)
10766 segment_info_type
*seg_info
;
10767 segment_info_type
*xt_seg_info
;
10768 bfd_vma seg_offset
;
10771 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
10772 seg_info
= retrieve_segment_info (sec
);
10773 /* Build it if needed. */
10774 while (*xt_block
!= NULL
)
10776 xt_block
= &(*xt_block
)->next
;
10778 /* We are either at NULL at the beginning or at the end. */
10780 /* Walk through the frags. */
10783 if (seg_info
->frchainP
)
10785 for (fragP
= seg_info
->frchainP
->frch_root
; fragP
;
10786 fragP
= fragP
->fr_next
)
10788 xtensa_block_info tmp_block
;
10789 tmp_block
.sec
= sec
;
10790 tmp_block
.offset
= fragP
->fr_address
;
10791 tmp_block
.size
= fragP
->fr_fix
;
10792 tmp_block
.next
= NULL
;
10793 property_function (fragP
, &tmp_block
.flags
);
10795 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
10796 /* && fragP->fr_fix != 0) */
10798 if ((*xt_block
) == NULL
10799 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
10801 xtensa_block_info
*new_block
;
10802 if ((*xt_block
) != NULL
)
10803 xt_block
= &(*xt_block
)->next
;
10804 new_block
= (xtensa_block_info
*)
10805 xmalloc (sizeof (xtensa_block_info
));
10806 *new_block
= tmp_block
;
10807 *xt_block
= new_block
;
10815 /* op_placement_info_table */
10817 /* op_placement_info makes it easier to determine which
10818 ops can go in which slots. */
10821 init_op_placement_info_table (void)
10823 xtensa_isa isa
= xtensa_default_isa
;
10824 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
10825 xtensa_opcode opcode
;
10828 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
10830 op_placement_table
= (op_placement_info_table
)
10831 xmalloc (sizeof (op_placement_info
) * num_opcodes
);
10832 assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
10834 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
10836 op_placement_info
*opi
= &op_placement_table
[opcode
];
10837 /* FIXME: Make tinsn allocation dynamic. */
10838 if (xtensa_opcode_num_operands (isa
, opcode
) >= MAX_INSN_ARGS
)
10839 as_fatal (_("too many operands in instruction"));
10840 opi
->narrowest
= XTENSA_UNDEFINED
;
10841 opi
->narrowest_size
= 0x7F;
10842 opi
->narrowest_slot
= 0;
10844 opi
->num_formats
= 0;
10846 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
10848 opi
->slots
[fmt
] = 0;
10849 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
10851 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
10853 int fmt_length
= xtensa_format_length (isa
, fmt
);
10855 set_bit (fmt
, opi
->formats
);
10856 set_bit (slot
, opi
->slots
[fmt
]);
10857 if (fmt_length
< opi
->narrowest_size
10858 || (fmt_length
== opi
->narrowest_size
10859 && (xtensa_format_num_slots (isa
, fmt
)
10860 < xtensa_format_num_slots (isa
,
10863 opi
->narrowest
= fmt
;
10864 opi
->narrowest_size
= fmt_length
;
10865 opi
->narrowest_slot
= slot
;
10870 opi
->num_formats
++;
10873 xtensa_insnbuf_free (isa
, ibuf
);
10878 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
10880 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
10884 /* If the opcode is available in a single slot format, return its size. */
10887 xg_get_single_size (xtensa_opcode opcode
)
10889 return op_placement_table
[opcode
].narrowest_size
;
10893 static xtensa_format
10894 xg_get_single_format (xtensa_opcode opcode
)
10896 return op_placement_table
[opcode
].narrowest
;
10901 xg_get_single_slot (xtensa_opcode opcode
)
10903 return op_placement_table
[opcode
].narrowest_slot
;
10907 /* Instruction Stack Functions (from "xtensa-istack.h"). */
10910 istack_init (IStack
*stack
)
10912 memset (stack
, 0, sizeof (IStack
));
10918 istack_empty (IStack
*stack
)
10920 return (stack
->ninsn
== 0);
10925 istack_full (IStack
*stack
)
10927 return (stack
->ninsn
== MAX_ISTACK
);
10931 /* Return a pointer to the top IStack entry.
10932 It is an error to call this if istack_empty () is TRUE. */
10935 istack_top (IStack
*stack
)
10937 int rec
= stack
->ninsn
- 1;
10938 assert (!istack_empty (stack
));
10939 return &stack
->insn
[rec
];
10943 /* Add a new TInsn to an IStack.
10944 It is an error to call this if istack_full () is TRUE. */
10947 istack_push (IStack
*stack
, TInsn
*insn
)
10949 int rec
= stack
->ninsn
;
10950 assert (!istack_full (stack
));
10951 stack
->insn
[rec
] = *insn
;
10956 /* Clear space for the next TInsn on the IStack and return a pointer
10957 to it. It is an error to call this if istack_full () is TRUE. */
10960 istack_push_space (IStack
*stack
)
10962 int rec
= stack
->ninsn
;
10964 assert (!istack_full (stack
));
10965 insn
= &stack
->insn
[rec
];
10966 memset (insn
, 0, sizeof (TInsn
));
10972 /* Remove the last pushed instruction. It is an error to call this if
10973 istack_empty () returns TRUE. */
10976 istack_pop (IStack
*stack
)
10978 int rec
= stack
->ninsn
- 1;
10979 assert (!istack_empty (stack
));
10981 memset (&stack
->insn
[rec
], 0, sizeof (TInsn
));
10985 /* TInsn functions. */
10988 tinsn_init (TInsn
*dst
)
10990 memset (dst
, 0, sizeof (TInsn
));
10994 /* Return TRUE if ANY of the operands in the insn are symbolic. */
10997 tinsn_has_symbolic_operands (const TInsn
*insn
)
11000 int n
= insn
->ntok
;
11002 assert (insn
->insn_type
== ITYPE_INSN
);
11004 for (i
= 0; i
< n
; ++i
)
11006 switch (insn
->tok
[i
].X_op
)
11020 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
11022 xtensa_isa isa
= xtensa_default_isa
;
11024 int n
= insn
->ntok
;
11026 assert (insn
->insn_type
== ITYPE_INSN
);
11028 for (i
= 0; i
< n
; ++i
)
11030 switch (insn
->tok
[i
].X_op
)
11038 /* Errors for these types are caught later. */
11043 /* Symbolic immediates are only allowed on the last immediate
11044 operand. At this time, CONST16 is the only opcode where we
11045 support non-PC-relative relocations. */
11046 if (i
!= get_relaxable_immed (insn
->opcode
)
11047 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
11048 && insn
->opcode
!= xtensa_const16_opcode
))
11050 as_bad (_("invalid symbolic operand"));
11059 /* For assembly code with complex expressions (e.g. subtraction),
11060 we have to build them in the literal pool so that
11061 their results are calculated correctly after relaxation.
11062 The relaxation only handles expressions that
11063 boil down to SYMBOL + OFFSET. */
11066 tinsn_has_complex_operands (const TInsn
*insn
)
11069 int n
= insn
->ntok
;
11070 assert (insn
->insn_type
== ITYPE_INSN
);
11071 for (i
= 0; i
< n
; ++i
)
11073 switch (insn
->tok
[i
].X_op
)
11089 /* Encode a TInsn opcode and its constant operands into slotbuf.
11090 Return TRUE if there is a symbol in the immediate field. This
11091 function assumes that:
11092 1) The number of operands are correct.
11093 2) The insn_type is ITYPE_INSN.
11094 3) The opcode can be encoded in the specified format and slot.
11095 4) Operands are either O_constant or O_symbol, and all constants fit. */
11098 tinsn_to_slotbuf (xtensa_format fmt
,
11101 xtensa_insnbuf slotbuf
)
11103 xtensa_isa isa
= xtensa_default_isa
;
11104 xtensa_opcode opcode
= tinsn
->opcode
;
11105 bfd_boolean has_fixup
= FALSE
;
11106 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11109 assert (tinsn
->insn_type
== ITYPE_INSN
);
11110 if (noperands
!= tinsn
->ntok
)
11111 as_fatal (_("operand number mismatch"));
11113 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
11115 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
11116 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
11120 for (i
= 0; i
< noperands
; i
++)
11122 expressionS
*expr
= &tinsn
->tok
[i
];
11128 switch (expr
->X_op
)
11131 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11133 /* The register number has already been checked in
11134 expression_maybe_register, so we don't need to check here. */
11135 opnd_value
= expr
->X_add_number
;
11136 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11137 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
11140 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
11144 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11146 as_where (&file_name
, &line
);
11147 /* It is a constant and we called this function
11148 then we have to try to fit it. */
11149 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
11150 expr
->X_add_number
, file_name
, line
);
11163 /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded
11164 into a multi-slot instruction, fill the other slots with NOPs.
11165 Return TRUE if there is a symbol in the immediate field. See also the
11166 assumptions listed for tinsn_to_slotbuf. */
11169 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
11171 static xtensa_insnbuf slotbuf
= 0;
11172 static vliw_insn vinsn
;
11173 xtensa_isa isa
= xtensa_default_isa
;
11174 bfd_boolean has_fixup
= FALSE
;
11179 slotbuf
= xtensa_insnbuf_alloc (isa
);
11180 xg_init_vinsn (&vinsn
);
11183 xg_clear_vinsn (&vinsn
);
11185 bundle_tinsn (tinsn
, &vinsn
);
11187 xtensa_format_encode (isa
, vinsn
.format
, insnbuf
);
11189 for (i
= 0; i
< vinsn
.num_slots
; i
++)
11191 /* Only one slot may have a fix-up because the rest contains NOPs. */
11193 tinsn_to_slotbuf (vinsn
.format
, i
, &vinsn
.slots
[i
], vinsn
.slotbuf
[i
]);
11194 xtensa_format_set_slot (isa
, vinsn
.format
, i
, insnbuf
, vinsn
.slotbuf
[i
]);
11201 /* Check the instruction arguments. Return TRUE on failure. */
11204 tinsn_check_arguments (const TInsn
*insn
)
11206 xtensa_isa isa
= xtensa_default_isa
;
11207 xtensa_opcode opcode
= insn
->opcode
;
11209 if (opcode
== XTENSA_UNDEFINED
)
11211 as_bad (_("invalid opcode"));
11215 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
11217 as_bad (_("too few operands"));
11221 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
11223 as_bad (_("too many operands"));
11230 /* Load an instruction from its encoded form. */
11233 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
11237 xg_init_vinsn (&vinsn
);
11238 vinsn_from_chars (&vinsn
, f
);
11240 *tinsn
= vinsn
.slots
[slot
];
11241 xg_free_vinsn (&vinsn
);
11246 tinsn_from_insnbuf (TInsn
*tinsn
,
11247 xtensa_insnbuf slotbuf
,
11252 xtensa_isa isa
= xtensa_default_isa
;
11254 /* Find the immed. */
11255 tinsn_init (tinsn
);
11256 tinsn
->insn_type
= ITYPE_INSN
;
11257 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
11258 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
11259 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
11260 for (i
= 0; i
< tinsn
->ntok
; i
++)
11262 set_expr_const (&tinsn
->tok
[i
],
11263 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
11264 tinsn
->opcode
, i
));
11269 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
11272 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
11274 xtensa_opcode opcode
= tinsn
->opcode
;
11277 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
11279 opnum
= get_relaxable_immed (opcode
);
11280 assert (opnum
>= 0);
11281 set_expr_symbol_offset (&tinsn
->tok
[opnum
],
11282 fragP
->tc_frag_data
.slot_symbols
[slot
],
11283 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11289 get_num_stack_text_bytes (IStack
*istack
)
11292 int text_bytes
= 0;
11294 for (i
= 0; i
< istack
->ninsn
; i
++)
11296 TInsn
*tinsn
= &istack
->insn
[i
];
11297 if (tinsn
->insn_type
== ITYPE_INSN
)
11298 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
11305 get_num_stack_literal_bytes (IStack
*istack
)
11310 for (i
= 0; i
< istack
->ninsn
; i
++)
11312 TInsn
*tinsn
= &istack
->insn
[i
];
11313 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
11320 /* vliw_insn functions. */
11323 xg_init_vinsn (vliw_insn
*v
)
11326 xtensa_isa isa
= xtensa_default_isa
;
11328 xg_clear_vinsn (v
);
11330 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
11331 if (v
->insnbuf
== NULL
)
11332 as_fatal (_("out of memory"));
11334 for (i
= 0; i
< MAX_SLOTS
; i
++)
11336 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
11337 if (v
->slotbuf
[i
] == NULL
)
11338 as_fatal (_("out of memory"));
11344 xg_clear_vinsn (vliw_insn
*v
)
11348 memset (v
, 0, offsetof (vliw_insn
, insnbuf
));
11350 v
->format
= XTENSA_UNDEFINED
;
11352 v
->inside_bundle
= FALSE
;
11354 if (xt_saved_debug_type
!= DEBUG_NONE
)
11355 debug_type
= xt_saved_debug_type
;
11357 for (i
= 0; i
< MAX_SLOTS
; i
++)
11358 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
11363 vinsn_has_specific_opcodes (vliw_insn
*v
)
11367 for (i
= 0; i
< v
->num_slots
; i
++)
11369 if (v
->slots
[i
].is_specific_opcode
)
11377 xg_free_vinsn (vliw_insn
*v
)
11380 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
11381 for (i
= 0; i
< MAX_SLOTS
; i
++)
11382 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
11386 /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic
11387 operands. See also the assumptions listed for tinsn_to_slotbuf. */
11390 vinsn_to_insnbuf (vliw_insn
*vinsn
,
11393 bfd_boolean record_fixup
)
11395 xtensa_isa isa
= xtensa_default_isa
;
11396 xtensa_format fmt
= vinsn
->format
;
11397 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
11399 bfd_boolean has_fixup
= FALSE
;
11401 xtensa_format_encode (isa
, fmt
, insnbuf
);
11403 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
11405 TInsn
*tinsn
= &vinsn
->slots
[slot
];
11406 bfd_boolean tinsn_has_fixup
=
11407 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
11408 vinsn
->slotbuf
[slot
]);
11410 xtensa_format_set_slot (isa
, fmt
, slot
,
11411 insnbuf
, vinsn
->slotbuf
[slot
]);
11412 if (tinsn_has_fixup
)
11415 xtensa_opcode opcode
= tinsn
->opcode
;
11416 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11419 for (i
= 0; i
< noperands
; i
++)
11421 expressionS
* expr
= &tinsn
->tok
[i
];
11422 switch (expr
->X_op
)
11427 if (get_relaxable_immed (opcode
) == i
)
11429 /* Add a fix record for the instruction, except if this
11430 function is being called prior to relaxation, i.e.,
11431 if record_fixup is false, and the instruction might
11432 be relaxed later. */
11434 || tinsn
->is_specific_opcode
11435 || !xg_is_relaxable_insn (tinsn
, 0))
11437 xg_add_opcode_fix (tinsn
, i
, fmt
, slot
, expr
, fragP
,
11438 frag_offset
- fragP
->fr_literal
);
11442 if (expr
->X_op
!= O_symbol
)
11443 as_bad (_("invalid operand"));
11444 tinsn
->symbol
= expr
->X_add_symbol
;
11445 tinsn
->offset
= expr
->X_add_number
;
11449 as_bad (_("symbolic operand not allowed"));
11457 as_bad (_("expression too complex"));
11469 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
11471 static xtensa_insnbuf insnbuf
= NULL
;
11472 static xtensa_insnbuf slotbuf
= NULL
;
11475 xtensa_isa isa
= xtensa_default_isa
;
11479 insnbuf
= xtensa_insnbuf_alloc (isa
);
11480 slotbuf
= xtensa_insnbuf_alloc (isa
);
11483 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) f
, 0);
11484 fmt
= xtensa_format_decode (isa
, insnbuf
);
11485 if (fmt
== XTENSA_UNDEFINED
)
11486 as_fatal (_("cannot decode instruction format"));
11487 vinsn
->format
= fmt
;
11488 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
11490 for (i
= 0; i
< vinsn
->num_slots
; i
++)
11492 TInsn
*tinsn
= &vinsn
->slots
[i
];
11493 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
11494 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
11499 /* Expression utilities. */
11501 /* Return TRUE if the expression is an integer constant. */
11504 expr_is_const (const expressionS
*s
)
11506 return (s
->X_op
== O_constant
);
11510 /* Get the expression constant.
11511 Calling this is illegal if expr_is_const () returns TRUE. */
11514 get_expr_const (const expressionS
*s
)
11516 assert (expr_is_const (s
));
11517 return s
->X_add_number
;
11521 /* Set the expression to a constant value. */
11524 set_expr_const (expressionS
*s
, offsetT val
)
11526 s
->X_op
= O_constant
;
11527 s
->X_add_number
= val
;
11528 s
->X_add_symbol
= NULL
;
11529 s
->X_op_symbol
= NULL
;
11534 expr_is_register (const expressionS
*s
)
11536 return (s
->X_op
== O_register
);
11540 /* Get the expression constant.
11541 Calling this is illegal if expr_is_const () returns TRUE. */
11544 get_expr_register (const expressionS
*s
)
11546 assert (expr_is_register (s
));
11547 return s
->X_add_number
;
11551 /* Set the expression to a symbol + constant offset. */
11554 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
11556 s
->X_op
= O_symbol
;
11557 s
->X_add_symbol
= sym
;
11558 s
->X_op_symbol
= NULL
; /* unused */
11559 s
->X_add_number
= offset
;
11563 /* Return TRUE if the two expressions are equal. */
11566 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
11568 if (s1
->X_op
!= s2
->X_op
)
11570 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
11572 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
11574 if (s1
->X_add_number
!= s2
->X_add_number
)
11581 copy_expr (expressionS
*dst
, const expressionS
*src
)
11583 memcpy (dst
, src
, sizeof (expressionS
));
11587 /* Support for the "--rename-section" option. */
11589 struct rename_section_struct
11593 struct rename_section_struct
*next
;
11596 static struct rename_section_struct
*section_rename
;
11599 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
11600 entries to the section_rename list. Note: Specifying multiple
11601 renamings separated by colons is not documented and is retained only
11602 for backward compatibility. */
11605 build_section_rename (const char *arg
)
11607 struct rename_section_struct
*r
;
11608 char *this_arg
= NULL
;
11609 char *next_arg
= NULL
;
11611 for (this_arg
= xstrdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
11613 char *old_name
, *new_name
;
11617 next_arg
= strchr (this_arg
, ':');
11625 old_name
= this_arg
;
11626 new_name
= strchr (this_arg
, '=');
11628 if (*old_name
== '\0')
11630 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
11633 if (!new_name
|| new_name
[1] == '\0')
11635 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
11642 /* Check for invalid section renaming. */
11643 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11645 if (strcmp (r
->old_name
, old_name
) == 0)
11646 as_bad (_("section %s renamed multiple times"), old_name
);
11647 if (strcmp (r
->new_name
, new_name
) == 0)
11648 as_bad (_("multiple sections remapped to output section %s"),
11653 r
= (struct rename_section_struct
*)
11654 xmalloc (sizeof (struct rename_section_struct
));
11655 r
->old_name
= xstrdup (old_name
);
11656 r
->new_name
= xstrdup (new_name
);
11657 r
->next
= section_rename
;
11658 section_rename
= r
;
11664 xtensa_section_rename (char *name
)
11666 struct rename_section_struct
*r
= section_rename
;
11668 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11670 if (strcmp (r
->old_name
, name
) == 0)
11671 return r
->new_name
;