1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
24 #include "safe-ctype.h"
25 #include "tc-xtensa.h"
27 #include "xtensa-relax.h"
28 #include "dwarf2dbg.h"
29 #include "xtensa-istack.h"
30 #include "struc-symbol.h"
31 #include "xtensa-config.h"
33 /* Provide default values for new configuration settings. */
39 #define uint32 unsigned int
42 #define int32 signed int
47 Naming conventions (used somewhat inconsistently):
48 The xtensa_ functions are exported
49 The xg_ functions are internal
51 We also have a couple of different extensibility mechanisms.
52 1) The idiom replacement:
53 This is used when a line is first parsed to
54 replace an instruction pattern with another instruction
55 It is currently limited to replacements of instructions
56 with constant operands.
57 2) The xtensa-relax.c mechanism that has stronger instruction
58 replacement patterns. When an instruction's immediate field
59 does not fit the next instruction sequence is attempted.
60 In addition, "narrow" opcodes are supported this way. */
63 /* Define characters with special meanings to GAS. */
64 const char comment_chars
[] = "#";
65 const char line_comment_chars
[] = "#";
66 const char line_separator_chars
[] = ";";
67 const char EXP_CHARS
[] = "eE";
68 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
71 /* Flags to indicate whether the hardware supports the density and
72 absolute literals options. */
74 bfd_boolean density_supported
= XCHAL_HAVE_DENSITY
;
75 bfd_boolean absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
77 /* Maximum width we would pad an unreachable frag to get alignment. */
78 #define UNREACHABLE_MAX_WIDTH 8
80 static vliw_insn cur_vinsn
;
82 unsigned xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
84 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
86 /* Some functions are only valid in the front end. This variable
87 allows us to assert that we haven't crossed over into the
89 static bfd_boolean past_xtensa_end
= FALSE
;
91 /* Flags for properties of the last instruction in a segment. */
92 #define FLAG_IS_A0_WRITER 0x1
93 #define FLAG_IS_BAD_LOOPEND 0x2
96 /* We define a special segment names ".literal" to place literals
97 into. The .fini and .init sections are special because they
98 contain code that is moved together by the linker. We give them
99 their own special .fini.literal and .init.literal sections. */
101 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
102 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
103 #define INIT_SECTION_NAME xtensa_section_rename (".init")
104 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
107 /* This type is used for the directive_stack to keep track of the
108 state of the literal collection pools. If lit_prefix is set, it is
109 used to determine the literal section names; otherwise, the literal
110 sections are determined based on the current text section. The
111 lit_seg and lit4_seg fields cache these literal sections, with the
112 current_text_seg field used a tag to indicate whether the cached
115 typedef struct lit_state_struct
118 segT current_text_seg
;
123 static lit_state default_lit_sections
;
126 /* We keep a list of literal segments. The seg_list type is the node
127 for this list. The literal_head pointer is the head of the list,
128 with the literal_head_h dummy node at the start. */
130 typedef struct seg_list_struct
132 struct seg_list_struct
*next
;
136 static seg_list literal_head_h
;
137 static seg_list
*literal_head
= &literal_head_h
;
140 /* Lists of symbols. We keep a list of symbols that label the current
141 instruction, so that we can adjust the symbols when inserting alignment
142 for various instructions. We also keep a list of all the symbols on
143 literals, so that we can fix up those symbols when the literals are
144 later moved into the text sections. */
146 typedef struct sym_list_struct
148 struct sym_list_struct
*next
;
152 static sym_list
*insn_labels
= NULL
;
153 static sym_list
*free_insn_labels
= NULL
;
154 static sym_list
*saved_insn_labels
= NULL
;
156 static sym_list
*literal_syms
;
159 /* Flags to determine whether to prefer const16 or l32r
160 if both options are available. */
161 int prefer_const16
= 0;
164 /* Global flag to indicate when we are emitting literals. */
165 int generating_literals
= 0;
167 /* The following PROPERTY table definitions are copied from
168 <elf/xtensa.h> and must be kept in sync with the code there. */
170 /* Flags in the property tables to specify whether blocks of memory
171 are literals, instructions, data, or unreachable. For
172 instructions, blocks that begin loop targets and branch targets are
173 designated. Blocks that do not allow density, instruction
174 reordering or transformation are also specified. Finally, for
175 branch targets, branch target alignment priority is included.
176 Alignment of the next block is specified in the current block
177 and the size of the current block does not include any fill required
178 to align to the next block. */
180 #define XTENSA_PROP_LITERAL 0x00000001
181 #define XTENSA_PROP_INSN 0x00000002
182 #define XTENSA_PROP_DATA 0x00000004
183 #define XTENSA_PROP_UNREACHABLE 0x00000008
184 /* Instruction only properties at beginning of code. */
185 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
186 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
187 /* Instruction only properties about code. */
188 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
189 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
190 /* Historically, NO_TRANSFORM was a property of instructions,
191 but it should apply to literals under certain circumstances. */
192 #define XTENSA_PROP_NO_TRANSFORM 0x00000100
194 /* Branch target alignment information. This transmits information
195 to the linker optimization about the priority of aligning a
196 particular block for branch target alignment: None, low priority,
197 high priority, or required. These only need to be checked in
198 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
201 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
202 case XTENSA_PROP_BT_ALIGN_NONE:
203 case XTENSA_PROP_BT_ALIGN_LOW:
204 case XTENSA_PROP_BT_ALIGN_HIGH:
205 case XTENSA_PROP_BT_ALIGN_REQUIRE:
207 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
209 /* No branch target alignment. */
210 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
211 /* Low priority branch target alignment. */
212 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
213 /* High priority branch target alignment. */
214 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
215 /* Required branch target alignment. */
216 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
218 #define GET_XTENSA_PROP_BT_ALIGN(flag) \
219 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
220 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
221 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
222 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
225 /* Alignment is specified in the block BEFORE the one that needs
226 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
227 get the required alignment specified as a power of 2. Use
228 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
229 alignment. Be careful of side effects since the SET will evaluate
230 flags twice. Also, note that the SIZE of a block in the property
231 table does not include the alignment size, so the alignment fill
232 must be calculated to determine if two blocks are contiguous.
233 TEXT_ALIGN is not currently implemented but is a placeholder for a
234 possible future implementation. */
236 #define XTENSA_PROP_ALIGN 0x00000800
238 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
240 #define GET_XTENSA_PROP_ALIGNMENT(flag) \
241 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
242 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
243 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
244 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
246 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
249 /* Structure for saving instruction and alignment per-fragment data
250 that will be written to the object file. This structure is
251 equivalent to the actual data that will be written out to the file
252 but is easier to use. We provide a conversion to file flags
253 in frag_flags_to_number. */
255 typedef struct frag_flags_struct frag_flags
;
257 struct frag_flags_struct
259 /* is_literal should only be used after xtensa_move_literals.
260 If you need to check if you are generating a literal fragment,
261 then use the generating_literals global. */
263 unsigned is_literal
: 1;
264 unsigned is_insn
: 1;
265 unsigned is_data
: 1;
266 unsigned is_unreachable
: 1;
268 /* is_specific_opcode implies no_transform. */
269 unsigned is_no_transform
: 1;
273 unsigned is_loop_target
: 1;
274 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
275 unsigned bt_align_priority
: 2;
277 unsigned is_no_density
: 1;
278 /* no_longcalls flag does not need to be placed in the object file. */
280 unsigned is_no_reorder
: 1;
282 /* Uses absolute literal addressing for l32r. */
283 unsigned is_abslit
: 1;
285 unsigned is_align
: 1;
286 unsigned alignment
: 5;
290 /* Structure for saving information about a block of property data
291 for frags that have the same flags. */
292 struct xtensa_block_info_struct
298 struct xtensa_block_info_struct
*next
;
302 /* Structure for saving the current state before emitting literals. */
303 typedef struct emit_state_struct
308 int generating_literals
;
312 /* Opcode placement information */
314 typedef unsigned long long bitfield
;
315 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
316 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
317 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
319 #define MAX_FORMATS 32
321 typedef struct op_placement_info_struct
324 /* A number describing how restrictive the issue is for this
325 opcode. For example, an opcode that fits lots of different
326 formats has a high freedom, as does an opcode that fits
327 only one format but many slots in that format. The most
328 restrictive is the opcode that fits only one slot in one
331 xtensa_format narrowest
;
335 /* formats is a bitfield with the Nth bit set
336 if the opcode fits in the Nth xtensa_format. */
339 /* slots[N]'s Mth bit is set if the op fits in the
340 Mth slot of the Nth xtensa_format. */
341 bitfield slots
[MAX_FORMATS
];
343 /* A count of the number of slots in a given format
344 an op can fit (i.e., the bitcount of the slot field above). */
345 char slots_in_format
[MAX_FORMATS
];
347 } op_placement_info
, *op_placement_info_table
;
349 op_placement_info_table op_placement_table
;
352 /* Extra expression types. */
354 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
355 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
356 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
358 struct suffix_reloc_map
362 bfd_reloc_code_real_type reloc
;
363 unsigned char operator;
366 #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op }
368 static struct suffix_reloc_map suffix_relocs
[] =
370 SUFFIX_MAP ("l", BFD_RELOC_LO16
, O_lo16
),
371 SUFFIX_MAP ("h", BFD_RELOC_HI16
, O_hi16
),
372 SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT
, O_pltrel
),
373 { (char *) 0, 0, BFD_RELOC_UNUSED
, 0 }
387 directive_literal_prefix
,
389 directive_absolute_literals
,
390 directive_last_directive
396 bfd_boolean can_be_negated
;
399 const directive_infoS directive_info
[] =
402 { "literal", FALSE
},
404 { "transform", TRUE
},
405 { "freeregs", FALSE
},
406 { "longcalls", TRUE
},
407 { "literal_prefix", FALSE
},
408 { "schedule", TRUE
},
409 { "absolute-literals", TRUE
}
412 bfd_boolean directive_state
[] =
416 #if !XCHAL_HAVE_DENSITY
421 TRUE
, /* transform */
422 FALSE
, /* freeregs */
423 FALSE
, /* longcalls */
424 FALSE
, /* literal_prefix */
425 FALSE
, /* schedule */
426 #if XSHAL_USE_ABSOLUTE_LITERALS
427 TRUE
/* absolute_literals */
429 FALSE
/* absolute_literals */
434 /* Directive functions. */
436 static void xtensa_begin_directive (int);
437 static void xtensa_end_directive (int);
438 static void xtensa_literal_prefix (void);
439 static void xtensa_literal_position (int);
440 static void xtensa_literal_pseudo (int);
441 static void xtensa_frequency_pseudo (int);
442 static void xtensa_elf_cons (int);
444 /* Parsing and Idiom Translation. */
446 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
448 /* Various Other Internal Functions. */
450 extern bfd_boolean
xg_is_single_relaxable_insn (TInsn
*, TInsn
*, bfd_boolean
);
451 static bfd_boolean
xg_build_to_insn (TInsn
*, TInsn
*, BuildInstr
*);
452 static void xtensa_mark_literal_pool_location (void);
453 static addressT
get_expanded_loop_offset (xtensa_opcode
);
454 static fragS
*get_literal_pool_location (segT
);
455 static void set_literal_pool_location (segT
, fragS
*);
456 static void xtensa_set_frag_assembly_state (fragS
*);
457 static void finish_vinsn (vliw_insn
*);
458 static bfd_boolean
emit_single_op (TInsn
*);
459 static int total_frag_text_expansion (fragS
*);
461 /* Alignment Functions. */
463 static int get_text_align_power (unsigned);
464 static int get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
465 static int branch_align_power (segT
);
467 /* Helpers for xtensa_relax_frag(). */
469 static long relax_frag_add_nop (fragS
*);
471 /* Accessors for additional per-subsegment information. */
473 static unsigned get_last_insn_flags (segT
, subsegT
);
474 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
475 static float get_subseg_total_freq (segT
, subsegT
);
476 static float get_subseg_target_freq (segT
, subsegT
);
477 static void set_subseg_freq (segT
, subsegT
, float, float);
479 /* Segment list functions. */
481 static void xtensa_move_literals (void);
482 static void xtensa_reorder_segments (void);
483 static void xtensa_switch_to_literal_fragment (emit_state
*);
484 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
485 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
486 static void xtensa_restore_emit_state (emit_state
*);
487 static segT
cache_literal_section (bfd_boolean
);
489 /* Import from elf32-xtensa.c in BFD library. */
491 extern asection
*xtensa_get_property_section (asection
*, const char *);
493 /* op_placement_info functions. */
495 static void init_op_placement_info_table (void);
496 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
497 static int xg_get_single_size (xtensa_opcode
);
498 static xtensa_format
xg_get_single_format (xtensa_opcode
);
499 static int xg_get_single_slot (xtensa_opcode
);
501 /* TInsn and IStack functions. */
503 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
504 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
505 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
506 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
507 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
508 static void tinsn_from_chars (TInsn
*, char *, int);
509 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
510 static int get_num_stack_text_bytes (IStack
*);
511 static int get_num_stack_literal_bytes (IStack
*);
513 /* vliw_insn functions. */
515 static void xg_init_vinsn (vliw_insn
*);
516 static void xg_clear_vinsn (vliw_insn
*);
517 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
518 static void xg_free_vinsn (vliw_insn
*);
519 static bfd_boolean vinsn_to_insnbuf
520 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
521 static void vinsn_from_chars (vliw_insn
*, char *);
523 /* Expression Utilities. */
525 bfd_boolean
expr_is_const (const expressionS
*);
526 offsetT
get_expr_const (const expressionS
*);
527 void set_expr_const (expressionS
*, offsetT
);
528 bfd_boolean
expr_is_register (const expressionS
*);
529 offsetT
get_expr_register (const expressionS
*);
530 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
531 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
532 static void copy_expr (expressionS
*, const expressionS
*);
534 /* Section renaming. */
536 static void build_section_rename (const char *);
539 /* ISA imported from bfd. */
540 extern xtensa_isa xtensa_default_isa
;
542 extern int target_big_endian
;
544 static xtensa_opcode xtensa_addi_opcode
;
545 static xtensa_opcode xtensa_addmi_opcode
;
546 static xtensa_opcode xtensa_call0_opcode
;
547 static xtensa_opcode xtensa_call4_opcode
;
548 static xtensa_opcode xtensa_call8_opcode
;
549 static xtensa_opcode xtensa_call12_opcode
;
550 static xtensa_opcode xtensa_callx0_opcode
;
551 static xtensa_opcode xtensa_callx4_opcode
;
552 static xtensa_opcode xtensa_callx8_opcode
;
553 static xtensa_opcode xtensa_callx12_opcode
;
554 static xtensa_opcode xtensa_const16_opcode
;
555 static xtensa_opcode xtensa_entry_opcode
;
556 static xtensa_opcode xtensa_extui_opcode
;
557 static xtensa_opcode xtensa_movi_opcode
;
558 static xtensa_opcode xtensa_movi_n_opcode
;
559 static xtensa_opcode xtensa_isync_opcode
;
560 static xtensa_opcode xtensa_jx_opcode
;
561 static xtensa_opcode xtensa_l32r_opcode
;
562 static xtensa_opcode xtensa_loop_opcode
;
563 static xtensa_opcode xtensa_loopnez_opcode
;
564 static xtensa_opcode xtensa_loopgtz_opcode
;
565 static xtensa_opcode xtensa_nop_opcode
;
566 static xtensa_opcode xtensa_nop_n_opcode
;
567 static xtensa_opcode xtensa_or_opcode
;
568 static xtensa_opcode xtensa_ret_opcode
;
569 static xtensa_opcode xtensa_ret_n_opcode
;
570 static xtensa_opcode xtensa_retw_opcode
;
571 static xtensa_opcode xtensa_retw_n_opcode
;
572 static xtensa_opcode xtensa_rsr_lcount_opcode
;
573 static xtensa_opcode xtensa_waiti_opcode
;
576 /* Command-line Options. */
578 bfd_boolean use_literal_section
= TRUE
;
579 static bfd_boolean align_targets
= TRUE
;
580 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
581 static bfd_boolean has_a0_b_retw
= FALSE
;
582 static bfd_boolean workaround_a0_b_retw
= FALSE
;
583 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
584 static bfd_boolean workaround_short_loop
= FALSE
;
585 static bfd_boolean maybe_has_short_loop
= FALSE
;
586 static bfd_boolean workaround_close_loop_end
= FALSE
;
587 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
588 static bfd_boolean enforce_three_byte_loop_align
= FALSE
;
590 /* When workaround_short_loops is TRUE, all loops with early exits must
591 have at least 3 instructions. workaround_all_short_loops is a modifier
592 to the workaround_short_loop flag. In addition to the
593 workaround_short_loop actions, all straightline loopgtz and loopnez
594 must have at least 3 instructions. */
596 static bfd_boolean workaround_all_short_loops
= FALSE
;
600 xtensa_setup_hw_workarounds (int earliest
, int latest
)
602 if (earliest
> latest
)
603 as_fatal (_("illegal range of target hardware versions"));
605 /* Enable all workarounds for pre-T1050.0 hardware. */
606 if (earliest
< 105000 || latest
< 105000)
608 workaround_a0_b_retw
|= TRUE
;
609 workaround_b_j_loop_end
|= TRUE
;
610 workaround_short_loop
|= TRUE
;
611 workaround_close_loop_end
|= TRUE
;
612 workaround_all_short_loops
|= TRUE
;
613 enforce_three_byte_loop_align
= TRUE
;
620 option_density
= OPTION_MD_BASE
,
627 option_no_link_relax
,
635 option_text_section_literals
,
636 option_no_text_section_literals
,
638 option_absolute_literals
,
639 option_no_absolute_literals
,
641 option_align_targets
,
642 option_no_align_targets
,
644 option_warn_unaligned_targets
,
649 option_workaround_a0_b_retw
,
650 option_no_workaround_a0_b_retw
,
652 option_workaround_b_j_loop_end
,
653 option_no_workaround_b_j_loop_end
,
655 option_workaround_short_loop
,
656 option_no_workaround_short_loop
,
658 option_workaround_all_short_loops
,
659 option_no_workaround_all_short_loops
,
661 option_workaround_close_loop_end
,
662 option_no_workaround_close_loop_end
,
664 option_no_workarounds
,
666 option_rename_section_name
,
669 option_prefer_const16
,
671 option_target_hardware
674 const char *md_shortopts
= "";
676 struct option md_longopts
[] =
678 { "density", no_argument
, NULL
, option_density
},
679 { "no-density", no_argument
, NULL
, option_no_density
},
681 /* Both "relax" and "generics" are deprecated and treated as equivalent
682 to the "transform" option. */
683 { "relax", no_argument
, NULL
, option_relax
},
684 { "no-relax", no_argument
, NULL
, option_no_relax
},
685 { "generics", no_argument
, NULL
, option_generics
},
686 { "no-generics", no_argument
, NULL
, option_no_generics
},
688 { "transform", no_argument
, NULL
, option_transform
},
689 { "no-transform", no_argument
, NULL
, option_no_transform
},
690 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
691 { "no-text-section-literals", no_argument
, NULL
,
692 option_no_text_section_literals
},
693 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
694 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
695 /* This option was changed from -align-target to -target-align
696 because it conflicted with the "-al" option. */
697 { "target-align", no_argument
, NULL
, option_align_targets
},
698 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
699 { "warn-unaligned-targets", no_argument
, NULL
,
700 option_warn_unaligned_targets
},
701 { "longcalls", no_argument
, NULL
, option_longcalls
},
702 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
704 { "no-workaround-a0-b-retw", no_argument
, NULL
,
705 option_no_workaround_a0_b_retw
},
706 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
708 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
709 option_no_workaround_b_j_loop_end
},
710 { "workaround-b-j-loop-end", no_argument
, NULL
,
711 option_workaround_b_j_loop_end
},
713 { "no-workaround-short-loops", no_argument
, NULL
,
714 option_no_workaround_short_loop
},
715 { "workaround-short-loops", no_argument
, NULL
,
716 option_workaround_short_loop
},
718 { "no-workaround-all-short-loops", no_argument
, NULL
,
719 option_no_workaround_all_short_loops
},
720 { "workaround-all-short-loop", no_argument
, NULL
,
721 option_workaround_all_short_loops
},
723 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
724 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
726 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
728 { "no-workaround-close-loop-end", no_argument
, NULL
,
729 option_no_workaround_close_loop_end
},
730 { "workaround-close-loop-end", no_argument
, NULL
,
731 option_workaround_close_loop_end
},
733 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
735 { "link-relax", no_argument
, NULL
, option_link_relax
},
736 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
738 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
740 { NULL
, no_argument
, NULL
, 0 }
743 size_t md_longopts_size
= sizeof md_longopts
;
747 md_parse_option (int c
, char *arg
)
752 as_warn (_("--density option is ignored"));
754 case option_no_density
:
755 as_warn (_("--no-density option is ignored"));
757 case option_link_relax
:
760 case option_no_link_relax
:
763 case option_generics
:
764 as_warn (_("--generics is deprecated; use --transform instead"));
765 return md_parse_option (option_transform
, arg
);
766 case option_no_generics
:
767 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
768 return md_parse_option (option_no_transform
, arg
);
770 as_warn (_("--relax is deprecated; use --transform instead"));
771 return md_parse_option (option_transform
, arg
);
772 case option_no_relax
:
773 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
774 return md_parse_option (option_no_transform
, arg
);
775 case option_longcalls
:
776 directive_state
[directive_longcalls
] = TRUE
;
778 case option_no_longcalls
:
779 directive_state
[directive_longcalls
] = FALSE
;
781 case option_text_section_literals
:
782 use_literal_section
= FALSE
;
784 case option_no_text_section_literals
:
785 use_literal_section
= TRUE
;
787 case option_absolute_literals
:
788 if (!absolute_literals_supported
)
790 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
793 directive_state
[directive_absolute_literals
] = TRUE
;
795 case option_no_absolute_literals
:
796 directive_state
[directive_absolute_literals
] = FALSE
;
799 case option_workaround_a0_b_retw
:
800 workaround_a0_b_retw
= TRUE
;
802 case option_no_workaround_a0_b_retw
:
803 workaround_a0_b_retw
= FALSE
;
805 case option_workaround_b_j_loop_end
:
806 workaround_b_j_loop_end
= TRUE
;
808 case option_no_workaround_b_j_loop_end
:
809 workaround_b_j_loop_end
= FALSE
;
812 case option_workaround_short_loop
:
813 workaround_short_loop
= TRUE
;
815 case option_no_workaround_short_loop
:
816 workaround_short_loop
= FALSE
;
819 case option_workaround_all_short_loops
:
820 workaround_all_short_loops
= TRUE
;
822 case option_no_workaround_all_short_loops
:
823 workaround_all_short_loops
= FALSE
;
826 case option_workaround_close_loop_end
:
827 workaround_close_loop_end
= TRUE
;
829 case option_no_workaround_close_loop_end
:
830 workaround_close_loop_end
= FALSE
;
833 case option_no_workarounds
:
834 workaround_a0_b_retw
= FALSE
;
835 workaround_b_j_loop_end
= FALSE
;
836 workaround_short_loop
= FALSE
;
837 workaround_all_short_loops
= FALSE
;
838 workaround_close_loop_end
= FALSE
;
841 case option_align_targets
:
842 align_targets
= TRUE
;
844 case option_no_align_targets
:
845 align_targets
= FALSE
;
848 case option_warn_unaligned_targets
:
849 warn_unaligned_branch_targets
= TRUE
;
852 case option_rename_section_name
:
853 build_section_rename (arg
);
857 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
858 should be emitted or not. FIXME: Not implemented. */
861 case option_prefer_l32r
:
863 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
867 case option_prefer_const16
:
869 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
873 case option_target_hardware
:
875 int earliest
, latest
= 0;
876 if (*arg
== 0 || *arg
== '-')
877 as_fatal (_("invalid target hardware version"));
879 earliest
= strtol (arg
, &arg
, 0);
883 else if (*arg
== '-')
886 as_fatal (_("invalid target hardware version"));
887 latest
= strtol (arg
, &arg
, 0);
890 as_fatal (_("invalid target hardware version"));
892 xtensa_setup_hw_workarounds (earliest
, latest
);
896 case option_transform
:
897 /* This option has no affect other than to use the defaults,
898 which are already set. */
901 case option_no_transform
:
902 /* This option turns off all transformations of any kind.
903 However, because we want to preserve the state of other
904 directives, we only change its own field. Thus, before
905 you perform any transformation, always check if transform
906 is available. If you use the functions we provide for this
907 purpose, you will be ok. */
908 directive_state
[directive_transform
] = FALSE
;
918 md_show_usage (FILE *stream
)
922 --[no-]text-section-literals\n\
923 [Do not] put literals in the text section\n\
924 --[no-]absolute-literals\n\
925 [Do not] default to use non-PC-relative literals\n\
926 --[no-]target-align [Do not] try to align branch targets\n\
927 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
928 --[no-]transform [Do not] transform instructions\n\
929 --rename-section old=new Rename section 'old' to 'new'\n", stream
);
933 /* Functions related to the list of current label symbols. */
936 xtensa_add_insn_label (symbolS
*sym
)
940 if (!free_insn_labels
)
941 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
944 l
= free_insn_labels
;
945 free_insn_labels
= l
->next
;
949 l
->next
= insn_labels
;
955 xtensa_clear_insn_labels (void)
959 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
967 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
)
971 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
973 symbolS
*lit_sym
= lit
->sym
;
974 S_SET_VALUE (lit_sym
, new_offset
);
975 symbol_set_frag (lit_sym
, new_frag
);
980 /* Directive data and functions. */
982 typedef struct state_stackS_struct
984 directiveE directive
;
986 bfd_boolean old_state
;
990 struct state_stackS_struct
*prev
;
993 state_stackS
*directive_state_stack
;
995 const pseudo_typeS md_pseudo_table
[] =
997 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
998 { "literal_position", xtensa_literal_position
, 0 },
999 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
1000 { "long", xtensa_elf_cons
, 4 },
1001 { "word", xtensa_elf_cons
, 4 },
1002 { "short", xtensa_elf_cons
, 2 },
1003 { "begin", xtensa_begin_directive
, 0 },
1004 { "end", xtensa_end_directive
, 0 },
1005 { "literal", xtensa_literal_pseudo
, 0 },
1006 { "frequency", xtensa_frequency_pseudo
, 0 },
1012 use_transform (void)
1014 /* After md_end, you should be checking frag by frag, rather
1015 than state directives. */
1016 assert (!past_xtensa_end
);
1017 return directive_state
[directive_transform
];
1022 do_align_targets (void)
1024 /* Do not use this function after md_end; just look at align_targets
1025 instead. There is no target-align directive, so alignment is either
1026 enabled for all frags or not done at all. */
1027 assert (!past_xtensa_end
);
1028 return align_targets
&& use_transform ();
1033 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1037 state_stackS
*stack
= (state_stackS
*) xmalloc (sizeof (state_stackS
));
1039 as_where (&file
, &line
);
1041 stack
->directive
= directive
;
1042 stack
->negated
= negated
;
1043 stack
->old_state
= directive_state
[directive
];
1046 stack
->datum
= datum
;
1047 stack
->prev
= directive_state_stack
;
1048 directive_state_stack
= stack
;
1050 directive_state
[directive
] = !negated
;
1055 directive_pop (directiveE
*directive
,
1056 bfd_boolean
*negated
,
1061 state_stackS
*top
= directive_state_stack
;
1063 if (!directive_state_stack
)
1065 as_bad (_("unmatched end directive"));
1066 *directive
= directive_none
;
1070 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1071 *directive
= top
->directive
;
1072 *negated
= top
->negated
;
1075 *datum
= top
->datum
;
1076 directive_state_stack
= top
->prev
;
1082 directive_balance (void)
1084 while (directive_state_stack
)
1086 directiveE directive
;
1087 bfd_boolean negated
;
1092 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1093 as_warn_where ((char *) file
, line
,
1094 _(".begin directive with no matching .end directive"));
1100 inside_directive (directiveE dir
)
1102 state_stackS
*top
= directive_state_stack
;
1104 while (top
&& top
->directive
!= dir
)
1107 return (top
!= NULL
);
1112 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1116 char *directive_string
;
1118 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1123 input_line_pointer
+= 3;
1126 len
= strspn (input_line_pointer
,
1127 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1129 /* This code is a hack to make .begin [no-][generics|relax] exactly
1130 equivalent to .begin [no-]transform. We should remove it when
1131 we stop accepting those options. */
1133 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1135 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1136 directive_string
= "transform";
1138 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1140 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1141 directive_string
= "transform";
1144 directive_string
= input_line_pointer
;
1146 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1148 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1150 input_line_pointer
+= len
;
1151 *directive
= (directiveE
) i
;
1152 if (*negated
&& !directive_info
[i
].can_be_negated
)
1153 as_bad (_("directive %s cannot be negated"),
1154 directive_info
[i
].name
);
1159 as_bad (_("unknown directive"));
1160 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1165 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1167 directiveE directive
;
1168 bfd_boolean negated
;
1172 get_directive (&directive
, &negated
);
1173 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1175 discard_rest_of_line ();
1179 if (cur_vinsn
.inside_bundle
)
1180 as_bad (_("directives are not valid inside bundles"));
1184 case directive_literal
:
1185 if (!inside_directive (directive_literal
))
1187 /* Previous labels go with whatever follows this directive, not with
1188 the literal, so save them now. */
1189 saved_insn_labels
= insn_labels
;
1192 as_warn (_(".begin literal is deprecated; use .literal instead"));
1193 state
= (emit_state
*) xmalloc (sizeof (emit_state
));
1194 xtensa_switch_to_literal_fragment (state
);
1195 directive_push (directive_literal
, negated
, state
);
1198 case directive_literal_prefix
:
1199 /* Have to flush pending output because a movi relaxed to an l32r
1200 might produce a literal. */
1201 md_flush_pending_output ();
1202 /* Check to see if the current fragment is a literal
1203 fragment. If it is, then this operation is not allowed. */
1204 if (generating_literals
)
1206 as_bad (_("cannot set literal_prefix inside literal fragment"));
1210 /* Allocate the literal state for this section and push
1211 onto the directive stack. */
1212 ls
= xmalloc (sizeof (lit_state
));
1215 *ls
= default_lit_sections
;
1216 directive_push (directive_literal_prefix
, negated
, ls
);
1218 /* Process the new prefix. */
1219 xtensa_literal_prefix ();
1222 case directive_freeregs
:
1223 /* This information is currently unused, but we'll accept the statement
1224 and just discard the rest of the line. This won't check the syntax,
1225 but it will accept every correct freeregs directive. */
1226 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1227 directive_push (directive_freeregs
, negated
, 0);
1230 case directive_schedule
:
1231 md_flush_pending_output ();
1232 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1233 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1234 directive_push (directive_schedule
, negated
, 0);
1235 xtensa_set_frag_assembly_state (frag_now
);
1238 case directive_density
:
1239 as_warn (_(".begin [no-]density is ignored"));
1242 case directive_absolute_literals
:
1243 md_flush_pending_output ();
1244 if (!absolute_literals_supported
&& !negated
)
1246 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1249 xtensa_set_frag_assembly_state (frag_now
);
1250 directive_push (directive
, negated
, 0);
1254 md_flush_pending_output ();
1255 xtensa_set_frag_assembly_state (frag_now
);
1256 directive_push (directive
, negated
, 0);
1260 demand_empty_rest_of_line ();
1265 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1267 directiveE begin_directive
, end_directive
;
1268 bfd_boolean begin_negated
, end_negated
;
1272 emit_state
**state_ptr
;
1275 if (cur_vinsn
.inside_bundle
)
1276 as_bad (_("directives are not valid inside bundles"));
1278 get_directive (&end_directive
, &end_negated
);
1280 md_flush_pending_output ();
1282 switch (end_directive
)
1284 case (directiveE
) XTENSA_UNDEFINED
:
1285 discard_rest_of_line ();
1288 case directive_density
:
1289 as_warn (_(".end [no-]density is ignored"));
1290 demand_empty_rest_of_line ();
1293 case directive_absolute_literals
:
1294 if (!absolute_literals_supported
&& !end_negated
)
1296 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1297 demand_empty_rest_of_line ();
1306 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1307 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1308 (const void **) state_ptr
);
1310 if (begin_directive
!= directive_none
)
1312 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1314 as_bad (_("does not match begin %s%s at %s:%d"),
1315 begin_negated
? "no-" : "",
1316 directive_info
[begin_directive
].name
, file
, line
);
1320 switch (end_directive
)
1322 case directive_literal
:
1323 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1324 xtensa_restore_emit_state (state
);
1325 xtensa_set_frag_assembly_state (frag_now
);
1327 if (!inside_directive (directive_literal
))
1329 /* Restore the list of current labels. */
1330 xtensa_clear_insn_labels ();
1331 insn_labels
= saved_insn_labels
;
1335 case directive_literal_prefix
:
1336 /* Restore the default collection sections from saved state. */
1337 s
= (lit_state
*) state
;
1339 default_lit_sections
= *s
;
1341 /* Free the state storage. */
1342 free (s
->lit_prefix
);
1346 case directive_schedule
:
1347 case directive_freeregs
:
1351 xtensa_set_frag_assembly_state (frag_now
);
1357 demand_empty_rest_of_line ();
1361 /* Place an aligned literal fragment at the current location. */
1364 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1366 md_flush_pending_output ();
1368 if (inside_directive (directive_literal
))
1369 as_warn (_(".literal_position inside literal directive; ignoring"));
1370 xtensa_mark_literal_pool_location ();
1372 demand_empty_rest_of_line ();
1373 xtensa_clear_insn_labels ();
1377 /* Support .literal label, expr, ... */
1380 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1383 char *p
, *base_name
;
1387 if (inside_directive (directive_literal
))
1389 as_bad (_(".literal not allowed inside .begin literal region"));
1390 ignore_rest_of_line ();
1394 md_flush_pending_output ();
1396 /* Previous labels go with whatever follows this directive, not with
1397 the literal, so save them now. */
1398 saved_insn_labels
= insn_labels
;
1401 /* If we are using text-section literals, then this is the right value... */
1404 base_name
= input_line_pointer
;
1406 xtensa_switch_to_literal_fragment (&state
);
1408 /* ...but if we aren't using text-section-literals, then we
1409 need to put them in the section we just switched to. */
1410 if (use_literal_section
|| directive_state
[directive_absolute_literals
])
1413 /* All literals are aligned to four-byte boundaries. */
1414 frag_align (2, 0, 0);
1415 record_alignment (now_seg
, 2);
1417 c
= get_symbol_end ();
1418 /* Just after name is now '\0'. */
1419 p
= input_line_pointer
;
1423 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1425 as_bad (_("expected comma or colon after symbol name; "
1426 "rest of line ignored"));
1427 ignore_rest_of_line ();
1428 xtensa_restore_emit_state (&state
);
1436 input_line_pointer
++; /* skip ',' or ':' */
1438 xtensa_elf_cons (4);
1440 xtensa_restore_emit_state (&state
);
1442 /* Restore the list of current labels. */
1443 xtensa_clear_insn_labels ();
1444 insn_labels
= saved_insn_labels
;
1449 xtensa_literal_prefix (void)
1454 /* Parse the new prefix from the input_line_pointer. */
1456 len
= strspn (input_line_pointer
,
1457 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1458 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1460 /* Get a null-terminated copy of the name. */
1461 name
= xmalloc (len
+ 1);
1463 strncpy (name
, input_line_pointer
, len
);
1466 /* Skip the name in the input line. */
1467 input_line_pointer
+= len
;
1469 default_lit_sections
.lit_prefix
= name
;
1471 /* Clear cached literal sections, since the prefix has changed. */
1472 default_lit_sections
.lit_seg
= NULL
;
1473 default_lit_sections
.lit4_seg
= NULL
;
1477 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1480 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1482 float fall_through_f
, target_f
;
1484 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1485 if (fall_through_f
< 0)
1487 as_bad (_("fall through frequency must be greater than 0"));
1488 ignore_rest_of_line ();
1492 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1495 as_bad (_("branch target frequency must be greater than 0"));
1496 ignore_rest_of_line ();
1500 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1502 demand_empty_rest_of_line ();
1506 /* Like normal .long/.short/.word, except support @plt, etc.
1507 Clobbers input_line_pointer, checks end-of-line. */
1510 xtensa_elf_cons (int nbytes
)
1513 bfd_reloc_code_real_type reloc
;
1515 md_flush_pending_output ();
1517 if (cur_vinsn
.inside_bundle
)
1518 as_bad (_("directives are not valid inside bundles"));
1520 if (is_it_end_of_statement ())
1522 demand_empty_rest_of_line ();
1529 if (exp
.X_op
== O_symbol
1530 && *input_line_pointer
== '@'
1531 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1534 reloc_howto_type
*reloc_howto
=
1535 bfd_reloc_type_lookup (stdoutput
, reloc
);
1537 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1538 as_bad (_("unsupported relocation"));
1539 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1540 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1541 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1542 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1543 as_bad (_("opcode-specific %s relocation used outside "
1544 "an instruction"), reloc_howto
->name
);
1545 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1546 as_bad (_("%s relocations do not fit in %d bytes"),
1547 reloc_howto
->name
, nbytes
);
1550 char *p
= frag_more ((int) nbytes
);
1551 xtensa_set_frag_assembly_state (frag_now
);
1552 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1553 nbytes
, &exp
, 0, reloc
);
1557 emit_expr (&exp
, (unsigned int) nbytes
);
1559 while (*input_line_pointer
++ == ',');
1561 input_line_pointer
--; /* Put terminator back into stream. */
1562 demand_empty_rest_of_line ();
1566 /* Parsing and Idiom Translation. */
1568 /* Parse @plt, etc. and return the desired relocation. */
1569 static bfd_reloc_code_real_type
1570 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1577 struct suffix_reloc_map
*ptr
;
1580 return BFD_RELOC_NONE
;
1582 for (ch
= *str
, str2
= ident
;
1583 (str2
< ident
+ sizeof (ident
) - 1
1584 && (ISALNUM (ch
) || ch
== '@'));
1587 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1594 for (ptr
= &suffix_relocs
[0]; ptr
->length
> 0; ptr
++)
1595 if (ch
== ptr
->suffix
[0]
1596 && len
== ptr
->length
1597 && memcmp (ident
, ptr
->suffix
, ptr
->length
) == 0)
1599 /* Now check for "identifier@suffix+constant". */
1600 if (*str
== '-' || *str
== '+')
1602 char *orig_line
= input_line_pointer
;
1603 expressionS new_exp
;
1605 input_line_pointer
= str
;
1606 expression (&new_exp
);
1607 if (new_exp
.X_op
== O_constant
)
1609 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1610 str
= input_line_pointer
;
1613 if (&input_line_pointer
!= str_p
)
1614 input_line_pointer
= orig_line
;
1621 return BFD_RELOC_UNUSED
;
1625 /* Find the matching operator type. */
1626 static unsigned char
1627 map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc
)
1629 struct suffix_reloc_map
*sfx
;
1630 unsigned char operator = (unsigned char) -1;
1632 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1634 if (sfx
->reloc
== reloc
)
1636 operator = sfx
->operator;
1640 assert (operator != (unsigned char) -1);
1645 /* Find the matching reloc type. */
1646 static bfd_reloc_code_real_type
1647 map_operator_to_reloc (unsigned char operator)
1649 struct suffix_reloc_map
*sfx
;
1650 bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
1652 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1654 if (sfx
->operator == operator)
1661 if (reloc
== BFD_RELOC_UNUSED
)
1662 return BFD_RELOC_32
;
1669 expression_end (const char *name
)
1692 #define ERROR_REG_NUM ((unsigned) -1)
1695 tc_get_register (const char *prefix
)
1698 const char *next_expr
;
1699 const char *old_line_pointer
;
1702 old_line_pointer
= input_line_pointer
;
1704 if (*input_line_pointer
== '$')
1705 ++input_line_pointer
;
1707 /* Accept "sp" as a synonym for "a1". */
1708 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1709 && expression_end (input_line_pointer
+ 2))
1711 input_line_pointer
+= 2;
1712 return 1; /* AR[1] */
1715 while (*input_line_pointer
++ == *prefix
++)
1717 --input_line_pointer
;
1722 as_bad (_("bad register name: %s"), old_line_pointer
);
1723 return ERROR_REG_NUM
;
1726 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1728 as_bad (_("bad register number: %s"), input_line_pointer
);
1729 return ERROR_REG_NUM
;
1734 while (ISDIGIT ((int) *input_line_pointer
))
1735 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1737 if (!(next_expr
= expression_end (input_line_pointer
)))
1739 as_bad (_("bad register name: %s"), old_line_pointer
);
1740 return ERROR_REG_NUM
;
1743 input_line_pointer
= (char *) next_expr
;
1750 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1752 xtensa_isa isa
= xtensa_default_isa
;
1754 /* Check if this is an immediate operand. */
1755 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1757 bfd_reloc_code_real_type reloc
;
1758 segT t
= expression (tok
);
1759 if (t
== absolute_section
1760 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1762 assert (tok
->X_op
== O_constant
);
1763 tok
->X_op
= O_symbol
;
1764 tok
->X_add_symbol
= &abs_symbol
;
1767 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1768 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1771 if (reloc
== BFD_RELOC_UNUSED
)
1773 as_bad (_("unsupported relocation"));
1777 if (tok
->X_op
== O_constant
)
1781 case BFD_RELOC_LO16
:
1782 tok
->X_add_number
&= 0xffff;
1785 case BFD_RELOC_HI16
:
1786 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1793 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
1798 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1799 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1801 if (reg
!= ERROR_REG_NUM
) /* Already errored */
1804 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
1805 as_bad (_("register number out of range"));
1808 tok
->X_op
= O_register
;
1809 tok
->X_add_symbol
= 0;
1810 tok
->X_add_number
= reg
;
1815 /* Split up the arguments for an opcode or pseudo-op. */
1818 tokenize_arguments (char **args
, char *str
)
1820 char *old_input_line_pointer
;
1821 bfd_boolean saw_comma
= FALSE
;
1822 bfd_boolean saw_arg
= FALSE
;
1823 bfd_boolean saw_colon
= FALSE
;
1825 char *arg_end
, *arg
;
1828 /* Save and restore input_line_pointer around this function. */
1829 old_input_line_pointer
= input_line_pointer
;
1830 input_line_pointer
= str
;
1832 while (*input_line_pointer
)
1835 switch (*input_line_pointer
)
1842 input_line_pointer
++;
1843 if (saw_comma
|| saw_colon
|| !saw_arg
)
1849 input_line_pointer
++;
1850 if (saw_comma
|| saw_colon
|| !saw_arg
)
1856 if (!saw_comma
&& !saw_colon
&& saw_arg
)
1859 arg_end
= input_line_pointer
+ 1;
1860 while (!expression_end (arg_end
))
1863 arg_len
= arg_end
- input_line_pointer
;
1864 arg
= (char *) xmalloc ((saw_colon
? 1 : 0) + arg_len
+ 1);
1865 args
[num_args
] = arg
;
1869 strncpy (arg
, input_line_pointer
, arg_len
);
1870 arg
[arg_len
] = '\0';
1872 input_line_pointer
= arg_end
;
1882 if (saw_comma
|| saw_colon
)
1884 input_line_pointer
= old_input_line_pointer
;
1889 as_bad (_("extra comma"));
1891 as_bad (_("extra colon"));
1893 as_bad (_("missing argument"));
1895 as_bad (_("missing comma or colon"));
1896 input_line_pointer
= old_input_line_pointer
;
1901 /* Parse the arguments to an opcode. Return TRUE on error. */
1904 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
1906 expressionS
*tok
, *last_tok
;
1907 xtensa_opcode opcode
= insn
->opcode
;
1908 bfd_boolean had_error
= TRUE
;
1909 xtensa_isa isa
= xtensa_default_isa
;
1910 int n
, num_regs
= 0;
1911 int opcode_operand_count
;
1912 int opnd_cnt
, last_opnd_cnt
;
1913 unsigned int next_reg
= 0;
1914 char *old_input_line_pointer
;
1916 if (insn
->insn_type
== ITYPE_LITERAL
)
1917 opcode_operand_count
= 1;
1919 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
1922 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
1924 /* Save and restore input_line_pointer around this function. */
1925 old_input_line_pointer
= input_line_pointer
;
1931 /* Skip invisible operands. */
1932 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
1938 for (n
= 0; n
< num_args
; n
++)
1940 input_line_pointer
= arg_strings
[n
];
1941 if (*input_line_pointer
== ':')
1943 xtensa_regfile opnd_rf
;
1944 input_line_pointer
++;
1947 assert (opnd_cnt
> 0);
1949 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
1951 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
1952 as_warn (_("incorrect register number, ignoring"));
1957 if (opnd_cnt
>= opcode_operand_count
)
1959 as_warn (_("too many arguments"));
1962 assert (opnd_cnt
< MAX_INSN_ARGS
);
1964 expression_maybe_register (opcode
, opnd_cnt
, tok
);
1965 next_reg
= tok
->X_add_number
+ 1;
1967 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
1969 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
1971 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
1972 /* minus 1 because we are seeing one right now */
1978 last_opnd_cnt
= opnd_cnt
;
1985 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
1989 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
1992 insn
->ntok
= tok
- insn
->tok
;
1996 input_line_pointer
= old_input_line_pointer
;
2002 get_invisible_operands (TInsn
*insn
)
2004 xtensa_isa isa
= xtensa_default_isa
;
2005 static xtensa_insnbuf slotbuf
= NULL
;
2007 xtensa_opcode opc
= insn
->opcode
;
2008 int slot
, opnd
, fmt_found
;
2012 slotbuf
= xtensa_insnbuf_alloc (isa
);
2014 /* Find format/slot where this can be encoded. */
2017 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2019 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2021 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2027 if (fmt_found
) break;
2032 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2036 /* First encode all the visible operands
2037 (to deal with shared field operands). */
2038 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2040 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2041 && (insn
->tok
[opnd
].X_op
== O_register
2042 || insn
->tok
[opnd
].X_op
== O_constant
))
2044 val
= insn
->tok
[opnd
].X_add_number
;
2045 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2046 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2050 /* Then pull out the values for the invisible ones. */
2051 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2053 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2055 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2056 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2057 insn
->tok
[opnd
].X_add_number
= val
;
2058 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2059 insn
->tok
[opnd
].X_op
= O_register
;
2061 insn
->tok
[opnd
].X_op
= O_constant
;
2070 xg_reverse_shift_count (char **cnt_argp
)
2072 char *cnt_arg
, *new_arg
;
2073 cnt_arg
= *cnt_argp
;
2075 /* replace the argument with "31-(argument)" */
2076 new_arg
= (char *) xmalloc (strlen (cnt_arg
) + 6);
2077 sprintf (new_arg
, "31-(%s)", cnt_arg
);
2080 *cnt_argp
= new_arg
;
2084 /* If "arg" is a constant expression, return non-zero with the value
2088 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2091 char *save_ptr
= input_line_pointer
;
2093 input_line_pointer
= arg
;
2095 input_line_pointer
= save_ptr
;
2097 if (exp
.X_op
== O_constant
)
2099 *valp
= exp
.X_add_number
;
2108 xg_replace_opname (char **popname
, char *newop
)
2111 *popname
= (char *) xmalloc (strlen (newop
) + 1);
2112 strcpy (*popname
, newop
);
2117 xg_check_num_args (int *pnum_args
,
2122 int num_args
= *pnum_args
;
2124 if (num_args
< expected_num
)
2126 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2127 num_args
, opname
, expected_num
);
2131 if (num_args
> expected_num
)
2133 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2134 num_args
, opname
, expected_num
);
2135 while (num_args
-- > expected_num
)
2137 free (arg_strings
[num_args
]);
2138 arg_strings
[num_args
] = 0;
2140 *pnum_args
= expected_num
;
2148 /* If the register is not specified as part of the opcode,
2149 then get it from the operand and move it to the opcode. */
2152 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2154 xtensa_isa isa
= xtensa_default_isa
;
2156 char *opname
, *new_opname
;
2157 const char *sr_name
;
2158 int is_user
, is_write
;
2163 is_user
= (opname
[1] == 'u');
2164 is_write
= (opname
[0] == 'w');
2166 /* Opname == [rw]ur or [rwx]sr... */
2168 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2171 /* Check if the argument is a symbolic register name. */
2172 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2173 /* Handle WSR to "INTSET" as a special case. */
2174 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2175 && !strcasecmp (arg_strings
[1], "intset"))
2176 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2177 if (sr
== XTENSA_UNDEFINED
2178 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2180 /* Maybe it's a register number.... */
2182 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2184 as_bad (_("invalid register '%s' for '%s' instruction"),
2185 arg_strings
[1], opname
);
2188 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2189 if (sr
== XTENSA_UNDEFINED
)
2191 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2192 (long) val
, opname
);
2197 /* Remove the last argument, which is now part of the opcode. */
2198 free (arg_strings
[1]);
2202 /* Translate the opcode. */
2203 sr_name
= xtensa_sysreg_name (isa
, sr
);
2204 /* Another special case for "WSR.INTSET".... */
2205 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2207 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2208 sprintf (new_opname
, "%s.%s", *popname
, sr_name
);
2210 *popname
= new_opname
;
2217 xtensa_translate_old_userreg_ops (char **popname
)
2219 xtensa_isa isa
= xtensa_default_isa
;
2221 char *opname
, *new_opname
;
2222 const char *sr_name
;
2223 bfd_boolean has_underbar
= FALSE
;
2226 if (opname
[0] == '_')
2228 has_underbar
= TRUE
;
2232 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2233 if (sr
!= XTENSA_UNDEFINED
)
2235 /* The new default name ("nnn") is different from the old default
2236 name ("URnnn"). The old default is handled below, and we don't
2237 want to recognize [RW]nnn, so do nothing if the name is the (new)
2239 static char namebuf
[10];
2240 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2241 if (strcmp (namebuf
, opname
+ 1) == 0)
2249 /* Only continue if the reg name is "URnnn". */
2250 if (opname
[1] != 'u' || opname
[2] != 'r')
2252 val
= strtoul (opname
+ 3, &end
, 10);
2256 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2257 if (sr
== XTENSA_UNDEFINED
)
2259 as_bad (_("invalid register number (%ld) for '%s'"),
2260 (long) val
, opname
);
2265 /* Translate the opcode. */
2266 sr_name
= xtensa_sysreg_name (isa
, sr
);
2267 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2268 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2269 opname
[0], sr_name
);
2271 *popname
= new_opname
;
2278 xtensa_translate_zero_immed (char *old_op
,
2288 assert (opname
[0] != '_');
2290 if (strcmp (opname
, old_op
) != 0)
2293 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2295 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2297 xg_replace_opname (popname
, new_op
);
2298 free (arg_strings
[1]);
2299 arg_strings
[1] = arg_strings
[2];
2308 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2309 Returns non-zero if an error was found. */
2312 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2314 char *opname
= *popname
;
2315 bfd_boolean has_underbar
= FALSE
;
2319 has_underbar
= TRUE
;
2323 if (strcmp (opname
, "mov") == 0)
2325 if (use_transform () && !has_underbar
&& density_supported
)
2326 xg_replace_opname (popname
, "mov.n");
2329 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2331 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2332 arg_strings
[2] = (char *) xmalloc (strlen (arg_strings
[1]) + 1);
2333 strcpy (arg_strings
[2], arg_strings
[1]);
2339 if (strcmp (opname
, "bbsi.l") == 0)
2341 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2343 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2344 if (target_big_endian
)
2345 xg_reverse_shift_count (&arg_strings
[1]);
2349 if (strcmp (opname
, "bbci.l") == 0)
2351 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2353 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2354 if (target_big_endian
)
2355 xg_reverse_shift_count (&arg_strings
[1]);
2359 /* Don't do anything special with NOPs inside FLIX instructions. They
2360 are handled elsewhere. Real NOP instructions are always available
2361 in configurations with FLIX, so this should never be an issue but
2362 check for it anyway. */
2363 if (!cur_vinsn
.inside_bundle
&& xtensa_nop_opcode
== XTENSA_UNDEFINED
2364 && strcmp (opname
, "nop") == 0)
2366 if (use_transform () && !has_underbar
&& density_supported
)
2367 xg_replace_opname (popname
, "nop.n");
2370 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2372 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2373 arg_strings
[0] = (char *) xmalloc (3);
2374 arg_strings
[1] = (char *) xmalloc (3);
2375 arg_strings
[2] = (char *) xmalloc (3);
2376 strcpy (arg_strings
[0], "a1");
2377 strcpy (arg_strings
[1], "a1");
2378 strcpy (arg_strings
[2], "a1");
2384 /* Recognize [RW]UR and [RWX]SR. */
2385 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2386 && (opname
[1] == 'u' || opname
[1] == 's'))
2387 || (opname
[0] == 'x' && opname
[1] == 's'))
2389 && opname
[3] == '\0')
2390 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2392 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2393 [RW]<name> if <name> is the non-default name of a user register. */
2394 if ((opname
[0] == 'r' || opname
[0] == 'w')
2395 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2396 return xtensa_translate_old_userreg_ops (popname
);
2398 /* Relax branches that don't allow comparisons against an immediate value
2399 of zero to the corresponding branches with implicit zero immediates. */
2400 if (!has_underbar
&& use_transform ())
2402 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2403 pnum_args
, arg_strings
))
2406 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2407 pnum_args
, arg_strings
))
2410 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2411 pnum_args
, arg_strings
))
2414 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2415 pnum_args
, arg_strings
))
2423 /* Functions for dealing with the Xtensa ISA. */
2425 /* Currently the assembler only allows us to use a single target per
2426 fragment. Because of this, only one operand for a given
2427 instruction may be symbolic. If there is a PC-relative operand,
2428 the last one is chosen. Otherwise, the result is the number of the
2429 last immediate operand, and if there are none of those, we fail and
2433 get_relaxable_immed (xtensa_opcode opcode
)
2435 int last_immed
= -1;
2438 if (opcode
== XTENSA_UNDEFINED
)
2441 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2442 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2444 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2446 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2448 if (last_immed
== -1
2449 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2456 static xtensa_opcode
2457 get_opcode_from_buf (const char *buf
, int slot
)
2459 static xtensa_insnbuf insnbuf
= NULL
;
2460 static xtensa_insnbuf slotbuf
= NULL
;
2461 xtensa_isa isa
= xtensa_default_isa
;
2466 insnbuf
= xtensa_insnbuf_alloc (isa
);
2467 slotbuf
= xtensa_insnbuf_alloc (isa
);
2470 xtensa_insnbuf_from_chars (isa
, insnbuf
, (const unsigned char *) buf
, 0);
2471 fmt
= xtensa_format_decode (isa
, insnbuf
);
2472 if (fmt
== XTENSA_UNDEFINED
)
2473 return XTENSA_UNDEFINED
;
2475 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2476 return XTENSA_UNDEFINED
;
2478 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2479 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2483 #ifdef TENSILICA_DEBUG
2485 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2488 xtensa_print_insn_table (void)
2490 int num_opcodes
, num_operands
;
2491 xtensa_opcode opcode
;
2492 xtensa_isa isa
= xtensa_default_isa
;
2494 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2495 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2498 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2499 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2500 for (opn
= 0; opn
< num_operands
; opn
++)
2502 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2504 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2506 xtensa_regfile opnd_rf
=
2507 xtensa_operand_regfile (isa
, opcode
, opn
);
2508 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2510 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2511 fputs ("[lLr] ", stderr
);
2513 fputs ("i ", stderr
);
2515 fprintf (stderr
, "\n");
2521 print_vliw_insn (xtensa_insnbuf vbuf
)
2523 xtensa_isa isa
= xtensa_default_isa
;
2524 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2525 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2528 fprintf (stderr
, "format = %d\n", f
);
2530 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2532 xtensa_opcode opcode
;
2536 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2537 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2538 opname
= xtensa_opcode_name (isa
, opcode
);
2540 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2541 fprintf (stderr
, " operands = ");
2543 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2547 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2549 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2550 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2551 fprintf (stderr
, "%d ", val
);
2553 fprintf (stderr
, "\n");
2555 xtensa_insnbuf_free (isa
, sbuf
);
2558 #endif /* TENSILICA_DEBUG */
2562 is_direct_call_opcode (xtensa_opcode opcode
)
2564 xtensa_isa isa
= xtensa_default_isa
;
2565 int n
, num_operands
;
2567 if (xtensa_opcode_is_call (isa
, opcode
) != 1)
2570 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2571 for (n
= 0; n
< num_operands
; n
++)
2573 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2574 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2581 /* Convert from BFD relocation type code to slot and operand number.
2582 Returns non-zero on failure. */
2585 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2587 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2588 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2590 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2593 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2594 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2596 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2606 /* Convert from slot number to BFD relocation type code for the
2607 standard PC-relative relocations. Return BFD_RELOC_NONE on
2610 static bfd_reloc_code_real_type
2611 encode_reloc (int slot
)
2613 if (slot
< 0 || slot
> 14)
2614 return BFD_RELOC_NONE
;
2616 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2620 /* Convert from slot numbers to BFD relocation type code for the
2621 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2623 static bfd_reloc_code_real_type
2624 encode_alt_reloc (int slot
)
2626 if (slot
< 0 || slot
> 14)
2627 return BFD_RELOC_NONE
;
2629 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2634 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2637 xtensa_opcode opcode
,
2643 uint32 valbuf
= value
;
2645 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2647 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2649 as_bad_where ((char *) file
, line
,
2650 _("operand %d of '%s' has out of range value '%u'"),
2652 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2655 as_bad_where ((char *) file
, line
,
2656 _("operand %d of '%s' has invalid value '%u'"),
2658 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2663 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2669 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2672 xtensa_opcode opcode
,
2676 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2677 fmt
, slot
, slotbuf
, &val
);
2678 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2683 /* Checks for rules from xtensa-relax tables. */
2685 /* The routine xg_instruction_matches_option_term must return TRUE
2686 when a given option term is true. The meaning of all of the option
2687 terms is given interpretation by this function. This is needed when
2688 an option depends on the state of a directive, but there are no such
2689 options in use right now. */
2692 xg_instruction_matches_option_term (TInsn
*insn ATTRIBUTE_UNUSED
,
2693 const ReqOrOption
*option
)
2695 if (strcmp (option
->option_name
, "realnop") == 0
2696 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2698 /* These conditions were evaluated statically when building the
2699 relaxation table. There's no need to reevaluate them now. */
2704 as_fatal (_("internal error: unknown option name '%s'"),
2705 option
->option_name
);
2711 xg_instruction_matches_or_options (TInsn
*insn
,
2712 const ReqOrOptionList
*or_option
)
2714 const ReqOrOption
*option
;
2715 /* Must match each of the AND terms. */
2716 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2718 if (xg_instruction_matches_option_term (insn
, option
))
2726 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2728 const ReqOption
*req_options
;
2729 /* Must match each of the AND terms. */
2730 for (req_options
= options
;
2731 req_options
!= NULL
;
2732 req_options
= req_options
->next
)
2734 /* Must match one of the OR clauses. */
2735 if (!xg_instruction_matches_or_options (insn
,
2736 req_options
->or_option_terms
))
2743 /* Return the transition rule that matches or NULL if none matches. */
2746 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2748 PreconditionList
*condition_l
;
2750 if (rule
->opcode
!= insn
->opcode
)
2753 for (condition_l
= rule
->conditions
;
2754 condition_l
!= NULL
;
2755 condition_l
= condition_l
->next
)
2759 Precondition
*cond
= condition_l
->precond
;
2764 /* The expression must be the constant. */
2765 assert (cond
->op_num
< insn
->ntok
);
2766 exp1
= &insn
->tok
[cond
->op_num
];
2767 if (expr_is_const (exp1
))
2772 if (get_expr_const (exp1
) != cond
->op_data
)
2776 if (get_expr_const (exp1
) == cond
->op_data
)
2783 else if (expr_is_register (exp1
))
2788 if (get_expr_register (exp1
) != cond
->op_data
)
2792 if (get_expr_register (exp1
) == cond
->op_data
)
2804 assert (cond
->op_num
< insn
->ntok
);
2805 assert (cond
->op_data
< insn
->ntok
);
2806 exp1
= &insn
->tok
[cond
->op_num
];
2807 exp2
= &insn
->tok
[cond
->op_data
];
2812 if (!expr_is_equal (exp1
, exp2
))
2816 if (expr_is_equal (exp1
, exp2
))
2828 if (!xg_instruction_matches_options (insn
, rule
->options
))
2836 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
2838 bfd_boolean a_greater
= FALSE
;
2839 bfd_boolean b_greater
= FALSE
;
2841 ReqOptionList
*l_a
= a
->options
;
2842 ReqOptionList
*l_b
= b
->options
;
2844 /* We only care if they both are the same except for
2845 a const16 vs. an l32r. */
2847 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2849 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
2850 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
2851 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2853 if (l_or_a
->is_true
!= l_or_b
->is_true
)
2855 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
2857 /* This is the case we care about. */
2858 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
2859 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
2866 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
2867 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
2877 l_or_a
= l_or_a
->next
;
2878 l_or_b
= l_or_b
->next
;
2880 if (l_or_a
|| l_or_b
)
2889 /* Incomparable if the substitution was used differently in two cases. */
2890 if (a_greater
&& b_greater
)
2902 static TransitionRule
*
2903 xg_instruction_match (TInsn
*insn
)
2905 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
2907 assert (insn
->opcode
< table
->num_opcodes
);
2909 /* Walk through all of the possible transitions. */
2910 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2912 TransitionRule
*rule
= l
->rule
;
2913 if (xg_instruction_matches_rule (insn
, rule
))
2920 /* Various Other Internal Functions. */
2923 is_unique_insn_expansion (TransitionRule
*r
)
2925 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
2927 if (r
->to_instr
->typ
!= INSTR_INSTR
)
2933 /* Check if there is exactly one relaxation for INSN that converts it to
2934 another instruction of equal or larger size. If so, and if TARG is
2935 non-null, go ahead and generate the relaxed instruction into TARG. If
2936 NARROW_ONLY is true, then only consider relaxations that widen a narrow
2937 instruction, i.e., ignore relaxations that convert to an instruction of
2938 equal size. In some contexts where this function is used, only
2939 a single widening is allowed and the NARROW_ONLY argument is used to
2940 exclude cases like ADDI being "widened" to an ADDMI, which may
2941 later be relaxed to an ADDMI/ADDI pair. */
2944 xg_is_single_relaxable_insn (TInsn
*insn
, TInsn
*targ
, bfd_boolean narrow_only
)
2946 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
2948 TransitionRule
*match
= 0;
2950 assert (insn
->insn_type
== ITYPE_INSN
);
2951 assert (insn
->opcode
< table
->num_opcodes
);
2953 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2955 TransitionRule
*rule
= l
->rule
;
2957 if (xg_instruction_matches_rule (insn
, rule
)
2958 && is_unique_insn_expansion (rule
)
2959 && (xg_get_single_size (insn
->opcode
) + (narrow_only
? 1 : 0)
2960 <= xg_get_single_size (rule
->to_instr
->opcode
)))
2971 xg_build_to_insn (targ
, insn
, match
->to_instr
);
2976 /* Return the maximum number of bytes this opcode can expand to. */
2979 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
2981 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
2983 int max_size
= xg_get_single_size (opcode
);
2985 assert (opcode
< table
->num_opcodes
);
2987 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
2989 TransitionRule
*rule
= l
->rule
;
2990 BuildInstr
*build_list
;
2995 build_list
= rule
->to_instr
;
2996 if (is_unique_insn_expansion (rule
))
2998 assert (build_list
->typ
== INSTR_INSTR
);
2999 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
3002 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3004 switch (build_list
->typ
)
3007 this_size
+= xg_get_single_size (build_list
->opcode
);
3009 case INSTR_LITERAL_DEF
:
3010 case INSTR_LABEL_DEF
:
3015 if (this_size
> max_size
)
3016 max_size
= this_size
;
3022 /* Return the maximum number of literal bytes this opcode can generate. */
3025 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3027 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3031 assert (opcode
< table
->num_opcodes
);
3033 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3035 TransitionRule
*rule
= l
->rule
;
3036 BuildInstr
*build_list
;
3041 build_list
= rule
->to_instr
;
3042 if (is_unique_insn_expansion (rule
))
3044 assert (build_list
->typ
== INSTR_INSTR
);
3045 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3048 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3050 switch (build_list
->typ
)
3052 case INSTR_LITERAL_DEF
:
3053 /* Hard-coded 4-byte literal. */
3057 case INSTR_LABEL_DEF
:
3062 if (this_size
> max_size
)
3063 max_size
= this_size
;
3070 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3072 int steps_taken
= 0;
3073 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3076 assert (insn
->insn_type
== ITYPE_INSN
);
3077 assert (insn
->opcode
< table
->num_opcodes
);
3079 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3081 TransitionRule
*rule
= l
->rule
;
3083 if (xg_instruction_matches_rule (insn
, rule
))
3085 if (steps_taken
== lateral_steps
)
3095 get_special_literal_symbol (void)
3097 static symbolS
*sym
= NULL
;
3100 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3106 get_special_label_symbol (void)
3108 static symbolS
*sym
= NULL
;
3111 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3117 xg_valid_literal_expression (const expressionS
*exp
)
3134 /* This will check to see if the value can be converted into the
3135 operand type. It will return TRUE if it does not fit. */
3138 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3140 uint32 valbuf
= value
;
3141 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3147 /* Assumes: All immeds are constants. Check that all constants fit
3148 into their immeds; return FALSE if not. */
3151 xg_immeds_fit (const TInsn
*insn
)
3153 xtensa_isa isa
= xtensa_default_isa
;
3157 assert (insn
->insn_type
== ITYPE_INSN
);
3158 for (i
= 0; i
< n
; ++i
)
3160 const expressionS
*expr
= &insn
->tok
[i
];
3161 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3168 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3173 /* The symbol should have a fixup associated with it. */
3182 /* This should only be called after we have an initial
3183 estimate of the addresses. */
3186 xg_symbolic_immeds_fit (const TInsn
*insn
,
3192 xtensa_isa isa
= xtensa_default_isa
;
3200 assert (insn
->insn_type
== ITYPE_INSN
);
3202 for (i
= 0; i
< n
; ++i
)
3204 const expressionS
*expr
= &insn
->tok
[i
];
3205 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3212 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3218 /* Check for the worst case. */
3219 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3224 /* We only allow symbols for PC-relative references.
3225 If pc_frag == 0, then we don't have frag locations yet. */
3227 || xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0)
3230 /* If it is a weak symbol, then assume it won't reach. */
3231 if (S_IS_WEAK (expr
->X_add_symbol
))
3234 if (is_direct_call_opcode (insn
->opcode
)
3235 && ! pc_frag
->tc_frag_data
.use_longcalls
)
3237 /* If callee is undefined or in a different segment, be
3238 optimistic and assume it will be in range. */
3239 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3243 /* Only references within a segment can be known to fit in the
3244 operands at assembly time. */
3245 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3248 symbolP
= expr
->X_add_symbol
;
3249 sym_frag
= symbol_get_frag (symbolP
);
3250 target
= S_GET_VALUE (symbolP
) + expr
->X_add_number
;
3251 pc
= pc_frag
->fr_address
+ pc_offset
;
3253 /* If frag has yet to be reached on this pass, assume it
3254 will move by STRETCH just as we did. If this is not so,
3255 it will be because some frag between grows, and that will
3256 force another pass. Beware zero-length frags. There
3257 should be a faster way to do this. */
3260 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3261 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3266 new_offset
= target
;
3267 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3268 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3273 /* The symbol should have a fixup associated with it. */
3282 /* Return TRUE on success. */
3285 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3291 targ
->debug_line
= insn
->debug_line
;
3292 targ
->loc_directive_seen
= insn
->loc_directive_seen
;
3297 targ
->opcode
= bi
->opcode
;
3298 targ
->insn_type
= ITYPE_INSN
;
3299 targ
->is_specific_opcode
= FALSE
;
3301 for (; op
!= NULL
; op
= op
->next
)
3303 int op_num
= op
->op_num
;
3304 int op_data
= op
->op_data
;
3306 assert (op
->op_num
< MAX_INSN_ARGS
);
3308 if (targ
->ntok
<= op_num
)
3309 targ
->ntok
= op_num
+ 1;
3314 set_expr_const (&targ
->tok
[op_num
], op_data
);
3317 assert (op_data
< insn
->ntok
);
3318 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3321 sym
= get_special_literal_symbol ();
3322 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3325 sym
= get_special_label_symbol ();
3326 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3328 case OP_OPERAND_HI16U
:
3329 case OP_OPERAND_LOW16U
:
3330 assert (op_data
< insn
->ntok
);
3331 if (expr_is_const (&insn
->tok
[op_data
]))
3334 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3335 val
= xg_apply_userdef_op_fn (op
->typ
,
3338 targ
->tok
[op_num
].X_add_number
= val
;
3342 /* For const16 we can create relocations for these. */
3343 if (targ
->opcode
== XTENSA_UNDEFINED
3344 || (targ
->opcode
!= xtensa_const16_opcode
))
3346 assert (op_data
< insn
->ntok
);
3347 /* Need to build a O_lo16 or O_hi16. */
3348 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3349 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3351 if (op
->typ
== OP_OPERAND_HI16U
)
3352 targ
->tok
[op_num
].X_op
= O_hi16
;
3353 else if (op
->typ
== OP_OPERAND_LOW16U
)
3354 targ
->tok
[op_num
].X_op
= O_lo16
;
3361 /* currently handles:
3364 OP_OPERAND_F32MINUS */
3365 if (xg_has_userdef_op_fn (op
->typ
))
3367 assert (op_data
< insn
->ntok
);
3368 if (expr_is_const (&insn
->tok
[op_data
]))
3371 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3372 val
= xg_apply_userdef_op_fn (op
->typ
,
3375 targ
->tok
[op_num
].X_add_number
= val
;
3378 return FALSE
; /* We cannot use a relocation for this. */
3387 case INSTR_LITERAL_DEF
:
3389 targ
->opcode
= XTENSA_UNDEFINED
;
3390 targ
->insn_type
= ITYPE_LITERAL
;
3391 targ
->is_specific_opcode
= FALSE
;
3392 for (; op
!= NULL
; op
= op
->next
)
3394 int op_num
= op
->op_num
;
3395 int op_data
= op
->op_data
;
3396 assert (op
->op_num
< MAX_INSN_ARGS
);
3398 if (targ
->ntok
<= op_num
)
3399 targ
->ntok
= op_num
+ 1;
3404 assert (op_data
< insn
->ntok
);
3405 /* We can only pass resolvable literals through. */
3406 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3408 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3420 case INSTR_LABEL_DEF
:
3422 targ
->opcode
= XTENSA_UNDEFINED
;
3423 targ
->insn_type
= ITYPE_LABEL
;
3424 targ
->is_specific_opcode
= FALSE
;
3425 /* Literal with no ops is a label? */
3426 assert (op
== NULL
);
3437 /* Return TRUE on success. */
3440 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3442 for (; bi
!= NULL
; bi
= bi
->next
)
3444 TInsn
*next_insn
= istack_push_space (istack
);
3446 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3453 /* Return TRUE on valid expansion. */
3456 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3458 int stack_size
= istack
->ninsn
;
3459 int steps_taken
= 0;
3460 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3463 assert (insn
->insn_type
== ITYPE_INSN
);
3464 assert (insn
->opcode
< table
->num_opcodes
);
3466 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3468 TransitionRule
*rule
= l
->rule
;
3470 if (xg_instruction_matches_rule (insn
, rule
))
3472 if (lateral_steps
== steps_taken
)
3476 /* This is it. Expand the rule to the stack. */
3477 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3480 /* Check to see if it fits. */
3481 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3483 TInsn
*insn
= &istack
->insn
[i
];
3485 if (insn
->insn_type
== ITYPE_INSN
3486 && !tinsn_has_symbolic_operands (insn
)
3487 && !xg_immeds_fit (insn
))
3489 istack
->ninsn
= stack_size
;
3502 /* Relax the assembly instruction at least "min_steps".
3503 Return the number of steps taken.
3505 For relaxation to correctly terminate, every relaxation chain must
3506 terminate in one of two ways:
3508 1. If the chain from one instruction to the next consists entirely of
3509 single instructions, then the chain *must* handle all possible
3510 immediates without failing. It must not ever fail because an
3511 immediate is out of range. The MOVI.N -> MOVI -> L32R relaxation
3512 chain is one example. L32R loads 32 bits, and there cannot be an
3513 immediate larger than 32 bits, so it satisfies this condition.
3514 Single instruction relaxation chains are as defined by
3515 xg_is_single_relaxable_instruction.
3517 2. Otherwise, the chain must end in a multi-instruction expansion: e.g.,
3518 BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J
3520 Strictly speaking, in most cases you can violate condition 1 and be OK
3521 -- in particular when the last two instructions have the same single
3522 size. But nevertheless, you should guarantee the above two conditions.
3524 We could fix this so that single-instruction expansions correctly
3525 terminate when they can't handle the range, but the error messages are
3526 worse, and it actually turns out that in every case but one (18-bit wide
3527 branches), you need a multi-instruction expansion to get the full range
3528 anyway. And because 18-bit branches are handled identically to 15-bit
3529 branches, there isn't any point in changing it. */
3532 xg_assembly_relax (IStack
*istack
,
3535 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3536 offsetT pc_offset
, /* offset in fragment */
3537 int min_steps
, /* minimum conversion steps */
3538 long stretch
) /* number of bytes stretched so far */
3540 int steps_taken
= 0;
3542 /* Some of its immeds don't fit. Try to build a relaxed version.
3543 This may go through a couple of stages of single instruction
3544 transformations before we get there. */
3546 TInsn single_target
;
3548 int lateral_steps
= 0;
3549 int istack_size
= istack
->ninsn
;
3551 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3552 && steps_taken
>= min_steps
)
3554 istack_push (istack
, insn
);
3557 current_insn
= *insn
;
3559 /* Walk through all of the single instruction expansions. */
3560 while (xg_is_single_relaxable_insn (¤t_insn
, &single_target
, FALSE
))
3563 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3566 if (steps_taken
>= min_steps
)
3568 istack_push (istack
, &single_target
);
3572 current_insn
= single_target
;
3575 /* Now check for a multi-instruction expansion. */
3576 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3578 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3581 if (steps_taken
>= min_steps
)
3583 istack_push (istack
, ¤t_insn
);
3588 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3590 if (steps_taken
>= min_steps
)
3594 istack
->ninsn
= istack_size
;
3597 /* It's not going to work -- use the original. */
3598 istack_push (istack
, insn
);
3604 xg_force_frag_space (int size
)
3606 /* This may have the side effect of creating a new fragment for the
3607 space to go into. I just do not like the name of the "frag"
3614 xg_finish_frag (char *last_insn
,
3615 enum xtensa_relax_statesE frag_state
,
3616 enum xtensa_relax_statesE slot0_state
,
3618 bfd_boolean is_insn
)
3620 /* Finish off this fragment so that it has at LEAST the desired
3621 max_growth. If it doesn't fit in this fragment, close this one
3622 and start a new one. In either case, return a pointer to the
3623 beginning of the growth area. */
3627 xg_force_frag_space (max_growth
);
3629 old_frag
= frag_now
;
3631 frag_now
->fr_opcode
= last_insn
;
3633 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3635 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3636 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3638 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3639 xtensa_set_frag_assembly_state (frag_now
);
3641 /* Just to make sure that we did not split it up. */
3642 assert (old_frag
->fr_next
== frag_now
);
3646 /* Return TRUE if the target frag is one of the next non-empty frags. */
3649 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3654 for (; fragP
; fragP
= fragP
->fr_next
)
3656 if (fragP
== target
)
3658 if (fragP
->fr_fix
!= 0)
3660 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3662 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3663 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3665 if (fragP
->fr_type
== rs_space
)
3673 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3675 xtensa_isa isa
= xtensa_default_isa
;
3677 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3682 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) != 1
3683 && xtensa_opcode_is_jump (isa
, insn
->opcode
) != 1)
3686 for (i
= 0; i
< num_ops
; i
++)
3688 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3694 if (target_op
== -1)
3697 if (insn
->ntok
<= target_op
)
3700 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3703 sym
= insn
->tok
[target_op
].X_add_symbol
;
3707 if (insn
->tok
[target_op
].X_add_number
!= 0)
3710 target_frag
= symbol_get_frag (sym
);
3711 if (target_frag
== NULL
)
3714 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3715 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3723 xg_add_branch_and_loop_targets (TInsn
*insn
)
3725 xtensa_isa isa
= xtensa_default_isa
;
3726 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3728 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3731 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3732 && insn
->tok
[i
].X_op
== O_symbol
)
3733 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3737 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3738 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3742 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3744 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3745 && insn
->tok
[i
].X_op
== O_symbol
)
3747 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3748 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3749 if (S_IS_DEFINED (sym
))
3750 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3757 /* Return FALSE if no error. */
3760 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3765 switch (instr_spec
->typ
)
3768 new_insn
->insn_type
= ITYPE_INSN
;
3769 new_insn
->opcode
= instr_spec
->opcode
;
3771 case INSTR_LITERAL_DEF
:
3772 new_insn
->insn_type
= ITYPE_LITERAL
;
3773 new_insn
->opcode
= XTENSA_UNDEFINED
;
3775 case INSTR_LABEL_DEF
:
3778 new_insn
->is_specific_opcode
= FALSE
;
3779 new_insn
->debug_line
= old_insn
->debug_line
;
3780 new_insn
->loc_directive_seen
= old_insn
->loc_directive_seen
;
3782 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3785 const expressionS
*src_exp
;
3791 /* The expression must be the constant. */
3792 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3793 exp
= &new_insn
->tok
[b_op
->op_num
];
3794 set_expr_const (exp
, b_op
->op_data
);
3798 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3799 assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
3800 src_exp
= &old_insn
->tok
[b_op
->op_data
];
3801 exp
= &new_insn
->tok
[b_op
->op_num
];
3802 copy_expr (exp
, src_exp
);
3807 as_bad (_("can't handle generation of literal/labels yet"));
3811 as_bad (_("can't handle undefined OP TYPE"));
3816 new_insn
->ntok
= num_ops
;
3821 /* Return TRUE if it was simplified. */
3824 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
3826 TransitionRule
*rule
;
3827 BuildInstr
*insn_spec
;
3829 if (old_insn
->is_specific_opcode
|| !density_supported
)
3832 rule
= xg_instruction_match (old_insn
);
3836 insn_spec
= rule
->to_instr
;
3837 /* There should only be one. */
3838 assert (insn_spec
!= NULL
);
3839 assert (insn_spec
->next
== NULL
);
3840 if (insn_spec
->next
!= NULL
)
3843 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
3849 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3850 l32i.n. (2) Check the number of operands. (3) Place the instruction
3851 tokens into the stack or relax it and place multiple
3852 instructions/literals onto the stack. Return FALSE if no error. */
3855 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
3859 bfd_boolean do_expand
;
3861 tinsn_init (&new_insn
);
3863 /* Narrow it if we can. xg_simplify_insn now does all the
3864 appropriate checking (e.g., for the density option). */
3865 if (xg_simplify_insn (orig_insn
, &new_insn
))
3866 orig_insn
= &new_insn
;
3868 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
3870 if (orig_insn
->ntok
< noperands
)
3872 as_bad (_("found %d operands for '%s': Expected %d"),
3874 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3878 if (orig_insn
->ntok
> noperands
)
3879 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
3881 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3884 /* If there are not enough operands, we will assert above. If there
3885 are too many, just cut out the extras here. */
3886 orig_insn
->ntok
= noperands
;
3888 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
3891 /* Special case for extui opcode which has constraints not handled
3892 by the ordinary operand encoding checks. The number of operands
3893 and related syntax issues have already been checked. */
3894 if (orig_insn
->opcode
== xtensa_extui_opcode
)
3896 int shiftimm
= orig_insn
->tok
[2].X_add_number
;
3897 int maskimm
= orig_insn
->tok
[3].X_add_number
;
3898 if (shiftimm
+ maskimm
> 32)
3900 as_bad (_("immediate operands sum to greater than 32"));
3905 /* If the instruction will definitely need to be relaxed, it is better
3906 to expand it now for better scheduling. Decide whether to expand
3908 do_expand
= (!orig_insn
->is_specific_opcode
&& use_transform ());
3910 /* Calls should be expanded to longcalls only in the backend relaxation
3911 so that the assembly scheduler will keep the L32R/CALLX instructions
3913 if (is_direct_call_opcode (orig_insn
->opcode
))
3916 if (tinsn_has_symbolic_operands (orig_insn
))
3918 /* The values of symbolic operands are not known yet, so only expand
3919 now if an operand is "complex" (e.g., difference of symbols) and
3920 will have to be stored as a literal regardless of the value. */
3921 if (!tinsn_has_complex_operands (orig_insn
))
3924 else if (xg_immeds_fit (orig_insn
))
3928 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
3930 istack_push (istack
, orig_insn
);
3936 /* Return TRUE if the section flags are marked linkonce
3937 or the name is .gnu.linkonce.*. */
3939 static int linkonce_len
= sizeof (".gnu.linkonce.") - 1;
3942 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
3944 flagword flags
, link_once_flags
;
3946 flags
= bfd_get_section_flags (abfd
, sec
);
3947 link_once_flags
= (flags
& SEC_LINK_ONCE
);
3949 /* Flags might not be set yet. */
3950 if (!link_once_flags
3951 && strncmp (segment_name (sec
), ".gnu.linkonce.", linkonce_len
) == 0)
3952 link_once_flags
= SEC_LINK_ONCE
;
3954 return (link_once_flags
!= 0);
3959 xtensa_add_literal_sym (symbolS
*sym
)
3963 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
3965 l
->next
= literal_syms
;
3971 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
3973 static int lit_num
= 0;
3974 static char name
[256];
3977 sprintf (name
, ".L_lit_sym%d", lit_num
);
3979 /* Create a local symbol. If it is in a linkonce section, we have to
3980 be careful to make sure that if it is used in a relocation that the
3981 symbol will be in the output file. */
3982 if (get_is_linkonce_section (stdoutput
, sec
))
3984 symbolP
= symbol_new (name
, sec
, 0, frag
);
3985 S_CLEAR_EXTERNAL (symbolP
);
3986 /* symbolP->local = 1; */
3989 symbolP
= symbol_new (name
, sec
, 0, frag
);
3991 xtensa_add_literal_sym (symbolP
);
3998 /* Currently all literals that are generated here are 32-bit L32R targets. */
4001 xg_assemble_literal (/* const */ TInsn
*insn
)
4004 symbolS
*lit_sym
= NULL
;
4005 bfd_reloc_code_real_type reloc
;
4008 /* size = 4 for L32R. It could easily be larger when we move to
4009 larger constants. Add a parameter later. */
4010 offsetT litsize
= 4;
4011 offsetT litalign
= 2; /* 2^2 = 4 */
4012 expressionS saved_loc
;
4013 expressionS
* emit_val
;
4015 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
4017 assert (insn
->insn_type
== ITYPE_LITERAL
);
4018 assert (insn
->ntok
== 1); /* must be only one token here */
4020 xtensa_switch_to_literal_fragment (&state
);
4022 emit_val
= &insn
->tok
[0];
4023 if (emit_val
->X_op
== O_big
)
4025 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
4028 /* This happens when someone writes a "movi a2, big_number". */
4029 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4030 _("invalid immediate"));
4031 xtensa_restore_emit_state (&state
);
4036 /* Force a 4-byte align here. Note that this opens a new frag, so all
4037 literals done with this function have a frag to themselves. That's
4038 important for the way text section literals work. */
4039 frag_align (litalign
, 0, 0);
4040 record_alignment (now_seg
, litalign
);
4042 switch (emit_val
->X_op
)
4045 p
= frag_more (litsize
);
4046 xtensa_set_frag_assembly_state (frag_now
);
4047 reloc
= map_operator_to_reloc (emit_val
->X_op
);
4048 if (emit_val
->X_add_symbol
)
4049 emit_val
->X_op
= O_symbol
;
4051 emit_val
->X_op
= O_constant
;
4052 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
4053 litsize
, emit_val
, 0, reloc
);
4057 emit_expr (emit_val
, litsize
);
4061 assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
4062 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4063 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4064 lit_sym
= frag_now
->fr_symbol
;
4067 xtensa_restore_emit_state (&state
);
4073 xg_assemble_literal_space (/* const */ int size
, int slot
)
4076 /* We might have to do something about this alignment. It only
4077 takes effect if something is placed here. */
4078 offsetT litalign
= 2; /* 2^2 = 4 */
4079 fragS
*lit_saved_frag
;
4081 assert (size
% 4 == 0);
4083 xtensa_switch_to_literal_fragment (&state
);
4085 /* Force a 4-byte align here. */
4086 frag_align (litalign
, 0, 0);
4087 record_alignment (now_seg
, litalign
);
4089 xg_force_frag_space (size
);
4091 lit_saved_frag
= frag_now
;
4092 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4093 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4094 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4097 xtensa_restore_emit_state (&state
);
4098 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4102 /* Put in a fixup record based on the opcode.
4103 Return TRUE on success. */
4106 xg_add_opcode_fix (TInsn
*tinsn
,
4114 xtensa_opcode opcode
= tinsn
->opcode
;
4115 bfd_reloc_code_real_type reloc
;
4116 reloc_howto_type
*howto
;
4120 reloc
= BFD_RELOC_NONE
;
4122 /* First try the special cases for "alternate" relocs. */
4123 if (opcode
== xtensa_l32r_opcode
)
4125 if (fragP
->tc_frag_data
.use_absolute_literals
)
4126 reloc
= encode_alt_reloc (slot
);
4128 else if (opcode
== xtensa_const16_opcode
)
4130 if (expr
->X_op
== O_lo16
)
4132 reloc
= encode_reloc (slot
);
4133 expr
->X_op
= O_symbol
;
4135 else if (expr
->X_op
== O_hi16
)
4137 reloc
= encode_alt_reloc (slot
);
4138 expr
->X_op
= O_symbol
;
4142 if (opnum
!= get_relaxable_immed (opcode
))
4144 as_bad (_("invalid relocation for operand %i of '%s'"),
4145 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4149 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4150 into the symbol table where the generic portions of the assembler
4151 won't know what to do with them. */
4152 if (expr
->X_op
== O_lo16
|| expr
->X_op
== O_hi16
)
4154 as_bad (_("invalid expression for operand %i of '%s'"),
4155 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4159 /* Next try the generic relocs. */
4160 if (reloc
== BFD_RELOC_NONE
)
4161 reloc
= encode_reloc (slot
);
4162 if (reloc
== BFD_RELOC_NONE
)
4164 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4168 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4171 as_bad (_("undefined symbol for opcode \"%s\""),
4172 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4176 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4177 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, expr
,
4178 howto
->pc_relative
, reloc
);
4179 the_fix
->fx_no_overflow
= 1;
4180 the_fix
->tc_fix_data
.X_add_symbol
= expr
->X_add_symbol
;
4181 the_fix
->tc_fix_data
.X_add_number
= expr
->X_add_number
;
4182 the_fix
->tc_fix_data
.slot
= slot
;
4189 xg_emit_insn_to_buf (TInsn
*tinsn
,
4193 bfd_boolean build_fix
)
4195 static xtensa_insnbuf insnbuf
= NULL
;
4196 bfd_boolean has_symbolic_immed
= FALSE
;
4197 bfd_boolean ok
= TRUE
;
4200 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4202 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4203 if (has_symbolic_immed
&& build_fix
)
4206 xtensa_format fmt
= xg_get_single_format (tinsn
->opcode
);
4207 int slot
= xg_get_single_slot (tinsn
->opcode
);
4208 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4209 expressionS
*exp
= &tinsn
->tok
[opnum
];
4211 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, slot
, exp
, fragP
, offset
))
4214 fragP
->tc_frag_data
.is_insn
= TRUE
;
4215 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4216 (unsigned char *) buf
, 0);
4222 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4224 symbolS
*sym
= get_special_literal_symbol ();
4228 assert (insn
->insn_type
== ITYPE_INSN
);
4229 for (i
= 0; i
< insn
->ntok
; i
++)
4230 if (insn
->tok
[i
].X_add_symbol
== sym
)
4231 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4237 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4239 symbolS
*sym
= get_special_label_symbol ();
4241 for (i
= 0; i
< insn
->ntok
; i
++)
4242 if (insn
->tok
[i
].X_add_symbol
== sym
)
4243 insn
->tok
[i
].X_add_symbol
= label_sym
;
4248 /* Return TRUE if the instruction can write to the specified
4249 integer register. */
4252 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4256 xtensa_isa isa
= xtensa_default_isa
;
4258 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4260 for (i
= 0; i
< num_ops
; i
++)
4263 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4264 if ((inout
== 'o' || inout
== 'm')
4265 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4267 xtensa_regfile opnd_rf
=
4268 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4269 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4271 if ((insn
->tok
[i
].X_op
== O_register
)
4272 && (insn
->tok
[i
].X_add_number
== regnum
))
4282 is_bad_loopend_opcode (const TInsn
*tinsn
)
4284 xtensa_opcode opcode
= tinsn
->opcode
;
4286 if (opcode
== XTENSA_UNDEFINED
)
4289 if (opcode
== xtensa_call0_opcode
4290 || opcode
== xtensa_callx0_opcode
4291 || opcode
== xtensa_call4_opcode
4292 || opcode
== xtensa_callx4_opcode
4293 || opcode
== xtensa_call8_opcode
4294 || opcode
== xtensa_callx8_opcode
4295 || opcode
== xtensa_call12_opcode
4296 || opcode
== xtensa_callx12_opcode
4297 || opcode
== xtensa_isync_opcode
4298 || opcode
== xtensa_ret_opcode
4299 || opcode
== xtensa_ret_n_opcode
4300 || opcode
== xtensa_retw_opcode
4301 || opcode
== xtensa_retw_n_opcode
4302 || opcode
== xtensa_waiti_opcode
4303 || opcode
== xtensa_rsr_lcount_opcode
)
4310 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4311 This allows the debugger to add unaligned labels.
4312 Also, the assembler generates stabs labels that need
4313 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4316 is_unaligned_label (symbolS
*sym
)
4318 const char *name
= S_GET_NAME (sym
);
4319 static size_t fake_size
= 0;
4323 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4326 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4328 fake_size
= strlen (FAKE_LABEL_NAME
);
4331 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4332 && (name
[fake_size
] == 'F'
4333 || name
[fake_size
] == 'L'
4334 || (name
[fake_size
] == 'e'
4335 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4343 next_non_empty_frag (const fragS
*fragP
)
4345 fragS
*next_fragP
= fragP
->fr_next
;
4347 /* Sometimes an empty will end up here due storage allocation issues.
4348 So we have to skip until we find something legit. */
4349 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4350 next_fragP
= next_fragP
->fr_next
;
4352 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4360 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4362 xtensa_opcode out_opcode
;
4363 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4365 if (next_fragP
== NULL
)
4368 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4369 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4371 *opcode
= out_opcode
;
4379 frag_format_size (const fragS
*fragP
)
4381 static xtensa_insnbuf insnbuf
= NULL
;
4382 xtensa_isa isa
= xtensa_default_isa
;
4387 insnbuf
= xtensa_insnbuf_alloc (isa
);
4390 return XTENSA_UNDEFINED
;
4392 xtensa_insnbuf_from_chars (isa
, insnbuf
,
4393 (unsigned char *) fragP
->fr_literal
, 0);
4395 fmt
= xtensa_format_decode (isa
, insnbuf
);
4396 if (fmt
== XTENSA_UNDEFINED
)
4397 return XTENSA_UNDEFINED
;
4398 fmt_size
= xtensa_format_length (isa
, fmt
);
4400 /* If the next format won't be changing due to relaxation, just
4401 return the length of the first format. */
4402 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4405 /* If during relaxation we have to pull an instruction out of a
4406 multi-slot instruction, we will return the more conservative
4407 number. This works because alignment on bigger instructions
4408 is more restrictive than alignment on smaller instructions.
4409 This is more conservative than we would like, but it happens
4412 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4415 /* If we aren't doing one of our own relaxations or it isn't
4416 slot-based, then the insn size won't change. */
4417 if (fragP
->fr_type
!= rs_machine_dependent
)
4419 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4422 /* If an instruction is about to grow, return the longer size. */
4423 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4424 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
4425 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP3
)
4428 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4429 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4436 next_frag_format_size (const fragS
*fragP
)
4438 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4439 return frag_format_size (next_fragP
);
4443 /* In early Xtensa Processors, for reasons that are unclear, the ISA
4444 required two-byte instructions to be treated as three-byte instructions
4445 for loop instruction alignment. This restriction was removed beginning
4446 with Xtensa LX. Now the only requirement on loop instruction alignment
4447 is that the first instruction of the loop must appear at an address that
4448 does not cross a fetch boundary. */
4451 get_loop_align_size (int insn_size
)
4453 if (insn_size
== XTENSA_UNDEFINED
)
4454 return xtensa_fetch_width
;
4456 if (enforce_three_byte_loop_align
&& insn_size
== 2)
4463 /* If the next legit fragment is an end-of-loop marker,
4464 switch its state so it will instantiate a NOP. */
4467 update_next_frag_state (fragS
*fragP
)
4469 fragS
*next_fragP
= fragP
->fr_next
;
4470 fragS
*new_target
= NULL
;
4474 /* We are guaranteed there will be one of these... */
4475 while (!(next_fragP
->fr_type
== rs_machine_dependent
4476 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4477 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4478 next_fragP
= next_fragP
->fr_next
;
4480 assert (next_fragP
->fr_type
== rs_machine_dependent
4481 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4482 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4484 /* ...and one of these. */
4485 new_target
= next_fragP
->fr_next
;
4486 while (!(new_target
->fr_type
== rs_machine_dependent
4487 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4488 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4489 new_target
= new_target
->fr_next
;
4491 assert (new_target
->fr_type
== rs_machine_dependent
4492 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4493 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4496 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4498 if (next_fragP
->fr_type
== rs_machine_dependent
4499 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4501 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4505 next_fragP
= next_fragP
->fr_next
;
4511 next_frag_is_branch_target (const fragS
*fragP
)
4513 /* Sometimes an empty will end up here due to storage allocation issues,
4514 so we have to skip until we find something legit. */
4515 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4517 if (fragP
->tc_frag_data
.is_branch_target
)
4519 if (fragP
->fr_fix
!= 0)
4527 next_frag_is_loop_target (const fragS
*fragP
)
4529 /* Sometimes an empty will end up here due storage allocation issues.
4530 So we have to skip until we find something legit. */
4531 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4533 if (fragP
->tc_frag_data
.is_loop_target
)
4535 if (fragP
->fr_fix
!= 0)
4543 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4545 const fragS
*next_fragp
= fragp
->fr_next
;
4546 xtensa_opcode next_opcode
;
4548 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4551 /* Sometimes an empty will end up here due to storage allocation issues,
4552 so we have to skip until we find something legit. */
4553 while (next_fragp
->fr_fix
== 0)
4554 next_fragp
= next_fragp
->fr_next
;
4556 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4559 /* There is some implicit knowledge encoded in here.
4560 The LOOP instructions that are NOT RELAX_IMMED have
4561 been relaxed. Note that we can assume that the LOOP
4562 instruction is in slot 0 because loops aren't bundleable. */
4563 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4564 return get_expanded_loop_offset (next_opcode
);
4570 /* Mark a location where we can later insert literal frags. Update
4571 the section's literal_pool_loc, so subsequent literals can be
4572 placed nearest to their use. */
4575 xtensa_mark_literal_pool_location (void)
4577 /* Any labels pointing to the current location need
4578 to be adjusted to after the literal pool. */
4580 fragS
*pool_location
;
4582 if (use_literal_section
)
4585 /* We stash info in these frags so we can later move the literal's
4586 fixes into this frchain's fix list. */
4587 pool_location
= frag_now
;
4588 frag_now
->tc_frag_data
.lit_frchain
= frchain_now
;
4589 frag_now
->tc_frag_data
.literal_frag
= frag_now
;
4590 frag_variant (rs_machine_dependent
, 0, 0,
4591 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4592 xtensa_set_frag_assembly_state (frag_now
);
4593 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
4594 frag_variant (rs_machine_dependent
, 0, 0,
4595 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4596 xtensa_set_frag_assembly_state (frag_now
);
4598 /* Now put a frag into the literal pool that points to this location. */
4599 set_literal_pool_location (now_seg
, pool_location
);
4600 xtensa_switch_to_non_abs_literal_fragment (&s
);
4601 frag_align (2, 0, 0);
4602 record_alignment (now_seg
, 2);
4604 /* Close whatever frag is there. */
4605 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4606 xtensa_set_frag_assembly_state (frag_now
);
4607 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
4608 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4609 xtensa_restore_emit_state (&s
);
4610 xtensa_set_frag_assembly_state (frag_now
);
4614 /* Build a nop of the correct size into tinsn. */
4617 build_nop (TInsn
*tinsn
, int size
)
4623 tinsn
->opcode
= xtensa_nop_n_opcode
;
4625 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4626 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4630 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4632 tinsn
->opcode
= xtensa_or_opcode
;
4633 set_expr_const (&tinsn
->tok
[0], 1);
4634 set_expr_const (&tinsn
->tok
[1], 1);
4635 set_expr_const (&tinsn
->tok
[2], 1);
4639 tinsn
->opcode
= xtensa_nop_opcode
;
4641 assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4646 /* Assemble a NOP of the requested size in the buffer. User must have
4647 allocated "buf" with at least "size" bytes. */
4650 assemble_nop (int size
, char *buf
)
4652 static xtensa_insnbuf insnbuf
= NULL
;
4655 build_nop (&tinsn
, size
);
4658 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4660 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4661 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4662 (unsigned char *) buf
, 0);
4666 /* Return the number of bytes for the offset of the expanded loop
4667 instruction. This should be incorporated into the relaxation
4668 specification but is hard-coded here. This is used to auto-align
4669 the loop instruction. It is invalid to call this function if the
4670 configuration does not have loops or if the opcode is not a loop
4674 get_expanded_loop_offset (xtensa_opcode opcode
)
4676 /* This is the OFFSET of the loop instruction in the expanded loop.
4677 This MUST correspond directly to the specification of the loop
4678 expansion. It will be validated on fragment conversion. */
4679 assert (opcode
!= XTENSA_UNDEFINED
);
4680 if (opcode
== xtensa_loop_opcode
)
4682 if (opcode
== xtensa_loopnez_opcode
)
4684 if (opcode
== xtensa_loopgtz_opcode
)
4686 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4692 get_literal_pool_location (segT seg
)
4694 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4699 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4701 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4705 /* Set frag assembly state should be called when a new frag is
4706 opened and after a frag has been closed. */
4709 xtensa_set_frag_assembly_state (fragS
*fragP
)
4711 if (!density_supported
)
4712 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4714 /* This function is called from subsegs_finish, which is called
4715 after xtensa_end, so we can't use "use_transform" or
4716 "use_schedule" here. */
4717 if (!directive_state
[directive_transform
])
4718 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4719 if (directive_state
[directive_longcalls
])
4720 fragP
->tc_frag_data
.use_longcalls
= TRUE
;
4721 fragP
->tc_frag_data
.use_absolute_literals
=
4722 directive_state
[directive_absolute_literals
];
4723 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4728 relaxable_section (asection
*sec
)
4730 return ((sec
->flags
& SEC_DEBUGGING
) == 0
4731 && strcmp (sec
->name
, ".eh_frame") != 0);
4736 xtensa_mark_frags_for_org (void)
4740 /* Walk over each fragment of all of the current segments. If we find
4741 a .org frag in any of the segments, mark all frags prior to it as
4742 "no transform", which will prevent linker optimizations from messing
4743 up the .org distance. This should be done after
4744 xtensa_find_unmarked_state_frags, because we don't want to worry here
4745 about that function trashing the data we save here. */
4747 for (seclist
= &stdoutput
->sections
;
4748 seclist
&& *seclist
;
4749 seclist
= &(*seclist
)->next
)
4751 segT sec
= *seclist
;
4752 segment_info_type
*seginfo
;
4755 flags
= bfd_get_section_flags (stdoutput
, sec
);
4756 if (flags
& SEC_DEBUGGING
)
4758 if (!(flags
& SEC_ALLOC
))
4761 seginfo
= seg_info (sec
);
4762 if (seginfo
&& seginfo
->frchainP
)
4764 fragS
*last_fragP
= seginfo
->frchainP
->frch_root
;
4765 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4766 fragP
= fragP
->fr_next
)
4768 /* cvt_frag_to_fill has changed the fr_type of org frags to
4769 rs_fill, so use the value as cached in rs_subtype here. */
4770 if (fragP
->fr_subtype
== RELAX_ORG
)
4772 while (last_fragP
!= fragP
->fr_next
)
4774 last_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4775 last_fragP
= last_fragP
->fr_next
;
4785 xtensa_find_unmarked_state_frags (void)
4789 /* Walk over each fragment of all of the current segments. For each
4790 unmarked fragment, mark it with the same info as the previous
4792 for (seclist
= &stdoutput
->sections
;
4793 seclist
&& *seclist
;
4794 seclist
= &(*seclist
)->next
)
4796 segT sec
= *seclist
;
4797 segment_info_type
*seginfo
;
4800 flags
= bfd_get_section_flags (stdoutput
, sec
);
4801 if (flags
& SEC_DEBUGGING
)
4803 if (!(flags
& SEC_ALLOC
))
4806 seginfo
= seg_info (sec
);
4807 if (seginfo
&& seginfo
->frchainP
)
4809 fragS
*last_fragP
= 0;
4810 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4811 fragP
= fragP
->fr_next
)
4813 if (fragP
->fr_fix
!= 0
4814 && !fragP
->tc_frag_data
.is_assembly_state_set
)
4816 if (last_fragP
== 0)
4818 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
4819 _("assembly state not set for first frag in section %s"),
4824 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4825 fragP
->tc_frag_data
.is_no_density
=
4826 last_fragP
->tc_frag_data
.is_no_density
;
4827 fragP
->tc_frag_data
.is_no_transform
=
4828 last_fragP
->tc_frag_data
.is_no_transform
;
4829 fragP
->tc_frag_data
.use_longcalls
=
4830 last_fragP
->tc_frag_data
.use_longcalls
;
4831 fragP
->tc_frag_data
.use_absolute_literals
=
4832 last_fragP
->tc_frag_data
.use_absolute_literals
;
4835 if (fragP
->tc_frag_data
.is_assembly_state_set
)
4844 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
4846 void *unused ATTRIBUTE_UNUSED
)
4848 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4849 segment_info_type
*seginfo
= seg_info (sec
);
4850 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4852 if (flags
& SEC_CODE
)
4854 xtensa_isa isa
= xtensa_default_isa
;
4855 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4856 while (frag
!= NULL
)
4858 if (frag
->tc_frag_data
.is_branch_target
)
4861 addressT branch_align
, frag_addr
;
4864 xtensa_insnbuf_from_chars
4865 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4866 fmt
= xtensa_format_decode (isa
, insnbuf
);
4867 op_size
= xtensa_format_length (isa
, fmt
);
4868 branch_align
= 1 << branch_align_power (sec
);
4869 frag_addr
= frag
->fr_address
% branch_align
;
4870 if (frag_addr
+ op_size
> branch_align
)
4871 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4872 _("unaligned branch target: %d bytes at 0x%lx"),
4873 op_size
, (long) frag
->fr_address
);
4875 frag
= frag
->fr_next
;
4877 xtensa_insnbuf_free (isa
, insnbuf
);
4883 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
4885 void *unused ATTRIBUTE_UNUSED
)
4887 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4888 segment_info_type
*seginfo
= seg_info (sec
);
4889 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4890 xtensa_isa isa
= xtensa_default_isa
;
4892 if (flags
& SEC_CODE
)
4894 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4895 while (frag
!= NULL
)
4897 if (frag
->tc_frag_data
.is_first_loop_insn
)
4903 xtensa_insnbuf_from_chars
4904 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4905 fmt
= xtensa_format_decode (isa
, insnbuf
);
4906 op_size
= xtensa_format_length (isa
, fmt
);
4907 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
4909 if (frag_addr
+ op_size
> xtensa_fetch_width
)
4910 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4911 _("unaligned loop: %d bytes at 0x%lx"),
4912 op_size
, (long) frag
->fr_address
);
4914 frag
= frag
->fr_next
;
4916 xtensa_insnbuf_free (isa
, insnbuf
);
4922 xg_apply_fix_value (fixS
*fixP
, valueT val
)
4924 xtensa_isa isa
= xtensa_default_isa
;
4925 static xtensa_insnbuf insnbuf
= NULL
;
4926 static xtensa_insnbuf slotbuf
= NULL
;
4929 bfd_boolean alt_reloc
;
4930 xtensa_opcode opcode
;
4931 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
4933 (void) decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
);
4935 as_fatal (_("unexpected fix"));
4939 insnbuf
= xtensa_insnbuf_alloc (isa
);
4940 slotbuf
= xtensa_insnbuf_alloc (isa
);
4943 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4944 fmt
= xtensa_format_decode (isa
, insnbuf
);
4945 if (fmt
== XTENSA_UNDEFINED
)
4946 as_fatal (_("undecodable fix"));
4947 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4948 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
4949 if (opcode
== XTENSA_UNDEFINED
)
4950 as_fatal (_("undecodable fix"));
4952 /* CONST16 immediates are not PC-relative, despite the fact that we
4953 reuse the normal PC-relative operand relocations for the low part
4954 of a CONST16 operand. */
4955 if (opcode
== xtensa_const16_opcode
)
4958 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
4959 get_relaxable_immed (opcode
), val
,
4960 fixP
->fx_file
, fixP
->fx_line
);
4962 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4963 xtensa_insnbuf_to_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4969 /* External Functions and Other GAS Hooks. */
4972 xtensa_target_format (void)
4974 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
4979 xtensa_file_arch_init (bfd
*abfd
)
4981 bfd_set_private_flags (abfd
, 0x100 | 0x200);
4986 md_number_to_chars (char *buf
, valueT val
, int n
)
4988 if (target_big_endian
)
4989 number_to_chars_bigendian (buf
, val
, n
);
4991 number_to_chars_littleendian (buf
, val
, n
);
4995 /* This function is called once, at assembler startup time. It should
4996 set up all the tables, etc. that the MD part of the assembler will
5002 segT current_section
= now_seg
;
5003 int current_subsec
= now_subseg
;
5006 xtensa_default_isa
= xtensa_isa_init (0, 0);
5007 isa
= xtensa_default_isa
;
5011 /* Set up the literal sections. */
5012 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
5014 subseg_set (current_section
, current_subsec
);
5016 xg_init_vinsn (&cur_vinsn
);
5018 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
5019 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
5020 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
5021 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
5022 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
5023 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
5024 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
5025 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
5026 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
5027 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
5028 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
5029 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
5030 xtensa_extui_opcode
= xtensa_opcode_lookup (isa
, "extui");
5031 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
5032 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
5033 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
5034 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
5035 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
5036 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
5037 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
5038 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
5039 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
5040 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
5041 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
5042 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
5043 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
5044 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
5045 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
5046 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
5047 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
5049 init_op_placement_info_table ();
5051 /* Set up the assembly state. */
5052 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5053 xtensa_set_frag_assembly_state (frag_now
);
5057 /* TC_INIT_FIX_DATA hook */
5060 xtensa_init_fix_data (fixS
*x
)
5062 x
->tc_fix_data
.slot
= 0;
5063 x
->tc_fix_data
.X_add_symbol
= NULL
;
5064 x
->tc_fix_data
.X_add_number
= 0;
5068 /* tc_frob_label hook */
5071 xtensa_frob_label (symbolS
*sym
)
5075 if (cur_vinsn
.inside_bundle
)
5077 as_bad (_("labels are not valid inside bundles"));
5081 freq
= get_subseg_target_freq (now_seg
, now_subseg
);
5083 /* Since the label was already attached to a frag associated with the
5084 previous basic block, it now needs to be reset to the current frag. */
5085 symbol_set_frag (sym
, frag_now
);
5086 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5088 if (generating_literals
)
5089 xtensa_add_literal_sym (sym
);
5091 xtensa_add_insn_label (sym
);
5093 if (symbol_get_tc (sym
)->is_loop_target
)
5095 if ((get_last_insn_flags (now_seg
, now_subseg
)
5096 & FLAG_IS_BAD_LOOPEND
) != 0)
5097 as_bad (_("invalid last instruction for a zero-overhead loop"));
5099 xtensa_set_frag_assembly_state (frag_now
);
5100 frag_var (rs_machine_dependent
, 4, 4, RELAX_LOOP_END
,
5101 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5103 xtensa_set_frag_assembly_state (frag_now
);
5104 xtensa_move_labels (frag_now
, 0);
5107 /* No target aligning in the absolute section. */
5108 if (now_seg
!= absolute_section
5109 && do_align_targets ()
5110 && !is_unaligned_label (sym
)
5111 && !generating_literals
)
5113 xtensa_set_frag_assembly_state (frag_now
);
5115 frag_var (rs_machine_dependent
,
5117 RELAX_DESIRE_ALIGN_IF_TARGET
,
5118 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5119 xtensa_set_frag_assembly_state (frag_now
);
5120 xtensa_move_labels (frag_now
, 0);
5123 /* We need to mark the following properties even if we aren't aligning. */
5125 /* If the label is already known to be a branch target, i.e., a
5126 forward branch, mark the frag accordingly. Backward branches
5127 are handled by xg_add_branch_and_loop_targets. */
5128 if (symbol_get_tc (sym
)->is_branch_target
)
5129 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5131 /* Loops only go forward, so they can be identified here. */
5132 if (symbol_get_tc (sym
)->is_loop_target
)
5133 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5135 dwarf2_emit_label (sym
);
5139 /* tc_unrecognized_line hook */
5142 xtensa_unrecognized_line (int ch
)
5147 if (cur_vinsn
.inside_bundle
== 0)
5149 /* PR8110: Cannot emit line number info inside a FLIX bundle
5150 when using --gstabs. Temporarily disable debug info. */
5151 generate_lineno_debug ();
5152 if (debug_type
== DEBUG_STABS
)
5154 xt_saved_debug_type
= debug_type
;
5155 debug_type
= DEBUG_NONE
;
5158 cur_vinsn
.inside_bundle
= 1;
5162 as_bad (_("extra opening brace"));
5168 if (cur_vinsn
.inside_bundle
)
5169 finish_vinsn (&cur_vinsn
);
5172 as_bad (_("extra closing brace"));
5177 as_bad (_("syntax error"));
5184 /* md_flush_pending_output hook */
5187 xtensa_flush_pending_output (void)
5189 /* This line fixes a bug where automatically generated gstabs info
5190 separates a function label from its entry instruction, ending up
5191 with the literal position between the function label and the entry
5192 instruction and crashing code. It only happens with --gstabs and
5193 --text-section-literals, and when several other obscure relaxation
5194 conditions are met. */
5195 if (outputting_stabs_line_debug
)
5198 if (cur_vinsn
.inside_bundle
)
5199 as_bad (_("missing closing brace"));
5201 /* If there is a non-zero instruction fragment, close it. */
5202 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5204 frag_wane (frag_now
);
5206 xtensa_set_frag_assembly_state (frag_now
);
5208 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5210 xtensa_clear_insn_labels ();
5214 /* We had an error while parsing an instruction. The string might look
5215 like this: "insn arg1, arg2 }". If so, we need to see the closing
5216 brace and reset some fields. Otherwise, the vinsn never gets closed
5217 and the num_slots field will grow past the end of the array of slots,
5218 and bad things happen. */
5221 error_reset_cur_vinsn (void)
5223 if (cur_vinsn
.inside_bundle
)
5225 if (*input_line_pointer
== '}'
5226 || *(input_line_pointer
- 1) == '}'
5227 || *(input_line_pointer
- 2) == '}')
5228 xg_clear_vinsn (&cur_vinsn
);
5234 md_assemble (char *str
)
5236 xtensa_isa isa
= xtensa_default_isa
;
5239 bfd_boolean has_underbar
= FALSE
;
5240 char *arg_strings
[MAX_INSN_ARGS
];
5242 TInsn orig_insn
; /* Original instruction from the input. */
5244 tinsn_init (&orig_insn
);
5246 /* Split off the opcode. */
5247 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5248 opname
= xmalloc (opnamelen
+ 1);
5249 memcpy (opname
, str
, opnamelen
);
5250 opname
[opnamelen
] = '\0';
5252 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5255 as_bad (_("syntax error"));
5259 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5262 /* Check for an underbar prefix. */
5265 has_underbar
= TRUE
;
5269 orig_insn
.insn_type
= ITYPE_INSN
;
5271 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5273 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5274 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5276 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5277 if (fmt
== XTENSA_UNDEFINED
)
5279 as_bad (_("unknown opcode or format name '%s'"), opname
);
5280 error_reset_cur_vinsn ();
5283 if (!cur_vinsn
.inside_bundle
)
5285 as_bad (_("format names only valid inside bundles"));
5286 error_reset_cur_vinsn ();
5289 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5290 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5292 cur_vinsn
.format
= fmt
;
5293 free (has_underbar
? opname
- 1 : opname
);
5294 error_reset_cur_vinsn ();
5298 /* Parse the arguments. */
5299 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5301 as_bad (_("syntax error"));
5302 error_reset_cur_vinsn ();
5306 /* Free the opcode and argument strings, now that they've been parsed. */
5307 free (has_underbar
? opname
- 1 : opname
);
5309 while (num_args
-- > 0)
5310 free (arg_strings
[num_args
]);
5312 /* Get expressions for invisible operands. */
5313 if (get_invisible_operands (&orig_insn
))
5315 error_reset_cur_vinsn ();
5319 /* Check for the right number and type of arguments. */
5320 if (tinsn_check_arguments (&orig_insn
))
5322 error_reset_cur_vinsn ();
5326 /* Record the line number for each TInsn, because a FLIX bundle may be
5327 spread across multiple input lines and individual instructions may be
5328 moved around in some cases. */
5329 orig_insn
.loc_directive_seen
= dwarf2_loc_directive_seen
;
5330 dwarf2_where (&orig_insn
.debug_line
);
5331 dwarf2_consume_line_info ();
5333 xg_add_branch_and_loop_targets (&orig_insn
);
5335 /* Check that immediate value for ENTRY is >= 16. */
5336 if (orig_insn
.opcode
== xtensa_entry_opcode
&& orig_insn
.ntok
>= 3)
5338 expressionS
*exp
= &orig_insn
.tok
[2];
5339 if (exp
->X_op
== O_constant
&& exp
->X_add_number
< 16)
5340 as_warn (_("entry instruction with stack decrement < 16"));
5344 assemble_tokens (opcode, tok, ntok);
5345 expand the tokens from the orig_insn into the
5346 stack of instructions that will not expand
5347 unless required at relaxation time. */
5349 if (!cur_vinsn
.inside_bundle
)
5350 emit_single_op (&orig_insn
);
5351 else /* We are inside a bundle. */
5353 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5354 cur_vinsn
.num_slots
++;
5355 if (*input_line_pointer
== '}'
5356 || *(input_line_pointer
- 1) == '}'
5357 || *(input_line_pointer
- 2) == '}')
5358 finish_vinsn (&cur_vinsn
);
5361 /* We've just emitted a new instruction so clear the list of labels. */
5362 xtensa_clear_insn_labels ();
5366 /* HANDLE_ALIGN hook */
5368 /* For a .align directive, we mark the previous block with the alignment
5369 information. This will be placed in the object file in the
5370 property section corresponding to this section. */
5373 xtensa_handle_align (fragS
*fragP
)
5376 && ! fragP
->tc_frag_data
.is_literal
5377 && (fragP
->fr_type
== rs_align
5378 || fragP
->fr_type
== rs_align_code
)
5379 && fragP
->fr_address
+ fragP
->fr_fix
> 0
5380 && fragP
->fr_offset
> 0
5381 && now_seg
!= bss_section
)
5383 fragP
->tc_frag_data
.is_align
= TRUE
;
5384 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5387 if (fragP
->fr_type
== rs_align_test
)
5390 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5392 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5393 _("unaligned entry instruction"));
5396 if (linkrelax
&& fragP
->fr_type
== rs_org
)
5397 fragP
->fr_subtype
= RELAX_ORG
;
5401 /* TC_FRAG_INIT hook */
5404 xtensa_frag_init (fragS
*frag
)
5406 xtensa_set_frag_assembly_state (frag
);
5411 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5417 /* Round up a section size to the appropriate boundary. */
5420 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5422 return size
; /* Byte alignment is fine. */
5427 md_pcrel_from (fixS
*fixP
)
5430 static xtensa_insnbuf insnbuf
= NULL
;
5431 static xtensa_insnbuf slotbuf
= NULL
;
5434 xtensa_opcode opcode
;
5437 xtensa_isa isa
= xtensa_default_isa
;
5438 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5439 bfd_boolean alt_reloc
;
5441 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5446 insnbuf
= xtensa_insnbuf_alloc (isa
);
5447 slotbuf
= xtensa_insnbuf_alloc (isa
);
5450 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5451 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) insn_p
, 0);
5452 fmt
= xtensa_format_decode (isa
, insnbuf
);
5454 if (fmt
== XTENSA_UNDEFINED
)
5455 as_fatal (_("bad instruction format"));
5457 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5458 as_fatal (_("invalid relocation"));
5460 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5461 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5463 /* Check for "alternate" relocations (operand not specified). None
5464 of the current uses for these are really PC-relative. */
5465 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5467 if (opcode
!= xtensa_l32r_opcode
5468 && opcode
!= xtensa_const16_opcode
)
5469 as_fatal (_("invalid relocation for '%s' instruction"),
5470 xtensa_opcode_name (isa
, opcode
));
5474 opnum
= get_relaxable_immed (opcode
);
5476 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5477 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5479 as_bad_where (fixP
->fx_file
,
5481 _("invalid relocation for operand %d of '%s'"),
5482 opnum
, xtensa_opcode_name (isa
, opcode
));
5485 return 0 - opnd_value
;
5489 /* TC_FORCE_RELOCATION hook */
5492 xtensa_force_relocation (fixS
*fix
)
5494 switch (fix
->fx_r_type
)
5496 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5497 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5498 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5499 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5500 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5501 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5502 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5503 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5504 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5505 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5506 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5507 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5508 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5509 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5510 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5511 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5517 if (linkrelax
&& fix
->fx_addsy
5518 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5521 return generic_force_reloc (fix
);
5525 /* TC_VALIDATE_FIX_SUB hook */
5528 xtensa_validate_fix_sub (fixS
*fix
)
5530 segT add_symbol_segment
, sub_symbol_segment
;
5532 /* The difference of two symbols should be resolved by the assembler when
5533 linkrelax is not set. If the linker may relax the section containing
5534 the symbols, then an Xtensa DIFF relocation must be generated so that
5535 the linker knows to adjust the difference value. */
5536 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
5539 /* Make sure both symbols are in the same segment, and that segment is
5540 "normal" and relaxable. If the segment is not "normal", then the
5541 fix is not valid. If the segment is not "relaxable", then the fix
5542 should have been handled earlier. */
5543 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
5544 if (! SEG_NORMAL (add_symbol_segment
) ||
5545 ! relaxable_section (add_symbol_segment
))
5547 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
5548 return (sub_symbol_segment
== add_symbol_segment
);
5552 /* NO_PSEUDO_DOT hook */
5554 /* This function has nothing to do with pseudo dots, but this is the
5555 nearest macro to where the check needs to take place. FIXME: This
5559 xtensa_check_inside_bundle (void)
5561 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5562 as_bad (_("directives are not valid inside bundles"));
5564 /* This function must always return FALSE because it is called via a
5565 macro that has nothing to do with bundling. */
5570 /* md_elf_section_change_hook */
5573 xtensa_elf_section_change_hook (void)
5575 /* Set up the assembly state. */
5576 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5577 xtensa_set_frag_assembly_state (frag_now
);
5581 /* tc_fix_adjustable hook */
5584 xtensa_fix_adjustable (fixS
*fixP
)
5586 /* An offset is not allowed in combination with the difference of two
5587 symbols, but that cannot be easily detected after a local symbol
5588 has been adjusted to a (section+offset) form. Return 0 so that such
5589 an fix will not be adjusted. */
5590 if (fixP
->fx_subsy
&& fixP
->fx_addsy
&& fixP
->fx_offset
5591 && relaxable_section (S_GET_SEGMENT (fixP
->fx_subsy
)))
5594 /* We need the symbol name for the VTABLE entries. */
5595 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5596 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5603 /* tc_symbol_new_hook */
5605 symbolS
*expr_symbols
= NULL
;
5608 xtensa_symbol_new_hook (symbolS
*sym
)
5610 if (S_GET_SEGMENT (sym
) == expr_section
)
5612 symbol_get_tc (sym
)->next_expr_symbol
= expr_symbols
;
5620 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg
)
5622 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5625 /* Subtracted symbols are only allowed for a few relocation types, and
5626 unless linkrelax is enabled, they should not make it to this point. */
5627 if (fixP
->fx_subsy
&& !(linkrelax
&& (fixP
->fx_r_type
== BFD_RELOC_32
5628 || fixP
->fx_r_type
== BFD_RELOC_16
5629 || fixP
->fx_r_type
== BFD_RELOC_8
)))
5630 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("expression too complex"));
5632 switch (fixP
->fx_r_type
)
5639 switch (fixP
->fx_r_type
)
5642 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF8
;
5645 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF16
;
5648 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF32
;
5654 /* An offset is only allowed when it results from adjusting a
5655 local symbol into a section-relative offset. If the offset
5656 came from the original expression, tc_fix_adjustable will have
5657 prevented the fix from being converted to a section-relative
5658 form so that we can flag the error here. */
5659 if (fixP
->fx_offset
!= 0 && !symbol_section_p (fixP
->fx_addsy
))
5660 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5661 _("cannot represent subtraction with an offset"));
5663 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5664 - S_GET_VALUE (fixP
->fx_subsy
));
5666 /* The difference value gets written out, and the DIFF reloc
5667 identifies the address of the subtracted symbol (i.e., the one
5668 with the lowest address). */
5670 fixP
->fx_offset
-= val
;
5671 fixP
->fx_subsy
= NULL
;
5673 else if (! fixP
->fx_addsy
)
5680 case BFD_RELOC_XTENSA_PLT
:
5681 md_number_to_chars (fixpos
, val
, fixP
->fx_size
);
5682 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5685 case BFD_RELOC_XTENSA_SLOT0_OP
:
5686 case BFD_RELOC_XTENSA_SLOT1_OP
:
5687 case BFD_RELOC_XTENSA_SLOT2_OP
:
5688 case BFD_RELOC_XTENSA_SLOT3_OP
:
5689 case BFD_RELOC_XTENSA_SLOT4_OP
:
5690 case BFD_RELOC_XTENSA_SLOT5_OP
:
5691 case BFD_RELOC_XTENSA_SLOT6_OP
:
5692 case BFD_RELOC_XTENSA_SLOT7_OP
:
5693 case BFD_RELOC_XTENSA_SLOT8_OP
:
5694 case BFD_RELOC_XTENSA_SLOT9_OP
:
5695 case BFD_RELOC_XTENSA_SLOT10_OP
:
5696 case BFD_RELOC_XTENSA_SLOT11_OP
:
5697 case BFD_RELOC_XTENSA_SLOT12_OP
:
5698 case BFD_RELOC_XTENSA_SLOT13_OP
:
5699 case BFD_RELOC_XTENSA_SLOT14_OP
:
5702 /* Write the tentative value of a PC-relative relocation to a
5703 local symbol into the instruction. The value will be ignored
5704 by the linker, and it makes the object file disassembly
5705 readable when all branch targets are encoded in relocations. */
5707 assert (fixP
->fx_addsy
);
5708 if (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
5709 && !S_FORCE_RELOC (fixP
->fx_addsy
, 1))
5711 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5712 - md_pcrel_from (fixP
));
5713 (void) xg_apply_fix_value (fixP
, val
);
5716 else if (! fixP
->fx_addsy
)
5719 if (xg_apply_fix_value (fixP
, val
))
5724 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5725 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5726 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5727 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5728 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5729 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5730 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5731 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5732 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5733 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5734 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5735 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5736 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5737 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5738 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5739 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5740 /* These all need to be resolved at link-time. Do nothing now. */
5743 case BFD_RELOC_VTABLE_INHERIT
:
5744 case BFD_RELOC_VTABLE_ENTRY
:
5749 as_bad (_("unhandled local relocation fix %s"),
5750 bfd_get_reloc_code_name (fixP
->fx_r_type
));
5756 md_atof (int type
, char *litP
, int *sizeP
)
5758 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
5763 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
5765 return total_frag_text_expansion (fragP
);
5769 /* Translate internal representation of relocation info to BFD target
5773 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
5777 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
5778 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5779 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5780 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5782 /* Make sure none of our internal relocations make it this far.
5783 They'd better have been fully resolved by this point. */
5784 assert ((int) fixp
->fx_r_type
> 0);
5786 reloc
->addend
= fixp
->fx_offset
;
5788 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
5789 if (reloc
->howto
== NULL
)
5791 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5792 _("cannot represent `%s' relocation in object file"),
5793 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5794 free (reloc
->sym_ptr_ptr
);
5799 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
5800 as_fatal (_("internal error? cannot generate `%s' relocation"),
5801 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5807 /* Checks for resource conflicts between instructions. */
5809 /* The func unit stuff could be implemented as bit-vectors rather
5810 than the iterative approach here. If it ends up being too
5811 slow, we will switch it. */
5814 new_resource_table (void *data
,
5817 unit_num_copies_func uncf
,
5818 opcode_num_units_func onuf
,
5819 opcode_funcUnit_use_unit_func ouuf
,
5820 opcode_funcUnit_use_stage_func ousf
)
5823 resource_table
*rt
= (resource_table
*) xmalloc (sizeof (resource_table
));
5825 rt
->cycles
= cycles
;
5826 rt
->allocated_cycles
= cycles
;
5828 rt
->unit_num_copies
= uncf
;
5829 rt
->opcode_num_units
= onuf
;
5830 rt
->opcode_unit_use
= ouuf
;
5831 rt
->opcode_unit_stage
= ousf
;
5833 rt
->units
= (unsigned char **) xcalloc (cycles
, sizeof (unsigned char *));
5834 for (i
= 0; i
< cycles
; i
++)
5835 rt
->units
[i
] = (unsigned char *) xcalloc (nu
, sizeof (unsigned char));
5842 clear_resource_table (resource_table
*rt
)
5845 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
5846 for (j
= 0; j
< rt
->num_units
; j
++)
5847 rt
->units
[i
][j
] = 0;
5851 /* We never shrink it, just fake it into thinking so. */
5854 resize_resource_table (resource_table
*rt
, int cycles
)
5858 rt
->cycles
= cycles
;
5859 if (cycles
<= rt
->allocated_cycles
)
5862 old_cycles
= rt
->allocated_cycles
;
5863 rt
->allocated_cycles
= cycles
;
5865 rt
->units
= xrealloc (rt
->units
,
5866 rt
->allocated_cycles
* sizeof (unsigned char *));
5867 for (i
= 0; i
< old_cycles
; i
++)
5868 rt
->units
[i
] = xrealloc (rt
->units
[i
],
5869 rt
->num_units
* sizeof (unsigned char));
5870 for (i
= old_cycles
; i
< cycles
; i
++)
5871 rt
->units
[i
] = xcalloc (rt
->num_units
, sizeof (unsigned char));
5876 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5879 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5881 for (i
= 0; i
< uses
; i
++)
5883 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5884 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5885 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
5886 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
5887 if (copies_in_use
>= copies
)
5895 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5898 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5900 for (i
= 0; i
< uses
; i
++)
5902 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5903 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5904 /* Note that this allows resources to be oversubscribed. That's
5905 essential to the way the optional scheduler works.
5906 resources_available reports when a resource is over-subscribed,
5907 so it's easy to tell. */
5908 rt
->units
[stage
+ cycle
][unit
]++;
5914 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5917 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5919 for (i
= 0; i
< uses
; i
++)
5921 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5922 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5923 assert (rt
->units
[stage
+ cycle
][unit
] > 0);
5924 rt
->units
[stage
+ cycle
][unit
]--;
5929 /* Wrapper functions make parameterized resource reservation
5933 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
5935 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5941 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
5943 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5948 /* Note that this function does not check issue constraints, but
5949 solely whether the hardware is available to execute the given
5950 instructions together. It also doesn't check if the tinsns
5951 write the same state, or access the same tieports. That is
5952 checked by check_t1_t2_reads_and_writes. */
5955 resources_conflict (vliw_insn
*vinsn
)
5958 static resource_table
*rt
= NULL
;
5960 /* This is the most common case by far. Optimize it. */
5961 if (vinsn
->num_slots
== 1)
5966 xtensa_isa isa
= xtensa_default_isa
;
5967 rt
= new_resource_table
5968 (isa
, xtensa_isa_num_pipe_stages (isa
),
5969 xtensa_isa_num_funcUnits (isa
),
5970 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
5971 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
5972 opcode_funcUnit_use_unit
,
5973 opcode_funcUnit_use_stage
);
5976 clear_resource_table (rt
);
5978 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5980 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
5982 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
5989 /* finish_vinsn, emit_single_op and helper functions. */
5991 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
5992 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
5993 static void xg_assemble_vliw_tokens (vliw_insn
*);
5996 /* We have reached the end of a bundle; emit into the frag. */
5999 finish_vinsn (vliw_insn
*vinsn
)
6006 if (find_vinsn_conflicts (vinsn
))
6008 xg_clear_vinsn (vinsn
);
6012 /* First, find a format that works. */
6013 if (vinsn
->format
== XTENSA_UNDEFINED
)
6014 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6016 if (vinsn
->format
== XTENSA_UNDEFINED
)
6018 as_where (&file_name
, &line
);
6019 as_bad_where (file_name
, line
,
6020 _("couldn't find a valid instruction format"));
6021 fprintf (stderr
, _(" ops were: "));
6022 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6023 fprintf (stderr
, _(" %s;"),
6024 xtensa_opcode_name (xtensa_default_isa
,
6025 vinsn
->slots
[i
].opcode
));
6026 fprintf (stderr
, _("\n"));
6027 xg_clear_vinsn (vinsn
);
6031 if (vinsn
->num_slots
6032 != xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
))
6034 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
6035 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
6036 xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
),
6038 xg_clear_vinsn (vinsn
);
6042 if (resources_conflict (vinsn
))
6044 as_where (&file_name
, &line
);
6045 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6046 fprintf (stderr
, " ops were: ");
6047 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6048 fprintf (stderr
, " %s;",
6049 xtensa_opcode_name (xtensa_default_isa
,
6050 vinsn
->slots
[i
].opcode
));
6051 fprintf (stderr
, "\n");
6052 xg_clear_vinsn (vinsn
);
6056 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6058 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
6060 symbolS
*lit_sym
= NULL
;
6062 bfd_boolean e
= FALSE
;
6063 bfd_boolean saved_density
= density_supported
;
6065 /* We don't want to narrow ops inside multi-slot bundles. */
6066 if (vinsn
->num_slots
> 1)
6067 density_supported
= FALSE
;
6069 istack_init (&slotstack
);
6070 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
6072 vinsn
->slots
[i
].opcode
=
6073 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6075 vinsn
->slots
[i
].ntok
= 0;
6078 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
6084 density_supported
= saved_density
;
6088 xg_clear_vinsn (vinsn
);
6092 for (j
= 0; j
< slotstack
.ninsn
; j
++)
6094 TInsn
*insn
= &slotstack
.insn
[j
];
6095 if (insn
->insn_type
== ITYPE_LITERAL
)
6097 assert (lit_sym
== NULL
);
6098 lit_sym
= xg_assemble_literal (insn
);
6102 assert (insn
->insn_type
== ITYPE_INSN
);
6104 xg_resolve_literals (insn
, lit_sym
);
6105 if (j
!= slotstack
.ninsn
- 1)
6106 emit_single_op (insn
);
6110 if (vinsn
->num_slots
> 1)
6112 if (opcode_fits_format_slot
6113 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6116 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6120 emit_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6121 if (vinsn
->format
== XTENSA_UNDEFINED
)
6122 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6124 vinsn
->slots
[i
].opcode
6125 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6128 vinsn
->slots
[i
].ntok
= 0;
6133 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6134 vinsn
->format
= XTENSA_UNDEFINED
;
6139 /* Now check resource conflicts on the modified bundle. */
6140 if (resources_conflict (vinsn
))
6142 as_where (&file_name
, &line
);
6143 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6144 fprintf (stderr
, " ops were: ");
6145 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6146 fprintf (stderr
, " %s;",
6147 xtensa_opcode_name (xtensa_default_isa
,
6148 vinsn
->slots
[i
].opcode
));
6149 fprintf (stderr
, "\n");
6150 xg_clear_vinsn (vinsn
);
6154 /* First, find a format that works. */
6155 if (vinsn
->format
== XTENSA_UNDEFINED
)
6156 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6158 xg_assemble_vliw_tokens (vinsn
);
6160 xg_clear_vinsn (vinsn
);
6164 /* Given an vliw instruction, what conflicts are there in register
6165 usage and in writes to states and queues?
6167 This function does two things:
6168 1. Reports an error when a vinsn contains illegal combinations
6169 of writes to registers states or queues.
6170 2. Marks individual tinsns as not relaxable if the combination
6171 contains antidependencies.
6173 Job 2 handles things like swap semantics in instructions that need
6174 to be relaxed. For example,
6178 normally would be relaxed to
6183 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6185 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6187 then we can't relax it into
6190 { add a0, a1, a0 ; add a2, a0, a4 ; }
6192 because the value of a0 is trashed before the second add can read it. */
6194 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6197 find_vinsn_conflicts (vliw_insn
*vinsn
)
6201 xtensa_isa isa
= xtensa_default_isa
;
6203 assert (!past_xtensa_end
);
6205 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6207 TInsn
*op1
= &vinsn
->slots
[i
];
6208 if (op1
->is_specific_opcode
)
6209 op1
->keep_wide
= TRUE
;
6211 op1
->keep_wide
= FALSE
;
6214 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6216 TInsn
*op1
= &vinsn
->slots
[i
];
6218 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6221 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6225 TInsn
*op2
= &vinsn
->slots
[j
];
6226 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6227 switch (conflict_type
)
6230 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6231 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6232 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6235 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6236 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6237 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6240 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"),
6241 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6242 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6245 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"),
6246 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6247 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6250 /* Everything is OK. */
6253 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6254 || conflict_type
== 'a');
6261 as_bad (_("multiple branches or jumps in the same bundle"));
6269 /* Check how the state used by t1 and t2 relate.
6272 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6273 case B: no relationship between what is read and written (both could
6274 read the same reg though)
6275 case C: t1 writes a register t2 writes (a register conflict within a
6277 case D: t1 writes a state that t2 also writes
6278 case E: t1 writes a tie queue that t2 also writes
6279 case F: two volatile queue accesses
6283 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6285 xtensa_isa isa
= xtensa_default_isa
;
6286 xtensa_regfile t1_regfile
, t2_regfile
;
6288 int t1_base_reg
, t1_last_reg
;
6289 int t2_base_reg
, t2_last_reg
;
6290 char t1_inout
, t2_inout
;
6292 char conflict
= 'b';
6297 bfd_boolean t1_volatile
= FALSE
;
6298 bfd_boolean t2_volatile
= FALSE
;
6300 /* Check registers. */
6301 for (j
= 0; j
< t2
->ntok
; j
++)
6303 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6306 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6307 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6308 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6310 for (i
= 0; i
< t1
->ntok
; i
++)
6312 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6315 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6317 if (t1_regfile
!= t2_regfile
)
6320 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6321 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6323 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6324 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6326 if (t1_inout
== 'm' || t1_inout
== 'o'
6327 || t2_inout
== 'm' || t2_inout
== 'o')
6334 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6335 t1_last_reg
= (t1_base_reg
6336 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6338 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6340 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6342 if (t1_reg
!= t2_reg
)
6345 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6351 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6357 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6365 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6366 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6367 for (j
= 0; j
< t2_states
; j
++)
6369 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6370 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6371 for (i
= 0; i
< t1_states
; i
++)
6373 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6374 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6378 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6384 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6390 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6395 /* Check tieports. */
6396 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6397 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6398 for (j
= 0; j
< t2_interfaces
; j
++)
6400 xtensa_interface t2_int
6401 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6402 int t2_class
= xtensa_interface_class_id (isa
, t2_int
);
6404 t2_inout
= xtensa_interface_inout (isa
, t2_int
);
6405 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1)
6408 for (i
= 0; i
< t1_interfaces
; i
++)
6410 xtensa_interface t1_int
6411 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6412 int t1_class
= xtensa_interface_class_id (isa
, t1_int
);
6414 t1_inout
= xtensa_interface_inout (isa
, t1_int
);
6415 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1)
6418 if (t1_volatile
&& t2_volatile
&& (t1_class
== t2_class
))
6421 if (t1_int
!= t2_int
)
6424 if (t2_inout
== 'i' && t1_inout
== 'o')
6430 if (t1_inout
== 'i' && t2_inout
== 'o')
6436 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6445 static xtensa_format
6446 xg_find_narrowest_format (vliw_insn
*vinsn
)
6448 /* Right now we assume that the ops within the vinsn are properly
6449 ordered for the slots that the programmer wanted them in. In
6450 other words, we don't rearrange the ops in hopes of finding a
6451 better format. The scheduler handles that. */
6453 xtensa_isa isa
= xtensa_default_isa
;
6454 xtensa_format format
;
6455 vliw_insn v_copy
= *vinsn
;
6456 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6458 if (vinsn
->num_slots
== 1)
6459 return xg_get_single_format (vinsn
->slots
[0].opcode
);
6461 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6464 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6468 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6470 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6472 v_copy
.slots
[slot
].opcode
=
6473 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6474 v_copy
.slots
[slot
].ntok
= 0;
6477 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6480 else if (v_copy
.num_slots
> 1)
6483 /* Try the widened version. */
6484 if (!v_copy
.slots
[slot
].keep_wide
6485 && !v_copy
.slots
[slot
].is_specific_opcode
6486 && xg_is_single_relaxable_insn (&v_copy
.slots
[slot
],
6488 && opcode_fits_format_slot (widened
.opcode
,
6491 v_copy
.slots
[slot
] = widened
;
6496 if (fit
== v_copy
.num_slots
)
6499 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6500 vinsn
->format
= format
;
6506 if (format
== xtensa_isa_num_formats (isa
))
6507 return XTENSA_UNDEFINED
;
6513 /* Return the additional space needed in a frag
6514 for possible relaxations of any ops in a VLIW insn.
6515 Also fill out the relaxations that might be required of
6516 each tinsn in the vinsn. */
6519 relaxation_requirements (vliw_insn
*vinsn
, bfd_boolean
*pfinish_frag
)
6521 bfd_boolean finish_frag
= FALSE
;
6522 int extra_space
= 0;
6525 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6527 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6528 if (!tinsn_has_symbolic_operands (tinsn
))
6530 /* A narrow instruction could be widened later to help
6531 alignment issues. */
6532 if (xg_is_single_relaxable_insn (tinsn
, 0, TRUE
)
6533 && !tinsn
->is_specific_opcode
6534 && vinsn
->num_slots
== 1)
6536 /* Difference in bytes between narrow and wide insns... */
6538 tinsn
->subtype
= RELAX_NARROW
;
6543 if (workaround_b_j_loop_end
6544 && tinsn
->opcode
== xtensa_jx_opcode
6545 && use_transform ())
6547 /* Add 2 of these. */
6548 extra_space
+= 3; /* for the nop size */
6549 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6552 /* Need to assemble it with space for the relocation. */
6553 if (xg_is_relaxable_insn (tinsn
, 0)
6554 && !tinsn
->is_specific_opcode
)
6556 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6557 int max_literal_size
=
6558 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6560 tinsn
->literal_space
= max_literal_size
;
6562 tinsn
->subtype
= RELAX_IMMED
;
6563 extra_space
+= max_size
;
6567 /* A fix record will be added for this instruction prior
6568 to relaxation, so make it end the frag. */
6573 *pfinish_frag
= finish_frag
;
6579 bundle_tinsn (TInsn
*tinsn
, vliw_insn
*vinsn
)
6581 xtensa_isa isa
= xtensa_default_isa
;
6582 int slot
, chosen_slot
;
6584 vinsn
->format
= xg_get_single_format (tinsn
->opcode
);
6585 assert (vinsn
->format
!= XTENSA_UNDEFINED
);
6586 vinsn
->num_slots
= xtensa_format_num_slots (isa
, vinsn
->format
);
6588 chosen_slot
= xg_get_single_slot (tinsn
->opcode
);
6589 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6591 if (slot
== chosen_slot
)
6592 vinsn
->slots
[slot
] = *tinsn
;
6595 vinsn
->slots
[slot
].opcode
=
6596 xtensa_format_slot_nop_opcode (isa
, vinsn
->format
, slot
);
6597 vinsn
->slots
[slot
].ntok
= 0;
6598 vinsn
->slots
[slot
].insn_type
= ITYPE_INSN
;
6605 emit_single_op (TInsn
*orig_insn
)
6608 IStack istack
; /* put instructions into here */
6609 symbolS
*lit_sym
= NULL
;
6610 symbolS
*label_sym
= NULL
;
6612 istack_init (&istack
);
6614 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6615 Because the scheduling and bundling characteristics of movi and
6616 l32r or const16 are so different, we can do much better if we relax
6617 it prior to scheduling and bundling, rather than after. */
6618 if ((orig_insn
->opcode
== xtensa_movi_opcode
6619 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
6620 && !cur_vinsn
.inside_bundle
6621 && (orig_insn
->tok
[1].X_op
== O_symbol
6622 || orig_insn
->tok
[1].X_op
== O_pltrel
)
6623 && !orig_insn
->is_specific_opcode
&& use_transform ())
6624 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
6626 if (xg_expand_assembly_insn (&istack
, orig_insn
))
6629 for (i
= 0; i
< istack
.ninsn
; i
++)
6631 TInsn
*insn
= &istack
.insn
[i
];
6632 switch (insn
->insn_type
)
6635 assert (lit_sym
== NULL
);
6636 lit_sym
= xg_assemble_literal (insn
);
6640 static int relaxed_sym_idx
= 0;
6641 char *label
= xmalloc (strlen (FAKE_LABEL_NAME
) + 12);
6642 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
6644 assert (label_sym
== NULL
);
6645 label_sym
= symbol_find_or_make (label
);
6654 xg_resolve_literals (insn
, lit_sym
);
6656 xg_resolve_labels (insn
, label_sym
);
6658 bundle_tinsn (insn
, &v
);
6673 total_frag_text_expansion (fragS
*fragP
)
6676 int total_expansion
= 0;
6678 for (slot
= 0; slot
< MAX_SLOTS
; slot
++)
6679 total_expansion
+= fragP
->tc_frag_data
.text_expansion
[slot
];
6681 return total_expansion
;
6685 /* Emit a vliw instruction to the current fragment. */
6688 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
6690 bfd_boolean finish_frag
;
6691 bfd_boolean is_jump
= FALSE
;
6692 bfd_boolean is_branch
= FALSE
;
6693 xtensa_isa isa
= xtensa_default_isa
;
6698 struct dwarf2_line_info debug_line
;
6699 bfd_boolean loc_directive_seen
= FALSE
;
6702 memset (&debug_line
, 0, sizeof (struct dwarf2_line_info
));
6704 if (generating_literals
)
6706 static int reported
= 0;
6708 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
6709 _("cannot assemble into a literal fragment"));
6716 if (frag_now_fix () != 0
6717 && (! frag_now
->tc_frag_data
.is_insn
6718 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6719 || !use_transform () != frag_now
->tc_frag_data
.is_no_transform
6720 || (directive_state
[directive_longcalls
]
6721 != frag_now
->tc_frag_data
.use_longcalls
)
6722 || (directive_state
[directive_absolute_literals
]
6723 != frag_now
->tc_frag_data
.use_absolute_literals
)))
6725 frag_wane (frag_now
);
6727 xtensa_set_frag_assembly_state (frag_now
);
6730 if (workaround_a0_b_retw
6731 && vinsn
->num_slots
== 1
6732 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
6733 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
6734 && use_transform ())
6736 has_a0_b_retw
= TRUE
;
6738 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
6739 After the first assembly pass we will check all of them and
6740 add a nop if needed. */
6741 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6742 frag_var (rs_machine_dependent
, 4, 4,
6743 RELAX_ADD_NOP_IF_A0_B_RETW
,
6744 frag_now
->fr_symbol
,
6745 frag_now
->fr_offset
,
6747 xtensa_set_frag_assembly_state (frag_now
);
6748 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6749 frag_var (rs_machine_dependent
, 4, 4,
6750 RELAX_ADD_NOP_IF_A0_B_RETW
,
6751 frag_now
->fr_symbol
,
6752 frag_now
->fr_offset
,
6754 xtensa_set_frag_assembly_state (frag_now
);
6757 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6759 tinsn
= &vinsn
->slots
[slot
];
6761 /* See if the instruction implies an aligned section. */
6762 if (xtensa_opcode_is_loop (isa
, tinsn
->opcode
) == 1)
6763 record_alignment (now_seg
, 2);
6765 /* Determine the best line number for debug info. */
6766 if ((tinsn
->loc_directive_seen
|| !loc_directive_seen
)
6767 && (tinsn
->debug_line
.filenum
!= debug_line
.filenum
6768 || tinsn
->debug_line
.line
< debug_line
.line
6769 || tinsn
->debug_line
.column
< debug_line
.column
))
6770 debug_line
= tinsn
->debug_line
;
6771 if (tinsn
->loc_directive_seen
)
6772 loc_directive_seen
= TRUE
;
6775 /* Special cases for instructions that force an alignment... */
6776 /* None of these opcodes are bundle-able. */
6777 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
6781 /* Remember the symbol that marks the end of the loop in the frag
6782 that marks the start of the loop. This way we can easily find
6783 the end of the loop at the beginning, without adding special code
6784 to mark the loop instructions themselves. */
6785 symbolS
*target_sym
= NULL
;
6786 if (vinsn
->slots
[0].tok
[1].X_op
== O_symbol
)
6787 target_sym
= vinsn
->slots
[0].tok
[1].X_add_symbol
;
6789 xtensa_set_frag_assembly_state (frag_now
);
6790 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6792 max_fill
= get_text_align_max_fill_size
6793 (get_text_align_power (xtensa_fetch_width
),
6794 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
6796 if (use_transform ())
6797 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
6798 RELAX_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
6800 frag_var (rs_machine_dependent
, 0, 0,
6801 RELAX_CHECK_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
6802 xtensa_set_frag_assembly_state (frag_now
);
6805 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
6806 && !vinsn
->slots
[0].is_specific_opcode
)
6808 xtensa_mark_literal_pool_location ();
6809 xtensa_move_labels (frag_now
, 0);
6810 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
6813 if (vinsn
->num_slots
== 1)
6815 if (workaround_a0_b_retw
&& use_transform ())
6816 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
6817 is_register_writer (&vinsn
->slots
[0], "a", 0));
6819 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
6820 is_bad_loopend_opcode (&vinsn
->slots
[0]));
6823 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
6825 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
6827 extra_space
= relaxation_requirements (vinsn
, &finish_frag
);
6829 /* vinsn_to_insnbuf will produce the error. */
6830 if (vinsn
->format
!= XTENSA_UNDEFINED
)
6832 f
= frag_more (insn_size
+ extra_space
);
6833 xtensa_set_frag_assembly_state (frag_now
);
6834 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6837 vinsn_to_insnbuf (vinsn
, f
, frag_now
, FALSE
);
6838 if (vinsn
->format
== XTENSA_UNDEFINED
)
6841 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, (unsigned char *) f
, 0);
6843 if (debug_type
== DEBUG_DWARF2
|| loc_directive_seen
)
6844 dwarf2_gen_line_info (frag_now_fix () - (insn_size
+ extra_space
),
6847 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6849 tinsn
= &vinsn
->slots
[slot
];
6850 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
6851 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
6852 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
6853 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
6854 if (tinsn
->literal_space
!= 0)
6855 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
6857 if (tinsn
->subtype
== RELAX_NARROW
)
6858 assert (vinsn
->num_slots
== 1);
6859 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
6861 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
6864 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->offset
6865 || tinsn
->literal_frag
|| is_jump
|| is_branch
)
6869 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6870 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
6874 frag_variant (rs_machine_dependent
,
6875 extra_space
, extra_space
, RELAX_SLOTS
,
6876 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
6877 xtensa_set_frag_assembly_state (frag_now
);
6880 /* Special cases for loops:
6881 close_loop_end should be inserted AFTER short_loop.
6882 Make sure that CLOSE loops are processed BEFORE short_loops
6883 when converting them. */
6885 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
6886 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1
6887 && !vinsn
->slots
[0].is_specific_opcode
)
6889 if (workaround_short_loop
&& use_transform ())
6891 maybe_has_short_loop
= TRUE
;
6892 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6893 frag_var (rs_machine_dependent
, 4, 4,
6894 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6895 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6896 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6897 frag_var (rs_machine_dependent
, 4, 4,
6898 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6899 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6902 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
6903 loop at least 12 bytes away from another loop's end. */
6904 if (workaround_close_loop_end
&& use_transform ())
6906 maybe_has_close_loop_end
= TRUE
;
6907 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6908 frag_var (rs_machine_dependent
, 12, 12,
6909 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
6910 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6914 if (use_transform ())
6918 assert (finish_frag
);
6919 frag_var (rs_machine_dependent
,
6920 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6922 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6923 xtensa_set_frag_assembly_state (frag_now
);
6925 else if (is_branch
&& do_align_targets ())
6927 assert (finish_frag
);
6928 frag_var (rs_machine_dependent
,
6929 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6930 RELAX_MAYBE_UNREACHABLE
,
6931 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6932 xtensa_set_frag_assembly_state (frag_now
);
6933 frag_var (rs_machine_dependent
,
6935 RELAX_MAYBE_DESIRE_ALIGN
,
6936 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6937 xtensa_set_frag_assembly_state (frag_now
);
6941 /* Now, if the original opcode was a call... */
6942 if (do_align_targets ()
6943 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
6945 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
6946 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6947 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
6948 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6949 xtensa_set_frag_assembly_state (frag_now
);
6952 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6954 frag_wane (frag_now
);
6956 xtensa_set_frag_assembly_state (frag_now
);
6961 /* xtensa_end and helper functions. */
6963 static void xtensa_cleanup_align_frags (void);
6964 static void xtensa_fix_target_frags (void);
6965 static void xtensa_mark_narrow_branches (void);
6966 static void xtensa_mark_zcl_first_insns (void);
6967 static void xtensa_mark_difference_of_two_symbols (void);
6968 static void xtensa_fix_a0_b_retw_frags (void);
6969 static void xtensa_fix_b_j_loop_end_frags (void);
6970 static void xtensa_fix_close_loop_end_frags (void);
6971 static void xtensa_fix_short_loop_frags (void);
6972 static void xtensa_sanity_check (void);
6973 static void xtensa_add_config_info (void);
6978 directive_balance ();
6979 xtensa_flush_pending_output ();
6981 past_xtensa_end
= TRUE
;
6983 xtensa_move_literals ();
6985 xtensa_reorder_segments ();
6986 xtensa_cleanup_align_frags ();
6987 xtensa_fix_target_frags ();
6988 if (workaround_a0_b_retw
&& has_a0_b_retw
)
6989 xtensa_fix_a0_b_retw_frags ();
6990 if (workaround_b_j_loop_end
)
6991 xtensa_fix_b_j_loop_end_frags ();
6993 /* "close_loop_end" should be processed BEFORE "short_loop". */
6994 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
6995 xtensa_fix_close_loop_end_frags ();
6997 if (workaround_short_loop
&& maybe_has_short_loop
)
6998 xtensa_fix_short_loop_frags ();
7000 xtensa_mark_narrow_branches ();
7001 xtensa_mark_zcl_first_insns ();
7003 xtensa_sanity_check ();
7005 xtensa_add_config_info ();
7010 xtensa_cleanup_align_frags (void)
7015 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7016 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7019 /* Walk over all of the fragments in a subsection. */
7020 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7022 if ((fragP
->fr_type
== rs_align
7023 || fragP
->fr_type
== rs_align_code
7024 || (fragP
->fr_type
== rs_machine_dependent
7025 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
7026 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
7027 && fragP
->fr_fix
== 0)
7029 fragS
*next
= fragP
->fr_next
;
7032 && next
->fr_fix
== 0
7033 && next
->fr_type
== rs_machine_dependent
7034 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7037 next
= next
->fr_next
;
7040 /* If we don't widen branch targets, then they
7041 will be easier to align. */
7042 if (fragP
->tc_frag_data
.is_branch_target
7043 && fragP
->fr_opcode
== fragP
->fr_literal
7044 && fragP
->fr_type
== rs_machine_dependent
7045 && fragP
->fr_subtype
== RELAX_SLOTS
7046 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
7048 if (fragP
->fr_type
== rs_machine_dependent
7049 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
7050 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
7056 /* Re-process all of the fragments looking to convert all of the
7057 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
7058 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7059 Otherwise, convert to a .fill 0. */
7062 xtensa_fix_target_frags (void)
7067 /* When this routine is called, all of the subsections are still intact
7068 so we walk over subsections instead of sections. */
7069 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7070 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7074 /* Walk over all of the fragments in a subsection. */
7075 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7077 if (fragP
->fr_type
== rs_machine_dependent
7078 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7080 if (next_frag_is_branch_target (fragP
))
7081 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7090 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
7093 xtensa_mark_narrow_branches (void)
7098 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7099 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7102 /* Walk over all of the fragments in a subsection. */
7103 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7105 if (fragP
->fr_type
== rs_machine_dependent
7106 && fragP
->fr_subtype
== RELAX_SLOTS
7107 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7111 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7112 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
7114 if (vinsn
.num_slots
== 1
7115 && xtensa_opcode_is_branch (xtensa_default_isa
,
7116 vinsn
.slots
[0].opcode
) == 1
7117 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
7118 && is_narrow_branch_guaranteed_in_range (fragP
,
7121 fragP
->fr_subtype
= RELAX_SLOTS
;
7122 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
7123 fragP
->tc_frag_data
.is_aligning_branch
= 1;
7131 /* A branch is typically widened only when its target is out of
7132 range. However, we would like to widen them to align a subsequent
7133 branch target when possible.
7135 Because the branch relaxation code is so convoluted, the optimal solution
7136 (combining the two cases) is difficult to get right in all circumstances.
7137 We therefore go with an "almost as good" solution, where we only
7138 use for alignment narrow branches that definitely will not expand to a
7139 jump and a branch. These functions find and mark these cases. */
7141 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
7142 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7143 We start counting beginning with the frag after the 2-byte branch, so the
7144 maximum offset is (4 - 2) + 63 = 65. */
7145 #define MAX_IMMED6 65
7147 static offsetT
unrelaxed_frag_max_size (fragS
*);
7150 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
7152 const expressionS
*expr
= &tinsn
->tok
[1];
7153 symbolS
*symbolP
= expr
->X_add_symbol
;
7154 offsetT max_distance
= expr
->X_add_number
;
7157 if (expr
->X_op
!= O_symbol
)
7160 target_frag
= symbol_get_frag (symbolP
);
7162 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
7163 if (is_branch_jmp_to_next (tinsn
, fragP
))
7166 /* The branch doesn't branch over it's own frag,
7167 but over the subsequent ones. */
7168 fragP
= fragP
->fr_next
;
7169 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
7171 max_distance
+= unrelaxed_frag_max_size (fragP
);
7172 fragP
= fragP
->fr_next
;
7174 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
7181 xtensa_mark_zcl_first_insns (void)
7186 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7187 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7190 /* Walk over all of the fragments in a subsection. */
7191 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7193 if (fragP
->fr_type
== rs_machine_dependent
7194 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7195 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7197 /* Find the loop frag. */
7198 fragS
*targ_frag
= next_non_empty_frag (fragP
);
7199 /* Find the first insn frag. */
7200 targ_frag
= next_non_empty_frag (targ_frag
);
7202 /* Of course, sometimes (mostly for toy test cases) a
7203 zero-cost loop instruction is the last in a section. */
7206 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
7207 /* Do not widen a frag that is the first instruction of a
7208 zero-cost loop. It makes that loop harder to align. */
7209 if (targ_frag
->fr_type
== rs_machine_dependent
7210 && targ_frag
->fr_subtype
== RELAX_SLOTS
7211 && (targ_frag
->tc_frag_data
.slot_subtypes
[0]
7214 if (targ_frag
->tc_frag_data
.is_aligning_branch
)
7215 targ_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
7218 frag_wane (targ_frag
);
7219 targ_frag
->tc_frag_data
.slot_subtypes
[0] = 0;
7223 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
7231 /* Some difference-of-symbols expressions make it out to the linker. Some
7232 don't. If one does, then the linker can optimize between the two labels.
7233 If it doesn't, then the linker shouldn't. */
7236 xtensa_mark_difference_of_two_symbols (void)
7240 for (expr_sym
= expr_symbols
; expr_sym
;
7241 expr_sym
= symbol_get_tc (expr_sym
)->next_expr_symbol
)
7243 expressionS
*expr
= symbol_get_value_expression (expr_sym
);
7245 if (expr
->X_op
== O_subtract
)
7247 symbolS
*left
= expr
->X_add_symbol
;
7248 symbolS
*right
= expr
->X_op_symbol
;
7250 /* Difference of two symbols not in the same section
7251 are handled with relocations in the linker. */
7252 if (S_GET_SEGMENT (left
) == S_GET_SEGMENT (right
))
7257 if (symbol_get_frag (left
)->fr_address
7258 <= symbol_get_frag (right
)->fr_address
)
7260 start
= symbol_get_frag (left
);
7261 end
= symbol_get_frag (right
);
7265 start
= symbol_get_frag (right
);
7266 end
= symbol_get_frag (left
);
7270 start
->tc_frag_data
.is_no_transform
= 1;
7271 start
= start
->fr_next
;
7273 while (start
&& start
->fr_address
< end
->fr_address
);
7280 /* Re-process all of the fragments looking to convert all of the
7281 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7282 conditional branch or a retw/retw.n, convert this frag to one that
7283 will generate a NOP. In any case close it off with a .fill 0. */
7285 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
7288 xtensa_fix_a0_b_retw_frags (void)
7293 /* When this routine is called, all of the subsections are still intact
7294 so we walk over subsections instead of sections. */
7295 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7296 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7300 /* Walk over all of the fragments in a subsection. */
7301 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7303 if (fragP
->fr_type
== rs_machine_dependent
7304 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
7306 if (next_instrs_are_b_retw (fragP
))
7308 if (fragP
->tc_frag_data
.is_no_transform
)
7309 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7311 relax_frag_add_nop (fragP
);
7321 next_instrs_are_b_retw (fragS
*fragP
)
7323 xtensa_opcode opcode
;
7325 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
7326 static xtensa_insnbuf insnbuf
= NULL
;
7327 static xtensa_insnbuf slotbuf
= NULL
;
7328 xtensa_isa isa
= xtensa_default_isa
;
7331 bfd_boolean branch_seen
= FALSE
;
7335 insnbuf
= xtensa_insnbuf_alloc (isa
);
7336 slotbuf
= xtensa_insnbuf_alloc (isa
);
7339 if (next_fragP
== NULL
)
7342 /* Check for the conditional branch. */
7343 xtensa_insnbuf_from_chars
7344 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7345 fmt
= xtensa_format_decode (isa
, insnbuf
);
7346 if (fmt
== XTENSA_UNDEFINED
)
7349 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7351 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
7352 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
7354 branch_seen
= (branch_seen
7355 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
7361 offset
+= xtensa_format_length (isa
, fmt
);
7362 if (offset
== next_fragP
->fr_fix
)
7364 next_fragP
= next_non_empty_frag (next_fragP
);
7368 if (next_fragP
== NULL
)
7371 /* Check for the retw/retw.n. */
7372 xtensa_insnbuf_from_chars
7373 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7374 fmt
= xtensa_format_decode (isa
, insnbuf
);
7376 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
7377 have no problems. */
7378 if (fmt
== XTENSA_UNDEFINED
7379 || xtensa_format_num_slots (isa
, fmt
) != 1)
7382 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
7383 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
7385 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
7392 /* Re-process all of the fragments looking to convert all of the
7393 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
7394 loop end label, convert this frag to one that will generate a NOP.
7395 In any case close it off with a .fill 0. */
7397 static bfd_boolean
next_instr_is_loop_end (fragS
*);
7400 xtensa_fix_b_j_loop_end_frags (void)
7405 /* When this routine is called, all of the subsections are still intact
7406 so we walk over subsections instead of sections. */
7407 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7408 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7412 /* Walk over all of the fragments in a subsection. */
7413 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7415 if (fragP
->fr_type
== rs_machine_dependent
7416 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
7418 if (next_instr_is_loop_end (fragP
))
7420 if (fragP
->tc_frag_data
.is_no_transform
)
7421 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
7423 relax_frag_add_nop (fragP
);
7433 next_instr_is_loop_end (fragS
*fragP
)
7435 const fragS
*next_fragP
;
7437 if (next_frag_is_loop_target (fragP
))
7440 next_fragP
= next_non_empty_frag (fragP
);
7441 if (next_fragP
== NULL
)
7444 if (!next_frag_is_loop_target (next_fragP
))
7447 /* If the size is >= 3 then there is more than one instruction here.
7448 The hardware bug will not fire. */
7449 if (next_fragP
->fr_fix
> 3)
7456 /* Re-process all of the fragments looking to convert all of the
7457 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
7458 not MY loop's loop end within 12 bytes, add enough nops here to
7459 make it at least 12 bytes away. In any case close it off with a
7462 static offsetT min_bytes_to_other_loop_end
7463 (fragS
*, fragS
*, offsetT
);
7466 xtensa_fix_close_loop_end_frags (void)
7471 /* When this routine is called, all of the subsections are still intact
7472 so we walk over subsections instead of sections. */
7473 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7474 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7478 fragS
*current_target
= NULL
;
7480 /* Walk over all of the fragments in a subsection. */
7481 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7483 if (fragP
->fr_type
== rs_machine_dependent
7484 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7485 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7486 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7489 && fragP
->fr_type
== rs_machine_dependent
7490 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
7493 int bytes_added
= 0;
7495 #define REQUIRED_LOOP_DIVIDING_BYTES 12
7496 /* Max out at 12. */
7497 min_bytes
= min_bytes_to_other_loop_end
7498 (fragP
->fr_next
, current_target
, REQUIRED_LOOP_DIVIDING_BYTES
);
7500 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
7502 if (fragP
->tc_frag_data
.is_no_transform
)
7503 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
7506 while (min_bytes
+ bytes_added
7507 < REQUIRED_LOOP_DIVIDING_BYTES
)
7511 if (fragP
->fr_var
< length
)
7512 as_fatal (_("fr_var %lu < length %d"),
7513 (long) fragP
->fr_var
, length
);
7516 assemble_nop (length
,
7517 fragP
->fr_literal
+ fragP
->fr_fix
);
7518 fragP
->fr_fix
+= length
;
7519 fragP
->fr_var
-= length
;
7521 bytes_added
+= length
;
7527 assert (fragP
->fr_type
!= rs_machine_dependent
7528 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
7534 static offsetT
unrelaxed_frag_min_size (fragS
*);
7537 min_bytes_to_other_loop_end (fragS
*fragP
,
7538 fragS
*current_target
,
7542 fragS
*current_fragP
;
7544 for (current_fragP
= fragP
;
7546 current_fragP
= current_fragP
->fr_next
)
7548 if (current_fragP
->tc_frag_data
.is_loop_target
7549 && current_fragP
!= current_target
)
7552 offset
+= unrelaxed_frag_min_size (current_fragP
);
7554 if (offset
>= max_size
)
7562 unrelaxed_frag_min_size (fragS
*fragP
)
7564 offsetT size
= fragP
->fr_fix
;
7566 /* Add fill size. */
7567 if (fragP
->fr_type
== rs_fill
)
7568 size
+= fragP
->fr_offset
;
7575 unrelaxed_frag_max_size (fragS
*fragP
)
7577 offsetT size
= fragP
->fr_fix
;
7578 switch (fragP
->fr_type
)
7581 /* Empty frags created by the obstack allocation scheme
7582 end up with type 0. */
7587 size
+= fragP
->fr_offset
;
7595 /* No further adjustments needed. */
7597 case rs_machine_dependent
:
7598 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
7599 size
+= fragP
->fr_var
;
7602 /* We had darn well better know how big it is. */
7611 /* Re-process all of the fragments looking to convert all
7612 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
7615 1) the instruction size count to the loop end label
7616 is too short (<= 2 instructions),
7617 2) loop has a jump or branch in it
7620 1) workaround_all_short_loops is TRUE
7621 2) The generating loop was a 'loopgtz' or 'loopnez'
7622 3) the instruction size count to the loop end label is too short
7624 then convert this frag (and maybe the next one) to generate a NOP.
7625 In any case close it off with a .fill 0. */
7627 static int count_insns_to_loop_end (fragS
*, bfd_boolean
, int);
7628 static bfd_boolean
branch_before_loop_end (fragS
*);
7631 xtensa_fix_short_loop_frags (void)
7636 /* When this routine is called, all of the subsections are still intact
7637 so we walk over subsections instead of sections. */
7638 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7639 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7642 fragS
*current_target
= NULL
;
7643 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
7645 /* Walk over all of the fragments in a subsection. */
7646 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7648 if (fragP
->fr_type
== rs_machine_dependent
7649 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7650 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7653 fragS
*loop_frag
= next_non_empty_frag (fragP
);
7654 tinsn_from_chars (&t_insn
, loop_frag
->fr_opcode
, 0);
7655 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7656 current_opcode
= t_insn
.opcode
;
7657 assert (xtensa_opcode_is_loop (xtensa_default_isa
,
7658 current_opcode
) == 1);
7661 if (fragP
->fr_type
== rs_machine_dependent
7662 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7664 if (count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3) < 3
7665 && (branch_before_loop_end (fragP
->fr_next
)
7666 || (workaround_all_short_loops
7667 && current_opcode
!= XTENSA_UNDEFINED
7668 && current_opcode
!= xtensa_loop_opcode
)))
7670 if (fragP
->tc_frag_data
.is_no_transform
)
7671 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
7673 relax_frag_add_nop (fragP
);
7682 static int unrelaxed_frag_min_insn_count (fragS
*);
7685 count_insns_to_loop_end (fragS
*base_fragP
,
7686 bfd_boolean count_relax_add
,
7689 fragS
*fragP
= NULL
;
7694 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
7696 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
7697 if (insn_count
>= max_count
)
7700 if (count_relax_add
)
7702 if (fragP
->fr_type
== rs_machine_dependent
7703 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7705 /* In order to add the appropriate number of
7706 NOPs, we count an instruction for downstream
7709 if (insn_count
>= max_count
)
7719 unrelaxed_frag_min_insn_count (fragS
*fragP
)
7721 xtensa_isa isa
= xtensa_default_isa
;
7722 static xtensa_insnbuf insnbuf
= NULL
;
7726 if (!fragP
->tc_frag_data
.is_insn
)
7730 insnbuf
= xtensa_insnbuf_alloc (isa
);
7732 /* Decode the fixed instructions. */
7733 while (offset
< fragP
->fr_fix
)
7737 xtensa_insnbuf_from_chars
7738 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7739 fmt
= xtensa_format_decode (isa
, insnbuf
);
7741 if (fmt
== XTENSA_UNDEFINED
)
7743 as_fatal (_("undecodable instruction in instruction frag"));
7746 offset
+= xtensa_format_length (isa
, fmt
);
7754 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
7757 branch_before_loop_end (fragS
*base_fragP
)
7761 for (fragP
= base_fragP
;
7762 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
7763 fragP
= fragP
->fr_next
)
7765 if (unrelaxed_frag_has_b_j (fragP
))
7773 unrelaxed_frag_has_b_j (fragS
*fragP
)
7775 static xtensa_insnbuf insnbuf
= NULL
;
7776 xtensa_isa isa
= xtensa_default_isa
;
7779 if (!fragP
->tc_frag_data
.is_insn
)
7783 insnbuf
= xtensa_insnbuf_alloc (isa
);
7785 /* Decode the fixed instructions. */
7786 while (offset
< fragP
->fr_fix
)
7791 xtensa_insnbuf_from_chars
7792 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7793 fmt
= xtensa_format_decode (isa
, insnbuf
);
7794 if (fmt
== XTENSA_UNDEFINED
)
7797 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7799 xtensa_opcode opcode
=
7800 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
7801 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
7802 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
7805 offset
+= xtensa_format_length (isa
, fmt
);
7811 /* Checks to be made after initial assembly but before relaxation. */
7813 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
7814 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
7817 xtensa_sanity_check (void)
7824 as_where (&file_name
, &line
);
7825 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7826 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7830 /* Walk over all of the fragments in a subsection. */
7831 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7833 if (fragP
->fr_type
== rs_machine_dependent
7834 && fragP
->fr_subtype
== RELAX_SLOTS
7835 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7837 static xtensa_insnbuf insnbuf
= NULL
;
7840 if (fragP
->fr_opcode
!= NULL
)
7843 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7844 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7845 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
7847 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7848 t_insn
.opcode
) == 1)
7850 if (is_empty_loop (&t_insn
, fragP
))
7852 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7853 as_bad (_("invalid empty loop"));
7855 if (!is_local_forward_loop (&t_insn
, fragP
))
7857 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7858 as_bad (_("loop target does not follow "
7859 "loop instruction in section"));
7866 new_logical_line (file_name
, line
);
7870 #define LOOP_IMMED_OPN 1
7872 /* Return TRUE if the loop target is the next non-zero fragment. */
7875 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
7877 const expressionS
*expr
;
7881 if (insn
->insn_type
!= ITYPE_INSN
)
7884 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
7887 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7890 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7892 if (expr
->X_op
!= O_symbol
)
7895 symbolP
= expr
->X_add_symbol
;
7899 if (symbol_get_frag (symbolP
) == NULL
)
7902 if (S_GET_VALUE (symbolP
) != 0)
7905 /* Walk through the zero-size fragments from this one. If we find
7906 the target fragment, then this is a zero-size loop. */
7908 for (next_fragP
= fragP
->fr_next
;
7910 next_fragP
= next_fragP
->fr_next
)
7912 if (next_fragP
== symbol_get_frag (symbolP
))
7914 if (next_fragP
->fr_fix
!= 0)
7922 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
7924 const expressionS
*expr
;
7928 if (insn
->insn_type
!= ITYPE_INSN
)
7931 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
7934 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7937 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7939 if (expr
->X_op
!= O_symbol
)
7942 symbolP
= expr
->X_add_symbol
;
7946 if (symbol_get_frag (symbolP
) == NULL
)
7949 /* Walk through fragments until we find the target.
7950 If we do not find the target, then this is an invalid loop. */
7952 for (next_fragP
= fragP
->fr_next
;
7954 next_fragP
= next_fragP
->fr_next
)
7956 if (next_fragP
== symbol_get_frag (symbolP
))
7964 #define XTINFO_NAME "Xtensa_Info"
7965 #define XTINFO_NAMESZ 12
7966 #define XTINFO_TYPE 1
7969 xtensa_add_config_info (void)
7975 info_sec
= subseg_new (".xtensa.info", 0);
7976 bfd_set_section_flags (stdoutput
, info_sec
, SEC_HAS_CONTENTS
| SEC_READONLY
);
7978 data
= xmalloc (100);
7979 sprintf (data
, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n",
7980 XSHAL_USE_ABSOLUTE_LITERALS
, XSHAL_ABI
);
7981 sz
= strlen (data
) + 1;
7983 /* Add enough null terminators to pad to a word boundary. */
7986 while ((sz
& 3) != 0);
7988 /* Follow the standard note section layout:
7989 First write the length of the name string. */
7991 md_number_to_chars (p
, (valueT
) XTINFO_NAMESZ
, 4);
7993 /* Next comes the length of the "descriptor", i.e., the actual data. */
7995 md_number_to_chars (p
, (valueT
) sz
, 4);
7997 /* Write the note type. */
7999 md_number_to_chars (p
, (valueT
) XTINFO_TYPE
, 4);
8001 /* Write the name field. */
8002 p
= frag_more (XTINFO_NAMESZ
);
8003 memcpy (p
, XTINFO_NAME
, XTINFO_NAMESZ
);
8005 /* Finally, write the descriptor. */
8007 memcpy (p
, data
, sz
);
8013 /* Alignment Functions. */
8016 get_text_align_power (unsigned target_size
)
8018 if (target_size
<= 4)
8020 assert (target_size
== 8);
8026 get_text_align_max_fill_size (int align_pow
,
8027 bfd_boolean use_nops
,
8028 bfd_boolean use_no_density
)
8031 return (1 << align_pow
);
8033 return 3 * (1 << align_pow
);
8035 return 1 + (1 << align_pow
);
8039 /* Calculate the minimum bytes of fill needed at "address" to align a
8040 target instruction of size "target_size" so that it does not cross a
8041 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE,
8042 the fill can be an arbitrary number of bytes. Otherwise, the space must
8043 be filled by NOP instructions. */
8046 get_text_align_fill_size (addressT address
,
8049 bfd_boolean use_nops
,
8050 bfd_boolean use_no_density
)
8052 addressT alignment
, fill
, fill_limit
, fill_step
;
8053 bfd_boolean skip_one
= FALSE
;
8055 alignment
= (1 << align_pow
);
8056 assert (target_size
> 0 && alignment
>= (addressT
) target_size
);
8060 fill_limit
= alignment
;
8063 else if (!use_no_density
)
8065 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */
8066 fill_limit
= alignment
* 2;
8072 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */
8073 fill_limit
= alignment
* 3;
8077 /* Try all fill sizes until finding one that works. */
8078 for (fill
= 0; fill
< fill_limit
; fill
+= fill_step
)
8080 if (skip_one
&& fill
== 1)
8082 if ((address
+ fill
) >> align_pow
8083 == (address
+ fill
+ target_size
- 1) >> align_pow
)
8092 branch_align_power (segT sec
)
8094 /* If the Xtensa processor has a fetch width of 8 bytes, and the section
8095 is aligned to at least an 8-byte boundary, then a branch target need
8096 only fit within an 8-byte aligned block of memory to avoid a stall.
8097 Otherwise, try to fit branch targets within 4-byte aligned blocks
8098 (which may be insufficient, e.g., if the section has no alignment, but
8099 it's good enough). */
8100 if (xtensa_fetch_width
== 8)
8102 if (get_recorded_alignment (sec
) >= 3)
8106 assert (xtensa_fetch_width
== 4);
8112 /* This will assert if it is not possible. */
8115 get_text_align_nop_count (offsetT fill_size
, bfd_boolean use_no_density
)
8121 assert (fill_size
% 3 == 0);
8122 return (fill_size
/ 3);
8125 assert (fill_size
!= 1); /* Bad argument. */
8127 while (fill_size
> 1)
8130 if (fill_size
== 2 || fill_size
== 4)
8132 fill_size
-= insn_size
;
8135 assert (fill_size
!= 1); /* Bad algorithm. */
8141 get_text_align_nth_nop_size (offsetT fill_size
,
8143 bfd_boolean use_no_density
)
8150 assert (fill_size
!= 1); /* Bad argument. */
8152 while (fill_size
> 1)
8155 if (fill_size
== 2 || fill_size
== 4)
8157 fill_size
-= insn_size
;
8167 /* For the given fragment, find the appropriate address
8168 for it to begin at if we are using NOPs to align it. */
8171 get_noop_aligned_address (fragS
*fragP
, addressT address
)
8173 /* The rule is: get next fragment's FIRST instruction. Find
8174 the smallest number of bytes that need to be added to
8175 ensure that the next fragment's FIRST instruction will fit
8178 E.G., 2 bytes : 0, 1, 2 mod 4
8181 If the FIRST instruction MIGHT be relaxed,
8182 assume that it will become a 3-byte instruction.
8184 Note again here that LOOP instructions are not bundleable,
8185 and this relaxation only applies to LOOP opcodes. */
8188 int first_insn_size
;
8190 addressT pre_opcode_bytes
;
8193 xtensa_opcode opcode
;
8194 bfd_boolean is_loop
;
8196 assert (fragP
->fr_type
== rs_machine_dependent
);
8197 assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
8199 /* Find the loop frag. */
8200 first_insn
= next_non_empty_frag (fragP
);
8201 /* Now find the first insn frag. */
8202 first_insn
= next_non_empty_frag (first_insn
);
8204 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
8206 loop_insn_size
= xg_get_single_size (opcode
);
8208 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
8209 pre_opcode_bytes
+= loop_insn_size
;
8211 /* For loops, the alignment depends on the size of the
8212 instruction following the loop, not the LOOP instruction. */
8214 if (first_insn
== NULL
)
8215 first_insn_size
= xtensa_fetch_width
;
8217 first_insn_size
= get_loop_align_size (frag_format_size (first_insn
));
8219 /* If it was 8, then we'll need a larger alignment for the section. */
8220 align_power
= get_text_align_power (first_insn_size
);
8221 record_alignment (now_seg
, align_power
);
8223 fill_size
= get_text_align_fill_size
8224 (address
+ pre_opcode_bytes
, align_power
, first_insn_size
, TRUE
,
8225 fragP
->tc_frag_data
.is_no_density
);
8227 return address
+ fill_size
;
8231 /* 3 mechanisms for relaxing an alignment:
8233 Align to a power of 2.
8234 Align so the next fragment's instruction does not cross a word boundary.
8235 Align the current instruction so that if the next instruction
8236 were 3 bytes, it would not cross a word boundary.
8240 zeros - This is easy; always insert zeros.
8241 nops - 3-byte and 2-byte instructions
8245 >=5 : 3-byte instruction + fn (n-3)
8246 widening - widen previous instructions. */
8249 get_aligned_diff (fragS
*fragP
, addressT address
, offsetT
*max_diff
)
8251 addressT target_address
, loop_insn_offset
;
8253 xtensa_opcode loop_opcode
;
8254 bfd_boolean is_loop
;
8257 offsetT branch_align
;
8259 assert (fragP
->fr_type
== rs_machine_dependent
);
8260 switch (fragP
->fr_subtype
)
8262 case RELAX_DESIRE_ALIGN
:
8263 target_size
= next_frag_format_size (fragP
);
8264 if (target_size
== XTENSA_UNDEFINED
)
8266 align_power
= branch_align_power (now_seg
);
8267 branch_align
= 1 << align_power
;
8268 /* Don't count on the section alignment being as large as the target. */
8269 if (target_size
> branch_align
)
8270 target_size
= branch_align
;
8271 opt_diff
= get_text_align_fill_size (address
, align_power
,
8272 target_size
, FALSE
, FALSE
);
8274 *max_diff
= (opt_diff
+ branch_align
8275 - (target_size
+ ((address
+ opt_diff
) % branch_align
)));
8276 assert (*max_diff
>= opt_diff
);
8279 case RELAX_ALIGN_NEXT_OPCODE
:
8280 target_size
= get_loop_align_size (next_frag_format_size (fragP
));
8281 loop_insn_offset
= 0;
8282 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
8285 /* If the loop has been expanded then the LOOP instruction
8286 could be at an offset from this fragment. */
8287 if (next_non_empty_frag(fragP
)->tc_frag_data
.slot_subtypes
[0]
8289 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
8291 /* In an ideal world, which is what we are shooting for here,
8292 we wouldn't need to use any NOPs immediately prior to the
8293 LOOP instruction. If this approach fails, relax_frag_loop_align
8294 will call get_noop_aligned_address. */
8296 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
8297 align_power
= get_text_align_power (target_size
),
8298 opt_diff
= get_text_align_fill_size (target_address
, align_power
,
8299 target_size
, FALSE
, FALSE
);
8301 *max_diff
= xtensa_fetch_width
8302 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
8303 - target_size
+ opt_diff
;
8304 assert (*max_diff
>= opt_diff
);
8315 /* md_relax_frag Hook and Helper Functions. */
8317 static long relax_frag_loop_align (fragS
*, long);
8318 static long relax_frag_for_align (fragS
*, long);
8319 static long relax_frag_immed
8320 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
8323 /* Return the number of bytes added to this fragment, given that the
8324 input has been stretched already by "stretch". */
8327 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
8329 xtensa_isa isa
= xtensa_default_isa
;
8330 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
8331 long new_stretch
= 0;
8335 static xtensa_insnbuf vbuf
= NULL
;
8336 int slot
, num_slots
;
8339 as_where (&file_name
, &line
);
8340 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8342 fragP
->tc_frag_data
.unreported_expansion
= 0;
8344 switch (fragP
->fr_subtype
)
8346 case RELAX_ALIGN_NEXT_OPCODE
:
8347 /* Always convert. */
8348 if (fragP
->tc_frag_data
.relax_seen
)
8349 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
8352 case RELAX_LOOP_END
:
8356 case RELAX_LOOP_END_ADD_NOP
:
8357 /* Add a NOP and switch to .fill 0. */
8358 new_stretch
= relax_frag_add_nop (fragP
);
8362 case RELAX_DESIRE_ALIGN
:
8363 /* Do nothing. The narrowing before this frag will either align
8368 case RELAX_LITERAL_FINAL
:
8371 case RELAX_LITERAL_NR
:
8373 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
8374 assert (unreported
== lit_size
);
8375 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
8376 fragP
->fr_var
-= lit_size
;
8377 fragP
->fr_fix
+= lit_size
;
8383 vbuf
= xtensa_insnbuf_alloc (isa
);
8385 xtensa_insnbuf_from_chars
8386 (isa
, vbuf
, (unsigned char *) fragP
->fr_opcode
, 0);
8387 fmt
= xtensa_format_decode (isa
, vbuf
);
8388 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8390 for (slot
= 0; slot
< num_slots
; slot
++)
8392 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
8395 if (fragP
->tc_frag_data
.relax_seen
)
8396 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8400 case RELAX_IMMED_STEP1
:
8401 case RELAX_IMMED_STEP2
:
8402 case RELAX_IMMED_STEP3
:
8403 /* Place the immediate. */
8404 new_stretch
+= relax_frag_immed
8405 (now_seg
, fragP
, stretch
,
8406 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8407 fmt
, slot
, stretched_p
, FALSE
);
8411 /* This is OK; see the note in xg_assemble_vliw_tokens. */
8417 case RELAX_LITERAL_POOL_BEGIN
:
8418 case RELAX_LITERAL_POOL_END
:
8419 case RELAX_MAYBE_UNREACHABLE
:
8420 case RELAX_MAYBE_DESIRE_ALIGN
:
8421 /* No relaxation required. */
8424 case RELAX_FILL_NOP
:
8425 case RELAX_UNREACHABLE
:
8426 if (fragP
->tc_frag_data
.relax_seen
)
8427 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8431 as_bad (_("bad relaxation state"));
8434 /* Tell gas we need another relaxation pass. */
8435 if (! fragP
->tc_frag_data
.relax_seen
)
8437 fragP
->tc_frag_data
.relax_seen
= TRUE
;
8441 new_logical_line (file_name
, line
);
8447 relax_frag_loop_align (fragS
*fragP
, long stretch
)
8449 addressT old_address
, old_next_address
, old_size
;
8450 addressT new_address
, new_next_address
, new_size
;
8453 /* All the frags with relax_frag_for_alignment prior to this one in the
8454 section have been done, hopefully eliminating the need for a NOP here.
8455 But, this will put it in if necessary. */
8457 /* Calculate the old address of this fragment and the next fragment. */
8458 old_address
= fragP
->fr_address
- stretch
;
8459 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
8460 fragP
->tc_frag_data
.text_expansion
[0]);
8461 old_size
= old_next_address
- old_address
;
8463 /* Calculate the new address of this fragment and the next fragment. */
8464 new_address
= fragP
->fr_address
;
8466 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
8467 new_size
= new_next_address
- new_address
;
8469 growth
= new_size
- old_size
;
8471 /* Fix up the text_expansion field and return the new growth. */
8472 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
8477 /* Add a NOP instruction. */
8480 relax_frag_add_nop (fragS
*fragP
)
8482 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
8483 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
8484 assemble_nop (length
, nop_buf
);
8485 fragP
->tc_frag_data
.is_insn
= TRUE
;
8487 if (fragP
->fr_var
< length
)
8489 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP
->fr_var
, length
);
8493 fragP
->fr_fix
+= length
;
8494 fragP
->fr_var
-= length
;
8499 static long future_alignment_required (fragS
*, long);
8502 relax_frag_for_align (fragS
*fragP
, long stretch
)
8504 /* Overview of the relaxation procedure for alignment:
8505 We can widen with NOPs or by widening instructions or by filling
8506 bytes after jump instructions. Find the opportune places and widen
8507 them if necessary. */
8512 assert (fragP
->fr_subtype
== RELAX_FILL_NOP
8513 || fragP
->fr_subtype
== RELAX_UNREACHABLE
8514 || (fragP
->fr_subtype
== RELAX_SLOTS
8515 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
8517 stretch_me
= future_alignment_required (fragP
, stretch
);
8518 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
8524 /* We expanded on a previous pass. Can we shrink now? */
8525 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
8526 if (shrink
<= stretch
&& stretch
> 0)
8528 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8534 /* Below here, diff > 0. */
8535 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8541 /* Return the address of the next frag that should be aligned.
8543 By "address" we mean the address it _would_ be at if there
8544 is no action taken to align it between here and the target frag.
8545 In other words, if no narrows and no fill nops are used between
8546 here and the frag to align, _even_if_ some of the frags we use
8547 to align targets have already expanded on a previous relaxation
8550 Also, count each frag that may be used to help align the target.
8552 Return 0 if there are no frags left in the chain that need to be
8556 find_address_of_next_align_frag (fragS
**fragPP
,
8560 bfd_boolean
*paddable
)
8562 fragS
*fragP
= *fragPP
;
8563 addressT address
= fragP
->fr_address
;
8565 /* Do not reset the counts to 0. */
8569 /* Limit this to a small search. */
8570 if (*widens
>= (int) xtensa_fetch_width
)
8575 address
+= fragP
->fr_fix
;
8577 if (fragP
->fr_type
== rs_fill
)
8578 address
+= fragP
->fr_offset
* fragP
->fr_var
;
8579 else if (fragP
->fr_type
== rs_machine_dependent
)
8581 switch (fragP
->fr_subtype
)
8583 case RELAX_UNREACHABLE
:
8587 case RELAX_FILL_NOP
:
8589 if (!fragP
->tc_frag_data
.is_no_density
)
8594 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8599 address
+= total_frag_text_expansion (fragP
);;
8603 address
+= fragP
->tc_frag_data
.text_expansion
[0];
8606 case RELAX_ALIGN_NEXT_OPCODE
:
8607 case RELAX_DESIRE_ALIGN
:
8611 case RELAX_MAYBE_UNREACHABLE
:
8612 case RELAX_MAYBE_DESIRE_ALIGN
:
8617 /* Just punt if we don't know the type. */
8624 /* Just punt if we don't know the type. */
8628 fragP
= fragP
->fr_next
;
8636 static long bytes_to_stretch (fragS
*, int, int, int, int);
8639 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
8641 fragS
*this_frag
= fragP
;
8645 int narrow_nops
= 0;
8646 bfd_boolean paddable
= FALSE
;
8647 offsetT local_opt_diff
;
8650 int stretch_amount
= 0;
8651 int local_stretch_amount
;
8652 int global_stretch_amount
;
8654 address
= find_address_of_next_align_frag
8655 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
8659 if (this_frag
->tc_frag_data
.is_aligning_branch
)
8660 this_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
8662 frag_wane (this_frag
);
8666 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
8667 opt_diff
= local_opt_diff
;
8668 assert (opt_diff
>= 0);
8669 assert (max_diff
>= opt_diff
);
8674 fragP
= fragP
->fr_next
;
8676 while (fragP
&& opt_diff
< max_diff
&& address
)
8678 /* We only use these to determine if we can exit early
8679 because there will be plenty of ways to align future
8681 int glob_widens
= 0;
8684 bfd_boolean glob_pad
= 0;
8685 address
= find_address_of_next_align_frag
8686 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
8687 /* If there is a padable portion, then skip. */
8688 if (glob_pad
|| glob_widens
>= (1 << branch_align_power (now_seg
)))
8693 offsetT next_m_diff
;
8694 offsetT next_o_diff
;
8696 /* Downrange frags haven't had stretch added to them yet. */
8699 /* The address also includes any text expansion from this
8700 frag in a previous pass, but we don't want that. */
8701 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
8703 /* Assume we are going to move at least opt_diff. In
8704 reality, we might not be able to, but assuming that
8705 we will helps catch cases where moving opt_diff pushes
8706 the next target from aligned to unaligned. */
8707 address
+= opt_diff
;
8709 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
8711 /* Now cleanup for the adjustments to address. */
8712 next_o_diff
+= opt_diff
;
8713 next_m_diff
+= opt_diff
;
8714 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
8715 opt_diff
= next_o_diff
;
8716 if (next_m_diff
< max_diff
)
8717 max_diff
= next_m_diff
;
8718 fragP
= fragP
->fr_next
;
8722 /* If there are enough wideners in between, do it. */
8725 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
8727 assert (opt_diff
<= UNREACHABLE_MAX_WIDTH
);
8732 local_stretch_amount
8733 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8734 num_widens
, local_opt_diff
);
8735 global_stretch_amount
8736 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8737 num_widens
, opt_diff
);
8738 /* If the condition below is true, then the frag couldn't
8739 stretch the correct amount for the global case, so we just
8740 optimize locally. We'll rely on the subsequent frags to get
8741 the correct alignment in the global case. */
8742 if (global_stretch_amount
< local_stretch_amount
)
8743 stretch_amount
= local_stretch_amount
;
8745 stretch_amount
= global_stretch_amount
;
8747 if (this_frag
->fr_subtype
== RELAX_SLOTS
8748 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8749 assert (stretch_amount
<= 1);
8750 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8752 if (this_frag
->tc_frag_data
.is_no_density
)
8753 assert (stretch_amount
== 3 || stretch_amount
== 0);
8755 assert (stretch_amount
<= 3);
8758 return stretch_amount
;
8762 /* The idea: widen everything you can to get a target or loop aligned,
8763 then start using NOPs.
8765 When we must have a NOP, here is a table of how we decide
8766 (so you don't have to fight through the control flow below):
8768 wide_nops = the number of wide NOPs available for aligning
8769 narrow_nops = the number of narrow NOPs available for aligning
8770 (a subset of wide_nops)
8771 widens = the number of narrow instructions that should be widened
8778 b 0 1 1 (case 3a makes this case unnecessary)
8781 c 0 1 2 (case 4a makes this case unnecessary)
8784 c 0 2 1 (case 5b makes this case unnecessary)
8787 c 0 1 4 (case 6b makes this case unnecessary)
8788 d 1 1 1 (case 6a makes this case unnecessary)
8789 e 0 2 2 (case 6a makes this case unnecessary)
8790 f 0 3 0 (case 6a makes this case unnecessary)
8793 c 1 1 2 (case 7b makes this case unnecessary)
8794 d 0 1 5 (case 7a makes this case unnecessary)
8795 e 0 2 3 (case 7b makes this case unnecessary)
8796 f 0 3 1 (case 7b makes this case unnecessary)
8797 g 1 2 1 (case 7b makes this case unnecessary)
8801 bytes_to_stretch (fragS
*this_frag
,
8807 int bytes_short
= desired_diff
- num_widens
;
8809 assert (desired_diff
>= 0 && desired_diff
< 8);
8810 if (desired_diff
== 0)
8813 assert (wide_nops
> 0 || num_widens
> 0);
8815 /* Always prefer widening to NOP-filling. */
8816 if (bytes_short
< 0)
8818 /* There are enough RELAX_NARROW frags after this one
8819 to align the target without widening this frag in any way. */
8823 if (bytes_short
== 0)
8825 /* Widen every narrow between here and the align target
8826 and the align target will be properly aligned. */
8827 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8833 /* From here we will need at least one NOP to get an alignment.
8834 However, we may not be able to align at all, in which case,
8836 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8838 switch (desired_diff
)
8843 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 1)
8844 return 2; /* case 2 */
8850 return 3; /* case 3a */
8852 if (num_widens
>= 1 && wide_nops
== 1)
8853 return 3; /* case 4a */
8854 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 2)
8855 return 2; /* case 4b */
8858 if (num_widens
>= 2 && wide_nops
== 1)
8859 return 3; /* case 5a */
8860 /* We will need two nops. Are there enough nops
8861 between here and the align target? */
8862 if (wide_nops
< 2 || narrow_nops
== 0)
8864 /* Are there other nops closer that can serve instead? */
8865 if (wide_nops
> 2 && narrow_nops
> 1)
8867 /* Take the density one first, because there might not be
8868 another density one available. */
8869 if (!this_frag
->tc_frag_data
.is_no_density
)
8870 return 2; /* case 5b narrow */
8872 return 3; /* case 5b wide */
8876 return 3; /* case 6a */
8877 else if (num_widens
>= 3 && wide_nops
== 1)
8878 return 3; /* case 6b */
8881 if (wide_nops
== 1 && num_widens
>= 4)
8882 return 3; /* case 7a */
8883 else if (wide_nops
== 2 && num_widens
>= 1)
8884 return 3; /* case 7b */
8892 /* We will need a NOP no matter what, but should we widen
8893 this instruction to help?
8895 This is a RELAX_NARROW frag. */
8896 switch (desired_diff
)
8905 if (wide_nops
>= 1 && num_widens
== 1)
8906 return 1; /* case 4a */
8909 if (wide_nops
>= 1 && num_widens
== 2)
8910 return 1; /* case 5a */
8914 return 0; /* case 6a */
8915 else if (wide_nops
>= 1 && num_widens
== 3)
8916 return 1; /* case 6b */
8919 if (wide_nops
>= 1 && num_widens
== 4)
8920 return 1; /* case 7a */
8921 else if (wide_nops
>= 2 && num_widens
== 1)
8922 return 1; /* case 7b */
8935 relax_frag_immed (segT segP
,
8942 bfd_boolean estimate_only
)
8946 bfd_boolean negatable_branch
= FALSE
;
8947 bfd_boolean branch_jmp_to_next
= FALSE
;
8948 bfd_boolean wide_insn
= FALSE
;
8949 xtensa_isa isa
= xtensa_default_isa
;
8951 offsetT frag_offset
;
8954 int num_text_bytes
, num_literal_bytes
;
8955 int literal_diff
, total_text_diff
, this_text_diff
, first
;
8957 assert (fragP
->fr_opcode
!= NULL
);
8959 xg_clear_vinsn (&cur_vinsn
);
8960 vinsn_from_chars (&cur_vinsn
, fragP
->fr_opcode
);
8961 if (cur_vinsn
.num_slots
> 1)
8964 tinsn
= cur_vinsn
.slots
[slot
];
8965 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
8967 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
) == 1)
8970 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
8971 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
8973 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
8975 old_size
= xtensa_format_length (isa
, fmt
);
8977 /* Special case: replace a branch to the next instruction with a NOP.
8978 This is required to work around a hardware bug in T1040.0 and also
8979 serves as an optimization. */
8981 if (branch_jmp_to_next
8982 && ((old_size
== 2) || (old_size
== 3))
8983 && !next_frag_is_loop_target (fragP
))
8986 /* Here is the fun stuff: Get the immediate field from this
8987 instruction. If it fits, we are done. If not, find the next
8988 instruction sequence that fits. */
8990 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
8991 istack_init (&istack
);
8992 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
8993 min_steps
, stretch
);
8994 if (num_steps
< min_steps
)
8996 as_fatal (_("internal error: relaxation failed"));
9000 if (num_steps
> RELAX_IMMED_MAXSTEPS
)
9002 as_fatal (_("internal error: relaxation requires too many steps"));
9006 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
9008 /* Figure out the number of bytes needed. */
9010 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
9012 num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
9014 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
9016 num_text_bytes
= get_num_stack_text_bytes (&istack
);
9019 num_text_bytes
+= old_size
;
9020 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
9021 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
9023 total_text_diff
= num_text_bytes
- old_size
;
9024 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
9026 /* It MUST get larger. If not, we could get an infinite loop. */
9027 assert (num_text_bytes
>= 0);
9028 assert (literal_diff
>= 0);
9029 assert (total_text_diff
>= 0);
9031 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
9032 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
9033 assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
9034 assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
9036 /* Find the associated expandable literal for this. */
9037 if (literal_diff
!= 0)
9039 lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
9042 assert (literal_diff
== 4);
9043 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
9045 /* We expect that the literal section state has NOT been
9047 assert (lit_fragP
->fr_type
== rs_machine_dependent
9048 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
9049 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
9051 /* We need to mark this section for another iteration
9057 if (negatable_branch
&& istack
.ninsn
> 1)
9058 update_next_frag_state (fragP
);
9060 return this_text_diff
;
9064 /* md_convert_frag Hook and Helper Functions. */
9066 static void convert_frag_align_next_opcode (fragS
*);
9067 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
9068 static void convert_frag_fill_nop (fragS
*);
9069 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
9072 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
9074 static xtensa_insnbuf vbuf
= NULL
;
9075 xtensa_isa isa
= xtensa_default_isa
;
9082 as_where (&file_name
, &line
);
9083 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
9085 switch (fragp
->fr_subtype
)
9087 case RELAX_ALIGN_NEXT_OPCODE
:
9088 /* Always convert. */
9089 convert_frag_align_next_opcode (fragp
);
9092 case RELAX_DESIRE_ALIGN
:
9093 /* Do nothing. If not aligned already, too bad. */
9097 case RELAX_LITERAL_FINAL
:
9102 vbuf
= xtensa_insnbuf_alloc (isa
);
9104 xtensa_insnbuf_from_chars
9105 (isa
, vbuf
, (unsigned char *) fragp
->fr_opcode
, 0);
9106 fmt
= xtensa_format_decode (isa
, vbuf
);
9107 num_slots
= xtensa_format_num_slots (isa
, fmt
);
9109 for (slot
= 0; slot
< num_slots
; slot
++)
9111 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
9114 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
9118 case RELAX_IMMED_STEP1
:
9119 case RELAX_IMMED_STEP2
:
9120 case RELAX_IMMED_STEP3
:
9121 /* Place the immediate. */
9124 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
9129 /* This is OK because some slots could have
9130 relaxations and others have none. */
9136 case RELAX_UNREACHABLE
:
9137 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
9138 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
9139 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
9143 case RELAX_MAYBE_UNREACHABLE
:
9144 case RELAX_MAYBE_DESIRE_ALIGN
:
9148 case RELAX_FILL_NOP
:
9149 convert_frag_fill_nop (fragp
);
9152 case RELAX_LITERAL_NR
:
9153 if (use_literal_section
)
9155 /* This should have been handled during relaxation. When
9156 relaxing a code segment, literals sometimes need to be
9157 added to the corresponding literal segment. If that
9158 literal segment has already been relaxed, then we end up
9159 in this situation. Marking the literal segments as data
9160 would make this happen less often (since GAS always relaxes
9161 code before data), but we could still get into trouble if
9162 there are instructions in a segment that is not marked as
9163 containing code. Until we can implement a better solution,
9164 cheat and adjust the addresses of all the following frags.
9165 This could break subsequent alignments, but the linker's
9166 literal coalescing will do that anyway. */
9169 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
9170 assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
9171 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
9174 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
9178 as_bad (_("invalid relaxation fragment result"));
9183 new_logical_line (file_name
, line
);
9188 convert_frag_align_next_opcode (fragS
*fragp
)
9190 char *nop_buf
; /* Location for Writing. */
9191 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
9192 addressT aligned_address
;
9196 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
9198 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
9199 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
9200 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
9202 for (nop
= 0; nop
< nop_count
; nop
++)
9205 nop_size
= get_text_align_nth_nop_size (fill_size
, nop
, use_no_density
);
9207 assemble_nop (nop_size
, nop_buf
);
9208 nop_buf
+= nop_size
;
9211 fragp
->fr_fix
+= fill_size
;
9212 fragp
->fr_var
-= fill_size
;
9217 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
9219 TInsn tinsn
, single_target
;
9220 int size
, old_size
, diff
;
9221 offsetT frag_offset
;
9224 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
9226 if (fragP
->tc_frag_data
.is_aligning_branch
== 1)
9228 assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
9229 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
9230 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
9235 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
9237 /* No conversion. */
9242 assert (fragP
->fr_opcode
!= NULL
);
9244 /* Frags in this relaxation state should only contain
9245 single instruction bundles. */
9246 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
9248 /* Just convert it to a wide form.... */
9250 old_size
= xg_get_single_size (tinsn
.opcode
);
9252 tinsn_init (&single_target
);
9253 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9255 if (! xg_is_single_relaxable_insn (&tinsn
, &single_target
, FALSE
))
9257 as_bad (_("unable to widen instruction"));
9261 size
= xg_get_single_size (single_target
.opcode
);
9262 xg_emit_insn_to_buf (&single_target
, fragP
->fr_opcode
, fragP
,
9265 diff
= size
- old_size
;
9267 assert (diff
<= fragP
->fr_var
);
9268 fragP
->fr_var
-= diff
;
9269 fragP
->fr_fix
+= diff
;
9277 convert_frag_fill_nop (fragS
*fragP
)
9279 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
9280 int size
= fragP
->tc_frag_data
.text_expansion
[0];
9281 assert ((unsigned) size
== (fragP
->fr_next
->fr_address
9282 - fragP
->fr_address
- fragP
->fr_fix
));
9285 /* No conversion. */
9289 assemble_nop (size
, loc
);
9290 fragP
->tc_frag_data
.is_insn
= TRUE
;
9291 fragP
->fr_var
-= size
;
9292 fragP
->fr_fix
+= size
;
9297 static fixS
*fix_new_exp_in_seg
9298 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
9299 bfd_reloc_code_real_type
);
9300 static void convert_frag_immed_finish_loop (segT
, fragS
*, TInsn
*);
9303 convert_frag_immed (segT segP
,
9309 char *immed_instr
= fragP
->fr_opcode
;
9311 bfd_boolean expanded
= FALSE
;
9312 bfd_boolean branch_jmp_to_next
= FALSE
;
9313 char *fr_opcode
= fragP
->fr_opcode
;
9314 xtensa_isa isa
= xtensa_default_isa
;
9315 bfd_boolean wide_insn
= FALSE
;
9317 bfd_boolean is_loop
;
9319 assert (fr_opcode
!= NULL
);
9321 xg_clear_vinsn (&cur_vinsn
);
9323 vinsn_from_chars (&cur_vinsn
, fr_opcode
);
9324 if (cur_vinsn
.num_slots
> 1)
9327 orig_tinsn
= cur_vinsn
.slots
[slot
];
9328 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
9330 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
9332 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9333 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
9335 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
9337 /* Conversion just inserts a NOP and marks the fix as completed. */
9338 bytes
= xtensa_format_length (isa
, fmt
);
9341 cur_vinsn
.slots
[slot
].opcode
=
9342 xtensa_format_slot_nop_opcode (isa
, cur_vinsn
.format
, slot
);
9343 cur_vinsn
.slots
[slot
].ntok
= 0;
9347 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
9348 assert (bytes
== 2 || bytes
== 3);
9349 build_nop (&cur_vinsn
.slots
[0], bytes
);
9350 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
9352 vinsn_to_insnbuf (&cur_vinsn
, fr_opcode
, frag_now
, TRUE
);
9353 xtensa_insnbuf_to_chars
9354 (isa
, cur_vinsn
.insnbuf
, (unsigned char *) fr_opcode
, 0);
9359 /* Here is the fun stuff: Get the immediate field from this
9360 instruction. If it fits, we're done. If not, find the next
9361 instruction sequence that fits. */
9365 symbolS
*lit_sym
= NULL
;
9367 int target_offset
= 0;
9370 symbolS
*gen_label
= NULL
;
9371 offsetT frag_offset
;
9372 bfd_boolean first
= TRUE
;
9373 bfd_boolean last_is_jump
;
9375 /* It does not fit. Find something that does and
9376 convert immediately. */
9377 frag_offset
= fr_opcode
- fragP
->fr_literal
;
9378 istack_init (&istack
);
9379 xg_assembly_relax (&istack
, &orig_tinsn
,
9380 segP
, fragP
, frag_offset
, min_steps
, 0);
9382 old_size
= xtensa_format_length (isa
, fmt
);
9384 /* Assemble this right inline. */
9386 /* First, create the mapping from a label name to the REAL label. */
9388 for (i
= 0; i
< istack
.ninsn
; i
++)
9390 TInsn
*tinsn
= &istack
.insn
[i
];
9393 switch (tinsn
->insn_type
)
9396 if (lit_sym
!= NULL
)
9397 as_bad (_("multiple literals in expansion"));
9398 /* First find the appropriate space in the literal pool. */
9399 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9400 if (lit_frag
== NULL
)
9401 as_bad (_("no registered fragment for literal"));
9402 if (tinsn
->ntok
!= 1)
9403 as_bad (_("number of literal tokens != 1"));
9405 /* Set the literal symbol and add a fixup. */
9406 lit_sym
= lit_frag
->fr_symbol
;
9410 if (align_targets
&& !is_loop
)
9412 fragS
*unreach
= fragP
->fr_next
;
9413 while (!(unreach
->fr_type
== rs_machine_dependent
9414 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9415 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
9417 unreach
= unreach
->fr_next
;
9420 assert (unreach
->fr_type
== rs_machine_dependent
9421 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9422 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
9424 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
9426 assert (gen_label
== NULL
);
9427 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
9428 fr_opcode
- fragP
->fr_literal
9429 + target_offset
, fragP
);
9433 if (first
&& wide_insn
)
9435 target_offset
+= xtensa_format_length (isa
, fmt
);
9437 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9438 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9441 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9448 last_is_jump
= FALSE
;
9449 for (i
= 0; i
< istack
.ninsn
; i
++)
9451 TInsn
*tinsn
= &istack
.insn
[i
];
9455 bfd_reloc_code_real_type reloc_type
;
9457 switch (tinsn
->insn_type
)
9460 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9461 /* Already checked. */
9462 assert (lit_frag
!= NULL
);
9463 assert (lit_sym
!= NULL
);
9464 assert (tinsn
->ntok
== 1);
9466 target_seg
= S_GET_SEGMENT (lit_sym
);
9467 assert (target_seg
);
9468 reloc_type
= map_operator_to_reloc (tinsn
->tok
[0].X_op
);
9469 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
9470 &tinsn
->tok
[0], FALSE
, reloc_type
);
9477 xg_resolve_labels (tinsn
, gen_label
);
9478 xg_resolve_literals (tinsn
, lit_sym
);
9479 if (wide_insn
&& first
)
9482 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9484 cur_vinsn
.slots
[slot
] = *tinsn
;
9488 cur_vinsn
.slots
[slot
].opcode
=
9489 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
9490 cur_vinsn
.slots
[slot
].ntok
= 0;
9492 vinsn_to_insnbuf (&cur_vinsn
, immed_instr
, fragP
, TRUE
);
9493 xtensa_insnbuf_to_chars (isa
, cur_vinsn
.insnbuf
,
9494 (unsigned char *) immed_instr
, 0);
9495 fragP
->tc_frag_data
.is_insn
= TRUE
;
9496 size
= xtensa_format_length (isa
, fmt
);
9497 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9500 (tinsn
, immed_instr
+ size
, fragP
,
9501 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
9502 size
+= xg_get_single_size (tinsn
->opcode
);
9507 size
= xg_get_single_size (tinsn
->opcode
);
9508 xg_emit_insn_to_buf (tinsn
, immed_instr
, fragP
,
9509 immed_instr
- fragP
->fr_literal
, TRUE
);
9511 immed_instr
+= size
;
9517 diff
= total_size
- old_size
;
9521 assert (diff
<= fragP
->fr_var
);
9522 fragP
->fr_var
-= diff
;
9523 fragP
->fr_fix
+= diff
;
9526 /* Check for undefined immediates in LOOP instructions. */
9530 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
9531 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9533 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9536 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
9537 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9539 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9544 if (expanded
&& xtensa_opcode_is_loop (isa
, orig_tinsn
.opcode
) == 1)
9545 convert_frag_immed_finish_loop (segP
, fragP
, &orig_tinsn
);
9547 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
9549 /* Add an expansion note on the expanded instruction. */
9550 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
9551 &orig_tinsn
.tok
[0], TRUE
,
9552 BFD_RELOC_XTENSA_ASM_EXPAND
);
9557 /* Add a new fix expression into the desired segment. We have to
9558 switch to that segment to do this. */
9561 fix_new_exp_in_seg (segT new_seg
,
9568 bfd_reloc_code_real_type r_type
)
9572 subsegT subseg
= now_subseg
;
9574 assert (new_seg
!= 0);
9575 subseg_set (new_seg
, new_subseg
);
9577 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
9578 subseg_set (seg
, subseg
);
9583 /* Relax a loop instruction so that it can span loop >256 bytes.
9589 addi as, as, lo8 (label-.L1)
9590 addmi as, as, mid8 (label-.L1)
9601 convert_frag_immed_finish_loop (segT segP
, fragS
*fragP
, TInsn
*tinsn
)
9606 unsigned long target
;
9607 static xtensa_insnbuf insnbuf
= NULL
;
9608 unsigned int loop_length
, loop_length_hi
, loop_length_lo
;
9609 xtensa_isa isa
= xtensa_default_isa
;
9610 addressT loop_offset
;
9611 addressT addi_offset
= 9;
9612 addressT addmi_offset
= 12;
9617 insnbuf
= xtensa_insnbuf_alloc (isa
);
9619 /* Get the loop offset. */
9620 loop_offset
= get_expanded_loop_offset (tinsn
->opcode
);
9622 /* Validate that there really is a LOOP at the loop_offset. Because
9623 loops are not bundleable, we can assume that the instruction will be
9625 tinsn_from_chars (&loop_insn
, fragP
->fr_opcode
+ loop_offset
, 0);
9626 tinsn_immed_from_frag (&loop_insn
, fragP
, 0);
9628 assert (xtensa_opcode_is_loop (isa
, loop_insn
.opcode
) == 1);
9629 addi_offset
+= loop_offset
;
9630 addmi_offset
+= loop_offset
;
9632 assert (tinsn
->ntok
== 2);
9633 if (tinsn
->tok
[1].X_op
== O_constant
)
9634 target
= tinsn
->tok
[1].X_add_number
;
9635 else if (tinsn
->tok
[1].X_op
== O_symbol
)
9637 /* Find the fragment. */
9638 symbolS
*sym
= tinsn
->tok
[1].X_add_symbol
;
9639 assert (S_GET_SEGMENT (sym
) == segP
9640 || S_GET_SEGMENT (sym
) == absolute_section
);
9641 target
= (S_GET_VALUE (sym
) + tinsn
->tok
[1].X_add_number
);
9645 as_bad (_("invalid expression evaluation type %d"), tinsn
->tok
[1].X_op
);
9649 loop_length
= target
- (fragP
->fr_address
+ fragP
->fr_fix
);
9650 loop_length_hi
= loop_length
& ~0x0ff;
9651 loop_length_lo
= loop_length
& 0x0ff;
9652 if (loop_length_lo
>= 128)
9654 loop_length_lo
-= 256;
9655 loop_length_hi
+= 256;
9658 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
9659 32512. If the loop is larger than that, then we just fail. */
9660 if (loop_length_hi
> 32512)
9661 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9662 _("loop too long for LOOP instruction"));
9664 tinsn_from_chars (&addi_insn
, fragP
->fr_opcode
+ addi_offset
, 0);
9665 assert (addi_insn
.opcode
== xtensa_addi_opcode
);
9667 tinsn_from_chars (&addmi_insn
, fragP
->fr_opcode
+ addmi_offset
, 0);
9668 assert (addmi_insn
.opcode
== xtensa_addmi_opcode
);
9670 set_expr_const (&addi_insn
.tok
[2], loop_length_lo
);
9671 tinsn_to_insnbuf (&addi_insn
, insnbuf
);
9673 fragP
->tc_frag_data
.is_insn
= TRUE
;
9674 xtensa_insnbuf_to_chars
9675 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addi_offset
, 0);
9677 set_expr_const (&addmi_insn
.tok
[2], loop_length_hi
);
9678 tinsn_to_insnbuf (&addmi_insn
, insnbuf
);
9679 xtensa_insnbuf_to_chars
9680 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addmi_offset
, 0);
9682 /* Walk through all of the frags from here to the loop end
9683 and mark them as no_transform to keep them from being modified
9684 by the linker. If we ever have a relocation for the
9685 addi/addmi of the difference of two symbols we can remove this. */
9688 for (next_fragP
= fragP
; next_fragP
!= NULL
;
9689 next_fragP
= next_fragP
->fr_next
)
9691 next_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
9692 if (next_fragP
->tc_frag_data
.is_loop_target
)
9694 if (target_count
== 2)
9700 /* A map that keeps information on a per-subsegment basis. This is
9701 maintained during initial assembly, but is invalid once the
9702 subsegments are smashed together. I.E., it cannot be used during
9705 typedef struct subseg_map_struct
9713 float total_freq
; /* fall-through + branch target frequency */
9714 float target_freq
; /* branch target frequency alone */
9716 struct subseg_map_struct
*next
;
9720 static subseg_map
*sseg_map
= NULL
;
9723 get_subseg_info (segT seg
, subsegT subseg
)
9725 subseg_map
*subseg_e
;
9727 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
9729 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
9737 add_subseg_info (segT seg
, subsegT subseg
)
9739 subseg_map
*subseg_e
= (subseg_map
*) xmalloc (sizeof (subseg_map
));
9740 memset (subseg_e
, 0, sizeof (subseg_map
));
9741 subseg_e
->seg
= seg
;
9742 subseg_e
->subseg
= subseg
;
9743 subseg_e
->flags
= 0;
9744 /* Start off considering every branch target very important. */
9745 subseg_e
->target_freq
= 1.0;
9746 subseg_e
->total_freq
= 1.0;
9747 subseg_e
->next
= sseg_map
;
9748 sseg_map
= subseg_e
;
9754 get_last_insn_flags (segT seg
, subsegT subseg
)
9756 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9758 return subseg_e
->flags
;
9764 set_last_insn_flags (segT seg
,
9769 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9771 subseg_e
= add_subseg_info (seg
, subseg
);
9773 subseg_e
->flags
|= fl
;
9775 subseg_e
->flags
&= ~fl
;
9780 get_subseg_total_freq (segT seg
, subsegT subseg
)
9782 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9784 return subseg_e
->total_freq
;
9790 get_subseg_target_freq (segT seg
, subsegT subseg
)
9792 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9794 return subseg_e
->target_freq
;
9800 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
9802 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9804 subseg_e
= add_subseg_info (seg
, subseg
);
9805 subseg_e
->total_freq
= total_f
;
9806 subseg_e
->target_freq
= target_f
;
9810 /* Segment Lists and emit_state Stuff. */
9813 xtensa_move_seg_list_to_beginning (seg_list
*head
)
9818 segT literal_section
= head
->seg
;
9820 /* Move the literal section to the front of the section list. */
9821 assert (literal_section
);
9822 if (literal_section
!= stdoutput
->sections
)
9824 bfd_section_list_remove (stdoutput
, literal_section
);
9825 bfd_section_list_prepend (stdoutput
, literal_section
);
9832 static void mark_literal_frags (seg_list
*);
9835 xtensa_move_literals (void)
9838 frchainS
*frchain_from
, *frchain_to
;
9839 fragS
*search_frag
, *next_frag
, *last_frag
, *literal_pool
, *insert_after
;
9840 fragS
**frag_splice
;
9843 fixS
*fix
, *next_fix
, **fix_splice
;
9846 mark_literal_frags (literal_head
->next
);
9848 if (use_literal_section
)
9851 for (segment
= literal_head
->next
; segment
; segment
= segment
->next
)
9853 /* Keep the literals for .init and .fini in separate sections. */
9854 if (!strcmp (segment_name (segment
->seg
), INIT_SECTION_NAME
)
9855 || !strcmp (segment_name (segment
->seg
), FINI_SECTION_NAME
))
9858 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9859 search_frag
= frchain_from
->frch_root
;
9860 literal_pool
= NULL
;
9862 frag_splice
= &(frchain_from
->frch_root
);
9864 while (!search_frag
->tc_frag_data
.literal_frag
)
9866 assert (search_frag
->fr_fix
== 0
9867 || search_frag
->fr_type
== rs_align
);
9868 search_frag
= search_frag
->fr_next
;
9871 assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
9872 == RELAX_LITERAL_POOL_BEGIN
);
9873 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
9875 /* Make sure that all the frags in this series are closed, and
9876 that there is at least one left over of zero-size. This
9877 prevents us from making a segment with an frchain without any
9879 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9880 xtensa_set_frag_assembly_state (frag_now
);
9881 last_frag
= frag_now
;
9882 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9883 xtensa_set_frag_assembly_state (frag_now
);
9885 while (search_frag
!= frag_now
)
9887 next_frag
= search_frag
->fr_next
;
9889 /* First, move the frag out of the literal section and
9890 to the appropriate place. */
9891 if (search_frag
->tc_frag_data
.literal_frag
)
9893 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
9894 assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
9895 frchain_to
= literal_pool
->tc_frag_data
.lit_frchain
;
9896 assert (frchain_to
);
9898 insert_after
= literal_pool
->tc_frag_data
.literal_frag
;
9899 dest_seg
= insert_after
->fr_next
->tc_frag_data
.lit_seg
;
9901 *frag_splice
= next_frag
;
9902 search_frag
->fr_next
= insert_after
->fr_next
;
9903 insert_after
->fr_next
= search_frag
;
9904 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
9905 literal_pool
->tc_frag_data
.literal_frag
= search_frag
;
9907 /* Now move any fixups associated with this frag to the
9909 fix
= frchain_from
->fix_root
;
9910 fix_splice
= &(frchain_from
->fix_root
);
9913 next_fix
= fix
->fx_next
;
9914 if (fix
->fx_frag
== search_frag
)
9916 *fix_splice
= next_fix
;
9917 fix
->fx_next
= frchain_to
->fix_root
;
9918 frchain_to
->fix_root
= fix
;
9919 if (frchain_to
->fix_tail
== NULL
)
9920 frchain_to
->fix_tail
= fix
;
9923 fix_splice
= &(fix
->fx_next
);
9926 search_frag
= next_frag
;
9929 if (frchain_from
->fix_root
!= NULL
)
9931 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9932 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
9934 assert (frchain_from
->fix_root
== NULL
);
9936 frchain_from
->fix_tail
= NULL
;
9937 xtensa_restore_emit_state (&state
);
9940 /* Now fix up the SEGMENT value for all the literal symbols. */
9941 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
9943 symbolS
*lit_sym
= lit
->sym
;
9944 segT dest_seg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
9946 S_SET_SEGMENT (lit_sym
, dest_seg
);
9951 /* Walk over all the frags for segments in a list and mark them as
9952 containing literals. As clunky as this is, we can't rely on frag_var
9953 and frag_variant to get called in all situations. */
9956 mark_literal_frags (seg_list
*segment
)
9958 frchainS
*frchain_from
;
9963 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9964 search_frag
= frchain_from
->frch_root
;
9967 search_frag
->tc_frag_data
.is_literal
= TRUE
;
9968 search_frag
= search_frag
->fr_next
;
9970 segment
= segment
->next
;
9976 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
9978 /* Move all of the sections in the section list to come
9979 after "after" in the gnu segment list. */
9984 segT literal_section
= head
->seg
;
9986 /* Move the literal section after "after". */
9987 assert (literal_section
);
9988 if (literal_section
!= after
)
9990 bfd_section_list_remove (stdoutput
, literal_section
);
9991 bfd_section_list_insert_after (stdoutput
, after
, literal_section
);
9999 /* Push all the literal segments to the end of the gnu list. */
10002 xtensa_reorder_segments (void)
10009 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
10015 /* Now that we have the last section, push all the literal
10016 sections to the end. */
10017 xtensa_reorder_seg_list (literal_head
, last_sec
);
10019 /* Now perform the final error check. */
10020 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
10022 assert (new_count
== old_count
);
10026 /* Change the emit state (seg, subseg, and frag related stuff) to the
10027 correct location. Return a emit_state which can be passed to
10028 xtensa_restore_emit_state to return to current fragment. */
10031 xtensa_switch_to_literal_fragment (emit_state
*result
)
10033 if (directive_state
[directive_absolute_literals
])
10035 segT lit4_seg
= cache_literal_section (TRUE
);
10036 xtensa_switch_section_emit_state (result
, lit4_seg
, 0);
10039 xtensa_switch_to_non_abs_literal_fragment (result
);
10041 /* Do a 4-byte align here. */
10042 frag_align (2, 0, 0);
10043 record_alignment (now_seg
, 2);
10048 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
10050 static bfd_boolean recursive
= FALSE
;
10051 fragS
*pool_location
= get_literal_pool_location (now_seg
);
10053 bfd_boolean is_init
=
10054 (now_seg
&& !strcmp (segment_name (now_seg
), INIT_SECTION_NAME
));
10055 bfd_boolean is_fini
=
10056 (now_seg
&& !strcmp (segment_name (now_seg
), FINI_SECTION_NAME
));
10058 if (pool_location
== NULL
10059 && !use_literal_section
10061 && !is_init
&& ! is_fini
)
10063 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
10065 /* When we mark a literal pool location, we want to put a frag in
10066 the literal pool that points to it. But to do that, we want to
10067 switch_to_literal_fragment. But literal sections don't have
10068 literal pools, so their location is always null, so we would
10069 recurse forever. This is kind of hacky, but it works. */
10072 xtensa_mark_literal_pool_location ();
10076 lit_seg
= cache_literal_section (FALSE
);
10077 xtensa_switch_section_emit_state (result
, lit_seg
, 0);
10079 if (!use_literal_section
10080 && !is_init
&& !is_fini
10081 && get_literal_pool_location (now_seg
) != pool_location
)
10083 /* Close whatever frag is there. */
10084 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10085 xtensa_set_frag_assembly_state (frag_now
);
10086 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
10087 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10088 xtensa_set_frag_assembly_state (frag_now
);
10093 /* Call this function before emitting data into the literal section.
10094 This is a helper function for xtensa_switch_to_literal_fragment.
10095 This is similar to a .section new_now_seg subseg. */
10098 xtensa_switch_section_emit_state (emit_state
*state
,
10100 subsegT new_now_subseg
)
10102 state
->name
= now_seg
->name
;
10103 state
->now_seg
= now_seg
;
10104 state
->now_subseg
= now_subseg
;
10105 state
->generating_literals
= generating_literals
;
10106 generating_literals
++;
10107 subseg_set (new_now_seg
, new_now_subseg
);
10111 /* Use to restore the emitting into the normal place. */
10114 xtensa_restore_emit_state (emit_state
*state
)
10116 generating_literals
= state
->generating_literals
;
10117 subseg_set (state
->now_seg
, state
->now_subseg
);
10121 /* Predicate function used to look up a section in a particular group. */
10124 match_section_group (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
, void *inf
)
10126 const char *gname
= inf
;
10127 const char *group_name
= elf_group_name (sec
);
10129 return (group_name
== gname
10130 || (group_name
!= NULL
10132 && strcmp (group_name
, gname
) == 0));
10136 /* Get the literal section to be used for the current text section.
10137 The result may be cached in the default_lit_sections structure. */
10140 cache_literal_section (bfd_boolean use_abs_literals
)
10142 const char *text_name
, *group_name
= 0;
10143 char *base_name
, *name
, *suffix
;
10145 segT seg
, current_section
;
10146 int current_subsec
;
10147 bfd_boolean linkonce
= FALSE
;
10149 /* Save the current section/subsection. */
10150 current_section
= now_seg
;
10151 current_subsec
= now_subseg
;
10153 /* Clear the cached values if they are no longer valid. */
10154 if (now_seg
!= default_lit_sections
.current_text_seg
)
10156 default_lit_sections
.current_text_seg
= now_seg
;
10157 default_lit_sections
.lit_seg
= NULL
;
10158 default_lit_sections
.lit4_seg
= NULL
;
10161 /* Check if the literal section is already cached. */
10162 if (use_abs_literals
)
10163 pcached
= &default_lit_sections
.lit4_seg
;
10165 pcached
= &default_lit_sections
.lit_seg
;
10170 text_name
= default_lit_sections
.lit_prefix
;
10171 if (! text_name
|| ! *text_name
)
10173 text_name
= segment_name (current_section
);
10174 group_name
= elf_group_name (current_section
);
10175 linkonce
= (current_section
->flags
& SEC_LINK_ONCE
) != 0;
10178 base_name
= use_abs_literals
? ".lit4" : ".literal";
10181 name
= xmalloc (strlen (base_name
) + strlen (group_name
) + 2);
10182 sprintf (name
, "%s.%s", base_name
, group_name
);
10184 else if (strncmp (text_name
, ".gnu.linkonce.", linkonce_len
) == 0)
10186 suffix
= strchr (text_name
+ linkonce_len
, '.');
10188 name
= xmalloc (linkonce_len
+ strlen (base_name
) + 1
10189 + (suffix
? strlen (suffix
) : 0));
10190 strcpy (name
, ".gnu.linkonce");
10191 strcat (name
, base_name
);
10193 strcat (name
, suffix
);
10198 /* If the section name ends with ".text", then replace that suffix
10199 instead of appending an additional suffix. */
10200 size_t len
= strlen (text_name
);
10201 if (len
>= 5 && strcmp (text_name
+ len
- 5, ".text") == 0)
10204 name
= xmalloc (len
+ strlen (base_name
) + 1);
10205 strcpy (name
, text_name
);
10206 strcpy (name
+ len
, base_name
);
10209 /* Canonicalize section names to allow renaming literal sections.
10210 The group name, if any, came from the current text section and
10211 has already been canonicalized. */
10212 name
= tc_canonicalize_symbol_name (name
);
10214 seg
= bfd_get_section_by_name_if (stdoutput
, name
, match_section_group
,
10215 (void *) group_name
);
10220 seg
= subseg_force_new (name
, 0);
10222 if (! use_abs_literals
)
10224 /* Add the newly created literal segment to the list. */
10225 seg_list
*n
= (seg_list
*) xmalloc (sizeof (seg_list
));
10227 n
->next
= literal_head
->next
;
10228 literal_head
->next
= n
;
10231 flags
= (SEC_HAS_CONTENTS
| SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
10232 | (linkonce
? (SEC_LINK_ONCE
| SEC_LINK_DUPLICATES_DISCARD
) : 0)
10233 | (use_abs_literals
? SEC_DATA
: SEC_CODE
));
10235 elf_group_name (seg
) = group_name
;
10237 bfd_set_section_flags (stdoutput
, seg
, flags
);
10238 bfd_set_section_alignment (stdoutput
, seg
, 2);
10242 subseg_set (current_section
, current_subsec
);
10247 /* Property Tables Stuff. */
10249 #define XTENSA_INSN_SEC_NAME ".xt.insn"
10250 #define XTENSA_LIT_SEC_NAME ".xt.lit"
10251 #define XTENSA_PROP_SEC_NAME ".xt.prop"
10253 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
10254 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
10256 static bfd_boolean
get_frag_is_literal (const fragS
*);
10257 static void xtensa_create_property_segments
10258 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
10259 static void xtensa_create_xproperty_segments
10260 (frag_flags_fn
, const char *, xt_section_type
);
10261 static segment_info_type
*retrieve_segment_info (segT
);
10262 static bfd_boolean
section_has_property (segT
, frag_predicate
);
10263 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
10264 static void add_xt_block_frags
10265 (segT
, segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
10266 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
10267 static void xtensa_frag_flags_init (frag_flags
*);
10268 static void get_frag_property_flags (const fragS
*, frag_flags
*);
10269 static bfd_vma
frag_flags_to_number (const frag_flags
*);
10270 static void add_xt_prop_frags
10271 (segT
, segT
, xtensa_block_info
**, frag_flags_fn
);
10273 /* Set up property tables after relaxation. */
10276 xtensa_post_relax_hook (void)
10278 xtensa_move_seg_list_to_beginning (literal_head
);
10280 xtensa_find_unmarked_state_frags ();
10281 xtensa_mark_frags_for_org ();
10282 xtensa_mark_difference_of_two_symbols ();
10284 xtensa_create_property_segments (get_frag_is_literal
,
10286 XTENSA_LIT_SEC_NAME
,
10288 xtensa_create_xproperty_segments (get_frag_property_flags
,
10289 XTENSA_PROP_SEC_NAME
,
10292 if (warn_unaligned_branch_targets
)
10293 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
10294 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
10298 /* This function is only meaningful after xtensa_move_literals. */
10301 get_frag_is_literal (const fragS
*fragP
)
10303 assert (fragP
!= NULL
);
10304 return fragP
->tc_frag_data
.is_literal
;
10309 xtensa_create_property_segments (frag_predicate property_function
,
10310 frag_predicate end_property_function
,
10311 const char *section_name_base
,
10312 xt_section_type sec_type
)
10316 /* Walk over all of the current segments.
10317 Walk over each fragment
10318 For each non-empty fragment,
10319 Build a property record (append where possible). */
10321 for (seclist
= &stdoutput
->sections
;
10322 seclist
&& *seclist
;
10323 seclist
= &(*seclist
)->next
)
10325 segT sec
= *seclist
;
10328 flags
= bfd_get_section_flags (stdoutput
, sec
);
10329 if (flags
& SEC_DEBUGGING
)
10331 if (!(flags
& SEC_ALLOC
))
10334 if (section_has_property (sec
, property_function
))
10337 xtensa_get_property_section (sec
, section_name_base
);
10338 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10339 xtensa_block_info
**xt_blocks
=
10340 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10341 /* Walk over all of the frchains here and add new sections. */
10342 add_xt_block_frags (sec
, insn_sec
, xt_blocks
, property_function
,
10343 end_property_function
);
10347 /* Now we fill them out.... */
10349 for (seclist
= &stdoutput
->sections
;
10350 seclist
&& *seclist
;
10351 seclist
= &(*seclist
)->next
)
10353 segment_info_type
*seginfo
;
10354 xtensa_block_info
*block
;
10355 segT sec
= *seclist
;
10357 seginfo
= seg_info (sec
);
10358 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10362 xtensa_block_info
*cur_block
;
10363 /* This is a section with some data. */
10365 bfd_size_type rec_size
;
10367 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10370 rec_size
= num_recs
* 8;
10371 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10373 /* In order to make this work with the assembler, we have to
10374 build some frags and then build the "fixups" for it. It
10375 would be easier to just set the contents then set the
10380 /* Allocate a fragment and leak it. */
10382 bfd_size_type frag_size
;
10384 frchainS
*frchainP
;
10388 frag_size
= sizeof (fragS
) + rec_size
;
10389 fragP
= (fragS
*) xmalloc (frag_size
);
10391 memset (fragP
, 0, frag_size
);
10392 fragP
->fr_address
= 0;
10393 fragP
->fr_next
= NULL
;
10394 fragP
->fr_fix
= rec_size
;
10396 fragP
->fr_type
= rs_fill
;
10397 /* The rest are zeros. */
10399 frchainP
= seginfo
->frchainP
;
10400 frchainP
->frch_root
= fragP
;
10401 frchainP
->frch_last
= fragP
;
10403 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10404 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10406 seginfo
->fix_root
= fixes
;
10407 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10409 frag_data
= &fragP
->fr_literal
[0];
10410 for (i
= 0; i
< num_recs
; i
++)
10412 fixS
*fix
= &fixes
[i
];
10413 assert (cur_block
);
10415 /* Write the fixup. */
10416 if (i
!= num_recs
- 1)
10417 fix
->fx_next
= &fixes
[i
+ 1];
10419 fix
->fx_next
= NULL
;
10422 fix
->fx_frag
= fragP
;
10423 fix
->fx_where
= i
* 8;
10424 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10425 fix
->fx_offset
= cur_block
->offset
;
10426 fix
->fx_r_type
= BFD_RELOC_32
;
10427 fix
->fx_file
= "Internal Assembly";
10430 /* Write the length. */
10431 md_number_to_chars (&frag_data
[4 + 8 * i
],
10432 cur_block
->size
, 4);
10433 cur_block
= cur_block
->next
;
10442 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
10443 const char *section_name_base
,
10444 xt_section_type sec_type
)
10448 /* Walk over all of the current segments.
10449 Walk over each fragment.
10450 For each fragment that has instructions,
10451 build an instruction record (append where possible). */
10453 for (seclist
= &stdoutput
->sections
;
10454 seclist
&& *seclist
;
10455 seclist
= &(*seclist
)->next
)
10457 segT sec
= *seclist
;
10460 flags
= bfd_get_section_flags (stdoutput
, sec
);
10461 if ((flags
& SEC_DEBUGGING
)
10462 || !(flags
& SEC_ALLOC
)
10463 || (flags
& SEC_MERGE
))
10466 if (section_has_xproperty (sec
, flag_fn
))
10469 xtensa_get_property_section (sec
, section_name_base
);
10470 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10471 xtensa_block_info
**xt_blocks
=
10472 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10473 /* Walk over all of the frchains here and add new sections. */
10474 add_xt_prop_frags (sec
, insn_sec
, xt_blocks
, flag_fn
);
10478 /* Now we fill them out.... */
10480 for (seclist
= &stdoutput
->sections
;
10481 seclist
&& *seclist
;
10482 seclist
= &(*seclist
)->next
)
10484 segment_info_type
*seginfo
;
10485 xtensa_block_info
*block
;
10486 segT sec
= *seclist
;
10488 seginfo
= seg_info (sec
);
10489 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10493 xtensa_block_info
*cur_block
;
10494 /* This is a section with some data. */
10496 bfd_size_type rec_size
;
10498 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10501 rec_size
= num_recs
* (8 + 4);
10502 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10504 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
10506 /* In order to make this work with the assembler, we have to build
10507 some frags then build the "fixups" for it. It would be easier to
10508 just set the contents then set the arlents. */
10512 /* Allocate a fragment and (unfortunately) leak it. */
10514 bfd_size_type frag_size
;
10516 frchainS
*frchainP
;
10520 frag_size
= sizeof (fragS
) + rec_size
;
10521 fragP
= (fragS
*) xmalloc (frag_size
);
10523 memset (fragP
, 0, frag_size
);
10524 fragP
->fr_address
= 0;
10525 fragP
->fr_next
= NULL
;
10526 fragP
->fr_fix
= rec_size
;
10528 fragP
->fr_type
= rs_fill
;
10529 /* The rest are zeros. */
10531 frchainP
= seginfo
->frchainP
;
10532 frchainP
->frch_root
= fragP
;
10533 frchainP
->frch_last
= fragP
;
10535 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10536 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10538 seginfo
->fix_root
= fixes
;
10539 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10541 frag_data
= &fragP
->fr_literal
[0];
10542 for (i
= 0; i
< num_recs
; i
++)
10544 fixS
*fix
= &fixes
[i
];
10545 assert (cur_block
);
10547 /* Write the fixup. */
10548 if (i
!= num_recs
- 1)
10549 fix
->fx_next
= &fixes
[i
+ 1];
10551 fix
->fx_next
= NULL
;
10554 fix
->fx_frag
= fragP
;
10555 fix
->fx_where
= i
* (8 + 4);
10556 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10557 fix
->fx_offset
= cur_block
->offset
;
10558 fix
->fx_r_type
= BFD_RELOC_32
;
10559 fix
->fx_file
= "Internal Assembly";
10562 /* Write the length. */
10563 md_number_to_chars (&frag_data
[4 + (8+4) * i
],
10564 cur_block
->size
, 4);
10565 md_number_to_chars (&frag_data
[8 + (8+4) * i
],
10566 frag_flags_to_number (&cur_block
->flags
),
10568 cur_block
= cur_block
->next
;
10576 static segment_info_type
*
10577 retrieve_segment_info (segT seg
)
10579 segment_info_type
*seginfo
;
10580 seginfo
= (segment_info_type
*) bfd_get_section_userdata (stdoutput
, seg
);
10583 frchainS
*frchainP
;
10585 seginfo
= (segment_info_type
*) xmalloc (sizeof (*seginfo
));
10586 memset ((void *) seginfo
, 0, sizeof (*seginfo
));
10587 seginfo
->fix_root
= NULL
;
10588 seginfo
->fix_tail
= NULL
;
10589 seginfo
->bfd_section
= seg
;
10591 /* We will not be dealing with these, only our special ones. */
10592 bfd_set_section_userdata (stdoutput
, seg
, (void *) seginfo
);
10594 frchainP
= (frchainS
*) xmalloc (sizeof (frchainS
));
10595 frchainP
->frch_root
= NULL
;
10596 frchainP
->frch_last
= NULL
;
10597 frchainP
->frch_next
= NULL
;
10598 frchainP
->frch_subseg
= 0;
10599 frchainP
->fix_root
= NULL
;
10600 frchainP
->fix_tail
= NULL
;
10601 /* Do not init the objstack. */
10602 /* obstack_begin (&frchainP->frch_obstack, chunksize); */
10603 /* frchainP->frch_frag_now = fragP; */
10604 frchainP
->frch_frag_now
= NULL
;
10606 seginfo
->frchainP
= frchainP
;
10614 section_has_property (segT sec
, frag_predicate property_function
)
10616 segment_info_type
*seginfo
= seg_info (sec
);
10619 if (seginfo
&& seginfo
->frchainP
)
10621 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10623 if (property_function (fragP
)
10624 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10633 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
10635 segment_info_type
*seginfo
= seg_info (sec
);
10638 if (seginfo
&& seginfo
->frchainP
)
10640 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10642 frag_flags prop_flags
;
10643 property_function (fragP
, &prop_flags
);
10644 if (!xtensa_frag_flags_is_empty (&prop_flags
))
10652 /* Two types of block sections exist right now: literal and insns. */
10655 add_xt_block_frags (segT sec
,
10657 xtensa_block_info
**xt_block
,
10658 frag_predicate property_function
,
10659 frag_predicate end_property_function
)
10661 segment_info_type
*seg_info
;
10662 segment_info_type
*xt_seg_info
;
10663 bfd_vma seg_offset
;
10666 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
10667 seg_info
= retrieve_segment_info (sec
);
10669 /* Build it if needed. */
10670 while (*xt_block
!= NULL
)
10671 xt_block
= &(*xt_block
)->next
;
10672 /* We are either at NULL at the beginning or at the end. */
10674 /* Walk through the frags. */
10677 if (seg_info
->frchainP
)
10679 for (fragP
= seg_info
->frchainP
->frch_root
;
10681 fragP
= fragP
->fr_next
)
10683 if (property_function (fragP
)
10684 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10686 if (*xt_block
!= NULL
)
10688 if ((*xt_block
)->offset
+ (*xt_block
)->size
10689 == fragP
->fr_address
)
10690 (*xt_block
)->size
+= fragP
->fr_fix
;
10692 xt_block
= &((*xt_block
)->next
);
10694 if (*xt_block
== NULL
)
10696 xtensa_block_info
*new_block
= (xtensa_block_info
*)
10697 xmalloc (sizeof (xtensa_block_info
));
10698 new_block
->sec
= sec
;
10699 new_block
->offset
= fragP
->fr_address
;
10700 new_block
->size
= fragP
->fr_fix
;
10701 new_block
->next
= NULL
;
10702 xtensa_frag_flags_init (&new_block
->flags
);
10703 *xt_block
= new_block
;
10705 if (end_property_function
10706 && end_property_function (fragP
))
10708 xt_block
= &((*xt_block
)->next
);
10716 /* Break the encapsulation of add_xt_prop_frags here. */
10719 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
10721 if (prop_flags
->is_literal
10722 || prop_flags
->is_insn
10723 || prop_flags
->is_data
10724 || prop_flags
->is_unreachable
)
10731 xtensa_frag_flags_init (frag_flags
*prop_flags
)
10733 memset (prop_flags
, 0, sizeof (frag_flags
));
10738 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
10740 xtensa_frag_flags_init (prop_flags
);
10741 if (fragP
->tc_frag_data
.is_literal
)
10742 prop_flags
->is_literal
= TRUE
;
10743 if (fragP
->tc_frag_data
.is_specific_opcode
10744 || fragP
->tc_frag_data
.is_no_transform
)
10745 prop_flags
->is_no_transform
= TRUE
;
10746 if (fragP
->tc_frag_data
.is_unreachable
)
10747 prop_flags
->is_unreachable
= TRUE
;
10748 else if (fragP
->tc_frag_data
.is_insn
)
10750 prop_flags
->is_insn
= TRUE
;
10751 if (fragP
->tc_frag_data
.is_loop_target
)
10752 prop_flags
->insn
.is_loop_target
= TRUE
;
10753 if (fragP
->tc_frag_data
.is_branch_target
)
10754 prop_flags
->insn
.is_branch_target
= TRUE
;
10755 if (fragP
->tc_frag_data
.is_no_density
)
10756 prop_flags
->insn
.is_no_density
= TRUE
;
10757 if (fragP
->tc_frag_data
.use_absolute_literals
)
10758 prop_flags
->insn
.is_abslit
= TRUE
;
10760 if (fragP
->tc_frag_data
.is_align
)
10762 prop_flags
->is_align
= TRUE
;
10763 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
10764 if (xtensa_frag_flags_is_empty (prop_flags
))
10765 prop_flags
->is_data
= TRUE
;
10771 frag_flags_to_number (const frag_flags
*prop_flags
)
10774 if (prop_flags
->is_literal
)
10775 num
|= XTENSA_PROP_LITERAL
;
10776 if (prop_flags
->is_insn
)
10777 num
|= XTENSA_PROP_INSN
;
10778 if (prop_flags
->is_data
)
10779 num
|= XTENSA_PROP_DATA
;
10780 if (prop_flags
->is_unreachable
)
10781 num
|= XTENSA_PROP_UNREACHABLE
;
10782 if (prop_flags
->insn
.is_loop_target
)
10783 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
10784 if (prop_flags
->insn
.is_branch_target
)
10786 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
10787 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
10790 if (prop_flags
->insn
.is_no_density
)
10791 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
10792 if (prop_flags
->is_no_transform
)
10793 num
|= XTENSA_PROP_NO_TRANSFORM
;
10794 if (prop_flags
->insn
.is_no_reorder
)
10795 num
|= XTENSA_PROP_INSN_NO_REORDER
;
10796 if (prop_flags
->insn
.is_abslit
)
10797 num
|= XTENSA_PROP_INSN_ABSLIT
;
10799 if (prop_flags
->is_align
)
10801 num
|= XTENSA_PROP_ALIGN
;
10802 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
10810 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
10811 const frag_flags
*prop_flags_2
)
10813 /* Cannot combine with an end marker. */
10815 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
10817 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
10819 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
10822 if (prop_flags_1
->is_insn
)
10824 /* Properties of the beginning of the frag. */
10825 if (prop_flags_2
->insn
.is_loop_target
)
10827 if (prop_flags_2
->insn
.is_branch_target
)
10829 if (prop_flags_1
->insn
.is_no_density
!=
10830 prop_flags_2
->insn
.is_no_density
)
10832 if (prop_flags_1
->is_no_transform
!=
10833 prop_flags_2
->is_no_transform
)
10835 if (prop_flags_1
->insn
.is_no_reorder
!=
10836 prop_flags_2
->insn
.is_no_reorder
)
10838 if (prop_flags_1
->insn
.is_abslit
!=
10839 prop_flags_2
->insn
.is_abslit
)
10843 if (prop_flags_1
->is_align
)
10851 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
10854 unsigned align_bits
;
10856 if (!xt_block
->flags
.is_align
)
10857 return xt_block
->size
;
10859 end_addr
= xt_block
->offset
+ xt_block
->size
;
10860 align_bits
= xt_block
->flags
.alignment
;
10861 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
10862 return end_addr
- xt_block
->offset
;
10867 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
10868 const xtensa_block_info
*xt_block_2
)
10870 if (xt_block
->sec
!= xt_block_2
->sec
)
10872 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
10873 != xt_block_2
->offset
)
10876 if (xt_block_2
->size
== 0
10877 && (!xt_block_2
->flags
.is_unreachable
10878 || xt_block
->flags
.is_unreachable
))
10880 if (xt_block_2
->flags
.is_align
10881 && xt_block
->flags
.is_align
)
10883 /* Nothing needed. */
10884 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
10889 if (xt_block_2
->flags
.is_align
)
10891 /* Push alignment to previous entry. */
10892 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
10893 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10898 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
10899 &xt_block_2
->flags
))
10902 xt_block
->size
+= xt_block_2
->size
;
10904 if (xt_block_2
->flags
.is_align
)
10906 xt_block
->flags
.is_align
= TRUE
;
10907 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10915 add_xt_prop_frags (segT sec
,
10917 xtensa_block_info
**xt_block
,
10918 frag_flags_fn property_function
)
10920 segment_info_type
*seg_info
;
10921 segment_info_type
*xt_seg_info
;
10922 bfd_vma seg_offset
;
10925 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
10926 seg_info
= retrieve_segment_info (sec
);
10927 /* Build it if needed. */
10928 while (*xt_block
!= NULL
)
10930 xt_block
= &(*xt_block
)->next
;
10932 /* We are either at NULL at the beginning or at the end. */
10934 /* Walk through the frags. */
10937 if (seg_info
->frchainP
)
10939 for (fragP
= seg_info
->frchainP
->frch_root
; fragP
;
10940 fragP
= fragP
->fr_next
)
10942 xtensa_block_info tmp_block
;
10943 tmp_block
.sec
= sec
;
10944 tmp_block
.offset
= fragP
->fr_address
;
10945 tmp_block
.size
= fragP
->fr_fix
;
10946 tmp_block
.next
= NULL
;
10947 property_function (fragP
, &tmp_block
.flags
);
10949 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
10950 /* && fragP->fr_fix != 0) */
10952 if ((*xt_block
) == NULL
10953 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
10955 xtensa_block_info
*new_block
;
10956 if ((*xt_block
) != NULL
)
10957 xt_block
= &(*xt_block
)->next
;
10958 new_block
= (xtensa_block_info
*)
10959 xmalloc (sizeof (xtensa_block_info
));
10960 *new_block
= tmp_block
;
10961 *xt_block
= new_block
;
10969 /* op_placement_info_table */
10971 /* op_placement_info makes it easier to determine which
10972 ops can go in which slots. */
10975 init_op_placement_info_table (void)
10977 xtensa_isa isa
= xtensa_default_isa
;
10978 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
10979 xtensa_opcode opcode
;
10982 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
10984 op_placement_table
= (op_placement_info_table
)
10985 xmalloc (sizeof (op_placement_info
) * num_opcodes
);
10986 assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
10988 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
10990 op_placement_info
*opi
= &op_placement_table
[opcode
];
10991 /* FIXME: Make tinsn allocation dynamic. */
10992 if (xtensa_opcode_num_operands (isa
, opcode
) >= MAX_INSN_ARGS
)
10993 as_fatal (_("too many operands in instruction"));
10994 opi
->narrowest
= XTENSA_UNDEFINED
;
10995 opi
->narrowest_size
= 0x7F;
10996 opi
->narrowest_slot
= 0;
10998 opi
->num_formats
= 0;
11000 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
11002 opi
->slots
[fmt
] = 0;
11003 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
11005 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
11007 int fmt_length
= xtensa_format_length (isa
, fmt
);
11009 set_bit (fmt
, opi
->formats
);
11010 set_bit (slot
, opi
->slots
[fmt
]);
11011 if (fmt_length
< opi
->narrowest_size
11012 || (fmt_length
== opi
->narrowest_size
11013 && (xtensa_format_num_slots (isa
, fmt
)
11014 < xtensa_format_num_slots (isa
,
11017 opi
->narrowest
= fmt
;
11018 opi
->narrowest_size
= fmt_length
;
11019 opi
->narrowest_slot
= slot
;
11024 opi
->num_formats
++;
11027 xtensa_insnbuf_free (isa
, ibuf
);
11032 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
11034 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
11038 /* If the opcode is available in a single slot format, return its size. */
11041 xg_get_single_size (xtensa_opcode opcode
)
11043 return op_placement_table
[opcode
].narrowest_size
;
11047 static xtensa_format
11048 xg_get_single_format (xtensa_opcode opcode
)
11050 return op_placement_table
[opcode
].narrowest
;
11055 xg_get_single_slot (xtensa_opcode opcode
)
11057 return op_placement_table
[opcode
].narrowest_slot
;
11061 /* Instruction Stack Functions (from "xtensa-istack.h"). */
11064 istack_init (IStack
*stack
)
11066 memset (stack
, 0, sizeof (IStack
));
11072 istack_empty (IStack
*stack
)
11074 return (stack
->ninsn
== 0);
11079 istack_full (IStack
*stack
)
11081 return (stack
->ninsn
== MAX_ISTACK
);
11085 /* Return a pointer to the top IStack entry.
11086 It is an error to call this if istack_empty () is TRUE. */
11089 istack_top (IStack
*stack
)
11091 int rec
= stack
->ninsn
- 1;
11092 assert (!istack_empty (stack
));
11093 return &stack
->insn
[rec
];
11097 /* Add a new TInsn to an IStack.
11098 It is an error to call this if istack_full () is TRUE. */
11101 istack_push (IStack
*stack
, TInsn
*insn
)
11103 int rec
= stack
->ninsn
;
11104 assert (!istack_full (stack
));
11105 stack
->insn
[rec
] = *insn
;
11110 /* Clear space for the next TInsn on the IStack and return a pointer
11111 to it. It is an error to call this if istack_full () is TRUE. */
11114 istack_push_space (IStack
*stack
)
11116 int rec
= stack
->ninsn
;
11118 assert (!istack_full (stack
));
11119 insn
= &stack
->insn
[rec
];
11126 /* Remove the last pushed instruction. It is an error to call this if
11127 istack_empty () returns TRUE. */
11130 istack_pop (IStack
*stack
)
11132 int rec
= stack
->ninsn
- 1;
11133 assert (!istack_empty (stack
));
11135 tinsn_init (&stack
->insn
[rec
]);
11139 /* TInsn functions. */
11142 tinsn_init (TInsn
*dst
)
11144 memset (dst
, 0, sizeof (TInsn
));
11148 /* Return TRUE if ANY of the operands in the insn are symbolic. */
11151 tinsn_has_symbolic_operands (const TInsn
*insn
)
11154 int n
= insn
->ntok
;
11156 assert (insn
->insn_type
== ITYPE_INSN
);
11158 for (i
= 0; i
< n
; ++i
)
11160 switch (insn
->tok
[i
].X_op
)
11174 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
11176 xtensa_isa isa
= xtensa_default_isa
;
11178 int n
= insn
->ntok
;
11180 assert (insn
->insn_type
== ITYPE_INSN
);
11182 for (i
= 0; i
< n
; ++i
)
11184 switch (insn
->tok
[i
].X_op
)
11192 /* Errors for these types are caught later. */
11197 /* Symbolic immediates are only allowed on the last immediate
11198 operand. At this time, CONST16 is the only opcode where we
11199 support non-PC-relative relocations. */
11200 if (i
!= get_relaxable_immed (insn
->opcode
)
11201 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
11202 && insn
->opcode
!= xtensa_const16_opcode
))
11204 as_bad (_("invalid symbolic operand"));
11213 /* For assembly code with complex expressions (e.g. subtraction),
11214 we have to build them in the literal pool so that
11215 their results are calculated correctly after relaxation.
11216 The relaxation only handles expressions that
11217 boil down to SYMBOL + OFFSET. */
11220 tinsn_has_complex_operands (const TInsn
*insn
)
11223 int n
= insn
->ntok
;
11224 assert (insn
->insn_type
== ITYPE_INSN
);
11225 for (i
= 0; i
< n
; ++i
)
11227 switch (insn
->tok
[i
].X_op
)
11243 /* Encode a TInsn opcode and its constant operands into slotbuf.
11244 Return TRUE if there is a symbol in the immediate field. This
11245 function assumes that:
11246 1) The number of operands are correct.
11247 2) The insn_type is ITYPE_INSN.
11248 3) The opcode can be encoded in the specified format and slot.
11249 4) Operands are either O_constant or O_symbol, and all constants fit. */
11252 tinsn_to_slotbuf (xtensa_format fmt
,
11255 xtensa_insnbuf slotbuf
)
11257 xtensa_isa isa
= xtensa_default_isa
;
11258 xtensa_opcode opcode
= tinsn
->opcode
;
11259 bfd_boolean has_fixup
= FALSE
;
11260 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11263 assert (tinsn
->insn_type
== ITYPE_INSN
);
11264 if (noperands
!= tinsn
->ntok
)
11265 as_fatal (_("operand number mismatch"));
11267 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
11269 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
11270 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
11274 for (i
= 0; i
< noperands
; i
++)
11276 expressionS
*expr
= &tinsn
->tok
[i
];
11282 switch (expr
->X_op
)
11285 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11287 /* The register number has already been checked in
11288 expression_maybe_register, so we don't need to check here. */
11289 opnd_value
= expr
->X_add_number
;
11290 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11291 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
11294 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
11298 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11300 as_where (&file_name
, &line
);
11301 /* It is a constant and we called this function
11302 then we have to try to fit it. */
11303 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
11304 expr
->X_add_number
, file_name
, line
);
11317 /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded
11318 into a multi-slot instruction, fill the other slots with NOPs.
11319 Return TRUE if there is a symbol in the immediate field. See also the
11320 assumptions listed for tinsn_to_slotbuf. */
11323 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
11325 static xtensa_insnbuf slotbuf
= 0;
11326 static vliw_insn vinsn
;
11327 xtensa_isa isa
= xtensa_default_isa
;
11328 bfd_boolean has_fixup
= FALSE
;
11333 slotbuf
= xtensa_insnbuf_alloc (isa
);
11334 xg_init_vinsn (&vinsn
);
11337 xg_clear_vinsn (&vinsn
);
11339 bundle_tinsn (tinsn
, &vinsn
);
11341 xtensa_format_encode (isa
, vinsn
.format
, insnbuf
);
11343 for (i
= 0; i
< vinsn
.num_slots
; i
++)
11345 /* Only one slot may have a fix-up because the rest contains NOPs. */
11347 tinsn_to_slotbuf (vinsn
.format
, i
, &vinsn
.slots
[i
], vinsn
.slotbuf
[i
]);
11348 xtensa_format_set_slot (isa
, vinsn
.format
, i
, insnbuf
, vinsn
.slotbuf
[i
]);
11355 /* Check the instruction arguments. Return TRUE on failure. */
11358 tinsn_check_arguments (const TInsn
*insn
)
11360 xtensa_isa isa
= xtensa_default_isa
;
11361 xtensa_opcode opcode
= insn
->opcode
;
11363 if (opcode
== XTENSA_UNDEFINED
)
11365 as_bad (_("invalid opcode"));
11369 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
11371 as_bad (_("too few operands"));
11375 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
11377 as_bad (_("too many operands"));
11384 /* Load an instruction from its encoded form. */
11387 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
11391 xg_init_vinsn (&vinsn
);
11392 vinsn_from_chars (&vinsn
, f
);
11394 *tinsn
= vinsn
.slots
[slot
];
11395 xg_free_vinsn (&vinsn
);
11400 tinsn_from_insnbuf (TInsn
*tinsn
,
11401 xtensa_insnbuf slotbuf
,
11406 xtensa_isa isa
= xtensa_default_isa
;
11408 /* Find the immed. */
11409 tinsn_init (tinsn
);
11410 tinsn
->insn_type
= ITYPE_INSN
;
11411 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
11412 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
11413 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
11414 for (i
= 0; i
< tinsn
->ntok
; i
++)
11416 set_expr_const (&tinsn
->tok
[i
],
11417 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
11418 tinsn
->opcode
, i
));
11423 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
11426 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
11428 xtensa_opcode opcode
= tinsn
->opcode
;
11431 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
11433 opnum
= get_relaxable_immed (opcode
);
11434 assert (opnum
>= 0);
11435 set_expr_symbol_offset (&tinsn
->tok
[opnum
],
11436 fragP
->tc_frag_data
.slot_symbols
[slot
],
11437 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11443 get_num_stack_text_bytes (IStack
*istack
)
11446 int text_bytes
= 0;
11448 for (i
= 0; i
< istack
->ninsn
; i
++)
11450 TInsn
*tinsn
= &istack
->insn
[i
];
11451 if (tinsn
->insn_type
== ITYPE_INSN
)
11452 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
11459 get_num_stack_literal_bytes (IStack
*istack
)
11464 for (i
= 0; i
< istack
->ninsn
; i
++)
11466 TInsn
*tinsn
= &istack
->insn
[i
];
11467 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
11474 /* vliw_insn functions. */
11477 xg_init_vinsn (vliw_insn
*v
)
11480 xtensa_isa isa
= xtensa_default_isa
;
11482 xg_clear_vinsn (v
);
11484 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
11485 if (v
->insnbuf
== NULL
)
11486 as_fatal (_("out of memory"));
11488 for (i
= 0; i
< MAX_SLOTS
; i
++)
11490 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
11491 if (v
->slotbuf
[i
] == NULL
)
11492 as_fatal (_("out of memory"));
11498 xg_clear_vinsn (vliw_insn
*v
)
11502 memset (v
, 0, offsetof (vliw_insn
, insnbuf
));
11504 v
->format
= XTENSA_UNDEFINED
;
11506 v
->inside_bundle
= FALSE
;
11508 if (xt_saved_debug_type
!= DEBUG_NONE
)
11509 debug_type
= xt_saved_debug_type
;
11511 for (i
= 0; i
< MAX_SLOTS
; i
++)
11512 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
11517 vinsn_has_specific_opcodes (vliw_insn
*v
)
11521 for (i
= 0; i
< v
->num_slots
; i
++)
11523 if (v
->slots
[i
].is_specific_opcode
)
11531 xg_free_vinsn (vliw_insn
*v
)
11534 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
11535 for (i
= 0; i
< MAX_SLOTS
; i
++)
11536 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
11540 /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic
11541 operands. See also the assumptions listed for tinsn_to_slotbuf. */
11544 vinsn_to_insnbuf (vliw_insn
*vinsn
,
11547 bfd_boolean record_fixup
)
11549 xtensa_isa isa
= xtensa_default_isa
;
11550 xtensa_format fmt
= vinsn
->format
;
11551 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
11553 bfd_boolean has_fixup
= FALSE
;
11555 xtensa_format_encode (isa
, fmt
, insnbuf
);
11557 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
11559 TInsn
*tinsn
= &vinsn
->slots
[slot
];
11560 bfd_boolean tinsn_has_fixup
=
11561 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
11562 vinsn
->slotbuf
[slot
]);
11564 xtensa_format_set_slot (isa
, fmt
, slot
,
11565 insnbuf
, vinsn
->slotbuf
[slot
]);
11566 if (tinsn_has_fixup
)
11569 xtensa_opcode opcode
= tinsn
->opcode
;
11570 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11573 for (i
= 0; i
< noperands
; i
++)
11575 expressionS
* expr
= &tinsn
->tok
[i
];
11576 switch (expr
->X_op
)
11581 if (get_relaxable_immed (opcode
) == i
)
11583 /* Add a fix record for the instruction, except if this
11584 function is being called prior to relaxation, i.e.,
11585 if record_fixup is false, and the instruction might
11586 be relaxed later. */
11588 || tinsn
->is_specific_opcode
11589 || !xg_is_relaxable_insn (tinsn
, 0))
11591 xg_add_opcode_fix (tinsn
, i
, fmt
, slot
, expr
, fragP
,
11592 frag_offset
- fragP
->fr_literal
);
11596 if (expr
->X_op
!= O_symbol
)
11597 as_bad (_("invalid operand"));
11598 tinsn
->symbol
= expr
->X_add_symbol
;
11599 tinsn
->offset
= expr
->X_add_number
;
11603 as_bad (_("symbolic operand not allowed"));
11611 as_bad (_("expression too complex"));
11623 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
11625 static xtensa_insnbuf insnbuf
= NULL
;
11626 static xtensa_insnbuf slotbuf
= NULL
;
11629 xtensa_isa isa
= xtensa_default_isa
;
11633 insnbuf
= xtensa_insnbuf_alloc (isa
);
11634 slotbuf
= xtensa_insnbuf_alloc (isa
);
11637 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) f
, 0);
11638 fmt
= xtensa_format_decode (isa
, insnbuf
);
11639 if (fmt
== XTENSA_UNDEFINED
)
11640 as_fatal (_("cannot decode instruction format"));
11641 vinsn
->format
= fmt
;
11642 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
11644 for (i
= 0; i
< vinsn
->num_slots
; i
++)
11646 TInsn
*tinsn
= &vinsn
->slots
[i
];
11647 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
11648 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
11653 /* Expression utilities. */
11655 /* Return TRUE if the expression is an integer constant. */
11658 expr_is_const (const expressionS
*s
)
11660 return (s
->X_op
== O_constant
);
11664 /* Get the expression constant.
11665 Calling this is illegal if expr_is_const () returns TRUE. */
11668 get_expr_const (const expressionS
*s
)
11670 assert (expr_is_const (s
));
11671 return s
->X_add_number
;
11675 /* Set the expression to a constant value. */
11678 set_expr_const (expressionS
*s
, offsetT val
)
11680 s
->X_op
= O_constant
;
11681 s
->X_add_number
= val
;
11682 s
->X_add_symbol
= NULL
;
11683 s
->X_op_symbol
= NULL
;
11688 expr_is_register (const expressionS
*s
)
11690 return (s
->X_op
== O_register
);
11694 /* Get the expression constant.
11695 Calling this is illegal if expr_is_const () returns TRUE. */
11698 get_expr_register (const expressionS
*s
)
11700 assert (expr_is_register (s
));
11701 return s
->X_add_number
;
11705 /* Set the expression to a symbol + constant offset. */
11708 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
11710 s
->X_op
= O_symbol
;
11711 s
->X_add_symbol
= sym
;
11712 s
->X_op_symbol
= NULL
; /* unused */
11713 s
->X_add_number
= offset
;
11717 /* Return TRUE if the two expressions are equal. */
11720 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
11722 if (s1
->X_op
!= s2
->X_op
)
11724 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
11726 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
11728 if (s1
->X_add_number
!= s2
->X_add_number
)
11735 copy_expr (expressionS
*dst
, const expressionS
*src
)
11737 memcpy (dst
, src
, sizeof (expressionS
));
11741 /* Support for the "--rename-section" option. */
11743 struct rename_section_struct
11747 struct rename_section_struct
*next
;
11750 static struct rename_section_struct
*section_rename
;
11753 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
11754 entries to the section_rename list. Note: Specifying multiple
11755 renamings separated by colons is not documented and is retained only
11756 for backward compatibility. */
11759 build_section_rename (const char *arg
)
11761 struct rename_section_struct
*r
;
11762 char *this_arg
= NULL
;
11763 char *next_arg
= NULL
;
11765 for (this_arg
= xstrdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
11767 char *old_name
, *new_name
;
11771 next_arg
= strchr (this_arg
, ':');
11779 old_name
= this_arg
;
11780 new_name
= strchr (this_arg
, '=');
11782 if (*old_name
== '\0')
11784 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
11787 if (!new_name
|| new_name
[1] == '\0')
11789 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
11796 /* Check for invalid section renaming. */
11797 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11799 if (strcmp (r
->old_name
, old_name
) == 0)
11800 as_bad (_("section %s renamed multiple times"), old_name
);
11801 if (strcmp (r
->new_name
, new_name
) == 0)
11802 as_bad (_("multiple sections remapped to output section %s"),
11807 r
= (struct rename_section_struct
*)
11808 xmalloc (sizeof (struct rename_section_struct
));
11809 r
->old_name
= xstrdup (old_name
);
11810 r
->new_name
= xstrdup (new_name
);
11811 r
->next
= section_rename
;
11812 section_rename
= r
;
11818 xtensa_section_rename (char *name
)
11820 struct rename_section_struct
*r
= section_rename
;
11822 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11824 if (strcmp (r
->old_name
, name
) == 0)
11825 return r
->new_name
;