1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright 2003, 2004, 2005 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
25 #include "safe-ctype.h"
26 #include "tc-xtensa.h"
29 #include "xtensa-relax.h"
30 #include "xtensa-istack.h"
31 #include "dwarf2dbg.h"
32 #include "struc-symbol.h"
33 #include "xtensa-config.h"
36 #define uint32 unsigned int
39 #define int32 signed int
44 Naming conventions (used somewhat inconsistently):
45 The xtensa_ functions are exported
46 The xg_ functions are internal
48 We also have a couple of different extensibility mechanisms.
49 1) The idiom replacement:
50 This is used when a line is first parsed to
51 replace an instruction pattern with another instruction
52 It is currently limited to replacements of instructions
53 with constant operands.
54 2) The xtensa-relax.c mechanism that has stronger instruction
55 replacement patterns. When an instruction's immediate field
56 does not fit the next instruction sequence is attempted.
57 In addition, "narrow" opcodes are supported this way. */
60 /* Define characters with special meanings to GAS. */
61 const char comment_chars
[] = "#";
62 const char line_comment_chars
[] = "#";
63 const char line_separator_chars
[] = ";";
64 const char EXP_CHARS
[] = "eE";
65 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
68 /* Flags to indicate whether the hardware supports the density and
69 absolute literals options. */
71 bfd_boolean density_supported
= XCHAL_HAVE_DENSITY
;
72 bfd_boolean absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
74 /* Maximum width we would pad an unreachable frag to get alignment. */
75 #define UNREACHABLE_MAX_WIDTH 8
77 static vliw_insn cur_vinsn
;
79 unsigned xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
81 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
83 /* Some functions are only valid in the front end. This variable
84 allows us to assert that we haven't crossed over into the
86 static bfd_boolean past_xtensa_end
= FALSE
;
88 /* Flags for properties of the last instruction in a segment. */
89 #define FLAG_IS_A0_WRITER 0x1
90 #define FLAG_IS_BAD_LOOPEND 0x2
93 /* We define a special segment names ".literal" to place literals
94 into. The .fini and .init sections are special because they
95 contain code that is moved together by the linker. We give them
96 their own special .fini.literal and .init.literal sections. */
98 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
99 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
100 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
101 #define INIT_SECTION_NAME xtensa_section_rename (".init")
102 #define FINI_LITERAL_SECTION_NAME xtensa_section_rename (".fini.literal")
103 #define INIT_LITERAL_SECTION_NAME xtensa_section_rename (".init.literal")
106 /* This type is used for the directive_stack to keep track of the
107 state of the literal collection pools. */
109 typedef struct lit_state_struct
111 const char *lit_seg_name
;
112 const char *lit4_seg_name
;
113 const char *init_lit_seg_name
;
114 const char *fini_lit_seg_name
;
121 static lit_state default_lit_sections
;
124 /* We keep lists of literal segments. The seg_list type is the node
125 for such a list. The *_literal_head locals are the heads of the
126 various lists. All of these lists have a dummy node at the start. */
128 typedef struct seg_list_struct
130 struct seg_list_struct
*next
;
134 static seg_list literal_head_h
;
135 static seg_list
*literal_head
= &literal_head_h
;
136 static seg_list init_literal_head_h
;
137 static seg_list
*init_literal_head
= &init_literal_head_h
;
138 static seg_list fini_literal_head_h
;
139 static seg_list
*fini_literal_head
= &fini_literal_head_h
;
142 /* Lists of symbols. We keep a list of symbols that label the current
143 instruction, so that we can adjust the symbols when inserting alignment
144 for various instructions. We also keep a list of all the symbols on
145 literals, so that we can fix up those symbols when the literals are
146 later moved into the text sections. */
148 typedef struct sym_list_struct
150 struct sym_list_struct
*next
;
154 static sym_list
*insn_labels
= NULL
;
155 static sym_list
*free_insn_labels
= NULL
;
156 static sym_list
*saved_insn_labels
= NULL
;
158 static sym_list
*literal_syms
;
161 /* Flags to determine whether to prefer const16 or l32r
162 if both options are available. */
163 int prefer_const16
= 0;
166 /* Global flag to indicate when we are emitting literals. */
167 int generating_literals
= 0;
169 /* The following PROPERTY table definitions are copied from
170 <elf/xtensa.h> and must be kept in sync with the code there. */
172 /* Flags in the property tables to specify whether blocks of memory
173 are literals, instructions, data, or unreachable. For
174 instructions, blocks that begin loop targets and branch targets are
175 designated. Blocks that do not allow density, instruction
176 reordering or transformation are also specified. Finally, for
177 branch targets, branch target alignment priority is included.
178 Alignment of the next block is specified in the current block
179 and the size of the current block does not include any fill required
180 to align to the next block. */
182 #define XTENSA_PROP_LITERAL 0x00000001
183 #define XTENSA_PROP_INSN 0x00000002
184 #define XTENSA_PROP_DATA 0x00000004
185 #define XTENSA_PROP_UNREACHABLE 0x00000008
186 /* Instruction only properties at beginning of code. */
187 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
188 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
189 /* Instruction only properties about code. */
190 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
191 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
192 #define XTENSA_PROP_INSN_NO_TRANSFORM 0x00000100
194 /* Branch target alignment information. This transmits information
195 to the linker optimization about the priority of aligning a
196 particular block for branch target alignment: None, low priority,
197 high priority, or required. These only need to be checked in
198 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
201 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
202 case XTENSA_PROP_BT_ALIGN_NONE:
203 case XTENSA_PROP_BT_ALIGN_LOW:
204 case XTENSA_PROP_BT_ALIGN_HIGH:
205 case XTENSA_PROP_BT_ALIGN_REQUIRE:
207 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
209 /* No branch target alignment. */
210 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
211 /* Low priority branch target alignment. */
212 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
213 /* High priority branch target alignment. */
214 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
215 /* Required branch target alignment. */
216 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
218 #define GET_XTENSA_PROP_BT_ALIGN(flag) \
219 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
220 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
221 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
222 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
225 /* Alignment is specified in the block BEFORE the one that needs
226 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
227 get the required alignment specified as a power of 2. Use
228 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
229 alignment. Be careful of side effects since the SET will evaluate
230 flags twice. Also, note that the SIZE of a block in the property
231 table does not include the alignment size, so the alignment fill
232 must be calculated to determine if two blocks are contiguous.
233 TEXT_ALIGN is not currently implemented but is a placeholder for a
234 possible future implementation. */
236 #define XTENSA_PROP_ALIGN 0x00000800
238 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
240 #define GET_XTENSA_PROP_ALIGNMENT(flag) \
241 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
242 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
243 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
244 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
246 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
249 /* Structure for saving instruction and alignment per-fragment data
250 that will be written to the object file. This structure is
251 equivalent to the actual data that will be written out to the file
252 but is easier to use. We provide a conversion to file flags
253 in frag_flags_to_number. */
255 typedef struct frag_flags_struct frag_flags
;
257 struct frag_flags_struct
259 /* is_literal should only be used after xtensa_move_literals.
260 If you need to check if you are generating a literal fragment,
261 then use the generating_literals global. */
263 unsigned is_literal
: 1;
264 unsigned is_insn
: 1;
265 unsigned is_data
: 1;
266 unsigned is_unreachable
: 1;
270 unsigned is_loop_target
: 1;
271 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
272 unsigned bt_align_priority
: 2;
274 unsigned is_no_density
: 1;
275 /* no_longcalls flag does not need to be placed in the object file. */
276 /* is_specific_opcode implies no_transform. */
277 unsigned is_no_transform
: 1;
279 unsigned is_no_reorder
: 1;
281 /* Uses absolute literal addressing for l32r. */
282 unsigned is_abslit
: 1;
284 unsigned is_align
: 1;
285 unsigned alignment
: 5;
289 /* Structure for saving information about a block of property data
290 for frags that have the same flags. */
291 struct xtensa_block_info_struct
297 struct xtensa_block_info_struct
*next
;
301 /* Structure for saving the current state before emitting literals. */
302 typedef struct emit_state_struct
307 int generating_literals
;
311 /* Opcode placement information */
313 typedef unsigned long long bitfield
;
314 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
315 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
316 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
318 #define MAX_FORMATS 32
320 typedef struct op_placement_info_struct
323 /* A number describing how restrictive the issue is for this
324 opcode. For example, an opcode that fits lots of different
325 formats has a high freedom, as does an opcode that fits
326 only one format but many slots in that format. The most
327 restrictive is the opcode that fits only one slot in one
330 /* The single format (i.e., if the op can live in a bundle by itself),
331 narrowest format, and widest format the op can be bundled in
333 xtensa_format single
;
334 xtensa_format narrowest
;
335 xtensa_format widest
;
340 /* formats is a bitfield with the Nth bit set
341 if the opcode fits in the Nth xtensa_format. */
344 /* slots[N]'s Mth bit is set if the op fits in the
345 Mth slot of the Nth xtensa_format. */
346 bitfield slots
[MAX_FORMATS
];
348 /* A count of the number of slots in a given format
349 an op can fit (i.e., the bitcount of the slot field above). */
350 char slots_in_format
[MAX_FORMATS
];
352 } op_placement_info
, *op_placement_info_table
;
354 op_placement_info_table op_placement_table
;
357 /* Extra expression types. */
359 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
360 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
361 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
374 directive_literal_prefix
,
376 directive_absolute_literals
,
377 directive_last_directive
383 bfd_boolean can_be_negated
;
386 const directive_infoS directive_info
[] =
389 { "literal", FALSE
},
391 { "transform", TRUE
},
392 { "freeregs", FALSE
},
393 { "longcalls", TRUE
},
394 { "literal_prefix", FALSE
},
395 { "schedule", TRUE
},
396 { "absolute-literals", TRUE
}
399 bfd_boolean directive_state
[] =
403 #if !XCHAL_HAVE_DENSITY
408 TRUE
, /* transform */
409 FALSE
, /* freeregs */
410 FALSE
, /* longcalls */
411 FALSE
, /* literal_prefix */
413 #if XSHAL_USE_ABSOLUTE_LITERALS
414 TRUE
/* absolute_literals */
416 FALSE
/* absolute_literals */
421 /* Directive functions. */
423 static void xtensa_begin_directive (int);
424 static void xtensa_end_directive (int);
425 static void xtensa_literal_prefix (char const *, int);
426 static void xtensa_literal_position (int);
427 static void xtensa_literal_pseudo (int);
428 static void xtensa_frequency_pseudo (int);
429 static void xtensa_elf_cons (int);
431 /* Parsing and Idiom Translation. */
433 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
435 /* Various Other Internal Functions. */
437 extern bfd_boolean
xg_is_single_relaxable_insn (TInsn
*, TInsn
*, bfd_boolean
);
438 static bfd_boolean
xg_build_to_insn (TInsn
*, TInsn
*, BuildInstr
*);
439 static void xtensa_mark_literal_pool_location (void);
440 static addressT
get_expanded_loop_offset (xtensa_opcode
);
441 static fragS
*get_literal_pool_location (segT
);
442 static void set_literal_pool_location (segT
, fragS
*);
443 static void xtensa_set_frag_assembly_state (fragS
*);
444 static void finish_vinsn (vliw_insn
*);
445 static bfd_boolean
emit_single_op (TInsn
*);
446 static int total_frag_text_expansion (fragS
*);
448 /* Alignment Functions. */
450 static int get_text_align_power (unsigned);
451 static int get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
452 static int branch_align_power (segT
);
454 /* Helpers for xtensa_relax_frag(). */
456 static long relax_frag_add_nop (fragS
*);
458 /* Accessors for additional per-subsegment information. */
460 static unsigned get_last_insn_flags (segT
, subsegT
);
461 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
462 static float get_subseg_total_freq (segT
, subsegT
);
463 static float get_subseg_target_freq (segT
, subsegT
);
464 static void set_subseg_freq (segT
, subsegT
, float, float);
466 /* Segment list functions. */
468 static void xtensa_move_literals (void);
469 static void xtensa_reorder_segments (void);
470 static void xtensa_switch_to_literal_fragment (emit_state
*);
471 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
472 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
473 static void xtensa_restore_emit_state (emit_state
*);
474 static void cache_literal_section
475 (seg_list
*, const char *, segT
*, bfd_boolean
);
477 /* Import from elf32-xtensa.c in BFD library. */
479 extern char *xtensa_get_property_section_name (asection
*, const char *);
481 /* op_placement_info functions. */
483 static void init_op_placement_info_table (void);
484 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
485 static int xg_get_single_size (xtensa_opcode
);
486 static xtensa_format
xg_get_single_format (xtensa_opcode
);
488 /* TInsn and IStack functions. */
490 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
491 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
492 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
493 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
494 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
495 static void tinsn_from_chars (TInsn
*, char *, int);
496 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
497 static int get_num_stack_text_bytes (IStack
*);
498 static int get_num_stack_literal_bytes (IStack
*);
500 /* vliw_insn functions. */
502 static void xg_init_vinsn (vliw_insn
*);
503 static void xg_clear_vinsn (vliw_insn
*);
504 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
505 static void xg_free_vinsn (vliw_insn
*);
506 static bfd_boolean vinsn_to_insnbuf
507 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
508 static void vinsn_from_chars (vliw_insn
*, char *);
510 /* Expression Utilities. */
512 bfd_boolean
expr_is_const (const expressionS
*);
513 offsetT
get_expr_const (const expressionS
*);
514 void set_expr_const (expressionS
*, offsetT
);
515 bfd_boolean
expr_is_register (const expressionS
*);
516 offsetT
get_expr_register (const expressionS
*);
517 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
518 static void set_expr_symbol_offset_diff
519 (expressionS
*, symbolS
*, symbolS
*, offsetT
);
520 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
521 static void copy_expr (expressionS
*, const expressionS
*);
523 /* Section renaming. */
525 static void build_section_rename (const char *);
528 /* ISA imported from bfd. */
529 extern xtensa_isa xtensa_default_isa
;
531 extern int target_big_endian
;
533 static xtensa_opcode xtensa_addi_opcode
;
534 static xtensa_opcode xtensa_addmi_opcode
;
535 static xtensa_opcode xtensa_call0_opcode
;
536 static xtensa_opcode xtensa_call4_opcode
;
537 static xtensa_opcode xtensa_call8_opcode
;
538 static xtensa_opcode xtensa_call12_opcode
;
539 static xtensa_opcode xtensa_callx0_opcode
;
540 static xtensa_opcode xtensa_callx4_opcode
;
541 static xtensa_opcode xtensa_callx8_opcode
;
542 static xtensa_opcode xtensa_callx12_opcode
;
543 static xtensa_opcode xtensa_const16_opcode
;
544 static xtensa_opcode xtensa_entry_opcode
;
545 static xtensa_opcode xtensa_movi_opcode
;
546 static xtensa_opcode xtensa_movi_n_opcode
;
547 static xtensa_opcode xtensa_isync_opcode
;
548 static xtensa_opcode xtensa_jx_opcode
;
549 static xtensa_opcode xtensa_l32r_opcode
;
550 static xtensa_opcode xtensa_loop_opcode
;
551 static xtensa_opcode xtensa_loopnez_opcode
;
552 static xtensa_opcode xtensa_loopgtz_opcode
;
553 static xtensa_opcode xtensa_nop_opcode
;
554 static xtensa_opcode xtensa_nop_n_opcode
;
555 static xtensa_opcode xtensa_or_opcode
;
556 static xtensa_opcode xtensa_ret_opcode
;
557 static xtensa_opcode xtensa_ret_n_opcode
;
558 static xtensa_opcode xtensa_retw_opcode
;
559 static xtensa_opcode xtensa_retw_n_opcode
;
560 static xtensa_opcode xtensa_rsr_lcount_opcode
;
561 static xtensa_opcode xtensa_waiti_opcode
;
564 /* Command-line Options. */
566 bfd_boolean use_literal_section
= TRUE
;
567 static bfd_boolean align_targets
= TRUE
;
568 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
569 static bfd_boolean has_a0_b_retw
= FALSE
;
570 static bfd_boolean workaround_a0_b_retw
= FALSE
;
571 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
572 static bfd_boolean workaround_short_loop
= FALSE
;
573 static bfd_boolean maybe_has_short_loop
= FALSE
;
574 static bfd_boolean workaround_close_loop_end
= FALSE
;
575 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
577 /* When workaround_short_loops is TRUE, all loops with early exits must
578 have at least 3 instructions. workaround_all_short_loops is a modifier
579 to the workaround_short_loop flag. In addition to the
580 workaround_short_loop actions, all straightline loopgtz and loopnez
581 must have at least 3 instructions. */
583 static bfd_boolean workaround_all_short_loops
= FALSE
;
587 xtensa_setup_hw_workarounds (int earliest
, int latest
)
589 if (earliest
> latest
)
590 as_fatal (_("illegal range of target hardware versions"));
592 /* Enable all workarounds for pre-T1050.0 hardware. */
593 if (earliest
< 105000 || latest
< 105000)
595 workaround_a0_b_retw
|= TRUE
;
596 workaround_b_j_loop_end
|= TRUE
;
597 workaround_short_loop
|= TRUE
;
598 workaround_close_loop_end
|= TRUE
;
599 workaround_all_short_loops
|= TRUE
;
606 option_density
= OPTION_MD_BASE
,
613 option_no_link_relax
,
621 option_text_section_literals
,
622 option_no_text_section_literals
,
624 option_absolute_literals
,
625 option_no_absolute_literals
,
627 option_align_targets
,
628 option_no_align_targets
,
630 option_warn_unaligned_targets
,
635 option_workaround_a0_b_retw
,
636 option_no_workaround_a0_b_retw
,
638 option_workaround_b_j_loop_end
,
639 option_no_workaround_b_j_loop_end
,
641 option_workaround_short_loop
,
642 option_no_workaround_short_loop
,
644 option_workaround_all_short_loops
,
645 option_no_workaround_all_short_loops
,
647 option_workaround_close_loop_end
,
648 option_no_workaround_close_loop_end
,
650 option_no_workarounds
,
652 option_rename_section_name
,
655 option_prefer_const16
,
657 option_target_hardware
660 const char *md_shortopts
= "";
662 struct option md_longopts
[] =
664 { "density", no_argument
, NULL
, option_density
},
665 { "no-density", no_argument
, NULL
, option_no_density
},
667 /* Both "relax" and "generics" are deprecated and treated as equivalent
668 to the "transform" option. */
669 { "relax", no_argument
, NULL
, option_relax
},
670 { "no-relax", no_argument
, NULL
, option_no_relax
},
671 { "generics", no_argument
, NULL
, option_generics
},
672 { "no-generics", no_argument
, NULL
, option_no_generics
},
674 { "transform", no_argument
, NULL
, option_transform
},
675 { "no-transform", no_argument
, NULL
, option_no_transform
},
676 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
677 { "no-text-section-literals", no_argument
, NULL
,
678 option_no_text_section_literals
},
679 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
680 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
681 /* This option was changed from -align-target to -target-align
682 because it conflicted with the "-al" option. */
683 { "target-align", no_argument
, NULL
, option_align_targets
},
684 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
685 { "warn-unaligned-targets", no_argument
, NULL
,
686 option_warn_unaligned_targets
},
687 { "longcalls", no_argument
, NULL
, option_longcalls
},
688 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
690 { "no-workaround-a0-b-retw", no_argument
, NULL
,
691 option_no_workaround_a0_b_retw
},
692 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
694 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
695 option_no_workaround_b_j_loop_end
},
696 { "workaround-b-j-loop-end", no_argument
, NULL
,
697 option_workaround_b_j_loop_end
},
699 { "no-workaround-short-loops", no_argument
, NULL
,
700 option_no_workaround_short_loop
},
701 { "workaround-short-loops", no_argument
, NULL
,
702 option_workaround_short_loop
},
704 { "no-workaround-all-short-loops", no_argument
, NULL
,
705 option_no_workaround_all_short_loops
},
706 { "workaround-all-short-loop", no_argument
, NULL
,
707 option_workaround_all_short_loops
},
709 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
710 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
712 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
714 { "no-workaround-close-loop-end", no_argument
, NULL
,
715 option_no_workaround_close_loop_end
},
716 { "workaround-close-loop-end", no_argument
, NULL
,
717 option_workaround_close_loop_end
},
719 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
721 { "link-relax", no_argument
, NULL
, option_link_relax
},
722 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
724 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
726 { NULL
, no_argument
, NULL
, 0 }
729 size_t md_longopts_size
= sizeof md_longopts
;
733 md_parse_option (int c
, char *arg
)
738 as_warn (_("--density option is ignored"));
740 case option_no_density
:
741 as_warn (_("--no-density option is ignored"));
743 case option_link_relax
:
746 case option_no_link_relax
:
749 case option_generics
:
750 as_warn (_("--generics is deprecated; use --transform instead"));
751 return md_parse_option (option_transform
, arg
);
752 case option_no_generics
:
753 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
754 return md_parse_option (option_no_transform
, arg
);
756 as_warn (_("--relax is deprecated; use --transform instead"));
757 return md_parse_option (option_transform
, arg
);
758 case option_no_relax
:
759 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
760 return md_parse_option (option_no_transform
, arg
);
761 case option_longcalls
:
762 directive_state
[directive_longcalls
] = TRUE
;
764 case option_no_longcalls
:
765 directive_state
[directive_longcalls
] = FALSE
;
767 case option_text_section_literals
:
768 use_literal_section
= FALSE
;
770 case option_no_text_section_literals
:
771 use_literal_section
= TRUE
;
773 case option_absolute_literals
:
774 if (!absolute_literals_supported
)
776 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
779 directive_state
[directive_absolute_literals
] = TRUE
;
781 case option_no_absolute_literals
:
782 directive_state
[directive_absolute_literals
] = FALSE
;
785 case option_workaround_a0_b_retw
:
786 workaround_a0_b_retw
= TRUE
;
788 case option_no_workaround_a0_b_retw
:
789 workaround_a0_b_retw
= FALSE
;
791 case option_workaround_b_j_loop_end
:
792 workaround_b_j_loop_end
= TRUE
;
794 case option_no_workaround_b_j_loop_end
:
795 workaround_b_j_loop_end
= FALSE
;
798 case option_workaround_short_loop
:
799 workaround_short_loop
= TRUE
;
801 case option_no_workaround_short_loop
:
802 workaround_short_loop
= FALSE
;
805 case option_workaround_all_short_loops
:
806 workaround_all_short_loops
= TRUE
;
808 case option_no_workaround_all_short_loops
:
809 workaround_all_short_loops
= FALSE
;
812 case option_workaround_close_loop_end
:
813 workaround_close_loop_end
= TRUE
;
815 case option_no_workaround_close_loop_end
:
816 workaround_close_loop_end
= FALSE
;
819 case option_no_workarounds
:
820 workaround_a0_b_retw
= FALSE
;
821 workaround_b_j_loop_end
= FALSE
;
822 workaround_short_loop
= FALSE
;
823 workaround_all_short_loops
= FALSE
;
824 workaround_close_loop_end
= FALSE
;
827 case option_align_targets
:
828 align_targets
= TRUE
;
830 case option_no_align_targets
:
831 align_targets
= FALSE
;
834 case option_warn_unaligned_targets
:
835 warn_unaligned_branch_targets
= TRUE
;
838 case option_rename_section_name
:
839 build_section_rename (arg
);
843 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
844 should be emitted or not. FIXME: Not implemented. */
847 case option_prefer_l32r
:
849 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
853 case option_prefer_const16
:
855 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
859 case option_target_hardware
:
861 int earliest
, latest
= 0;
862 if (*arg
== 0 || *arg
== '-')
863 as_fatal (_("invalid target hardware version"));
865 earliest
= strtol (arg
, &arg
, 0);
869 else if (*arg
== '-')
872 as_fatal (_("invalid target hardware version"));
873 latest
= strtol (arg
, &arg
, 0);
876 as_fatal (_("invalid target hardware version"));
878 xtensa_setup_hw_workarounds (earliest
, latest
);
882 case option_transform
:
883 /* This option has no affect other than to use the defaults,
884 which are already set. */
887 case option_no_transform
:
888 /* This option turns off all transformations of any kind.
889 However, because we want to preserve the state of other
890 directives, we only change its own field. Thus, before
891 you perform any transformation, always check if transform
892 is available. If you use the functions we provide for this
893 purpose, you will be ok. */
894 directive_state
[directive_transform
] = FALSE
;
904 md_show_usage (FILE *stream
)
908 --[no-]text-section-literals\n\
909 [Do not] put literals in the text section\n\
910 --[no-]absolute-literals\n\
911 [Do not] default to use non-PC-relative literals\n\
912 --[no-]target-align [Do not] try to align branch targets\n\
913 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
914 --[no-]transform [Do not] transform instructions\n\
915 --rename-section old=new Rename section 'old' to 'new'\n", stream
);
919 /* Functions related to the list of current label symbols. */
922 xtensa_add_insn_label (symbolS
*sym
)
926 if (!free_insn_labels
)
927 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
930 l
= free_insn_labels
;
931 free_insn_labels
= l
->next
;
935 l
->next
= insn_labels
;
941 xtensa_clear_insn_labels (void)
945 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
952 /* The "loops_ok" argument is provided to allow ignoring labels that
953 define loop ends. This fixes a bug where the NOPs to align a
954 loop opcode were included in a previous zero-cost loop:
973 This argument is used to prevent moving the NOP to before the
974 loop-end label, which is what you want in this special case. */
977 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
, bfd_boolean loops_ok
)
981 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
983 symbolS
*lit_sym
= lit
->sym
;
984 if (loops_ok
|| ! symbol_get_tc (lit_sym
)->is_loop_target
)
986 S_SET_VALUE (lit_sym
, new_offset
);
987 symbol_set_frag (lit_sym
, new_frag
);
993 /* Directive data and functions. */
995 typedef struct state_stackS_struct
997 directiveE directive
;
999 bfd_boolean old_state
;
1003 struct state_stackS_struct
*prev
;
1006 state_stackS
*directive_state_stack
;
1008 const pseudo_typeS md_pseudo_table
[] =
1010 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
1011 { "literal_position", xtensa_literal_position
, 0 },
1012 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
1013 { "long", xtensa_elf_cons
, 4 },
1014 { "word", xtensa_elf_cons
, 4 },
1015 { "short", xtensa_elf_cons
, 2 },
1016 { "begin", xtensa_begin_directive
, 0 },
1017 { "end", xtensa_end_directive
, 0 },
1018 { "literal", xtensa_literal_pseudo
, 0 },
1019 { "frequency", xtensa_frequency_pseudo
, 0 },
1025 use_transform (void)
1027 /* After md_end, you should be checking frag by frag, rather
1028 than state directives. */
1029 assert (!past_xtensa_end
);
1030 return directive_state
[directive_transform
];
1035 do_align_targets (void)
1037 /* Do not use this function after md_end; just look at align_targets
1038 instead. There is no target-align directive, so alignment is either
1039 enabled for all frags or not done at all. */
1040 assert (!past_xtensa_end
);
1041 return align_targets
&& use_transform ();
1046 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1050 state_stackS
*stack
= (state_stackS
*) xmalloc (sizeof (state_stackS
));
1052 as_where (&file
, &line
);
1054 stack
->directive
= directive
;
1055 stack
->negated
= negated
;
1056 stack
->old_state
= directive_state
[directive
];
1059 stack
->datum
= datum
;
1060 stack
->prev
= directive_state_stack
;
1061 directive_state_stack
= stack
;
1063 directive_state
[directive
] = !negated
;
1068 directive_pop (directiveE
*directive
,
1069 bfd_boolean
*negated
,
1074 state_stackS
*top
= directive_state_stack
;
1076 if (!directive_state_stack
)
1078 as_bad (_("unmatched end directive"));
1079 *directive
= directive_none
;
1083 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1084 *directive
= top
->directive
;
1085 *negated
= top
->negated
;
1088 *datum
= top
->datum
;
1089 directive_state_stack
= top
->prev
;
1095 directive_balance (void)
1097 while (directive_state_stack
)
1099 directiveE directive
;
1100 bfd_boolean negated
;
1105 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1106 as_warn_where ((char *) file
, line
,
1107 _(".begin directive with no matching .end directive"));
1113 inside_directive (directiveE dir
)
1115 state_stackS
*top
= directive_state_stack
;
1117 while (top
&& top
->directive
!= dir
)
1120 return (top
!= NULL
);
1125 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1129 char *directive_string
;
1131 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1136 input_line_pointer
+= 3;
1139 len
= strspn (input_line_pointer
,
1140 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1142 /* This code is a hack to make .begin [no-][generics|relax] exactly
1143 equivalent to .begin [no-]transform. We should remove it when
1144 we stop accepting those options. */
1146 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1148 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1149 directive_string
= "transform";
1151 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1153 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1154 directive_string
= "transform";
1157 directive_string
= input_line_pointer
;
1159 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1161 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1163 input_line_pointer
+= len
;
1164 *directive
= (directiveE
) i
;
1165 if (*negated
&& !directive_info
[i
].can_be_negated
)
1166 as_bad (_("directive %s cannot be negated"),
1167 directive_info
[i
].name
);
1172 as_bad (_("unknown directive"));
1173 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1178 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1180 directiveE directive
;
1181 bfd_boolean negated
;
1186 get_directive (&directive
, &negated
);
1187 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1189 discard_rest_of_line ();
1193 if (cur_vinsn
.inside_bundle
)
1194 as_bad (_("directives are not valid inside bundles"));
1198 case directive_literal
:
1199 if (!inside_directive (directive_literal
))
1201 /* Previous labels go with whatever follows this directive, not with
1202 the literal, so save them now. */
1203 saved_insn_labels
= insn_labels
;
1206 as_warn (_(".begin literal is deprecated; use .literal instead"));
1207 state
= (emit_state
*) xmalloc (sizeof (emit_state
));
1208 xtensa_switch_to_literal_fragment (state
);
1209 directive_push (directive_literal
, negated
, state
);
1212 case directive_literal_prefix
:
1213 /* Have to flush pending output because a movi relaxed to an l32r
1214 might produce a literal. */
1215 md_flush_pending_output ();
1216 /* Check to see if the current fragment is a literal
1217 fragment. If it is, then this operation is not allowed. */
1218 if (generating_literals
)
1220 as_bad (_("cannot set literal_prefix inside literal fragment"));
1224 /* Allocate the literal state for this section and push
1225 onto the directive stack. */
1226 ls
= xmalloc (sizeof (lit_state
));
1229 *ls
= default_lit_sections
;
1231 directive_push (directive_literal_prefix
, negated
, ls
);
1233 /* Parse the new prefix from the input_line_pointer. */
1235 len
= strspn (input_line_pointer
,
1236 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1237 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1239 /* Process the new prefix. */
1240 xtensa_literal_prefix (input_line_pointer
, len
);
1242 /* Skip the name in the input line. */
1243 input_line_pointer
+= len
;
1246 case directive_freeregs
:
1247 /* This information is currently unused, but we'll accept the statement
1248 and just discard the rest of the line. This won't check the syntax,
1249 but it will accept every correct freeregs directive. */
1250 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1251 directive_push (directive_freeregs
, negated
, 0);
1254 case directive_schedule
:
1255 md_flush_pending_output ();
1256 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1257 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1258 directive_push (directive_schedule
, negated
, 0);
1259 xtensa_set_frag_assembly_state (frag_now
);
1262 case directive_density
:
1263 as_warn (_(".begin [no-]density is ignored"));
1266 case directive_absolute_literals
:
1267 md_flush_pending_output ();
1268 if (!absolute_literals_supported
&& !negated
)
1270 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1273 xtensa_set_frag_assembly_state (frag_now
);
1274 directive_push (directive
, negated
, 0);
1278 md_flush_pending_output ();
1279 xtensa_set_frag_assembly_state (frag_now
);
1280 directive_push (directive
, negated
, 0);
1284 demand_empty_rest_of_line ();
1289 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1291 directiveE begin_directive
, end_directive
;
1292 bfd_boolean begin_negated
, end_negated
;
1296 emit_state
**state_ptr
;
1299 if (cur_vinsn
.inside_bundle
)
1300 as_bad (_("directives are not valid inside bundles"));
1302 get_directive (&end_directive
, &end_negated
);
1304 md_flush_pending_output ();
1306 switch (end_directive
)
1308 case (directiveE
) XTENSA_UNDEFINED
:
1309 discard_rest_of_line ();
1312 case directive_density
:
1313 as_warn (_(".end [no-]density is ignored"));
1314 demand_empty_rest_of_line ();
1317 case directive_absolute_literals
:
1318 if (!absolute_literals_supported
&& !end_negated
)
1320 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1321 demand_empty_rest_of_line ();
1330 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1331 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1332 (const void **) state_ptr
);
1334 if (begin_directive
!= directive_none
)
1336 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1338 as_bad (_("does not match begin %s%s at %s:%d"),
1339 begin_negated
? "no-" : "",
1340 directive_info
[begin_directive
].name
, file
, line
);
1344 switch (end_directive
)
1346 case directive_literal
:
1347 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1348 xtensa_restore_emit_state (state
);
1349 xtensa_set_frag_assembly_state (frag_now
);
1351 if (!inside_directive (directive_literal
))
1353 /* Restore the list of current labels. */
1354 xtensa_clear_insn_labels ();
1355 insn_labels
= saved_insn_labels
;
1359 case directive_literal_prefix
:
1360 /* Restore the default collection sections from saved state. */
1361 s
= (lit_state
*) state
;
1364 default_lit_sections
= *s
;
1366 /* free the state storage */
1370 case directive_schedule
:
1371 case directive_freeregs
:
1375 xtensa_set_frag_assembly_state (frag_now
);
1381 demand_empty_rest_of_line ();
1385 /* Place an aligned literal fragment at the current location. */
1388 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1390 md_flush_pending_output ();
1392 if (inside_directive (directive_literal
))
1393 as_warn (_(".literal_position inside literal directive; ignoring"));
1394 xtensa_mark_literal_pool_location ();
1396 demand_empty_rest_of_line ();
1397 xtensa_clear_insn_labels ();
1401 /* Support .literal label, expr, ... */
1404 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1407 char *p
, *base_name
;
1411 if (inside_directive (directive_literal
))
1413 as_bad (_(".literal not allowed inside .begin literal region"));
1414 ignore_rest_of_line ();
1418 md_flush_pending_output ();
1420 /* Previous labels go with whatever follows this directive, not with
1421 the literal, so save them now. */
1422 saved_insn_labels
= insn_labels
;
1425 /* If we are using text-section literals, then this is the right value... */
1428 base_name
= input_line_pointer
;
1430 xtensa_switch_to_literal_fragment (&state
);
1432 /* ...but if we aren't using text-section-literals, then we
1433 need to put them in the section we just switched to. */
1434 if (use_literal_section
|| directive_state
[directive_absolute_literals
])
1437 /* All literals are aligned to four-byte boundaries. */
1438 frag_align (2, 0, 0);
1439 record_alignment (now_seg
, 2);
1441 c
= get_symbol_end ();
1442 /* Just after name is now '\0'. */
1443 p
= input_line_pointer
;
1447 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1449 as_bad (_("expected comma or colon after symbol name; "
1450 "rest of line ignored"));
1451 ignore_rest_of_line ();
1452 xtensa_restore_emit_state (&state
);
1460 input_line_pointer
++; /* skip ',' or ':' */
1462 xtensa_elf_cons (4);
1464 xtensa_restore_emit_state (&state
);
1466 /* Restore the list of current labels. */
1467 xtensa_clear_insn_labels ();
1468 insn_labels
= saved_insn_labels
;
1473 xtensa_literal_prefix (char const *start
, int len
)
1475 char *name
, *linkonce_suffix
;
1476 char *newname
, *newname4
;
1477 size_t linkonce_len
;
1479 /* Get a null-terminated copy of the name. */
1480 name
= xmalloc (len
+ 1);
1483 strncpy (name
, start
, len
);
1486 /* Allocate the sections (interesting note: the memory pointing to
1487 the name is actually used for the name by the new section). */
1489 newname
= xmalloc (len
+ strlen (".literal") + 1);
1490 newname4
= xmalloc (len
+ strlen (".lit4") + 1);
1492 linkonce_len
= sizeof (".gnu.linkonce.") - 1;
1493 if (strncmp (name
, ".gnu.linkonce.", linkonce_len
) == 0
1494 && (linkonce_suffix
= strchr (name
+ linkonce_len
, '.')) != 0)
1496 strcpy (newname
, ".gnu.linkonce.literal");
1497 strcpy (newname4
, ".gnu.linkonce.lit4");
1499 strcat (newname
, linkonce_suffix
);
1500 strcat (newname4
, linkonce_suffix
);
1504 int suffix_pos
= len
;
1506 /* If the section name ends with ".text", then replace that suffix
1507 instead of appending an additional suffix. */
1508 if (len
>= 5 && strcmp (name
+ len
- 5, ".text") == 0)
1511 strcpy (newname
, name
);
1512 strcpy (newname4
, name
);
1514 strcpy (newname
+ suffix_pos
, ".literal");
1515 strcpy (newname4
+ suffix_pos
, ".lit4");
1518 /* Note that cache_literal_section does not create a segment if
1519 it already exists. */
1520 default_lit_sections
.lit_seg
= NULL
;
1521 default_lit_sections
.lit4_seg
= NULL
;
1523 /* Canonicalizing section names allows renaming literal
1524 sections to occur correctly. */
1525 default_lit_sections
.lit_seg_name
= tc_canonicalize_symbol_name (newname
);
1526 default_lit_sections
.lit4_seg_name
= tc_canonicalize_symbol_name (newname4
);
1532 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1535 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1537 float fall_through_f
, target_f
;
1539 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1540 if (fall_through_f
< 0)
1542 as_bad (_("fall through frequency must be greater than 0"));
1543 ignore_rest_of_line ();
1547 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1550 as_bad (_("branch target frequency must be greater than 0"));
1551 ignore_rest_of_line ();
1555 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1557 demand_empty_rest_of_line ();
1561 /* Like normal .long/.short/.word, except support @plt, etc.
1562 Clobbers input_line_pointer, checks end-of-line. */
1565 xtensa_elf_cons (int nbytes
)
1568 bfd_reloc_code_real_type reloc
;
1570 md_flush_pending_output ();
1572 if (cur_vinsn
.inside_bundle
)
1573 as_bad (_("directives are not valid inside bundles"));
1575 if (is_it_end_of_statement ())
1577 demand_empty_rest_of_line ();
1584 if (exp
.X_op
== O_symbol
1585 && *input_line_pointer
== '@'
1586 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1589 reloc_howto_type
*reloc_howto
=
1590 bfd_reloc_type_lookup (stdoutput
, reloc
);
1592 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1593 as_bad (_("unsupported relocation"));
1594 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1595 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1596 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1597 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1598 as_bad (_("opcode-specific %s relocation used outside "
1599 "an instruction"), reloc_howto
->name
);
1600 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1601 as_bad (_("%s relocations do not fit in %d bytes"),
1602 reloc_howto
->name
, nbytes
);
1605 char *p
= frag_more ((int) nbytes
);
1606 xtensa_set_frag_assembly_state (frag_now
);
1607 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1608 nbytes
, &exp
, 0, reloc
);
1612 emit_expr (&exp
, (unsigned int) nbytes
);
1614 while (*input_line_pointer
++ == ',');
1616 input_line_pointer
--; /* Put terminator back into stream. */
1617 demand_empty_rest_of_line ();
1621 /* Parsing and Idiom Translation. */
1623 /* Parse @plt, etc. and return the desired relocation. */
1624 static bfd_reloc_code_real_type
1625 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1631 bfd_reloc_code_real_type reloc
;
1639 struct map_bfd
*ptr
;
1641 #define MAP(str,reloc) { str, sizeof (str) - 1, reloc }
1643 static struct map_bfd mapping
[] =
1645 MAP ("l", BFD_RELOC_LO16
),
1646 MAP ("h", BFD_RELOC_HI16
),
1647 MAP ("plt", BFD_RELOC_XTENSA_PLT
),
1648 { (char *) 0, 0, BFD_RELOC_UNUSED
}
1652 return BFD_RELOC_NONE
;
1654 for (ch
= *str
, str2
= ident
;
1655 (str2
< ident
+ sizeof (ident
) - 1
1656 && (ISALNUM (ch
) || ch
== '@'));
1659 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1666 for (ptr
= &mapping
[0]; ptr
->length
> 0; ptr
++)
1667 if (ch
== ptr
->string
[0]
1668 && len
== ptr
->length
1669 && memcmp (ident
, ptr
->string
, ptr
->length
) == 0)
1671 /* Now check for "identifier@suffix+constant". */
1672 if (*str
== '-' || *str
== '+')
1674 char *orig_line
= input_line_pointer
;
1675 expressionS new_exp
;
1677 input_line_pointer
= str
;
1678 expression (&new_exp
);
1679 if (new_exp
.X_op
== O_constant
)
1681 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1682 str
= input_line_pointer
;
1685 if (&input_line_pointer
!= str_p
)
1686 input_line_pointer
= orig_line
;
1693 return BFD_RELOC_UNUSED
;
1698 expression_end (const char *name
)
1721 #define ERROR_REG_NUM ((unsigned) -1)
1724 tc_get_register (const char *prefix
)
1727 const char *next_expr
;
1728 const char *old_line_pointer
;
1731 old_line_pointer
= input_line_pointer
;
1733 if (*input_line_pointer
== '$')
1734 ++input_line_pointer
;
1736 /* Accept "sp" as a synonym for "a1". */
1737 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1738 && expression_end (input_line_pointer
+ 2))
1740 input_line_pointer
+= 2;
1741 return 1; /* AR[1] */
1744 while (*input_line_pointer
++ == *prefix
++)
1746 --input_line_pointer
;
1751 as_bad (_("bad register name: %s"), old_line_pointer
);
1752 return ERROR_REG_NUM
;
1755 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1757 as_bad (_("bad register number: %s"), input_line_pointer
);
1758 return ERROR_REG_NUM
;
1763 while (ISDIGIT ((int) *input_line_pointer
))
1764 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1766 if (!(next_expr
= expression_end (input_line_pointer
)))
1768 as_bad (_("bad register name: %s"), old_line_pointer
);
1769 return ERROR_REG_NUM
;
1772 input_line_pointer
= (char *) next_expr
;
1779 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1781 xtensa_isa isa
= xtensa_default_isa
;
1783 /* Check if this is an immediate operand. */
1784 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1786 bfd_reloc_code_real_type reloc
;
1787 segT t
= expression (tok
);
1788 if (t
== absolute_section
1789 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1791 assert (tok
->X_op
== O_constant
);
1792 tok
->X_op
= O_symbol
;
1793 tok
->X_add_symbol
= &abs_symbol
;
1796 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1797 && (reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1798 && (reloc
!= BFD_RELOC_NONE
))
1803 case BFD_RELOC_UNUSED
:
1804 as_bad (_("unsupported relocation"));
1807 case BFD_RELOC_XTENSA_PLT
:
1808 tok
->X_op
= O_pltrel
;
1811 case BFD_RELOC_LO16
:
1812 if (tok
->X_op
== O_constant
)
1813 tok
->X_add_number
&= 0xffff;
1818 case BFD_RELOC_HI16
:
1819 if (tok
->X_op
== O_constant
)
1820 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1829 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1830 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1832 if (reg
!= ERROR_REG_NUM
) /* Already errored */
1835 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
1836 as_bad (_("register number out of range"));
1839 tok
->X_op
= O_register
;
1840 tok
->X_add_symbol
= 0;
1841 tok
->X_add_number
= reg
;
1846 /* Split up the arguments for an opcode or pseudo-op. */
1849 tokenize_arguments (char **args
, char *str
)
1851 char *old_input_line_pointer
;
1852 bfd_boolean saw_comma
= FALSE
;
1853 bfd_boolean saw_arg
= FALSE
;
1854 bfd_boolean saw_colon
= FALSE
;
1856 char *arg_end
, *arg
;
1859 /* Save and restore input_line_pointer around this function. */
1860 old_input_line_pointer
= input_line_pointer
;
1861 input_line_pointer
= str
;
1863 while (*input_line_pointer
)
1866 switch (*input_line_pointer
)
1873 input_line_pointer
++;
1874 if (saw_comma
|| saw_colon
|| !saw_arg
)
1880 input_line_pointer
++;
1881 if (saw_comma
|| saw_colon
|| !saw_arg
)
1887 if (!saw_comma
&& !saw_colon
&& saw_arg
)
1890 arg_end
= input_line_pointer
+ 1;
1891 while (!expression_end (arg_end
))
1894 arg_len
= arg_end
- input_line_pointer
;
1895 arg
= (char *) xmalloc ((saw_colon
? 1 : 0) + arg_len
+ 1);
1896 args
[num_args
] = arg
;
1900 strncpy (arg
, input_line_pointer
, arg_len
);
1901 arg
[arg_len
] = '\0';
1903 input_line_pointer
= arg_end
;
1913 if (saw_comma
|| saw_colon
)
1915 input_line_pointer
= old_input_line_pointer
;
1920 as_bad (_("extra comma"));
1922 as_bad (_("extra colon"));
1924 as_bad (_("missing argument"));
1926 as_bad (_("missing comma or colon"));
1927 input_line_pointer
= old_input_line_pointer
;
1932 /* Parse the arguments to an opcode. Return TRUE on error. */
1935 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
1937 expressionS
*tok
, *last_tok
;
1938 xtensa_opcode opcode
= insn
->opcode
;
1939 bfd_boolean had_error
= TRUE
;
1940 xtensa_isa isa
= xtensa_default_isa
;
1941 int n
, num_regs
= 0;
1942 int opcode_operand_count
;
1943 int opnd_cnt
, last_opnd_cnt
;
1944 unsigned int next_reg
= 0;
1945 char *old_input_line_pointer
;
1947 if (insn
->insn_type
== ITYPE_LITERAL
)
1948 opcode_operand_count
= 1;
1950 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
1953 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
1955 /* Save and restore input_line_pointer around this function. */
1956 old_input_line_pointer
= input_line_pointer
;
1962 /* Skip invisible operands. */
1963 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
1969 for (n
= 0; n
< num_args
; n
++)
1971 input_line_pointer
= arg_strings
[n
];
1972 if (*input_line_pointer
== ':')
1974 xtensa_regfile opnd_rf
;
1975 input_line_pointer
++;
1978 assert (opnd_cnt
> 0);
1980 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
1982 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
1983 as_warn (_("incorrect register number, ignoring"));
1988 if (opnd_cnt
>= opcode_operand_count
)
1990 as_warn (_("too many arguments"));
1993 assert (opnd_cnt
< MAX_INSN_ARGS
);
1995 expression_maybe_register (opcode
, opnd_cnt
, tok
);
1996 next_reg
= tok
->X_add_number
+ 1;
1998 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
2000 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
2002 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
2003 /* minus 1 because we are seeing one right now */
2009 last_opnd_cnt
= opnd_cnt
;
2016 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
2020 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
2023 insn
->ntok
= tok
- insn
->tok
;
2027 input_line_pointer
= old_input_line_pointer
;
2033 get_invisible_operands (TInsn
*insn
)
2035 xtensa_isa isa
= xtensa_default_isa
;
2036 static xtensa_insnbuf slotbuf
= NULL
;
2038 xtensa_opcode opc
= insn
->opcode
;
2039 int slot
, opnd
, fmt_found
;
2043 slotbuf
= xtensa_insnbuf_alloc (isa
);
2045 /* Find format/slot where this can be encoded. */
2048 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2050 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2052 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2058 if (fmt_found
) break;
2063 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2067 /* First encode all the visible operands
2068 (to deal with shared field operands). */
2069 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2071 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2072 && (insn
->tok
[opnd
].X_op
== O_register
2073 || insn
->tok
[opnd
].X_op
== O_constant
))
2075 val
= insn
->tok
[opnd
].X_add_number
;
2076 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2077 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2081 /* Then pull out the values for the invisible ones. */
2082 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2084 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2086 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2087 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2088 insn
->tok
[opnd
].X_add_number
= val
;
2089 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2090 insn
->tok
[opnd
].X_op
= O_register
;
2092 insn
->tok
[opnd
].X_op
= O_constant
;
2101 xg_reverse_shift_count (char **cnt_argp
)
2103 char *cnt_arg
, *new_arg
;
2104 cnt_arg
= *cnt_argp
;
2106 /* replace the argument with "31-(argument)" */
2107 new_arg
= (char *) xmalloc (strlen (cnt_arg
) + 6);
2108 sprintf (new_arg
, "31-(%s)", cnt_arg
);
2111 *cnt_argp
= new_arg
;
2115 /* If "arg" is a constant expression, return non-zero with the value
2119 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2122 char *save_ptr
= input_line_pointer
;
2124 input_line_pointer
= arg
;
2126 input_line_pointer
= save_ptr
;
2128 if (exp
.X_op
== O_constant
)
2130 *valp
= exp
.X_add_number
;
2139 xg_replace_opname (char **popname
, char *newop
)
2142 *popname
= (char *) xmalloc (strlen (newop
) + 1);
2143 strcpy (*popname
, newop
);
2148 xg_check_num_args (int *pnum_args
,
2153 int num_args
= *pnum_args
;
2155 if (num_args
< expected_num
)
2157 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2158 num_args
, opname
, expected_num
);
2162 if (num_args
> expected_num
)
2164 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2165 num_args
, opname
, expected_num
);
2166 while (num_args
-- > expected_num
)
2168 free (arg_strings
[num_args
]);
2169 arg_strings
[num_args
] = 0;
2171 *pnum_args
= expected_num
;
2179 /* If the register is not specified as part of the opcode,
2180 then get it from the operand and move it to the opcode. */
2183 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2185 xtensa_isa isa
= xtensa_default_isa
;
2187 char *opname
, *new_opname
;
2188 const char *sr_name
;
2189 int is_user
, is_write
;
2190 bfd_boolean has_underbar
= FALSE
;
2195 has_underbar
= TRUE
;
2198 is_user
= (opname
[1] == 'u');
2199 is_write
= (opname
[0] == 'w');
2201 /* Opname == [rw]ur or [rwx]sr... */
2203 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2206 /* Check if the argument is a symbolic register name. */
2207 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2208 /* Handle WSR to "INTSET" as a special case. */
2209 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2210 && !strcasecmp (arg_strings
[1], "intset"))
2211 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2212 if (sr
== XTENSA_UNDEFINED
2213 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2215 /* Maybe it's a register number.... */
2217 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2219 as_bad (_("invalid register '%s' for '%s' instruction"),
2220 arg_strings
[1], opname
);
2223 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2224 if (sr
== XTENSA_UNDEFINED
)
2226 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2227 (long) val
, opname
);
2232 /* Remove the last argument, which is now part of the opcode. */
2233 free (arg_strings
[1]);
2237 /* Translate the opcode. */
2238 sr_name
= xtensa_sysreg_name (isa
, sr
);
2239 /* Another special case for "WSR.INTSET".... */
2240 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2242 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2243 sprintf (new_opname
, "%s%s.%s", (has_underbar
? "_" : ""),
2246 *popname
= new_opname
;
2253 xtensa_translate_old_userreg_ops (char **popname
)
2255 xtensa_isa isa
= xtensa_default_isa
;
2257 char *opname
, *new_opname
;
2258 const char *sr_name
;
2259 bfd_boolean has_underbar
= FALSE
;
2262 if (opname
[0] == '_')
2264 has_underbar
= TRUE
;
2268 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2269 if (sr
!= XTENSA_UNDEFINED
)
2271 /* The new default name ("nnn") is different from the old default
2272 name ("URnnn"). The old default is handled below, and we don't
2273 want to recognize [RW]nnn, so do nothing if the name is the (new)
2275 static char namebuf
[10];
2276 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2277 if (strcmp (namebuf
, opname
+ 1) == 0)
2285 /* Only continue if the reg name is "URnnn". */
2286 if (opname
[1] != 'u' || opname
[2] != 'r')
2288 val
= strtoul (opname
+ 3, &end
, 10);
2292 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2293 if (sr
== XTENSA_UNDEFINED
)
2295 as_bad (_("invalid register number (%ld) for '%s'"),
2296 (long) val
, opname
);
2301 /* Translate the opcode. */
2302 sr_name
= xtensa_sysreg_name (isa
, sr
);
2303 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2304 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2305 opname
[0], sr_name
);
2307 *popname
= new_opname
;
2314 xtensa_translate_zero_immed (char *old_op
,
2324 assert (opname
[0] != '_');
2326 if (strcmp (opname
, old_op
) != 0)
2329 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2331 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2333 xg_replace_opname (popname
, new_op
);
2334 free (arg_strings
[1]);
2335 arg_strings
[1] = arg_strings
[2];
2344 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2345 Returns non-zero if an error was found. */
2348 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2350 char *opname
= *popname
;
2351 bfd_boolean has_underbar
= FALSE
;
2353 if (cur_vinsn
.inside_bundle
)
2358 has_underbar
= TRUE
;
2362 if (strcmp (opname
, "mov") == 0)
2364 if (use_transform () && !has_underbar
&& density_supported
)
2365 xg_replace_opname (popname
, "mov.n");
2368 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2370 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2371 arg_strings
[2] = (char *) xmalloc (strlen (arg_strings
[1]) + 1);
2372 strcpy (arg_strings
[2], arg_strings
[1]);
2378 if (strcmp (opname
, "bbsi.l") == 0)
2380 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2382 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2383 if (target_big_endian
)
2384 xg_reverse_shift_count (&arg_strings
[1]);
2388 if (strcmp (opname
, "bbci.l") == 0)
2390 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2392 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2393 if (target_big_endian
)
2394 xg_reverse_shift_count (&arg_strings
[1]);
2398 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
2399 && strcmp (opname
, "nop") == 0)
2401 if (use_transform () && !has_underbar
&& density_supported
)
2402 xg_replace_opname (popname
, "nop.n");
2405 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2407 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2408 arg_strings
[0] = (char *) xmalloc (3);
2409 arg_strings
[1] = (char *) xmalloc (3);
2410 arg_strings
[2] = (char *) xmalloc (3);
2411 strcpy (arg_strings
[0], "a1");
2412 strcpy (arg_strings
[1], "a1");
2413 strcpy (arg_strings
[2], "a1");
2419 /* Recognize [RW]UR and [RWX]SR. */
2420 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2421 && (opname
[1] == 'u' || opname
[1] == 's'))
2422 || (opname
[0] == 'x' && opname
[1] == 's'))
2424 && opname
[3] == '\0')
2425 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2427 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2428 [RW]<name> if <name> is the non-default name of a user register. */
2429 if ((opname
[0] == 'r' || opname
[0] == 'w')
2430 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2431 return xtensa_translate_old_userreg_ops (popname
);
2433 /* Relax branches that don't allow comparisons against an immediate value
2434 of zero to the corresponding branches with implicit zero immediates. */
2435 if (!has_underbar
&& use_transform ())
2437 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2438 pnum_args
, arg_strings
))
2441 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2442 pnum_args
, arg_strings
))
2445 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2446 pnum_args
, arg_strings
))
2449 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2450 pnum_args
, arg_strings
))
2458 /* Functions for dealing with the Xtensa ISA. */
2460 /* Currently the assembler only allows us to use a single target per
2461 fragment. Because of this, only one operand for a given
2462 instruction may be symbolic. If there is a PC-relative operand,
2463 the last one is chosen. Otherwise, the result is the number of the
2464 last immediate operand, and if there are none of those, we fail and
2468 get_relaxable_immed (xtensa_opcode opcode
)
2470 int last_immed
= -1;
2473 if (opcode
== XTENSA_UNDEFINED
)
2476 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2477 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2479 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2481 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2483 if (last_immed
== -1
2484 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2491 static xtensa_opcode
2492 get_opcode_from_buf (const char *buf
, int slot
)
2494 static xtensa_insnbuf insnbuf
= NULL
;
2495 static xtensa_insnbuf slotbuf
= NULL
;
2496 xtensa_isa isa
= xtensa_default_isa
;
2501 insnbuf
= xtensa_insnbuf_alloc (isa
);
2502 slotbuf
= xtensa_insnbuf_alloc (isa
);
2505 xtensa_insnbuf_from_chars (isa
, insnbuf
, (const unsigned char *) buf
, 0);
2506 fmt
= xtensa_format_decode (isa
, insnbuf
);
2507 if (fmt
== XTENSA_UNDEFINED
)
2508 return XTENSA_UNDEFINED
;
2510 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2511 return XTENSA_UNDEFINED
;
2513 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2514 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2518 #ifdef TENSILICA_DEBUG
2520 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2523 xtensa_print_insn_table (void)
2525 int num_opcodes
, num_operands
;
2526 xtensa_opcode opcode
;
2527 xtensa_isa isa
= xtensa_default_isa
;
2529 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2530 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2533 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2534 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2535 for (opn
= 0; opn
< num_operands
; opn
++)
2537 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2539 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2541 xtensa_regfile opnd_rf
=
2542 xtensa_operand_regfile (isa
, opcode
, opn
);
2543 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2545 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2546 fputs ("[lLr] ", stderr
);
2548 fputs ("i ", stderr
);
2550 fprintf (stderr
, "\n");
2556 print_vliw_insn (xtensa_insnbuf vbuf
)
2558 xtensa_isa isa
= xtensa_default_isa
;
2559 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2560 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2563 fprintf (stderr
, "format = %d\n", f
);
2565 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2567 xtensa_opcode opcode
;
2571 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2572 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2573 opname
= xtensa_opcode_name (isa
, opcode
);
2575 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2576 fprintf (stderr
, " operands = ");
2578 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2582 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2584 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2585 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2586 fprintf (stderr
, "%d ", val
);
2588 fprintf (stderr
, "\n");
2590 xtensa_insnbuf_free (isa
, sbuf
);
2593 #endif /* TENSILICA_DEBUG */
2597 is_direct_call_opcode (xtensa_opcode opcode
)
2599 xtensa_isa isa
= xtensa_default_isa
;
2600 int n
, num_operands
;
2602 if (xtensa_opcode_is_call (isa
, opcode
) == 0)
2605 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2606 for (n
= 0; n
< num_operands
; n
++)
2608 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2609 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2616 /* Convert from BFD relocation type code to slot and operand number.
2617 Returns non-zero on failure. */
2620 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2622 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2623 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2625 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2628 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2629 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2631 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2641 /* Convert from slot number to BFD relocation type code for the
2642 standard PC-relative relocations. Return BFD_RELOC_NONE on
2645 static bfd_reloc_code_real_type
2646 encode_reloc (int slot
)
2648 if (slot
< 0 || slot
> 14)
2649 return BFD_RELOC_NONE
;
2651 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2655 /* Convert from slot numbers to BFD relocation type code for the
2656 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2658 static bfd_reloc_code_real_type
2659 encode_alt_reloc (int slot
)
2661 if (slot
< 0 || slot
> 14)
2662 return BFD_RELOC_NONE
;
2664 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2669 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2672 xtensa_opcode opcode
,
2678 uint32 valbuf
= value
;
2680 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2682 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2684 as_bad_where ((char *) file
, line
,
2685 _("operand %d of '%s' has out of range value '%u'"),
2687 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2690 as_bad_where ((char *) file
, line
,
2691 _("operand %d of '%s' has invalid value '%u'"),
2693 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2698 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2704 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2707 xtensa_opcode opcode
,
2711 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2712 fmt
, slot
, slotbuf
, &val
);
2713 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2718 /* Checks for rules from xtensa-relax tables. */
2720 /* The routine xg_instruction_matches_option_term must return TRUE
2721 when a given option term is true. The meaning of all of the option
2722 terms is given interpretation by this function. This is needed when
2723 an option depends on the state of a directive, but there are no such
2724 options in use right now. */
2727 xg_instruction_matches_option_term (TInsn
*insn ATTRIBUTE_UNUSED
,
2728 const ReqOrOption
*option
)
2730 if (strcmp (option
->option_name
, "realnop") == 0
2731 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2733 /* These conditions were evaluated statically when building the
2734 relaxation table. There's no need to reevaluate them now. */
2739 as_fatal (_("internal error: unknown option name '%s'"),
2740 option
->option_name
);
2746 xg_instruction_matches_or_options (TInsn
*insn
,
2747 const ReqOrOptionList
*or_option
)
2749 const ReqOrOption
*option
;
2750 /* Must match each of the AND terms. */
2751 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2753 if (xg_instruction_matches_option_term (insn
, option
))
2761 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2763 const ReqOption
*req_options
;
2764 /* Must match each of the AND terms. */
2765 for (req_options
= options
;
2766 req_options
!= NULL
;
2767 req_options
= req_options
->next
)
2769 /* Must match one of the OR clauses. */
2770 if (!xg_instruction_matches_or_options (insn
,
2771 req_options
->or_option_terms
))
2778 /* Return the transition rule that matches or NULL if none matches. */
2781 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2783 PreconditionList
*condition_l
;
2785 if (rule
->opcode
!= insn
->opcode
)
2788 for (condition_l
= rule
->conditions
;
2789 condition_l
!= NULL
;
2790 condition_l
= condition_l
->next
)
2794 Precondition
*cond
= condition_l
->precond
;
2799 /* The expression must be the constant. */
2800 assert (cond
->op_num
< insn
->ntok
);
2801 exp1
= &insn
->tok
[cond
->op_num
];
2802 if (expr_is_const (exp1
))
2807 if (get_expr_const (exp1
) != cond
->op_data
)
2811 if (get_expr_const (exp1
) == cond
->op_data
)
2818 else if (expr_is_register (exp1
))
2823 if (get_expr_register (exp1
) != cond
->op_data
)
2827 if (get_expr_register (exp1
) == cond
->op_data
)
2839 assert (cond
->op_num
< insn
->ntok
);
2840 assert (cond
->op_data
< insn
->ntok
);
2841 exp1
= &insn
->tok
[cond
->op_num
];
2842 exp2
= &insn
->tok
[cond
->op_data
];
2847 if (!expr_is_equal (exp1
, exp2
))
2851 if (expr_is_equal (exp1
, exp2
))
2863 if (!xg_instruction_matches_options (insn
, rule
->options
))
2871 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
2873 bfd_boolean a_greater
= FALSE
;
2874 bfd_boolean b_greater
= FALSE
;
2876 ReqOptionList
*l_a
= a
->options
;
2877 ReqOptionList
*l_b
= b
->options
;
2879 /* We only care if they both are the same except for
2880 a const16 vs. an l32r. */
2882 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2884 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
2885 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
2886 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2888 if (l_or_a
->is_true
!= l_or_b
->is_true
)
2890 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
2892 /* This is the case we care about. */
2893 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
2894 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
2901 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
2902 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
2912 l_or_a
= l_or_a
->next
;
2913 l_or_b
= l_or_b
->next
;
2915 if (l_or_a
|| l_or_b
)
2924 /* Incomparable if the substitution was used differently in two cases. */
2925 if (a_greater
&& b_greater
)
2937 static TransitionRule
*
2938 xg_instruction_match (TInsn
*insn
)
2940 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
2942 assert (insn
->opcode
< table
->num_opcodes
);
2944 /* Walk through all of the possible transitions. */
2945 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2947 TransitionRule
*rule
= l
->rule
;
2948 if (xg_instruction_matches_rule (insn
, rule
))
2955 /* Various Other Internal Functions. */
2958 is_unique_insn_expansion (TransitionRule
*r
)
2960 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
2962 if (r
->to_instr
->typ
!= INSTR_INSTR
)
2968 /* Check if there is exactly one relaxation for INSN that converts it to
2969 another instruction of equal or larger size. If so, and if TARG is
2970 non-null, go ahead and generate the relaxed instruction into TARG. If
2971 NARROW_ONLY is true, then only consider relaxations that widen a narrow
2972 instruction, i.e., ignore relaxations that convert to an instruction of
2973 equal size. In some contexts where this function is used, only
2974 a single widening is allowed and the NARROW_ONLY argument is used to
2975 exclude cases like ADDI being "widened" to an ADDMI, which may
2976 later be relaxed to an ADDMI/ADDI pair. */
2979 xg_is_single_relaxable_insn (TInsn
*insn
, TInsn
*targ
, bfd_boolean narrow_only
)
2981 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
2983 TransitionRule
*match
= 0;
2985 assert (insn
->insn_type
== ITYPE_INSN
);
2986 assert (insn
->opcode
< table
->num_opcodes
);
2988 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2990 TransitionRule
*rule
= l
->rule
;
2992 if (xg_instruction_matches_rule (insn
, rule
)
2993 && is_unique_insn_expansion (rule
)
2994 && (xg_get_single_size (insn
->opcode
) + (narrow_only
? 1 : 0)
2995 <= xg_get_single_size (rule
->to_instr
->opcode
)))
3006 xg_build_to_insn (targ
, insn
, match
->to_instr
);
3011 /* Return the maximum number of bytes this opcode can expand to. */
3014 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
3016 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3018 int max_size
= xg_get_single_size (opcode
);
3020 assert (opcode
< table
->num_opcodes
);
3022 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3024 TransitionRule
*rule
= l
->rule
;
3025 BuildInstr
*build_list
;
3030 build_list
= rule
->to_instr
;
3031 if (is_unique_insn_expansion (rule
))
3033 assert (build_list
->typ
== INSTR_INSTR
);
3034 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
3037 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3039 switch (build_list
->typ
)
3042 this_size
+= xg_get_single_size (build_list
->opcode
);
3044 case INSTR_LITERAL_DEF
:
3045 case INSTR_LABEL_DEF
:
3050 if (this_size
> max_size
)
3051 max_size
= this_size
;
3057 /* Return the maximum number of literal bytes this opcode can generate. */
3060 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3062 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3066 assert (opcode
< table
->num_opcodes
);
3068 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3070 TransitionRule
*rule
= l
->rule
;
3071 BuildInstr
*build_list
;
3076 build_list
= rule
->to_instr
;
3077 if (is_unique_insn_expansion (rule
))
3079 assert (build_list
->typ
== INSTR_INSTR
);
3080 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3083 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3085 switch (build_list
->typ
)
3087 case INSTR_LITERAL_DEF
:
3088 /* Hard-coded 4-byte literal. */
3092 case INSTR_LABEL_DEF
:
3097 if (this_size
> max_size
)
3098 max_size
= this_size
;
3105 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3107 int steps_taken
= 0;
3108 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3111 assert (insn
->insn_type
== ITYPE_INSN
);
3112 assert (insn
->opcode
< table
->num_opcodes
);
3114 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3116 TransitionRule
*rule
= l
->rule
;
3118 if (xg_instruction_matches_rule (insn
, rule
))
3120 if (steps_taken
== lateral_steps
)
3130 get_special_literal_symbol (void)
3132 static symbolS
*sym
= NULL
;
3135 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3141 get_special_label_symbol (void)
3143 static symbolS
*sym
= NULL
;
3146 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3152 xg_valid_literal_expression (const expressionS
*exp
)
3169 /* This will check to see if the value can be converted into the
3170 operand type. It will return TRUE if it does not fit. */
3173 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3175 uint32 valbuf
= value
;
3176 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3182 /* Assumes: All immeds are constants. Check that all constants fit
3183 into their immeds; return FALSE if not. */
3186 xg_immeds_fit (const TInsn
*insn
)
3188 xtensa_isa isa
= xtensa_default_isa
;
3192 assert (insn
->insn_type
== ITYPE_INSN
);
3193 for (i
= 0; i
< n
; ++i
)
3195 const expressionS
*expr
= &insn
->tok
[i
];
3196 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3203 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3208 /* The symbol should have a fixup associated with it. */
3217 /* This should only be called after we have an initial
3218 estimate of the addresses. */
3221 xg_symbolic_immeds_fit (const TInsn
*insn
,
3227 xtensa_isa isa
= xtensa_default_isa
;
3235 assert (insn
->insn_type
== ITYPE_INSN
);
3237 for (i
= 0; i
< n
; ++i
)
3239 const expressionS
*expr
= &insn
->tok
[i
];
3240 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3247 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3253 /* Check for the worst case. */
3254 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3259 /* We only allow symbols for PC-relative references.
3260 If pc_frag == 0, then we don't have frag locations yet. */
3262 || xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0)
3265 /* If it is a weak symbol, then assume it won't reach. */
3266 if (S_IS_WEAK (expr
->X_add_symbol
))
3269 if (is_direct_call_opcode (insn
->opcode
)
3270 && ! pc_frag
->tc_frag_data
.use_longcalls
)
3272 /* If callee is undefined or in a different segment, be
3273 optimistic and assume it will be in range. */
3274 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3278 /* Only references within a segment can be known to fit in the
3279 operands at assembly time. */
3280 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3283 symbolP
= expr
->X_add_symbol
;
3284 sym_frag
= symbol_get_frag (symbolP
);
3285 target
= S_GET_VALUE (symbolP
) + expr
->X_add_number
;
3286 pc
= pc_frag
->fr_address
+ pc_offset
;
3288 /* If frag has yet to be reached on this pass, assume it
3289 will move by STRETCH just as we did. If this is not so,
3290 it will be because some frag between grows, and that will
3291 force another pass. Beware zero-length frags. There
3292 should be a faster way to do this. */
3295 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3296 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3301 new_offset
= target
;
3302 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3303 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3308 /* The symbol should have a fixup associated with it. */
3317 /* Return TRUE on success. */
3320 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3325 memset (targ
, 0, sizeof (TInsn
));
3326 targ
->linenum
= insn
->linenum
;
3331 targ
->opcode
= bi
->opcode
;
3332 targ
->insn_type
= ITYPE_INSN
;
3333 targ
->is_specific_opcode
= FALSE
;
3335 for (; op
!= NULL
; op
= op
->next
)
3337 int op_num
= op
->op_num
;
3338 int op_data
= op
->op_data
;
3340 assert (op
->op_num
< MAX_INSN_ARGS
);
3342 if (targ
->ntok
<= op_num
)
3343 targ
->ntok
= op_num
+ 1;
3348 set_expr_const (&targ
->tok
[op_num
], op_data
);
3351 assert (op_data
< insn
->ntok
);
3352 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3355 sym
= get_special_literal_symbol ();
3356 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3359 sym
= get_special_label_symbol ();
3360 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3362 case OP_OPERAND_HI16U
:
3363 case OP_OPERAND_LOW16U
:
3364 assert (op_data
< insn
->ntok
);
3365 if (expr_is_const (&insn
->tok
[op_data
]))
3368 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3369 val
= xg_apply_userdef_op_fn (op
->typ
,
3372 targ
->tok
[op_num
].X_add_number
= val
;
3376 /* For const16 we can create relocations for these. */
3377 if (targ
->opcode
== XTENSA_UNDEFINED
3378 || (targ
->opcode
!= xtensa_const16_opcode
))
3380 assert (op_data
< insn
->ntok
);
3381 /* Need to build a O_lo16 or O_hi16. */
3382 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3383 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3385 if (op
->typ
== OP_OPERAND_HI16U
)
3386 targ
->tok
[op_num
].X_op
= O_hi16
;
3387 else if (op
->typ
== OP_OPERAND_LOW16U
)
3388 targ
->tok
[op_num
].X_op
= O_lo16
;
3395 /* currently handles:
3398 OP_OPERAND_F32MINUS */
3399 if (xg_has_userdef_op_fn (op
->typ
))
3401 assert (op_data
< insn
->ntok
);
3402 if (expr_is_const (&insn
->tok
[op_data
]))
3405 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3406 val
= xg_apply_userdef_op_fn (op
->typ
,
3409 targ
->tok
[op_num
].X_add_number
= val
;
3412 return FALSE
; /* We cannot use a relocation for this. */
3421 case INSTR_LITERAL_DEF
:
3423 targ
->opcode
= XTENSA_UNDEFINED
;
3424 targ
->insn_type
= ITYPE_LITERAL
;
3425 targ
->is_specific_opcode
= FALSE
;
3426 for (; op
!= NULL
; op
= op
->next
)
3428 int op_num
= op
->op_num
;
3429 int op_data
= op
->op_data
;
3430 assert (op
->op_num
< MAX_INSN_ARGS
);
3432 if (targ
->ntok
<= op_num
)
3433 targ
->ntok
= op_num
+ 1;
3438 assert (op_data
< insn
->ntok
);
3439 /* We can only pass resolvable literals through. */
3440 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3442 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3454 case INSTR_LABEL_DEF
:
3456 targ
->opcode
= XTENSA_UNDEFINED
;
3457 targ
->insn_type
= ITYPE_LABEL
;
3458 targ
->is_specific_opcode
= FALSE
;
3459 /* Literal with no ops is a label? */
3460 assert (op
== NULL
);
3471 /* Return TRUE on success. */
3474 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3476 for (; bi
!= NULL
; bi
= bi
->next
)
3478 TInsn
*next_insn
= istack_push_space (istack
);
3480 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3487 /* Return TRUE on valid expansion. */
3490 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3492 int stack_size
= istack
->ninsn
;
3493 int steps_taken
= 0;
3494 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3497 assert (insn
->insn_type
== ITYPE_INSN
);
3498 assert (insn
->opcode
< table
->num_opcodes
);
3500 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3502 TransitionRule
*rule
= l
->rule
;
3504 if (xg_instruction_matches_rule (insn
, rule
))
3506 if (lateral_steps
== steps_taken
)
3510 /* This is it. Expand the rule to the stack. */
3511 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3514 /* Check to see if it fits. */
3515 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3517 TInsn
*insn
= &istack
->insn
[i
];
3519 if (insn
->insn_type
== ITYPE_INSN
3520 && !tinsn_has_symbolic_operands (insn
)
3521 && !xg_immeds_fit (insn
))
3523 istack
->ninsn
= stack_size
;
3536 /* Relax the assembly instruction at least "min_steps".
3537 Return the number of steps taken. */
3540 xg_assembly_relax (IStack
*istack
,
3543 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3544 offsetT pc_offset
, /* offset in fragment */
3545 int min_steps
, /* minimum conversion steps */
3546 long stretch
) /* number of bytes stretched so far */
3548 int steps_taken
= 0;
3550 /* assert (has no symbolic operands)
3551 Some of its immeds don't fit.
3552 Try to build a relaxed version.
3553 This may go through a couple of stages
3554 of single instruction transformations before
3557 TInsn single_target
;
3559 int lateral_steps
= 0;
3560 int istack_size
= istack
->ninsn
;
3562 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3563 && steps_taken
>= min_steps
)
3565 istack_push (istack
, insn
);
3568 current_insn
= *insn
;
3570 /* Walk through all of the single instruction expansions. */
3571 while (xg_is_single_relaxable_insn (¤t_insn
, &single_target
, FALSE
))
3573 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3577 if (steps_taken
>= min_steps
)
3579 istack_push (istack
, &single_target
);
3583 current_insn
= single_target
;
3586 /* Now check for a multi-instruction expansion. */
3587 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3589 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3592 if (steps_taken
>= min_steps
)
3594 istack_push (istack
, ¤t_insn
);
3599 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3601 if (steps_taken
>= min_steps
)
3605 istack
->ninsn
= istack_size
;
3608 /* It's not going to work -- use the original. */
3609 istack_push (istack
, insn
);
3615 xg_force_frag_space (int size
)
3617 /* This may have the side effect of creating a new fragment for the
3618 space to go into. I just do not like the name of the "frag"
3625 xg_finish_frag (char *last_insn
,
3626 enum xtensa_relax_statesE frag_state
,
3627 enum xtensa_relax_statesE slot0_state
,
3629 bfd_boolean is_insn
)
3631 /* Finish off this fragment so that it has at LEAST the desired
3632 max_growth. If it doesn't fit in this fragment, close this one
3633 and start a new one. In either case, return a pointer to the
3634 beginning of the growth area. */
3638 xg_force_frag_space (max_growth
);
3640 old_frag
= frag_now
;
3642 frag_now
->fr_opcode
= last_insn
;
3644 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3646 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3647 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3649 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3650 xtensa_set_frag_assembly_state (frag_now
);
3652 /* Just to make sure that we did not split it up. */
3653 assert (old_frag
->fr_next
== frag_now
);
3657 /* Return TRUE if the target frag is one of the next non-empty frags. */
3660 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3665 for (; fragP
; fragP
= fragP
->fr_next
)
3667 if (fragP
== target
)
3669 if (fragP
->fr_fix
!= 0)
3671 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3673 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3674 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3676 if (fragP
->fr_type
== rs_space
)
3684 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3686 xtensa_isa isa
= xtensa_default_isa
;
3688 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3693 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 0
3694 && xtensa_opcode_is_jump (isa
, insn
->opcode
) == 0)
3697 for (i
= 0; i
< num_ops
; i
++)
3699 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3705 if (target_op
== -1)
3708 if (insn
->ntok
<= target_op
)
3711 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3714 sym
= insn
->tok
[target_op
].X_add_symbol
;
3718 if (insn
->tok
[target_op
].X_add_number
!= 0)
3721 target_frag
= symbol_get_frag (sym
);
3722 if (target_frag
== NULL
)
3725 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3726 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3734 xg_add_branch_and_loop_targets (TInsn
*insn
)
3736 xtensa_isa isa
= xtensa_default_isa
;
3737 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3739 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3742 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3743 && insn
->tok
[i
].X_op
== O_symbol
)
3744 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3748 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3749 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3753 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3755 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3756 && insn
->tok
[i
].X_op
== O_symbol
)
3758 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3759 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3760 if (S_IS_DEFINED (sym
))
3761 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3768 /* Return FALSE if no error. */
3771 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3776 switch (instr_spec
->typ
)
3779 new_insn
->insn_type
= ITYPE_INSN
;
3780 new_insn
->opcode
= instr_spec
->opcode
;
3781 new_insn
->is_specific_opcode
= FALSE
;
3782 new_insn
->linenum
= old_insn
->linenum
;
3784 case INSTR_LITERAL_DEF
:
3785 new_insn
->insn_type
= ITYPE_LITERAL
;
3786 new_insn
->opcode
= XTENSA_UNDEFINED
;
3787 new_insn
->is_specific_opcode
= FALSE
;
3788 new_insn
->linenum
= old_insn
->linenum
;
3790 case INSTR_LABEL_DEF
:
3791 as_bad (_("INSTR_LABEL_DEF not supported yet"));
3795 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3798 const expressionS
*src_exp
;
3804 /* The expression must be the constant. */
3805 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3806 exp
= &new_insn
->tok
[b_op
->op_num
];
3807 set_expr_const (exp
, b_op
->op_data
);
3811 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3812 assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
3813 src_exp
= &old_insn
->tok
[b_op
->op_data
];
3814 exp
= &new_insn
->tok
[b_op
->op_num
];
3815 copy_expr (exp
, src_exp
);
3820 as_bad (_("can't handle generation of literal/labels yet"));
3824 as_bad (_("can't handle undefined OP TYPE"));
3829 new_insn
->ntok
= num_ops
;
3834 /* Return TRUE if it was simplified. */
3837 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
3839 TransitionRule
*rule
;
3840 BuildInstr
*insn_spec
;
3842 if (old_insn
->is_specific_opcode
|| !density_supported
)
3845 rule
= xg_instruction_match (old_insn
);
3849 insn_spec
= rule
->to_instr
;
3850 /* There should only be one. */
3851 assert (insn_spec
!= NULL
);
3852 assert (insn_spec
->next
== NULL
);
3853 if (insn_spec
->next
!= NULL
)
3856 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
3862 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3863 l32i.n. (2) Check the number of operands. (3) Place the instruction
3864 tokens into the stack or relax it and place multiple
3865 instructions/literals onto the stack. Return FALSE if no error. */
3868 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
3872 bfd_boolean do_expand
;
3874 memset (&new_insn
, 0, sizeof (TInsn
));
3876 /* Narrow it if we can. xg_simplify_insn now does all the
3877 appropriate checking (e.g., for the density option). */
3878 if (xg_simplify_insn (orig_insn
, &new_insn
))
3879 orig_insn
= &new_insn
;
3881 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
3883 if (orig_insn
->ntok
< noperands
)
3885 as_bad (_("found %d operands for '%s': Expected %d"),
3887 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3891 if (orig_insn
->ntok
> noperands
)
3892 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
3894 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3897 /* If there are not enough operands, we will assert above. If there
3898 are too many, just cut out the extras here. */
3899 orig_insn
->ntok
= noperands
;
3901 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
3904 /* If the instruction will definitely need to be relaxed, it is better
3905 to expand it now for better scheduling. Decide whether to expand
3907 do_expand
= (!orig_insn
->is_specific_opcode
&& use_transform ());
3909 /* Calls should be expanded to longcalls only in the backend relaxation
3910 so that the assembly scheduler will keep the L32R/CALLX instructions
3912 if (is_direct_call_opcode (orig_insn
->opcode
))
3915 if (tinsn_has_symbolic_operands (orig_insn
))
3917 /* The values of symbolic operands are not known yet, so only expand
3918 now if an operand is "complex" (e.g., difference of symbols) and
3919 will have to be stored as a literal regardless of the value. */
3920 if (!tinsn_has_complex_operands (orig_insn
))
3923 else if (xg_immeds_fit (orig_insn
))
3927 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
3929 istack_push (istack
, orig_insn
);
3935 /* Return TRUE if the section flags are marked linkonce
3936 or the name is .gnu.linkonce*. */
3939 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
3941 flagword flags
, link_once_flags
;
3943 flags
= bfd_get_section_flags (abfd
, sec
);
3944 link_once_flags
= (flags
& SEC_LINK_ONCE
);
3946 /* Flags might not be set yet. */
3947 if (!link_once_flags
)
3949 static size_t len
= sizeof ".gnu.linkonce.t.";
3951 if (strncmp (segment_name (sec
), ".gnu.linkonce.t.", len
- 1) == 0)
3952 link_once_flags
= SEC_LINK_ONCE
;
3954 return (link_once_flags
!= 0);
3959 xtensa_add_literal_sym (symbolS
*sym
)
3963 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
3965 l
->next
= literal_syms
;
3971 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
3973 static int lit_num
= 0;
3974 static char name
[256];
3977 sprintf (name
, ".L_lit_sym%d", lit_num
);
3979 /* Create a local symbol. If it is in a linkonce section, we have to
3980 be careful to make sure that if it is used in a relocation that the
3981 symbol will be in the output file. */
3982 if (get_is_linkonce_section (stdoutput
, sec
))
3984 symbolP
= symbol_new (name
, sec
, 0, frag
);
3985 S_CLEAR_EXTERNAL (symbolP
);
3986 /* symbolP->local = 1; */
3989 symbolP
= symbol_new (name
, sec
, 0, frag
);
3991 xtensa_add_literal_sym (symbolP
);
3993 frag
->tc_frag_data
.is_literal
= TRUE
;
3999 /* Currently all literals that are generated here are 32-bit L32R targets. */
4002 xg_assemble_literal (/* const */ TInsn
*insn
)
4005 symbolS
*lit_sym
= NULL
;
4007 /* size = 4 for L32R. It could easily be larger when we move to
4008 larger constants. Add a parameter later. */
4009 offsetT litsize
= 4;
4010 offsetT litalign
= 2; /* 2^2 = 4 */
4011 expressionS saved_loc
;
4012 expressionS
* emit_val
;
4014 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
4016 assert (insn
->insn_type
== ITYPE_LITERAL
);
4017 assert (insn
->ntok
== 1); /* must be only one token here */
4019 xtensa_switch_to_literal_fragment (&state
);
4021 emit_val
= &insn
->tok
[0];
4022 if (emit_val
->X_op
== O_big
)
4024 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
4027 /* This happens when someone writes a "movi a2, big_number". */
4028 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4029 _("invalid immediate"));
4030 xtensa_restore_emit_state (&state
);
4035 /* Force a 4-byte align here. Note that this opens a new frag, so all
4036 literals done with this function have a frag to themselves. That's
4037 important for the way text section literals work. */
4038 frag_align (litalign
, 0, 0);
4039 record_alignment (now_seg
, litalign
);
4041 if (emit_val
->X_op
== O_pltrel
)
4043 char *p
= frag_more (litsize
);
4044 xtensa_set_frag_assembly_state (frag_now
);
4045 if (emit_val
->X_add_symbol
)
4046 emit_val
->X_op
= O_symbol
;
4048 emit_val
->X_op
= O_constant
;
4049 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
4050 litsize
, emit_val
, 0, BFD_RELOC_XTENSA_PLT
);
4053 emit_expr (emit_val
, litsize
);
4055 assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
4056 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4057 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4058 lit_sym
= frag_now
->fr_symbol
;
4059 frag_now
->tc_frag_data
.is_literal
= TRUE
;
4062 xtensa_restore_emit_state (&state
);
4068 xg_assemble_literal_space (/* const */ int size
, int slot
)
4071 /* We might have to do something about this alignment. It only
4072 takes effect if something is placed here. */
4073 offsetT litalign
= 2; /* 2^2 = 4 */
4074 fragS
*lit_saved_frag
;
4076 assert (size
% 4 == 0);
4078 xtensa_switch_to_literal_fragment (&state
);
4080 /* Force a 4-byte align here. */
4081 frag_align (litalign
, 0, 0);
4082 record_alignment (now_seg
, litalign
);
4084 xg_force_frag_space (size
);
4086 lit_saved_frag
= frag_now
;
4087 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4088 frag_now
->tc_frag_data
.is_literal
= TRUE
;
4089 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4090 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4093 xtensa_restore_emit_state (&state
);
4094 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4098 /* Put in a fixup record based on the opcode.
4099 Return TRUE on success. */
4102 xg_add_opcode_fix (TInsn
*tinsn
,
4110 xtensa_opcode opcode
= tinsn
->opcode
;
4111 bfd_reloc_code_real_type reloc
;
4112 reloc_howto_type
*howto
;
4116 reloc
= BFD_RELOC_NONE
;
4118 /* First try the special cases for "alternate" relocs. */
4119 if (opcode
== xtensa_l32r_opcode
)
4121 if (fragP
->tc_frag_data
.use_absolute_literals
)
4122 reloc
= encode_alt_reloc (slot
);
4124 else if (opcode
== xtensa_const16_opcode
)
4126 if (expr
->X_op
== O_lo16
)
4128 reloc
= encode_reloc (slot
);
4129 expr
->X_op
= O_symbol
;
4131 else if (expr
->X_op
== O_hi16
)
4133 reloc
= encode_alt_reloc (slot
);
4134 expr
->X_op
= O_symbol
;
4138 if (opnum
!= get_relaxable_immed (opcode
))
4140 as_bad (_("invalid relocation for operand %i of '%s'"),
4141 opnum
, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4145 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4146 into the symbol table where the generic portions of the assembler
4147 won't know what to do with them. */
4148 if (expr
->X_op
== O_lo16
|| expr
->X_op
== O_hi16
)
4150 as_bad (_("invalid expression for operand %i of '%s'"),
4151 opnum
, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4155 /* Next try the generic relocs. */
4156 if (reloc
== BFD_RELOC_NONE
)
4157 reloc
= encode_reloc (slot
);
4158 if (reloc
== BFD_RELOC_NONE
)
4160 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4164 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4167 as_bad (_("undefined symbol for opcode \"%s\""),
4168 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4172 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4173 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, expr
,
4174 howto
->pc_relative
, reloc
);
4175 the_fix
->fx_no_overflow
= 1;
4177 if (expr
->X_add_symbol
4178 && (S_IS_EXTERNAL (expr
->X_add_symbol
)
4179 || S_IS_WEAK (expr
->X_add_symbol
)))
4180 the_fix
->fx_plt
= TRUE
;
4182 the_fix
->tc_fix_data
.X_add_symbol
= expr
->X_add_symbol
;
4183 the_fix
->tc_fix_data
.X_add_number
= expr
->X_add_number
;
4184 the_fix
->tc_fix_data
.slot
= slot
;
4191 xg_emit_insn_to_buf (TInsn
*tinsn
,
4196 bfd_boolean build_fix
)
4198 static xtensa_insnbuf insnbuf
= NULL
;
4199 bfd_boolean has_symbolic_immed
= FALSE
;
4200 bfd_boolean ok
= TRUE
;
4202 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4204 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4205 if (has_symbolic_immed
&& build_fix
)
4208 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4209 expressionS
*exp
= &tinsn
->tok
[opnum
];
4211 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, 0, exp
, fragP
, offset
))
4214 fragP
->tc_frag_data
.is_insn
= TRUE
;
4215 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4216 (unsigned char *) buf
, 0);
4222 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4224 symbolS
*sym
= get_special_literal_symbol ();
4228 assert (insn
->insn_type
== ITYPE_INSN
);
4229 for (i
= 0; i
< insn
->ntok
; i
++)
4230 if (insn
->tok
[i
].X_add_symbol
== sym
)
4231 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4237 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4239 symbolS
*sym
= get_special_label_symbol ();
4241 /* assert (!insn->is_literal); */
4242 for (i
= 0; i
< insn
->ntok
; i
++)
4243 if (insn
->tok
[i
].X_add_symbol
== sym
)
4244 insn
->tok
[i
].X_add_symbol
= label_sym
;
4249 /* Return TRUE if the instruction can write to the specified
4250 integer register. */
4253 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4257 xtensa_isa isa
= xtensa_default_isa
;
4259 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4261 for (i
= 0; i
< num_ops
; i
++)
4264 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4265 if ((inout
== 'o' || inout
== 'm')
4266 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4268 xtensa_regfile opnd_rf
=
4269 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4270 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4272 if ((insn
->tok
[i
].X_op
== O_register
)
4273 && (insn
->tok
[i
].X_add_number
== regnum
))
4283 is_bad_loopend_opcode (const TInsn
*tinsn
)
4285 xtensa_opcode opcode
= tinsn
->opcode
;
4287 if (opcode
== XTENSA_UNDEFINED
)
4290 if (opcode
== xtensa_call0_opcode
4291 || opcode
== xtensa_callx0_opcode
4292 || opcode
== xtensa_call4_opcode
4293 || opcode
== xtensa_callx4_opcode
4294 || opcode
== xtensa_call8_opcode
4295 || opcode
== xtensa_callx8_opcode
4296 || opcode
== xtensa_call12_opcode
4297 || opcode
== xtensa_callx12_opcode
4298 || opcode
== xtensa_isync_opcode
4299 || opcode
== xtensa_ret_opcode
4300 || opcode
== xtensa_ret_n_opcode
4301 || opcode
== xtensa_retw_opcode
4302 || opcode
== xtensa_retw_n_opcode
4303 || opcode
== xtensa_waiti_opcode
4304 || opcode
== xtensa_rsr_lcount_opcode
)
4311 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4312 This allows the debugger to add unaligned labels.
4313 Also, the assembler generates stabs labels that need
4314 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4317 is_unaligned_label (symbolS
*sym
)
4319 const char *name
= S_GET_NAME (sym
);
4320 static size_t fake_size
= 0;
4324 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4327 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4329 fake_size
= strlen (FAKE_LABEL_NAME
);
4332 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4333 && (name
[fake_size
] == 'F'
4334 || name
[fake_size
] == 'L'
4335 || (name
[fake_size
] == 'e'
4336 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4344 next_non_empty_frag (const fragS
*fragP
)
4346 fragS
*next_fragP
= fragP
->fr_next
;
4348 /* Sometimes an empty will end up here due storage allocation issues.
4349 So we have to skip until we find something legit. */
4350 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4351 next_fragP
= next_fragP
->fr_next
;
4353 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4361 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4363 xtensa_opcode out_opcode
;
4364 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4366 if (next_fragP
== NULL
)
4369 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4370 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4372 *opcode
= out_opcode
;
4380 frag_format_size (const fragS
*fragP
)
4382 static xtensa_insnbuf insnbuf
= NULL
;
4383 xtensa_isa isa
= xtensa_default_isa
;
4388 insnbuf
= xtensa_insnbuf_alloc (isa
);
4391 return XTENSA_UNDEFINED
;
4393 xtensa_insnbuf_from_chars (isa
, insnbuf
,
4394 (unsigned char *) fragP
->fr_literal
, 0);
4396 fmt
= xtensa_format_decode (isa
, insnbuf
);
4397 if (fmt
== XTENSA_UNDEFINED
)
4398 return XTENSA_UNDEFINED
;
4399 fmt_size
= xtensa_format_length (isa
, fmt
);
4401 /* If the next format won't be changing due to relaxation, just
4402 return the length of the first format. */
4403 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4406 /* If during relaxation we have to pull an instruction out of a
4407 multi-slot instruction, we will return the more conservative
4408 number. This works because alignment on bigger instructions
4409 is more restrictive than alignment on smaller instructions.
4410 This is more conservative than we would like, but it happens
4413 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4416 /* If we aren't doing one of our own relaxations or it isn't
4417 slot-based, then the insn size won't change. */
4418 if (fragP
->fr_type
!= rs_machine_dependent
)
4420 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4423 /* If an instruction is about to grow, return the longer size. */
4424 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4425 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
)
4428 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4429 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4436 next_frag_format_size (const fragS
*fragP
)
4438 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4439 return frag_format_size (next_fragP
);
4443 /* If the next legit fragment is an end-of-loop marker,
4444 switch its state so it will instantiate a NOP. */
4447 update_next_frag_state (fragS
*fragP
)
4449 fragS
*next_fragP
= fragP
->fr_next
;
4450 fragS
*new_target
= NULL
;
4454 /* We are guaranteed there will be one of these... */
4455 while (!(next_fragP
->fr_type
== rs_machine_dependent
4456 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4457 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4458 next_fragP
= next_fragP
->fr_next
;
4460 assert (next_fragP
->fr_type
== rs_machine_dependent
4461 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4462 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4464 /* ...and one of these. */
4465 new_target
= next_fragP
->fr_next
;
4466 while (!(new_target
->fr_type
== rs_machine_dependent
4467 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4468 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4469 new_target
= new_target
->fr_next
;
4471 assert (new_target
->fr_type
== rs_machine_dependent
4472 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4473 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4476 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4478 if (next_fragP
->fr_type
== rs_machine_dependent
4479 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4481 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4485 next_fragP
= next_fragP
->fr_next
;
4491 next_frag_is_branch_target (const fragS
*fragP
)
4493 /* Sometimes an empty will end up here due to storage allocation issues,
4494 so we have to skip until we find something legit. */
4495 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4497 if (fragP
->tc_frag_data
.is_branch_target
)
4499 if (fragP
->fr_fix
!= 0)
4507 next_frag_is_loop_target (const fragS
*fragP
)
4509 /* Sometimes an empty will end up here due storage allocation issues.
4510 So we have to skip until we find something legit. */
4511 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4513 if (fragP
->tc_frag_data
.is_loop_target
)
4515 if (fragP
->fr_fix
!= 0)
4523 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4525 const fragS
*next_fragp
= fragp
->fr_next
;
4526 xtensa_opcode next_opcode
;
4528 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4531 /* Sometimes an empty will end up here due to storage allocation issues,
4532 so we have to skip until we find something legit. */
4533 while (next_fragp
->fr_fix
== 0)
4534 next_fragp
= next_fragp
->fr_next
;
4536 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4539 /* There is some implicit knowledge encoded in here.
4540 The LOOP instructions that are NOT RELAX_IMMED have
4541 been relaxed. Note that we can assume that the LOOP
4542 instruction is in slot 0 because loops aren't bundleable. */
4543 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4544 return get_expanded_loop_offset (next_opcode
);
4550 /* Mark a location where we can later insert literal frags. Update
4551 the section's literal_pool_loc, so subsequent literals can be
4552 placed nearest to their use. */
4555 xtensa_mark_literal_pool_location (void)
4557 /* Any labels pointing to the current location need
4558 to be adjusted to after the literal pool. */
4560 fragS
*pool_location
;
4562 if (use_literal_section
&& !directive_state
[directive_absolute_literals
])
4565 frag_align (2, 0, 0);
4566 record_alignment (now_seg
, 2);
4568 /* We stash info in these frags so we can later move the literal's
4569 fixes into this frchain's fix list. */
4570 pool_location
= frag_now
;
4571 frag_now
->tc_frag_data
.lit_frchain
= frchain_now
;
4572 frag_variant (rs_machine_dependent
, 0, 0,
4573 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4574 xtensa_set_frag_assembly_state (frag_now
);
4575 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
4576 frag_variant (rs_machine_dependent
, 0, 0,
4577 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4578 xtensa_set_frag_assembly_state (frag_now
);
4580 /* Now put a frag into the literal pool that points to this location. */
4581 set_literal_pool_location (now_seg
, pool_location
);
4582 xtensa_switch_to_non_abs_literal_fragment (&s
);
4583 frag_align (2, 0, 0);
4584 record_alignment (now_seg
, 2);
4586 /* Close whatever frag is there. */
4587 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4588 xtensa_set_frag_assembly_state (frag_now
);
4589 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
4590 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4591 xtensa_restore_emit_state (&s
);
4592 xtensa_set_frag_assembly_state (frag_now
);
4596 /* Build a nop of the correct size into tinsn. */
4599 build_nop (TInsn
*tinsn
, int size
)
4605 tinsn
->opcode
= xtensa_nop_n_opcode
;
4607 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4608 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4612 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4614 tinsn
->opcode
= xtensa_or_opcode
;
4615 set_expr_const (&tinsn
->tok
[0], 1);
4616 set_expr_const (&tinsn
->tok
[1], 1);
4617 set_expr_const (&tinsn
->tok
[2], 1);
4621 tinsn
->opcode
= xtensa_nop_opcode
;
4623 assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4628 /* Assemble a NOP of the requested size in the buffer. User must have
4629 allocated "buf" with at least "size" bytes. */
4632 assemble_nop (int size
, char *buf
)
4634 static xtensa_insnbuf insnbuf
= NULL
;
4637 build_nop (&tinsn
, size
);
4640 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4642 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4643 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4644 (unsigned char *) buf
, 0);
4648 /* Return the number of bytes for the offset of the expanded loop
4649 instruction. This should be incorporated into the relaxation
4650 specification but is hard-coded here. This is used to auto-align
4651 the loop instruction. It is invalid to call this function if the
4652 configuration does not have loops or if the opcode is not a loop
4656 get_expanded_loop_offset (xtensa_opcode opcode
)
4658 /* This is the OFFSET of the loop instruction in the expanded loop.
4659 This MUST correspond directly to the specification of the loop
4660 expansion. It will be validated on fragment conversion. */
4661 assert (opcode
!= XTENSA_UNDEFINED
);
4662 if (opcode
== xtensa_loop_opcode
)
4664 if (opcode
== xtensa_loopnez_opcode
)
4666 if (opcode
== xtensa_loopgtz_opcode
)
4668 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4674 get_literal_pool_location (segT seg
)
4676 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4681 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4683 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4687 /* Set frag assembly state should be called when a new frag is
4688 opened and after a frag has been closed. */
4691 xtensa_set_frag_assembly_state (fragS
*fragP
)
4693 if (!density_supported
)
4694 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4696 /* This function is called from subsegs_finish, which is called
4697 after xtensa_end, so we can't use "use_transform" or
4698 "use_schedule" here. */
4699 if (!directive_state
[directive_transform
])
4700 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4701 if (directive_state
[directive_longcalls
])
4702 fragP
->tc_frag_data
.use_longcalls
= TRUE
;
4703 fragP
->tc_frag_data
.use_absolute_literals
=
4704 directive_state
[directive_absolute_literals
];
4705 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4710 relaxable_section (asection
*sec
)
4712 return (sec
->flags
& SEC_DEBUGGING
) == 0;
4717 xtensa_find_unmarked_state_frags (void)
4721 /* Walk over each fragment of all of the current segments. For each
4722 unmarked fragment, mark it with the same info as the previous
4724 for (seclist
= &stdoutput
->sections
;
4725 seclist
&& *seclist
;
4726 seclist
= &(*seclist
)->next
)
4728 segT sec
= *seclist
;
4729 segment_info_type
*seginfo
;
4732 flags
= bfd_get_section_flags (stdoutput
, sec
);
4733 if (flags
& SEC_DEBUGGING
)
4735 if (!(flags
& SEC_ALLOC
))
4738 seginfo
= seg_info (sec
);
4739 if (seginfo
&& seginfo
->frchainP
)
4741 fragS
*last_fragP
= 0;
4742 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4743 fragP
= fragP
->fr_next
)
4745 if (fragP
->fr_fix
!= 0
4746 && !fragP
->tc_frag_data
.is_assembly_state_set
)
4748 if (last_fragP
== 0)
4750 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
4751 _("assembly state not set for first frag in section %s"),
4756 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4757 fragP
->tc_frag_data
.is_no_density
=
4758 last_fragP
->tc_frag_data
.is_no_density
;
4759 fragP
->tc_frag_data
.is_no_transform
=
4760 last_fragP
->tc_frag_data
.is_no_transform
;
4761 fragP
->tc_frag_data
.use_longcalls
=
4762 last_fragP
->tc_frag_data
.use_longcalls
;
4763 fragP
->tc_frag_data
.use_absolute_literals
=
4764 last_fragP
->tc_frag_data
.use_absolute_literals
;
4767 if (fragP
->tc_frag_data
.is_assembly_state_set
)
4776 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
4778 void *unused ATTRIBUTE_UNUSED
)
4780 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4781 segment_info_type
*seginfo
= seg_info (sec
);
4782 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4784 if (flags
& SEC_CODE
)
4786 xtensa_isa isa
= xtensa_default_isa
;
4787 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4788 while (frag
!= NULL
)
4790 if (frag
->tc_frag_data
.is_branch_target
)
4793 addressT branch_align
, frag_addr
;
4796 xtensa_insnbuf_from_chars
4797 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4798 fmt
= xtensa_format_decode (isa
, insnbuf
);
4799 op_size
= xtensa_format_length (isa
, fmt
);
4800 branch_align
= 1 << branch_align_power (sec
);
4801 frag_addr
= frag
->fr_address
% branch_align
;
4802 if (frag_addr
+ op_size
> branch_align
)
4803 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4804 _("unaligned branch target: %d bytes at 0x%lx"),
4805 op_size
, (long) frag
->fr_address
);
4807 frag
= frag
->fr_next
;
4809 xtensa_insnbuf_free (isa
, insnbuf
);
4815 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
4817 void *unused ATTRIBUTE_UNUSED
)
4819 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4820 segment_info_type
*seginfo
= seg_info (sec
);
4821 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4822 xtensa_isa isa
= xtensa_default_isa
;
4824 if (flags
& SEC_CODE
)
4826 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4827 while (frag
!= NULL
)
4829 if (frag
->tc_frag_data
.is_first_loop_insn
)
4835 xtensa_insnbuf_from_chars
4836 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4837 fmt
= xtensa_format_decode (isa
, insnbuf
);
4838 op_size
= xtensa_format_length (isa
, fmt
);
4839 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
4841 if (frag_addr
+ op_size
> xtensa_fetch_width
)
4842 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4843 _("unaligned loop: %d bytes at 0x%lx"),
4844 op_size
, (long) frag
->fr_address
);
4846 frag
= frag
->fr_next
;
4848 xtensa_insnbuf_free (isa
, insnbuf
);
4854 xg_apply_fix_value (fixS
*fixP
, valueT val
)
4856 xtensa_isa isa
= xtensa_default_isa
;
4857 static xtensa_insnbuf insnbuf
= NULL
;
4858 static xtensa_insnbuf slotbuf
= NULL
;
4861 bfd_boolean alt_reloc
;
4862 xtensa_opcode opcode
;
4863 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
4865 (void) decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
);
4867 as_fatal (_("unexpected fix"));
4871 insnbuf
= xtensa_insnbuf_alloc (isa
);
4872 slotbuf
= xtensa_insnbuf_alloc (isa
);
4875 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4876 fmt
= xtensa_format_decode (isa
, insnbuf
);
4877 if (fmt
== XTENSA_UNDEFINED
)
4878 as_fatal (_("undecodable fix"));
4879 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4880 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
4881 if (opcode
== XTENSA_UNDEFINED
)
4882 as_fatal (_("undecodable fix"));
4884 /* CONST16 immediates are not PC-relative, despite the fact that we
4885 reuse the normal PC-relative operand relocations for the low part
4886 of a CONST16 operand. */
4887 if (opcode
== xtensa_const16_opcode
)
4890 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
4891 get_relaxable_immed (opcode
), val
,
4892 fixP
->fx_file
, fixP
->fx_line
);
4894 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4895 xtensa_insnbuf_to_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4901 /* External Functions and Other GAS Hooks. */
4904 xtensa_target_format (void)
4906 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
4911 xtensa_file_arch_init (bfd
*abfd
)
4913 bfd_set_private_flags (abfd
, 0x100 | 0x200);
4918 md_number_to_chars (char *buf
, valueT val
, int n
)
4920 if (target_big_endian
)
4921 number_to_chars_bigendian (buf
, val
, n
);
4923 number_to_chars_littleendian (buf
, val
, n
);
4927 /* This function is called once, at assembler startup time. It should
4928 set up all the tables, etc. that the MD part of the assembler will
4934 segT current_section
= now_seg
;
4935 int current_subsec
= now_subseg
;
4938 xtensa_default_isa
= xtensa_isa_init (0, 0);
4939 isa
= xtensa_default_isa
;
4943 /* Set up the .literal, .fini.literal and .init.literal sections. */
4944 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
4945 default_lit_sections
.init_lit_seg_name
= INIT_LITERAL_SECTION_NAME
;
4946 default_lit_sections
.fini_lit_seg_name
= FINI_LITERAL_SECTION_NAME
;
4947 default_lit_sections
.lit_seg_name
= LITERAL_SECTION_NAME
;
4948 default_lit_sections
.lit4_seg_name
= LIT4_SECTION_NAME
;
4950 subseg_set (current_section
, current_subsec
);
4952 xg_init_vinsn (&cur_vinsn
);
4954 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
4955 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
4956 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
4957 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
4958 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
4959 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
4960 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
4961 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
4962 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
4963 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
4964 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
4965 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
4966 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
4967 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
4968 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
4969 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
4970 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
4971 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
4972 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
4973 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
4974 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
4975 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
4976 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
4977 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
4978 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
4979 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
4980 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
4981 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
4982 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
4984 init_op_placement_info_table ();
4986 /* Set up the assembly state. */
4987 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
4988 xtensa_set_frag_assembly_state (frag_now
);
4992 /* TC_INIT_FIX_DATA hook */
4995 xtensa_init_fix_data (fixS
*x
)
4997 x
->tc_fix_data
.slot
= 0;
4998 x
->tc_fix_data
.X_add_symbol
= NULL
;
4999 x
->tc_fix_data
.X_add_number
= 0;
5003 /* tc_frob_label hook */
5006 xtensa_frob_label (symbolS
*sym
)
5010 if (cur_vinsn
.inside_bundle
)
5012 as_bad (_("labels are not valid inside bundles"));
5016 freq
= get_subseg_target_freq (now_seg
, now_subseg
);
5018 /* Since the label was already attached to a frag associated with the
5019 previous basic block, it now needs to be reset to the current frag. */
5020 symbol_set_frag (sym
, frag_now
);
5021 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5023 if (generating_literals
)
5024 xtensa_add_literal_sym (sym
);
5026 xtensa_add_insn_label (sym
);
5028 if (symbol_get_tc (sym
)->is_loop_target
)
5030 if ((get_last_insn_flags (now_seg
, now_subseg
)
5031 & FLAG_IS_BAD_LOOPEND
) != 0)
5032 as_bad (_("invalid last instruction for a zero-overhead loop"));
5034 xtensa_set_frag_assembly_state (frag_now
);
5035 frag_var (rs_machine_dependent
, 4, 4, RELAX_LOOP_END
,
5036 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5038 xtensa_set_frag_assembly_state (frag_now
);
5039 xtensa_move_labels (frag_now
, 0, TRUE
);
5042 /* No target aligning in the absolute section. */
5043 if (now_seg
!= absolute_section
5044 && do_align_targets ()
5045 && !is_unaligned_label (sym
)
5046 && !generating_literals
)
5048 xtensa_set_frag_assembly_state (frag_now
);
5050 frag_var (rs_machine_dependent
,
5052 RELAX_DESIRE_ALIGN_IF_TARGET
,
5053 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5054 xtensa_set_frag_assembly_state (frag_now
);
5055 xtensa_move_labels (frag_now
, 0, TRUE
);
5058 /* We need to mark the following properties even if we aren't aligning. */
5060 /* If the label is already known to be a branch target, i.e., a
5061 forward branch, mark the frag accordingly. Backward branches
5062 are handled by xg_add_branch_and_loop_targets. */
5063 if (symbol_get_tc (sym
)->is_branch_target
)
5064 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5066 /* Loops only go forward, so they can be identified here. */
5067 if (symbol_get_tc (sym
)->is_loop_target
)
5068 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5070 dwarf2_emit_label (sym
);
5074 /* tc_unrecognized_line hook */
5077 xtensa_unrecognized_line (int ch
)
5082 if (cur_vinsn
.inside_bundle
== 0)
5084 /* PR8110: Cannot emit line number info inside a FLIX bundle
5085 when using --gstabs. Temporarily disable debug info. */
5086 generate_lineno_debug ();
5087 if (debug_type
== DEBUG_STABS
)
5089 xt_saved_debug_type
= debug_type
;
5090 debug_type
= DEBUG_NONE
;
5093 cur_vinsn
.inside_bundle
= 1;
5097 as_bad (_("extra opening brace"));
5103 if (cur_vinsn
.inside_bundle
)
5104 finish_vinsn (&cur_vinsn
);
5107 as_bad (_("extra closing brace"));
5112 as_bad (_("syntax error"));
5119 /* md_flush_pending_output hook */
5122 xtensa_flush_pending_output (void)
5124 if (cur_vinsn
.inside_bundle
)
5125 as_bad (_("missing closing brace"));
5127 /* If there is a non-zero instruction fragment, close it. */
5128 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5130 frag_wane (frag_now
);
5132 xtensa_set_frag_assembly_state (frag_now
);
5134 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5136 xtensa_clear_insn_labels ();
5140 /* We had an error while parsing an instruction. The string might look
5141 like this: "insn arg1, arg2 }". If so, we need to see the closing
5142 brace and reset some fields. Otherwise, the vinsn never gets closed
5143 and the num_slots field will grow past the end of the array of slots,
5144 and bad things happen. */
5147 error_reset_cur_vinsn (void)
5149 if (cur_vinsn
.inside_bundle
)
5151 if (*input_line_pointer
== '}'
5152 || *(input_line_pointer
- 1) == '}'
5153 || *(input_line_pointer
- 2) == '}')
5154 xg_clear_vinsn (&cur_vinsn
);
5160 md_assemble (char *str
)
5162 xtensa_isa isa
= xtensa_default_isa
;
5163 char *opname
, *file_name
;
5165 bfd_boolean has_underbar
= FALSE
;
5166 char *arg_strings
[MAX_INSN_ARGS
];
5168 TInsn orig_insn
; /* Original instruction from the input. */
5170 tinsn_init (&orig_insn
);
5172 /* Split off the opcode. */
5173 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5174 opname
= xmalloc (opnamelen
+ 1);
5175 memcpy (opname
, str
, opnamelen
);
5176 opname
[opnamelen
] = '\0';
5178 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5181 as_bad (_("syntax error"));
5185 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5188 /* Check for an underbar prefix. */
5191 has_underbar
= TRUE
;
5195 orig_insn
.insn_type
= ITYPE_INSN
;
5197 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5199 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5200 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5202 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5203 if (fmt
== XTENSA_UNDEFINED
)
5205 as_bad (_("unknown opcode or format name '%s'"), opname
);
5206 error_reset_cur_vinsn ();
5209 if (!cur_vinsn
.inside_bundle
)
5211 as_bad (_("format names only valid inside bundles"));
5212 error_reset_cur_vinsn ();
5215 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5216 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5218 cur_vinsn
.format
= fmt
;
5219 free (has_underbar
? opname
- 1 : opname
);
5220 error_reset_cur_vinsn ();
5224 /* Parse the arguments. */
5225 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5227 as_bad (_("syntax error"));
5228 error_reset_cur_vinsn ();
5232 /* Free the opcode and argument strings, now that they've been parsed. */
5233 free (has_underbar
? opname
- 1 : opname
);
5235 while (num_args
-- > 0)
5236 free (arg_strings
[num_args
]);
5238 /* Get expressions for invisible operands. */
5239 if (get_invisible_operands (&orig_insn
))
5241 error_reset_cur_vinsn ();
5245 /* Check for the right number and type of arguments. */
5246 if (tinsn_check_arguments (&orig_insn
))
5248 error_reset_cur_vinsn ();
5252 /* A FLIX bundle may be spread across multiple input lines. We want to
5253 report the first such line in the debug information. Record the line
5254 number for each TInsn (assume the file name doesn't change), so the
5255 first line can be found later. */
5256 as_where (&file_name
, &orig_insn
.linenum
);
5258 xg_add_branch_and_loop_targets (&orig_insn
);
5260 /* Special-case for "entry" instruction. */
5261 if (orig_insn
.opcode
== xtensa_entry_opcode
)
5263 /* Check that the third opcode (#2) is >= 16. */
5264 if (orig_insn
.ntok
>= 3)
5266 expressionS
*exp
= &orig_insn
.tok
[2];
5270 if (exp
->X_add_number
< 16)
5271 as_warn (_("entry instruction with stack decrement < 16"));
5275 as_warn (_("entry instruction with non-constant decrement"));
5281 assemble_tokens (opcode, tok, ntok);
5282 expand the tokens from the orig_insn into the
5283 stack of instructions that will not expand
5284 unless required at relaxation time. */
5286 if (!cur_vinsn
.inside_bundle
)
5287 emit_single_op (&orig_insn
);
5288 else /* We are inside a bundle. */
5290 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5291 cur_vinsn
.num_slots
++;
5292 if (*input_line_pointer
== '}'
5293 || *(input_line_pointer
- 1) == '}'
5294 || *(input_line_pointer
- 2) == '}')
5295 finish_vinsn (&cur_vinsn
);
5298 /* We've just emitted a new instruction so clear the list of labels. */
5299 xtensa_clear_insn_labels ();
5303 /* HANDLE_ALIGN hook */
5305 /* For a .align directive, we mark the previous block with the alignment
5306 information. This will be placed in the object file in the
5307 property section corresponding to this section. */
5310 xtensa_handle_align (fragS
*fragP
)
5313 && ! fragP
->tc_frag_data
.is_literal
5314 && (fragP
->fr_type
== rs_align
5315 || fragP
->fr_type
== rs_align_code
)
5316 && fragP
->fr_address
+ fragP
->fr_fix
> 0
5317 && fragP
->fr_offset
> 0
5318 && now_seg
!= bss_section
)
5320 fragP
->tc_frag_data
.is_align
= TRUE
;
5321 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5324 if (fragP
->fr_type
== rs_align_test
)
5327 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5329 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5330 _("unaligned entry instruction"));
5335 /* TC_FRAG_INIT hook */
5338 xtensa_frag_init (fragS
*frag
)
5340 xtensa_set_frag_assembly_state (frag
);
5345 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5351 /* Round up a section size to the appropriate boundary. */
5354 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5356 return size
; /* Byte alignment is fine. */
5361 md_pcrel_from (fixS
*fixP
)
5364 static xtensa_insnbuf insnbuf
= NULL
;
5365 static xtensa_insnbuf slotbuf
= NULL
;
5368 xtensa_opcode opcode
;
5371 xtensa_isa isa
= xtensa_default_isa
;
5372 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5373 bfd_boolean alt_reloc
;
5375 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5380 insnbuf
= xtensa_insnbuf_alloc (isa
);
5381 slotbuf
= xtensa_insnbuf_alloc (isa
);
5384 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5385 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) insn_p
, 0);
5386 fmt
= xtensa_format_decode (isa
, insnbuf
);
5388 if (fmt
== XTENSA_UNDEFINED
)
5389 as_fatal (_("bad instruction format"));
5391 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5392 as_fatal (_("invalid relocation"));
5394 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5395 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5397 /* Check for "alternate" relocations (operand not specified). None
5398 of the current uses for these are really PC-relative. */
5399 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5401 if (opcode
!= xtensa_l32r_opcode
5402 && opcode
!= xtensa_const16_opcode
)
5403 as_fatal (_("invalid relocation for '%s' instruction"),
5404 xtensa_opcode_name (isa
, opcode
));
5408 opnum
= get_relaxable_immed (opcode
);
5410 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5411 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5413 as_bad_where (fixP
->fx_file
,
5415 _("invalid relocation for operand %d of '%s'"),
5416 opnum
, xtensa_opcode_name (isa
, opcode
));
5419 return 0 - opnd_value
;
5423 /* TC_FORCE_RELOCATION hook */
5426 xtensa_force_relocation (fixS
*fix
)
5428 switch (fix
->fx_r_type
)
5430 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5431 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5432 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5433 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5434 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5435 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5436 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5437 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5438 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5439 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5440 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5441 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5442 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5443 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5444 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5445 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5451 if (linkrelax
&& fix
->fx_addsy
5452 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5455 return generic_force_reloc (fix
);
5459 /* TC_VALIDATE_FIX_SUB hook */
5462 xtensa_validate_fix_sub (fixS
*fix
)
5464 segT add_symbol_segment
, sub_symbol_segment
;
5466 /* The difference of two symbols should be resolved by the assembler when
5467 linkrelax is not set. If the linker may relax the section containing
5468 the symbols, then an Xtensa DIFF relocation must be generated so that
5469 the linker knows to adjust the difference value. */
5470 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
5473 /* Make sure both symbols are in the same segment, and that segment is
5474 "normal" and relaxable. If the segment is not "normal", then the
5475 fix is not valid. If the segment is not "relaxable", then the fix
5476 should have been handled earlier. */
5477 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
5478 if (! SEG_NORMAL (add_symbol_segment
) ||
5479 ! relaxable_section (add_symbol_segment
))
5481 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
5482 return (sub_symbol_segment
== add_symbol_segment
);
5486 /* NO_PSEUDO_DOT hook */
5488 /* This function has nothing to do with pseudo dots, but this is the
5489 nearest macro to where the check needs to take place. FIXME: This
5493 xtensa_check_inside_bundle (void)
5495 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5496 as_bad (_("directives are not valid inside bundles"));
5498 /* This function must always return FALSE because it is called via a
5499 macro that has nothing to do with bundling. */
5504 /* md_elf_section_change_hook */
5507 xtensa_elf_section_change_hook (void)
5509 /* Set up the assembly state. */
5510 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5511 xtensa_set_frag_assembly_state (frag_now
);
5515 /* tc_fix_adjustable hook */
5518 xtensa_fix_adjustable (fixS
*fixP
)
5520 /* An offset is not allowed in combination with the difference of two
5521 symbols, but that cannot be easily detected after a local symbol
5522 has been adjusted to a (section+offset) form. Return 0 so that such
5523 an fix will not be adjusted. */
5524 if (fixP
->fx_subsy
&& fixP
->fx_addsy
&& fixP
->fx_offset
5525 && relaxable_section (S_GET_SEGMENT (fixP
->fx_subsy
)))
5528 /* We need the symbol name for the VTABLE entries. */
5529 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5530 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5538 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg
)
5540 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5543 switch (fixP
->fx_r_type
)
5548 if (linkrelax
&& fixP
->fx_subsy
)
5550 switch (fixP
->fx_r_type
)
5553 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF8
;
5556 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF16
;
5559 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF32
;
5565 /* An offset is only allowed when it results from adjusting a
5566 local symbol into a section-relative offset. If the offset
5567 came from the original expression, tc_fix_adjustable will have
5568 prevented the fix from being converted to a section-relative
5569 form so that we can flag the error here. */
5570 if (fixP
->fx_offset
!= 0 && !symbol_section_p (fixP
->fx_addsy
))
5571 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5572 _("cannot represent subtraction with an offset"));
5574 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5575 - S_GET_VALUE (fixP
->fx_subsy
));
5577 /* The difference value gets written out, and the DIFF reloc
5578 identifies the address of the subtracted symbol (i.e., the one
5579 with the lowest address). */
5581 fixP
->fx_offset
-= val
;
5582 fixP
->fx_subsy
= NULL
;
5584 else if (! fixP
->fx_addsy
)
5591 md_number_to_chars (fixpos
, val
, fixP
->fx_size
);
5592 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5595 case BFD_RELOC_XTENSA_SLOT0_OP
:
5596 case BFD_RELOC_XTENSA_SLOT1_OP
:
5597 case BFD_RELOC_XTENSA_SLOT2_OP
:
5598 case BFD_RELOC_XTENSA_SLOT3_OP
:
5599 case BFD_RELOC_XTENSA_SLOT4_OP
:
5600 case BFD_RELOC_XTENSA_SLOT5_OP
:
5601 case BFD_RELOC_XTENSA_SLOT6_OP
:
5602 case BFD_RELOC_XTENSA_SLOT7_OP
:
5603 case BFD_RELOC_XTENSA_SLOT8_OP
:
5604 case BFD_RELOC_XTENSA_SLOT9_OP
:
5605 case BFD_RELOC_XTENSA_SLOT10_OP
:
5606 case BFD_RELOC_XTENSA_SLOT11_OP
:
5607 case BFD_RELOC_XTENSA_SLOT12_OP
:
5608 case BFD_RELOC_XTENSA_SLOT13_OP
:
5609 case BFD_RELOC_XTENSA_SLOT14_OP
:
5612 /* Write the tentative value of a PC-relative relocation to a
5613 local symbol into the instruction. The value will be ignored
5614 by the linker, and it makes the object file disassembly
5615 readable when all branch targets are encoded in relocations. */
5617 assert (fixP
->fx_addsy
);
5618 if (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
&& !fixP
->fx_plt
5619 && !S_FORCE_RELOC (fixP
->fx_addsy
, 1))
5621 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5622 - md_pcrel_from (fixP
));
5623 (void) xg_apply_fix_value (fixP
, val
);
5626 else if (! fixP
->fx_addsy
)
5629 if (xg_apply_fix_value (fixP
, val
))
5634 case BFD_RELOC_XTENSA_PLT
:
5635 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5636 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5637 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5638 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5639 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5640 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5641 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5642 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5643 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5644 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5645 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5646 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5647 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5648 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5649 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5650 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5651 /* These all need to be resolved at link-time. Do nothing now. */
5654 case BFD_RELOC_VTABLE_INHERIT
:
5655 case BFD_RELOC_VTABLE_ENTRY
:
5660 as_bad (_("unhandled local relocation fix %s"),
5661 bfd_get_reloc_code_name (fixP
->fx_r_type
));
5667 md_atof (int type
, char *litP
, int *sizeP
)
5670 LITTLENUM_TYPE words
[4];
5686 return "bad call to md_atof";
5689 t
= atof_ieee (input_line_pointer
, type
, words
);
5691 input_line_pointer
= t
;
5695 for (i
= prec
- 1; i
>= 0; i
--)
5698 if (target_big_endian
)
5699 idx
= (prec
- 1 - i
);
5701 md_number_to_chars (litP
, (valueT
) words
[idx
], 2);
5710 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
5712 return total_frag_text_expansion (fragP
);
5716 /* Translate internal representation of relocation info to BFD target
5720 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
5724 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
5725 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5726 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5727 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5729 /* Make sure none of our internal relocations make it this far.
5730 They'd better have been fully resolved by this point. */
5731 assert ((int) fixp
->fx_r_type
> 0);
5733 reloc
->addend
= fixp
->fx_offset
;
5735 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
5736 if (reloc
->howto
== NULL
)
5738 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5739 _("cannot represent `%s' relocation in object file"),
5740 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5741 free (reloc
->sym_ptr_ptr
);
5746 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
5747 as_fatal (_("internal error? cannot generate `%s' relocation"),
5748 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5754 /* Checks for resource conflicts between instructions. */
5756 /* The func unit stuff could be implemented as bit-vectors rather
5757 than the iterative approach here. If it ends up being too
5758 slow, we will switch it. */
5761 new_resource_table (void *data
,
5764 unit_num_copies_func uncf
,
5765 opcode_num_units_func onuf
,
5766 opcode_funcUnit_use_unit_func ouuf
,
5767 opcode_funcUnit_use_stage_func ousf
)
5770 resource_table
*rt
= (resource_table
*) xmalloc (sizeof (resource_table
));
5772 rt
->cycles
= cycles
;
5773 rt
->allocated_cycles
= cycles
;
5775 rt
->unit_num_copies
= uncf
;
5776 rt
->opcode_num_units
= onuf
;
5777 rt
->opcode_unit_use
= ouuf
;
5778 rt
->opcode_unit_stage
= ousf
;
5780 rt
->units
= (unsigned char **) xcalloc (cycles
, sizeof (unsigned char *));
5781 for (i
= 0; i
< cycles
; i
++)
5782 rt
->units
[i
] = (unsigned char *) xcalloc (nu
, sizeof (unsigned char));
5789 clear_resource_table (resource_table
*rt
)
5792 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
5793 for (j
= 0; j
< rt
->num_units
; j
++)
5794 rt
->units
[i
][j
] = 0;
5798 /* We never shrink it, just fake it into thinking so. */
5801 resize_resource_table (resource_table
*rt
, int cycles
)
5805 rt
->cycles
= cycles
;
5806 if (cycles
<= rt
->allocated_cycles
)
5809 old_cycles
= rt
->allocated_cycles
;
5810 rt
->allocated_cycles
= cycles
;
5812 rt
->units
= xrealloc (rt
->units
,
5813 rt
->allocated_cycles
* sizeof (unsigned char *));
5814 for (i
= 0; i
< old_cycles
; i
++)
5815 rt
->units
[i
] = xrealloc (rt
->units
[i
],
5816 rt
->num_units
* sizeof (unsigned char));
5817 for (i
= old_cycles
; i
< cycles
; i
++)
5818 rt
->units
[i
] = xcalloc (rt
->num_units
, sizeof (unsigned char));
5823 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5826 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5828 for (i
= 0; i
< uses
; i
++)
5830 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5831 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5832 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
5833 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
5834 if (copies_in_use
>= copies
)
5842 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5845 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5847 for (i
= 0; i
< uses
; i
++)
5849 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5850 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5851 /* Note that this allows resources to be oversubscribed. That's
5852 essential to the way the optional scheduler works.
5853 resources_available reports when a resource is over-subscribed,
5854 so it's easy to tell. */
5855 rt
->units
[stage
+ cycle
][unit
]++;
5861 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5864 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5866 for (i
= 0; i
< uses
; i
++)
5868 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5869 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5870 assert (rt
->units
[stage
+ cycle
][unit
] > 0);
5871 rt
->units
[stage
+ cycle
][unit
]--;
5876 /* Wrapper functions make parameterized resource reservation
5880 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
5882 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5888 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
5890 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5895 /* Note that this function does not check issue constraints, but
5896 solely whether the hardware is available to execute the given
5897 instructions together. It also doesn't check if the tinsns
5898 write the same state, or access the same tieports. That is
5899 checked by check_t1_t2_reads_and_writes. */
5902 resources_conflict (vliw_insn
*vinsn
)
5905 static resource_table
*rt
= NULL
;
5907 /* This is the most common case by far. Optimize it. */
5908 if (vinsn
->num_slots
== 1)
5913 xtensa_isa isa
= xtensa_default_isa
;
5914 rt
= new_resource_table
5915 (isa
, xtensa_isa_num_pipe_stages (isa
),
5916 xtensa_isa_num_funcUnits (isa
),
5917 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
5918 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
5919 opcode_funcUnit_use_unit
,
5920 opcode_funcUnit_use_stage
);
5923 clear_resource_table (rt
);
5925 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5927 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
5929 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
5936 /* finish_vinsn, emit_single_op and helper functions. */
5938 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
5939 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
5940 static void bundle_single_op (TInsn
*);
5941 static void xg_assemble_vliw_tokens (vliw_insn
*);
5944 /* We have reached the end of a bundle; emit into the frag. */
5947 finish_vinsn (vliw_insn
*vinsn
)
5954 if (find_vinsn_conflicts (vinsn
))
5956 xg_clear_vinsn (vinsn
);
5960 /* First, find a format that works. */
5961 if (vinsn
->format
== XTENSA_UNDEFINED
)
5962 vinsn
->format
= xg_find_narrowest_format (vinsn
);
5964 if (vinsn
->format
== XTENSA_UNDEFINED
)
5966 as_where (&file_name
, &line
);
5967 as_bad_where (file_name
, line
,
5968 _("couldn't find a valid instruction format"));
5969 fprintf (stderr
, _(" ops were: "));
5970 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5971 fprintf (stderr
, _(" %s;"),
5972 xtensa_opcode_name (xtensa_default_isa
,
5973 vinsn
->slots
[i
].opcode
));
5974 fprintf (stderr
, _("\n"));
5975 xg_clear_vinsn (vinsn
);
5979 if (vinsn
->num_slots
5980 != xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
))
5982 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
5983 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
5984 xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
),
5986 xg_clear_vinsn (vinsn
);
5990 if (resources_conflict (vinsn
))
5992 as_where (&file_name
, &line
);
5993 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
5994 fprintf (stderr
, " ops were: ");
5995 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5996 fprintf (stderr
, " %s;",
5997 xtensa_opcode_name (xtensa_default_isa
,
5998 vinsn
->slots
[i
].opcode
));
5999 fprintf (stderr
, "\n");
6000 xg_clear_vinsn (vinsn
);
6004 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6006 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
6008 symbolS
*lit_sym
= NULL
;
6010 bfd_boolean e
= FALSE
;
6011 bfd_boolean saved_density
= density_supported
;
6013 /* We don't want to narrow ops inside multi-slot bundles. */
6014 if (vinsn
->num_slots
> 1)
6015 density_supported
= FALSE
;
6017 istack_init (&slotstack
);
6018 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
6020 vinsn
->slots
[i
].opcode
=
6021 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6023 vinsn
->slots
[i
].ntok
= 0;
6026 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
6032 density_supported
= saved_density
;
6036 xg_clear_vinsn (vinsn
);
6040 for (j
= 0; j
< slotstack
.ninsn
; j
++)
6042 TInsn
*insn
= &slotstack
.insn
[j
];
6043 if (insn
->insn_type
== ITYPE_LITERAL
)
6045 assert (lit_sym
== NULL
);
6046 lit_sym
= xg_assemble_literal (insn
);
6050 assert (insn
->insn_type
== ITYPE_INSN
);
6052 xg_resolve_literals (insn
, lit_sym
);
6053 if (j
!= slotstack
.ninsn
- 1)
6054 emit_single_op (insn
);
6058 if (vinsn
->num_slots
> 1)
6060 if (opcode_fits_format_slot
6061 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6064 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6068 bundle_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6069 if (vinsn
->format
== XTENSA_UNDEFINED
)
6070 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6072 vinsn
->slots
[i
].opcode
6073 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6076 vinsn
->slots
[i
].ntok
= 0;
6081 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6082 vinsn
->format
= XTENSA_UNDEFINED
;
6087 /* Now check resource conflicts on the modified bundle. */
6088 if (resources_conflict (vinsn
))
6090 as_where (&file_name
, &line
);
6091 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6092 fprintf (stderr
, " ops were: ");
6093 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6094 fprintf (stderr
, " %s;",
6095 xtensa_opcode_name (xtensa_default_isa
,
6096 vinsn
->slots
[i
].opcode
));
6097 fprintf (stderr
, "\n");
6098 xg_clear_vinsn (vinsn
);
6102 /* First, find a format that works. */
6103 if (vinsn
->format
== XTENSA_UNDEFINED
)
6104 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6106 xg_assemble_vliw_tokens (vinsn
);
6108 xg_clear_vinsn (vinsn
);
6112 /* Given an vliw instruction, what conflicts are there in register
6113 usage and in writes to states and queues?
6115 This function does two things:
6116 1. Reports an error when a vinsn contains illegal combinations
6117 of writes to registers states or queues.
6118 2. Marks individual tinsns as not relaxable if the combination
6119 contains antidependencies.
6121 Job 2 handles things like swap semantics in instructions that need
6122 to be relaxed. For example,
6126 normally would be relaxed to
6131 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6133 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6135 then we can't relax it into
6138 { add a0, a1, a0 ; add a2, a0, a4 ; }
6140 because the value of a0 is trashed before the second add can read it. */
6142 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6145 find_vinsn_conflicts (vliw_insn
*vinsn
)
6149 xtensa_isa isa
= xtensa_default_isa
;
6151 assert (!past_xtensa_end
);
6153 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6155 TInsn
*op1
= &vinsn
->slots
[i
];
6156 if (op1
->is_specific_opcode
)
6157 op1
->keep_wide
= TRUE
;
6159 op1
->keep_wide
= FALSE
;
6162 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6164 TInsn
*op1
= &vinsn
->slots
[i
];
6166 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6169 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6173 TInsn
*op2
= &vinsn
->slots
[j
];
6174 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6175 switch (conflict_type
)
6178 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6179 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6180 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6183 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6184 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6185 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6188 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"),
6189 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6190 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6193 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"),
6194 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6195 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6198 /* Everything is OK. */
6201 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6202 || conflict_type
== 'a');
6209 as_bad (_("multiple branches or jumps in the same bundle"));
6217 /* Check how the state used by t1 and t2 relate.
6220 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6221 case B: no relationship between what is read and written (both could
6222 read the same reg though)
6223 case C: t1 writes a register t2 writes (a register conflict within a
6225 case D: t1 writes a state that t2 also writes
6226 case E: t1 writes a tie queue that t2 also writes
6227 case F: two volatile queue accesses
6231 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6233 xtensa_isa isa
= xtensa_default_isa
;
6234 xtensa_regfile t1_regfile
, t2_regfile
;
6236 int t1_base_reg
, t1_last_reg
;
6237 int t2_base_reg
, t2_last_reg
;
6238 char t1_inout
, t2_inout
;
6240 char conflict
= 'b';
6245 bfd_boolean t1_volatile
= FALSE
;
6246 bfd_boolean t2_volatile
= FALSE
;
6248 /* Check registers. */
6249 for (j
= 0; j
< t2
->ntok
; j
++)
6251 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6254 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6255 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6256 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6258 for (i
= 0; i
< t1
->ntok
; i
++)
6260 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6263 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6265 if (t1_regfile
!= t2_regfile
)
6268 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6269 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6271 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6272 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6274 if (t1_inout
== 'm' || t1_inout
== 'o'
6275 || t2_inout
== 'm' || t2_inout
== 'o')
6282 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6283 t1_last_reg
= (t1_base_reg
6284 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6286 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6288 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6290 if (t1_reg
!= t2_reg
)
6293 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6299 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6305 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6313 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6314 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6315 for (j
= 0; j
< t2_states
; j
++)
6317 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6318 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6319 for (i
= 0; i
< t1_states
; i
++)
6321 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6322 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6326 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6332 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6338 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6343 /* Check tieports. */
6344 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6345 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6346 for (j
= 0; j
< t2_interfaces
; j
++)
6348 xtensa_interface t2_int
6349 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6350 int t2_class
= xtensa_interface_class_id (isa
, t2_int
);
6352 t2_inout
= xtensa_interface_inout (isa
, t2_int
);
6353 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1)
6356 for (i
= 0; i
< t1_interfaces
; i
++)
6358 xtensa_interface t1_int
6359 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6360 int t1_class
= xtensa_interface_class_id (isa
, t1_int
);
6362 t1_inout
= xtensa_interface_inout (isa
, t1_int
);
6363 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1)
6366 if (t1_volatile
&& t2_volatile
&& (t1_class
== t2_class
))
6369 if (t1_int
!= t2_int
)
6372 if (t2_inout
== 'i' && t1_inout
== 'o')
6378 if (t1_inout
== 'i' && t2_inout
== 'o')
6384 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6393 static xtensa_format
6394 xg_find_narrowest_format (vliw_insn
*vinsn
)
6396 /* Right now we assume that the ops within the vinsn are properly
6397 ordered for the slots that the programmer wanted them in. In
6398 other words, we don't rearrange the ops in hopes of finding a
6399 better format. The scheduler handles that. */
6401 xtensa_isa isa
= xtensa_default_isa
;
6402 xtensa_format format
;
6403 vliw_insn v_copy
= *vinsn
;
6404 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6406 if (vinsn
->num_slots
== 1)
6407 return xg_get_single_format (vinsn
->slots
[0].opcode
);
6409 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6412 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6416 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6418 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6420 v_copy
.slots
[slot
].opcode
=
6421 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6422 v_copy
.slots
[slot
].ntok
= 0;
6425 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6428 else if (v_copy
.num_slots
> 1)
6431 /* Try the widened version. */
6432 if (!v_copy
.slots
[slot
].keep_wide
6433 && !v_copy
.slots
[slot
].is_specific_opcode
6434 && xg_is_single_relaxable_insn (&v_copy
.slots
[slot
],
6436 && opcode_fits_format_slot (widened
.opcode
,
6439 v_copy
.slots
[slot
] = widened
;
6444 if (fit
== v_copy
.num_slots
)
6447 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6448 vinsn
->format
= format
;
6454 if (format
== xtensa_isa_num_formats (isa
))
6455 return XTENSA_UNDEFINED
;
6461 /* Return the additional space needed in a frag
6462 for possible relaxations of any ops in a VLIW insn.
6463 Also fill out the relaxations that might be required of
6464 each tinsn in the vinsn. */
6467 relaxation_requirements (vliw_insn
*vinsn
)
6469 int extra_space
= 0;
6472 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6474 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6475 if (!tinsn_has_symbolic_operands (tinsn
))
6477 /* A narrow instruction could be widened later to help
6478 alignment issues. */
6479 if (xg_is_single_relaxable_insn (tinsn
, 0, TRUE
)
6480 && !tinsn
->is_specific_opcode
6481 && vinsn
->num_slots
== 1)
6483 /* Difference in bytes between narrow and wide insns... */
6485 tinsn
->subtype
= RELAX_NARROW
;
6486 tinsn
->record_fix
= TRUE
;
6491 tinsn
->record_fix
= FALSE
;
6492 /* No extra_space needed. */
6497 if (workaround_b_j_loop_end
6498 && tinsn
->opcode
== xtensa_jx_opcode
6499 && use_transform ())
6501 /* Add 2 of these. */
6502 extra_space
+= 3; /* for the nop size */
6503 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6506 /* Need to assemble it with space for the relocation. */
6507 if (xg_is_relaxable_insn (tinsn
, 0)
6508 && !tinsn
->is_specific_opcode
)
6510 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6511 int max_literal_size
=
6512 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6514 tinsn
->literal_space
= max_literal_size
;
6516 tinsn
->subtype
= RELAX_IMMED
;
6517 tinsn
->record_fix
= FALSE
;
6518 extra_space
+= max_size
;
6522 tinsn
->record_fix
= TRUE
;
6523 /* No extra space needed. */
6532 bundle_single_op (TInsn
*orig_insn
)
6534 xtensa_isa isa
= xtensa_default_isa
;
6539 v
.format
= op_placement_table
[orig_insn
->opcode
].narrowest
;
6540 assert (v
.format
!= XTENSA_UNDEFINED
);
6541 v
.num_slots
= xtensa_format_num_slots (isa
, v
.format
);
6544 !opcode_fits_format_slot (orig_insn
->opcode
, v
.format
, slot
);
6547 v
.slots
[slot
].opcode
=
6548 xtensa_format_slot_nop_opcode (isa
, v
.format
, slot
);
6549 v
.slots
[slot
].ntok
= 0;
6550 v
.slots
[slot
].insn_type
= ITYPE_INSN
;
6553 v
.slots
[slot
] = *orig_insn
;
6556 for ( ; slot
< v
.num_slots
; slot
++)
6558 v
.slots
[slot
].opcode
=
6559 xtensa_format_slot_nop_opcode (isa
, v
.format
, slot
);
6560 v
.slots
[slot
].ntok
= 0;
6561 v
.slots
[slot
].insn_type
= ITYPE_INSN
;
6570 emit_single_op (TInsn
*orig_insn
)
6573 IStack istack
; /* put instructions into here */
6574 symbolS
*lit_sym
= NULL
;
6575 symbolS
*label_sym
= NULL
;
6577 istack_init (&istack
);
6579 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6580 Because the scheduling and bundling characteristics of movi and
6581 l32r or const16 are so different, we can do much better if we relax
6582 it prior to scheduling and bundling, rather than after. */
6583 if ((orig_insn
->opcode
== xtensa_movi_opcode
6584 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
6585 && !cur_vinsn
.inside_bundle
6586 && (orig_insn
->tok
[1].X_op
== O_symbol
6587 || orig_insn
->tok
[1].X_op
== O_pltrel
))
6588 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
6590 if (xg_expand_assembly_insn (&istack
, orig_insn
))
6593 for (i
= 0; i
< istack
.ninsn
; i
++)
6595 TInsn
*insn
= &istack
.insn
[i
];
6596 switch (insn
->insn_type
)
6599 assert (lit_sym
== NULL
);
6600 lit_sym
= xg_assemble_literal (insn
);
6604 static int relaxed_sym_idx
= 0;
6605 char *label
= xmalloc (strlen (FAKE_LABEL_NAME
) + 12);
6606 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
6608 assert (label_sym
== NULL
);
6609 label_sym
= symbol_find_or_make (label
);
6616 xg_resolve_literals (insn
, lit_sym
);
6618 xg_resolve_labels (insn
, label_sym
);
6619 bundle_single_op (insn
);
6631 total_frag_text_expansion (fragS
*fragP
)
6634 int total_expansion
= 0;
6636 for (slot
= 0; slot
< MAX_SLOTS
; slot
++)
6637 total_expansion
+= fragP
->tc_frag_data
.text_expansion
[slot
];
6639 return total_expansion
;
6643 /* Emit a vliw instruction to the current fragment. */
6646 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
6648 bfd_boolean finish_frag
= FALSE
;
6649 bfd_boolean is_jump
= FALSE
;
6650 bfd_boolean is_branch
= FALSE
;
6651 xtensa_isa isa
= xtensa_default_isa
;
6657 unsigned current_line
, best_linenum
;
6660 best_linenum
= UINT_MAX
;
6662 if (generating_literals
)
6664 static int reported
= 0;
6666 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
6667 _("cannot assemble into a literal fragment"));
6674 if (frag_now_fix () != 0
6675 && (! frag_now
->tc_frag_data
.is_insn
6676 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6677 || !use_transform () != frag_now
->tc_frag_data
.is_no_transform
6678 || (directive_state
[directive_longcalls
]
6679 != frag_now
->tc_frag_data
.use_longcalls
)
6680 || (directive_state
[directive_absolute_literals
]
6681 != frag_now
->tc_frag_data
.use_absolute_literals
)))
6683 frag_wane (frag_now
);
6685 xtensa_set_frag_assembly_state (frag_now
);
6688 if (workaround_a0_b_retw
6689 && vinsn
->num_slots
== 1
6690 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
6691 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
6692 && use_transform ())
6694 has_a0_b_retw
= TRUE
;
6696 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
6697 After the first assembly pass we will check all of them and
6698 add a nop if needed. */
6699 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6700 frag_var (rs_machine_dependent
, 4, 4,
6701 RELAX_ADD_NOP_IF_A0_B_RETW
,
6702 frag_now
->fr_symbol
,
6703 frag_now
->fr_offset
,
6705 xtensa_set_frag_assembly_state (frag_now
);
6706 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6707 frag_var (rs_machine_dependent
, 4, 4,
6708 RELAX_ADD_NOP_IF_A0_B_RETW
,
6709 frag_now
->fr_symbol
,
6710 frag_now
->fr_offset
,
6712 xtensa_set_frag_assembly_state (frag_now
);
6715 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6717 /* See if the instruction implies an aligned section. */
6718 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[i
].opcode
) == 1)
6719 record_alignment (now_seg
, 2);
6721 /* Also determine the best line number for debug info. */
6722 best_linenum
= vinsn
->slots
[i
].linenum
< best_linenum
6723 ? vinsn
->slots
[i
].linenum
: best_linenum
;
6726 /* Special cases for instructions that force an alignment... */
6727 /* None of these opcodes are bundle-able. */
6728 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
6732 xtensa_set_frag_assembly_state (frag_now
);
6733 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6735 max_fill
= get_text_align_max_fill_size
6736 (get_text_align_power (xtensa_fetch_width
),
6737 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
6739 if (use_transform ())
6740 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
6741 RELAX_ALIGN_NEXT_OPCODE
,
6742 frag_now
->fr_symbol
,
6743 frag_now
->fr_offset
,
6746 frag_var (rs_machine_dependent
, 0, 0,
6747 RELAX_CHECK_ALIGN_NEXT_OPCODE
, 0, 0, NULL
);
6748 xtensa_set_frag_assembly_state (frag_now
);
6750 xtensa_move_labels (frag_now
, 0, FALSE
);
6753 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
6754 && !vinsn
->slots
[0].is_specific_opcode
)
6756 xtensa_mark_literal_pool_location ();
6757 xtensa_move_labels (frag_now
, 0, TRUE
);
6758 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
6761 if (vinsn
->num_slots
== 1)
6763 if (workaround_a0_b_retw
&& use_transform ())
6764 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
6765 is_register_writer (&vinsn
->slots
[0], "a", 0));
6767 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
6768 is_bad_loopend_opcode (&vinsn
->slots
[0]));
6771 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
6773 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
6775 extra_space
= relaxation_requirements (vinsn
);
6777 /* vinsn_to_insnbuf will produce the error. */
6778 if (vinsn
->format
!= XTENSA_UNDEFINED
)
6780 f
= frag_more (insn_size
+ extra_space
);
6781 xtensa_set_frag_assembly_state (frag_now
);
6782 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6785 vinsn_to_insnbuf (vinsn
, f
, frag_now
, TRUE
);
6786 if (vinsn
->format
== XTENSA_UNDEFINED
)
6789 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, (unsigned char *) f
, 0);
6791 /* Temporarily set the logical line number to the one we want to appear
6792 in the debug information. */
6793 as_where (¤t_file
, ¤t_line
);
6794 new_logical_line (current_file
, best_linenum
);
6795 dwarf2_emit_insn (insn_size
+ extra_space
);
6796 new_logical_line (current_file
, current_line
);
6798 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6800 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6801 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
6802 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
6803 frag_now
->tc_frag_data
.slot_sub_symbols
[slot
] = tinsn
->sub_symbol
;
6804 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
6805 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
6806 if (tinsn
->literal_space
!= 0)
6807 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
6809 if (tinsn
->subtype
== RELAX_NARROW
)
6810 assert (vinsn
->num_slots
== 1);
6811 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
6813 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
6816 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->record_fix
6817 || tinsn
->offset
|| tinsn
->literal_frag
|| is_jump
|| is_branch
)
6821 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6822 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
6826 frag_variant (rs_machine_dependent
,
6827 extra_space
, extra_space
, RELAX_SLOTS
,
6828 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
6829 xtensa_set_frag_assembly_state (frag_now
);
6832 /* Special cases for loops:
6833 close_loop_end should be inserted AFTER short_loop.
6834 Make sure that CLOSE loops are processed BEFORE short_loops
6835 when converting them. */
6837 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
6838 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
)
6839 && !vinsn
->slots
[0].is_specific_opcode
)
6841 if (workaround_short_loop
&& use_transform ())
6843 maybe_has_short_loop
= TRUE
;
6844 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6845 frag_var (rs_machine_dependent
, 4, 4,
6846 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6847 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6848 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6849 frag_var (rs_machine_dependent
, 4, 4,
6850 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6851 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6854 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
6855 loop at least 12 bytes away from another loop's end. */
6856 if (workaround_close_loop_end
&& use_transform ())
6858 maybe_has_close_loop_end
= TRUE
;
6859 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6860 frag_var (rs_machine_dependent
, 12, 12,
6861 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
6862 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6866 if (use_transform ())
6870 assert (finish_frag
);
6871 frag_var (rs_machine_dependent
,
6872 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6874 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6875 xtensa_set_frag_assembly_state (frag_now
);
6877 else if (is_branch
&& do_align_targets ())
6879 assert (finish_frag
);
6880 frag_var (rs_machine_dependent
,
6881 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6882 RELAX_MAYBE_UNREACHABLE
,
6883 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6884 xtensa_set_frag_assembly_state (frag_now
);
6885 frag_var (rs_machine_dependent
,
6887 RELAX_MAYBE_DESIRE_ALIGN
,
6888 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6889 xtensa_set_frag_assembly_state (frag_now
);
6893 /* Now, if the original opcode was a call... */
6894 if (do_align_targets ()
6895 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
6897 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
6898 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6899 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
6900 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6901 xtensa_set_frag_assembly_state (frag_now
);
6904 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6906 frag_wane (frag_now
);
6908 xtensa_set_frag_assembly_state (frag_now
);
6913 /* xtensa_end and helper functions. */
6915 static void xtensa_cleanup_align_frags (void);
6916 static void xtensa_fix_target_frags (void);
6917 static void xtensa_mark_narrow_branches (void);
6918 static void xtensa_mark_zcl_first_insns (void);
6919 static void xtensa_fix_a0_b_retw_frags (void);
6920 static void xtensa_fix_b_j_loop_end_frags (void);
6921 static void xtensa_fix_close_loop_end_frags (void);
6922 static void xtensa_fix_short_loop_frags (void);
6923 static void xtensa_sanity_check (void);
6928 directive_balance ();
6929 xtensa_flush_pending_output ();
6931 past_xtensa_end
= TRUE
;
6933 xtensa_move_literals ();
6935 xtensa_reorder_segments ();
6936 xtensa_cleanup_align_frags ();
6937 xtensa_fix_target_frags ();
6938 if (workaround_a0_b_retw
&& has_a0_b_retw
)
6939 xtensa_fix_a0_b_retw_frags ();
6940 if (workaround_b_j_loop_end
)
6941 xtensa_fix_b_j_loop_end_frags ();
6943 /* "close_loop_end" should be processed BEFORE "short_loop". */
6944 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
6945 xtensa_fix_close_loop_end_frags ();
6947 if (workaround_short_loop
&& maybe_has_short_loop
)
6948 xtensa_fix_short_loop_frags ();
6949 xtensa_mark_narrow_branches ();
6950 xtensa_mark_zcl_first_insns ();
6952 xtensa_sanity_check ();
6957 xtensa_cleanup_align_frags (void)
6961 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
6964 /* Walk over all of the fragments in a subsection. */
6965 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
6967 if ((fragP
->fr_type
== rs_align
6968 || fragP
->fr_type
== rs_align_code
6969 || (fragP
->fr_type
== rs_machine_dependent
6970 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
6971 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
6972 && fragP
->fr_fix
== 0)
6974 fragS
*next
= fragP
->fr_next
;
6977 && next
->fr_fix
== 0
6978 && next
->fr_type
== rs_machine_dependent
6979 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
6982 next
= next
->fr_next
;
6985 /* If we don't widen branch targets, then they
6986 will be easier to align. */
6987 if (fragP
->tc_frag_data
.is_branch_target
6988 && fragP
->fr_opcode
== fragP
->fr_literal
6989 && fragP
->fr_type
== rs_machine_dependent
6990 && fragP
->fr_subtype
== RELAX_SLOTS
6991 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
6993 if (fragP
->fr_type
== rs_machine_dependent
6994 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
6995 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
7001 /* Re-process all of the fragments looking to convert all of the
7002 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
7003 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7004 Otherwise, convert to a .fill 0. */
7007 xtensa_fix_target_frags (void)
7011 /* When this routine is called, all of the subsections are still intact
7012 so we walk over subsections instead of sections. */
7013 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7017 /* Walk over all of the fragments in a subsection. */
7018 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7020 if (fragP
->fr_type
== rs_machine_dependent
7021 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7023 if (next_frag_is_branch_target (fragP
))
7024 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7033 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
7036 xtensa_mark_narrow_branches (void)
7040 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7043 /* Walk over all of the fragments in a subsection. */
7044 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7046 if (fragP
->fr_type
== rs_machine_dependent
7047 && fragP
->fr_subtype
== RELAX_SLOTS
7048 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7051 const expressionS
*expr
;
7054 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7055 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
7057 expr
= &vinsn
.slots
[0].tok
[1];
7058 symbolP
= expr
->X_add_symbol
;
7060 if (vinsn
.num_slots
== 1
7061 && xtensa_opcode_is_branch (xtensa_default_isa
,
7062 vinsn
.slots
[0].opcode
)
7063 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
7064 && is_narrow_branch_guaranteed_in_range (fragP
,
7067 fragP
->fr_subtype
= RELAX_SLOTS
;
7068 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
7069 fragP
->tc_frag_data
.is_aligning_branch
= 1;
7077 /* A branch is typically widened only when its target is out of
7078 range. However, we would like to widen them to align a subsequent
7079 branch target when possible.
7081 Because the branch relaxation code is so convoluted, the optimal solution
7082 (combining the two cases) is difficult to get right in all circumstances.
7083 We therefore go with an "almost as good" solution, where we only
7084 use for alignment narrow branches that definitely will not expand to a
7085 jump and a branch. These functions find and mark these cases. */
7087 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
7088 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7089 We start counting beginning with the frag after the 2-byte branch, so the
7090 maximum offset is (4 - 2) + 63 = 65. */
7091 #define MAX_IMMED6 65
7093 static offsetT
unrelaxed_frag_max_size (fragS
*);
7096 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
7098 const expressionS
*expr
= &tinsn
->tok
[1];
7099 symbolS
*symbolP
= expr
->X_add_symbol
;
7100 fragS
*target_frag
= symbol_get_frag (symbolP
);
7101 offsetT max_distance
= expr
->X_add_number
;
7102 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
7103 if (is_branch_jmp_to_next (tinsn
, fragP
))
7106 /* The branch doesn't branch over it's own frag,
7107 but over the subsequent ones. */
7108 fragP
= fragP
->fr_next
;
7109 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
7111 max_distance
+= unrelaxed_frag_max_size (fragP
);
7112 fragP
= fragP
->fr_next
;
7114 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
7121 xtensa_mark_zcl_first_insns (void)
7125 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7128 /* Walk over all of the fragments in a subsection. */
7129 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7131 if (fragP
->fr_type
== rs_machine_dependent
7132 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7133 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7135 /* Find the loop frag. */
7136 fragS
*targ_frag
= next_non_empty_frag (fragP
);
7137 /* Find the first insn frag. */
7138 targ_frag
= next_non_empty_frag (targ_frag
);
7140 /* Of course, sometimes (mostly for toy test cases) a
7141 zero-cost loop instruction is the last in a section. */
7143 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
7144 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
7152 /* Re-process all of the fragments looking to convert all of the
7153 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7154 conditional branch or a retw/retw.n, convert this frag to one that
7155 will generate a NOP. In any case close it off with a .fill 0. */
7157 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
7160 xtensa_fix_a0_b_retw_frags (void)
7164 /* When this routine is called, all of the subsections are still intact
7165 so we walk over subsections instead of sections. */
7166 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7170 /* Walk over all of the fragments in a subsection. */
7171 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7173 if (fragP
->fr_type
== rs_machine_dependent
7174 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
7176 if (next_instrs_are_b_retw (fragP
))
7178 if (fragP
->tc_frag_data
.is_no_transform
)
7179 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7181 relax_frag_add_nop (fragP
);
7191 next_instrs_are_b_retw (fragS
*fragP
)
7193 xtensa_opcode opcode
;
7195 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
7196 static xtensa_insnbuf insnbuf
= NULL
;
7197 static xtensa_insnbuf slotbuf
= NULL
;
7198 xtensa_isa isa
= xtensa_default_isa
;
7201 bfd_boolean branch_seen
= FALSE
;
7205 insnbuf
= xtensa_insnbuf_alloc (isa
);
7206 slotbuf
= xtensa_insnbuf_alloc (isa
);
7209 if (next_fragP
== NULL
)
7212 /* Check for the conditional branch. */
7213 xtensa_insnbuf_from_chars
7214 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7215 fmt
= xtensa_format_decode (isa
, insnbuf
);
7216 if (fmt
== XTENSA_UNDEFINED
)
7219 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7221 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
7222 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
7224 branch_seen
= (branch_seen
7225 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
7231 offset
+= xtensa_format_length (isa
, fmt
);
7232 if (offset
== next_fragP
->fr_fix
)
7234 next_fragP
= next_non_empty_frag (next_fragP
);
7238 if (next_fragP
== NULL
)
7241 /* Check for the retw/retw.n. */
7242 xtensa_insnbuf_from_chars
7243 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7244 fmt
= xtensa_format_decode (isa
, insnbuf
);
7246 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
7247 have no problems. */
7248 if (fmt
== XTENSA_UNDEFINED
7249 || xtensa_format_num_slots (isa
, fmt
) != 1)
7252 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
7253 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
7255 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
7262 /* Re-process all of the fragments looking to convert all of the
7263 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
7264 loop end label, convert this frag to one that will generate a NOP.
7265 In any case close it off with a .fill 0. */
7267 static bfd_boolean
next_instr_is_loop_end (fragS
*);
7270 xtensa_fix_b_j_loop_end_frags (void)
7274 /* When this routine is called, all of the subsections are still intact
7275 so we walk over subsections instead of sections. */
7276 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7280 /* Walk over all of the fragments in a subsection. */
7281 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7283 if (fragP
->fr_type
== rs_machine_dependent
7284 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
7286 if (next_instr_is_loop_end (fragP
))
7288 if (fragP
->tc_frag_data
.is_no_transform
)
7289 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
7291 relax_frag_add_nop (fragP
);
7301 next_instr_is_loop_end (fragS
*fragP
)
7303 const fragS
*next_fragP
;
7305 if (next_frag_is_loop_target (fragP
))
7308 next_fragP
= next_non_empty_frag (fragP
);
7309 if (next_fragP
== NULL
)
7312 if (!next_frag_is_loop_target (next_fragP
))
7315 /* If the size is >= 3 then there is more than one instruction here.
7316 The hardware bug will not fire. */
7317 if (next_fragP
->fr_fix
> 3)
7324 /* Re-process all of the fragments looking to convert all of the
7325 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
7326 not MY loop's loop end within 12 bytes, add enough nops here to
7327 make it at least 12 bytes away. In any case close it off with a
7330 static offsetT min_bytes_to_other_loop_end
7331 (fragS
*, fragS
*, offsetT
, offsetT
);
7334 xtensa_fix_close_loop_end_frags (void)
7338 /* When this routine is called, all of the subsections are still intact
7339 so we walk over subsections instead of sections. */
7340 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7344 fragS
*current_target
= NULL
;
7345 offsetT current_offset
= 0;
7347 /* Walk over all of the fragments in a subsection. */
7348 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7350 if (fragP
->fr_type
== rs_machine_dependent
7351 && ((fragP
->fr_subtype
== RELAX_IMMED
)
7352 || ((fragP
->fr_subtype
== RELAX_SLOTS
)
7353 && (fragP
->tc_frag_data
.slot_subtypes
[0]
7356 /* Read it. If the instruction is a loop, get the target. */
7358 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7359 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7360 t_insn
.opcode
) == 1)
7362 /* Get the current fragment target. */
7363 if (fragP
->tc_frag_data
.slot_symbols
[0])
7365 symbolS
*sym
= fragP
->tc_frag_data
.slot_symbols
[0];
7366 current_target
= symbol_get_frag (sym
);
7367 current_offset
= fragP
->fr_offset
;
7373 && fragP
->fr_type
== rs_machine_dependent
7374 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
7377 int bytes_added
= 0;
7379 #define REQUIRED_LOOP_DIVIDING_BYTES 12
7380 /* Max out at 12. */
7381 min_bytes
= min_bytes_to_other_loop_end
7382 (fragP
->fr_next
, current_target
, current_offset
,
7383 REQUIRED_LOOP_DIVIDING_BYTES
);
7385 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
7387 if (fragP
->tc_frag_data
.is_no_transform
)
7388 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
7391 while (min_bytes
+ bytes_added
7392 < REQUIRED_LOOP_DIVIDING_BYTES
)
7396 if (fragP
->fr_var
< length
)
7397 as_fatal (_("fr_var %lu < length %d"),
7398 (long) fragP
->fr_var
, length
);
7401 assemble_nop (length
,
7402 fragP
->fr_literal
+ fragP
->fr_fix
);
7403 fragP
->fr_fix
+= length
;
7404 fragP
->fr_var
-= length
;
7406 bytes_added
+= length
;
7412 assert (fragP
->fr_type
!= rs_machine_dependent
7413 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
7419 static offsetT
unrelaxed_frag_min_size (fragS
*);
7422 min_bytes_to_other_loop_end (fragS
*fragP
,
7423 fragS
*current_target
,
7424 offsetT current_offset
,
7428 fragS
*current_fragP
;
7430 for (current_fragP
= fragP
;
7432 current_fragP
= current_fragP
->fr_next
)
7434 if (current_fragP
->tc_frag_data
.is_loop_target
7435 && current_fragP
!= current_target
)
7436 return offset
+ current_offset
;
7438 offset
+= unrelaxed_frag_min_size (current_fragP
);
7440 if (offset
+ current_offset
>= max_size
)
7448 unrelaxed_frag_min_size (fragS
*fragP
)
7450 offsetT size
= fragP
->fr_fix
;
7452 /* Add fill size. */
7453 if (fragP
->fr_type
== rs_fill
)
7454 size
+= fragP
->fr_offset
;
7461 unrelaxed_frag_max_size (fragS
*fragP
)
7463 offsetT size
= fragP
->fr_fix
;
7464 switch (fragP
->fr_type
)
7467 /* Empty frags created by the obstack allocation scheme
7468 end up with type 0. */
7473 size
+= fragP
->fr_offset
;
7481 /* No further adjustments needed. */
7483 case rs_machine_dependent
:
7484 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
7485 size
+= fragP
->fr_var
;
7488 /* We had darn well better know how big it is. */
7497 /* Re-process all of the fragments looking to convert all
7498 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
7501 1) the instruction size count to the loop end label
7502 is too short (<= 2 instructions),
7503 2) loop has a jump or branch in it
7506 1) workaround_all_short_loops is TRUE
7507 2) The generating loop was a 'loopgtz' or 'loopnez'
7508 3) the instruction size count to the loop end label is too short
7510 then convert this frag (and maybe the next one) to generate a NOP.
7511 In any case close it off with a .fill 0. */
7513 static int count_insns_to_loop_end (fragS
*, bfd_boolean
, int);
7514 static bfd_boolean
branch_before_loop_end (fragS
*);
7517 xtensa_fix_short_loop_frags (void)
7521 /* When this routine is called, all of the subsections are still intact
7522 so we walk over subsections instead of sections. */
7523 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7526 fragS
*current_target
= NULL
;
7527 offsetT current_offset
= 0;
7528 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
7530 /* Walk over all of the fragments in a subsection. */
7531 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7533 /* Check on the current loop. */
7534 if (fragP
->fr_type
== rs_machine_dependent
7535 && ((fragP
->fr_subtype
== RELAX_IMMED
)
7536 || ((fragP
->fr_subtype
== RELAX_SLOTS
)
7537 && (fragP
->tc_frag_data
.slot_subtypes
[0]
7542 /* Read it. If the instruction is a loop, get the target. */
7543 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7544 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7545 t_insn
.opcode
) == 1)
7547 /* Get the current fragment target. */
7548 if (fragP
->tc_frag_data
.slot_symbols
[0])
7550 symbolS
*sym
= fragP
->tc_frag_data
.slot_symbols
[0];
7551 current_target
= symbol_get_frag (sym
);
7552 current_offset
= fragP
->fr_offset
;
7553 current_opcode
= t_insn
.opcode
;
7558 if (fragP
->fr_type
== rs_machine_dependent
7559 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7561 if (count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3) < 3
7562 && (branch_before_loop_end (fragP
->fr_next
)
7563 || (workaround_all_short_loops
7564 && current_opcode
!= XTENSA_UNDEFINED
7565 && current_opcode
!= xtensa_loop_opcode
)))
7567 if (fragP
->tc_frag_data
.is_no_transform
)
7568 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
7570 relax_frag_add_nop (fragP
);
7579 static int unrelaxed_frag_min_insn_count (fragS
*);
7582 count_insns_to_loop_end (fragS
*base_fragP
,
7583 bfd_boolean count_relax_add
,
7586 fragS
*fragP
= NULL
;
7591 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
7593 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
7594 if (insn_count
>= max_count
)
7597 if (count_relax_add
)
7599 if (fragP
->fr_type
== rs_machine_dependent
7600 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7602 /* In order to add the appropriate number of
7603 NOPs, we count an instruction for downstream
7606 if (insn_count
>= max_count
)
7616 unrelaxed_frag_min_insn_count (fragS
*fragP
)
7618 xtensa_isa isa
= xtensa_default_isa
;
7619 static xtensa_insnbuf insnbuf
= NULL
;
7623 if (!fragP
->tc_frag_data
.is_insn
)
7627 insnbuf
= xtensa_insnbuf_alloc (isa
);
7629 /* Decode the fixed instructions. */
7630 while (offset
< fragP
->fr_fix
)
7634 xtensa_insnbuf_from_chars
7635 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7636 fmt
= xtensa_format_decode (isa
, insnbuf
);
7638 if (fmt
== XTENSA_UNDEFINED
)
7640 as_fatal (_("undecodable instruction in instruction frag"));
7643 offset
+= xtensa_format_length (isa
, fmt
);
7651 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
7654 branch_before_loop_end (fragS
*base_fragP
)
7658 for (fragP
= base_fragP
;
7659 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
7660 fragP
= fragP
->fr_next
)
7662 if (unrelaxed_frag_has_b_j (fragP
))
7670 unrelaxed_frag_has_b_j (fragS
*fragP
)
7672 static xtensa_insnbuf insnbuf
= NULL
;
7673 xtensa_isa isa
= xtensa_default_isa
;
7676 if (!fragP
->tc_frag_data
.is_insn
)
7680 insnbuf
= xtensa_insnbuf_alloc (isa
);
7682 /* Decode the fixed instructions. */
7683 while (offset
< fragP
->fr_fix
)
7688 xtensa_insnbuf_from_chars
7689 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7690 fmt
= xtensa_format_decode (isa
, insnbuf
);
7691 if (fmt
== XTENSA_UNDEFINED
)
7694 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7696 xtensa_opcode opcode
=
7697 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
7698 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
7699 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
7702 offset
+= xtensa_format_length (isa
, fmt
);
7708 /* Checks to be made after initial assembly but before relaxation. */
7710 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
7711 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
7714 xtensa_sanity_check (void)
7721 as_where (&file_name
, &line
);
7722 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7726 /* Walk over all of the fragments in a subsection. */
7727 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7729 /* Currently we only check for empty loops here. */
7730 if (fragP
->fr_type
== rs_machine_dependent
7731 && fragP
->fr_subtype
== RELAX_IMMED
)
7733 static xtensa_insnbuf insnbuf
= NULL
;
7736 if (fragP
->fr_opcode
!= NULL
)
7739 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7740 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7741 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
7743 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7744 t_insn
.opcode
) == 1)
7746 if (is_empty_loop (&t_insn
, fragP
))
7748 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7749 as_bad (_("invalid empty loop"));
7751 if (!is_local_forward_loop (&t_insn
, fragP
))
7753 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7754 as_bad (_("loop target does not follow "
7755 "loop instruction in section"));
7762 new_logical_line (file_name
, line
);
7766 #define LOOP_IMMED_OPN 1
7768 /* Return TRUE if the loop target is the next non-zero fragment. */
7771 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
7773 const expressionS
*expr
;
7777 if (insn
->insn_type
!= ITYPE_INSN
)
7780 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
7783 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7786 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7788 if (expr
->X_op
!= O_symbol
)
7791 symbolP
= expr
->X_add_symbol
;
7795 if (symbol_get_frag (symbolP
) == NULL
)
7798 if (S_GET_VALUE (symbolP
) != 0)
7801 /* Walk through the zero-size fragments from this one. If we find
7802 the target fragment, then this is a zero-size loop. */
7804 for (next_fragP
= fragP
->fr_next
;
7806 next_fragP
= next_fragP
->fr_next
)
7808 if (next_fragP
== symbol_get_frag (symbolP
))
7810 if (next_fragP
->fr_fix
!= 0)
7818 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
7820 const expressionS
*expr
;
7824 if (insn
->insn_type
!= ITYPE_INSN
)
7827 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) == 0)
7830 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7833 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7835 if (expr
->X_op
!= O_symbol
)
7838 symbolP
= expr
->X_add_symbol
;
7842 if (symbol_get_frag (symbolP
) == NULL
)
7845 /* Walk through fragments until we find the target.
7846 If we do not find the target, then this is an invalid loop. */
7848 for (next_fragP
= fragP
->fr_next
;
7850 next_fragP
= next_fragP
->fr_next
)
7852 if (next_fragP
== symbol_get_frag (symbolP
))
7860 /* Alignment Functions. */
7863 get_text_align_power (unsigned target_size
)
7868 assert (target_size
<= INT_MAX
);
7869 while (target_size
> power
)
7879 get_text_align_max_fill_size (int align_pow
,
7880 bfd_boolean use_nops
,
7881 bfd_boolean use_no_density
)
7884 return (1 << align_pow
);
7886 return 3 * (1 << align_pow
);
7888 return 1 + (1 << align_pow
);
7892 /* Calculate the minimum bytes of fill needed at "address" to align a
7893 target instruction of size "target_size" so that it does not cross a
7894 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE,
7895 the fill can be an arbitrary number of bytes. Otherwise, the space must
7896 be filled by NOP instructions. */
7899 get_text_align_fill_size (addressT address
,
7902 bfd_boolean use_nops
,
7903 bfd_boolean use_no_density
)
7905 addressT alignment
, fill
, fill_limit
, fill_step
;
7906 bfd_boolean skip_one
= FALSE
;
7908 alignment
= (1 << align_pow
);
7909 assert (target_size
> 0 && alignment
>= (addressT
) target_size
);
7913 fill_limit
= alignment
;
7916 else if (!use_no_density
)
7918 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */
7919 fill_limit
= alignment
* 2;
7925 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */
7926 fill_limit
= alignment
* 3;
7930 /* Try all fill sizes until finding one that works. */
7931 for (fill
= 0; fill
< fill_limit
; fill
+= fill_step
)
7933 if (skip_one
&& fill
== 1)
7935 if ((address
+ fill
) >> align_pow
7936 == (address
+ fill
+ target_size
- 1) >> align_pow
)
7945 branch_align_power (segT sec
)
7947 /* If the Xtensa processor has a fetch width of 8 bytes, and the section
7948 is aligned to at least an 8-byte boundary, then a branch target need
7949 only fit within an 8-byte aligned block of memory to avoid a stall.
7950 Otherwise, try to fit branch targets within 4-byte aligned blocks
7951 (which may be insufficient, e.g., if the section has no alignment, but
7952 it's good enough). */
7953 if (xtensa_fetch_width
== 8)
7955 if (get_recorded_alignment (sec
) >= 3)
7959 assert (xtensa_fetch_width
== 4);
7965 /* This will assert if it is not possible. */
7968 get_text_align_nop_count (offsetT fill_size
, bfd_boolean use_no_density
)
7974 assert (fill_size
% 3 == 0);
7975 return (fill_size
/ 3);
7978 assert (fill_size
!= 1); /* Bad argument. */
7980 while (fill_size
> 1)
7983 if (fill_size
== 2 || fill_size
== 4)
7985 fill_size
-= insn_size
;
7988 assert (fill_size
!= 1); /* Bad algorithm. */
7994 get_text_align_nth_nop_size (offsetT fill_size
,
7996 bfd_boolean use_no_density
)
8003 assert (fill_size
!= 1); /* Bad argument. */
8005 while (fill_size
> 1)
8008 if (fill_size
== 2 || fill_size
== 4)
8010 fill_size
-= insn_size
;
8020 /* For the given fragment, find the appropriate address
8021 for it to begin at if we are using NOPs to align it. */
8024 get_noop_aligned_address (fragS
*fragP
, addressT address
)
8026 /* The rule is: get next fragment's FIRST instruction. Find
8027 the smallest number of bytes that need to be added to
8028 ensure that the next fragment's FIRST instruction will fit
8031 E.G., 2 bytes : 0, 1, 2 mod 4
8034 If the FIRST instruction MIGHT be relaxed,
8035 assume that it will become a 3-byte instruction.
8037 Note again here that LOOP instructions are not bundleable,
8038 and this relaxation only applies to LOOP opcodes. */
8041 int first_insn_size
;
8043 addressT pre_opcode_bytes
;
8046 xtensa_opcode opcode
;
8047 bfd_boolean is_loop
;
8049 assert (fragP
->fr_type
== rs_machine_dependent
);
8050 assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
8052 /* Find the loop frag. */
8053 first_insn
= next_non_empty_frag (fragP
);
8054 /* Now find the first insn frag. */
8055 first_insn
= next_non_empty_frag (first_insn
);
8057 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
8059 loop_insn_size
= xg_get_single_size (opcode
);
8061 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
8062 pre_opcode_bytes
+= loop_insn_size
;
8064 /* For loops, the alignment depends on the size of the
8065 instruction following the loop, not the LOOP instruction. */
8067 if (first_insn
== NULL
)
8070 assert (first_insn
->tc_frag_data
.is_first_loop_insn
);
8072 first_insn_size
= frag_format_size (first_insn
);
8074 if (first_insn_size
== 2 || first_insn_size
== XTENSA_UNDEFINED
)
8075 first_insn_size
= 3; /* ISA specifies this */
8077 /* If it was 8, then we'll need a larger alignment for the section. */
8078 align_power
= get_text_align_power (first_insn_size
);
8079 record_alignment (now_seg
, align_power
);
8081 fill_size
= get_text_align_fill_size
8082 (address
+ pre_opcode_bytes
, align_power
, first_insn_size
, TRUE
,
8083 fragP
->tc_frag_data
.is_no_density
);
8085 return address
+ fill_size
;
8089 /* 3 mechanisms for relaxing an alignment:
8091 Align to a power of 2.
8092 Align so the next fragment's instruction does not cross a word boundary.
8093 Align the current instruction so that if the next instruction
8094 were 3 bytes, it would not cross a word boundary.
8098 zeros - This is easy; always insert zeros.
8099 nops - 3-byte and 2-byte instructions
8103 >=5 : 3-byte instruction + fn (n-3)
8104 widening - widen previous instructions. */
8107 get_aligned_diff (fragS
*fragP
, addressT address
, offsetT
*max_diff
)
8109 addressT target_address
, loop_insn_offset
;
8111 xtensa_opcode loop_opcode
;
8112 bfd_boolean is_loop
;
8115 offsetT branch_align
;
8117 assert (fragP
->fr_type
== rs_machine_dependent
);
8118 switch (fragP
->fr_subtype
)
8120 case RELAX_DESIRE_ALIGN
:
8121 target_size
= next_frag_format_size (fragP
);
8122 if (target_size
== XTENSA_UNDEFINED
)
8124 align_power
= branch_align_power (now_seg
);
8125 branch_align
= 1 << align_power
;
8126 /* Don't count on the section alignment being as large as the target. */
8127 if (target_size
> branch_align
)
8128 target_size
= branch_align
;
8129 opt_diff
= get_text_align_fill_size (address
, align_power
,
8130 target_size
, FALSE
, FALSE
);
8132 *max_diff
= (opt_diff
+ branch_align
8133 - (target_size
+ ((address
+ opt_diff
) % branch_align
)));
8134 assert (*max_diff
>= opt_diff
);
8137 case RELAX_ALIGN_NEXT_OPCODE
:
8138 target_size
= next_frag_format_size (fragP
);
8139 loop_insn_offset
= 0;
8140 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
8143 /* If the loop has been expanded then the LOOP instruction
8144 could be at an offset from this fragment. */
8145 if (next_non_empty_frag(fragP
)->tc_frag_data
.slot_subtypes
[0]
8147 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
8149 if (target_size
== 2)
8150 target_size
= 3; /* ISA specifies this */
8152 /* In an ideal world, which is what we are shooting for here,
8153 we wouldn't need to use any NOPs immediately prior to the
8154 LOOP instruction. If this approach fails, relax_frag_loop_align
8155 will call get_noop_aligned_address. */
8157 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
8158 align_power
= get_text_align_power (target_size
),
8159 opt_diff
= get_text_align_fill_size (target_address
, align_power
,
8160 target_size
, FALSE
, FALSE
);
8162 *max_diff
= xtensa_fetch_width
8163 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
8164 - target_size
+ opt_diff
;
8165 assert (*max_diff
>= opt_diff
);
8176 /* md_relax_frag Hook and Helper Functions. */
8178 static long relax_frag_loop_align (fragS
*, long);
8179 static long relax_frag_for_align (fragS
*, long);
8180 static long relax_frag_immed
8181 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
8184 /* Return the number of bytes added to this fragment, given that the
8185 input has been stretched already by "stretch". */
8188 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
8190 xtensa_isa isa
= xtensa_default_isa
;
8191 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
8192 long new_stretch
= 0;
8196 static xtensa_insnbuf vbuf
= NULL
;
8197 int slot
, num_slots
;
8200 as_where (&file_name
, &line
);
8201 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8203 fragP
->tc_frag_data
.unreported_expansion
= 0;
8205 switch (fragP
->fr_subtype
)
8207 case RELAX_ALIGN_NEXT_OPCODE
:
8208 /* Always convert. */
8209 if (fragP
->tc_frag_data
.relax_seen
)
8210 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
8213 case RELAX_LOOP_END
:
8217 case RELAX_LOOP_END_ADD_NOP
:
8218 /* Add a NOP and switch to .fill 0. */
8219 new_stretch
= relax_frag_add_nop (fragP
);
8223 case RELAX_DESIRE_ALIGN
:
8224 /* Do nothing. The narrowing before this frag will either align
8229 case RELAX_LITERAL_FINAL
:
8232 case RELAX_LITERAL_NR
:
8234 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
8235 assert (unreported
== lit_size
);
8236 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
8237 fragP
->fr_var
-= lit_size
;
8238 fragP
->fr_fix
+= lit_size
;
8244 vbuf
= xtensa_insnbuf_alloc (isa
);
8246 xtensa_insnbuf_from_chars
8247 (isa
, vbuf
, (unsigned char *) fragP
->fr_opcode
, 0);
8248 fmt
= xtensa_format_decode (isa
, vbuf
);
8249 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8251 for (slot
= 0; slot
< num_slots
; slot
++)
8253 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
8256 if (fragP
->tc_frag_data
.relax_seen
)
8257 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8261 case RELAX_IMMED_STEP1
:
8262 case RELAX_IMMED_STEP2
:
8263 /* Place the immediate. */
8264 new_stretch
+= relax_frag_immed
8265 (now_seg
, fragP
, stretch
,
8266 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8267 fmt
, slot
, stretched_p
, FALSE
);
8271 /* This is OK; see the note in xg_assemble_vliw_tokens. */
8277 case RELAX_LITERAL_POOL_BEGIN
:
8278 case RELAX_LITERAL_POOL_END
:
8279 case RELAX_MAYBE_UNREACHABLE
:
8280 case RELAX_MAYBE_DESIRE_ALIGN
:
8281 /* No relaxation required. */
8284 case RELAX_FILL_NOP
:
8285 case RELAX_UNREACHABLE
:
8286 if (fragP
->tc_frag_data
.relax_seen
)
8287 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8291 as_bad (_("bad relaxation state"));
8294 /* Tell gas we need another relaxation pass. */
8295 if (! fragP
->tc_frag_data
.relax_seen
)
8297 fragP
->tc_frag_data
.relax_seen
= TRUE
;
8301 new_logical_line (file_name
, line
);
8307 relax_frag_loop_align (fragS
*fragP
, long stretch
)
8309 addressT old_address
, old_next_address
, old_size
;
8310 addressT new_address
, new_next_address
, new_size
;
8313 /* All the frags with relax_frag_for_alignment prior to this one in the
8314 section have been done, hopefully eliminating the need for a NOP here.
8315 But, this will put it in if necessary. */
8317 /* Calculate the old address of this fragment and the next fragment. */
8318 old_address
= fragP
->fr_address
- stretch
;
8319 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
8320 fragP
->tc_frag_data
.text_expansion
[0]);
8321 old_size
= old_next_address
- old_address
;
8323 /* Calculate the new address of this fragment and the next fragment. */
8324 new_address
= fragP
->fr_address
;
8326 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
8327 new_size
= new_next_address
- new_address
;
8329 growth
= new_size
- old_size
;
8331 /* Fix up the text_expansion field and return the new growth. */
8332 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
8337 /* Add a NOP instruction. */
8340 relax_frag_add_nop (fragS
*fragP
)
8342 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
8343 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
8344 assemble_nop (length
, nop_buf
);
8345 fragP
->tc_frag_data
.is_insn
= TRUE
;
8347 if (fragP
->fr_var
< length
)
8349 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP
->fr_var
, length
);
8353 fragP
->fr_fix
+= length
;
8354 fragP
->fr_var
-= length
;
8359 static long future_alignment_required (fragS
*, long);
8362 relax_frag_for_align (fragS
*fragP
, long stretch
)
8364 /* Overview of the relaxation procedure for alignment:
8365 We can widen with NOPs or by widening instructions or by filling
8366 bytes after jump instructions. Find the opportune places and widen
8367 them if necessary. */
8372 assert (fragP
->fr_subtype
== RELAX_FILL_NOP
8373 || fragP
->fr_subtype
== RELAX_UNREACHABLE
8374 || (fragP
->fr_subtype
== RELAX_SLOTS
8375 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
8377 stretch_me
= future_alignment_required (fragP
, stretch
);
8378 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
8384 /* We expanded on a previous pass. Can we shrink now? */
8385 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
8386 if (shrink
<= stretch
&& stretch
> 0)
8388 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8394 /* Below here, diff > 0. */
8395 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8401 /* Return the address of the next frag that should be aligned.
8403 By "address" we mean the address it _would_ be at if there
8404 is no action taken to align it between here and the target frag.
8405 In other words, if no narrows and no fill nops are used between
8406 here and the frag to align, _even_if_ some of the frags we use
8407 to align targets have already expanded on a previous relaxation
8410 Also, count each frag that may be used to help align the target.
8412 Return 0 if there are no frags left in the chain that need to be
8416 find_address_of_next_align_frag (fragS
**fragPP
,
8420 bfd_boolean
*paddable
)
8422 fragS
*fragP
= *fragPP
;
8423 addressT address
= fragP
->fr_address
;
8425 /* Do not reset the counts to 0. */
8429 /* Limit this to a small search. */
8430 if (*widens
>= (int) xtensa_fetch_width
)
8435 address
+= fragP
->fr_fix
;
8437 if (fragP
->fr_type
== rs_fill
)
8438 address
+= fragP
->fr_offset
* fragP
->fr_var
;
8439 else if (fragP
->fr_type
== rs_machine_dependent
)
8441 switch (fragP
->fr_subtype
)
8443 case RELAX_UNREACHABLE
:
8447 case RELAX_FILL_NOP
:
8449 if (!fragP
->tc_frag_data
.is_no_density
)
8454 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8459 address
+= total_frag_text_expansion (fragP
);;
8463 address
+= fragP
->tc_frag_data
.text_expansion
[0];
8466 case RELAX_ALIGN_NEXT_OPCODE
:
8467 case RELAX_DESIRE_ALIGN
:
8471 case RELAX_MAYBE_UNREACHABLE
:
8472 case RELAX_MAYBE_DESIRE_ALIGN
:
8477 /* Just punt if we don't know the type. */
8484 /* Just punt if we don't know the type. */
8488 fragP
= fragP
->fr_next
;
8496 static long bytes_to_stretch (fragS
*, int, int, int, int);
8499 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
8501 fragS
*this_frag
= fragP
;
8505 int narrow_nops
= 0;
8506 bfd_boolean paddable
= FALSE
;
8507 offsetT local_opt_diff
;
8510 int stretch_amount
= 0;
8511 int local_stretch_amount
;
8512 int global_stretch_amount
;
8514 address
= find_address_of_next_align_frag
8515 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
8519 if (this_frag
->tc_frag_data
.is_aligning_branch
)
8520 this_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
8522 frag_wane (this_frag
);
8526 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
8527 opt_diff
= local_opt_diff
;
8528 assert (opt_diff
>= 0);
8529 assert (max_diff
>= opt_diff
);
8534 fragP
= fragP
->fr_next
;
8536 while (fragP
&& opt_diff
< max_diff
&& address
)
8538 /* We only use these to determine if we can exit early
8539 because there will be plenty of ways to align future
8541 int glob_widens
= 0;
8544 bfd_boolean glob_pad
= 0;
8545 address
= find_address_of_next_align_frag
8546 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
8547 /* If there is a padable portion, then skip. */
8548 if (glob_pad
|| glob_widens
>= (1 << branch_align_power (now_seg
)))
8553 offsetT next_m_diff
;
8554 offsetT next_o_diff
;
8556 /* Downrange frags haven't had stretch added to them yet. */
8559 /* The address also includes any text expansion from this
8560 frag in a previous pass, but we don't want that. */
8561 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
8563 /* Assume we are going to move at least opt_diff. In
8564 reality, we might not be able to, but assuming that
8565 we will helps catch cases where moving opt_diff pushes
8566 the next target from aligned to unaligned. */
8567 address
+= opt_diff
;
8569 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
8571 /* Now cleanup for the adjustments to address. */
8572 next_o_diff
+= opt_diff
;
8573 next_m_diff
+= opt_diff
;
8574 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
8575 opt_diff
= next_o_diff
;
8576 if (next_m_diff
< max_diff
)
8577 max_diff
= next_m_diff
;
8578 fragP
= fragP
->fr_next
;
8582 /* If there are enough wideners in between, do it. */
8585 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
8587 assert (opt_diff
<= UNREACHABLE_MAX_WIDTH
);
8592 local_stretch_amount
8593 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8594 num_widens
, local_opt_diff
);
8595 global_stretch_amount
8596 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8597 num_widens
, opt_diff
);
8598 /* If the condition below is true, then the frag couldn't
8599 stretch the correct amount for the global case, so we just
8600 optimize locally. We'll rely on the subsequent frags to get
8601 the correct alignment in the global case. */
8602 if (global_stretch_amount
< local_stretch_amount
)
8603 stretch_amount
= local_stretch_amount
;
8605 stretch_amount
= global_stretch_amount
;
8607 if (this_frag
->fr_subtype
== RELAX_SLOTS
8608 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8609 assert (stretch_amount
<= 1);
8610 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8612 if (this_frag
->tc_frag_data
.is_no_density
)
8613 assert (stretch_amount
== 3 || stretch_amount
== 0);
8615 assert (stretch_amount
<= 3);
8618 return stretch_amount
;
8622 /* The idea: widen everything you can to get a target or loop aligned,
8623 then start using NOPs.
8625 When we must have a NOP, here is a table of how we decide
8626 (so you don't have to fight through the control flow below):
8628 wide_nops = the number of wide NOPs available for aligning
8629 narrow_nops = the number of narrow NOPs available for aligning
8630 (a subset of wide_nops)
8631 widens = the number of narrow instructions that should be widened
8638 b 0 1 1 (case 3a makes this case unnecessary)
8641 c 0 1 2 (case 4a makes this case unnecessary)
8644 c 0 2 1 (case 5b makes this case unnecessary)
8647 c 0 1 4 (case 6b makes this case unneccesary)
8648 d 1 1 1 (case 6a makes this case unnecessary)
8649 e 0 2 2 (case 6a makes this case unnecessary)
8650 f 0 3 0 (case 6a makes this case unnecessary)
8653 c 1 1 2 (case 7b makes this case unnecessary)
8654 d 0 1 5 (case 7a makes this case unnecessary)
8655 e 0 2 3 (case 7b makes this case unnecessary)
8656 f 0 3 1 (case 7b makes this case unnecessary)
8657 g 1 2 1 (case 7b makes this case unnecessary)
8661 bytes_to_stretch (fragS
*this_frag
,
8667 int bytes_short
= desired_diff
- num_widens
;
8669 assert (desired_diff
>= 0 && desired_diff
< 8);
8670 if (desired_diff
== 0)
8673 assert (wide_nops
> 0 || num_widens
> 0);
8675 /* Always prefer widening to NOP-filling. */
8676 if (bytes_short
< 0)
8678 /* There are enough RELAX_NARROW frags after this one
8679 to align the target without widening this frag in any way. */
8683 if (bytes_short
== 0)
8685 /* Widen every narrow between here and the align target
8686 and the align target will be properly aligned. */
8687 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8693 /* From here we will need at least one NOP to get an alignment.
8694 However, we may not be able to align at all, in which case,
8696 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8698 switch (desired_diff
)
8703 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 1)
8704 return 2; /* case 2 */
8710 return 3; /* case 3a */
8712 if (num_widens
>= 1 && wide_nops
== 1)
8713 return 3; /* case 4a */
8714 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 2)
8715 return 2; /* case 4b */
8718 if (num_widens
>= 2 && wide_nops
== 1)
8719 return 3; /* case 5a */
8720 /* We will need two nops. Are there enough nops
8721 between here and the align target? */
8722 if (wide_nops
< 2 || narrow_nops
== 0)
8724 /* Are there other nops closer that can serve instead? */
8725 if (wide_nops
> 2 && narrow_nops
> 1)
8727 /* Take the density one first, because there might not be
8728 another density one available. */
8729 if (!this_frag
->tc_frag_data
.is_no_density
)
8730 return 2; /* case 5b narrow */
8732 return 3; /* case 5b wide */
8736 return 3; /* case 6a */
8737 else if (num_widens
>= 3 && wide_nops
== 1)
8738 return 3; /* case 6b */
8741 if (wide_nops
== 1 && num_widens
>= 4)
8742 return 3; /* case 7a */
8743 else if (wide_nops
== 2 && num_widens
>= 1)
8744 return 3; /* case 7b */
8752 /* We will need a NOP no matter what, but should we widen
8753 this instruction to help?
8755 This is a RELAX_FRAG_NARROW frag. */
8756 switch (desired_diff
)
8765 if (wide_nops
>= 1 && num_widens
== 1)
8766 return 1; /* case 4a */
8769 if (wide_nops
>= 1 && num_widens
== 2)
8770 return 1; /* case 5a */
8774 return 0; /* case 6a */
8775 else if (wide_nops
>= 1 && num_widens
== 3)
8776 return 1; /* case 6b */
8779 if (wide_nops
>= 1 && num_widens
== 4)
8780 return 1; /* case 7a */
8781 else if (wide_nops
>= 2 && num_widens
== 1)
8782 return 1; /* case 7b */
8795 relax_frag_immed (segT segP
,
8802 bfd_boolean estimate_only
)
8806 bfd_boolean negatable_branch
= FALSE
;
8807 bfd_boolean branch_jmp_to_next
= FALSE
;
8808 bfd_boolean wide_insn
= FALSE
;
8809 xtensa_isa isa
= xtensa_default_isa
;
8811 offsetT frag_offset
;
8814 int num_text_bytes
, num_literal_bytes
;
8815 int literal_diff
, total_text_diff
, this_text_diff
, first
;
8817 assert (fragP
->fr_opcode
!= NULL
);
8819 xg_clear_vinsn (&cur_vinsn
);
8820 vinsn_from_chars (&cur_vinsn
, fragP
->fr_opcode
);
8821 if (xtensa_format_num_slots (isa
, fmt
) > 1)
8824 tinsn
= cur_vinsn
.slots
[slot
];
8825 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
8827 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
))
8830 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
8831 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
8833 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
8835 old_size
= xtensa_format_length (isa
, fmt
);
8837 /* Special case: replace a branch to the next instruction with a NOP.
8838 This is required to work around a hardware bug in T1040.0 and also
8839 serves as an optimization. */
8841 if (branch_jmp_to_next
8842 && ((old_size
== 2) || (old_size
== 3))
8843 && !next_frag_is_loop_target (fragP
))
8846 /* Here is the fun stuff: Get the immediate field from this
8847 instruction. If it fits, we are done. If not, find the next
8848 instruction sequence that fits. */
8850 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
8851 istack_init (&istack
);
8852 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
8853 min_steps
, stretch
);
8854 if (num_steps
< min_steps
)
8856 as_fatal (_("internal error: relaxation failed"));
8860 if (num_steps
> RELAX_IMMED_MAXSTEPS
)
8862 as_fatal (_("internal error: relaxation requires too many steps"));
8866 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
8868 /* Figure out the number of bytes needed. */
8870 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
8872 num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
8874 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
8876 num_text_bytes
= get_num_stack_text_bytes (&istack
);
8879 num_text_bytes
+= old_size
;
8880 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
8881 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
8883 total_text_diff
= num_text_bytes
- old_size
;
8884 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
8886 /* It MUST get larger. If not, we could get an infinite loop. */
8887 assert (num_text_bytes
>= 0);
8888 assert (literal_diff
>= 0);
8889 assert (total_text_diff
>= 0);
8891 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
8892 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
8893 assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
8894 assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
8896 /* Find the associated expandable literal for this. */
8897 if (literal_diff
!= 0)
8899 lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
8902 assert (literal_diff
== 4);
8903 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
8905 /* We expect that the literal section state has NOT been
8907 assert (lit_fragP
->fr_type
== rs_machine_dependent
8908 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
8909 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
8911 /* We need to mark this section for another iteration
8917 if (negatable_branch
&& istack
.ninsn
> 1)
8918 update_next_frag_state (fragP
);
8920 return this_text_diff
;
8924 /* md_convert_frag Hook and Helper Functions. */
8926 static void convert_frag_align_next_opcode (fragS
*);
8927 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
8928 static void convert_frag_fill_nop (fragS
*);
8929 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
8932 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
8934 static xtensa_insnbuf vbuf
= NULL
;
8935 xtensa_isa isa
= xtensa_default_isa
;
8942 as_where (&file_name
, &line
);
8943 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
8945 switch (fragp
->fr_subtype
)
8947 case RELAX_ALIGN_NEXT_OPCODE
:
8948 /* Always convert. */
8949 convert_frag_align_next_opcode (fragp
);
8952 case RELAX_DESIRE_ALIGN
:
8953 /* Do nothing. If not aligned already, too bad. */
8957 case RELAX_LITERAL_FINAL
:
8962 vbuf
= xtensa_insnbuf_alloc (isa
);
8964 xtensa_insnbuf_from_chars
8965 (isa
, vbuf
, (unsigned char *) fragp
->fr_opcode
, 0);
8966 fmt
= xtensa_format_decode (isa
, vbuf
);
8967 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8969 for (slot
= 0; slot
< num_slots
; slot
++)
8971 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
8974 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
8978 case RELAX_IMMED_STEP1
:
8979 case RELAX_IMMED_STEP2
:
8980 /* Place the immediate. */
8983 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8988 /* This is OK because some slots could have
8989 relaxations and others have none. */
8995 case RELAX_UNREACHABLE
:
8996 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
8997 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
8998 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
9002 case RELAX_MAYBE_UNREACHABLE
:
9003 case RELAX_MAYBE_DESIRE_ALIGN
:
9007 case RELAX_FILL_NOP
:
9008 convert_frag_fill_nop (fragp
);
9011 case RELAX_LITERAL_NR
:
9012 if (use_literal_section
)
9014 /* This should have been handled during relaxation. When
9015 relaxing a code segment, literals sometimes need to be
9016 added to the corresponding literal segment. If that
9017 literal segment has already been relaxed, then we end up
9018 in this situation. Marking the literal segments as data
9019 would make this happen less often (since GAS always relaxes
9020 code before data), but we could still get into trouble if
9021 there are instructions in a segment that is not marked as
9022 containing code. Until we can implement a better solution,
9023 cheat and adjust the addresses of all the following frags.
9024 This could break subsequent alignments, but the linker's
9025 literal coalescing will do that anyway. */
9028 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
9029 assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
9030 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
9033 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
9037 as_bad (_("invalid relaxation fragment result"));
9042 new_logical_line (file_name
, line
);
9047 convert_frag_align_next_opcode (fragS
*fragp
)
9049 char *nop_buf
; /* Location for Writing. */
9050 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
9051 addressT aligned_address
;
9055 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
9057 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
9058 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
9059 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
9061 for (nop
= 0; nop
< nop_count
; nop
++)
9064 nop_size
= get_text_align_nth_nop_size (fill_size
, nop
, use_no_density
);
9066 assemble_nop (nop_size
, nop_buf
);
9067 nop_buf
+= nop_size
;
9070 fragp
->fr_fix
+= fill_size
;
9071 fragp
->fr_var
-= fill_size
;
9076 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
9078 TInsn tinsn
, single_target
;
9079 xtensa_format single_fmt
;
9080 int size
, old_size
, diff
;
9081 offsetT frag_offset
;
9084 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
9086 if (fragP
->tc_frag_data
.is_aligning_branch
== 1)
9088 assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
9089 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
9090 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
9095 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
9097 /* No conversion. */
9102 assert (fragP
->fr_opcode
!= NULL
);
9104 /* Frags in this relaxation state should only contain
9105 single instruction bundles. */
9106 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
9108 /* Just convert it to a wide form.... */
9110 old_size
= xg_get_single_size (tinsn
.opcode
);
9112 tinsn_init (&single_target
);
9113 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9115 if (! xg_is_single_relaxable_insn (&tinsn
, &single_target
, FALSE
))
9117 as_bad (_("unable to widen instruction"));
9121 size
= xg_get_single_size (single_target
.opcode
);
9122 single_fmt
= xg_get_single_format (single_target
.opcode
);
9124 xg_emit_insn_to_buf (&single_target
, single_fmt
, fragP
->fr_opcode
,
9125 fragP
, frag_offset
, TRUE
);
9127 diff
= size
- old_size
;
9129 assert (diff
<= fragP
->fr_var
);
9130 fragP
->fr_var
-= diff
;
9131 fragP
->fr_fix
+= diff
;
9139 convert_frag_fill_nop (fragS
*fragP
)
9141 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
9142 int size
= fragP
->tc_frag_data
.text_expansion
[0];
9143 assert ((unsigned) size
== (fragP
->fr_next
->fr_address
9144 - fragP
->fr_address
- fragP
->fr_fix
));
9147 /* No conversion. */
9151 assemble_nop (size
, loc
);
9152 fragP
->tc_frag_data
.is_insn
= TRUE
;
9153 fragP
->fr_var
-= size
;
9154 fragP
->fr_fix
+= size
;
9159 static fixS
*fix_new_exp_in_seg
9160 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
9161 bfd_reloc_code_real_type
);
9162 static void convert_frag_immed_finish_loop (segT
, fragS
*, TInsn
*);
9165 convert_frag_immed (segT segP
,
9171 char *immed_instr
= fragP
->fr_opcode
;
9173 bfd_boolean expanded
= FALSE
;
9174 bfd_boolean branch_jmp_to_next
= FALSE
;
9175 char *fr_opcode
= fragP
->fr_opcode
;
9176 xtensa_isa isa
= xtensa_default_isa
;
9177 bfd_boolean wide_insn
= FALSE
;
9179 bfd_boolean is_loop
;
9181 assert (fr_opcode
!= NULL
);
9183 xg_clear_vinsn (&cur_vinsn
);
9185 vinsn_from_chars (&cur_vinsn
, fr_opcode
);
9186 if (xtensa_format_num_slots (isa
, fmt
) > 1)
9189 orig_tinsn
= cur_vinsn
.slots
[slot
];
9190 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
9192 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
9194 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9195 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
9197 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
9199 /* Conversion just inserts a NOP and marks the fix as completed. */
9200 bytes
= xtensa_format_length (isa
, fmt
);
9203 cur_vinsn
.slots
[slot
].opcode
=
9204 xtensa_format_slot_nop_opcode (isa
, cur_vinsn
.format
, slot
);
9205 cur_vinsn
.slots
[slot
].ntok
= 0;
9209 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
9210 assert (bytes
== 2 || bytes
== 3);
9211 build_nop (&cur_vinsn
.slots
[0], bytes
);
9212 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
9214 vinsn_to_insnbuf (&cur_vinsn
, fr_opcode
, frag_now
, FALSE
);
9215 xtensa_insnbuf_to_chars
9216 (isa
, cur_vinsn
.insnbuf
, (unsigned char *) fr_opcode
, 0);
9221 /* Here is the fun stuff: Get the immediate field from this
9222 instruction. If it fits, we're done. If not, find the next
9223 instruction sequence that fits. */
9227 symbolS
*lit_sym
= NULL
;
9229 int target_offset
= 0;
9232 symbolS
*gen_label
= NULL
;
9233 offsetT frag_offset
;
9234 bfd_boolean first
= TRUE
;
9235 bfd_boolean last_is_jump
;
9237 /* It does not fit. Find something that does and
9238 convert immediately. */
9239 frag_offset
= fr_opcode
- fragP
->fr_literal
;
9240 istack_init (&istack
);
9241 xg_assembly_relax (&istack
, &orig_tinsn
,
9242 segP
, fragP
, frag_offset
, min_steps
, 0);
9244 old_size
= xtensa_format_length (isa
, fmt
);
9246 /* Assemble this right inline. */
9248 /* First, create the mapping from a label name to the REAL label. */
9250 for (i
= 0; i
< istack
.ninsn
; i
++)
9252 TInsn
*tinsn
= &istack
.insn
[i
];
9255 switch (tinsn
->insn_type
)
9258 if (lit_sym
!= NULL
)
9259 as_bad (_("multiple literals in expansion"));
9260 /* First find the appropriate space in the literal pool. */
9261 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9262 if (lit_frag
== NULL
)
9263 as_bad (_("no registered fragment for literal"));
9264 if (tinsn
->ntok
!= 1)
9265 as_bad (_("number of literal tokens != 1"));
9267 /* Set the literal symbol and add a fixup. */
9268 lit_sym
= lit_frag
->fr_symbol
;
9272 if (align_targets
&& !is_loop
)
9274 fragS
*unreach
= fragP
->fr_next
;
9275 while (!(unreach
->fr_type
== rs_machine_dependent
9276 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9277 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
9279 unreach
= unreach
->fr_next
;
9282 assert (unreach
->fr_type
== rs_machine_dependent
9283 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9284 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
9286 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
9288 assert (gen_label
== NULL
);
9289 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
9290 fr_opcode
- fragP
->fr_literal
9291 + target_offset
, fragP
);
9295 if (first
&& wide_insn
)
9297 target_offset
+= xtensa_format_length (isa
, fmt
);
9299 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9300 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9303 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9310 last_is_jump
= FALSE
;
9311 for (i
= 0; i
< istack
.ninsn
; i
++)
9313 TInsn
*tinsn
= &istack
.insn
[i
];
9317 bfd_reloc_code_real_type reloc_type
;
9319 switch (tinsn
->insn_type
)
9322 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9323 /* Already checked. */
9324 assert (lit_frag
!= NULL
);
9325 assert (lit_sym
!= NULL
);
9326 assert (tinsn
->ntok
== 1);
9328 target_seg
= S_GET_SEGMENT (lit_sym
);
9329 assert (target_seg
);
9330 if (tinsn
->tok
[0].X_op
== O_pltrel
)
9331 reloc_type
= BFD_RELOC_XTENSA_PLT
;
9333 reloc_type
= BFD_RELOC_32
;
9334 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
9335 &tinsn
->tok
[0], FALSE
, reloc_type
);
9342 xg_resolve_labels (tinsn
, gen_label
);
9343 xg_resolve_literals (tinsn
, lit_sym
);
9344 if (wide_insn
&& first
)
9347 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9349 tinsn
->record_fix
= TRUE
;
9350 cur_vinsn
.slots
[slot
] = *tinsn
;
9354 cur_vinsn
.slots
[slot
].opcode
=
9355 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
9356 cur_vinsn
.slots
[slot
].ntok
= 0;
9357 cur_vinsn
.slots
[slot
].record_fix
= FALSE
;
9359 vinsn_to_insnbuf (&cur_vinsn
, immed_instr
, fragP
, TRUE
);
9360 xtensa_insnbuf_to_chars (isa
, cur_vinsn
.insnbuf
,
9361 (unsigned char *) immed_instr
, 0);
9362 fragP
->tc_frag_data
.is_insn
= TRUE
;
9363 size
= xtensa_format_length (isa
, fmt
);
9364 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9366 xtensa_format single_fmt
=
9367 xg_get_single_format (tinsn
->opcode
);
9370 (tinsn
, single_fmt
, immed_instr
+ size
, fragP
,
9371 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
9372 size
+= xg_get_single_size (tinsn
->opcode
);
9377 xtensa_format single_format
;
9378 size
= xg_get_single_size (tinsn
->opcode
);
9379 single_format
= xg_get_single_format (tinsn
->opcode
);
9380 xg_emit_insn_to_buf (tinsn
, single_format
, immed_instr
,
9382 immed_instr
- fragP
->fr_literal
, TRUE
);
9384 immed_instr
+= size
;
9390 diff
= total_size
- old_size
;
9394 assert (diff
<= fragP
->fr_var
);
9395 fragP
->fr_var
-= diff
;
9396 fragP
->fr_fix
+= diff
;
9399 /* Check for undefined immediates in LOOP instructions. */
9403 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
9404 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9406 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9409 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
9410 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9412 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9417 if (expanded
&& xtensa_opcode_is_loop (isa
, orig_tinsn
.opcode
) == 1)
9418 convert_frag_immed_finish_loop (segP
, fragP
, &orig_tinsn
);
9420 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
9422 /* Add an expansion note on the expanded instruction. */
9423 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
9424 &orig_tinsn
.tok
[0], TRUE
,
9425 BFD_RELOC_XTENSA_ASM_EXPAND
);
9430 /* Add a new fix expression into the desired segment. We have to
9431 switch to that segment to do this. */
9434 fix_new_exp_in_seg (segT new_seg
,
9441 bfd_reloc_code_real_type r_type
)
9445 subsegT subseg
= now_subseg
;
9447 assert (new_seg
!= 0);
9448 subseg_set (new_seg
, new_subseg
);
9450 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
9451 subseg_set (seg
, subseg
);
9456 /* Relax a loop instruction so that it can span loop >256 bytes.
9462 addi as, as, lo8 (label-.L1)
9463 addmi as, as, mid8 (label-.L1)
9474 convert_frag_immed_finish_loop (segT segP
, fragS
*fragP
, TInsn
*tinsn
)
9479 unsigned long target
;
9480 static xtensa_insnbuf insnbuf
= NULL
;
9481 unsigned int loop_length
, loop_length_hi
, loop_length_lo
;
9482 xtensa_isa isa
= xtensa_default_isa
;
9483 addressT loop_offset
;
9484 addressT addi_offset
= 9;
9485 addressT addmi_offset
= 12;
9490 insnbuf
= xtensa_insnbuf_alloc (isa
);
9492 /* Get the loop offset. */
9493 loop_offset
= get_expanded_loop_offset (tinsn
->opcode
);
9495 /* Validate that there really is a LOOP at the loop_offset. Because
9496 loops are not bundleable, we can assume that the instruction will be
9498 tinsn_from_chars (&loop_insn
, fragP
->fr_opcode
+ loop_offset
, 0);
9499 tinsn_immed_from_frag (&loop_insn
, fragP
, 0);
9501 assert (xtensa_opcode_is_loop (isa
, loop_insn
.opcode
) == 1);
9502 addi_offset
+= loop_offset
;
9503 addmi_offset
+= loop_offset
;
9505 assert (tinsn
->ntok
== 2);
9506 if (tinsn
->tok
[1].X_op
== O_constant
)
9507 target
= tinsn
->tok
[1].X_add_number
;
9508 else if (tinsn
->tok
[1].X_op
== O_symbol
)
9510 /* Find the fragment. */
9511 symbolS
*sym
= tinsn
->tok
[1].X_add_symbol
;
9512 assert (S_GET_SEGMENT (sym
) == segP
9513 || S_GET_SEGMENT (sym
) == absolute_section
);
9514 target
= (S_GET_VALUE (sym
) + tinsn
->tok
[1].X_add_number
);
9518 as_bad (_("invalid expression evaluation type %d"), tinsn
->tok
[1].X_op
);
9523 know (symbolP
->sy_frag
);
9524 know (!(S_GET_SEGMENT (symbolP
) == absolute_section
)
9525 || symbol_get_frag (symbolP
) == &zero_address_frag
);
9527 loop_length
= target
- (fragP
->fr_address
+ fragP
->fr_fix
);
9528 loop_length_hi
= loop_length
& ~0x0ff;
9529 loop_length_lo
= loop_length
& 0x0ff;
9530 if (loop_length_lo
>= 128)
9532 loop_length_lo
-= 256;
9533 loop_length_hi
+= 256;
9536 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
9537 32512. If the loop is larger than that, then we just fail. */
9538 if (loop_length_hi
> 32512)
9539 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9540 _("loop too long for LOOP instruction"));
9542 tinsn_from_chars (&addi_insn
, fragP
->fr_opcode
+ addi_offset
, 0);
9543 assert (addi_insn
.opcode
== xtensa_addi_opcode
);
9545 tinsn_from_chars (&addmi_insn
, fragP
->fr_opcode
+ addmi_offset
, 0);
9546 assert (addmi_insn
.opcode
== xtensa_addmi_opcode
);
9548 set_expr_const (&addi_insn
.tok
[2], loop_length_lo
);
9549 tinsn_to_insnbuf (&addi_insn
, insnbuf
);
9551 fragP
->tc_frag_data
.is_insn
= TRUE
;
9552 xtensa_insnbuf_to_chars
9553 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addi_offset
, 0);
9555 set_expr_const (&addmi_insn
.tok
[2], loop_length_hi
);
9556 tinsn_to_insnbuf (&addmi_insn
, insnbuf
);
9557 xtensa_insnbuf_to_chars
9558 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addmi_offset
, 0);
9560 /* Walk through all of the frags from here to the loop end
9561 and mark them as no_transform to keep them from being modified
9562 by the linker. If we ever have a relocation for the
9563 addi/addmi of the difference of two symbols we can remove this. */
9566 for (next_fragP
= fragP
; next_fragP
!= NULL
;
9567 next_fragP
= next_fragP
->fr_next
)
9569 next_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
9570 if (next_fragP
->tc_frag_data
.is_loop_target
)
9572 if (target_count
== 2)
9578 /* A map that keeps information on a per-subsegment basis. This is
9579 maintained during initial assembly, but is invalid once the
9580 subsegments are smashed together. I.E., it cannot be used during
9583 typedef struct subseg_map_struct
9591 float total_freq
; /* fall-through + branch target frequency */
9592 float target_freq
; /* branch target frequency alone */
9594 struct subseg_map_struct
*next
;
9598 static subseg_map
*sseg_map
= NULL
;
9601 get_subseg_info (segT seg
, subsegT subseg
)
9603 subseg_map
*subseg_e
;
9605 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
9607 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
9615 add_subseg_info (segT seg
, subsegT subseg
)
9617 subseg_map
*subseg_e
= (subseg_map
*) xmalloc (sizeof (subseg_map
));
9618 memset (subseg_e
, 0, sizeof (subseg_map
));
9619 subseg_e
->seg
= seg
;
9620 subseg_e
->subseg
= subseg
;
9621 subseg_e
->flags
= 0;
9622 /* Start off considering every branch target very important. */
9623 subseg_e
->target_freq
= 1.0;
9624 subseg_e
->total_freq
= 1.0;
9625 subseg_e
->next
= sseg_map
;
9626 sseg_map
= subseg_e
;
9632 get_last_insn_flags (segT seg
, subsegT subseg
)
9634 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9636 return subseg_e
->flags
;
9642 set_last_insn_flags (segT seg
,
9647 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9649 subseg_e
= add_subseg_info (seg
, subseg
);
9651 subseg_e
->flags
|= fl
;
9653 subseg_e
->flags
&= ~fl
;
9658 get_subseg_total_freq (segT seg
, subsegT subseg
)
9660 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9662 return subseg_e
->total_freq
;
9668 get_subseg_target_freq (segT seg
, subsegT subseg
)
9670 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9672 return subseg_e
->target_freq
;
9678 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
9680 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9682 subseg_e
= add_subseg_info (seg
, subseg
);
9683 subseg_e
->total_freq
= total_f
;
9684 subseg_e
->target_freq
= target_f
;
9688 /* Segment Lists and emit_state Stuff. */
9691 xtensa_move_seg_list_to_beginning (seg_list
*head
)
9696 segT literal_section
= head
->seg
;
9698 /* Move the literal section to the front of the section list. */
9699 assert (literal_section
);
9700 if (literal_section
!= stdoutput
->sections
)
9702 bfd_section_list_remove (stdoutput
, literal_section
);
9703 bfd_section_list_prepend (stdoutput
, literal_section
);
9710 static void mark_literal_frags (seg_list
*);
9713 xtensa_move_literals (void)
9716 frchainS
*frchain_from
, *frchain_to
;
9717 fragS
*search_frag
, *next_frag
, *last_frag
, *literal_pool
, *insert_after
;
9718 fragS
**frag_splice
;
9721 fixS
*fix
, *next_fix
, **fix_splice
;
9724 mark_literal_frags (literal_head
->next
);
9725 mark_literal_frags (init_literal_head
->next
);
9726 mark_literal_frags (fini_literal_head
->next
);
9728 if (use_literal_section
)
9731 segment
= literal_head
->next
;
9734 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9735 search_frag
= frchain_from
->frch_root
;
9736 literal_pool
= NULL
;
9738 frag_splice
= &(frchain_from
->frch_root
);
9740 while (!search_frag
->tc_frag_data
.literal_frag
)
9742 assert (search_frag
->fr_fix
== 0
9743 || search_frag
->fr_type
== rs_align
);
9744 search_frag
= search_frag
->fr_next
;
9747 assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
9748 == RELAX_LITERAL_POOL_BEGIN
);
9749 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
9751 /* Make sure that all the frags in this series are closed, and
9752 that there is at least one left over of zero-size. This
9753 prevents us from making a segment with an frchain without any
9755 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9756 xtensa_set_frag_assembly_state (frag_now
);
9757 last_frag
= frag_now
;
9758 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9759 xtensa_set_frag_assembly_state (frag_now
);
9761 while (search_frag
!= frag_now
)
9763 next_frag
= search_frag
->fr_next
;
9765 /* First, move the frag out of the literal section and
9766 to the appropriate place. */
9767 if (search_frag
->tc_frag_data
.literal_frag
)
9769 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
9770 assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
9771 frchain_to
= literal_pool
->tc_frag_data
.lit_frchain
;
9772 assert (frchain_to
);
9774 insert_after
= literal_pool
;
9776 while (insert_after
->fr_next
->fr_subtype
!= RELAX_LITERAL_POOL_END
)
9777 insert_after
= insert_after
->fr_next
;
9779 dest_seg
= insert_after
->fr_next
->tc_frag_data
.lit_seg
;
9781 *frag_splice
= next_frag
;
9782 search_frag
->fr_next
= insert_after
->fr_next
;
9783 insert_after
->fr_next
= search_frag
;
9784 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
9786 /* Now move any fixups associated with this frag to the
9788 fix
= frchain_from
->fix_root
;
9789 fix_splice
= &(frchain_from
->fix_root
);
9792 next_fix
= fix
->fx_next
;
9793 if (fix
->fx_frag
== search_frag
)
9795 *fix_splice
= next_fix
;
9796 fix
->fx_next
= frchain_to
->fix_root
;
9797 frchain_to
->fix_root
= fix
;
9798 if (frchain_to
->fix_tail
== NULL
)
9799 frchain_to
->fix_tail
= fix
;
9802 fix_splice
= &(fix
->fx_next
);
9805 search_frag
= next_frag
;
9808 if (frchain_from
->fix_root
!= NULL
)
9810 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9811 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
9813 assert (frchain_from
->fix_root
== NULL
);
9815 frchain_from
->fix_tail
= NULL
;
9816 xtensa_restore_emit_state (&state
);
9817 segment
= segment
->next
;
9820 /* Now fix up the SEGMENT value for all the literal symbols. */
9821 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
9823 symbolS
*lit_sym
= lit
->sym
;
9824 segT dest_seg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
9826 S_SET_SEGMENT (lit_sym
, dest_seg
);
9831 /* Walk over all the frags for segments in a list and mark them as
9832 containing literals. As clunky as this is, we can't rely on frag_var
9833 and frag_variant to get called in all situations. */
9836 mark_literal_frags (seg_list
*segment
)
9838 frchainS
*frchain_from
;
9843 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9844 search_frag
= frchain_from
->frch_root
;
9847 search_frag
->tc_frag_data
.is_literal
= TRUE
;
9848 search_frag
= search_frag
->fr_next
;
9850 segment
= segment
->next
;
9856 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
9858 /* Move all of the sections in the section list to come
9859 after "after" in the gnu segment list. */
9864 segT literal_section
= head
->seg
;
9866 /* Move the literal section after "after". */
9867 assert (literal_section
);
9868 if (literal_section
!= after
)
9870 bfd_section_list_remove (stdoutput
, literal_section
);
9871 bfd_section_list_insert_after (stdoutput
, after
, literal_section
);
9879 /* Push all the literal segments to the end of the gnu list. */
9882 xtensa_reorder_segments (void)
9889 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
9895 /* Now that we have the last section, push all the literal
9896 sections to the end. */
9897 xtensa_reorder_seg_list (literal_head
, last_sec
);
9898 xtensa_reorder_seg_list (init_literal_head
, last_sec
);
9899 xtensa_reorder_seg_list (fini_literal_head
, last_sec
);
9901 /* Now perform the final error check. */
9902 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
9904 assert (new_count
== old_count
);
9908 /* Change the emit state (seg, subseg, and frag related stuff) to the
9909 correct location. Return a emit_state which can be passed to
9910 xtensa_restore_emit_state to return to current fragment. */
9913 xtensa_switch_to_literal_fragment (emit_state
*result
)
9915 if (directive_state
[directive_absolute_literals
])
9917 cache_literal_section (0, default_lit_sections
.lit4_seg_name
,
9918 &default_lit_sections
.lit4_seg
, FALSE
);
9919 xtensa_switch_section_emit_state (result
,
9920 default_lit_sections
.lit4_seg
, 0);
9923 xtensa_switch_to_non_abs_literal_fragment (result
);
9925 /* Do a 4-byte align here. */
9926 frag_align (2, 0, 0);
9927 record_alignment (now_seg
, 2);
9932 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
9934 /* When we mark a literal pool location, we want to put a frag in
9935 the literal pool that points to it. But to do that, we want to
9936 switch_to_literal_fragment. But literal sections don't have
9937 literal pools, so their location is always null, so we would
9938 recurse forever. This is kind of hacky, but it works. */
9940 static bfd_boolean recursive
= FALSE
;
9941 fragS
*pool_location
= get_literal_pool_location (now_seg
);
9942 bfd_boolean is_init
=
9943 (now_seg
&& !strcmp (segment_name (now_seg
), INIT_SECTION_NAME
));
9945 bfd_boolean is_fini
=
9946 (now_seg
&& !strcmp (segment_name (now_seg
), FINI_SECTION_NAME
));
9948 if (pool_location
== NULL
9949 && !use_literal_section
9951 && !is_init
&& ! is_fini
)
9953 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
9955 xtensa_mark_literal_pool_location ();
9959 /* Special case: If we are in the ".fini" or ".init" section, then
9960 we will ALWAYS be generating to the ".fini.literal" and
9961 ".init.literal" sections. */
9965 cache_literal_section (init_literal_head
,
9966 default_lit_sections
.init_lit_seg_name
,
9967 &default_lit_sections
.init_lit_seg
, TRUE
);
9968 xtensa_switch_section_emit_state (result
,
9969 default_lit_sections
.init_lit_seg
, 0);
9973 cache_literal_section (fini_literal_head
,
9974 default_lit_sections
.fini_lit_seg_name
,
9975 &default_lit_sections
.fini_lit_seg
, TRUE
);
9976 xtensa_switch_section_emit_state (result
,
9977 default_lit_sections
.fini_lit_seg
, 0);
9981 cache_literal_section (literal_head
,
9982 default_lit_sections
.lit_seg_name
,
9983 &default_lit_sections
.lit_seg
, TRUE
);
9984 xtensa_switch_section_emit_state (result
,
9985 default_lit_sections
.lit_seg
, 0);
9988 if (!use_literal_section
9989 && !is_init
&& !is_fini
9990 && get_literal_pool_location (now_seg
) != pool_location
)
9992 /* Close whatever frag is there. */
9993 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9994 xtensa_set_frag_assembly_state (frag_now
);
9995 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
9996 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9997 xtensa_set_frag_assembly_state (frag_now
);
10002 /* Call this function before emitting data into the literal section.
10003 This is a helper function for xtensa_switch_to_literal_fragment.
10004 This is similar to a .section new_now_seg subseg. */
10007 xtensa_switch_section_emit_state (emit_state
*state
,
10009 subsegT new_now_subseg
)
10011 state
->name
= now_seg
->name
;
10012 state
->now_seg
= now_seg
;
10013 state
->now_subseg
= now_subseg
;
10014 state
->generating_literals
= generating_literals
;
10015 generating_literals
++;
10016 subseg_set (new_now_seg
, new_now_subseg
);
10020 /* Use to restore the emitting into the normal place. */
10023 xtensa_restore_emit_state (emit_state
*state
)
10025 generating_literals
= state
->generating_literals
;
10026 subseg_set (state
->now_seg
, state
->now_subseg
);
10030 /* Get a segment of a given name. If the segment is already
10031 present, return it; otherwise, create a new one. */
10034 cache_literal_section (seg_list
*head
,
10037 bfd_boolean is_code
)
10039 segT current_section
= now_seg
;
10040 int current_subsec
= now_subseg
;
10046 /* Check if the named section exists. */
10047 for (seg
= stdoutput
->sections
; seg
; seg
= seg
->next
)
10049 if (!strcmp (segment_name (seg
), name
))
10055 /* Create a new literal section. */
10056 seg
= subseg_new (name
, (subsegT
) 0);
10059 /* Add the newly created literal segment to the specified list. */
10060 seg_list
*n
= (seg_list
*) xmalloc (sizeof (seg_list
));
10062 n
->next
= head
->next
;
10065 bfd_set_section_flags (stdoutput
, seg
, SEC_HAS_CONTENTS
|
10066 SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
10067 | (is_code
? SEC_CODE
: SEC_DATA
));
10068 bfd_set_section_alignment (stdoutput
, seg
, 2);
10072 subseg_set (current_section
, current_subsec
);
10076 /* Property Tables Stuff. */
10078 #define XTENSA_INSN_SEC_NAME ".xt.insn"
10079 #define XTENSA_LIT_SEC_NAME ".xt.lit"
10080 #define XTENSA_PROP_SEC_NAME ".xt.prop"
10082 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
10083 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
10085 static bfd_boolean
get_frag_is_literal (const fragS
*);
10086 static void xtensa_create_property_segments
10087 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
10088 static void xtensa_create_xproperty_segments
10089 (frag_flags_fn
, const char *, xt_section_type
);
10090 static segment_info_type
*retrieve_segment_info (segT
);
10091 static segT
retrieve_xtensa_section (char *);
10092 static bfd_boolean
section_has_property (segT
, frag_predicate
);
10093 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
10094 static void add_xt_block_frags
10095 (segT
, segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
10096 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
10097 static void xtensa_frag_flags_init (frag_flags
*);
10098 static void get_frag_property_flags (const fragS
*, frag_flags
*);
10099 static bfd_vma
frag_flags_to_number (const frag_flags
*);
10100 static void add_xt_prop_frags
10101 (segT
, segT
, xtensa_block_info
**, frag_flags_fn
);
10103 /* Set up property tables after relaxation. */
10106 xtensa_post_relax_hook (void)
10108 xtensa_move_seg_list_to_beginning (literal_head
);
10109 xtensa_move_seg_list_to_beginning (init_literal_head
);
10110 xtensa_move_seg_list_to_beginning (fini_literal_head
);
10112 xtensa_find_unmarked_state_frags ();
10114 if (use_literal_section
)
10115 xtensa_create_property_segments (get_frag_is_literal
,
10117 XTENSA_LIT_SEC_NAME
,
10119 xtensa_create_xproperty_segments (get_frag_property_flags
,
10120 XTENSA_PROP_SEC_NAME
,
10123 if (warn_unaligned_branch_targets
)
10124 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
10125 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
10129 /* This function is only meaningful after xtensa_move_literals. */
10132 get_frag_is_literal (const fragS
*fragP
)
10134 assert (fragP
!= NULL
);
10135 return fragP
->tc_frag_data
.is_literal
;
10140 xtensa_create_property_segments (frag_predicate property_function
,
10141 frag_predicate end_property_function
,
10142 const char *section_name_base
,
10143 xt_section_type sec_type
)
10147 /* Walk over all of the current segments.
10148 Walk over each fragment
10149 For each non-empty fragment,
10150 Build a property record (append where possible). */
10152 for (seclist
= &stdoutput
->sections
;
10153 seclist
&& *seclist
;
10154 seclist
= &(*seclist
)->next
)
10156 segT sec
= *seclist
;
10159 flags
= bfd_get_section_flags (stdoutput
, sec
);
10160 if (flags
& SEC_DEBUGGING
)
10162 if (!(flags
& SEC_ALLOC
))
10165 if (section_has_property (sec
, property_function
))
10167 char *property_section_name
=
10168 xtensa_get_property_section_name (sec
, section_name_base
);
10169 segT insn_sec
= retrieve_xtensa_section (property_section_name
);
10170 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10171 xtensa_block_info
**xt_blocks
=
10172 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10173 /* Walk over all of the frchains here and add new sections. */
10174 add_xt_block_frags (sec
, insn_sec
, xt_blocks
, property_function
,
10175 end_property_function
);
10179 /* Now we fill them out.... */
10181 for (seclist
= &stdoutput
->sections
;
10182 seclist
&& *seclist
;
10183 seclist
= &(*seclist
)->next
)
10185 segment_info_type
*seginfo
;
10186 xtensa_block_info
*block
;
10187 segT sec
= *seclist
;
10189 seginfo
= seg_info (sec
);
10190 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10194 xtensa_block_info
*cur_block
;
10195 /* This is a section with some data. */
10197 bfd_size_type rec_size
;
10199 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10202 rec_size
= num_recs
* 8;
10203 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10205 /* In order to make this work with the assembler, we have to
10206 build some frags and then build the "fixups" for it. It
10207 would be easier to just set the contents then set the
10212 /* Allocate a fragment and leak it. */
10214 bfd_size_type frag_size
;
10216 frchainS
*frchainP
;
10220 frag_size
= sizeof (fragS
) + rec_size
;
10221 fragP
= (fragS
*) xmalloc (frag_size
);
10223 memset (fragP
, 0, frag_size
);
10224 fragP
->fr_address
= 0;
10225 fragP
->fr_next
= NULL
;
10226 fragP
->fr_fix
= rec_size
;
10228 fragP
->fr_type
= rs_fill
;
10229 /* The rest are zeros. */
10231 frchainP
= seginfo
->frchainP
;
10232 frchainP
->frch_root
= fragP
;
10233 frchainP
->frch_last
= fragP
;
10235 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10236 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10238 seginfo
->fix_root
= fixes
;
10239 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10241 frag_data
= &fragP
->fr_literal
[0];
10242 for (i
= 0; i
< num_recs
; i
++)
10244 fixS
*fix
= &fixes
[i
];
10245 assert (cur_block
);
10247 /* Write the fixup. */
10248 if (i
!= num_recs
- 1)
10249 fix
->fx_next
= &fixes
[i
+ 1];
10251 fix
->fx_next
= NULL
;
10254 fix
->fx_frag
= fragP
;
10255 fix
->fx_where
= i
* 8;
10256 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10257 fix
->fx_offset
= cur_block
->offset
;
10258 fix
->fx_r_type
= BFD_RELOC_32
;
10259 fix
->fx_file
= "Internal Assembly";
10262 /* Write the length. */
10263 md_number_to_chars (&frag_data
[4 + 8 * i
],
10264 cur_block
->size
, 4);
10265 cur_block
= cur_block
->next
;
10274 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
10275 const char *section_name_base
,
10276 xt_section_type sec_type
)
10280 /* Walk over all of the current segments.
10281 Walk over each fragment.
10282 For each fragment that has instructions,
10283 build an instruction record (append where possible). */
10285 for (seclist
= &stdoutput
->sections
;
10286 seclist
&& *seclist
;
10287 seclist
= &(*seclist
)->next
)
10289 segT sec
= *seclist
;
10292 flags
= bfd_get_section_flags (stdoutput
, sec
);
10293 if ((flags
& SEC_DEBUGGING
)
10294 || !(flags
& SEC_ALLOC
)
10295 || (flags
& SEC_MERGE
))
10298 if (section_has_xproperty (sec
, flag_fn
))
10300 char *property_section_name
=
10301 xtensa_get_property_section_name (sec
, section_name_base
);
10302 segT insn_sec
= retrieve_xtensa_section (property_section_name
);
10303 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10304 xtensa_block_info
**xt_blocks
=
10305 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10306 /* Walk over all of the frchains here and add new sections. */
10307 add_xt_prop_frags (sec
, insn_sec
, xt_blocks
, flag_fn
);
10311 /* Now we fill them out.... */
10313 for (seclist
= &stdoutput
->sections
;
10314 seclist
&& *seclist
;
10315 seclist
= &(*seclist
)->next
)
10317 segment_info_type
*seginfo
;
10318 xtensa_block_info
*block
;
10319 segT sec
= *seclist
;
10321 seginfo
= seg_info (sec
);
10322 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10326 xtensa_block_info
*cur_block
;
10327 /* This is a section with some data. */
10329 bfd_size_type rec_size
;
10331 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10334 rec_size
= num_recs
* (8 + 4);
10335 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10337 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
10339 /* In order to make this work with the assembler, we have to build
10340 some frags then build the "fixups" for it. It would be easier to
10341 just set the contents then set the arlents. */
10345 /* Allocate a fragment and (unfortunately) leak it. */
10347 bfd_size_type frag_size
;
10349 frchainS
*frchainP
;
10353 frag_size
= sizeof (fragS
) + rec_size
;
10354 fragP
= (fragS
*) xmalloc (frag_size
);
10356 memset (fragP
, 0, frag_size
);
10357 fragP
->fr_address
= 0;
10358 fragP
->fr_next
= NULL
;
10359 fragP
->fr_fix
= rec_size
;
10361 fragP
->fr_type
= rs_fill
;
10362 /* The rest are zeros. */
10364 frchainP
= seginfo
->frchainP
;
10365 frchainP
->frch_root
= fragP
;
10366 frchainP
->frch_last
= fragP
;
10368 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10369 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10371 seginfo
->fix_root
= fixes
;
10372 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10374 frag_data
= &fragP
->fr_literal
[0];
10375 for (i
= 0; i
< num_recs
; i
++)
10377 fixS
*fix
= &fixes
[i
];
10378 assert (cur_block
);
10380 /* Write the fixup. */
10381 if (i
!= num_recs
- 1)
10382 fix
->fx_next
= &fixes
[i
+ 1];
10384 fix
->fx_next
= NULL
;
10387 fix
->fx_frag
= fragP
;
10388 fix
->fx_where
= i
* (8 + 4);
10389 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10390 fix
->fx_offset
= cur_block
->offset
;
10391 fix
->fx_r_type
= BFD_RELOC_32
;
10392 fix
->fx_file
= "Internal Assembly";
10395 /* Write the length. */
10396 md_number_to_chars (&frag_data
[4 + (8+4) * i
],
10397 cur_block
->size
, 4);
10398 md_number_to_chars (&frag_data
[8 + (8+4) * i
],
10399 frag_flags_to_number (&cur_block
->flags
),
10401 cur_block
= cur_block
->next
;
10409 static segment_info_type
*
10410 retrieve_segment_info (segT seg
)
10412 segment_info_type
*seginfo
;
10413 seginfo
= (segment_info_type
*) bfd_get_section_userdata (stdoutput
, seg
);
10416 frchainS
*frchainP
;
10418 seginfo
= (segment_info_type
*) xmalloc (sizeof (*seginfo
));
10419 memset ((void *) seginfo
, 0, sizeof (*seginfo
));
10420 seginfo
->fix_root
= NULL
;
10421 seginfo
->fix_tail
= NULL
;
10422 seginfo
->bfd_section
= seg
;
10424 /* We will not be dealing with these, only our special ones. */
10425 bfd_set_section_userdata (stdoutput
, seg
, (void *) seginfo
);
10427 frchainP
= (frchainS
*) xmalloc (sizeof (frchainS
));
10428 frchainP
->frch_root
= NULL
;
10429 frchainP
->frch_last
= NULL
;
10430 frchainP
->frch_next
= NULL
;
10431 frchainP
->frch_seg
= seg
;
10432 frchainP
->frch_subseg
= 0;
10433 frchainP
->fix_root
= NULL
;
10434 frchainP
->fix_tail
= NULL
;
10435 /* Do not init the objstack. */
10436 /* obstack_begin (&frchainP->frch_obstack, chunksize); */
10437 /* frchainP->frch_frag_now = fragP; */
10438 frchainP
->frch_frag_now
= NULL
;
10440 seginfo
->frchainP
= frchainP
;
10448 retrieve_xtensa_section (char *sec_name
)
10450 bfd
*abfd
= stdoutput
;
10451 flagword flags
, out_flags
, link_once_flags
;
10454 flags
= bfd_get_section_flags (abfd
, now_seg
);
10455 link_once_flags
= (flags
& SEC_LINK_ONCE
);
10456 if (link_once_flags
)
10457 link_once_flags
|= (flags
& SEC_LINK_DUPLICATES
);
10458 out_flags
= (SEC_RELOC
| SEC_HAS_CONTENTS
| SEC_READONLY
| link_once_flags
);
10460 s
= bfd_make_section_old_way (abfd
, sec_name
);
10462 as_bad (_("could not create section %s"), sec_name
);
10463 if (!bfd_set_section_flags (abfd
, s
, out_flags
))
10464 as_bad (_("invalid flag combination on section %s"), sec_name
);
10471 section_has_property (segT sec
, frag_predicate property_function
)
10473 segment_info_type
*seginfo
= seg_info (sec
);
10476 if (seginfo
&& seginfo
->frchainP
)
10478 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10480 if (property_function (fragP
)
10481 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10490 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
10492 segment_info_type
*seginfo
= seg_info (sec
);
10495 if (seginfo
&& seginfo
->frchainP
)
10497 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10499 frag_flags prop_flags
;
10500 property_function (fragP
, &prop_flags
);
10501 if (!xtensa_frag_flags_is_empty (&prop_flags
))
10509 /* Two types of block sections exist right now: literal and insns. */
10512 add_xt_block_frags (segT sec
,
10514 xtensa_block_info
**xt_block
,
10515 frag_predicate property_function
,
10516 frag_predicate end_property_function
)
10518 segment_info_type
*seg_info
;
10519 segment_info_type
*xt_seg_info
;
10520 bfd_vma seg_offset
;
10523 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
10524 seg_info
= retrieve_segment_info (sec
);
10526 /* Build it if needed. */
10527 while (*xt_block
!= NULL
)
10528 xt_block
= &(*xt_block
)->next
;
10529 /* We are either at NULL at the beginning or at the end. */
10531 /* Walk through the frags. */
10534 if (seg_info
->frchainP
)
10536 for (fragP
= seg_info
->frchainP
->frch_root
;
10538 fragP
= fragP
->fr_next
)
10540 if (property_function (fragP
)
10541 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10543 if (*xt_block
!= NULL
)
10545 if ((*xt_block
)->offset
+ (*xt_block
)->size
10546 == fragP
->fr_address
)
10547 (*xt_block
)->size
+= fragP
->fr_fix
;
10549 xt_block
= &((*xt_block
)->next
);
10551 if (*xt_block
== NULL
)
10553 xtensa_block_info
*new_block
= (xtensa_block_info
*)
10554 xmalloc (sizeof (xtensa_block_info
));
10555 new_block
->sec
= sec
;
10556 new_block
->offset
= fragP
->fr_address
;
10557 new_block
->size
= fragP
->fr_fix
;
10558 new_block
->next
= NULL
;
10559 xtensa_frag_flags_init (&new_block
->flags
);
10560 *xt_block
= new_block
;
10562 if (end_property_function
10563 && end_property_function (fragP
))
10565 xt_block
= &((*xt_block
)->next
);
10573 /* Break the encapsulation of add_xt_prop_frags here. */
10576 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
10578 if (prop_flags
->is_literal
10579 || prop_flags
->is_insn
10580 || prop_flags
->is_data
10581 || prop_flags
->is_unreachable
)
10588 xtensa_frag_flags_init (frag_flags
*prop_flags
)
10590 memset (prop_flags
, 0, sizeof (frag_flags
));
10595 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
10597 xtensa_frag_flags_init (prop_flags
);
10598 if (fragP
->tc_frag_data
.is_literal
)
10599 prop_flags
->is_literal
= TRUE
;
10600 if (fragP
->tc_frag_data
.is_unreachable
)
10601 prop_flags
->is_unreachable
= TRUE
;
10602 else if (fragP
->tc_frag_data
.is_insn
)
10604 prop_flags
->is_insn
= TRUE
;
10605 if (fragP
->tc_frag_data
.is_loop_target
)
10606 prop_flags
->insn
.is_loop_target
= TRUE
;
10607 if (fragP
->tc_frag_data
.is_branch_target
)
10608 prop_flags
->insn
.is_branch_target
= TRUE
;
10609 if (fragP
->tc_frag_data
.is_specific_opcode
10610 || fragP
->tc_frag_data
.is_no_transform
)
10611 prop_flags
->insn
.is_no_transform
= TRUE
;
10612 if (fragP
->tc_frag_data
.is_no_density
)
10613 prop_flags
->insn
.is_no_density
= TRUE
;
10614 if (fragP
->tc_frag_data
.use_absolute_literals
)
10615 prop_flags
->insn
.is_abslit
= TRUE
;
10617 if (fragP
->tc_frag_data
.is_align
)
10619 prop_flags
->is_align
= TRUE
;
10620 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
10621 if (xtensa_frag_flags_is_empty (prop_flags
))
10622 prop_flags
->is_data
= TRUE
;
10628 frag_flags_to_number (const frag_flags
*prop_flags
)
10631 if (prop_flags
->is_literal
)
10632 num
|= XTENSA_PROP_LITERAL
;
10633 if (prop_flags
->is_insn
)
10634 num
|= XTENSA_PROP_INSN
;
10635 if (prop_flags
->is_data
)
10636 num
|= XTENSA_PROP_DATA
;
10637 if (prop_flags
->is_unreachable
)
10638 num
|= XTENSA_PROP_UNREACHABLE
;
10639 if (prop_flags
->insn
.is_loop_target
)
10640 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
10641 if (prop_flags
->insn
.is_branch_target
)
10643 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
10644 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
10647 if (prop_flags
->insn
.is_no_density
)
10648 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
10649 if (prop_flags
->insn
.is_no_transform
)
10650 num
|= XTENSA_PROP_INSN_NO_TRANSFORM
;
10651 if (prop_flags
->insn
.is_no_reorder
)
10652 num
|= XTENSA_PROP_INSN_NO_REORDER
;
10653 if (prop_flags
->insn
.is_abslit
)
10654 num
|= XTENSA_PROP_INSN_ABSLIT
;
10656 if (prop_flags
->is_align
)
10658 num
|= XTENSA_PROP_ALIGN
;
10659 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
10667 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
10668 const frag_flags
*prop_flags_2
)
10670 /* Cannot combine with an end marker. */
10672 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
10674 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
10676 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
10679 if (prop_flags_1
->is_insn
)
10681 /* Properties of the beginning of the frag. */
10682 if (prop_flags_2
->insn
.is_loop_target
)
10684 if (prop_flags_2
->insn
.is_branch_target
)
10686 if (prop_flags_1
->insn
.is_no_density
!=
10687 prop_flags_2
->insn
.is_no_density
)
10689 if (prop_flags_1
->insn
.is_no_transform
!=
10690 prop_flags_2
->insn
.is_no_transform
)
10692 if (prop_flags_1
->insn
.is_no_reorder
!=
10693 prop_flags_2
->insn
.is_no_reorder
)
10695 if (prop_flags_1
->insn
.is_abslit
!=
10696 prop_flags_2
->insn
.is_abslit
)
10700 if (prop_flags_1
->is_align
)
10708 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
10711 unsigned align_bits
;
10713 if (!xt_block
->flags
.is_align
)
10714 return xt_block
->size
;
10716 end_addr
= xt_block
->offset
+ xt_block
->size
;
10717 align_bits
= xt_block
->flags
.alignment
;
10718 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
10719 return end_addr
- xt_block
->offset
;
10724 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
10725 const xtensa_block_info
*xt_block_2
)
10727 if (xt_block
->sec
!= xt_block_2
->sec
)
10729 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
10730 != xt_block_2
->offset
)
10733 if (xt_block_2
->size
== 0
10734 && (!xt_block_2
->flags
.is_unreachable
10735 || xt_block
->flags
.is_unreachable
))
10737 if (xt_block_2
->flags
.is_align
10738 && xt_block
->flags
.is_align
)
10740 /* Nothing needed. */
10741 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
10746 if (xt_block_2
->flags
.is_align
)
10748 /* Push alignment to previous entry. */
10749 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
10750 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10755 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
10756 &xt_block_2
->flags
))
10759 xt_block
->size
+= xt_block_2
->size
;
10761 if (xt_block_2
->flags
.is_align
)
10763 xt_block
->flags
.is_align
= TRUE
;
10764 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10772 add_xt_prop_frags (segT sec
,
10774 xtensa_block_info
**xt_block
,
10775 frag_flags_fn property_function
)
10777 segment_info_type
*seg_info
;
10778 segment_info_type
*xt_seg_info
;
10779 bfd_vma seg_offset
;
10782 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
10783 seg_info
= retrieve_segment_info (sec
);
10784 /* Build it if needed. */
10785 while (*xt_block
!= NULL
)
10787 xt_block
= &(*xt_block
)->next
;
10789 /* We are either at NULL at the beginning or at the end. */
10791 /* Walk through the frags. */
10794 if (seg_info
->frchainP
)
10796 for (fragP
= seg_info
->frchainP
->frch_root
; fragP
;
10797 fragP
= fragP
->fr_next
)
10799 xtensa_block_info tmp_block
;
10800 tmp_block
.sec
= sec
;
10801 tmp_block
.offset
= fragP
->fr_address
;
10802 tmp_block
.size
= fragP
->fr_fix
;
10803 tmp_block
.next
= NULL
;
10804 property_function (fragP
, &tmp_block
.flags
);
10806 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
10807 /* && fragP->fr_fix != 0) */
10809 if ((*xt_block
) == NULL
10810 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
10812 xtensa_block_info
*new_block
;
10813 if ((*xt_block
) != NULL
)
10814 xt_block
= &(*xt_block
)->next
;
10815 new_block
= (xtensa_block_info
*)
10816 xmalloc (sizeof (xtensa_block_info
));
10817 *new_block
= tmp_block
;
10818 *xt_block
= new_block
;
10826 /* op_placement_info_table */
10828 /* op_placement_info makes it easier to determine which
10829 ops can go in which slots. */
10832 init_op_placement_info_table (void)
10834 xtensa_isa isa
= xtensa_default_isa
;
10835 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
10836 xtensa_opcode opcode
;
10839 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
10841 op_placement_table
= (op_placement_info_table
)
10842 xmalloc (sizeof (op_placement_info
) * num_opcodes
);
10843 assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
10845 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
10847 op_placement_info
*opi
= &op_placement_table
[opcode
];
10848 /* FIXME: Make tinsn allocation dynamic. */
10849 if (xtensa_opcode_num_operands (isa
, opcode
) >= MAX_INSN_ARGS
)
10850 as_fatal (_("too many operands in instruction"));
10851 opi
->single
= XTENSA_UNDEFINED
;
10852 opi
->single_size
= 0;
10853 opi
->widest
= XTENSA_UNDEFINED
;
10854 opi
->widest_size
= 0;
10855 opi
->narrowest
= XTENSA_UNDEFINED
;
10856 opi
->narrowest_size
= 0x7F;
10858 opi
->num_formats
= 0;
10860 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
10862 opi
->slots
[fmt
] = 0;
10863 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
10865 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
10867 int fmt_length
= xtensa_format_length (isa
, fmt
);
10869 set_bit (fmt
, opi
->formats
);
10870 set_bit (slot
, opi
->slots
[fmt
]);
10871 /* opi->slot_count[fmt]++; */
10872 if (fmt_length
< opi
->narrowest_size
)
10874 opi
->narrowest
= fmt
;
10875 opi
->narrowest_size
= fmt_length
;
10877 if (fmt_length
> opi
->widest_size
)
10880 opi
->widest_size
= fmt_length
;
10882 if (xtensa_format_num_slots (isa
, fmt
) == 1)
10884 if (opi
->single_size
== 0
10885 || fmt_length
< opi
->single_size
)
10888 opi
->single_size
= fmt_length
;
10894 opi
->num_formats
++;
10897 xtensa_insnbuf_free (isa
, ibuf
);
10902 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
10904 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
10908 /* If the opcode is available in a single slot format, return its size. */
10911 xg_get_single_size (xtensa_opcode opcode
)
10913 assert (op_placement_table
[opcode
].single
!= XTENSA_UNDEFINED
);
10914 return op_placement_table
[opcode
].single_size
;
10918 static xtensa_format
10919 xg_get_single_format (xtensa_opcode opcode
)
10921 return op_placement_table
[opcode
].single
;
10925 /* Instruction Stack Functions (from "xtensa-istack.h"). */
10928 istack_init (IStack
*stack
)
10930 memset (stack
, 0, sizeof (IStack
));
10936 istack_empty (IStack
*stack
)
10938 return (stack
->ninsn
== 0);
10943 istack_full (IStack
*stack
)
10945 return (stack
->ninsn
== MAX_ISTACK
);
10949 /* Return a pointer to the top IStack entry.
10950 It is an error to call this if istack_empty () is TRUE. */
10953 istack_top (IStack
*stack
)
10955 int rec
= stack
->ninsn
- 1;
10956 assert (!istack_empty (stack
));
10957 return &stack
->insn
[rec
];
10961 /* Add a new TInsn to an IStack.
10962 It is an error to call this if istack_full () is TRUE. */
10965 istack_push (IStack
*stack
, TInsn
*insn
)
10967 int rec
= stack
->ninsn
;
10968 assert (!istack_full (stack
));
10969 stack
->insn
[rec
] = *insn
;
10974 /* Clear space for the next TInsn on the IStack and return a pointer
10975 to it. It is an error to call this if istack_full () is TRUE. */
10978 istack_push_space (IStack
*stack
)
10980 int rec
= stack
->ninsn
;
10982 assert (!istack_full (stack
));
10983 insn
= &stack
->insn
[rec
];
10984 memset (insn
, 0, sizeof (TInsn
));
10990 /* Remove the last pushed instruction. It is an error to call this if
10991 istack_empty () returns TRUE. */
10994 istack_pop (IStack
*stack
)
10996 int rec
= stack
->ninsn
- 1;
10997 assert (!istack_empty (stack
));
10999 memset (&stack
->insn
[rec
], 0, sizeof (TInsn
));
11003 /* TInsn functions. */
11006 tinsn_init (TInsn
*dst
)
11008 memset (dst
, 0, sizeof (TInsn
));
11012 /* Get the ``num''th token of the TInsn.
11013 It is illegal to call this if num > insn->ntoks. */
11016 tinsn_get_tok (TInsn
*insn
, int num
)
11018 assert (num
< insn
->ntok
);
11019 return &insn
->tok
[num
];
11023 /* Return TRUE if ANY of the operands in the insn are symbolic. */
11026 tinsn_has_symbolic_operands (const TInsn
*insn
)
11029 int n
= insn
->ntok
;
11031 assert (insn
->insn_type
== ITYPE_INSN
);
11033 for (i
= 0; i
< n
; ++i
)
11035 switch (insn
->tok
[i
].X_op
)
11049 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
11051 xtensa_isa isa
= xtensa_default_isa
;
11053 int n
= insn
->ntok
;
11055 assert (insn
->insn_type
== ITYPE_INSN
);
11057 for (i
= 0; i
< n
; ++i
)
11059 switch (insn
->tok
[i
].X_op
)
11067 /* Errors for these types are caught later. */
11072 /* Symbolic immediates are only allowed on the last immediate
11073 operand. At this time, CONST16 is the only opcode where we
11074 support non-PC-relative relocations. (It isn't necessary
11075 to complain about non-PC-relative relocations here, but
11076 otherwise, no error is reported until the relocations are
11077 generated, and the assembler won't get that far if there
11078 are any other errors. It's nice to see all the problems
11080 if (i
!= get_relaxable_immed (insn
->opcode
)
11081 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
11082 && insn
->opcode
!= xtensa_const16_opcode
))
11084 as_bad (_("invalid symbolic operand %d on '%s'"),
11085 i
, xtensa_opcode_name (isa
, insn
->opcode
));
11094 /* For assembly code with complex expressions (e.g. subtraction),
11095 we have to build them in the literal pool so that
11096 their results are calculated correctly after relaxation.
11097 The relaxation only handles expressions that
11098 boil down to SYMBOL + OFFSET. */
11101 tinsn_has_complex_operands (const TInsn
*insn
)
11104 int n
= insn
->ntok
;
11105 assert (insn
->insn_type
== ITYPE_INSN
);
11106 for (i
= 0; i
< n
; ++i
)
11108 switch (insn
->tok
[i
].X_op
)
11124 /* Convert the constant operands in the tinsn to insnbuf.
11125 Return TRUE if there is a symbol in the immediate field.
11127 Before this is called,
11128 1) the number of operands are correct
11129 2) the tinsn is a ITYPE_INSN
11130 3) ONLY the relaxable_ is built
11131 4) All operands are O_constant, O_symbol. All constants fit
11132 The return value tells whether there are any remaining O_symbols. */
11135 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
11137 static xtensa_insnbuf slotbuf
= 0;
11138 xtensa_isa isa
= xtensa_default_isa
;
11139 xtensa_opcode opcode
= tinsn
->opcode
;
11140 xtensa_format fmt
= xg_get_single_format (opcode
);
11141 bfd_boolean has_fixup
= FALSE
;
11142 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11149 slotbuf
= xtensa_insnbuf_alloc (isa
);
11151 assert (tinsn
->insn_type
== ITYPE_INSN
);
11152 if (noperands
!= tinsn
->ntok
)
11153 as_fatal (_("operand number mismatch"));
11155 if (xtensa_opcode_encode (isa
, fmt
, 0, slotbuf
, opcode
))
11156 as_fatal (_("cannot encode opcode"));
11158 for (i
= 0; i
< noperands
; ++i
)
11160 expressionS
*expr
= &tinsn
->tok
[i
];
11161 switch (expr
->X_op
)
11164 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11166 /* The register number has already been checked in
11167 expression_maybe_register, so we don't need to check here. */
11168 opnd_value
= expr
->X_add_number
;
11169 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11170 xtensa_operand_set_field (isa
, opcode
, i
, fmt
, 0,
11171 slotbuf
, opnd_value
);
11175 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11177 as_where (&file_name
, &line
);
11178 /* It is a constant and we called this function,
11179 then we have to try to fit it. */
11180 xtensa_insnbuf_set_operand (slotbuf
, fmt
, 0, opcode
, i
,
11181 expr
->X_add_number
, file_name
, line
);
11190 xtensa_format_encode (isa
, fmt
, insnbuf
);
11191 xtensa_format_set_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
11197 /* Convert the constant operands in the tinsn to slotbuf.
11198 Return TRUE if there is a symbol in the immediate field.
11199 (Eventually this should replace tinsn_to_insnbuf.) */
11201 /* Before this is called,
11202 1) the number of operands are correct
11203 2) the tinsn is a ITYPE_INSN
11204 3) ONLY the relaxable_ is built
11205 4) All operands are
11206 O_constant, O_symbol
11209 The return value tells whether there are any remaining O_symbols. */
11212 tinsn_to_slotbuf (xtensa_format fmt
,
11215 xtensa_insnbuf slotbuf
)
11217 xtensa_isa isa
= xtensa_default_isa
;
11218 xtensa_opcode opcode
= tinsn
->opcode
;
11219 bfd_boolean has_fixup
= FALSE
;
11220 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11223 assert (tinsn
->insn_type
== ITYPE_INSN
);
11224 if (noperands
!= tinsn
->ntok
)
11225 as_fatal (_("operand number mismatch"));
11227 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
11229 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
11230 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
11234 for (i
= 0; i
< noperands
; i
++)
11236 expressionS
*expr
= &tinsn
->tok
[i
];
11242 switch (expr
->X_op
)
11245 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11247 /* The register number has already been checked in
11248 expression_maybe_register, so we don't need to check here. */
11249 opnd_value
= expr
->X_add_number
;
11250 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11251 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
11254 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
11258 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11260 as_where (&file_name
, &line
);
11261 /* It is a constant and we called this function
11262 then we have to try to fit it. */
11263 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
11264 expr
->X_add_number
, file_name
, line
);
11277 /* Check the instruction arguments. Return TRUE on failure. */
11280 tinsn_check_arguments (const TInsn
*insn
)
11282 xtensa_isa isa
= xtensa_default_isa
;
11283 xtensa_opcode opcode
= insn
->opcode
;
11285 if (opcode
== XTENSA_UNDEFINED
)
11287 as_bad (_("invalid opcode"));
11291 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
11293 as_bad (_("too few operands"));
11297 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
11299 as_bad (_("too many operands"));
11306 /* Load an instruction from its encoded form. */
11309 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
11313 xg_init_vinsn (&vinsn
);
11314 vinsn_from_chars (&vinsn
, f
);
11316 *tinsn
= vinsn
.slots
[slot
];
11317 xg_free_vinsn (&vinsn
);
11322 tinsn_from_insnbuf (TInsn
*tinsn
,
11323 xtensa_insnbuf slotbuf
,
11328 xtensa_isa isa
= xtensa_default_isa
;
11330 /* Find the immed. */
11331 tinsn_init (tinsn
);
11332 tinsn
->insn_type
= ITYPE_INSN
;
11333 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
11334 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
11335 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
11336 for (i
= 0; i
< tinsn
->ntok
; i
++)
11338 set_expr_const (&tinsn
->tok
[i
],
11339 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
11340 tinsn
->opcode
, i
));
11345 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
11348 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
11350 xtensa_opcode opcode
= tinsn
->opcode
;
11353 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
11355 opnum
= get_relaxable_immed (opcode
);
11356 assert (opnum
>= 0);
11357 if (fragP
->tc_frag_data
.slot_sub_symbols
[slot
])
11359 set_expr_symbol_offset_diff
11360 (&tinsn
->tok
[opnum
],
11361 fragP
->tc_frag_data
.slot_symbols
[slot
],
11362 fragP
->tc_frag_data
.slot_sub_symbols
[slot
],
11363 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11367 set_expr_symbol_offset
11368 (&tinsn
->tok
[opnum
],
11369 fragP
->tc_frag_data
.slot_symbols
[slot
],
11370 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11377 get_num_stack_text_bytes (IStack
*istack
)
11380 int text_bytes
= 0;
11382 for (i
= 0; i
< istack
->ninsn
; i
++)
11384 TInsn
*tinsn
= &istack
->insn
[i
];
11385 if (tinsn
->insn_type
== ITYPE_INSN
)
11386 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
11393 get_num_stack_literal_bytes (IStack
*istack
)
11398 for (i
= 0; i
< istack
->ninsn
; i
++)
11400 TInsn
*tinsn
= &istack
->insn
[i
];
11401 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
11408 /* vliw_insn functions. */
11411 xg_init_vinsn (vliw_insn
*v
)
11414 xtensa_isa isa
= xtensa_default_isa
;
11416 xg_clear_vinsn (v
);
11418 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
11419 if (v
->insnbuf
== NULL
)
11420 as_fatal (_("out of memory"));
11422 for (i
= 0; i
< MAX_SLOTS
; i
++)
11424 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
11425 if (v
->slotbuf
[i
] == NULL
)
11426 as_fatal (_("out of memory"));
11432 xg_clear_vinsn (vliw_insn
*v
)
11436 memset (v
, 0, offsetof (vliw_insn
, insnbuf
));
11438 v
->format
= XTENSA_UNDEFINED
;
11440 v
->inside_bundle
= FALSE
;
11442 if (xt_saved_debug_type
!= DEBUG_NONE
)
11443 debug_type
= xt_saved_debug_type
;
11445 for (i
= 0; i
< MAX_SLOTS
; i
++)
11446 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
11451 vinsn_has_specific_opcodes (vliw_insn
*v
)
11455 for (i
= 0; i
< v
->num_slots
; i
++)
11457 if (v
->slots
[i
].is_specific_opcode
)
11465 xg_free_vinsn (vliw_insn
*v
)
11468 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
11469 for (i
= 0; i
< MAX_SLOTS
; i
++)
11470 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
11474 /* Before this is called, we should have
11475 filled out the following fields:
11477 1) the number of operands for each opcode are correct
11478 2) the tinsn in the slots are ITYPE_INSN
11479 3) ONLY the relaxable_ is built
11480 4) All operands are
11481 O_constant, O_symbol
11484 The return value tells whether there are any remaining O_symbols. */
11487 vinsn_to_insnbuf (vliw_insn
*vinsn
,
11490 bfd_boolean record_fixup
)
11492 xtensa_isa isa
= xtensa_default_isa
;
11493 xtensa_format fmt
= vinsn
->format
;
11494 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
11496 bfd_boolean has_fixup
= FALSE
;
11498 xtensa_format_encode (isa
, fmt
, insnbuf
);
11500 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
11502 TInsn
*tinsn
= &vinsn
->slots
[slot
];
11503 bfd_boolean tinsn_has_fixup
=
11504 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
11505 vinsn
->slotbuf
[slot
]);
11507 xtensa_format_set_slot (isa
, fmt
, slot
,
11508 insnbuf
, vinsn
->slotbuf
[slot
]);
11509 /* tinsn_has_fixup tracks if there is a fixup at all.
11510 record_fixup controls globally. I.E., we use this
11511 function from several places, some of which are after
11512 fixups have already been recorded. Finally,
11513 tinsn->record_fixup controls based on the individual ops,
11514 which may or may not need it based on the relaxation
11516 if (tinsn_has_fixup
&& record_fixup
)
11519 xtensa_opcode opcode
= tinsn
->opcode
;
11520 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11523 for (i
= 0; i
< noperands
; i
++)
11525 expressionS
* expr
= &tinsn
->tok
[i
];
11526 switch (expr
->X_op
)
11531 if (get_relaxable_immed (opcode
) == i
)
11533 if (tinsn
->record_fix
|| expr
->X_op
!= O_symbol
)
11535 if (!xg_add_opcode_fix
11536 (tinsn
, i
, fmt
, slot
, expr
, fragP
,
11537 frag_offset
- fragP
->fr_literal
))
11538 as_bad (_("instruction with constant operands does not fit"));
11542 tinsn
->symbol
= expr
->X_add_symbol
;
11543 tinsn
->offset
= expr
->X_add_number
;
11547 as_bad (_("invalid operand %d on '%s'"),
11548 i
, xtensa_opcode_name (isa
, opcode
));
11556 if (get_relaxable_immed (opcode
) == i
)
11558 if (tinsn
->record_fix
)
11559 as_bad (_("invalid subtract operand"));
11562 tinsn
->symbol
= expr
->X_add_symbol
;
11563 tinsn
->sub_symbol
= expr
->X_op_symbol
;
11564 tinsn
->offset
= expr
->X_add_number
;
11568 as_bad (_("invalid operand %d on '%s'"),
11569 i
, xtensa_opcode_name (isa
, opcode
));
11573 as_bad (_("invalid expression for operand %d on '%s'"),
11574 i
, xtensa_opcode_name (isa
, opcode
));
11586 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
11588 static xtensa_insnbuf insnbuf
= NULL
;
11589 static xtensa_insnbuf slotbuf
= NULL
;
11592 xtensa_isa isa
= xtensa_default_isa
;
11596 insnbuf
= xtensa_insnbuf_alloc (isa
);
11597 slotbuf
= xtensa_insnbuf_alloc (isa
);
11600 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) f
, 0);
11601 fmt
= xtensa_format_decode (isa
, insnbuf
);
11602 if (fmt
== XTENSA_UNDEFINED
)
11603 as_fatal (_("cannot decode instruction format"));
11604 vinsn
->format
= fmt
;
11605 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
11607 for (i
= 0; i
< vinsn
->num_slots
; i
++)
11609 TInsn
*tinsn
= &vinsn
->slots
[i
];
11610 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
11611 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
11616 /* Expression utilities. */
11618 /* Return TRUE if the expression is an integer constant. */
11621 expr_is_const (const expressionS
*s
)
11623 return (s
->X_op
== O_constant
);
11627 /* Get the expression constant.
11628 Calling this is illegal if expr_is_const () returns TRUE. */
11631 get_expr_const (const expressionS
*s
)
11633 assert (expr_is_const (s
));
11634 return s
->X_add_number
;
11638 /* Set the expression to a constant value. */
11641 set_expr_const (expressionS
*s
, offsetT val
)
11643 s
->X_op
= O_constant
;
11644 s
->X_add_number
= val
;
11645 s
->X_add_symbol
= NULL
;
11646 s
->X_op_symbol
= NULL
;
11651 expr_is_register (const expressionS
*s
)
11653 return (s
->X_op
== O_register
);
11657 /* Get the expression constant.
11658 Calling this is illegal if expr_is_const () returns TRUE. */
11661 get_expr_register (const expressionS
*s
)
11663 assert (expr_is_register (s
));
11664 return s
->X_add_number
;
11668 /* Set the expression to a symbol + constant offset. */
11671 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
11673 s
->X_op
= O_symbol
;
11674 s
->X_add_symbol
= sym
;
11675 s
->X_op_symbol
= NULL
; /* unused */
11676 s
->X_add_number
= offset
;
11680 /* Set the expression to symbol - minus_sym + offset. */
11683 set_expr_symbol_offset_diff (expressionS
*s
,
11685 symbolS
*minus_sym
,
11688 s
->X_op
= O_subtract
;
11689 s
->X_add_symbol
= sym
;
11690 s
->X_op_symbol
= minus_sym
; /* unused */
11691 s
->X_add_number
= offset
;
11695 /* Return TRUE if the two expressions are equal. */
11698 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
11700 if (s1
->X_op
!= s2
->X_op
)
11702 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
11704 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
11706 if (s1
->X_add_number
!= s2
->X_add_number
)
11713 copy_expr (expressionS
*dst
, const expressionS
*src
)
11715 memcpy (dst
, src
, sizeof (expressionS
));
11719 /* Support for the "--rename-section" option. */
11721 struct rename_section_struct
11725 struct rename_section_struct
*next
;
11728 static struct rename_section_struct
*section_rename
;
11731 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
11732 entries to the section_rename list. Note: Specifying multiple
11733 renamings separated by colons is not documented and is retained only
11734 for backward compatibility. */
11737 build_section_rename (const char *arg
)
11739 struct rename_section_struct
*r
;
11740 char *this_arg
= NULL
;
11741 char *next_arg
= NULL
;
11743 for (this_arg
= xstrdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
11745 char *old_name
, *new_name
;
11749 next_arg
= strchr (this_arg
, ':');
11757 old_name
= this_arg
;
11758 new_name
= strchr (this_arg
, '=');
11760 if (*old_name
== '\0')
11762 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
11765 if (!new_name
|| new_name
[1] == '\0')
11767 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
11774 /* Check for invalid section renaming. */
11775 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11777 if (strcmp (r
->old_name
, old_name
) == 0)
11778 as_bad (_("section %s renamed multiple times"), old_name
);
11779 if (strcmp (r
->new_name
, new_name
) == 0)
11780 as_bad (_("multiple sections remapped to output section %s"),
11785 r
= (struct rename_section_struct
*)
11786 xmalloc (sizeof (struct rename_section_struct
));
11787 r
->old_name
= xstrdup (old_name
);
11788 r
->new_name
= xstrdup (new_name
);
11789 r
->next
= section_rename
;
11790 section_rename
= r
;
11796 xtensa_section_rename (char *name
)
11798 struct rename_section_struct
*r
= section_rename
;
11800 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11802 if (strcmp (r
->old_name
, name
) == 0)
11803 return r
->new_name
;