1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
24 #include "safe-ctype.h"
25 #include "tc-xtensa.h"
27 #include "xtensa-relax.h"
28 #include "dwarf2dbg.h"
29 #include "xtensa-istack.h"
30 #include "struc-symbol.h"
31 #include "xtensa-config.h"
33 /* Provide default values for new configuration settings. */
39 #define uint32 unsigned int
42 #define int32 signed int
47 Naming conventions (used somewhat inconsistently):
48 The xtensa_ functions are exported
49 The xg_ functions are internal
51 We also have a couple of different extensibility mechanisms.
52 1) The idiom replacement:
53 This is used when a line is first parsed to
54 replace an instruction pattern with another instruction
55 It is currently limited to replacements of instructions
56 with constant operands.
57 2) The xtensa-relax.c mechanism that has stronger instruction
58 replacement patterns. When an instruction's immediate field
59 does not fit the next instruction sequence is attempted.
60 In addition, "narrow" opcodes are supported this way. */
63 /* Define characters with special meanings to GAS. */
64 const char comment_chars
[] = "#";
65 const char line_comment_chars
[] = "#";
66 const char line_separator_chars
[] = ";";
67 const char EXP_CHARS
[] = "eE";
68 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
71 /* Flags to indicate whether the hardware supports the density and
72 absolute literals options. */
74 bfd_boolean density_supported
= XCHAL_HAVE_DENSITY
;
75 bfd_boolean absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
77 /* Maximum width we would pad an unreachable frag to get alignment. */
78 #define UNREACHABLE_MAX_WIDTH 8
80 static vliw_insn cur_vinsn
;
82 unsigned xtensa_num_pipe_stages
;
83 unsigned xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
85 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
87 /* Some functions are only valid in the front end. This variable
88 allows us to assert that we haven't crossed over into the
90 static bfd_boolean past_xtensa_end
= FALSE
;
92 /* Flags for properties of the last instruction in a segment. */
93 #define FLAG_IS_A0_WRITER 0x1
94 #define FLAG_IS_BAD_LOOPEND 0x2
97 /* We define a special segment names ".literal" to place literals
98 into. The .fini and .init sections are special because they
99 contain code that is moved together by the linker. We give them
100 their own special .fini.literal and .init.literal sections. */
102 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
103 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
104 #define INIT_SECTION_NAME xtensa_section_rename (".init")
105 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
108 /* This type is used for the directive_stack to keep track of the
109 state of the literal collection pools. If lit_prefix is set, it is
110 used to determine the literal section names; otherwise, the literal
111 sections are determined based on the current text section. The
112 lit_seg and lit4_seg fields cache these literal sections, with the
113 current_text_seg field used a tag to indicate whether the cached
116 typedef struct lit_state_struct
119 segT current_text_seg
;
124 static lit_state default_lit_sections
;
127 /* We keep a list of literal segments. The seg_list type is the node
128 for this list. The literal_head pointer is the head of the list,
129 with the literal_head_h dummy node at the start. */
131 typedef struct seg_list_struct
133 struct seg_list_struct
*next
;
137 static seg_list literal_head_h
;
138 static seg_list
*literal_head
= &literal_head_h
;
141 /* Lists of symbols. We keep a list of symbols that label the current
142 instruction, so that we can adjust the symbols when inserting alignment
143 for various instructions. We also keep a list of all the symbols on
144 literals, so that we can fix up those symbols when the literals are
145 later moved into the text sections. */
147 typedef struct sym_list_struct
149 struct sym_list_struct
*next
;
153 static sym_list
*insn_labels
= NULL
;
154 static sym_list
*free_insn_labels
= NULL
;
155 static sym_list
*saved_insn_labels
= NULL
;
157 static sym_list
*literal_syms
;
160 /* Flags to determine whether to prefer const16 or l32r
161 if both options are available. */
162 int prefer_const16
= 0;
165 /* Global flag to indicate when we are emitting literals. */
166 int generating_literals
= 0;
168 /* The following PROPERTY table definitions are copied from
169 <elf/xtensa.h> and must be kept in sync with the code there. */
171 /* Flags in the property tables to specify whether blocks of memory
172 are literals, instructions, data, or unreachable. For
173 instructions, blocks that begin loop targets and branch targets are
174 designated. Blocks that do not allow density, instruction
175 reordering or transformation are also specified. Finally, for
176 branch targets, branch target alignment priority is included.
177 Alignment of the next block is specified in the current block
178 and the size of the current block does not include any fill required
179 to align to the next block. */
181 #define XTENSA_PROP_LITERAL 0x00000001
182 #define XTENSA_PROP_INSN 0x00000002
183 #define XTENSA_PROP_DATA 0x00000004
184 #define XTENSA_PROP_UNREACHABLE 0x00000008
185 /* Instruction only properties at beginning of code. */
186 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
187 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
188 /* Instruction only properties about code. */
189 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
190 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
191 /* Historically, NO_TRANSFORM was a property of instructions,
192 but it should apply to literals under certain circumstances. */
193 #define XTENSA_PROP_NO_TRANSFORM 0x00000100
195 /* Branch target alignment information. This transmits information
196 to the linker optimization about the priority of aligning a
197 particular block for branch target alignment: None, low priority,
198 high priority, or required. These only need to be checked in
199 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
202 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
203 case XTENSA_PROP_BT_ALIGN_NONE:
204 case XTENSA_PROP_BT_ALIGN_LOW:
205 case XTENSA_PROP_BT_ALIGN_HIGH:
206 case XTENSA_PROP_BT_ALIGN_REQUIRE:
208 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
210 /* No branch target alignment. */
211 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
212 /* Low priority branch target alignment. */
213 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
214 /* High priority branch target alignment. */
215 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
216 /* Required branch target alignment. */
217 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
219 #define GET_XTENSA_PROP_BT_ALIGN(flag) \
220 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
221 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
222 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
223 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
226 /* Alignment is specified in the block BEFORE the one that needs
227 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
228 get the required alignment specified as a power of 2. Use
229 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
230 alignment. Be careful of side effects since the SET will evaluate
231 flags twice. Also, note that the SIZE of a block in the property
232 table does not include the alignment size, so the alignment fill
233 must be calculated to determine if two blocks are contiguous.
234 TEXT_ALIGN is not currently implemented but is a placeholder for a
235 possible future implementation. */
237 #define XTENSA_PROP_ALIGN 0x00000800
239 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
241 #define GET_XTENSA_PROP_ALIGNMENT(flag) \
242 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
243 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
244 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
245 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
247 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
250 /* Structure for saving instruction and alignment per-fragment data
251 that will be written to the object file. This structure is
252 equivalent to the actual data that will be written out to the file
253 but is easier to use. We provide a conversion to file flags
254 in frag_flags_to_number. */
256 typedef struct frag_flags_struct frag_flags
;
258 struct frag_flags_struct
260 /* is_literal should only be used after xtensa_move_literals.
261 If you need to check if you are generating a literal fragment,
262 then use the generating_literals global. */
264 unsigned is_literal
: 1;
265 unsigned is_insn
: 1;
266 unsigned is_data
: 1;
267 unsigned is_unreachable
: 1;
269 /* is_specific_opcode implies no_transform. */
270 unsigned is_no_transform
: 1;
274 unsigned is_loop_target
: 1;
275 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
276 unsigned bt_align_priority
: 2;
278 unsigned is_no_density
: 1;
279 /* no_longcalls flag does not need to be placed in the object file. */
281 unsigned is_no_reorder
: 1;
283 /* Uses absolute literal addressing for l32r. */
284 unsigned is_abslit
: 1;
286 unsigned is_align
: 1;
287 unsigned alignment
: 5;
291 /* Structure for saving information about a block of property data
292 for frags that have the same flags. */
293 struct xtensa_block_info_struct
299 struct xtensa_block_info_struct
*next
;
303 /* Structure for saving the current state before emitting literals. */
304 typedef struct emit_state_struct
309 int generating_literals
;
313 /* Opcode placement information */
315 typedef unsigned long long bitfield
;
316 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
317 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
318 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
320 #define MAX_FORMATS 32
322 typedef struct op_placement_info_struct
325 /* A number describing how restrictive the issue is for this
326 opcode. For example, an opcode that fits lots of different
327 formats has a high freedom, as does an opcode that fits
328 only one format but many slots in that format. The most
329 restrictive is the opcode that fits only one slot in one
332 xtensa_format narrowest
;
336 /* formats is a bitfield with the Nth bit set
337 if the opcode fits in the Nth xtensa_format. */
340 /* slots[N]'s Mth bit is set if the op fits in the
341 Mth slot of the Nth xtensa_format. */
342 bitfield slots
[MAX_FORMATS
];
344 /* A count of the number of slots in a given format
345 an op can fit (i.e., the bitcount of the slot field above). */
346 char slots_in_format
[MAX_FORMATS
];
348 } op_placement_info
, *op_placement_info_table
;
350 op_placement_info_table op_placement_table
;
353 /* Extra expression types. */
355 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
356 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
357 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
358 #define O_pcrel O_md4 /* value is a PC-relative offset */
359 #define O_tlsfunc O_md5 /* TLS_FUNC/TLSDESC_FN relocation */
360 #define O_tlsarg O_md6 /* TLS_ARG/TLSDESC_ARG relocation */
361 #define O_tlscall O_md7 /* TLS_CALL relocation */
362 #define O_tpoff O_md8 /* TPOFF relocation */
363 #define O_dtpoff O_md9 /* DTPOFF relocation */
365 struct suffix_reloc_map
369 bfd_reloc_code_real_type reloc
;
370 unsigned char operator;
373 #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op }
375 static struct suffix_reloc_map suffix_relocs
[] =
377 SUFFIX_MAP ("l", BFD_RELOC_LO16
, O_lo16
),
378 SUFFIX_MAP ("h", BFD_RELOC_HI16
, O_hi16
),
379 SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT
, O_pltrel
),
380 SUFFIX_MAP ("pcrel", BFD_RELOC_32_PCREL
, O_pcrel
),
381 SUFFIX_MAP ("tlsfunc", BFD_RELOC_XTENSA_TLS_FUNC
, O_tlsfunc
),
382 SUFFIX_MAP ("tlsarg", BFD_RELOC_XTENSA_TLS_ARG
, O_tlsarg
),
383 SUFFIX_MAP ("tlscall", BFD_RELOC_XTENSA_TLS_CALL
, O_tlscall
),
384 SUFFIX_MAP ("tpoff", BFD_RELOC_XTENSA_TLS_TPOFF
, O_tpoff
),
385 SUFFIX_MAP ("dtpoff", BFD_RELOC_XTENSA_TLS_DTPOFF
, O_dtpoff
),
386 { (char *) 0, 0, BFD_RELOC_UNUSED
, 0 }
400 directive_literal_prefix
,
402 directive_absolute_literals
,
403 directive_last_directive
409 bfd_boolean can_be_negated
;
412 const directive_infoS directive_info
[] =
415 { "literal", FALSE
},
417 { "transform", TRUE
},
418 { "freeregs", FALSE
},
419 { "longcalls", TRUE
},
420 { "literal_prefix", FALSE
},
421 { "schedule", TRUE
},
422 { "absolute-literals", TRUE
}
425 bfd_boolean directive_state
[] =
429 #if !XCHAL_HAVE_DENSITY
434 TRUE
, /* transform */
435 FALSE
, /* freeregs */
436 FALSE
, /* longcalls */
437 FALSE
, /* literal_prefix */
438 FALSE
, /* schedule */
439 #if XSHAL_USE_ABSOLUTE_LITERALS
440 TRUE
/* absolute_literals */
442 FALSE
/* absolute_literals */
447 /* Directive functions. */
449 static void xtensa_begin_directive (int);
450 static void xtensa_end_directive (int);
451 static void xtensa_literal_prefix (void);
452 static void xtensa_literal_position (int);
453 static void xtensa_literal_pseudo (int);
454 static void xtensa_frequency_pseudo (int);
455 static void xtensa_elf_cons (int);
456 static void xtensa_leb128 (int);
458 /* Parsing and Idiom Translation. */
460 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
462 /* Various Other Internal Functions. */
464 extern bfd_boolean
xg_is_single_relaxable_insn (TInsn
*, TInsn
*, bfd_boolean
);
465 static bfd_boolean
xg_build_to_insn (TInsn
*, TInsn
*, BuildInstr
*);
466 static void xtensa_mark_literal_pool_location (void);
467 static addressT
get_expanded_loop_offset (xtensa_opcode
);
468 static fragS
*get_literal_pool_location (segT
);
469 static void set_literal_pool_location (segT
, fragS
*);
470 static void xtensa_set_frag_assembly_state (fragS
*);
471 static void finish_vinsn (vliw_insn
*);
472 static bfd_boolean
emit_single_op (TInsn
*);
473 static int total_frag_text_expansion (fragS
*);
475 /* Alignment Functions. */
477 static int get_text_align_power (unsigned);
478 static int get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
479 static int branch_align_power (segT
);
481 /* Helpers for xtensa_relax_frag(). */
483 static long relax_frag_add_nop (fragS
*);
485 /* Accessors for additional per-subsegment information. */
487 static unsigned get_last_insn_flags (segT
, subsegT
);
488 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
489 static float get_subseg_total_freq (segT
, subsegT
);
490 static float get_subseg_target_freq (segT
, subsegT
);
491 static void set_subseg_freq (segT
, subsegT
, float, float);
493 /* Segment list functions. */
495 static void xtensa_move_literals (void);
496 static void xtensa_reorder_segments (void);
497 static void xtensa_switch_to_literal_fragment (emit_state
*);
498 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
499 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
500 static void xtensa_restore_emit_state (emit_state
*);
501 static segT
cache_literal_section (bfd_boolean
);
503 /* Import from elf32-xtensa.c in BFD library. */
505 extern asection
*xtensa_make_property_section (asection
*, const char *);
507 /* op_placement_info functions. */
509 static void init_op_placement_info_table (void);
510 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
511 static int xg_get_single_size (xtensa_opcode
);
512 static xtensa_format
xg_get_single_format (xtensa_opcode
);
513 static int xg_get_single_slot (xtensa_opcode
);
515 /* TInsn and IStack functions. */
517 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
518 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
519 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
520 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
521 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
522 static void tinsn_from_chars (TInsn
*, char *, int);
523 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
524 static int get_num_stack_text_bytes (IStack
*);
525 static int get_num_stack_literal_bytes (IStack
*);
527 /* vliw_insn functions. */
529 static void xg_init_vinsn (vliw_insn
*);
530 static void xg_copy_vinsn (vliw_insn
*, vliw_insn
*);
531 static void xg_clear_vinsn (vliw_insn
*);
532 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
533 static void xg_free_vinsn (vliw_insn
*);
534 static bfd_boolean vinsn_to_insnbuf
535 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
536 static void vinsn_from_chars (vliw_insn
*, char *);
538 /* Expression Utilities. */
540 bfd_boolean
expr_is_const (const expressionS
*);
541 offsetT
get_expr_const (const expressionS
*);
542 void set_expr_const (expressionS
*, offsetT
);
543 bfd_boolean
expr_is_register (const expressionS
*);
544 offsetT
get_expr_register (const expressionS
*);
545 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
546 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
547 static void copy_expr (expressionS
*, const expressionS
*);
549 /* Section renaming. */
551 static void build_section_rename (const char *);
554 /* ISA imported from bfd. */
555 extern xtensa_isa xtensa_default_isa
;
557 extern int target_big_endian
;
559 static xtensa_opcode xtensa_addi_opcode
;
560 static xtensa_opcode xtensa_addmi_opcode
;
561 static xtensa_opcode xtensa_call0_opcode
;
562 static xtensa_opcode xtensa_call4_opcode
;
563 static xtensa_opcode xtensa_call8_opcode
;
564 static xtensa_opcode xtensa_call12_opcode
;
565 static xtensa_opcode xtensa_callx0_opcode
;
566 static xtensa_opcode xtensa_callx4_opcode
;
567 static xtensa_opcode xtensa_callx8_opcode
;
568 static xtensa_opcode xtensa_callx12_opcode
;
569 static xtensa_opcode xtensa_const16_opcode
;
570 static xtensa_opcode xtensa_entry_opcode
;
571 static xtensa_opcode xtensa_extui_opcode
;
572 static xtensa_opcode xtensa_movi_opcode
;
573 static xtensa_opcode xtensa_movi_n_opcode
;
574 static xtensa_opcode xtensa_isync_opcode
;
575 static xtensa_opcode xtensa_j_opcode
;
576 static xtensa_opcode xtensa_jx_opcode
;
577 static xtensa_opcode xtensa_l32r_opcode
;
578 static xtensa_opcode xtensa_loop_opcode
;
579 static xtensa_opcode xtensa_loopnez_opcode
;
580 static xtensa_opcode xtensa_loopgtz_opcode
;
581 static xtensa_opcode xtensa_nop_opcode
;
582 static xtensa_opcode xtensa_nop_n_opcode
;
583 static xtensa_opcode xtensa_or_opcode
;
584 static xtensa_opcode xtensa_ret_opcode
;
585 static xtensa_opcode xtensa_ret_n_opcode
;
586 static xtensa_opcode xtensa_retw_opcode
;
587 static xtensa_opcode xtensa_retw_n_opcode
;
588 static xtensa_opcode xtensa_rsr_lcount_opcode
;
589 static xtensa_opcode xtensa_waiti_opcode
;
592 /* Command-line Options. */
594 bfd_boolean use_literal_section
= TRUE
;
595 enum flix_level produce_flix
= FLIX_ALL
;
596 static bfd_boolean align_targets
= TRUE
;
597 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
598 static bfd_boolean has_a0_b_retw
= FALSE
;
599 static bfd_boolean workaround_a0_b_retw
= FALSE
;
600 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
601 static bfd_boolean workaround_short_loop
= FALSE
;
602 static bfd_boolean maybe_has_short_loop
= FALSE
;
603 static bfd_boolean workaround_close_loop_end
= FALSE
;
604 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
605 static bfd_boolean enforce_three_byte_loop_align
= FALSE
;
607 /* When workaround_short_loops is TRUE, all loops with early exits must
608 have at least 3 instructions. workaround_all_short_loops is a modifier
609 to the workaround_short_loop flag. In addition to the
610 workaround_short_loop actions, all straightline loopgtz and loopnez
611 must have at least 3 instructions. */
613 static bfd_boolean workaround_all_short_loops
= FALSE
;
617 xtensa_setup_hw_workarounds (int earliest
, int latest
)
619 if (earliest
> latest
)
620 as_fatal (_("illegal range of target hardware versions"));
622 /* Enable all workarounds for pre-T1050.0 hardware. */
623 if (earliest
< 105000 || latest
< 105000)
625 workaround_a0_b_retw
|= TRUE
;
626 workaround_b_j_loop_end
|= TRUE
;
627 workaround_short_loop
|= TRUE
;
628 workaround_close_loop_end
|= TRUE
;
629 workaround_all_short_loops
|= TRUE
;
630 enforce_three_byte_loop_align
= TRUE
;
637 option_density
= OPTION_MD_BASE
,
641 option_no_generate_flix
,
648 option_no_link_relax
,
656 option_text_section_literals
,
657 option_no_text_section_literals
,
659 option_absolute_literals
,
660 option_no_absolute_literals
,
662 option_align_targets
,
663 option_no_align_targets
,
665 option_warn_unaligned_targets
,
670 option_workaround_a0_b_retw
,
671 option_no_workaround_a0_b_retw
,
673 option_workaround_b_j_loop_end
,
674 option_no_workaround_b_j_loop_end
,
676 option_workaround_short_loop
,
677 option_no_workaround_short_loop
,
679 option_workaround_all_short_loops
,
680 option_no_workaround_all_short_loops
,
682 option_workaround_close_loop_end
,
683 option_no_workaround_close_loop_end
,
685 option_no_workarounds
,
687 option_rename_section_name
,
690 option_prefer_const16
,
692 option_target_hardware
695 const char *md_shortopts
= "";
697 struct option md_longopts
[] =
699 { "density", no_argument
, NULL
, option_density
},
700 { "no-density", no_argument
, NULL
, option_no_density
},
702 { "flix", no_argument
, NULL
, option_flix
},
703 { "no-generate-flix", no_argument
, NULL
, option_no_generate_flix
},
704 { "no-allow-flix", no_argument
, NULL
, option_no_flix
},
706 /* Both "relax" and "generics" are deprecated and treated as equivalent
707 to the "transform" option. */
708 { "relax", no_argument
, NULL
, option_relax
},
709 { "no-relax", no_argument
, NULL
, option_no_relax
},
710 { "generics", no_argument
, NULL
, option_generics
},
711 { "no-generics", no_argument
, NULL
, option_no_generics
},
713 { "transform", no_argument
, NULL
, option_transform
},
714 { "no-transform", no_argument
, NULL
, option_no_transform
},
715 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
716 { "no-text-section-literals", no_argument
, NULL
,
717 option_no_text_section_literals
},
718 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
719 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
720 /* This option was changed from -align-target to -target-align
721 because it conflicted with the "-al" option. */
722 { "target-align", no_argument
, NULL
, option_align_targets
},
723 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
724 { "warn-unaligned-targets", no_argument
, NULL
,
725 option_warn_unaligned_targets
},
726 { "longcalls", no_argument
, NULL
, option_longcalls
},
727 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
729 { "no-workaround-a0-b-retw", no_argument
, NULL
,
730 option_no_workaround_a0_b_retw
},
731 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
733 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
734 option_no_workaround_b_j_loop_end
},
735 { "workaround-b-j-loop-end", no_argument
, NULL
,
736 option_workaround_b_j_loop_end
},
738 { "no-workaround-short-loops", no_argument
, NULL
,
739 option_no_workaround_short_loop
},
740 { "workaround-short-loops", no_argument
, NULL
,
741 option_workaround_short_loop
},
743 { "no-workaround-all-short-loops", no_argument
, NULL
,
744 option_no_workaround_all_short_loops
},
745 { "workaround-all-short-loop", no_argument
, NULL
,
746 option_workaround_all_short_loops
},
748 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
749 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
751 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
753 { "no-workaround-close-loop-end", no_argument
, NULL
,
754 option_no_workaround_close_loop_end
},
755 { "workaround-close-loop-end", no_argument
, NULL
,
756 option_workaround_close_loop_end
},
758 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
760 { "link-relax", no_argument
, NULL
, option_link_relax
},
761 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
763 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
765 { NULL
, no_argument
, NULL
, 0 }
768 size_t md_longopts_size
= sizeof md_longopts
;
772 md_parse_option (int c
, char *arg
)
777 as_warn (_("--density option is ignored"));
779 case option_no_density
:
780 as_warn (_("--no-density option is ignored"));
782 case option_link_relax
:
785 case option_no_link_relax
:
789 produce_flix
= FLIX_ALL
;
791 case option_no_generate_flix
:
792 produce_flix
= FLIX_NO_GENERATE
;
795 produce_flix
= FLIX_NONE
;
797 case option_generics
:
798 as_warn (_("--generics is deprecated; use --transform instead"));
799 return md_parse_option (option_transform
, arg
);
800 case option_no_generics
:
801 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
802 return md_parse_option (option_no_transform
, arg
);
804 as_warn (_("--relax is deprecated; use --transform instead"));
805 return md_parse_option (option_transform
, arg
);
806 case option_no_relax
:
807 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
808 return md_parse_option (option_no_transform
, arg
);
809 case option_longcalls
:
810 directive_state
[directive_longcalls
] = TRUE
;
812 case option_no_longcalls
:
813 directive_state
[directive_longcalls
] = FALSE
;
815 case option_text_section_literals
:
816 use_literal_section
= FALSE
;
818 case option_no_text_section_literals
:
819 use_literal_section
= TRUE
;
821 case option_absolute_literals
:
822 if (!absolute_literals_supported
)
824 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
827 directive_state
[directive_absolute_literals
] = TRUE
;
829 case option_no_absolute_literals
:
830 directive_state
[directive_absolute_literals
] = FALSE
;
833 case option_workaround_a0_b_retw
:
834 workaround_a0_b_retw
= TRUE
;
836 case option_no_workaround_a0_b_retw
:
837 workaround_a0_b_retw
= FALSE
;
839 case option_workaround_b_j_loop_end
:
840 workaround_b_j_loop_end
= TRUE
;
842 case option_no_workaround_b_j_loop_end
:
843 workaround_b_j_loop_end
= FALSE
;
846 case option_workaround_short_loop
:
847 workaround_short_loop
= TRUE
;
849 case option_no_workaround_short_loop
:
850 workaround_short_loop
= FALSE
;
853 case option_workaround_all_short_loops
:
854 workaround_all_short_loops
= TRUE
;
856 case option_no_workaround_all_short_loops
:
857 workaround_all_short_loops
= FALSE
;
860 case option_workaround_close_loop_end
:
861 workaround_close_loop_end
= TRUE
;
863 case option_no_workaround_close_loop_end
:
864 workaround_close_loop_end
= FALSE
;
867 case option_no_workarounds
:
868 workaround_a0_b_retw
= FALSE
;
869 workaround_b_j_loop_end
= FALSE
;
870 workaround_short_loop
= FALSE
;
871 workaround_all_short_loops
= FALSE
;
872 workaround_close_loop_end
= FALSE
;
875 case option_align_targets
:
876 align_targets
= TRUE
;
878 case option_no_align_targets
:
879 align_targets
= FALSE
;
882 case option_warn_unaligned_targets
:
883 warn_unaligned_branch_targets
= TRUE
;
886 case option_rename_section_name
:
887 build_section_rename (arg
);
891 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
892 should be emitted or not. FIXME: Not implemented. */
895 case option_prefer_l32r
:
897 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
901 case option_prefer_const16
:
903 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
907 case option_target_hardware
:
909 int earliest
, latest
= 0;
910 if (*arg
== 0 || *arg
== '-')
911 as_fatal (_("invalid target hardware version"));
913 earliest
= strtol (arg
, &arg
, 0);
917 else if (*arg
== '-')
920 as_fatal (_("invalid target hardware version"));
921 latest
= strtol (arg
, &arg
, 0);
924 as_fatal (_("invalid target hardware version"));
926 xtensa_setup_hw_workarounds (earliest
, latest
);
930 case option_transform
:
931 /* This option has no affect other than to use the defaults,
932 which are already set. */
935 case option_no_transform
:
936 /* This option turns off all transformations of any kind.
937 However, because we want to preserve the state of other
938 directives, we only change its own field. Thus, before
939 you perform any transformation, always check if transform
940 is available. If you use the functions we provide for this
941 purpose, you will be ok. */
942 directive_state
[directive_transform
] = FALSE
;
952 md_show_usage (FILE *stream
)
956 --[no-]text-section-literals\n\
957 [Do not] put literals in the text section\n\
958 --[no-]absolute-literals\n\
959 [Do not] default to use non-PC-relative literals\n\
960 --[no-]target-align [Do not] try to align branch targets\n\
961 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
962 --[no-]transform [Do not] transform instructions\n\
963 --flix both allow hand-written and generate flix bundles\n\
964 --no-generate-flix allow hand-written but do not generate\n\
966 --no-allow-flix neither allow hand-written nor generate\n\
968 --rename-section old=new Rename section 'old' to 'new'\n", stream
);
972 /* Functions related to the list of current label symbols. */
975 xtensa_add_insn_label (symbolS
*sym
)
979 if (!free_insn_labels
)
980 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
983 l
= free_insn_labels
;
984 free_insn_labels
= l
->next
;
988 l
->next
= insn_labels
;
994 xtensa_clear_insn_labels (void)
998 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1006 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
)
1010 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
1012 symbolS
*lit_sym
= lit
->sym
;
1013 S_SET_VALUE (lit_sym
, new_offset
);
1014 symbol_set_frag (lit_sym
, new_frag
);
1019 /* Directive data and functions. */
1021 typedef struct state_stackS_struct
1023 directiveE directive
;
1024 bfd_boolean negated
;
1025 bfd_boolean old_state
;
1029 struct state_stackS_struct
*prev
;
1032 state_stackS
*directive_state_stack
;
1034 const pseudo_typeS md_pseudo_table
[] =
1036 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
1037 { "literal_position", xtensa_literal_position
, 0 },
1038 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
1039 { "long", xtensa_elf_cons
, 4 },
1040 { "word", xtensa_elf_cons
, 4 },
1041 { "4byte", xtensa_elf_cons
, 4 },
1042 { "short", xtensa_elf_cons
, 2 },
1043 { "2byte", xtensa_elf_cons
, 2 },
1044 { "sleb128", xtensa_leb128
, 1},
1045 { "uleb128", xtensa_leb128
, 0},
1046 { "begin", xtensa_begin_directive
, 0 },
1047 { "end", xtensa_end_directive
, 0 },
1048 { "literal", xtensa_literal_pseudo
, 0 },
1049 { "frequency", xtensa_frequency_pseudo
, 0 },
1055 use_transform (void)
1057 /* After md_end, you should be checking frag by frag, rather
1058 than state directives. */
1059 gas_assert (!past_xtensa_end
);
1060 return directive_state
[directive_transform
];
1065 do_align_targets (void)
1067 /* Do not use this function after md_end; just look at align_targets
1068 instead. There is no target-align directive, so alignment is either
1069 enabled for all frags or not done at all. */
1070 gas_assert (!past_xtensa_end
);
1071 return align_targets
&& use_transform ();
1076 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1080 state_stackS
*stack
= (state_stackS
*) xmalloc (sizeof (state_stackS
));
1082 as_where (&file
, &line
);
1084 stack
->directive
= directive
;
1085 stack
->negated
= negated
;
1086 stack
->old_state
= directive_state
[directive
];
1089 stack
->datum
= datum
;
1090 stack
->prev
= directive_state_stack
;
1091 directive_state_stack
= stack
;
1093 directive_state
[directive
] = !negated
;
1098 directive_pop (directiveE
*directive
,
1099 bfd_boolean
*negated
,
1104 state_stackS
*top
= directive_state_stack
;
1106 if (!directive_state_stack
)
1108 as_bad (_("unmatched end directive"));
1109 *directive
= directive_none
;
1113 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1114 *directive
= top
->directive
;
1115 *negated
= top
->negated
;
1118 *datum
= top
->datum
;
1119 directive_state_stack
= top
->prev
;
1125 directive_balance (void)
1127 while (directive_state_stack
)
1129 directiveE directive
;
1130 bfd_boolean negated
;
1135 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1136 as_warn_where ((char *) file
, line
,
1137 _(".begin directive with no matching .end directive"));
1143 inside_directive (directiveE dir
)
1145 state_stackS
*top
= directive_state_stack
;
1147 while (top
&& top
->directive
!= dir
)
1150 return (top
!= NULL
);
1155 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1159 char *directive_string
;
1161 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1166 input_line_pointer
+= 3;
1169 len
= strspn (input_line_pointer
,
1170 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1172 /* This code is a hack to make .begin [no-][generics|relax] exactly
1173 equivalent to .begin [no-]transform. We should remove it when
1174 we stop accepting those options. */
1176 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1178 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1179 directive_string
= "transform";
1181 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1183 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1184 directive_string
= "transform";
1187 directive_string
= input_line_pointer
;
1189 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1191 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1193 input_line_pointer
+= len
;
1194 *directive
= (directiveE
) i
;
1195 if (*negated
&& !directive_info
[i
].can_be_negated
)
1196 as_bad (_("directive %s cannot be negated"),
1197 directive_info
[i
].name
);
1202 as_bad (_("unknown directive"));
1203 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1208 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1210 directiveE directive
;
1211 bfd_boolean negated
;
1215 get_directive (&directive
, &negated
);
1216 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1218 discard_rest_of_line ();
1222 if (cur_vinsn
.inside_bundle
)
1223 as_bad (_("directives are not valid inside bundles"));
1227 case directive_literal
:
1228 if (!inside_directive (directive_literal
))
1230 /* Previous labels go with whatever follows this directive, not with
1231 the literal, so save them now. */
1232 saved_insn_labels
= insn_labels
;
1235 as_warn (_(".begin literal is deprecated; use .literal instead"));
1236 state
= (emit_state
*) xmalloc (sizeof (emit_state
));
1237 xtensa_switch_to_literal_fragment (state
);
1238 directive_push (directive_literal
, negated
, state
);
1241 case directive_literal_prefix
:
1242 /* Have to flush pending output because a movi relaxed to an l32r
1243 might produce a literal. */
1244 md_flush_pending_output ();
1245 /* Check to see if the current fragment is a literal
1246 fragment. If it is, then this operation is not allowed. */
1247 if (generating_literals
)
1249 as_bad (_("cannot set literal_prefix inside literal fragment"));
1253 /* Allocate the literal state for this section and push
1254 onto the directive stack. */
1255 ls
= xmalloc (sizeof (lit_state
));
1258 *ls
= default_lit_sections
;
1259 directive_push (directive_literal_prefix
, negated
, ls
);
1261 /* Process the new prefix. */
1262 xtensa_literal_prefix ();
1265 case directive_freeregs
:
1266 /* This information is currently unused, but we'll accept the statement
1267 and just discard the rest of the line. This won't check the syntax,
1268 but it will accept every correct freeregs directive. */
1269 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1270 directive_push (directive_freeregs
, negated
, 0);
1273 case directive_schedule
:
1274 md_flush_pending_output ();
1275 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1276 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1277 directive_push (directive_schedule
, negated
, 0);
1278 xtensa_set_frag_assembly_state (frag_now
);
1281 case directive_density
:
1282 as_warn (_(".begin [no-]density is ignored"));
1285 case directive_absolute_literals
:
1286 md_flush_pending_output ();
1287 if (!absolute_literals_supported
&& !negated
)
1289 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1292 xtensa_set_frag_assembly_state (frag_now
);
1293 directive_push (directive
, negated
, 0);
1297 md_flush_pending_output ();
1298 xtensa_set_frag_assembly_state (frag_now
);
1299 directive_push (directive
, negated
, 0);
1303 demand_empty_rest_of_line ();
1308 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1310 directiveE begin_directive
, end_directive
;
1311 bfd_boolean begin_negated
, end_negated
;
1315 emit_state
**state_ptr
;
1318 if (cur_vinsn
.inside_bundle
)
1319 as_bad (_("directives are not valid inside bundles"));
1321 get_directive (&end_directive
, &end_negated
);
1323 md_flush_pending_output ();
1325 switch (end_directive
)
1327 case (directiveE
) XTENSA_UNDEFINED
:
1328 discard_rest_of_line ();
1331 case directive_density
:
1332 as_warn (_(".end [no-]density is ignored"));
1333 demand_empty_rest_of_line ();
1336 case directive_absolute_literals
:
1337 if (!absolute_literals_supported
&& !end_negated
)
1339 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1340 demand_empty_rest_of_line ();
1349 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1350 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1351 (const void **) state_ptr
);
1353 if (begin_directive
!= directive_none
)
1355 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1357 as_bad (_("does not match begin %s%s at %s:%d"),
1358 begin_negated
? "no-" : "",
1359 directive_info
[begin_directive
].name
, file
, line
);
1363 switch (end_directive
)
1365 case directive_literal
:
1366 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1367 xtensa_restore_emit_state (state
);
1368 xtensa_set_frag_assembly_state (frag_now
);
1370 if (!inside_directive (directive_literal
))
1372 /* Restore the list of current labels. */
1373 xtensa_clear_insn_labels ();
1374 insn_labels
= saved_insn_labels
;
1378 case directive_literal_prefix
:
1379 /* Restore the default collection sections from saved state. */
1380 s
= (lit_state
*) state
;
1382 default_lit_sections
= *s
;
1384 /* Free the state storage. */
1385 free (s
->lit_prefix
);
1389 case directive_schedule
:
1390 case directive_freeregs
:
1394 xtensa_set_frag_assembly_state (frag_now
);
1400 demand_empty_rest_of_line ();
1404 /* Place an aligned literal fragment at the current location. */
1407 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1409 md_flush_pending_output ();
1411 if (inside_directive (directive_literal
))
1412 as_warn (_(".literal_position inside literal directive; ignoring"));
1413 xtensa_mark_literal_pool_location ();
1415 demand_empty_rest_of_line ();
1416 xtensa_clear_insn_labels ();
1420 /* Support .literal label, expr, ... */
1423 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1426 char *p
, *base_name
;
1430 if (inside_directive (directive_literal
))
1432 as_bad (_(".literal not allowed inside .begin literal region"));
1433 ignore_rest_of_line ();
1437 md_flush_pending_output ();
1439 /* Previous labels go with whatever follows this directive, not with
1440 the literal, so save them now. */
1441 saved_insn_labels
= insn_labels
;
1444 /* If we are using text-section literals, then this is the right value... */
1447 base_name
= input_line_pointer
;
1449 xtensa_switch_to_literal_fragment (&state
);
1451 /* ...but if we aren't using text-section-literals, then we
1452 need to put them in the section we just switched to. */
1453 if (use_literal_section
|| directive_state
[directive_absolute_literals
])
1456 /* All literals are aligned to four-byte boundaries. */
1457 frag_align (2, 0, 0);
1458 record_alignment (now_seg
, 2);
1460 c
= get_symbol_end ();
1461 /* Just after name is now '\0'. */
1462 p
= input_line_pointer
;
1466 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1468 as_bad (_("expected comma or colon after symbol name; "
1469 "rest of line ignored"));
1470 ignore_rest_of_line ();
1471 xtensa_restore_emit_state (&state
);
1479 input_line_pointer
++; /* skip ',' or ':' */
1481 xtensa_elf_cons (4);
1483 xtensa_restore_emit_state (&state
);
1485 /* Restore the list of current labels. */
1486 xtensa_clear_insn_labels ();
1487 insn_labels
= saved_insn_labels
;
1492 xtensa_literal_prefix (void)
1497 /* Parse the new prefix from the input_line_pointer. */
1499 len
= strspn (input_line_pointer
,
1500 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1501 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1503 /* Get a null-terminated copy of the name. */
1504 name
= xmalloc (len
+ 1);
1506 strncpy (name
, input_line_pointer
, len
);
1509 /* Skip the name in the input line. */
1510 input_line_pointer
+= len
;
1512 default_lit_sections
.lit_prefix
= name
;
1514 /* Clear cached literal sections, since the prefix has changed. */
1515 default_lit_sections
.lit_seg
= NULL
;
1516 default_lit_sections
.lit4_seg
= NULL
;
1520 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1523 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1525 float fall_through_f
, target_f
;
1527 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1528 if (fall_through_f
< 0)
1530 as_bad (_("fall through frequency must be greater than 0"));
1531 ignore_rest_of_line ();
1535 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1538 as_bad (_("branch target frequency must be greater than 0"));
1539 ignore_rest_of_line ();
1543 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1545 demand_empty_rest_of_line ();
1549 /* Like normal .long/.short/.word, except support @plt, etc.
1550 Clobbers input_line_pointer, checks end-of-line. */
1553 xtensa_elf_cons (int nbytes
)
1556 bfd_reloc_code_real_type reloc
;
1558 md_flush_pending_output ();
1560 if (cur_vinsn
.inside_bundle
)
1561 as_bad (_("directives are not valid inside bundles"));
1563 if (is_it_end_of_statement ())
1565 demand_empty_rest_of_line ();
1572 if (exp
.X_op
== O_symbol
1573 && *input_line_pointer
== '@'
1574 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1577 reloc_howto_type
*reloc_howto
=
1578 bfd_reloc_type_lookup (stdoutput
, reloc
);
1580 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1581 as_bad (_("unsupported relocation"));
1582 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1583 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1584 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1585 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1586 as_bad (_("opcode-specific %s relocation used outside "
1587 "an instruction"), reloc_howto
->name
);
1588 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1589 as_bad (_("%s relocations do not fit in %d bytes"),
1590 reloc_howto
->name
, nbytes
);
1591 else if (reloc
== BFD_RELOC_XTENSA_TLS_FUNC
1592 || reloc
== BFD_RELOC_XTENSA_TLS_ARG
1593 || reloc
== BFD_RELOC_XTENSA_TLS_CALL
)
1594 as_bad (_("invalid use of %s relocation"), reloc_howto
->name
);
1597 char *p
= frag_more ((int) nbytes
);
1598 xtensa_set_frag_assembly_state (frag_now
);
1599 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1600 nbytes
, &exp
, reloc_howto
->pc_relative
, reloc
);
1605 xtensa_set_frag_assembly_state (frag_now
);
1606 emit_expr (&exp
, (unsigned int) nbytes
);
1609 while (*input_line_pointer
++ == ',');
1611 input_line_pointer
--; /* Put terminator back into stream. */
1612 demand_empty_rest_of_line ();
1615 static bfd_boolean is_leb128_expr
;
1618 xtensa_leb128 (int sign
)
1620 is_leb128_expr
= TRUE
;
1622 is_leb128_expr
= FALSE
;
1626 /* Parsing and Idiom Translation. */
1628 /* Parse @plt, etc. and return the desired relocation. */
1629 static bfd_reloc_code_real_type
1630 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1637 struct suffix_reloc_map
*ptr
;
1640 return BFD_RELOC_NONE
;
1642 for (ch
= *str
, str2
= ident
;
1643 (str2
< ident
+ sizeof (ident
) - 1
1644 && (ISALNUM (ch
) || ch
== '@'));
1647 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1654 for (ptr
= &suffix_relocs
[0]; ptr
->length
> 0; ptr
++)
1655 if (ch
== ptr
->suffix
[0]
1656 && len
== ptr
->length
1657 && memcmp (ident
, ptr
->suffix
, ptr
->length
) == 0)
1659 /* Now check for "identifier@suffix+constant". */
1660 if (*str
== '-' || *str
== '+')
1662 char *orig_line
= input_line_pointer
;
1663 expressionS new_exp
;
1665 input_line_pointer
= str
;
1666 expression (&new_exp
);
1667 if (new_exp
.X_op
== O_constant
)
1669 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1670 str
= input_line_pointer
;
1673 if (&input_line_pointer
!= str_p
)
1674 input_line_pointer
= orig_line
;
1681 return BFD_RELOC_UNUSED
;
1685 /* Find the matching operator type. */
1686 static unsigned char
1687 map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc
)
1689 struct suffix_reloc_map
*sfx
;
1690 unsigned char operator = (unsigned char) -1;
1692 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1694 if (sfx
->reloc
== reloc
)
1696 operator = sfx
->operator;
1700 gas_assert (operator != (unsigned char) -1);
1705 /* Find the matching reloc type. */
1706 static bfd_reloc_code_real_type
1707 map_operator_to_reloc (unsigned char operator, bfd_boolean is_literal
)
1709 struct suffix_reloc_map
*sfx
;
1710 bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
1712 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1714 if (sfx
->operator == operator)
1723 if (reloc
== BFD_RELOC_XTENSA_TLS_FUNC
)
1724 return BFD_RELOC_XTENSA_TLSDESC_FN
;
1725 else if (reloc
== BFD_RELOC_XTENSA_TLS_ARG
)
1726 return BFD_RELOC_XTENSA_TLSDESC_ARG
;
1729 if (reloc
== BFD_RELOC_UNUSED
)
1730 return BFD_RELOC_32
;
1737 expression_end (const char *name
)
1760 #define ERROR_REG_NUM ((unsigned) -1)
1763 tc_get_register (const char *prefix
)
1766 const char *next_expr
;
1767 const char *old_line_pointer
;
1770 old_line_pointer
= input_line_pointer
;
1772 if (*input_line_pointer
== '$')
1773 ++input_line_pointer
;
1775 /* Accept "sp" as a synonym for "a1". */
1776 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1777 && expression_end (input_line_pointer
+ 2))
1779 input_line_pointer
+= 2;
1780 return 1; /* AR[1] */
1783 while (*input_line_pointer
++ == *prefix
++)
1785 --input_line_pointer
;
1790 as_bad (_("bad register name: %s"), old_line_pointer
);
1791 return ERROR_REG_NUM
;
1794 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1796 as_bad (_("bad register number: %s"), input_line_pointer
);
1797 return ERROR_REG_NUM
;
1802 while (ISDIGIT ((int) *input_line_pointer
))
1803 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1805 if (!(next_expr
= expression_end (input_line_pointer
)))
1807 as_bad (_("bad register name: %s"), old_line_pointer
);
1808 return ERROR_REG_NUM
;
1811 input_line_pointer
= (char *) next_expr
;
1818 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1820 xtensa_isa isa
= xtensa_default_isa
;
1822 /* Check if this is an immediate operand. */
1823 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1825 bfd_reloc_code_real_type reloc
;
1826 segT t
= expression (tok
);
1827 if (t
== absolute_section
1828 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1830 gas_assert (tok
->X_op
== O_constant
);
1831 tok
->X_op
= O_symbol
;
1832 tok
->X_add_symbol
= &abs_symbol
;
1835 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1836 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1841 case BFD_RELOC_LO16
:
1842 if (tok
->X_op
== O_constant
)
1844 tok
->X_add_number
&= 0xffff;
1848 case BFD_RELOC_HI16
:
1849 if (tok
->X_op
== O_constant
)
1851 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1855 case BFD_RELOC_UNUSED
:
1856 as_bad (_("unsupported relocation"));
1858 case BFD_RELOC_32_PCREL
:
1859 as_bad (_("pcrel relocation not allowed in an instruction"));
1864 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
1869 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1870 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1872 if (reg
!= ERROR_REG_NUM
) /* Already errored */
1875 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
1876 as_bad (_("register number out of range"));
1879 tok
->X_op
= O_register
;
1880 tok
->X_add_symbol
= 0;
1881 tok
->X_add_number
= reg
;
1886 /* Split up the arguments for an opcode or pseudo-op. */
1889 tokenize_arguments (char **args
, char *str
)
1891 char *old_input_line_pointer
;
1892 bfd_boolean saw_comma
= FALSE
;
1893 bfd_boolean saw_arg
= FALSE
;
1894 bfd_boolean saw_colon
= FALSE
;
1896 char *arg_end
, *arg
;
1899 /* Save and restore input_line_pointer around this function. */
1900 old_input_line_pointer
= input_line_pointer
;
1901 input_line_pointer
= str
;
1903 while (*input_line_pointer
)
1906 switch (*input_line_pointer
)
1913 input_line_pointer
++;
1914 if (saw_comma
|| saw_colon
|| !saw_arg
)
1920 input_line_pointer
++;
1921 if (saw_comma
|| saw_colon
|| !saw_arg
)
1927 if (!saw_comma
&& !saw_colon
&& saw_arg
)
1930 arg_end
= input_line_pointer
+ 1;
1931 while (!expression_end (arg_end
))
1934 arg_len
= arg_end
- input_line_pointer
;
1935 arg
= (char *) xmalloc ((saw_colon
? 1 : 0) + arg_len
+ 1);
1936 args
[num_args
] = arg
;
1940 strncpy (arg
, input_line_pointer
, arg_len
);
1941 arg
[arg_len
] = '\0';
1943 input_line_pointer
= arg_end
;
1953 if (saw_comma
|| saw_colon
)
1955 input_line_pointer
= old_input_line_pointer
;
1960 as_bad (_("extra comma"));
1962 as_bad (_("extra colon"));
1964 as_bad (_("missing argument"));
1966 as_bad (_("missing comma or colon"));
1967 input_line_pointer
= old_input_line_pointer
;
1972 /* Parse the arguments to an opcode. Return TRUE on error. */
1975 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
1977 expressionS
*tok
, *last_tok
;
1978 xtensa_opcode opcode
= insn
->opcode
;
1979 bfd_boolean had_error
= TRUE
;
1980 xtensa_isa isa
= xtensa_default_isa
;
1981 int n
, num_regs
= 0;
1982 int opcode_operand_count
;
1983 int opnd_cnt
, last_opnd_cnt
;
1984 unsigned int next_reg
= 0;
1985 char *old_input_line_pointer
;
1987 if (insn
->insn_type
== ITYPE_LITERAL
)
1988 opcode_operand_count
= 1;
1990 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
1993 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
1995 /* Save and restore input_line_pointer around this function. */
1996 old_input_line_pointer
= input_line_pointer
;
2002 /* Skip invisible operands. */
2003 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
2009 for (n
= 0; n
< num_args
; n
++)
2011 input_line_pointer
= arg_strings
[n
];
2012 if (*input_line_pointer
== ':')
2014 xtensa_regfile opnd_rf
;
2015 input_line_pointer
++;
2018 gas_assert (opnd_cnt
> 0);
2020 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
2022 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
2023 as_warn (_("incorrect register number, ignoring"));
2028 if (opnd_cnt
>= opcode_operand_count
)
2030 as_warn (_("too many arguments"));
2033 gas_assert (opnd_cnt
< MAX_INSN_ARGS
);
2035 expression_maybe_register (opcode
, opnd_cnt
, tok
);
2036 next_reg
= tok
->X_add_number
+ 1;
2038 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
2040 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
2042 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
2043 /* minus 1 because we are seeing one right now */
2049 last_opnd_cnt
= opnd_cnt
;
2050 demand_empty_rest_of_line ();
2057 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
2061 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
2064 insn
->ntok
= tok
- insn
->tok
;
2068 input_line_pointer
= old_input_line_pointer
;
2074 get_invisible_operands (TInsn
*insn
)
2076 xtensa_isa isa
= xtensa_default_isa
;
2077 static xtensa_insnbuf slotbuf
= NULL
;
2079 xtensa_opcode opc
= insn
->opcode
;
2080 int slot
, opnd
, fmt_found
;
2084 slotbuf
= xtensa_insnbuf_alloc (isa
);
2086 /* Find format/slot where this can be encoded. */
2089 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2091 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2093 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2099 if (fmt_found
) break;
2104 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2108 /* First encode all the visible operands
2109 (to deal with shared field operands). */
2110 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2112 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2113 && (insn
->tok
[opnd
].X_op
== O_register
2114 || insn
->tok
[opnd
].X_op
== O_constant
))
2116 val
= insn
->tok
[opnd
].X_add_number
;
2117 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2118 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2122 /* Then pull out the values for the invisible ones. */
2123 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2125 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2127 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2128 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2129 insn
->tok
[opnd
].X_add_number
= val
;
2130 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2131 insn
->tok
[opnd
].X_op
= O_register
;
2133 insn
->tok
[opnd
].X_op
= O_constant
;
2142 xg_reverse_shift_count (char **cnt_argp
)
2144 char *cnt_arg
, *new_arg
;
2145 cnt_arg
= *cnt_argp
;
2147 /* replace the argument with "31-(argument)" */
2148 new_arg
= (char *) xmalloc (strlen (cnt_arg
) + 6);
2149 sprintf (new_arg
, "31-(%s)", cnt_arg
);
2152 *cnt_argp
= new_arg
;
2156 /* If "arg" is a constant expression, return non-zero with the value
2160 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2163 char *save_ptr
= input_line_pointer
;
2165 input_line_pointer
= arg
;
2167 input_line_pointer
= save_ptr
;
2169 if (exp
.X_op
== O_constant
)
2171 *valp
= exp
.X_add_number
;
2180 xg_replace_opname (char **popname
, char *newop
)
2183 *popname
= (char *) xmalloc (strlen (newop
) + 1);
2184 strcpy (*popname
, newop
);
2189 xg_check_num_args (int *pnum_args
,
2194 int num_args
= *pnum_args
;
2196 if (num_args
< expected_num
)
2198 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2199 num_args
, opname
, expected_num
);
2203 if (num_args
> expected_num
)
2205 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2206 num_args
, opname
, expected_num
);
2207 while (num_args
-- > expected_num
)
2209 free (arg_strings
[num_args
]);
2210 arg_strings
[num_args
] = 0;
2212 *pnum_args
= expected_num
;
2220 /* If the register is not specified as part of the opcode,
2221 then get it from the operand and move it to the opcode. */
2224 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2226 xtensa_isa isa
= xtensa_default_isa
;
2228 char *opname
, *new_opname
;
2229 const char *sr_name
;
2230 int is_user
, is_write
;
2235 is_user
= (opname
[1] == 'u');
2236 is_write
= (opname
[0] == 'w');
2238 /* Opname == [rw]ur or [rwx]sr... */
2240 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2243 /* Check if the argument is a symbolic register name. */
2244 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2245 /* Handle WSR to "INTSET" as a special case. */
2246 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2247 && !strcasecmp (arg_strings
[1], "intset"))
2248 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2249 if (sr
== XTENSA_UNDEFINED
2250 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2252 /* Maybe it's a register number.... */
2254 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2256 as_bad (_("invalid register '%s' for '%s' instruction"),
2257 arg_strings
[1], opname
);
2260 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2261 if (sr
== XTENSA_UNDEFINED
)
2263 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2264 (long) val
, opname
);
2269 /* Remove the last argument, which is now part of the opcode. */
2270 free (arg_strings
[1]);
2274 /* Translate the opcode. */
2275 sr_name
= xtensa_sysreg_name (isa
, sr
);
2276 /* Another special case for "WSR.INTSET".... */
2277 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2279 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2280 sprintf (new_opname
, "%s.%s", *popname
, sr_name
);
2282 *popname
= new_opname
;
2289 xtensa_translate_old_userreg_ops (char **popname
)
2291 xtensa_isa isa
= xtensa_default_isa
;
2293 char *opname
, *new_opname
;
2294 const char *sr_name
;
2295 bfd_boolean has_underbar
= FALSE
;
2298 if (opname
[0] == '_')
2300 has_underbar
= TRUE
;
2304 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2305 if (sr
!= XTENSA_UNDEFINED
)
2307 /* The new default name ("nnn") is different from the old default
2308 name ("URnnn"). The old default is handled below, and we don't
2309 want to recognize [RW]nnn, so do nothing if the name is the (new)
2311 static char namebuf
[10];
2312 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2313 if (strcmp (namebuf
, opname
+ 1) == 0)
2321 /* Only continue if the reg name is "URnnn". */
2322 if (opname
[1] != 'u' || opname
[2] != 'r')
2324 val
= strtoul (opname
+ 3, &end
, 10);
2328 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2329 if (sr
== XTENSA_UNDEFINED
)
2331 as_bad (_("invalid register number (%ld) for '%s'"),
2332 (long) val
, opname
);
2337 /* Translate the opcode. */
2338 sr_name
= xtensa_sysreg_name (isa
, sr
);
2339 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2340 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2341 opname
[0], sr_name
);
2343 *popname
= new_opname
;
2350 xtensa_translate_zero_immed (char *old_op
,
2360 gas_assert (opname
[0] != '_');
2362 if (strcmp (opname
, old_op
) != 0)
2365 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2367 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2369 xg_replace_opname (popname
, new_op
);
2370 free (arg_strings
[1]);
2371 arg_strings
[1] = arg_strings
[2];
2380 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2381 Returns non-zero if an error was found. */
2384 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2386 char *opname
= *popname
;
2387 bfd_boolean has_underbar
= FALSE
;
2391 has_underbar
= TRUE
;
2395 if (strcmp (opname
, "mov") == 0)
2397 if (use_transform () && !has_underbar
&& density_supported
)
2398 xg_replace_opname (popname
, "mov.n");
2401 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2403 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2404 arg_strings
[2] = (char *) xmalloc (strlen (arg_strings
[1]) + 1);
2405 strcpy (arg_strings
[2], arg_strings
[1]);
2411 if (strcmp (opname
, "bbsi.l") == 0)
2413 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2415 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2416 if (target_big_endian
)
2417 xg_reverse_shift_count (&arg_strings
[1]);
2421 if (strcmp (opname
, "bbci.l") == 0)
2423 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2425 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2426 if (target_big_endian
)
2427 xg_reverse_shift_count (&arg_strings
[1]);
2431 /* Don't do anything special with NOPs inside FLIX instructions. They
2432 are handled elsewhere. Real NOP instructions are always available
2433 in configurations with FLIX, so this should never be an issue but
2434 check for it anyway. */
2435 if (!cur_vinsn
.inside_bundle
&& xtensa_nop_opcode
== XTENSA_UNDEFINED
2436 && strcmp (opname
, "nop") == 0)
2438 if (use_transform () && !has_underbar
&& density_supported
)
2439 xg_replace_opname (popname
, "nop.n");
2442 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2444 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2445 arg_strings
[0] = (char *) xmalloc (3);
2446 arg_strings
[1] = (char *) xmalloc (3);
2447 arg_strings
[2] = (char *) xmalloc (3);
2448 strcpy (arg_strings
[0], "a1");
2449 strcpy (arg_strings
[1], "a1");
2450 strcpy (arg_strings
[2], "a1");
2456 /* Recognize [RW]UR and [RWX]SR. */
2457 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2458 && (opname
[1] == 'u' || opname
[1] == 's'))
2459 || (opname
[0] == 'x' && opname
[1] == 's'))
2461 && opname
[3] == '\0')
2462 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2464 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2465 [RW]<name> if <name> is the non-default name of a user register. */
2466 if ((opname
[0] == 'r' || opname
[0] == 'w')
2467 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2468 return xtensa_translate_old_userreg_ops (popname
);
2470 /* Relax branches that don't allow comparisons against an immediate value
2471 of zero to the corresponding branches with implicit zero immediates. */
2472 if (!has_underbar
&& use_transform ())
2474 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2475 pnum_args
, arg_strings
))
2478 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2479 pnum_args
, arg_strings
))
2482 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2483 pnum_args
, arg_strings
))
2486 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2487 pnum_args
, arg_strings
))
2495 /* Functions for dealing with the Xtensa ISA. */
2497 /* Currently the assembler only allows us to use a single target per
2498 fragment. Because of this, only one operand for a given
2499 instruction may be symbolic. If there is a PC-relative operand,
2500 the last one is chosen. Otherwise, the result is the number of the
2501 last immediate operand, and if there are none of those, we fail and
2505 get_relaxable_immed (xtensa_opcode opcode
)
2507 int last_immed
= -1;
2510 if (opcode
== XTENSA_UNDEFINED
)
2513 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2514 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2516 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2518 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2520 if (last_immed
== -1
2521 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2528 static xtensa_opcode
2529 get_opcode_from_buf (const char *buf
, int slot
)
2531 static xtensa_insnbuf insnbuf
= NULL
;
2532 static xtensa_insnbuf slotbuf
= NULL
;
2533 xtensa_isa isa
= xtensa_default_isa
;
2538 insnbuf
= xtensa_insnbuf_alloc (isa
);
2539 slotbuf
= xtensa_insnbuf_alloc (isa
);
2542 xtensa_insnbuf_from_chars (isa
, insnbuf
, (const unsigned char *) buf
, 0);
2543 fmt
= xtensa_format_decode (isa
, insnbuf
);
2544 if (fmt
== XTENSA_UNDEFINED
)
2545 return XTENSA_UNDEFINED
;
2547 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2548 return XTENSA_UNDEFINED
;
2550 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2551 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2555 #ifdef TENSILICA_DEBUG
2557 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2560 xtensa_print_insn_table (void)
2562 int num_opcodes
, num_operands
;
2563 xtensa_opcode opcode
;
2564 xtensa_isa isa
= xtensa_default_isa
;
2566 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2567 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2570 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2571 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2572 for (opn
= 0; opn
< num_operands
; opn
++)
2574 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2576 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2578 xtensa_regfile opnd_rf
=
2579 xtensa_operand_regfile (isa
, opcode
, opn
);
2580 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2582 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2583 fputs ("[lLr] ", stderr
);
2585 fputs ("i ", stderr
);
2587 fprintf (stderr
, "\n");
2593 print_vliw_insn (xtensa_insnbuf vbuf
)
2595 xtensa_isa isa
= xtensa_default_isa
;
2596 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2597 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2600 fprintf (stderr
, "format = %d\n", f
);
2602 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2604 xtensa_opcode opcode
;
2608 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2609 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2610 opname
= xtensa_opcode_name (isa
, opcode
);
2612 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2613 fprintf (stderr
, " operands = ");
2615 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2619 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2621 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2622 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2623 fprintf (stderr
, "%d ", val
);
2625 fprintf (stderr
, "\n");
2627 xtensa_insnbuf_free (isa
, sbuf
);
2630 #endif /* TENSILICA_DEBUG */
2634 is_direct_call_opcode (xtensa_opcode opcode
)
2636 xtensa_isa isa
= xtensa_default_isa
;
2637 int n
, num_operands
;
2639 if (xtensa_opcode_is_call (isa
, opcode
) != 1)
2642 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2643 for (n
= 0; n
< num_operands
; n
++)
2645 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2646 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2653 /* Convert from BFD relocation type code to slot and operand number.
2654 Returns non-zero on failure. */
2657 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2659 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2660 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2662 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2665 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2666 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2668 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2678 /* Convert from slot number to BFD relocation type code for the
2679 standard PC-relative relocations. Return BFD_RELOC_NONE on
2682 static bfd_reloc_code_real_type
2683 encode_reloc (int slot
)
2685 if (slot
< 0 || slot
> 14)
2686 return BFD_RELOC_NONE
;
2688 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2692 /* Convert from slot numbers to BFD relocation type code for the
2693 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2695 static bfd_reloc_code_real_type
2696 encode_alt_reloc (int slot
)
2698 if (slot
< 0 || slot
> 14)
2699 return BFD_RELOC_NONE
;
2701 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2706 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2709 xtensa_opcode opcode
,
2715 uint32 valbuf
= value
;
2717 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2719 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2721 as_bad_where ((char *) file
, line
,
2722 _("operand %d of '%s' has out of range value '%u'"),
2724 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2727 as_bad_where ((char *) file
, line
,
2728 _("operand %d of '%s' has invalid value '%u'"),
2730 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2735 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2741 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2744 xtensa_opcode opcode
,
2748 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2749 fmt
, slot
, slotbuf
, &val
);
2750 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2755 /* Checks for rules from xtensa-relax tables. */
2757 /* The routine xg_instruction_matches_option_term must return TRUE
2758 when a given option term is true. The meaning of all of the option
2759 terms is given interpretation by this function. */
2762 xg_instruction_matches_option_term (TInsn
*insn
, const ReqOrOption
*option
)
2764 if (strcmp (option
->option_name
, "realnop") == 0
2765 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2767 /* These conditions were evaluated statically when building the
2768 relaxation table. There's no need to reevaluate them now. */
2771 else if (strcmp (option
->option_name
, "FREEREG") == 0)
2772 return insn
->extra_arg
.X_op
== O_register
;
2775 as_fatal (_("internal error: unknown option name '%s'"),
2776 option
->option_name
);
2782 xg_instruction_matches_or_options (TInsn
*insn
,
2783 const ReqOrOptionList
*or_option
)
2785 const ReqOrOption
*option
;
2786 /* Must match each of the AND terms. */
2787 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2789 if (xg_instruction_matches_option_term (insn
, option
))
2797 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2799 const ReqOption
*req_options
;
2800 /* Must match each of the AND terms. */
2801 for (req_options
= options
;
2802 req_options
!= NULL
;
2803 req_options
= req_options
->next
)
2805 /* Must match one of the OR clauses. */
2806 if (!xg_instruction_matches_or_options (insn
,
2807 req_options
->or_option_terms
))
2814 /* Return the transition rule that matches or NULL if none matches. */
2817 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2819 PreconditionList
*condition_l
;
2821 if (rule
->opcode
!= insn
->opcode
)
2824 for (condition_l
= rule
->conditions
;
2825 condition_l
!= NULL
;
2826 condition_l
= condition_l
->next
)
2830 Precondition
*cond
= condition_l
->precond
;
2835 /* The expression must be the constant. */
2836 gas_assert (cond
->op_num
< insn
->ntok
);
2837 exp1
= &insn
->tok
[cond
->op_num
];
2838 if (expr_is_const (exp1
))
2843 if (get_expr_const (exp1
) != cond
->op_data
)
2847 if (get_expr_const (exp1
) == cond
->op_data
)
2854 else if (expr_is_register (exp1
))
2859 if (get_expr_register (exp1
) != cond
->op_data
)
2863 if (get_expr_register (exp1
) == cond
->op_data
)
2875 gas_assert (cond
->op_num
< insn
->ntok
);
2876 gas_assert (cond
->op_data
< insn
->ntok
);
2877 exp1
= &insn
->tok
[cond
->op_num
];
2878 exp2
= &insn
->tok
[cond
->op_data
];
2883 if (!expr_is_equal (exp1
, exp2
))
2887 if (expr_is_equal (exp1
, exp2
))
2899 if (!xg_instruction_matches_options (insn
, rule
->options
))
2907 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
2909 bfd_boolean a_greater
= FALSE
;
2910 bfd_boolean b_greater
= FALSE
;
2912 ReqOptionList
*l_a
= a
->options
;
2913 ReqOptionList
*l_b
= b
->options
;
2915 /* We only care if they both are the same except for
2916 a const16 vs. an l32r. */
2918 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2920 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
2921 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
2922 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2924 if (l_or_a
->is_true
!= l_or_b
->is_true
)
2926 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
2928 /* This is the case we care about. */
2929 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
2930 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
2937 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
2938 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
2948 l_or_a
= l_or_a
->next
;
2949 l_or_b
= l_or_b
->next
;
2951 if (l_or_a
|| l_or_b
)
2960 /* Incomparable if the substitution was used differently in two cases. */
2961 if (a_greater
&& b_greater
)
2973 static TransitionRule
*
2974 xg_instruction_match (TInsn
*insn
)
2976 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
2978 gas_assert (insn
->opcode
< table
->num_opcodes
);
2980 /* Walk through all of the possible transitions. */
2981 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2983 TransitionRule
*rule
= l
->rule
;
2984 if (xg_instruction_matches_rule (insn
, rule
))
2991 /* Various Other Internal Functions. */
2994 is_unique_insn_expansion (TransitionRule
*r
)
2996 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
2998 if (r
->to_instr
->typ
!= INSTR_INSTR
)
3004 /* Check if there is exactly one relaxation for INSN that converts it to
3005 another instruction of equal or larger size. If so, and if TARG is
3006 non-null, go ahead and generate the relaxed instruction into TARG. If
3007 NARROW_ONLY is true, then only consider relaxations that widen a narrow
3008 instruction, i.e., ignore relaxations that convert to an instruction of
3009 equal size. In some contexts where this function is used, only
3010 a single widening is allowed and the NARROW_ONLY argument is used to
3011 exclude cases like ADDI being "widened" to an ADDMI, which may
3012 later be relaxed to an ADDMI/ADDI pair. */
3015 xg_is_single_relaxable_insn (TInsn
*insn
, TInsn
*targ
, bfd_boolean narrow_only
)
3017 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3019 TransitionRule
*match
= 0;
3021 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3022 gas_assert (insn
->opcode
< table
->num_opcodes
);
3024 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3026 TransitionRule
*rule
= l
->rule
;
3028 if (xg_instruction_matches_rule (insn
, rule
)
3029 && is_unique_insn_expansion (rule
)
3030 && (xg_get_single_size (insn
->opcode
) + (narrow_only
? 1 : 0)
3031 <= xg_get_single_size (rule
->to_instr
->opcode
)))
3042 xg_build_to_insn (targ
, insn
, match
->to_instr
);
3047 /* Return the maximum number of bytes this opcode can expand to. */
3050 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
3052 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3054 int max_size
= xg_get_single_size (opcode
);
3056 gas_assert (opcode
< table
->num_opcodes
);
3058 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3060 TransitionRule
*rule
= l
->rule
;
3061 BuildInstr
*build_list
;
3066 build_list
= rule
->to_instr
;
3067 if (is_unique_insn_expansion (rule
))
3069 gas_assert (build_list
->typ
== INSTR_INSTR
);
3070 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
3073 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3075 switch (build_list
->typ
)
3078 this_size
+= xg_get_single_size (build_list
->opcode
);
3080 case INSTR_LITERAL_DEF
:
3081 case INSTR_LABEL_DEF
:
3086 if (this_size
> max_size
)
3087 max_size
= this_size
;
3093 /* Return the maximum number of literal bytes this opcode can generate. */
3096 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3098 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3102 gas_assert (opcode
< table
->num_opcodes
);
3104 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3106 TransitionRule
*rule
= l
->rule
;
3107 BuildInstr
*build_list
;
3112 build_list
= rule
->to_instr
;
3113 if (is_unique_insn_expansion (rule
))
3115 gas_assert (build_list
->typ
== INSTR_INSTR
);
3116 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3119 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3121 switch (build_list
->typ
)
3123 case INSTR_LITERAL_DEF
:
3124 /* Hard-coded 4-byte literal. */
3128 case INSTR_LABEL_DEF
:
3133 if (this_size
> max_size
)
3134 max_size
= this_size
;
3141 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3143 int steps_taken
= 0;
3144 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3147 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3148 gas_assert (insn
->opcode
< table
->num_opcodes
);
3150 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3152 TransitionRule
*rule
= l
->rule
;
3154 if (xg_instruction_matches_rule (insn
, rule
))
3156 if (steps_taken
== lateral_steps
)
3166 get_special_literal_symbol (void)
3168 static symbolS
*sym
= NULL
;
3171 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3177 get_special_label_symbol (void)
3179 static symbolS
*sym
= NULL
;
3182 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3188 xg_valid_literal_expression (const expressionS
*exp
)
3210 /* This will check to see if the value can be converted into the
3211 operand type. It will return TRUE if it does not fit. */
3214 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3216 uint32 valbuf
= value
;
3217 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3223 /* Assumes: All immeds are constants. Check that all constants fit
3224 into their immeds; return FALSE if not. */
3227 xg_immeds_fit (const TInsn
*insn
)
3229 xtensa_isa isa
= xtensa_default_isa
;
3233 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3234 for (i
= 0; i
< n
; ++i
)
3236 const expressionS
*expr
= &insn
->tok
[i
];
3237 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3244 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3249 /* The symbol should have a fixup associated with it. */
3258 /* This should only be called after we have an initial
3259 estimate of the addresses. */
3262 xg_symbolic_immeds_fit (const TInsn
*insn
,
3268 xtensa_isa isa
= xtensa_default_isa
;
3276 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3278 for (i
= 0; i
< n
; ++i
)
3280 const expressionS
*expr
= &insn
->tok
[i
];
3281 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3288 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3294 /* Check for the worst case. */
3295 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3300 /* We only allow symbols for PC-relative references.
3301 If pc_frag == 0, then we don't have frag locations yet. */
3303 || xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0)
3306 /* If it is a weak symbol or a symbol in a different section,
3307 it cannot be known to fit at assembly time. */
3308 if (S_IS_WEAK (expr
->X_add_symbol
)
3309 || S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3311 /* For a direct call with --no-longcalls, be optimistic and
3312 assume it will be in range. If the symbol is weak and
3313 undefined, it may remain undefined at link-time, in which
3314 case it will have a zero value and almost certainly be out
3315 of range for a direct call; thus, relax for undefined weak
3316 symbols even if longcalls is not enabled. */
3317 if (is_direct_call_opcode (insn
->opcode
)
3318 && ! pc_frag
->tc_frag_data
.use_longcalls
3319 && (! S_IS_WEAK (expr
->X_add_symbol
)
3320 || S_IS_DEFINED (expr
->X_add_symbol
)))
3326 symbolP
= expr
->X_add_symbol
;
3327 sym_frag
= symbol_get_frag (symbolP
);
3328 target
= S_GET_VALUE (symbolP
) + expr
->X_add_number
;
3329 pc
= pc_frag
->fr_address
+ pc_offset
;
3331 /* If frag has yet to be reached on this pass, assume it
3332 will move by STRETCH just as we did. If this is not so,
3333 it will be because some frag between grows, and that will
3334 force another pass. Beware zero-length frags. There
3335 should be a faster way to do this. */
3338 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3339 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3344 new_offset
= target
;
3345 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3346 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3351 /* The symbol should have a fixup associated with it. */
3360 /* Return TRUE on success. */
3363 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3369 targ
->debug_line
= insn
->debug_line
;
3370 targ
->loc_directive_seen
= insn
->loc_directive_seen
;
3375 targ
->opcode
= bi
->opcode
;
3376 targ
->insn_type
= ITYPE_INSN
;
3377 targ
->is_specific_opcode
= FALSE
;
3379 for (; op
!= NULL
; op
= op
->next
)
3381 int op_num
= op
->op_num
;
3382 int op_data
= op
->op_data
;
3384 gas_assert (op
->op_num
< MAX_INSN_ARGS
);
3386 if (targ
->ntok
<= op_num
)
3387 targ
->ntok
= op_num
+ 1;
3392 set_expr_const (&targ
->tok
[op_num
], op_data
);
3395 gas_assert (op_data
< insn
->ntok
);
3396 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3399 if (insn
->extra_arg
.X_op
!= O_register
)
3401 copy_expr (&targ
->tok
[op_num
], &insn
->extra_arg
);
3404 sym
= get_special_literal_symbol ();
3405 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3406 if (insn
->tok
[op_data
].X_op
== O_tlsfunc
3407 || insn
->tok
[op_data
].X_op
== O_tlsarg
)
3408 copy_expr (&targ
->extra_arg
, &insn
->tok
[op_data
]);
3411 sym
= get_special_label_symbol ();
3412 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3414 case OP_OPERAND_HI16U
:
3415 case OP_OPERAND_LOW16U
:
3416 gas_assert (op_data
< insn
->ntok
);
3417 if (expr_is_const (&insn
->tok
[op_data
]))
3420 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3421 val
= xg_apply_userdef_op_fn (op
->typ
,
3424 targ
->tok
[op_num
].X_add_number
= val
;
3428 /* For const16 we can create relocations for these. */
3429 if (targ
->opcode
== XTENSA_UNDEFINED
3430 || (targ
->opcode
!= xtensa_const16_opcode
))
3432 gas_assert (op_data
< insn
->ntok
);
3433 /* Need to build a O_lo16 or O_hi16. */
3434 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3435 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3437 if (op
->typ
== OP_OPERAND_HI16U
)
3438 targ
->tok
[op_num
].X_op
= O_hi16
;
3439 else if (op
->typ
== OP_OPERAND_LOW16U
)
3440 targ
->tok
[op_num
].X_op
= O_lo16
;
3447 /* currently handles:
3450 OP_OPERAND_F32MINUS */
3451 if (xg_has_userdef_op_fn (op
->typ
))
3453 gas_assert (op_data
< insn
->ntok
);
3454 if (expr_is_const (&insn
->tok
[op_data
]))
3457 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3458 val
= xg_apply_userdef_op_fn (op
->typ
,
3461 targ
->tok
[op_num
].X_add_number
= val
;
3464 return FALSE
; /* We cannot use a relocation for this. */
3473 case INSTR_LITERAL_DEF
:
3475 targ
->opcode
= XTENSA_UNDEFINED
;
3476 targ
->insn_type
= ITYPE_LITERAL
;
3477 targ
->is_specific_opcode
= FALSE
;
3478 for (; op
!= NULL
; op
= op
->next
)
3480 int op_num
= op
->op_num
;
3481 int op_data
= op
->op_data
;
3482 gas_assert (op
->op_num
< MAX_INSN_ARGS
);
3484 if (targ
->ntok
<= op_num
)
3485 targ
->ntok
= op_num
+ 1;
3490 gas_assert (op_data
< insn
->ntok
);
3491 /* We can only pass resolvable literals through. */
3492 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3494 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3506 case INSTR_LABEL_DEF
:
3508 targ
->opcode
= XTENSA_UNDEFINED
;
3509 targ
->insn_type
= ITYPE_LABEL
;
3510 targ
->is_specific_opcode
= FALSE
;
3511 /* Literal with no ops is a label? */
3512 gas_assert (op
== NULL
);
3523 /* Return TRUE on success. */
3526 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3528 for (; bi
!= NULL
; bi
= bi
->next
)
3530 TInsn
*next_insn
= istack_push_space (istack
);
3532 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3539 /* Return TRUE on valid expansion. */
3542 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3544 int stack_size
= istack
->ninsn
;
3545 int steps_taken
= 0;
3546 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3549 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3550 gas_assert (insn
->opcode
< table
->num_opcodes
);
3552 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3554 TransitionRule
*rule
= l
->rule
;
3556 if (xg_instruction_matches_rule (insn
, rule
))
3558 if (lateral_steps
== steps_taken
)
3562 /* This is it. Expand the rule to the stack. */
3563 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3566 /* Check to see if it fits. */
3567 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3569 TInsn
*insn
= &istack
->insn
[i
];
3571 if (insn
->insn_type
== ITYPE_INSN
3572 && !tinsn_has_symbolic_operands (insn
)
3573 && !xg_immeds_fit (insn
))
3575 istack
->ninsn
= stack_size
;
3588 /* Relax the assembly instruction at least "min_steps".
3589 Return the number of steps taken.
3591 For relaxation to correctly terminate, every relaxation chain must
3592 terminate in one of two ways:
3594 1. If the chain from one instruction to the next consists entirely of
3595 single instructions, then the chain *must* handle all possible
3596 immediates without failing. It must not ever fail because an
3597 immediate is out of range. The MOVI.N -> MOVI -> L32R relaxation
3598 chain is one example. L32R loads 32 bits, and there cannot be an
3599 immediate larger than 32 bits, so it satisfies this condition.
3600 Single instruction relaxation chains are as defined by
3601 xg_is_single_relaxable_instruction.
3603 2. Otherwise, the chain must end in a multi-instruction expansion: e.g.,
3604 BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J
3606 Strictly speaking, in most cases you can violate condition 1 and be OK
3607 -- in particular when the last two instructions have the same single
3608 size. But nevertheless, you should guarantee the above two conditions.
3610 We could fix this so that single-instruction expansions correctly
3611 terminate when they can't handle the range, but the error messages are
3612 worse, and it actually turns out that in every case but one (18-bit wide
3613 branches), you need a multi-instruction expansion to get the full range
3614 anyway. And because 18-bit branches are handled identically to 15-bit
3615 branches, there isn't any point in changing it. */
3618 xg_assembly_relax (IStack
*istack
,
3621 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3622 offsetT pc_offset
, /* offset in fragment */
3623 int min_steps
, /* minimum conversion steps */
3624 long stretch
) /* number of bytes stretched so far */
3626 int steps_taken
= 0;
3628 /* Some of its immeds don't fit. Try to build a relaxed version.
3629 This may go through a couple of stages of single instruction
3630 transformations before we get there. */
3632 TInsn single_target
;
3634 int lateral_steps
= 0;
3635 int istack_size
= istack
->ninsn
;
3637 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3638 && steps_taken
>= min_steps
)
3640 istack_push (istack
, insn
);
3643 current_insn
= *insn
;
3645 /* Walk through all of the single instruction expansions. */
3646 while (xg_is_single_relaxable_insn (¤t_insn
, &single_target
, FALSE
))
3649 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3652 if (steps_taken
>= min_steps
)
3654 istack_push (istack
, &single_target
);
3658 current_insn
= single_target
;
3661 /* Now check for a multi-instruction expansion. */
3662 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3664 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3667 if (steps_taken
>= min_steps
)
3669 istack_push (istack
, ¤t_insn
);
3674 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3676 if (steps_taken
>= min_steps
)
3680 istack
->ninsn
= istack_size
;
3683 /* It's not going to work -- use the original. */
3684 istack_push (istack
, insn
);
3690 xg_finish_frag (char *last_insn
,
3691 enum xtensa_relax_statesE frag_state
,
3692 enum xtensa_relax_statesE slot0_state
,
3694 bfd_boolean is_insn
)
3696 /* Finish off this fragment so that it has at LEAST the desired
3697 max_growth. If it doesn't fit in this fragment, close this one
3698 and start a new one. In either case, return a pointer to the
3699 beginning of the growth area. */
3703 frag_grow (max_growth
);
3704 old_frag
= frag_now
;
3706 frag_now
->fr_opcode
= last_insn
;
3708 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3710 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3711 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3713 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3714 xtensa_set_frag_assembly_state (frag_now
);
3716 /* Just to make sure that we did not split it up. */
3717 gas_assert (old_frag
->fr_next
== frag_now
);
3721 /* Return TRUE if the target frag is one of the next non-empty frags. */
3724 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3729 for (; fragP
; fragP
= fragP
->fr_next
)
3731 if (fragP
== target
)
3733 if (fragP
->fr_fix
!= 0)
3735 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3737 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3738 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3740 if (fragP
->fr_type
== rs_space
)
3748 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3750 xtensa_isa isa
= xtensa_default_isa
;
3752 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3757 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) != 1
3758 && xtensa_opcode_is_jump (isa
, insn
->opcode
) != 1)
3761 for (i
= 0; i
< num_ops
; i
++)
3763 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3769 if (target_op
== -1)
3772 if (insn
->ntok
<= target_op
)
3775 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3778 sym
= insn
->tok
[target_op
].X_add_symbol
;
3782 if (insn
->tok
[target_op
].X_add_number
!= 0)
3785 target_frag
= symbol_get_frag (sym
);
3786 if (target_frag
== NULL
)
3789 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3790 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3798 xg_add_branch_and_loop_targets (TInsn
*insn
)
3800 xtensa_isa isa
= xtensa_default_isa
;
3801 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3803 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3806 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3807 && insn
->tok
[i
].X_op
== O_symbol
)
3808 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3812 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3813 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3817 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3819 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3820 && insn
->tok
[i
].X_op
== O_symbol
)
3822 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3823 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3824 if (S_IS_DEFINED (sym
))
3825 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3832 /* Return FALSE if no error. */
3835 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3840 switch (instr_spec
->typ
)
3843 new_insn
->insn_type
= ITYPE_INSN
;
3844 new_insn
->opcode
= instr_spec
->opcode
;
3846 case INSTR_LITERAL_DEF
:
3847 new_insn
->insn_type
= ITYPE_LITERAL
;
3848 new_insn
->opcode
= XTENSA_UNDEFINED
;
3850 case INSTR_LABEL_DEF
:
3853 new_insn
->is_specific_opcode
= FALSE
;
3854 new_insn
->debug_line
= old_insn
->debug_line
;
3855 new_insn
->loc_directive_seen
= old_insn
->loc_directive_seen
;
3857 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3860 const expressionS
*src_exp
;
3866 /* The expression must be the constant. */
3867 gas_assert (b_op
->op_num
< MAX_INSN_ARGS
);
3868 exp
= &new_insn
->tok
[b_op
->op_num
];
3869 set_expr_const (exp
, b_op
->op_data
);
3873 gas_assert (b_op
->op_num
< MAX_INSN_ARGS
);
3874 gas_assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
3875 src_exp
= &old_insn
->tok
[b_op
->op_data
];
3876 exp
= &new_insn
->tok
[b_op
->op_num
];
3877 copy_expr (exp
, src_exp
);
3882 as_bad (_("can't handle generation of literal/labels yet"));
3886 as_bad (_("can't handle undefined OP TYPE"));
3891 new_insn
->ntok
= num_ops
;
3896 /* Return TRUE if it was simplified. */
3899 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
3901 TransitionRule
*rule
;
3902 BuildInstr
*insn_spec
;
3904 if (old_insn
->is_specific_opcode
|| !density_supported
)
3907 rule
= xg_instruction_match (old_insn
);
3911 insn_spec
= rule
->to_instr
;
3912 /* There should only be one. */
3913 gas_assert (insn_spec
!= NULL
);
3914 gas_assert (insn_spec
->next
== NULL
);
3915 if (insn_spec
->next
!= NULL
)
3918 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
3924 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3925 l32i.n. (2) Check the number of operands. (3) Place the instruction
3926 tokens into the stack or relax it and place multiple
3927 instructions/literals onto the stack. Return FALSE if no error. */
3930 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
3934 bfd_boolean do_expand
;
3936 tinsn_init (&new_insn
);
3938 /* Narrow it if we can. xg_simplify_insn now does all the
3939 appropriate checking (e.g., for the density option). */
3940 if (xg_simplify_insn (orig_insn
, &new_insn
))
3941 orig_insn
= &new_insn
;
3943 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
3945 if (orig_insn
->ntok
< noperands
)
3947 as_bad (_("found %d operands for '%s': Expected %d"),
3949 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3953 if (orig_insn
->ntok
> noperands
)
3954 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
3956 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3959 /* If there are not enough operands, we will assert above. If there
3960 are too many, just cut out the extras here. */
3961 orig_insn
->ntok
= noperands
;
3963 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
3966 /* Special case for extui opcode which has constraints not handled
3967 by the ordinary operand encoding checks. The number of operands
3968 and related syntax issues have already been checked. */
3969 if (orig_insn
->opcode
== xtensa_extui_opcode
)
3971 int shiftimm
= orig_insn
->tok
[2].X_add_number
;
3972 int maskimm
= orig_insn
->tok
[3].X_add_number
;
3973 if (shiftimm
+ maskimm
> 32)
3975 as_bad (_("immediate operands sum to greater than 32"));
3980 /* If the instruction will definitely need to be relaxed, it is better
3981 to expand it now for better scheduling. Decide whether to expand
3983 do_expand
= (!orig_insn
->is_specific_opcode
&& use_transform ());
3985 /* Calls should be expanded to longcalls only in the backend relaxation
3986 so that the assembly scheduler will keep the L32R/CALLX instructions
3988 if (is_direct_call_opcode (orig_insn
->opcode
))
3991 if (tinsn_has_symbolic_operands (orig_insn
))
3993 /* The values of symbolic operands are not known yet, so only expand
3994 now if an operand is "complex" (e.g., difference of symbols) and
3995 will have to be stored as a literal regardless of the value. */
3996 if (!tinsn_has_complex_operands (orig_insn
))
3999 else if (xg_immeds_fit (orig_insn
))
4003 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
4005 istack_push (istack
, orig_insn
);
4011 /* Return TRUE if the section flags are marked linkonce
4012 or the name is .gnu.linkonce.*. */
4014 static int linkonce_len
= sizeof (".gnu.linkonce.") - 1;
4017 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
4019 flagword flags
, link_once_flags
;
4021 flags
= bfd_get_section_flags (abfd
, sec
);
4022 link_once_flags
= (flags
& SEC_LINK_ONCE
);
4024 /* Flags might not be set yet. */
4025 if (!link_once_flags
4026 && strncmp (segment_name (sec
), ".gnu.linkonce.", linkonce_len
) == 0)
4027 link_once_flags
= SEC_LINK_ONCE
;
4029 return (link_once_flags
!= 0);
4034 xtensa_add_literal_sym (symbolS
*sym
)
4038 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
4040 l
->next
= literal_syms
;
4046 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
4048 static int lit_num
= 0;
4049 static char name
[256];
4052 sprintf (name
, ".L_lit_sym%d", lit_num
);
4054 /* Create a local symbol. If it is in a linkonce section, we have to
4055 be careful to make sure that if it is used in a relocation that the
4056 symbol will be in the output file. */
4057 if (get_is_linkonce_section (stdoutput
, sec
))
4059 symbolP
= symbol_new (name
, sec
, 0, frag
);
4060 S_CLEAR_EXTERNAL (symbolP
);
4061 /* symbolP->local = 1; */
4064 symbolP
= symbol_new (name
, sec
, 0, frag
);
4066 xtensa_add_literal_sym (symbolP
);
4073 /* Currently all literals that are generated here are 32-bit L32R targets. */
4076 xg_assemble_literal (/* const */ TInsn
*insn
)
4079 symbolS
*lit_sym
= NULL
;
4080 bfd_reloc_code_real_type reloc
;
4081 bfd_boolean pcrel
= FALSE
;
4084 /* size = 4 for L32R. It could easily be larger when we move to
4085 larger constants. Add a parameter later. */
4086 offsetT litsize
= 4;
4087 offsetT litalign
= 2; /* 2^2 = 4 */
4088 expressionS saved_loc
;
4089 expressionS
* emit_val
;
4091 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
4093 gas_assert (insn
->insn_type
== ITYPE_LITERAL
);
4094 gas_assert (insn
->ntok
== 1); /* must be only one token here */
4096 xtensa_switch_to_literal_fragment (&state
);
4098 emit_val
= &insn
->tok
[0];
4099 if (emit_val
->X_op
== O_big
)
4101 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
4104 /* This happens when someone writes a "movi a2, big_number". */
4105 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4106 _("invalid immediate"));
4107 xtensa_restore_emit_state (&state
);
4112 /* Force a 4-byte align here. Note that this opens a new frag, so all
4113 literals done with this function have a frag to themselves. That's
4114 important for the way text section literals work. */
4115 frag_align (litalign
, 0, 0);
4116 record_alignment (now_seg
, litalign
);
4118 switch (emit_val
->X_op
)
4128 p
= frag_more (litsize
);
4129 xtensa_set_frag_assembly_state (frag_now
);
4130 reloc
= map_operator_to_reloc (emit_val
->X_op
, TRUE
);
4131 if (emit_val
->X_add_symbol
)
4132 emit_val
->X_op
= O_symbol
;
4134 emit_val
->X_op
= O_constant
;
4135 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
4136 litsize
, emit_val
, pcrel
, reloc
);
4140 emit_expr (emit_val
, litsize
);
4144 gas_assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
4145 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4146 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4147 lit_sym
= frag_now
->fr_symbol
;
4150 xtensa_restore_emit_state (&state
);
4156 xg_assemble_literal_space (/* const */ int size
, int slot
)
4159 /* We might have to do something about this alignment. It only
4160 takes effect if something is placed here. */
4161 offsetT litalign
= 2; /* 2^2 = 4 */
4162 fragS
*lit_saved_frag
;
4164 gas_assert (size
% 4 == 0);
4166 xtensa_switch_to_literal_fragment (&state
);
4168 /* Force a 4-byte align here. */
4169 frag_align (litalign
, 0, 0);
4170 record_alignment (now_seg
, litalign
);
4174 lit_saved_frag
= frag_now
;
4175 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4176 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4177 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4180 xtensa_restore_emit_state (&state
);
4181 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4185 /* Put in a fixup record based on the opcode.
4186 Return TRUE on success. */
4189 xg_add_opcode_fix (TInsn
*tinsn
,
4197 xtensa_opcode opcode
= tinsn
->opcode
;
4198 bfd_reloc_code_real_type reloc
;
4199 reloc_howto_type
*howto
;
4203 reloc
= BFD_RELOC_NONE
;
4205 /* First try the special cases for "alternate" relocs. */
4206 if (opcode
== xtensa_l32r_opcode
)
4208 if (fragP
->tc_frag_data
.use_absolute_literals
)
4209 reloc
= encode_alt_reloc (slot
);
4211 else if (opcode
== xtensa_const16_opcode
)
4213 if (expr
->X_op
== O_lo16
)
4215 reloc
= encode_reloc (slot
);
4216 expr
->X_op
= O_symbol
;
4218 else if (expr
->X_op
== O_hi16
)
4220 reloc
= encode_alt_reloc (slot
);
4221 expr
->X_op
= O_symbol
;
4225 if (opnum
!= get_relaxable_immed (opcode
))
4227 as_bad (_("invalid relocation for operand %i of '%s'"),
4228 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4232 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4233 into the symbol table where the generic portions of the assembler
4234 won't know what to do with them. */
4235 if (expr
->X_op
== O_lo16
|| expr
->X_op
== O_hi16
)
4237 as_bad (_("invalid expression for operand %i of '%s'"),
4238 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4242 /* Next try the generic relocs. */
4243 if (reloc
== BFD_RELOC_NONE
)
4244 reloc
= encode_reloc (slot
);
4245 if (reloc
== BFD_RELOC_NONE
)
4247 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4251 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4254 as_bad (_("undefined symbol for opcode \"%s\""),
4255 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4259 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4260 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, expr
,
4261 howto
->pc_relative
, reloc
);
4262 the_fix
->fx_no_overflow
= 1;
4263 the_fix
->tc_fix_data
.X_add_symbol
= expr
->X_add_symbol
;
4264 the_fix
->tc_fix_data
.X_add_number
= expr
->X_add_number
;
4265 the_fix
->tc_fix_data
.slot
= slot
;
4272 xg_emit_insn_to_buf (TInsn
*tinsn
,
4276 bfd_boolean build_fix
)
4278 static xtensa_insnbuf insnbuf
= NULL
;
4279 bfd_boolean has_symbolic_immed
= FALSE
;
4280 bfd_boolean ok
= TRUE
;
4283 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4285 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4286 if (has_symbolic_immed
&& build_fix
)
4289 xtensa_format fmt
= xg_get_single_format (tinsn
->opcode
);
4290 int slot
= xg_get_single_slot (tinsn
->opcode
);
4291 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4292 expressionS
*exp
= &tinsn
->tok
[opnum
];
4294 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, slot
, exp
, fragP
, offset
))
4297 fragP
->tc_frag_data
.is_insn
= TRUE
;
4298 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4299 (unsigned char *) buf
, 0);
4305 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4307 symbolS
*sym
= get_special_literal_symbol ();
4311 gas_assert (insn
->insn_type
== ITYPE_INSN
);
4312 for (i
= 0; i
< insn
->ntok
; i
++)
4313 if (insn
->tok
[i
].X_add_symbol
== sym
)
4314 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4320 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4322 symbolS
*sym
= get_special_label_symbol ();
4324 for (i
= 0; i
< insn
->ntok
; i
++)
4325 if (insn
->tok
[i
].X_add_symbol
== sym
)
4326 insn
->tok
[i
].X_add_symbol
= label_sym
;
4331 /* Return TRUE if the instruction can write to the specified
4332 integer register. */
4335 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4339 xtensa_isa isa
= xtensa_default_isa
;
4341 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4343 for (i
= 0; i
< num_ops
; i
++)
4346 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4347 if ((inout
== 'o' || inout
== 'm')
4348 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4350 xtensa_regfile opnd_rf
=
4351 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4352 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4354 if ((insn
->tok
[i
].X_op
== O_register
)
4355 && (insn
->tok
[i
].X_add_number
== regnum
))
4365 is_bad_loopend_opcode (const TInsn
*tinsn
)
4367 xtensa_opcode opcode
= tinsn
->opcode
;
4369 if (opcode
== XTENSA_UNDEFINED
)
4372 if (opcode
== xtensa_call0_opcode
4373 || opcode
== xtensa_callx0_opcode
4374 || opcode
== xtensa_call4_opcode
4375 || opcode
== xtensa_callx4_opcode
4376 || opcode
== xtensa_call8_opcode
4377 || opcode
== xtensa_callx8_opcode
4378 || opcode
== xtensa_call12_opcode
4379 || opcode
== xtensa_callx12_opcode
4380 || opcode
== xtensa_isync_opcode
4381 || opcode
== xtensa_ret_opcode
4382 || opcode
== xtensa_ret_n_opcode
4383 || opcode
== xtensa_retw_opcode
4384 || opcode
== xtensa_retw_n_opcode
4385 || opcode
== xtensa_waiti_opcode
4386 || opcode
== xtensa_rsr_lcount_opcode
)
4393 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4394 This allows the debugger to add unaligned labels.
4395 Also, the assembler generates stabs labels that need
4396 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4399 is_unaligned_label (symbolS
*sym
)
4401 const char *name
= S_GET_NAME (sym
);
4402 static size_t fake_size
= 0;
4406 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4409 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4411 fake_size
= strlen (FAKE_LABEL_NAME
);
4414 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4415 && (name
[fake_size
] == 'F'
4416 || name
[fake_size
] == 'L'
4417 || (name
[fake_size
] == 'e'
4418 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4426 next_non_empty_frag (const fragS
*fragP
)
4428 fragS
*next_fragP
= fragP
->fr_next
;
4430 /* Sometimes an empty will end up here due storage allocation issues.
4431 So we have to skip until we find something legit. */
4432 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4433 next_fragP
= next_fragP
->fr_next
;
4435 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4443 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4445 xtensa_opcode out_opcode
;
4446 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4448 if (next_fragP
== NULL
)
4451 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4452 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4454 *opcode
= out_opcode
;
4462 frag_format_size (const fragS
*fragP
)
4464 static xtensa_insnbuf insnbuf
= NULL
;
4465 xtensa_isa isa
= xtensa_default_isa
;
4470 insnbuf
= xtensa_insnbuf_alloc (isa
);
4473 return XTENSA_UNDEFINED
;
4475 xtensa_insnbuf_from_chars (isa
, insnbuf
,
4476 (unsigned char *) fragP
->fr_literal
, 0);
4478 fmt
= xtensa_format_decode (isa
, insnbuf
);
4479 if (fmt
== XTENSA_UNDEFINED
)
4480 return XTENSA_UNDEFINED
;
4481 fmt_size
= xtensa_format_length (isa
, fmt
);
4483 /* If the next format won't be changing due to relaxation, just
4484 return the length of the first format. */
4485 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4488 /* If during relaxation we have to pull an instruction out of a
4489 multi-slot instruction, we will return the more conservative
4490 number. This works because alignment on bigger instructions
4491 is more restrictive than alignment on smaller instructions.
4492 This is more conservative than we would like, but it happens
4495 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4498 /* If we aren't doing one of our own relaxations or it isn't
4499 slot-based, then the insn size won't change. */
4500 if (fragP
->fr_type
!= rs_machine_dependent
)
4502 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4505 /* If an instruction is about to grow, return the longer size. */
4506 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4507 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
4508 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP3
)
4510 /* For most frags at RELAX_IMMED_STEPX, with X > 0, the first
4511 instruction in the relaxed version is of length 3. (The case
4512 where we have to pull the instruction out of a FLIX bundle
4513 is handled conservatively above.) However, frags with opcodes
4514 that are expanding to wide branches end up having formats that
4515 are not determinable by the RELAX_IMMED_STEPX enumeration, and
4516 we can't tell directly what format the relaxer picked. This
4517 is a wart in the design of the relaxer that should someday be
4518 fixed, but would require major changes, or at least should
4519 be accompanied by major changes to make use of that data.
4521 In any event, we can tell that we are expanding from a single-slot
4522 three-byte format to a wider one with the logic below. */
4524 if (fmt_size
<= 3 && fragP
->tc_frag_data
.text_expansion
[0] != 3)
4525 return 3 + fragP
->tc_frag_data
.text_expansion
[0];
4530 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4531 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4538 next_frag_format_size (const fragS
*fragP
)
4540 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4541 return frag_format_size (next_fragP
);
4545 /* In early Xtensa Processors, for reasons that are unclear, the ISA
4546 required two-byte instructions to be treated as three-byte instructions
4547 for loop instruction alignment. This restriction was removed beginning
4548 with Xtensa LX. Now the only requirement on loop instruction alignment
4549 is that the first instruction of the loop must appear at an address that
4550 does not cross a fetch boundary. */
4553 get_loop_align_size (int insn_size
)
4555 if (insn_size
== XTENSA_UNDEFINED
)
4556 return xtensa_fetch_width
;
4558 if (enforce_three_byte_loop_align
&& insn_size
== 2)
4565 /* If the next legit fragment is an end-of-loop marker,
4566 switch its state so it will instantiate a NOP. */
4569 update_next_frag_state (fragS
*fragP
)
4571 fragS
*next_fragP
= fragP
->fr_next
;
4572 fragS
*new_target
= NULL
;
4576 /* We are guaranteed there will be one of these... */
4577 while (!(next_fragP
->fr_type
== rs_machine_dependent
4578 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4579 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4580 next_fragP
= next_fragP
->fr_next
;
4582 gas_assert (next_fragP
->fr_type
== rs_machine_dependent
4583 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4584 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4586 /* ...and one of these. */
4587 new_target
= next_fragP
->fr_next
;
4588 while (!(new_target
->fr_type
== rs_machine_dependent
4589 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4590 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4591 new_target
= new_target
->fr_next
;
4593 gas_assert (new_target
->fr_type
== rs_machine_dependent
4594 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4595 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4598 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4600 if (next_fragP
->fr_type
== rs_machine_dependent
4601 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4603 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4607 next_fragP
= next_fragP
->fr_next
;
4613 next_frag_is_branch_target (const fragS
*fragP
)
4615 /* Sometimes an empty will end up here due to storage allocation issues,
4616 so we have to skip until we find something legit. */
4617 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4619 if (fragP
->tc_frag_data
.is_branch_target
)
4621 if (fragP
->fr_fix
!= 0)
4629 next_frag_is_loop_target (const fragS
*fragP
)
4631 /* Sometimes an empty will end up here due storage allocation issues.
4632 So we have to skip until we find something legit. */
4633 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4635 if (fragP
->tc_frag_data
.is_loop_target
)
4637 if (fragP
->fr_fix
!= 0)
4645 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4647 const fragS
*next_fragp
= fragp
->fr_next
;
4648 xtensa_opcode next_opcode
;
4650 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4653 /* Sometimes an empty will end up here due to storage allocation issues,
4654 so we have to skip until we find something legit. */
4655 while (next_fragp
->fr_fix
== 0)
4656 next_fragp
= next_fragp
->fr_next
;
4658 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4661 /* There is some implicit knowledge encoded in here.
4662 The LOOP instructions that are NOT RELAX_IMMED have
4663 been relaxed. Note that we can assume that the LOOP
4664 instruction is in slot 0 because loops aren't bundleable. */
4665 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4666 return get_expanded_loop_offset (next_opcode
);
4672 /* Mark a location where we can later insert literal frags. Update
4673 the section's literal_pool_loc, so subsequent literals can be
4674 placed nearest to their use. */
4677 xtensa_mark_literal_pool_location (void)
4679 /* Any labels pointing to the current location need
4680 to be adjusted to after the literal pool. */
4682 fragS
*pool_location
;
4684 if (use_literal_section
)
4687 /* We stash info in these frags so we can later move the literal's
4688 fixes into this frchain's fix list. */
4689 pool_location
= frag_now
;
4690 frag_now
->tc_frag_data
.lit_frchain
= frchain_now
;
4691 frag_now
->tc_frag_data
.literal_frag
= frag_now
;
4692 frag_variant (rs_machine_dependent
, 0, 0,
4693 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4694 xtensa_set_frag_assembly_state (frag_now
);
4695 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
4696 frag_variant (rs_machine_dependent
, 0, 0,
4697 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4698 xtensa_set_frag_assembly_state (frag_now
);
4700 /* Now put a frag into the literal pool that points to this location. */
4701 set_literal_pool_location (now_seg
, pool_location
);
4702 xtensa_switch_to_non_abs_literal_fragment (&s
);
4703 frag_align (2, 0, 0);
4704 record_alignment (now_seg
, 2);
4706 /* Close whatever frag is there. */
4707 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4708 xtensa_set_frag_assembly_state (frag_now
);
4709 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
4710 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4711 xtensa_restore_emit_state (&s
);
4712 xtensa_set_frag_assembly_state (frag_now
);
4716 /* Build a nop of the correct size into tinsn. */
4719 build_nop (TInsn
*tinsn
, int size
)
4725 tinsn
->opcode
= xtensa_nop_n_opcode
;
4727 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4728 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4732 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4734 tinsn
->opcode
= xtensa_or_opcode
;
4735 set_expr_const (&tinsn
->tok
[0], 1);
4736 set_expr_const (&tinsn
->tok
[1], 1);
4737 set_expr_const (&tinsn
->tok
[2], 1);
4741 tinsn
->opcode
= xtensa_nop_opcode
;
4743 gas_assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4748 /* Assemble a NOP of the requested size in the buffer. User must have
4749 allocated "buf" with at least "size" bytes. */
4752 assemble_nop (int size
, char *buf
)
4754 static xtensa_insnbuf insnbuf
= NULL
;
4757 build_nop (&tinsn
, size
);
4760 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4762 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4763 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4764 (unsigned char *) buf
, 0);
4768 /* Return the number of bytes for the offset of the expanded loop
4769 instruction. This should be incorporated into the relaxation
4770 specification but is hard-coded here. This is used to auto-align
4771 the loop instruction. It is invalid to call this function if the
4772 configuration does not have loops or if the opcode is not a loop
4776 get_expanded_loop_offset (xtensa_opcode opcode
)
4778 /* This is the OFFSET of the loop instruction in the expanded loop.
4779 This MUST correspond directly to the specification of the loop
4780 expansion. It will be validated on fragment conversion. */
4781 gas_assert (opcode
!= XTENSA_UNDEFINED
);
4782 if (opcode
== xtensa_loop_opcode
)
4784 if (opcode
== xtensa_loopnez_opcode
)
4786 if (opcode
== xtensa_loopgtz_opcode
)
4788 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4794 get_literal_pool_location (segT seg
)
4796 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4801 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4803 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4807 /* Set frag assembly state should be called when a new frag is
4808 opened and after a frag has been closed. */
4811 xtensa_set_frag_assembly_state (fragS
*fragP
)
4813 if (!density_supported
)
4814 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4816 /* This function is called from subsegs_finish, which is called
4817 after xtensa_end, so we can't use "use_transform" or
4818 "use_schedule" here. */
4819 if (!directive_state
[directive_transform
])
4820 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4821 if (directive_state
[directive_longcalls
])
4822 fragP
->tc_frag_data
.use_longcalls
= TRUE
;
4823 fragP
->tc_frag_data
.use_absolute_literals
=
4824 directive_state
[directive_absolute_literals
];
4825 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4830 relaxable_section (asection
*sec
)
4832 return ((sec
->flags
& SEC_DEBUGGING
) == 0
4833 && strcmp (sec
->name
, ".eh_frame") != 0);
4838 xtensa_mark_frags_for_org (void)
4842 /* Walk over each fragment of all of the current segments. If we find
4843 a .org frag in any of the segments, mark all frags prior to it as
4844 "no transform", which will prevent linker optimizations from messing
4845 up the .org distance. This should be done after
4846 xtensa_find_unmarked_state_frags, because we don't want to worry here
4847 about that function trashing the data we save here. */
4849 for (seclist
= &stdoutput
->sections
;
4850 seclist
&& *seclist
;
4851 seclist
= &(*seclist
)->next
)
4853 segT sec
= *seclist
;
4854 segment_info_type
*seginfo
;
4857 flags
= bfd_get_section_flags (stdoutput
, sec
);
4858 if (flags
& SEC_DEBUGGING
)
4860 if (!(flags
& SEC_ALLOC
))
4863 seginfo
= seg_info (sec
);
4864 if (seginfo
&& seginfo
->frchainP
)
4866 fragS
*last_fragP
= seginfo
->frchainP
->frch_root
;
4867 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4868 fragP
= fragP
->fr_next
)
4870 /* cvt_frag_to_fill has changed the fr_type of org frags to
4871 rs_fill, so use the value as cached in rs_subtype here. */
4872 if (fragP
->fr_subtype
== RELAX_ORG
)
4874 while (last_fragP
!= fragP
->fr_next
)
4876 last_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4877 last_fragP
= last_fragP
->fr_next
;
4887 xtensa_find_unmarked_state_frags (void)
4891 /* Walk over each fragment of all of the current segments. For each
4892 unmarked fragment, mark it with the same info as the previous
4894 for (seclist
= &stdoutput
->sections
;
4895 seclist
&& *seclist
;
4896 seclist
= &(*seclist
)->next
)
4898 segT sec
= *seclist
;
4899 segment_info_type
*seginfo
;
4902 flags
= bfd_get_section_flags (stdoutput
, sec
);
4903 if (flags
& SEC_DEBUGGING
)
4905 if (!(flags
& SEC_ALLOC
))
4908 seginfo
= seg_info (sec
);
4909 if (seginfo
&& seginfo
->frchainP
)
4911 fragS
*last_fragP
= 0;
4912 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4913 fragP
= fragP
->fr_next
)
4915 if (fragP
->fr_fix
!= 0
4916 && !fragP
->tc_frag_data
.is_assembly_state_set
)
4918 if (last_fragP
== 0)
4920 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
4921 _("assembly state not set for first frag in section %s"),
4926 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4927 fragP
->tc_frag_data
.is_no_density
=
4928 last_fragP
->tc_frag_data
.is_no_density
;
4929 fragP
->tc_frag_data
.is_no_transform
=
4930 last_fragP
->tc_frag_data
.is_no_transform
;
4931 fragP
->tc_frag_data
.use_longcalls
=
4932 last_fragP
->tc_frag_data
.use_longcalls
;
4933 fragP
->tc_frag_data
.use_absolute_literals
=
4934 last_fragP
->tc_frag_data
.use_absolute_literals
;
4937 if (fragP
->tc_frag_data
.is_assembly_state_set
)
4946 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
4948 void *unused ATTRIBUTE_UNUSED
)
4950 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4951 segment_info_type
*seginfo
= seg_info (sec
);
4952 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4954 if (flags
& SEC_CODE
)
4956 xtensa_isa isa
= xtensa_default_isa
;
4957 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4958 while (frag
!= NULL
)
4960 if (frag
->tc_frag_data
.is_branch_target
)
4963 addressT branch_align
, frag_addr
;
4966 xtensa_insnbuf_from_chars
4967 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4968 fmt
= xtensa_format_decode (isa
, insnbuf
);
4969 op_size
= xtensa_format_length (isa
, fmt
);
4970 branch_align
= 1 << branch_align_power (sec
);
4971 frag_addr
= frag
->fr_address
% branch_align
;
4972 if (frag_addr
+ op_size
> branch_align
)
4973 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4974 _("unaligned branch target: %d bytes at 0x%lx"),
4975 op_size
, (long) frag
->fr_address
);
4977 frag
= frag
->fr_next
;
4979 xtensa_insnbuf_free (isa
, insnbuf
);
4985 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
4987 void *unused ATTRIBUTE_UNUSED
)
4989 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4990 segment_info_type
*seginfo
= seg_info (sec
);
4991 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4992 xtensa_isa isa
= xtensa_default_isa
;
4994 if (flags
& SEC_CODE
)
4996 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4997 while (frag
!= NULL
)
4999 if (frag
->tc_frag_data
.is_first_loop_insn
)
5005 xtensa_insnbuf_from_chars
5006 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
5007 fmt
= xtensa_format_decode (isa
, insnbuf
);
5008 op_size
= xtensa_format_length (isa
, fmt
);
5009 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
5011 if (frag_addr
+ op_size
> xtensa_fetch_width
)
5012 as_warn_where (frag
->fr_file
, frag
->fr_line
,
5013 _("unaligned loop: %d bytes at 0x%lx"),
5014 op_size
, (long) frag
->fr_address
);
5016 frag
= frag
->fr_next
;
5018 xtensa_insnbuf_free (isa
, insnbuf
);
5024 xg_apply_fix_value (fixS
*fixP
, valueT val
)
5026 xtensa_isa isa
= xtensa_default_isa
;
5027 static xtensa_insnbuf insnbuf
= NULL
;
5028 static xtensa_insnbuf slotbuf
= NULL
;
5031 bfd_boolean alt_reloc
;
5032 xtensa_opcode opcode
;
5033 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5035 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
)
5037 as_fatal (_("unexpected fix"));
5041 insnbuf
= xtensa_insnbuf_alloc (isa
);
5042 slotbuf
= xtensa_insnbuf_alloc (isa
);
5045 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
5046 fmt
= xtensa_format_decode (isa
, insnbuf
);
5047 if (fmt
== XTENSA_UNDEFINED
)
5048 as_fatal (_("undecodable fix"));
5049 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5050 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5051 if (opcode
== XTENSA_UNDEFINED
)
5052 as_fatal (_("undecodable fix"));
5054 /* CONST16 immediates are not PC-relative, despite the fact that we
5055 reuse the normal PC-relative operand relocations for the low part
5056 of a CONST16 operand. */
5057 if (opcode
== xtensa_const16_opcode
)
5060 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
5061 get_relaxable_immed (opcode
), val
,
5062 fixP
->fx_file
, fixP
->fx_line
);
5064 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5065 xtensa_insnbuf_to_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
5071 /* External Functions and Other GAS Hooks. */
5074 xtensa_target_format (void)
5076 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
5081 xtensa_file_arch_init (bfd
*abfd
)
5083 bfd_set_private_flags (abfd
, 0x100 | 0x200);
5088 md_number_to_chars (char *buf
, valueT val
, int n
)
5090 if (target_big_endian
)
5091 number_to_chars_bigendian (buf
, val
, n
);
5093 number_to_chars_littleendian (buf
, val
, n
);
5097 /* This function is called once, at assembler startup time. It should
5098 set up all the tables, etc. that the MD part of the assembler will
5104 segT current_section
= now_seg
;
5105 int current_subsec
= now_subseg
;
5108 xtensa_default_isa
= xtensa_isa_init (0, 0);
5109 isa
= xtensa_default_isa
;
5113 /* Set up the literal sections. */
5114 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
5116 subseg_set (current_section
, current_subsec
);
5118 xg_init_vinsn (&cur_vinsn
);
5120 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
5121 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
5122 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
5123 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
5124 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
5125 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
5126 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
5127 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
5128 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
5129 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
5130 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
5131 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
5132 xtensa_extui_opcode
= xtensa_opcode_lookup (isa
, "extui");
5133 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
5134 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
5135 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
5136 xtensa_j_opcode
= xtensa_opcode_lookup (isa
, "j");
5137 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
5138 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
5139 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
5140 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
5141 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
5142 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
5143 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
5144 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
5145 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
5146 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
5147 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
5148 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
5149 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
5150 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
5152 xtensa_num_pipe_stages
= xtensa_isa_num_pipe_stages (isa
);
5154 init_op_placement_info_table ();
5156 /* Set up the assembly state. */
5157 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5158 xtensa_set_frag_assembly_state (frag_now
);
5162 /* TC_INIT_FIX_DATA hook */
5165 xtensa_init_fix_data (fixS
*x
)
5167 x
->tc_fix_data
.slot
= 0;
5168 x
->tc_fix_data
.X_add_symbol
= NULL
;
5169 x
->tc_fix_data
.X_add_number
= 0;
5173 /* tc_frob_label hook */
5176 xtensa_frob_label (symbolS
*sym
)
5180 if (cur_vinsn
.inside_bundle
)
5182 as_bad (_("labels are not valid inside bundles"));
5186 freq
= get_subseg_target_freq (now_seg
, now_subseg
);
5188 /* Since the label was already attached to a frag associated with the
5189 previous basic block, it now needs to be reset to the current frag. */
5190 symbol_set_frag (sym
, frag_now
);
5191 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5193 if (generating_literals
)
5194 xtensa_add_literal_sym (sym
);
5196 xtensa_add_insn_label (sym
);
5198 if (symbol_get_tc (sym
)->is_loop_target
)
5200 if ((get_last_insn_flags (now_seg
, now_subseg
)
5201 & FLAG_IS_BAD_LOOPEND
) != 0)
5202 as_bad (_("invalid last instruction for a zero-overhead loop"));
5204 xtensa_set_frag_assembly_state (frag_now
);
5205 frag_var (rs_machine_dependent
, 4, 4, RELAX_LOOP_END
,
5206 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5208 xtensa_set_frag_assembly_state (frag_now
);
5209 xtensa_move_labels (frag_now
, 0);
5212 /* No target aligning in the absolute section. */
5213 if (now_seg
!= absolute_section
5214 && !is_unaligned_label (sym
)
5215 && !generating_literals
)
5217 xtensa_set_frag_assembly_state (frag_now
);
5219 if (do_align_targets ())
5220 frag_var (rs_machine_dependent
, 0, (int) freq
,
5221 RELAX_DESIRE_ALIGN_IF_TARGET
, frag_now
->fr_symbol
,
5222 frag_now
->fr_offset
, NULL
);
5224 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
5225 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5226 xtensa_set_frag_assembly_state (frag_now
);
5227 xtensa_move_labels (frag_now
, 0);
5230 /* We need to mark the following properties even if we aren't aligning. */
5232 /* If the label is already known to be a branch target, i.e., a
5233 forward branch, mark the frag accordingly. Backward branches
5234 are handled by xg_add_branch_and_loop_targets. */
5235 if (symbol_get_tc (sym
)->is_branch_target
)
5236 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5238 /* Loops only go forward, so they can be identified here. */
5239 if (symbol_get_tc (sym
)->is_loop_target
)
5240 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5242 dwarf2_emit_label (sym
);
5246 /* tc_unrecognized_line hook */
5249 xtensa_unrecognized_line (int ch
)
5254 if (cur_vinsn
.inside_bundle
== 0)
5256 /* PR8110: Cannot emit line number info inside a FLIX bundle
5257 when using --gstabs. Temporarily disable debug info. */
5258 generate_lineno_debug ();
5259 if (debug_type
== DEBUG_STABS
)
5261 xt_saved_debug_type
= debug_type
;
5262 debug_type
= DEBUG_NONE
;
5265 cur_vinsn
.inside_bundle
= 1;
5269 as_bad (_("extra opening brace"));
5275 if (cur_vinsn
.inside_bundle
)
5276 finish_vinsn (&cur_vinsn
);
5279 as_bad (_("extra closing brace"));
5284 as_bad (_("syntax error"));
5291 /* md_flush_pending_output hook */
5294 xtensa_flush_pending_output (void)
5296 /* This line fixes a bug where automatically generated gstabs info
5297 separates a function label from its entry instruction, ending up
5298 with the literal position between the function label and the entry
5299 instruction and crashing code. It only happens with --gstabs and
5300 --text-section-literals, and when several other obscure relaxation
5301 conditions are met. */
5302 if (outputting_stabs_line_debug
)
5305 if (cur_vinsn
.inside_bundle
)
5306 as_bad (_("missing closing brace"));
5308 /* If there is a non-zero instruction fragment, close it. */
5309 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5311 frag_wane (frag_now
);
5313 xtensa_set_frag_assembly_state (frag_now
);
5315 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5317 xtensa_clear_insn_labels ();
5321 /* We had an error while parsing an instruction. The string might look
5322 like this: "insn arg1, arg2 }". If so, we need to see the closing
5323 brace and reset some fields. Otherwise, the vinsn never gets closed
5324 and the num_slots field will grow past the end of the array of slots,
5325 and bad things happen. */
5328 error_reset_cur_vinsn (void)
5330 if (cur_vinsn
.inside_bundle
)
5332 if (*input_line_pointer
== '}'
5333 || *(input_line_pointer
- 1) == '}'
5334 || *(input_line_pointer
- 2) == '}')
5335 xg_clear_vinsn (&cur_vinsn
);
5341 md_assemble (char *str
)
5343 xtensa_isa isa
= xtensa_default_isa
;
5346 bfd_boolean has_underbar
= FALSE
;
5347 char *arg_strings
[MAX_INSN_ARGS
];
5349 TInsn orig_insn
; /* Original instruction from the input. */
5351 tinsn_init (&orig_insn
);
5353 /* Split off the opcode. */
5354 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5355 opname
= xmalloc (opnamelen
+ 1);
5356 memcpy (opname
, str
, opnamelen
);
5357 opname
[opnamelen
] = '\0';
5359 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5362 as_bad (_("syntax error"));
5366 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5369 /* Check for an underbar prefix. */
5372 has_underbar
= TRUE
;
5376 orig_insn
.insn_type
= ITYPE_INSN
;
5378 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5379 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5381 /* Special case: Check for "CALLXn.TLS" psuedo op. If found, grab its
5382 extra argument and set the opcode to "CALLXn". */
5383 if (orig_insn
.opcode
== XTENSA_UNDEFINED
5384 && strncasecmp (opname
, "callx", 5) == 0)
5386 unsigned long window_size
;
5389 window_size
= strtoul (opname
+ 5, &suffix
, 10);
5390 if (suffix
!= opname
+ 5
5391 && (window_size
== 0
5394 || window_size
== 12)
5395 && strcasecmp (suffix
, ".tls") == 0)
5397 switch (window_size
)
5399 case 0: orig_insn
.opcode
= xtensa_callx0_opcode
; break;
5400 case 4: orig_insn
.opcode
= xtensa_callx4_opcode
; break;
5401 case 8: orig_insn
.opcode
= xtensa_callx8_opcode
; break;
5402 case 12: orig_insn
.opcode
= xtensa_callx12_opcode
; break;
5406 as_bad (_("wrong number of operands for '%s'"), opname
);
5409 bfd_reloc_code_real_type reloc
;
5410 char *old_input_line_pointer
;
5411 expressionS
*tok
= &orig_insn
.extra_arg
;
5414 old_input_line_pointer
= input_line_pointer
;
5415 input_line_pointer
= arg_strings
[num_args
- 1];
5417 t
= expression (tok
);
5418 if (tok
->X_op
== O_symbol
5419 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
5420 == BFD_RELOC_XTENSA_TLS_CALL
))
5421 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
5423 as_bad (_("bad relocation expression for '%s'"), opname
);
5425 input_line_pointer
= old_input_line_pointer
;
5431 /* Special case: Check for "j.l" psuedo op. */
5432 if (orig_insn
.opcode
== XTENSA_UNDEFINED
5433 && strncasecmp (opname
, "j.l", 3) == 0)
5436 as_bad (_("wrong number of operands for '%s'"), opname
);
5439 char *old_input_line_pointer
;
5440 expressionS
*tok
= &orig_insn
.extra_arg
;
5442 old_input_line_pointer
= input_line_pointer
;
5443 input_line_pointer
= arg_strings
[num_args
- 1];
5445 expression_maybe_register (xtensa_jx_opcode
, 0, tok
);
5446 input_line_pointer
= old_input_line_pointer
;
5449 orig_insn
.opcode
= xtensa_j_opcode
;
5453 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5455 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5456 if (fmt
== XTENSA_UNDEFINED
)
5458 as_bad (_("unknown opcode or format name '%s'"), opname
);
5459 error_reset_cur_vinsn ();
5462 if (!cur_vinsn
.inside_bundle
)
5464 as_bad (_("format names only valid inside bundles"));
5465 error_reset_cur_vinsn ();
5468 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5469 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5471 cur_vinsn
.format
= fmt
;
5472 free (has_underbar
? opname
- 1 : opname
);
5473 error_reset_cur_vinsn ();
5477 /* Parse the arguments. */
5478 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5480 as_bad (_("syntax error"));
5481 error_reset_cur_vinsn ();
5485 /* Free the opcode and argument strings, now that they've been parsed. */
5486 free (has_underbar
? opname
- 1 : opname
);
5488 while (num_args
-- > 0)
5489 free (arg_strings
[num_args
]);
5491 /* Get expressions for invisible operands. */
5492 if (get_invisible_operands (&orig_insn
))
5494 error_reset_cur_vinsn ();
5498 /* Check for the right number and type of arguments. */
5499 if (tinsn_check_arguments (&orig_insn
))
5501 error_reset_cur_vinsn ();
5505 /* Record the line number for each TInsn, because a FLIX bundle may be
5506 spread across multiple input lines and individual instructions may be
5507 moved around in some cases. */
5508 orig_insn
.loc_directive_seen
= dwarf2_loc_directive_seen
;
5509 dwarf2_where (&orig_insn
.debug_line
);
5510 dwarf2_consume_line_info ();
5512 xg_add_branch_and_loop_targets (&orig_insn
);
5514 /* Check that immediate value for ENTRY is >= 16. */
5515 if (orig_insn
.opcode
== xtensa_entry_opcode
&& orig_insn
.ntok
>= 3)
5517 expressionS
*exp
= &orig_insn
.tok
[2];
5518 if (exp
->X_op
== O_constant
&& exp
->X_add_number
< 16)
5519 as_warn (_("entry instruction with stack decrement < 16"));
5523 assemble_tokens (opcode, tok, ntok);
5524 expand the tokens from the orig_insn into the
5525 stack of instructions that will not expand
5526 unless required at relaxation time. */
5528 if (!cur_vinsn
.inside_bundle
)
5529 emit_single_op (&orig_insn
);
5530 else /* We are inside a bundle. */
5532 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5533 cur_vinsn
.num_slots
++;
5534 if (*input_line_pointer
== '}'
5535 || *(input_line_pointer
- 1) == '}'
5536 || *(input_line_pointer
- 2) == '}')
5537 finish_vinsn (&cur_vinsn
);
5540 /* We've just emitted a new instruction so clear the list of labels. */
5541 xtensa_clear_insn_labels ();
5545 /* HANDLE_ALIGN hook */
5547 /* For a .align directive, we mark the previous block with the alignment
5548 information. This will be placed in the object file in the
5549 property section corresponding to this section. */
5552 xtensa_handle_align (fragS
*fragP
)
5555 && ! fragP
->tc_frag_data
.is_literal
5556 && (fragP
->fr_type
== rs_align
5557 || fragP
->fr_type
== rs_align_code
)
5558 && fragP
->fr_address
+ fragP
->fr_fix
> 0
5559 && fragP
->fr_offset
> 0
5560 && now_seg
!= bss_section
)
5562 fragP
->tc_frag_data
.is_align
= TRUE
;
5563 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5566 if (fragP
->fr_type
== rs_align_test
)
5569 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5571 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5572 _("unaligned entry instruction"));
5575 if (linkrelax
&& fragP
->fr_type
== rs_org
)
5576 fragP
->fr_subtype
= RELAX_ORG
;
5580 /* TC_FRAG_INIT hook */
5583 xtensa_frag_init (fragS
*frag
)
5585 xtensa_set_frag_assembly_state (frag
);
5590 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5596 /* Round up a section size to the appropriate boundary. */
5599 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5601 return size
; /* Byte alignment is fine. */
5606 md_pcrel_from (fixS
*fixP
)
5609 static xtensa_insnbuf insnbuf
= NULL
;
5610 static xtensa_insnbuf slotbuf
= NULL
;
5613 xtensa_opcode opcode
;
5616 xtensa_isa isa
= xtensa_default_isa
;
5617 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5618 bfd_boolean alt_reloc
;
5620 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5623 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
5628 insnbuf
= xtensa_insnbuf_alloc (isa
);
5629 slotbuf
= xtensa_insnbuf_alloc (isa
);
5632 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5633 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) insn_p
, 0);
5634 fmt
= xtensa_format_decode (isa
, insnbuf
);
5636 if (fmt
== XTENSA_UNDEFINED
)
5637 as_fatal (_("bad instruction format"));
5639 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5640 as_fatal (_("invalid relocation"));
5642 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5643 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5645 /* Check for "alternate" relocations (operand not specified). None
5646 of the current uses for these are really PC-relative. */
5647 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5649 if (opcode
!= xtensa_l32r_opcode
5650 && opcode
!= xtensa_const16_opcode
)
5651 as_fatal (_("invalid relocation for '%s' instruction"),
5652 xtensa_opcode_name (isa
, opcode
));
5656 opnum
= get_relaxable_immed (opcode
);
5658 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5659 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5661 as_bad_where (fixP
->fx_file
,
5663 _("invalid relocation for operand %d of '%s'"),
5664 opnum
, xtensa_opcode_name (isa
, opcode
));
5667 return 0 - opnd_value
;
5671 /* TC_FORCE_RELOCATION hook */
5674 xtensa_force_relocation (fixS
*fix
)
5676 switch (fix
->fx_r_type
)
5678 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5679 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5680 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5681 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5682 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5683 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5684 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5685 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5686 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5687 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5688 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5689 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5690 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5691 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5692 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5693 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5699 if (linkrelax
&& fix
->fx_addsy
5700 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5703 return generic_force_reloc (fix
);
5707 /* TC_VALIDATE_FIX_SUB hook */
5710 xtensa_validate_fix_sub (fixS
*fix
)
5712 segT add_symbol_segment
, sub_symbol_segment
;
5714 /* The difference of two symbols should be resolved by the assembler when
5715 linkrelax is not set. If the linker may relax the section containing
5716 the symbols, then an Xtensa DIFF relocation must be generated so that
5717 the linker knows to adjust the difference value. */
5718 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
5721 /* Make sure both symbols are in the same segment, and that segment is
5722 "normal" and relaxable. If the segment is not "normal", then the
5723 fix is not valid. If the segment is not "relaxable", then the fix
5724 should have been handled earlier. */
5725 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
5726 if (! SEG_NORMAL (add_symbol_segment
) ||
5727 ! relaxable_section (add_symbol_segment
))
5729 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
5730 return (sub_symbol_segment
== add_symbol_segment
);
5734 /* NO_PSEUDO_DOT hook */
5736 /* This function has nothing to do with pseudo dots, but this is the
5737 nearest macro to where the check needs to take place. FIXME: This
5741 xtensa_check_inside_bundle (void)
5743 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5744 as_bad (_("directives are not valid inside bundles"));
5746 /* This function must always return FALSE because it is called via a
5747 macro that has nothing to do with bundling. */
5752 /* md_elf_section_change_hook */
5755 xtensa_elf_section_change_hook (void)
5757 /* Set up the assembly state. */
5758 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5759 xtensa_set_frag_assembly_state (frag_now
);
5763 /* tc_fix_adjustable hook */
5766 xtensa_fix_adjustable (fixS
*fixP
)
5768 /* An offset is not allowed in combination with the difference of two
5769 symbols, but that cannot be easily detected after a local symbol
5770 has been adjusted to a (section+offset) form. Return 0 so that such
5771 an fix will not be adjusted. */
5772 if (fixP
->fx_subsy
&& fixP
->fx_addsy
&& fixP
->fx_offset
5773 && relaxable_section (S_GET_SEGMENT (fixP
->fx_subsy
)))
5776 /* We need the symbol name for the VTABLE entries. */
5777 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5778 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5785 /* tc_symbol_new_hook */
5787 symbolS
*expr_symbols
= NULL
;
5790 xtensa_symbol_new_hook (symbolS
*sym
)
5792 if (is_leb128_expr
&& S_GET_SEGMENT (sym
) == expr_section
)
5794 symbol_get_tc (sym
)->next_expr_symbol
= expr_symbols
;
5801 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg
)
5803 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5806 /* Subtracted symbols are only allowed for a few relocation types, and
5807 unless linkrelax is enabled, they should not make it to this point. */
5808 if (fixP
->fx_subsy
&& !(linkrelax
&& (fixP
->fx_r_type
== BFD_RELOC_32
5809 || fixP
->fx_r_type
== BFD_RELOC_16
5810 || fixP
->fx_r_type
== BFD_RELOC_8
)))
5811 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("expression too complex"));
5813 switch (fixP
->fx_r_type
)
5815 case BFD_RELOC_32_PCREL
:
5821 switch (fixP
->fx_r_type
)
5824 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF8
;
5827 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF16
;
5830 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF32
;
5836 /* An offset is only allowed when it results from adjusting a
5837 local symbol into a section-relative offset. If the offset
5838 came from the original expression, tc_fix_adjustable will have
5839 prevented the fix from being converted to a section-relative
5840 form so that we can flag the error here. */
5841 if (fixP
->fx_offset
!= 0 && !symbol_section_p (fixP
->fx_addsy
))
5842 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5843 _("cannot represent subtraction with an offset"));
5845 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5846 - S_GET_VALUE (fixP
->fx_subsy
));
5848 /* The difference value gets written out, and the DIFF reloc
5849 identifies the address of the subtracted symbol (i.e., the one
5850 with the lowest address). */
5852 fixP
->fx_offset
-= val
;
5853 fixP
->fx_subsy
= NULL
;
5855 else if (! fixP
->fx_addsy
)
5862 case BFD_RELOC_XTENSA_PLT
:
5863 md_number_to_chars (fixpos
, val
, fixP
->fx_size
);
5864 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5867 case BFD_RELOC_XTENSA_TLSDESC_FN
:
5868 case BFD_RELOC_XTENSA_TLSDESC_ARG
:
5869 case BFD_RELOC_XTENSA_TLS_TPOFF
:
5870 case BFD_RELOC_XTENSA_TLS_DTPOFF
:
5871 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
5872 md_number_to_chars (fixpos
, 0, fixP
->fx_size
);
5873 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5876 case BFD_RELOC_XTENSA_SLOT0_OP
:
5877 case BFD_RELOC_XTENSA_SLOT1_OP
:
5878 case BFD_RELOC_XTENSA_SLOT2_OP
:
5879 case BFD_RELOC_XTENSA_SLOT3_OP
:
5880 case BFD_RELOC_XTENSA_SLOT4_OP
:
5881 case BFD_RELOC_XTENSA_SLOT5_OP
:
5882 case BFD_RELOC_XTENSA_SLOT6_OP
:
5883 case BFD_RELOC_XTENSA_SLOT7_OP
:
5884 case BFD_RELOC_XTENSA_SLOT8_OP
:
5885 case BFD_RELOC_XTENSA_SLOT9_OP
:
5886 case BFD_RELOC_XTENSA_SLOT10_OP
:
5887 case BFD_RELOC_XTENSA_SLOT11_OP
:
5888 case BFD_RELOC_XTENSA_SLOT12_OP
:
5889 case BFD_RELOC_XTENSA_SLOT13_OP
:
5890 case BFD_RELOC_XTENSA_SLOT14_OP
:
5893 /* Write the tentative value of a PC-relative relocation to a
5894 local symbol into the instruction. The value will be ignored
5895 by the linker, and it makes the object file disassembly
5896 readable when all branch targets are encoded in relocations. */
5898 gas_assert (fixP
->fx_addsy
);
5899 if (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
5900 && !S_FORCE_RELOC (fixP
->fx_addsy
, 1))
5902 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5903 - md_pcrel_from (fixP
));
5904 (void) xg_apply_fix_value (fixP
, val
);
5907 else if (! fixP
->fx_addsy
)
5910 if (xg_apply_fix_value (fixP
, val
))
5915 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5916 case BFD_RELOC_XTENSA_TLS_FUNC
:
5917 case BFD_RELOC_XTENSA_TLS_ARG
:
5918 case BFD_RELOC_XTENSA_TLS_CALL
:
5919 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5920 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5921 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5922 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5923 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5924 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5925 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5926 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5927 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5928 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5929 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5930 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5931 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5932 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5933 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5934 /* These all need to be resolved at link-time. Do nothing now. */
5937 case BFD_RELOC_VTABLE_INHERIT
:
5938 case BFD_RELOC_VTABLE_ENTRY
:
5943 as_bad (_("unhandled local relocation fix %s"),
5944 bfd_get_reloc_code_name (fixP
->fx_r_type
));
5950 md_atof (int type
, char *litP
, int *sizeP
)
5952 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
5957 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
5959 return total_frag_text_expansion (fragP
);
5963 /* Translate internal representation of relocation info to BFD target
5967 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
5971 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
5972 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5973 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5974 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5976 /* Make sure none of our internal relocations make it this far.
5977 They'd better have been fully resolved by this point. */
5978 gas_assert ((int) fixp
->fx_r_type
> 0);
5980 reloc
->addend
= fixp
->fx_offset
;
5982 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
5983 if (reloc
->howto
== NULL
)
5985 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5986 _("cannot represent `%s' relocation in object file"),
5987 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5988 free (reloc
->sym_ptr_ptr
);
5993 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
5994 as_fatal (_("internal error; cannot generate `%s' relocation"),
5995 bfd_get_reloc_code_name (fixp
->fx_r_type
));
6001 /* Checks for resource conflicts between instructions. */
6003 /* The func unit stuff could be implemented as bit-vectors rather
6004 than the iterative approach here. If it ends up being too
6005 slow, we will switch it. */
6008 new_resource_table (void *data
,
6011 unit_num_copies_func uncf
,
6012 opcode_num_units_func onuf
,
6013 opcode_funcUnit_use_unit_func ouuf
,
6014 opcode_funcUnit_use_stage_func ousf
)
6017 resource_table
*rt
= (resource_table
*) xmalloc (sizeof (resource_table
));
6019 rt
->cycles
= cycles
;
6020 rt
->allocated_cycles
= cycles
;
6022 rt
->unit_num_copies
= uncf
;
6023 rt
->opcode_num_units
= onuf
;
6024 rt
->opcode_unit_use
= ouuf
;
6025 rt
->opcode_unit_stage
= ousf
;
6027 rt
->units
= (unsigned char **) xcalloc (cycles
, sizeof (unsigned char *));
6028 for (i
= 0; i
< cycles
; i
++)
6029 rt
->units
[i
] = (unsigned char *) xcalloc (nu
, sizeof (unsigned char));
6036 clear_resource_table (resource_table
*rt
)
6039 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
6040 for (j
= 0; j
< rt
->num_units
; j
++)
6041 rt
->units
[i
][j
] = 0;
6045 /* We never shrink it, just fake it into thinking so. */
6048 resize_resource_table (resource_table
*rt
, int cycles
)
6052 rt
->cycles
= cycles
;
6053 if (cycles
<= rt
->allocated_cycles
)
6056 old_cycles
= rt
->allocated_cycles
;
6057 rt
->allocated_cycles
= cycles
;
6059 rt
->units
= xrealloc (rt
->units
,
6060 rt
->allocated_cycles
* sizeof (unsigned char *));
6061 for (i
= 0; i
< old_cycles
; i
++)
6062 rt
->units
[i
] = xrealloc (rt
->units
[i
],
6063 rt
->num_units
* sizeof (unsigned char));
6064 for (i
= old_cycles
; i
< cycles
; i
++)
6065 rt
->units
[i
] = xcalloc (rt
->num_units
, sizeof (unsigned char));
6070 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6073 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6075 for (i
= 0; i
< uses
; i
++)
6077 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6078 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6079 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
6080 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
6081 if (copies_in_use
>= copies
)
6089 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6092 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6094 for (i
= 0; i
< uses
; i
++)
6096 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6097 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6098 /* Note that this allows resources to be oversubscribed. That's
6099 essential to the way the optional scheduler works.
6100 resources_available reports when a resource is over-subscribed,
6101 so it's easy to tell. */
6102 rt
->units
[stage
+ cycle
][unit
]++;
6108 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6111 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6113 for (i
= 0; i
< uses
; i
++)
6115 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6116 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6117 gas_assert (rt
->units
[stage
+ cycle
][unit
] > 0);
6118 rt
->units
[stage
+ cycle
][unit
]--;
6123 /* Wrapper functions make parameterized resource reservation
6127 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
6129 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
6135 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
6137 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
6142 /* Note that this function does not check issue constraints, but
6143 solely whether the hardware is available to execute the given
6144 instructions together. It also doesn't check if the tinsns
6145 write the same state, or access the same tieports. That is
6146 checked by check_t1_t2_reads_and_writes. */
6149 resources_conflict (vliw_insn
*vinsn
)
6152 static resource_table
*rt
= NULL
;
6154 /* This is the most common case by far. Optimize it. */
6155 if (vinsn
->num_slots
== 1)
6160 xtensa_isa isa
= xtensa_default_isa
;
6161 rt
= new_resource_table
6162 (isa
, xtensa_num_pipe_stages
,
6163 xtensa_isa_num_funcUnits (isa
),
6164 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
6165 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
6166 opcode_funcUnit_use_unit
,
6167 opcode_funcUnit_use_stage
);
6170 clear_resource_table (rt
);
6172 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6174 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
6176 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
6183 /* finish_vinsn, emit_single_op and helper functions. */
6185 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
6186 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
6187 static void xg_assemble_vliw_tokens (vliw_insn
*);
6190 /* We have reached the end of a bundle; emit into the frag. */
6193 finish_vinsn (vliw_insn
*vinsn
)
6200 if (find_vinsn_conflicts (vinsn
))
6202 xg_clear_vinsn (vinsn
);
6206 /* First, find a format that works. */
6207 if (vinsn
->format
== XTENSA_UNDEFINED
)
6208 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6210 if (xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
) > 1
6211 && produce_flix
== FLIX_NONE
)
6213 as_bad (_("The option \"--no-allow-flix\" prohibits multi-slot flix."));
6214 xg_clear_vinsn (vinsn
);
6218 if (vinsn
->format
== XTENSA_UNDEFINED
)
6220 as_where (&file_name
, &line
);
6221 as_bad_where (file_name
, line
,
6222 _("couldn't find a valid instruction format"));
6223 fprintf (stderr
, _(" ops were: "));
6224 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6225 fprintf (stderr
, _(" %s;"),
6226 xtensa_opcode_name (xtensa_default_isa
,
6227 vinsn
->slots
[i
].opcode
));
6228 fprintf (stderr
, _("\n"));
6229 xg_clear_vinsn (vinsn
);
6233 if (vinsn
->num_slots
6234 != xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
))
6236 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
6237 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
6238 xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
),
6240 xg_clear_vinsn (vinsn
);
6244 if (resources_conflict (vinsn
))
6246 as_where (&file_name
, &line
);
6247 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6248 fprintf (stderr
, " ops were: ");
6249 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6250 fprintf (stderr
, " %s;",
6251 xtensa_opcode_name (xtensa_default_isa
,
6252 vinsn
->slots
[i
].opcode
));
6253 fprintf (stderr
, "\n");
6254 xg_clear_vinsn (vinsn
);
6258 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6260 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
6262 symbolS
*lit_sym
= NULL
;
6264 bfd_boolean e
= FALSE
;
6265 bfd_boolean saved_density
= density_supported
;
6267 /* We don't want to narrow ops inside multi-slot bundles. */
6268 if (vinsn
->num_slots
> 1)
6269 density_supported
= FALSE
;
6271 istack_init (&slotstack
);
6272 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
6274 vinsn
->slots
[i
].opcode
=
6275 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6277 vinsn
->slots
[i
].ntok
= 0;
6280 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
6286 density_supported
= saved_density
;
6290 xg_clear_vinsn (vinsn
);
6294 for (j
= 0; j
< slotstack
.ninsn
; j
++)
6296 TInsn
*insn
= &slotstack
.insn
[j
];
6297 if (insn
->insn_type
== ITYPE_LITERAL
)
6299 gas_assert (lit_sym
== NULL
);
6300 lit_sym
= xg_assemble_literal (insn
);
6304 gas_assert (insn
->insn_type
== ITYPE_INSN
);
6306 xg_resolve_literals (insn
, lit_sym
);
6307 if (j
!= slotstack
.ninsn
- 1)
6308 emit_single_op (insn
);
6312 if (vinsn
->num_slots
> 1)
6314 if (opcode_fits_format_slot
6315 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6318 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6322 emit_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6323 if (vinsn
->format
== XTENSA_UNDEFINED
)
6324 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6326 vinsn
->slots
[i
].opcode
6327 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6330 vinsn
->slots
[i
].ntok
= 0;
6335 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6336 vinsn
->format
= XTENSA_UNDEFINED
;
6341 /* Now check resource conflicts on the modified bundle. */
6342 if (resources_conflict (vinsn
))
6344 as_where (&file_name
, &line
);
6345 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6346 fprintf (stderr
, " ops were: ");
6347 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6348 fprintf (stderr
, " %s;",
6349 xtensa_opcode_name (xtensa_default_isa
,
6350 vinsn
->slots
[i
].opcode
));
6351 fprintf (stderr
, "\n");
6352 xg_clear_vinsn (vinsn
);
6356 /* First, find a format that works. */
6357 if (vinsn
->format
== XTENSA_UNDEFINED
)
6358 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6360 xg_assemble_vliw_tokens (vinsn
);
6362 xg_clear_vinsn (vinsn
);
6366 /* Given an vliw instruction, what conflicts are there in register
6367 usage and in writes to states and queues?
6369 This function does two things:
6370 1. Reports an error when a vinsn contains illegal combinations
6371 of writes to registers states or queues.
6372 2. Marks individual tinsns as not relaxable if the combination
6373 contains antidependencies.
6375 Job 2 handles things like swap semantics in instructions that need
6376 to be relaxed. For example,
6380 normally would be relaxed to
6385 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6387 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6389 then we can't relax it into
6392 { add a0, a1, a0 ; add a2, a0, a4 ; }
6394 because the value of a0 is trashed before the second add can read it. */
6396 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6399 find_vinsn_conflicts (vliw_insn
*vinsn
)
6403 xtensa_isa isa
= xtensa_default_isa
;
6405 gas_assert (!past_xtensa_end
);
6407 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6409 TInsn
*op1
= &vinsn
->slots
[i
];
6410 if (op1
->is_specific_opcode
)
6411 op1
->keep_wide
= TRUE
;
6413 op1
->keep_wide
= FALSE
;
6416 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6418 TInsn
*op1
= &vinsn
->slots
[i
];
6420 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6423 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6427 TInsn
*op2
= &vinsn
->slots
[j
];
6428 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6429 switch (conflict_type
)
6432 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6433 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6434 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6437 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6438 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6439 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6442 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"),
6443 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6444 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6447 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"),
6448 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6449 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6452 /* Everything is OK. */
6455 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6456 || conflict_type
== 'a');
6463 as_bad (_("multiple branches or jumps in the same bundle"));
6471 /* Check how the state used by t1 and t2 relate.
6474 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6475 case B: no relationship between what is read and written (both could
6476 read the same reg though)
6477 case C: t1 writes a register t2 writes (a register conflict within a
6479 case D: t1 writes a state that t2 also writes
6480 case E: t1 writes a tie queue that t2 also writes
6481 case F: two volatile queue accesses
6485 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6487 xtensa_isa isa
= xtensa_default_isa
;
6488 xtensa_regfile t1_regfile
, t2_regfile
;
6490 int t1_base_reg
, t1_last_reg
;
6491 int t2_base_reg
, t2_last_reg
;
6492 char t1_inout
, t2_inout
;
6494 char conflict
= 'b';
6499 bfd_boolean t1_volatile
= FALSE
;
6500 bfd_boolean t2_volatile
= FALSE
;
6502 /* Check registers. */
6503 for (j
= 0; j
< t2
->ntok
; j
++)
6505 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6508 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6509 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6510 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6512 for (i
= 0; i
< t1
->ntok
; i
++)
6514 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6517 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6519 if (t1_regfile
!= t2_regfile
)
6522 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6523 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6525 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6526 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6528 if (t1_inout
== 'm' || t1_inout
== 'o'
6529 || t2_inout
== 'm' || t2_inout
== 'o')
6536 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6537 t1_last_reg
= (t1_base_reg
6538 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6540 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6542 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6544 if (t1_reg
!= t2_reg
)
6547 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6553 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6559 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6567 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6568 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6569 for (j
= 0; j
< t2_states
; j
++)
6571 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6572 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6573 for (i
= 0; i
< t1_states
; i
++)
6575 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6576 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6577 if (t1_so
!= t2_so
|| xtensa_state_is_shared_or (isa
, t1_so
) == 1)
6580 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6586 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6592 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6597 /* Check tieports. */
6598 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6599 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6600 for (j
= 0; j
< t2_interfaces
; j
++)
6602 xtensa_interface t2_int
6603 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6604 int t2_class
= xtensa_interface_class_id (isa
, t2_int
);
6606 t2_inout
= xtensa_interface_inout (isa
, t2_int
);
6607 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1)
6610 for (i
= 0; i
< t1_interfaces
; i
++)
6612 xtensa_interface t1_int
6613 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6614 int t1_class
= xtensa_interface_class_id (isa
, t1_int
);
6616 t1_inout
= xtensa_interface_inout (isa
, t1_int
);
6617 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1)
6620 if (t1_volatile
&& t2_volatile
&& (t1_class
== t2_class
))
6623 if (t1_int
!= t2_int
)
6626 if (t2_inout
== 'i' && t1_inout
== 'o')
6632 if (t1_inout
== 'i' && t2_inout
== 'o')
6638 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6647 static xtensa_format
6648 xg_find_narrowest_format (vliw_insn
*vinsn
)
6650 /* Right now we assume that the ops within the vinsn are properly
6651 ordered for the slots that the programmer wanted them in. In
6652 other words, we don't rearrange the ops in hopes of finding a
6653 better format. The scheduler handles that. */
6655 xtensa_isa isa
= xtensa_default_isa
;
6656 xtensa_format format
;
6657 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6659 if (vinsn
->num_slots
== 1)
6660 return xg_get_single_format (vinsn
->slots
[0].opcode
);
6662 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6665 xg_copy_vinsn (&v_copy
, vinsn
);
6666 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6670 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6672 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6674 v_copy
.slots
[slot
].opcode
=
6675 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6676 v_copy
.slots
[slot
].ntok
= 0;
6679 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6682 else if (v_copy
.num_slots
> 1)
6685 /* Try the widened version. */
6686 if (!v_copy
.slots
[slot
].keep_wide
6687 && !v_copy
.slots
[slot
].is_specific_opcode
6688 && xg_is_single_relaxable_insn (&v_copy
.slots
[slot
],
6690 && opcode_fits_format_slot (widened
.opcode
,
6693 v_copy
.slots
[slot
] = widened
;
6698 if (fit
== v_copy
.num_slots
)
6700 xg_copy_vinsn (vinsn
, &v_copy
);
6701 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6702 vinsn
->format
= format
;
6708 if (format
== xtensa_isa_num_formats (isa
))
6709 return XTENSA_UNDEFINED
;
6715 /* Return the additional space needed in a frag
6716 for possible relaxations of any ops in a VLIW insn.
6717 Also fill out the relaxations that might be required of
6718 each tinsn in the vinsn. */
6721 relaxation_requirements (vliw_insn
*vinsn
, bfd_boolean
*pfinish_frag
)
6723 bfd_boolean finish_frag
= FALSE
;
6724 int extra_space
= 0;
6727 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6729 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6730 if (!tinsn_has_symbolic_operands (tinsn
))
6732 /* A narrow instruction could be widened later to help
6733 alignment issues. */
6734 if (xg_is_single_relaxable_insn (tinsn
, 0, TRUE
)
6735 && !tinsn
->is_specific_opcode
6736 && vinsn
->num_slots
== 1)
6738 /* Difference in bytes between narrow and wide insns... */
6740 tinsn
->subtype
= RELAX_NARROW
;
6745 if (workaround_b_j_loop_end
6746 && tinsn
->opcode
== xtensa_jx_opcode
6747 && use_transform ())
6749 /* Add 2 of these. */
6750 extra_space
+= 3; /* for the nop size */
6751 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6754 /* Need to assemble it with space for the relocation. */
6755 if (xg_is_relaxable_insn (tinsn
, 0)
6756 && !tinsn
->is_specific_opcode
)
6758 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6759 int max_literal_size
=
6760 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6762 tinsn
->literal_space
= max_literal_size
;
6764 tinsn
->subtype
= RELAX_IMMED
;
6765 extra_space
+= max_size
;
6769 /* A fix record will be added for this instruction prior
6770 to relaxation, so make it end the frag. */
6775 *pfinish_frag
= finish_frag
;
6781 bundle_tinsn (TInsn
*tinsn
, vliw_insn
*vinsn
)
6783 xtensa_isa isa
= xtensa_default_isa
;
6784 int slot
, chosen_slot
;
6786 vinsn
->format
= xg_get_single_format (tinsn
->opcode
);
6787 gas_assert (vinsn
->format
!= XTENSA_UNDEFINED
);
6788 vinsn
->num_slots
= xtensa_format_num_slots (isa
, vinsn
->format
);
6790 chosen_slot
= xg_get_single_slot (tinsn
->opcode
);
6791 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6793 if (slot
== chosen_slot
)
6794 vinsn
->slots
[slot
] = *tinsn
;
6797 vinsn
->slots
[slot
].opcode
=
6798 xtensa_format_slot_nop_opcode (isa
, vinsn
->format
, slot
);
6799 vinsn
->slots
[slot
].ntok
= 0;
6800 vinsn
->slots
[slot
].insn_type
= ITYPE_INSN
;
6807 emit_single_op (TInsn
*orig_insn
)
6810 IStack istack
; /* put instructions into here */
6811 symbolS
*lit_sym
= NULL
;
6812 symbolS
*label_sym
= NULL
;
6814 istack_init (&istack
);
6816 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6817 Because the scheduling and bundling characteristics of movi and
6818 l32r or const16 are so different, we can do much better if we relax
6819 it prior to scheduling and bundling, rather than after. */
6820 if ((orig_insn
->opcode
== xtensa_movi_opcode
6821 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
6822 && !cur_vinsn
.inside_bundle
6823 && (orig_insn
->tok
[1].X_op
== O_symbol
6824 || orig_insn
->tok
[1].X_op
== O_pltrel
6825 || orig_insn
->tok
[1].X_op
== O_tlsfunc
6826 || orig_insn
->tok
[1].X_op
== O_tlsarg
6827 || orig_insn
->tok
[1].X_op
== O_tpoff
6828 || orig_insn
->tok
[1].X_op
== O_dtpoff
)
6829 && !orig_insn
->is_specific_opcode
&& use_transform ())
6830 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
6832 if (xg_expand_assembly_insn (&istack
, orig_insn
))
6835 for (i
= 0; i
< istack
.ninsn
; i
++)
6837 TInsn
*insn
= &istack
.insn
[i
];
6838 switch (insn
->insn_type
)
6841 gas_assert (lit_sym
== NULL
);
6842 lit_sym
= xg_assemble_literal (insn
);
6846 static int relaxed_sym_idx
= 0;
6847 char *label
= xmalloc (strlen (FAKE_LABEL_NAME
) + 12);
6848 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
6850 gas_assert (label_sym
== NULL
);
6851 label_sym
= symbol_find_or_make (label
);
6852 gas_assert (label_sym
);
6860 xg_resolve_literals (insn
, lit_sym
);
6862 xg_resolve_labels (insn
, label_sym
);
6864 bundle_tinsn (insn
, &v
);
6879 total_frag_text_expansion (fragS
*fragP
)
6882 int total_expansion
= 0;
6884 for (slot
= 0; slot
< MAX_SLOTS
; slot
++)
6885 total_expansion
+= fragP
->tc_frag_data
.text_expansion
[slot
];
6887 return total_expansion
;
6891 /* Emit a vliw instruction to the current fragment. */
6894 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
6896 bfd_boolean finish_frag
;
6897 bfd_boolean is_jump
= FALSE
;
6898 bfd_boolean is_branch
= FALSE
;
6899 xtensa_isa isa
= xtensa_default_isa
;
6904 struct dwarf2_line_info debug_line
;
6905 bfd_boolean loc_directive_seen
= FALSE
;
6908 memset (&debug_line
, 0, sizeof (struct dwarf2_line_info
));
6910 if (generating_literals
)
6912 static int reported
= 0;
6914 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
6915 _("cannot assemble into a literal fragment"));
6922 if (frag_now_fix () != 0
6923 && (! frag_now
->tc_frag_data
.is_insn
6924 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6925 || !use_transform () != frag_now
->tc_frag_data
.is_no_transform
6926 || (directive_state
[directive_longcalls
]
6927 != frag_now
->tc_frag_data
.use_longcalls
)
6928 || (directive_state
[directive_absolute_literals
]
6929 != frag_now
->tc_frag_data
.use_absolute_literals
)))
6931 frag_wane (frag_now
);
6933 xtensa_set_frag_assembly_state (frag_now
);
6936 if (workaround_a0_b_retw
6937 && vinsn
->num_slots
== 1
6938 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
6939 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
6940 && use_transform ())
6942 has_a0_b_retw
= TRUE
;
6944 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
6945 After the first assembly pass we will check all of them and
6946 add a nop if needed. */
6947 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6948 frag_var (rs_machine_dependent
, 4, 4,
6949 RELAX_ADD_NOP_IF_A0_B_RETW
,
6950 frag_now
->fr_symbol
,
6951 frag_now
->fr_offset
,
6953 xtensa_set_frag_assembly_state (frag_now
);
6954 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6955 frag_var (rs_machine_dependent
, 4, 4,
6956 RELAX_ADD_NOP_IF_A0_B_RETW
,
6957 frag_now
->fr_symbol
,
6958 frag_now
->fr_offset
,
6960 xtensa_set_frag_assembly_state (frag_now
);
6963 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6965 tinsn
= &vinsn
->slots
[slot
];
6967 /* See if the instruction implies an aligned section. */
6968 if (xtensa_opcode_is_loop (isa
, tinsn
->opcode
) == 1)
6969 record_alignment (now_seg
, 2);
6971 /* Determine the best line number for debug info. */
6972 if ((tinsn
->loc_directive_seen
|| !loc_directive_seen
)
6973 && (tinsn
->debug_line
.filenum
!= debug_line
.filenum
6974 || tinsn
->debug_line
.line
< debug_line
.line
6975 || tinsn
->debug_line
.column
< debug_line
.column
))
6976 debug_line
= tinsn
->debug_line
;
6977 if (tinsn
->loc_directive_seen
)
6978 loc_directive_seen
= TRUE
;
6981 /* Special cases for instructions that force an alignment... */
6982 /* None of these opcodes are bundle-able. */
6983 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
6987 /* Remember the symbol that marks the end of the loop in the frag
6988 that marks the start of the loop. This way we can easily find
6989 the end of the loop at the beginning, without adding special code
6990 to mark the loop instructions themselves. */
6991 symbolS
*target_sym
= NULL
;
6992 if (vinsn
->slots
[0].tok
[1].X_op
== O_symbol
)
6993 target_sym
= vinsn
->slots
[0].tok
[1].X_add_symbol
;
6995 xtensa_set_frag_assembly_state (frag_now
);
6996 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6998 max_fill
= get_text_align_max_fill_size
6999 (get_text_align_power (xtensa_fetch_width
),
7000 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
7002 if (use_transform ())
7003 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
7004 RELAX_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
7006 frag_var (rs_machine_dependent
, 0, 0,
7007 RELAX_CHECK_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
7008 xtensa_set_frag_assembly_state (frag_now
);
7011 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
7012 && !vinsn
->slots
[0].is_specific_opcode
)
7014 xtensa_mark_literal_pool_location ();
7015 xtensa_move_labels (frag_now
, 0);
7016 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
7019 if (vinsn
->num_slots
== 1)
7021 if (workaround_a0_b_retw
&& use_transform ())
7022 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
7023 is_register_writer (&vinsn
->slots
[0], "a", 0));
7025 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
7026 is_bad_loopend_opcode (&vinsn
->slots
[0]));
7029 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
7031 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
7033 extra_space
= relaxation_requirements (vinsn
, &finish_frag
);
7035 /* vinsn_to_insnbuf will produce the error. */
7036 if (vinsn
->format
!= XTENSA_UNDEFINED
)
7038 f
= frag_more (insn_size
+ extra_space
);
7039 xtensa_set_frag_assembly_state (frag_now
);
7040 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7043 vinsn_to_insnbuf (vinsn
, f
, frag_now
, FALSE
);
7044 if (vinsn
->format
== XTENSA_UNDEFINED
)
7047 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, (unsigned char *) f
, 0);
7049 if (debug_type
== DEBUG_DWARF2
|| loc_directive_seen
)
7050 dwarf2_gen_line_info (frag_now_fix () - (insn_size
+ extra_space
),
7053 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
7055 tinsn
= &vinsn
->slots
[slot
];
7056 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
7057 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
7058 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
7059 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
7060 if (tinsn
->literal_space
!= 0)
7061 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
7062 frag_now
->tc_frag_data
.free_reg
[slot
] = tinsn
->extra_arg
;
7064 if (tinsn
->subtype
== RELAX_NARROW
)
7065 gas_assert (vinsn
->num_slots
== 1);
7066 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
7068 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
7071 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->offset
7072 || tinsn
->literal_frag
|| is_jump
|| is_branch
)
7076 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7077 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
7081 frag_variant (rs_machine_dependent
,
7082 extra_space
, extra_space
, RELAX_SLOTS
,
7083 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
7084 xtensa_set_frag_assembly_state (frag_now
);
7087 /* Special cases for loops:
7088 close_loop_end should be inserted AFTER short_loop.
7089 Make sure that CLOSE loops are processed BEFORE short_loops
7090 when converting them. */
7092 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
7093 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1
7094 && !vinsn
->slots
[0].is_specific_opcode
)
7096 if (workaround_short_loop
&& use_transform ())
7098 maybe_has_short_loop
= TRUE
;
7099 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7100 frag_var (rs_machine_dependent
, 4, 4,
7101 RELAX_ADD_NOP_IF_SHORT_LOOP
,
7102 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7103 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7104 frag_var (rs_machine_dependent
, 4, 4,
7105 RELAX_ADD_NOP_IF_SHORT_LOOP
,
7106 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7109 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
7110 loop at least 12 bytes away from another loop's end. */
7111 if (workaround_close_loop_end
&& use_transform ())
7113 maybe_has_close_loop_end
= TRUE
;
7114 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7115 frag_var (rs_machine_dependent
, 12, 12,
7116 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
7117 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7121 if (use_transform ())
7125 gas_assert (finish_frag
);
7126 frag_var (rs_machine_dependent
,
7127 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
7129 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7130 xtensa_set_frag_assembly_state (frag_now
);
7132 else if (is_branch
&& do_align_targets ())
7134 gas_assert (finish_frag
);
7135 frag_var (rs_machine_dependent
,
7136 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
7137 RELAX_MAYBE_UNREACHABLE
,
7138 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7139 xtensa_set_frag_assembly_state (frag_now
);
7140 frag_var (rs_machine_dependent
,
7142 RELAX_MAYBE_DESIRE_ALIGN
,
7143 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7144 xtensa_set_frag_assembly_state (frag_now
);
7148 /* Now, if the original opcode was a call... */
7149 if (do_align_targets ()
7150 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
7152 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
7153 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7154 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
7155 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7156 xtensa_set_frag_assembly_state (frag_now
);
7159 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7161 frag_wane (frag_now
);
7163 xtensa_set_frag_assembly_state (frag_now
);
7168 /* xtensa_end and helper functions. */
7170 static void xtensa_cleanup_align_frags (void);
7171 static void xtensa_fix_target_frags (void);
7172 static void xtensa_mark_narrow_branches (void);
7173 static void xtensa_mark_zcl_first_insns (void);
7174 static void xtensa_mark_difference_of_two_symbols (void);
7175 static void xtensa_fix_a0_b_retw_frags (void);
7176 static void xtensa_fix_b_j_loop_end_frags (void);
7177 static void xtensa_fix_close_loop_end_frags (void);
7178 static void xtensa_fix_short_loop_frags (void);
7179 static void xtensa_sanity_check (void);
7180 static void xtensa_add_config_info (void);
7185 directive_balance ();
7186 xtensa_flush_pending_output ();
7188 past_xtensa_end
= TRUE
;
7190 xtensa_move_literals ();
7192 xtensa_reorder_segments ();
7193 xtensa_cleanup_align_frags ();
7194 xtensa_fix_target_frags ();
7195 if (workaround_a0_b_retw
&& has_a0_b_retw
)
7196 xtensa_fix_a0_b_retw_frags ();
7197 if (workaround_b_j_loop_end
)
7198 xtensa_fix_b_j_loop_end_frags ();
7200 /* "close_loop_end" should be processed BEFORE "short_loop". */
7201 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
7202 xtensa_fix_close_loop_end_frags ();
7204 if (workaround_short_loop
&& maybe_has_short_loop
)
7205 xtensa_fix_short_loop_frags ();
7207 xtensa_mark_narrow_branches ();
7208 xtensa_mark_zcl_first_insns ();
7210 xtensa_sanity_check ();
7212 xtensa_add_config_info ();
7217 xtensa_cleanup_align_frags (void)
7222 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7223 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7226 /* Walk over all of the fragments in a subsection. */
7227 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7229 if ((fragP
->fr_type
== rs_align
7230 || fragP
->fr_type
== rs_align_code
7231 || (fragP
->fr_type
== rs_machine_dependent
7232 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
7233 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
7234 && fragP
->fr_fix
== 0)
7236 fragS
*next
= fragP
->fr_next
;
7239 && next
->fr_fix
== 0
7240 && next
->fr_type
== rs_machine_dependent
7241 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7244 next
= next
->fr_next
;
7247 /* If we don't widen branch targets, then they
7248 will be easier to align. */
7249 if (fragP
->tc_frag_data
.is_branch_target
7250 && fragP
->fr_opcode
== fragP
->fr_literal
7251 && fragP
->fr_type
== rs_machine_dependent
7252 && fragP
->fr_subtype
== RELAX_SLOTS
7253 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
7255 if (fragP
->fr_type
== rs_machine_dependent
7256 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
7257 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
7263 /* Re-process all of the fragments looking to convert all of the
7264 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
7265 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7266 Otherwise, convert to a .fill 0. */
7269 xtensa_fix_target_frags (void)
7274 /* When this routine is called, all of the subsections are still intact
7275 so we walk over subsections instead of sections. */
7276 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7277 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7281 /* Walk over all of the fragments in a subsection. */
7282 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7284 if (fragP
->fr_type
== rs_machine_dependent
7285 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7287 if (next_frag_is_branch_target (fragP
))
7288 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7297 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
7300 xtensa_mark_narrow_branches (void)
7305 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7306 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7309 /* Walk over all of the fragments in a subsection. */
7310 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7312 if (fragP
->fr_type
== rs_machine_dependent
7313 && fragP
->fr_subtype
== RELAX_SLOTS
7314 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7318 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7319 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
7321 if (vinsn
.num_slots
== 1
7322 && xtensa_opcode_is_branch (xtensa_default_isa
,
7323 vinsn
.slots
[0].opcode
) == 1
7324 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
7325 && is_narrow_branch_guaranteed_in_range (fragP
,
7328 fragP
->fr_subtype
= RELAX_SLOTS
;
7329 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
7330 fragP
->tc_frag_data
.is_aligning_branch
= 1;
7338 /* A branch is typically widened only when its target is out of
7339 range. However, we would like to widen them to align a subsequent
7340 branch target when possible.
7342 Because the branch relaxation code is so convoluted, the optimal solution
7343 (combining the two cases) is difficult to get right in all circumstances.
7344 We therefore go with an "almost as good" solution, where we only
7345 use for alignment narrow branches that definitely will not expand to a
7346 jump and a branch. These functions find and mark these cases. */
7348 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
7349 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7350 We start counting beginning with the frag after the 2-byte branch, so the
7351 maximum offset is (4 - 2) + 63 = 65. */
7352 #define MAX_IMMED6 65
7354 static offsetT
unrelaxed_frag_max_size (fragS
*);
7357 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
7359 const expressionS
*expr
= &tinsn
->tok
[1];
7360 symbolS
*symbolP
= expr
->X_add_symbol
;
7361 offsetT max_distance
= expr
->X_add_number
;
7364 if (expr
->X_op
!= O_symbol
)
7367 target_frag
= symbol_get_frag (symbolP
);
7369 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
7370 if (is_branch_jmp_to_next (tinsn
, fragP
))
7373 /* The branch doesn't branch over it's own frag,
7374 but over the subsequent ones. */
7375 fragP
= fragP
->fr_next
;
7376 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
7378 max_distance
+= unrelaxed_frag_max_size (fragP
);
7379 fragP
= fragP
->fr_next
;
7381 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
7388 xtensa_mark_zcl_first_insns (void)
7393 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7394 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7397 /* Walk over all of the fragments in a subsection. */
7398 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7400 if (fragP
->fr_type
== rs_machine_dependent
7401 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7402 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7404 /* Find the loop frag. */
7405 fragS
*targ_frag
= next_non_empty_frag (fragP
);
7406 /* Find the first insn frag. */
7407 targ_frag
= next_non_empty_frag (targ_frag
);
7409 /* Of course, sometimes (mostly for toy test cases) a
7410 zero-cost loop instruction is the last in a section. */
7413 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
7414 /* Do not widen a frag that is the first instruction of a
7415 zero-cost loop. It makes that loop harder to align. */
7416 if (targ_frag
->fr_type
== rs_machine_dependent
7417 && targ_frag
->fr_subtype
== RELAX_SLOTS
7418 && (targ_frag
->tc_frag_data
.slot_subtypes
[0]
7421 if (targ_frag
->tc_frag_data
.is_aligning_branch
)
7422 targ_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
7425 frag_wane (targ_frag
);
7426 targ_frag
->tc_frag_data
.slot_subtypes
[0] = 0;
7430 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
7438 /* When a difference-of-symbols expression is encoded as a uleb128 or
7439 sleb128 value, the linker is unable to adjust that value to account for
7440 link-time relaxation. Mark all the code between such symbols so that
7441 its size cannot be changed by linker relaxation. */
7444 xtensa_mark_difference_of_two_symbols (void)
7448 for (expr_sym
= expr_symbols
; expr_sym
;
7449 expr_sym
= symbol_get_tc (expr_sym
)->next_expr_symbol
)
7451 expressionS
*expr
= symbol_get_value_expression (expr_sym
);
7453 if (expr
->X_op
== O_subtract
)
7455 symbolS
*left
= expr
->X_add_symbol
;
7456 symbolS
*right
= expr
->X_op_symbol
;
7458 /* Difference of two symbols not in the same section
7459 are handled with relocations in the linker. */
7460 if (S_GET_SEGMENT (left
) == S_GET_SEGMENT (right
))
7466 if (symbol_get_frag (left
)->fr_address
7467 <= symbol_get_frag (right
)->fr_address
)
7469 start
= symbol_get_frag (left
);
7470 end
= symbol_get_frag (right
);
7474 start
= symbol_get_frag (right
);
7475 end
= symbol_get_frag (left
);
7478 if (start
->tc_frag_data
.no_transform_end
!= NULL
)
7479 walk
= start
->tc_frag_data
.no_transform_end
;
7484 walk
->tc_frag_data
.is_no_transform
= 1;
7485 walk
= walk
->fr_next
;
7487 while (walk
&& walk
->fr_address
< end
->fr_address
);
7489 start
->tc_frag_data
.no_transform_end
= walk
;
7496 /* Re-process all of the fragments looking to convert all of the
7497 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7498 conditional branch or a retw/retw.n, convert this frag to one that
7499 will generate a NOP. In any case close it off with a .fill 0. */
7501 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
7504 xtensa_fix_a0_b_retw_frags (void)
7509 /* When this routine is called, all of the subsections are still intact
7510 so we walk over subsections instead of sections. */
7511 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7512 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7516 /* Walk over all of the fragments in a subsection. */
7517 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7519 if (fragP
->fr_type
== rs_machine_dependent
7520 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
7522 if (next_instrs_are_b_retw (fragP
))
7524 if (fragP
->tc_frag_data
.is_no_transform
)
7525 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7527 relax_frag_add_nop (fragP
);
7537 next_instrs_are_b_retw (fragS
*fragP
)
7539 xtensa_opcode opcode
;
7541 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
7542 static xtensa_insnbuf insnbuf
= NULL
;
7543 static xtensa_insnbuf slotbuf
= NULL
;
7544 xtensa_isa isa
= xtensa_default_isa
;
7547 bfd_boolean branch_seen
= FALSE
;
7551 insnbuf
= xtensa_insnbuf_alloc (isa
);
7552 slotbuf
= xtensa_insnbuf_alloc (isa
);
7555 if (next_fragP
== NULL
)
7558 /* Check for the conditional branch. */
7559 xtensa_insnbuf_from_chars
7560 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7561 fmt
= xtensa_format_decode (isa
, insnbuf
);
7562 if (fmt
== XTENSA_UNDEFINED
)
7565 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7567 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
7568 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
7570 branch_seen
= (branch_seen
7571 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
7577 offset
+= xtensa_format_length (isa
, fmt
);
7578 if (offset
== next_fragP
->fr_fix
)
7580 next_fragP
= next_non_empty_frag (next_fragP
);
7584 if (next_fragP
== NULL
)
7587 /* Check for the retw/retw.n. */
7588 xtensa_insnbuf_from_chars
7589 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7590 fmt
= xtensa_format_decode (isa
, insnbuf
);
7592 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
7593 have no problems. */
7594 if (fmt
== XTENSA_UNDEFINED
7595 || xtensa_format_num_slots (isa
, fmt
) != 1)
7598 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
7599 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
7601 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
7608 /* Re-process all of the fragments looking to convert all of the
7609 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
7610 loop end label, convert this frag to one that will generate a NOP.
7611 In any case close it off with a .fill 0. */
7613 static bfd_boolean
next_instr_is_loop_end (fragS
*);
7616 xtensa_fix_b_j_loop_end_frags (void)
7621 /* When this routine is called, all of the subsections are still intact
7622 so we walk over subsections instead of sections. */
7623 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7624 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7628 /* Walk over all of the fragments in a subsection. */
7629 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7631 if (fragP
->fr_type
== rs_machine_dependent
7632 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
7634 if (next_instr_is_loop_end (fragP
))
7636 if (fragP
->tc_frag_data
.is_no_transform
)
7637 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
7639 relax_frag_add_nop (fragP
);
7649 next_instr_is_loop_end (fragS
*fragP
)
7651 const fragS
*next_fragP
;
7653 if (next_frag_is_loop_target (fragP
))
7656 next_fragP
= next_non_empty_frag (fragP
);
7657 if (next_fragP
== NULL
)
7660 if (!next_frag_is_loop_target (next_fragP
))
7663 /* If the size is >= 3 then there is more than one instruction here.
7664 The hardware bug will not fire. */
7665 if (next_fragP
->fr_fix
> 3)
7672 /* Re-process all of the fragments looking to convert all of the
7673 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
7674 not MY loop's loop end within 12 bytes, add enough nops here to
7675 make it at least 12 bytes away. In any case close it off with a
7678 static offsetT min_bytes_to_other_loop_end
7679 (fragS
*, fragS
*, offsetT
);
7682 xtensa_fix_close_loop_end_frags (void)
7687 /* When this routine is called, all of the subsections are still intact
7688 so we walk over subsections instead of sections. */
7689 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7690 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7694 fragS
*current_target
= NULL
;
7696 /* Walk over all of the fragments in a subsection. */
7697 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7699 if (fragP
->fr_type
== rs_machine_dependent
7700 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7701 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7702 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7705 && fragP
->fr_type
== rs_machine_dependent
7706 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
7709 int bytes_added
= 0;
7711 #define REQUIRED_LOOP_DIVIDING_BYTES 12
7712 /* Max out at 12. */
7713 min_bytes
= min_bytes_to_other_loop_end
7714 (fragP
->fr_next
, current_target
, REQUIRED_LOOP_DIVIDING_BYTES
);
7716 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
7718 if (fragP
->tc_frag_data
.is_no_transform
)
7719 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
7722 while (min_bytes
+ bytes_added
7723 < REQUIRED_LOOP_DIVIDING_BYTES
)
7727 if (fragP
->fr_var
< length
)
7728 as_fatal (_("fr_var %lu < length %d"),
7729 (long) fragP
->fr_var
, length
);
7732 assemble_nop (length
,
7733 fragP
->fr_literal
+ fragP
->fr_fix
);
7734 fragP
->fr_fix
+= length
;
7735 fragP
->fr_var
-= length
;
7737 bytes_added
+= length
;
7743 gas_assert (fragP
->fr_type
!= rs_machine_dependent
7744 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
7750 static offsetT
unrelaxed_frag_min_size (fragS
*);
7753 min_bytes_to_other_loop_end (fragS
*fragP
,
7754 fragS
*current_target
,
7758 fragS
*current_fragP
;
7760 for (current_fragP
= fragP
;
7762 current_fragP
= current_fragP
->fr_next
)
7764 if (current_fragP
->tc_frag_data
.is_loop_target
7765 && current_fragP
!= current_target
)
7768 offset
+= unrelaxed_frag_min_size (current_fragP
);
7770 if (offset
>= max_size
)
7778 unrelaxed_frag_min_size (fragS
*fragP
)
7780 offsetT size
= fragP
->fr_fix
;
7782 /* Add fill size. */
7783 if (fragP
->fr_type
== rs_fill
)
7784 size
+= fragP
->fr_offset
;
7791 unrelaxed_frag_max_size (fragS
*fragP
)
7793 offsetT size
= fragP
->fr_fix
;
7794 switch (fragP
->fr_type
)
7797 /* Empty frags created by the obstack allocation scheme
7798 end up with type 0. */
7803 size
+= fragP
->fr_offset
;
7811 /* No further adjustments needed. */
7813 case rs_machine_dependent
:
7814 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
7815 size
+= fragP
->fr_var
;
7818 /* We had darn well better know how big it is. */
7827 /* Re-process all of the fragments looking to convert all
7828 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
7831 1) the instruction size count to the loop end label
7832 is too short (<= 2 instructions),
7833 2) loop has a jump or branch in it
7836 1) workaround_all_short_loops is TRUE
7837 2) The generating loop was a 'loopgtz' or 'loopnez'
7838 3) the instruction size count to the loop end label is too short
7840 then convert this frag (and maybe the next one) to generate a NOP.
7841 In any case close it off with a .fill 0. */
7843 static int count_insns_to_loop_end (fragS
*, bfd_boolean
, int);
7844 static bfd_boolean
branch_before_loop_end (fragS
*);
7847 xtensa_fix_short_loop_frags (void)
7852 /* When this routine is called, all of the subsections are still intact
7853 so we walk over subsections instead of sections. */
7854 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7855 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7858 fragS
*current_target
= NULL
;
7859 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
7861 /* Walk over all of the fragments in a subsection. */
7862 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7864 if (fragP
->fr_type
== rs_machine_dependent
7865 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7866 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7869 fragS
*loop_frag
= next_non_empty_frag (fragP
);
7870 tinsn_from_chars (&t_insn
, loop_frag
->fr_opcode
, 0);
7871 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7872 current_opcode
= t_insn
.opcode
;
7873 gas_assert (xtensa_opcode_is_loop (xtensa_default_isa
,
7874 current_opcode
) == 1);
7877 if (fragP
->fr_type
== rs_machine_dependent
7878 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7880 if (count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3) < 3
7881 && (branch_before_loop_end (fragP
->fr_next
)
7882 || (workaround_all_short_loops
7883 && current_opcode
!= XTENSA_UNDEFINED
7884 && current_opcode
!= xtensa_loop_opcode
)))
7886 if (fragP
->tc_frag_data
.is_no_transform
)
7887 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
7889 relax_frag_add_nop (fragP
);
7898 static int unrelaxed_frag_min_insn_count (fragS
*);
7901 count_insns_to_loop_end (fragS
*base_fragP
,
7902 bfd_boolean count_relax_add
,
7905 fragS
*fragP
= NULL
;
7910 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
7912 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
7913 if (insn_count
>= max_count
)
7916 if (count_relax_add
)
7918 if (fragP
->fr_type
== rs_machine_dependent
7919 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7921 /* In order to add the appropriate number of
7922 NOPs, we count an instruction for downstream
7925 if (insn_count
>= max_count
)
7935 unrelaxed_frag_min_insn_count (fragS
*fragP
)
7937 xtensa_isa isa
= xtensa_default_isa
;
7938 static xtensa_insnbuf insnbuf
= NULL
;
7942 if (!fragP
->tc_frag_data
.is_insn
)
7946 insnbuf
= xtensa_insnbuf_alloc (isa
);
7948 /* Decode the fixed instructions. */
7949 while (offset
< fragP
->fr_fix
)
7953 xtensa_insnbuf_from_chars
7954 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7955 fmt
= xtensa_format_decode (isa
, insnbuf
);
7957 if (fmt
== XTENSA_UNDEFINED
)
7959 as_fatal (_("undecodable instruction in instruction frag"));
7962 offset
+= xtensa_format_length (isa
, fmt
);
7970 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
7973 branch_before_loop_end (fragS
*base_fragP
)
7977 for (fragP
= base_fragP
;
7978 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
7979 fragP
= fragP
->fr_next
)
7981 if (unrelaxed_frag_has_b_j (fragP
))
7989 unrelaxed_frag_has_b_j (fragS
*fragP
)
7991 static xtensa_insnbuf insnbuf
= NULL
;
7992 xtensa_isa isa
= xtensa_default_isa
;
7995 if (!fragP
->tc_frag_data
.is_insn
)
7999 insnbuf
= xtensa_insnbuf_alloc (isa
);
8001 /* Decode the fixed instructions. */
8002 while (offset
< fragP
->fr_fix
)
8007 xtensa_insnbuf_from_chars
8008 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
8009 fmt
= xtensa_format_decode (isa
, insnbuf
);
8010 if (fmt
== XTENSA_UNDEFINED
)
8013 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
8015 xtensa_opcode opcode
=
8016 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
8017 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
8018 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
8021 offset
+= xtensa_format_length (isa
, fmt
);
8027 /* Checks to be made after initial assembly but before relaxation. */
8029 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
8030 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
8033 xtensa_sanity_check (void)
8040 as_where (&file_name
, &line
);
8041 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8042 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8046 /* Walk over all of the fragments in a subsection. */
8047 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8049 if (fragP
->fr_type
== rs_machine_dependent
8050 && fragP
->fr_subtype
== RELAX_SLOTS
8051 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
8053 static xtensa_insnbuf insnbuf
= NULL
;
8056 if (fragP
->fr_opcode
!= NULL
)
8059 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
8060 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
8061 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
8063 if (xtensa_opcode_is_loop (xtensa_default_isa
,
8064 t_insn
.opcode
) == 1)
8066 if (is_empty_loop (&t_insn
, fragP
))
8068 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8069 as_bad (_("invalid empty loop"));
8071 if (!is_local_forward_loop (&t_insn
, fragP
))
8073 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8074 as_bad (_("loop target does not follow "
8075 "loop instruction in section"));
8082 new_logical_line (file_name
, line
);
8086 #define LOOP_IMMED_OPN 1
8088 /* Return TRUE if the loop target is the next non-zero fragment. */
8091 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
8093 const expressionS
*expr
;
8097 if (insn
->insn_type
!= ITYPE_INSN
)
8100 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
8103 if (insn
->ntok
<= LOOP_IMMED_OPN
)
8106 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
8108 if (expr
->X_op
!= O_symbol
)
8111 symbolP
= expr
->X_add_symbol
;
8115 if (symbol_get_frag (symbolP
) == NULL
)
8118 if (S_GET_VALUE (symbolP
) != 0)
8121 /* Walk through the zero-size fragments from this one. If we find
8122 the target fragment, then this is a zero-size loop. */
8124 for (next_fragP
= fragP
->fr_next
;
8126 next_fragP
= next_fragP
->fr_next
)
8128 if (next_fragP
== symbol_get_frag (symbolP
))
8130 if (next_fragP
->fr_fix
!= 0)
8138 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
8140 const expressionS
*expr
;
8144 if (insn
->insn_type
!= ITYPE_INSN
)
8147 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
8150 if (insn
->ntok
<= LOOP_IMMED_OPN
)
8153 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
8155 if (expr
->X_op
!= O_symbol
)
8158 symbolP
= expr
->X_add_symbol
;
8162 if (symbol_get_frag (symbolP
) == NULL
)
8165 /* Walk through fragments until we find the target.
8166 If we do not find the target, then this is an invalid loop. */
8168 for (next_fragP
= fragP
->fr_next
;
8170 next_fragP
= next_fragP
->fr_next
)
8172 if (next_fragP
== symbol_get_frag (symbolP
))
8180 #define XTINFO_NAME "Xtensa_Info"
8181 #define XTINFO_NAMESZ 12
8182 #define XTINFO_TYPE 1
8185 xtensa_add_config_info (void)
8191 info_sec
= subseg_new (".xtensa.info", 0);
8192 bfd_set_section_flags (stdoutput
, info_sec
, SEC_HAS_CONTENTS
| SEC_READONLY
);
8194 data
= xmalloc (100);
8195 sprintf (data
, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n",
8196 XSHAL_USE_ABSOLUTE_LITERALS
, XSHAL_ABI
);
8197 sz
= strlen (data
) + 1;
8199 /* Add enough null terminators to pad to a word boundary. */
8202 while ((sz
& 3) != 0);
8204 /* Follow the standard note section layout:
8205 First write the length of the name string. */
8207 md_number_to_chars (p
, (valueT
) XTINFO_NAMESZ
, 4);
8209 /* Next comes the length of the "descriptor", i.e., the actual data. */
8211 md_number_to_chars (p
, (valueT
) sz
, 4);
8213 /* Write the note type. */
8215 md_number_to_chars (p
, (valueT
) XTINFO_TYPE
, 4);
8217 /* Write the name field. */
8218 p
= frag_more (XTINFO_NAMESZ
);
8219 memcpy (p
, XTINFO_NAME
, XTINFO_NAMESZ
);
8221 /* Finally, write the descriptor. */
8223 memcpy (p
, data
, sz
);
8229 /* Alignment Functions. */
8232 get_text_align_power (unsigned target_size
)
8234 if (target_size
<= 4)
8236 gas_assert (target_size
== 8);
8242 get_text_align_max_fill_size (int align_pow
,
8243 bfd_boolean use_nops
,
8244 bfd_boolean use_no_density
)
8247 return (1 << align_pow
);
8249 return 3 * (1 << align_pow
);
8251 return 1 + (1 << align_pow
);
8255 /* Calculate the minimum bytes of fill needed at "address" to align a
8256 target instruction of size "target_size" so that it does not cross a
8257 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE,
8258 the fill can be an arbitrary number of bytes. Otherwise, the space must
8259 be filled by NOP instructions. */
8262 get_text_align_fill_size (addressT address
,
8265 bfd_boolean use_nops
,
8266 bfd_boolean use_no_density
)
8268 addressT alignment
, fill
, fill_limit
, fill_step
;
8269 bfd_boolean skip_one
= FALSE
;
8271 alignment
= (1 << align_pow
);
8272 gas_assert (target_size
> 0 && alignment
>= (addressT
) target_size
);
8276 fill_limit
= alignment
;
8279 else if (!use_no_density
)
8281 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */
8282 fill_limit
= alignment
* 2;
8288 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */
8289 fill_limit
= alignment
* 3;
8293 /* Try all fill sizes until finding one that works. */
8294 for (fill
= 0; fill
< fill_limit
; fill
+= fill_step
)
8296 if (skip_one
&& fill
== 1)
8298 if ((address
+ fill
) >> align_pow
8299 == (address
+ fill
+ target_size
- 1) >> align_pow
)
8308 branch_align_power (segT sec
)
8310 /* If the Xtensa processor has a fetch width of 8 bytes, and the section
8311 is aligned to at least an 8-byte boundary, then a branch target need
8312 only fit within an 8-byte aligned block of memory to avoid a stall.
8313 Otherwise, try to fit branch targets within 4-byte aligned blocks
8314 (which may be insufficient, e.g., if the section has no alignment, but
8315 it's good enough). */
8316 if (xtensa_fetch_width
== 8)
8318 if (get_recorded_alignment (sec
) >= 3)
8322 gas_assert (xtensa_fetch_width
== 4);
8328 /* This will assert if it is not possible. */
8331 get_text_align_nop_count (offsetT fill_size
, bfd_boolean use_no_density
)
8337 gas_assert (fill_size
% 3 == 0);
8338 return (fill_size
/ 3);
8341 gas_assert (fill_size
!= 1); /* Bad argument. */
8343 while (fill_size
> 1)
8346 if (fill_size
== 2 || fill_size
== 4)
8348 fill_size
-= insn_size
;
8351 gas_assert (fill_size
!= 1); /* Bad algorithm. */
8357 get_text_align_nth_nop_size (offsetT fill_size
,
8359 bfd_boolean use_no_density
)
8366 gas_assert (fill_size
!= 1); /* Bad argument. */
8368 while (fill_size
> 1)
8371 if (fill_size
== 2 || fill_size
== 4)
8373 fill_size
-= insn_size
;
8383 /* For the given fragment, find the appropriate address
8384 for it to begin at if we are using NOPs to align it. */
8387 get_noop_aligned_address (fragS
*fragP
, addressT address
)
8389 /* The rule is: get next fragment's FIRST instruction. Find
8390 the smallest number of bytes that need to be added to
8391 ensure that the next fragment's FIRST instruction will fit
8394 E.G., 2 bytes : 0, 1, 2 mod 4
8397 If the FIRST instruction MIGHT be relaxed,
8398 assume that it will become a 3-byte instruction.
8400 Note again here that LOOP instructions are not bundleable,
8401 and this relaxation only applies to LOOP opcodes. */
8404 int first_insn_size
;
8406 addressT pre_opcode_bytes
;
8409 xtensa_opcode opcode
;
8410 bfd_boolean is_loop
;
8412 gas_assert (fragP
->fr_type
== rs_machine_dependent
);
8413 gas_assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
8415 /* Find the loop frag. */
8416 first_insn
= next_non_empty_frag (fragP
);
8417 /* Now find the first insn frag. */
8418 first_insn
= next_non_empty_frag (first_insn
);
8420 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
8421 gas_assert (is_loop
);
8422 loop_insn_size
= xg_get_single_size (opcode
);
8424 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
8425 pre_opcode_bytes
+= loop_insn_size
;
8427 /* For loops, the alignment depends on the size of the
8428 instruction following the loop, not the LOOP instruction. */
8430 if (first_insn
== NULL
)
8431 first_insn_size
= xtensa_fetch_width
;
8433 first_insn_size
= get_loop_align_size (frag_format_size (first_insn
));
8435 /* If it was 8, then we'll need a larger alignment for the section. */
8436 align_power
= get_text_align_power (first_insn_size
);
8437 record_alignment (now_seg
, align_power
);
8439 fill_size
= get_text_align_fill_size
8440 (address
+ pre_opcode_bytes
, align_power
, first_insn_size
, TRUE
,
8441 fragP
->tc_frag_data
.is_no_density
);
8443 return address
+ fill_size
;
8447 /* 3 mechanisms for relaxing an alignment:
8449 Align to a power of 2.
8450 Align so the next fragment's instruction does not cross a word boundary.
8451 Align the current instruction so that if the next instruction
8452 were 3 bytes, it would not cross a word boundary.
8456 zeros - This is easy; always insert zeros.
8457 nops - 3-byte and 2-byte instructions
8461 >=5 : 3-byte instruction + fn (n-3)
8462 widening - widen previous instructions. */
8465 get_aligned_diff (fragS
*fragP
, addressT address
, offsetT
*max_diff
)
8467 addressT target_address
, loop_insn_offset
;
8469 xtensa_opcode loop_opcode
;
8470 bfd_boolean is_loop
;
8473 offsetT branch_align
;
8476 gas_assert (fragP
->fr_type
== rs_machine_dependent
);
8477 switch (fragP
->fr_subtype
)
8479 case RELAX_DESIRE_ALIGN
:
8480 target_size
= next_frag_format_size (fragP
);
8481 if (target_size
== XTENSA_UNDEFINED
)
8483 align_power
= branch_align_power (now_seg
);
8484 branch_align
= 1 << align_power
;
8485 /* Don't count on the section alignment being as large as the target. */
8486 if (target_size
> branch_align
)
8487 target_size
= branch_align
;
8488 opt_diff
= get_text_align_fill_size (address
, align_power
,
8489 target_size
, FALSE
, FALSE
);
8491 *max_diff
= (opt_diff
+ branch_align
8492 - (target_size
+ ((address
+ opt_diff
) % branch_align
)));
8493 gas_assert (*max_diff
>= opt_diff
);
8496 case RELAX_ALIGN_NEXT_OPCODE
:
8497 /* The next non-empty frag after this one holds the LOOP instruction
8498 that needs to be aligned. The required alignment depends on the
8499 size of the next non-empty frag after the loop frag, i.e., the
8500 first instruction in the loop. */
8501 loop_frag
= next_non_empty_frag (fragP
);
8502 target_size
= get_loop_align_size (next_frag_format_size (loop_frag
));
8503 loop_insn_offset
= 0;
8504 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
8505 gas_assert (is_loop
);
8507 /* If the loop has been expanded then the LOOP instruction
8508 could be at an offset from this fragment. */
8509 if (loop_frag
->tc_frag_data
.slot_subtypes
[0] != RELAX_IMMED
)
8510 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
8512 /* In an ideal world, which is what we are shooting for here,
8513 we wouldn't need to use any NOPs immediately prior to the
8514 LOOP instruction. If this approach fails, relax_frag_loop_align
8515 will call get_noop_aligned_address. */
8517 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
8518 align_power
= get_text_align_power (target_size
);
8519 opt_diff
= get_text_align_fill_size (target_address
, align_power
,
8520 target_size
, FALSE
, FALSE
);
8522 *max_diff
= xtensa_fetch_width
8523 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
8524 - target_size
+ opt_diff
;
8525 gas_assert (*max_diff
>= opt_diff
);
8536 /* md_relax_frag Hook and Helper Functions. */
8538 static long relax_frag_loop_align (fragS
*, long);
8539 static long relax_frag_for_align (fragS
*, long);
8540 static long relax_frag_immed
8541 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
8544 /* Return the number of bytes added to this fragment, given that the
8545 input has been stretched already by "stretch". */
8548 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
8550 xtensa_isa isa
= xtensa_default_isa
;
8551 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
8552 long new_stretch
= 0;
8556 static xtensa_insnbuf vbuf
= NULL
;
8557 int slot
, num_slots
;
8560 as_where (&file_name
, &line
);
8561 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8563 fragP
->tc_frag_data
.unreported_expansion
= 0;
8565 switch (fragP
->fr_subtype
)
8567 case RELAX_ALIGN_NEXT_OPCODE
:
8568 /* Always convert. */
8569 if (fragP
->tc_frag_data
.relax_seen
)
8570 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
8573 case RELAX_LOOP_END
:
8577 case RELAX_LOOP_END_ADD_NOP
:
8578 /* Add a NOP and switch to .fill 0. */
8579 new_stretch
= relax_frag_add_nop (fragP
);
8583 case RELAX_DESIRE_ALIGN
:
8584 /* Do nothing. The narrowing before this frag will either align
8589 case RELAX_LITERAL_FINAL
:
8592 case RELAX_LITERAL_NR
:
8594 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
8595 gas_assert (unreported
== lit_size
);
8596 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
8597 fragP
->fr_var
-= lit_size
;
8598 fragP
->fr_fix
+= lit_size
;
8604 vbuf
= xtensa_insnbuf_alloc (isa
);
8606 xtensa_insnbuf_from_chars
8607 (isa
, vbuf
, (unsigned char *) fragP
->fr_opcode
, 0);
8608 fmt
= xtensa_format_decode (isa
, vbuf
);
8609 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8611 for (slot
= 0; slot
< num_slots
; slot
++)
8613 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
8616 if (fragP
->tc_frag_data
.relax_seen
)
8617 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8621 case RELAX_IMMED_STEP1
:
8622 case RELAX_IMMED_STEP2
:
8623 case RELAX_IMMED_STEP3
:
8624 /* Place the immediate. */
8625 new_stretch
+= relax_frag_immed
8626 (now_seg
, fragP
, stretch
,
8627 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8628 fmt
, slot
, stretched_p
, FALSE
);
8632 /* This is OK; see the note in xg_assemble_vliw_tokens. */
8638 case RELAX_LITERAL_POOL_BEGIN
:
8639 case RELAX_LITERAL_POOL_END
:
8640 case RELAX_MAYBE_UNREACHABLE
:
8641 case RELAX_MAYBE_DESIRE_ALIGN
:
8642 /* No relaxation required. */
8645 case RELAX_FILL_NOP
:
8646 case RELAX_UNREACHABLE
:
8647 if (fragP
->tc_frag_data
.relax_seen
)
8648 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8652 as_bad (_("bad relaxation state"));
8655 /* Tell gas we need another relaxation pass. */
8656 if (! fragP
->tc_frag_data
.relax_seen
)
8658 fragP
->tc_frag_data
.relax_seen
= TRUE
;
8662 new_logical_line (file_name
, line
);
8668 relax_frag_loop_align (fragS
*fragP
, long stretch
)
8670 addressT old_address
, old_next_address
, old_size
;
8671 addressT new_address
, new_next_address
, new_size
;
8674 /* All the frags with relax_frag_for_alignment prior to this one in the
8675 section have been done, hopefully eliminating the need for a NOP here.
8676 But, this will put it in if necessary. */
8678 /* Calculate the old address of this fragment and the next fragment. */
8679 old_address
= fragP
->fr_address
- stretch
;
8680 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
8681 fragP
->tc_frag_data
.text_expansion
[0]);
8682 old_size
= old_next_address
- old_address
;
8684 /* Calculate the new address of this fragment and the next fragment. */
8685 new_address
= fragP
->fr_address
;
8687 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
8688 new_size
= new_next_address
- new_address
;
8690 growth
= new_size
- old_size
;
8692 /* Fix up the text_expansion field and return the new growth. */
8693 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
8698 /* Add a NOP instruction. */
8701 relax_frag_add_nop (fragS
*fragP
)
8703 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
8704 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
8705 assemble_nop (length
, nop_buf
);
8706 fragP
->tc_frag_data
.is_insn
= TRUE
;
8708 if (fragP
->fr_var
< length
)
8710 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP
->fr_var
, length
);
8714 fragP
->fr_fix
+= length
;
8715 fragP
->fr_var
-= length
;
8720 static long future_alignment_required (fragS
*, long);
8723 relax_frag_for_align (fragS
*fragP
, long stretch
)
8725 /* Overview of the relaxation procedure for alignment:
8726 We can widen with NOPs or by widening instructions or by filling
8727 bytes after jump instructions. Find the opportune places and widen
8728 them if necessary. */
8733 gas_assert (fragP
->fr_subtype
== RELAX_FILL_NOP
8734 || fragP
->fr_subtype
== RELAX_UNREACHABLE
8735 || (fragP
->fr_subtype
== RELAX_SLOTS
8736 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
8738 stretch_me
= future_alignment_required (fragP
, stretch
);
8739 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
8745 /* We expanded on a previous pass. Can we shrink now? */
8746 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
8747 if (shrink
<= stretch
&& stretch
> 0)
8749 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8755 /* Below here, diff > 0. */
8756 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8762 /* Return the address of the next frag that should be aligned.
8764 By "address" we mean the address it _would_ be at if there
8765 is no action taken to align it between here and the target frag.
8766 In other words, if no narrows and no fill nops are used between
8767 here and the frag to align, _even_if_ some of the frags we use
8768 to align targets have already expanded on a previous relaxation
8771 Also, count each frag that may be used to help align the target.
8773 Return 0 if there are no frags left in the chain that need to be
8777 find_address_of_next_align_frag (fragS
**fragPP
,
8781 bfd_boolean
*paddable
)
8783 fragS
*fragP
= *fragPP
;
8784 addressT address
= fragP
->fr_address
;
8786 /* Do not reset the counts to 0. */
8790 /* Limit this to a small search. */
8791 if (*widens
>= (int) xtensa_fetch_width
)
8796 address
+= fragP
->fr_fix
;
8798 if (fragP
->fr_type
== rs_fill
)
8799 address
+= fragP
->fr_offset
* fragP
->fr_var
;
8800 else if (fragP
->fr_type
== rs_machine_dependent
)
8802 switch (fragP
->fr_subtype
)
8804 case RELAX_UNREACHABLE
:
8808 case RELAX_FILL_NOP
:
8810 if (!fragP
->tc_frag_data
.is_no_density
)
8815 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8820 address
+= total_frag_text_expansion (fragP
);;
8824 address
+= fragP
->tc_frag_data
.text_expansion
[0];
8827 case RELAX_ALIGN_NEXT_OPCODE
:
8828 case RELAX_DESIRE_ALIGN
:
8832 case RELAX_MAYBE_UNREACHABLE
:
8833 case RELAX_MAYBE_DESIRE_ALIGN
:
8838 /* Just punt if we don't know the type. */
8845 /* Just punt if we don't know the type. */
8849 fragP
= fragP
->fr_next
;
8857 static long bytes_to_stretch (fragS
*, int, int, int, int);
8860 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
8862 fragS
*this_frag
= fragP
;
8866 int narrow_nops
= 0;
8867 bfd_boolean paddable
= FALSE
;
8868 offsetT local_opt_diff
;
8871 int stretch_amount
= 0;
8872 int local_stretch_amount
;
8873 int global_stretch_amount
;
8875 address
= find_address_of_next_align_frag
8876 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
8880 if (this_frag
->tc_frag_data
.is_aligning_branch
)
8881 this_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
8883 frag_wane (this_frag
);
8887 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
8888 opt_diff
= local_opt_diff
;
8889 gas_assert (opt_diff
>= 0);
8890 gas_assert (max_diff
>= opt_diff
);
8895 fragP
= fragP
->fr_next
;
8897 while (fragP
&& opt_diff
< max_diff
&& address
)
8899 /* We only use these to determine if we can exit early
8900 because there will be plenty of ways to align future
8902 int glob_widens
= 0;
8905 bfd_boolean glob_pad
= 0;
8906 address
= find_address_of_next_align_frag
8907 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
8908 /* If there is a padable portion, then skip. */
8909 if (glob_pad
|| glob_widens
>= (1 << branch_align_power (now_seg
)))
8914 offsetT next_m_diff
;
8915 offsetT next_o_diff
;
8917 /* Downrange frags haven't had stretch added to them yet. */
8920 /* The address also includes any text expansion from this
8921 frag in a previous pass, but we don't want that. */
8922 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
8924 /* Assume we are going to move at least opt_diff. In
8925 reality, we might not be able to, but assuming that
8926 we will helps catch cases where moving opt_diff pushes
8927 the next target from aligned to unaligned. */
8928 address
+= opt_diff
;
8930 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
8932 /* Now cleanup for the adjustments to address. */
8933 next_o_diff
+= opt_diff
;
8934 next_m_diff
+= opt_diff
;
8935 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
8936 opt_diff
= next_o_diff
;
8937 if (next_m_diff
< max_diff
)
8938 max_diff
= next_m_diff
;
8939 fragP
= fragP
->fr_next
;
8943 /* If there are enough wideners in between, do it. */
8946 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
8948 gas_assert (opt_diff
<= UNREACHABLE_MAX_WIDTH
);
8953 local_stretch_amount
8954 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8955 num_widens
, local_opt_diff
);
8956 global_stretch_amount
8957 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8958 num_widens
, opt_diff
);
8959 /* If the condition below is true, then the frag couldn't
8960 stretch the correct amount for the global case, so we just
8961 optimize locally. We'll rely on the subsequent frags to get
8962 the correct alignment in the global case. */
8963 if (global_stretch_amount
< local_stretch_amount
)
8964 stretch_amount
= local_stretch_amount
;
8966 stretch_amount
= global_stretch_amount
;
8968 if (this_frag
->fr_subtype
== RELAX_SLOTS
8969 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8970 gas_assert (stretch_amount
<= 1);
8971 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8973 if (this_frag
->tc_frag_data
.is_no_density
)
8974 gas_assert (stretch_amount
== 3 || stretch_amount
== 0);
8976 gas_assert (stretch_amount
<= 3);
8979 return stretch_amount
;
8983 /* The idea: widen everything you can to get a target or loop aligned,
8984 then start using NOPs.
8986 When we must have a NOP, here is a table of how we decide
8987 (so you don't have to fight through the control flow below):
8989 wide_nops = the number of wide NOPs available for aligning
8990 narrow_nops = the number of narrow NOPs available for aligning
8991 (a subset of wide_nops)
8992 widens = the number of narrow instructions that should be widened
8999 b 0 1 1 (case 3a makes this case unnecessary)
9002 c 0 1 2 (case 4a makes this case unnecessary)
9005 c 0 2 1 (case 5b makes this case unnecessary)
9008 c 0 1 4 (case 6b makes this case unnecessary)
9009 d 1 1 1 (case 6a makes this case unnecessary)
9010 e 0 2 2 (case 6a makes this case unnecessary)
9011 f 0 3 0 (case 6a makes this case unnecessary)
9014 c 1 1 2 (case 7b makes this case unnecessary)
9015 d 0 1 5 (case 7a makes this case unnecessary)
9016 e 0 2 3 (case 7b makes this case unnecessary)
9017 f 0 3 1 (case 7b makes this case unnecessary)
9018 g 1 2 1 (case 7b makes this case unnecessary)
9022 bytes_to_stretch (fragS
*this_frag
,
9028 int bytes_short
= desired_diff
- num_widens
;
9030 gas_assert (desired_diff
>= 0 && desired_diff
< 8);
9031 if (desired_diff
== 0)
9034 gas_assert (wide_nops
> 0 || num_widens
> 0);
9036 /* Always prefer widening to NOP-filling. */
9037 if (bytes_short
< 0)
9039 /* There are enough RELAX_NARROW frags after this one
9040 to align the target without widening this frag in any way. */
9044 if (bytes_short
== 0)
9046 /* Widen every narrow between here and the align target
9047 and the align target will be properly aligned. */
9048 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9054 /* From here we will need at least one NOP to get an alignment.
9055 However, we may not be able to align at all, in which case,
9057 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9059 switch (desired_diff
)
9064 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 1)
9065 return 2; /* case 2 */
9071 return 3; /* case 3a */
9073 if (num_widens
>= 1 && wide_nops
== 1)
9074 return 3; /* case 4a */
9075 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 2)
9076 return 2; /* case 4b */
9079 if (num_widens
>= 2 && wide_nops
== 1)
9080 return 3; /* case 5a */
9081 /* We will need two nops. Are there enough nops
9082 between here and the align target? */
9083 if (wide_nops
< 2 || narrow_nops
== 0)
9085 /* Are there other nops closer that can serve instead? */
9086 if (wide_nops
> 2 && narrow_nops
> 1)
9088 /* Take the density one first, because there might not be
9089 another density one available. */
9090 if (!this_frag
->tc_frag_data
.is_no_density
)
9091 return 2; /* case 5b narrow */
9093 return 3; /* case 5b wide */
9097 return 3; /* case 6a */
9098 else if (num_widens
>= 3 && wide_nops
== 1)
9099 return 3; /* case 6b */
9102 if (wide_nops
== 1 && num_widens
>= 4)
9103 return 3; /* case 7a */
9104 else if (wide_nops
== 2 && num_widens
>= 1)
9105 return 3; /* case 7b */
9113 /* We will need a NOP no matter what, but should we widen
9114 this instruction to help?
9116 This is a RELAX_NARROW frag. */
9117 switch (desired_diff
)
9126 if (wide_nops
>= 1 && num_widens
== 1)
9127 return 1; /* case 4a */
9130 if (wide_nops
>= 1 && num_widens
== 2)
9131 return 1; /* case 5a */
9135 return 0; /* case 6a */
9136 else if (wide_nops
>= 1 && num_widens
== 3)
9137 return 1; /* case 6b */
9140 if (wide_nops
>= 1 && num_widens
== 4)
9141 return 1; /* case 7a */
9142 else if (wide_nops
>= 2 && num_widens
== 1)
9143 return 1; /* case 7b */
9156 relax_frag_immed (segT segP
,
9163 bfd_boolean estimate_only
)
9167 bfd_boolean negatable_branch
= FALSE
;
9168 bfd_boolean branch_jmp_to_next
= FALSE
;
9169 bfd_boolean from_wide_insn
= FALSE
;
9170 xtensa_isa isa
= xtensa_default_isa
;
9172 offsetT frag_offset
;
9174 int num_text_bytes
, num_literal_bytes
;
9175 int literal_diff
, total_text_diff
, this_text_diff
;
9177 gas_assert (fragP
->fr_opcode
!= NULL
);
9179 xg_clear_vinsn (&cur_vinsn
);
9180 vinsn_from_chars (&cur_vinsn
, fragP
->fr_opcode
);
9181 if (cur_vinsn
.num_slots
> 1)
9182 from_wide_insn
= TRUE
;
9184 tinsn
= cur_vinsn
.slots
[slot
];
9185 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
9187 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
) == 1)
9190 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9191 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
9193 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
9195 old_size
= xtensa_format_length (isa
, fmt
);
9197 /* Special case: replace a branch to the next instruction with a NOP.
9198 This is required to work around a hardware bug in T1040.0 and also
9199 serves as an optimization. */
9201 if (branch_jmp_to_next
9202 && ((old_size
== 2) || (old_size
== 3))
9203 && !next_frag_is_loop_target (fragP
))
9206 /* Here is the fun stuff: Get the immediate field from this
9207 instruction. If it fits, we are done. If not, find the next
9208 instruction sequence that fits. */
9210 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9211 istack_init (&istack
);
9212 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
9213 min_steps
, stretch
);
9214 gas_assert (num_steps
>= min_steps
&& num_steps
<= RELAX_IMMED_MAXSTEPS
);
9216 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
9218 /* Figure out the number of bytes needed. */
9219 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
9221 = num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
9222 num_text_bytes
= get_num_stack_text_bytes (&istack
);
9227 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
9230 num_text_bytes
+= old_size
;
9231 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
9232 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
9235 /* The first instruction in the relaxed sequence will go after
9236 the current wide instruction, and thus its symbolic immediates
9239 istack_init (&istack
);
9240 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
,
9241 frag_offset
+ old_size
,
9242 min_steps
, stretch
+ old_size
);
9243 gas_assert (num_steps
>= min_steps
&& num_steps
<= RELAX_IMMED_MAXSTEPS
);
9245 fragP
->tc_frag_data
.slot_subtypes
[slot
]
9246 = (int) RELAX_IMMED
+ num_steps
;
9248 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
9250 = num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
9252 num_text_bytes
= get_num_stack_text_bytes (&istack
) + old_size
;
9256 total_text_diff
= num_text_bytes
- old_size
;
9257 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
9259 /* It MUST get larger. If not, we could get an infinite loop. */
9260 gas_assert (num_text_bytes
>= 0);
9261 gas_assert (literal_diff
>= 0);
9262 gas_assert (total_text_diff
>= 0);
9264 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
9265 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
9266 gas_assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
9267 gas_assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
9269 /* Find the associated expandable literal for this. */
9270 if (literal_diff
!= 0)
9272 fragS
*lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
9275 gas_assert (literal_diff
== 4);
9276 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
9278 /* We expect that the literal section state has NOT been
9280 gas_assert (lit_fragP
->fr_type
== rs_machine_dependent
9281 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
9282 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
9284 /* We need to mark this section for another iteration
9290 if (negatable_branch
&& istack
.ninsn
> 1)
9291 update_next_frag_state (fragP
);
9293 return this_text_diff
;
9297 /* md_convert_frag Hook and Helper Functions. */
9299 static void convert_frag_align_next_opcode (fragS
*);
9300 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
9301 static void convert_frag_fill_nop (fragS
*);
9302 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
9305 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
9307 static xtensa_insnbuf vbuf
= NULL
;
9308 xtensa_isa isa
= xtensa_default_isa
;
9315 as_where (&file_name
, &line
);
9316 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
9318 switch (fragp
->fr_subtype
)
9320 case RELAX_ALIGN_NEXT_OPCODE
:
9321 /* Always convert. */
9322 convert_frag_align_next_opcode (fragp
);
9325 case RELAX_DESIRE_ALIGN
:
9326 /* Do nothing. If not aligned already, too bad. */
9330 case RELAX_LITERAL_FINAL
:
9335 vbuf
= xtensa_insnbuf_alloc (isa
);
9337 xtensa_insnbuf_from_chars
9338 (isa
, vbuf
, (unsigned char *) fragp
->fr_opcode
, 0);
9339 fmt
= xtensa_format_decode (isa
, vbuf
);
9340 num_slots
= xtensa_format_num_slots (isa
, fmt
);
9342 for (slot
= 0; slot
< num_slots
; slot
++)
9344 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
9347 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
9351 case RELAX_IMMED_STEP1
:
9352 case RELAX_IMMED_STEP2
:
9353 case RELAX_IMMED_STEP3
:
9354 /* Place the immediate. */
9357 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
9362 /* This is OK because some slots could have
9363 relaxations and others have none. */
9369 case RELAX_UNREACHABLE
:
9370 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
9371 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
9372 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
9376 case RELAX_MAYBE_UNREACHABLE
:
9377 case RELAX_MAYBE_DESIRE_ALIGN
:
9381 case RELAX_FILL_NOP
:
9382 convert_frag_fill_nop (fragp
);
9385 case RELAX_LITERAL_NR
:
9386 if (use_literal_section
)
9388 /* This should have been handled during relaxation. When
9389 relaxing a code segment, literals sometimes need to be
9390 added to the corresponding literal segment. If that
9391 literal segment has already been relaxed, then we end up
9392 in this situation. Marking the literal segments as data
9393 would make this happen less often (since GAS always relaxes
9394 code before data), but we could still get into trouble if
9395 there are instructions in a segment that is not marked as
9396 containing code. Until we can implement a better solution,
9397 cheat and adjust the addresses of all the following frags.
9398 This could break subsequent alignments, but the linker's
9399 literal coalescing will do that anyway. */
9402 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
9403 gas_assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
9404 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
9407 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
9411 as_bad (_("invalid relaxation fragment result"));
9416 new_logical_line (file_name
, line
);
9421 convert_frag_align_next_opcode (fragS
*fragp
)
9423 char *nop_buf
; /* Location for Writing. */
9424 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
9425 addressT aligned_address
;
9429 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
9431 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
9432 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
9433 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
9435 for (nop
= 0; nop
< nop_count
; nop
++)
9438 nop_size
= get_text_align_nth_nop_size (fill_size
, nop
, use_no_density
);
9440 assemble_nop (nop_size
, nop_buf
);
9441 nop_buf
+= nop_size
;
9444 fragp
->fr_fix
+= fill_size
;
9445 fragp
->fr_var
-= fill_size
;
9450 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
9452 TInsn tinsn
, single_target
;
9453 int size
, old_size
, diff
;
9454 offsetT frag_offset
;
9456 gas_assert (slot
== 0);
9457 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
9459 if (fragP
->tc_frag_data
.is_aligning_branch
== 1)
9461 gas_assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
9462 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
9463 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
9468 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
9470 /* No conversion. */
9475 gas_assert (fragP
->fr_opcode
!= NULL
);
9477 /* Frags in this relaxation state should only contain
9478 single instruction bundles. */
9479 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
9481 /* Just convert it to a wide form.... */
9483 old_size
= xg_get_single_size (tinsn
.opcode
);
9485 tinsn_init (&single_target
);
9486 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9488 if (! xg_is_single_relaxable_insn (&tinsn
, &single_target
, FALSE
))
9490 as_bad (_("unable to widen instruction"));
9494 size
= xg_get_single_size (single_target
.opcode
);
9495 xg_emit_insn_to_buf (&single_target
, fragP
->fr_opcode
, fragP
,
9498 diff
= size
- old_size
;
9499 gas_assert (diff
>= 0);
9500 gas_assert (diff
<= fragP
->fr_var
);
9501 fragP
->fr_var
-= diff
;
9502 fragP
->fr_fix
+= diff
;
9510 convert_frag_fill_nop (fragS
*fragP
)
9512 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
9513 int size
= fragP
->tc_frag_data
.text_expansion
[0];
9514 gas_assert ((unsigned) size
== (fragP
->fr_next
->fr_address
9515 - fragP
->fr_address
- fragP
->fr_fix
));
9518 /* No conversion. */
9522 assemble_nop (size
, loc
);
9523 fragP
->tc_frag_data
.is_insn
= TRUE
;
9524 fragP
->fr_var
-= size
;
9525 fragP
->fr_fix
+= size
;
9530 static fixS
*fix_new_exp_in_seg
9531 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
9532 bfd_reloc_code_real_type
);
9533 static void convert_frag_immed_finish_loop (segT
, fragS
*, TInsn
*);
9536 convert_frag_immed (segT segP
,
9542 char *immed_instr
= fragP
->fr_opcode
;
9544 bfd_boolean expanded
= FALSE
;
9545 bfd_boolean branch_jmp_to_next
= FALSE
;
9546 char *fr_opcode
= fragP
->fr_opcode
;
9547 xtensa_isa isa
= xtensa_default_isa
;
9548 bfd_boolean from_wide_insn
= FALSE
;
9550 bfd_boolean is_loop
;
9552 gas_assert (fr_opcode
!= NULL
);
9554 xg_clear_vinsn (&cur_vinsn
);
9556 vinsn_from_chars (&cur_vinsn
, fr_opcode
);
9557 if (cur_vinsn
.num_slots
> 1)
9558 from_wide_insn
= TRUE
;
9560 orig_tinsn
= cur_vinsn
.slots
[slot
];
9561 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
9563 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
9565 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9566 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
9568 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
9570 /* Conversion just inserts a NOP and marks the fix as completed. */
9571 bytes
= xtensa_format_length (isa
, fmt
);
9574 cur_vinsn
.slots
[slot
].opcode
=
9575 xtensa_format_slot_nop_opcode (isa
, cur_vinsn
.format
, slot
);
9576 cur_vinsn
.slots
[slot
].ntok
= 0;
9580 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
9581 gas_assert (bytes
== 2 || bytes
== 3);
9582 build_nop (&cur_vinsn
.slots
[0], bytes
);
9583 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
9585 vinsn_to_insnbuf (&cur_vinsn
, fr_opcode
, frag_now
, TRUE
);
9586 xtensa_insnbuf_to_chars
9587 (isa
, cur_vinsn
.insnbuf
, (unsigned char *) fr_opcode
, 0);
9592 /* Here is the fun stuff: Get the immediate field from this
9593 instruction. If it fits, we're done. If not, find the next
9594 instruction sequence that fits. */
9598 symbolS
*lit_sym
= NULL
;
9600 int target_offset
= 0;
9603 symbolS
*gen_label
= NULL
;
9604 offsetT frag_offset
;
9605 bfd_boolean first
= TRUE
;
9606 bfd_boolean last_is_jump
;
9608 /* It does not fit. Find something that does and
9609 convert immediately. */
9610 frag_offset
= fr_opcode
- fragP
->fr_literal
;
9611 istack_init (&istack
);
9612 xg_assembly_relax (&istack
, &orig_tinsn
,
9613 segP
, fragP
, frag_offset
, min_steps
, 0);
9615 old_size
= xtensa_format_length (isa
, fmt
);
9617 /* Assemble this right inline. */
9619 /* First, create the mapping from a label name to the REAL label. */
9621 for (i
= 0; i
< istack
.ninsn
; i
++)
9623 TInsn
*tinsn
= &istack
.insn
[i
];
9626 switch (tinsn
->insn_type
)
9629 if (lit_sym
!= NULL
)
9630 as_bad (_("multiple literals in expansion"));
9631 /* First find the appropriate space in the literal pool. */
9632 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9633 if (lit_frag
== NULL
)
9634 as_bad (_("no registered fragment for literal"));
9635 if (tinsn
->ntok
!= 1)
9636 as_bad (_("number of literal tokens != 1"));
9638 /* Set the literal symbol and add a fixup. */
9639 lit_sym
= lit_frag
->fr_symbol
;
9643 if (align_targets
&& !is_loop
)
9645 fragS
*unreach
= fragP
->fr_next
;
9646 while (!(unreach
->fr_type
== rs_machine_dependent
9647 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9648 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
9650 unreach
= unreach
->fr_next
;
9653 gas_assert (unreach
->fr_type
== rs_machine_dependent
9654 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9655 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
9657 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
9659 gas_assert (gen_label
== NULL
);
9660 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
9661 fr_opcode
- fragP
->fr_literal
9662 + target_offset
, fragP
);
9666 if (first
&& from_wide_insn
)
9668 target_offset
+= xtensa_format_length (isa
, fmt
);
9670 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9671 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9674 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9681 last_is_jump
= FALSE
;
9682 for (i
= 0; i
< istack
.ninsn
; i
++)
9684 TInsn
*tinsn
= &istack
.insn
[i
];
9688 bfd_reloc_code_real_type reloc_type
;
9690 switch (tinsn
->insn_type
)
9693 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9694 /* Already checked. */
9695 gas_assert (lit_frag
!= NULL
);
9696 gas_assert (lit_sym
!= NULL
);
9697 gas_assert (tinsn
->ntok
== 1);
9699 target_seg
= S_GET_SEGMENT (lit_sym
);
9700 gas_assert (target_seg
);
9701 reloc_type
= map_operator_to_reloc (tinsn
->tok
[0].X_op
, TRUE
);
9702 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
9703 &tinsn
->tok
[0], FALSE
, reloc_type
);
9710 xg_resolve_labels (tinsn
, gen_label
);
9711 xg_resolve_literals (tinsn
, lit_sym
);
9712 if (from_wide_insn
&& first
)
9715 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9717 cur_vinsn
.slots
[slot
] = *tinsn
;
9721 cur_vinsn
.slots
[slot
].opcode
=
9722 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
9723 cur_vinsn
.slots
[slot
].ntok
= 0;
9725 vinsn_to_insnbuf (&cur_vinsn
, immed_instr
, fragP
, TRUE
);
9726 xtensa_insnbuf_to_chars (isa
, cur_vinsn
.insnbuf
,
9727 (unsigned char *) immed_instr
, 0);
9728 fragP
->tc_frag_data
.is_insn
= TRUE
;
9729 size
= xtensa_format_length (isa
, fmt
);
9730 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9733 (tinsn
, immed_instr
+ size
, fragP
,
9734 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
9735 size
+= xg_get_single_size (tinsn
->opcode
);
9740 size
= xg_get_single_size (tinsn
->opcode
);
9741 xg_emit_insn_to_buf (tinsn
, immed_instr
, fragP
,
9742 immed_instr
- fragP
->fr_literal
, TRUE
);
9744 immed_instr
+= size
;
9750 diff
= total_size
- old_size
;
9751 gas_assert (diff
>= 0);
9754 gas_assert (diff
<= fragP
->fr_var
);
9755 fragP
->fr_var
-= diff
;
9756 fragP
->fr_fix
+= diff
;
9759 /* Check for undefined immediates in LOOP instructions. */
9763 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
9764 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9766 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9769 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
9770 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9772 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9777 if (expanded
&& xtensa_opcode_is_loop (isa
, orig_tinsn
.opcode
) == 1)
9778 convert_frag_immed_finish_loop (segP
, fragP
, &orig_tinsn
);
9780 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
9782 /* Add an expansion note on the expanded instruction. */
9783 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
9784 &orig_tinsn
.tok
[0], TRUE
,
9785 BFD_RELOC_XTENSA_ASM_EXPAND
);
9790 /* Add a new fix expression into the desired segment. We have to
9791 switch to that segment to do this. */
9794 fix_new_exp_in_seg (segT new_seg
,
9801 bfd_reloc_code_real_type r_type
)
9805 subsegT subseg
= now_subseg
;
9807 gas_assert (new_seg
!= 0);
9808 subseg_set (new_seg
, new_subseg
);
9810 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
9811 subseg_set (seg
, subseg
);
9816 /* Relax a loop instruction so that it can span loop >256 bytes.
9822 addi as, as, lo8 (label-.L1)
9823 addmi as, as, mid8 (label-.L1)
9834 convert_frag_immed_finish_loop (segT segP
, fragS
*fragP
, TInsn
*tinsn
)
9839 unsigned long target
;
9840 static xtensa_insnbuf insnbuf
= NULL
;
9841 unsigned int loop_length
, loop_length_hi
, loop_length_lo
;
9842 xtensa_isa isa
= xtensa_default_isa
;
9843 addressT loop_offset
;
9844 addressT addi_offset
= 9;
9845 addressT addmi_offset
= 12;
9850 insnbuf
= xtensa_insnbuf_alloc (isa
);
9852 /* Get the loop offset. */
9853 loop_offset
= get_expanded_loop_offset (tinsn
->opcode
);
9855 /* Validate that there really is a LOOP at the loop_offset. Because
9856 loops are not bundleable, we can assume that the instruction will be
9858 tinsn_from_chars (&loop_insn
, fragP
->fr_opcode
+ loop_offset
, 0);
9859 tinsn_immed_from_frag (&loop_insn
, fragP
, 0);
9861 gas_assert (xtensa_opcode_is_loop (isa
, loop_insn
.opcode
) == 1);
9862 addi_offset
+= loop_offset
;
9863 addmi_offset
+= loop_offset
;
9865 gas_assert (tinsn
->ntok
== 2);
9866 if (tinsn
->tok
[1].X_op
== O_constant
)
9867 target
= tinsn
->tok
[1].X_add_number
;
9868 else if (tinsn
->tok
[1].X_op
== O_symbol
)
9870 /* Find the fragment. */
9871 symbolS
*sym
= tinsn
->tok
[1].X_add_symbol
;
9872 gas_assert (S_GET_SEGMENT (sym
) == segP
9873 || S_GET_SEGMENT (sym
) == absolute_section
);
9874 target
= (S_GET_VALUE (sym
) + tinsn
->tok
[1].X_add_number
);
9878 as_bad (_("invalid expression evaluation type %d"), tinsn
->tok
[1].X_op
);
9882 loop_length
= target
- (fragP
->fr_address
+ fragP
->fr_fix
);
9883 loop_length_hi
= loop_length
& ~0x0ff;
9884 loop_length_lo
= loop_length
& 0x0ff;
9885 if (loop_length_lo
>= 128)
9887 loop_length_lo
-= 256;
9888 loop_length_hi
+= 256;
9891 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
9892 32512. If the loop is larger than that, then we just fail. */
9893 if (loop_length_hi
> 32512)
9894 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9895 _("loop too long for LOOP instruction"));
9897 tinsn_from_chars (&addi_insn
, fragP
->fr_opcode
+ addi_offset
, 0);
9898 gas_assert (addi_insn
.opcode
== xtensa_addi_opcode
);
9900 tinsn_from_chars (&addmi_insn
, fragP
->fr_opcode
+ addmi_offset
, 0);
9901 gas_assert (addmi_insn
.opcode
== xtensa_addmi_opcode
);
9903 set_expr_const (&addi_insn
.tok
[2], loop_length_lo
);
9904 tinsn_to_insnbuf (&addi_insn
, insnbuf
);
9906 fragP
->tc_frag_data
.is_insn
= TRUE
;
9907 xtensa_insnbuf_to_chars
9908 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addi_offset
, 0);
9910 set_expr_const (&addmi_insn
.tok
[2], loop_length_hi
);
9911 tinsn_to_insnbuf (&addmi_insn
, insnbuf
);
9912 xtensa_insnbuf_to_chars
9913 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addmi_offset
, 0);
9915 /* Walk through all of the frags from here to the loop end
9916 and mark them as no_transform to keep them from being modified
9917 by the linker. If we ever have a relocation for the
9918 addi/addmi of the difference of two symbols we can remove this. */
9921 for (next_fragP
= fragP
; next_fragP
!= NULL
;
9922 next_fragP
= next_fragP
->fr_next
)
9924 next_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
9925 if (next_fragP
->tc_frag_data
.is_loop_target
)
9927 if (target_count
== 2)
9933 /* A map that keeps information on a per-subsegment basis. This is
9934 maintained during initial assembly, but is invalid once the
9935 subsegments are smashed together. I.E., it cannot be used during
9938 typedef struct subseg_map_struct
9946 float total_freq
; /* fall-through + branch target frequency */
9947 float target_freq
; /* branch target frequency alone */
9949 struct subseg_map_struct
*next
;
9953 static subseg_map
*sseg_map
= NULL
;
9956 get_subseg_info (segT seg
, subsegT subseg
)
9958 subseg_map
*subseg_e
;
9960 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
9962 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
9970 add_subseg_info (segT seg
, subsegT subseg
)
9972 subseg_map
*subseg_e
= (subseg_map
*) xmalloc (sizeof (subseg_map
));
9973 memset (subseg_e
, 0, sizeof (subseg_map
));
9974 subseg_e
->seg
= seg
;
9975 subseg_e
->subseg
= subseg
;
9976 subseg_e
->flags
= 0;
9977 /* Start off considering every branch target very important. */
9978 subseg_e
->target_freq
= 1.0;
9979 subseg_e
->total_freq
= 1.0;
9980 subseg_e
->next
= sseg_map
;
9981 sseg_map
= subseg_e
;
9987 get_last_insn_flags (segT seg
, subsegT subseg
)
9989 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9991 return subseg_e
->flags
;
9997 set_last_insn_flags (segT seg
,
10002 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
10004 subseg_e
= add_subseg_info (seg
, subseg
);
10006 subseg_e
->flags
|= fl
;
10008 subseg_e
->flags
&= ~fl
;
10013 get_subseg_total_freq (segT seg
, subsegT subseg
)
10015 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
10017 return subseg_e
->total_freq
;
10023 get_subseg_target_freq (segT seg
, subsegT subseg
)
10025 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
10027 return subseg_e
->target_freq
;
10033 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
10035 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
10037 subseg_e
= add_subseg_info (seg
, subseg
);
10038 subseg_e
->total_freq
= total_f
;
10039 subseg_e
->target_freq
= target_f
;
10043 /* Segment Lists and emit_state Stuff. */
10046 xtensa_move_seg_list_to_beginning (seg_list
*head
)
10051 segT literal_section
= head
->seg
;
10053 /* Move the literal section to the front of the section list. */
10054 gas_assert (literal_section
);
10055 if (literal_section
!= stdoutput
->sections
)
10057 bfd_section_list_remove (stdoutput
, literal_section
);
10058 bfd_section_list_prepend (stdoutput
, literal_section
);
10065 static void mark_literal_frags (seg_list
*);
10068 xtensa_move_literals (void)
10071 frchainS
*frchain_from
, *frchain_to
;
10072 fragS
*search_frag
, *next_frag
, *last_frag
, *literal_pool
, *insert_after
;
10073 fragS
**frag_splice
;
10076 fixS
*fix
, *next_fix
, **fix_splice
;
10079 mark_literal_frags (literal_head
->next
);
10081 if (use_literal_section
)
10084 for (segment
= literal_head
->next
; segment
; segment
= segment
->next
)
10086 /* Keep the literals for .init and .fini in separate sections. */
10087 if (!strcmp (segment_name (segment
->seg
), INIT_SECTION_NAME
)
10088 || !strcmp (segment_name (segment
->seg
), FINI_SECTION_NAME
))
10091 frchain_from
= seg_info (segment
->seg
)->frchainP
;
10092 search_frag
= frchain_from
->frch_root
;
10093 literal_pool
= NULL
;
10095 frag_splice
= &(frchain_from
->frch_root
);
10097 while (!search_frag
->tc_frag_data
.literal_frag
)
10099 gas_assert (search_frag
->fr_fix
== 0
10100 || search_frag
->fr_type
== rs_align
);
10101 search_frag
= search_frag
->fr_next
;
10104 gas_assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
10105 == RELAX_LITERAL_POOL_BEGIN
);
10106 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
10108 /* Make sure that all the frags in this series are closed, and
10109 that there is at least one left over of zero-size. This
10110 prevents us from making a segment with an frchain without any
10112 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10113 xtensa_set_frag_assembly_state (frag_now
);
10114 last_frag
= frag_now
;
10115 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10116 xtensa_set_frag_assembly_state (frag_now
);
10118 while (search_frag
!= frag_now
)
10120 next_frag
= search_frag
->fr_next
;
10122 /* First, move the frag out of the literal section and
10123 to the appropriate place. */
10124 if (search_frag
->tc_frag_data
.literal_frag
)
10126 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
10127 gas_assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
10128 frchain_to
= literal_pool
->tc_frag_data
.lit_frchain
;
10129 gas_assert (frchain_to
);
10131 insert_after
= literal_pool
->tc_frag_data
.literal_frag
;
10132 dest_seg
= insert_after
->fr_next
->tc_frag_data
.lit_seg
;
10134 *frag_splice
= next_frag
;
10135 search_frag
->fr_next
= insert_after
->fr_next
;
10136 insert_after
->fr_next
= search_frag
;
10137 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
10138 literal_pool
->tc_frag_data
.literal_frag
= search_frag
;
10140 /* Now move any fixups associated with this frag to the
10142 fix
= frchain_from
->fix_root
;
10143 fix_splice
= &(frchain_from
->fix_root
);
10146 next_fix
= fix
->fx_next
;
10147 if (fix
->fx_frag
== search_frag
)
10149 *fix_splice
= next_fix
;
10150 fix
->fx_next
= frchain_to
->fix_root
;
10151 frchain_to
->fix_root
= fix
;
10152 if (frchain_to
->fix_tail
== NULL
)
10153 frchain_to
->fix_tail
= fix
;
10156 fix_splice
= &(fix
->fx_next
);
10159 search_frag
= next_frag
;
10162 if (frchain_from
->fix_root
!= NULL
)
10164 frchain_from
= seg_info (segment
->seg
)->frchainP
;
10165 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
10167 gas_assert (frchain_from
->fix_root
== NULL
);
10169 frchain_from
->fix_tail
= NULL
;
10170 xtensa_restore_emit_state (&state
);
10173 /* Now fix up the SEGMENT value for all the literal symbols. */
10174 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
10176 symbolS
*lit_sym
= lit
->sym
;
10177 segT dest_seg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
10179 S_SET_SEGMENT (lit_sym
, dest_seg
);
10184 /* Walk over all the frags for segments in a list and mark them as
10185 containing literals. As clunky as this is, we can't rely on frag_var
10186 and frag_variant to get called in all situations. */
10189 mark_literal_frags (seg_list
*segment
)
10191 frchainS
*frchain_from
;
10192 fragS
*search_frag
;
10196 frchain_from
= seg_info (segment
->seg
)->frchainP
;
10197 search_frag
= frchain_from
->frch_root
;
10198 while (search_frag
)
10200 search_frag
->tc_frag_data
.is_literal
= TRUE
;
10201 search_frag
= search_frag
->fr_next
;
10203 segment
= segment
->next
;
10209 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
10211 /* Move all of the sections in the section list to come
10212 after "after" in the gnu segment list. */
10217 segT literal_section
= head
->seg
;
10219 /* Move the literal section after "after". */
10220 gas_assert (literal_section
);
10221 if (literal_section
!= after
)
10223 bfd_section_list_remove (stdoutput
, literal_section
);
10224 bfd_section_list_insert_after (stdoutput
, after
, literal_section
);
10232 /* Push all the literal segments to the end of the gnu list. */
10235 xtensa_reorder_segments (void)
10242 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
10248 /* Now that we have the last section, push all the literal
10249 sections to the end. */
10250 xtensa_reorder_seg_list (literal_head
, last_sec
);
10252 /* Now perform the final error check. */
10253 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
10255 gas_assert (new_count
== old_count
);
10259 /* Change the emit state (seg, subseg, and frag related stuff) to the
10260 correct location. Return a emit_state which can be passed to
10261 xtensa_restore_emit_state to return to current fragment. */
10264 xtensa_switch_to_literal_fragment (emit_state
*result
)
10266 if (directive_state
[directive_absolute_literals
])
10268 segT lit4_seg
= cache_literal_section (TRUE
);
10269 xtensa_switch_section_emit_state (result
, lit4_seg
, 0);
10272 xtensa_switch_to_non_abs_literal_fragment (result
);
10274 /* Do a 4-byte align here. */
10275 frag_align (2, 0, 0);
10276 record_alignment (now_seg
, 2);
10281 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
10283 static bfd_boolean recursive
= FALSE
;
10284 fragS
*pool_location
= get_literal_pool_location (now_seg
);
10286 bfd_boolean is_init
=
10287 (now_seg
&& !strcmp (segment_name (now_seg
), INIT_SECTION_NAME
));
10288 bfd_boolean is_fini
=
10289 (now_seg
&& !strcmp (segment_name (now_seg
), FINI_SECTION_NAME
));
10291 if (pool_location
== NULL
10292 && !use_literal_section
10294 && !is_init
&& ! is_fini
)
10296 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
10298 /* When we mark a literal pool location, we want to put a frag in
10299 the literal pool that points to it. But to do that, we want to
10300 switch_to_literal_fragment. But literal sections don't have
10301 literal pools, so their location is always null, so we would
10302 recurse forever. This is kind of hacky, but it works. */
10305 xtensa_mark_literal_pool_location ();
10309 lit_seg
= cache_literal_section (FALSE
);
10310 xtensa_switch_section_emit_state (result
, lit_seg
, 0);
10312 if (!use_literal_section
10313 && !is_init
&& !is_fini
10314 && get_literal_pool_location (now_seg
) != pool_location
)
10316 /* Close whatever frag is there. */
10317 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10318 xtensa_set_frag_assembly_state (frag_now
);
10319 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
10320 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10321 xtensa_set_frag_assembly_state (frag_now
);
10326 /* Call this function before emitting data into the literal section.
10327 This is a helper function for xtensa_switch_to_literal_fragment.
10328 This is similar to a .section new_now_seg subseg. */
10331 xtensa_switch_section_emit_state (emit_state
*state
,
10333 subsegT new_now_subseg
)
10335 state
->name
= now_seg
->name
;
10336 state
->now_seg
= now_seg
;
10337 state
->now_subseg
= now_subseg
;
10338 state
->generating_literals
= generating_literals
;
10339 generating_literals
++;
10340 subseg_set (new_now_seg
, new_now_subseg
);
10344 /* Use to restore the emitting into the normal place. */
10347 xtensa_restore_emit_state (emit_state
*state
)
10349 generating_literals
= state
->generating_literals
;
10350 subseg_set (state
->now_seg
, state
->now_subseg
);
10354 /* Predicate function used to look up a section in a particular group. */
10357 match_section_group (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
, void *inf
)
10359 const char *gname
= inf
;
10360 const char *group_name
= elf_group_name (sec
);
10362 return (group_name
== gname
10363 || (group_name
!= NULL
10365 && strcmp (group_name
, gname
) == 0));
10369 /* Get the literal section to be used for the current text section.
10370 The result may be cached in the default_lit_sections structure. */
10373 cache_literal_section (bfd_boolean use_abs_literals
)
10375 const char *text_name
, *group_name
= 0;
10376 char *base_name
, *name
, *suffix
;
10378 segT seg
, current_section
;
10379 int current_subsec
;
10380 bfd_boolean linkonce
= FALSE
;
10382 /* Save the current section/subsection. */
10383 current_section
= now_seg
;
10384 current_subsec
= now_subseg
;
10386 /* Clear the cached values if they are no longer valid. */
10387 if (now_seg
!= default_lit_sections
.current_text_seg
)
10389 default_lit_sections
.current_text_seg
= now_seg
;
10390 default_lit_sections
.lit_seg
= NULL
;
10391 default_lit_sections
.lit4_seg
= NULL
;
10394 /* Check if the literal section is already cached. */
10395 if (use_abs_literals
)
10396 pcached
= &default_lit_sections
.lit4_seg
;
10398 pcached
= &default_lit_sections
.lit_seg
;
10403 text_name
= default_lit_sections
.lit_prefix
;
10404 if (! text_name
|| ! *text_name
)
10406 text_name
= segment_name (current_section
);
10407 group_name
= elf_group_name (current_section
);
10408 linkonce
= (current_section
->flags
& SEC_LINK_ONCE
) != 0;
10411 base_name
= use_abs_literals
? ".lit4" : ".literal";
10414 name
= xmalloc (strlen (base_name
) + strlen (group_name
) + 2);
10415 sprintf (name
, "%s.%s", base_name
, group_name
);
10417 else if (strncmp (text_name
, ".gnu.linkonce.", linkonce_len
) == 0)
10419 suffix
= strchr (text_name
+ linkonce_len
, '.');
10421 name
= xmalloc (linkonce_len
+ strlen (base_name
) + 1
10422 + (suffix
? strlen (suffix
) : 0));
10423 strcpy (name
, ".gnu.linkonce");
10424 strcat (name
, base_name
);
10426 strcat (name
, suffix
);
10431 /* If the section name ends with ".text", then replace that suffix
10432 instead of appending an additional suffix. */
10433 size_t len
= strlen (text_name
);
10434 if (len
>= 5 && strcmp (text_name
+ len
- 5, ".text") == 0)
10437 name
= xmalloc (len
+ strlen (base_name
) + 1);
10438 strcpy (name
, text_name
);
10439 strcpy (name
+ len
, base_name
);
10442 /* Canonicalize section names to allow renaming literal sections.
10443 The group name, if any, came from the current text section and
10444 has already been canonicalized. */
10445 name
= tc_canonicalize_symbol_name (name
);
10447 seg
= bfd_get_section_by_name_if (stdoutput
, name
, match_section_group
,
10448 (void *) group_name
);
10453 seg
= subseg_force_new (name
, 0);
10455 if (! use_abs_literals
)
10457 /* Add the newly created literal segment to the list. */
10458 seg_list
*n
= (seg_list
*) xmalloc (sizeof (seg_list
));
10460 n
->next
= literal_head
->next
;
10461 literal_head
->next
= n
;
10464 flags
= (SEC_HAS_CONTENTS
| SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
10465 | (linkonce
? (SEC_LINK_ONCE
| SEC_LINK_DUPLICATES_DISCARD
) : 0)
10466 | (use_abs_literals
? SEC_DATA
: SEC_CODE
));
10468 elf_group_name (seg
) = group_name
;
10470 bfd_set_section_flags (stdoutput
, seg
, flags
);
10471 bfd_set_section_alignment (stdoutput
, seg
, 2);
10475 subseg_set (current_section
, current_subsec
);
10480 /* Property Tables Stuff. */
10482 #define XTENSA_INSN_SEC_NAME ".xt.insn"
10483 #define XTENSA_LIT_SEC_NAME ".xt.lit"
10484 #define XTENSA_PROP_SEC_NAME ".xt.prop"
10486 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
10487 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
10489 static bfd_boolean
get_frag_is_literal (const fragS
*);
10490 static void xtensa_create_property_segments
10491 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
10492 static void xtensa_create_xproperty_segments
10493 (frag_flags_fn
, const char *, xt_section_type
);
10494 static bfd_boolean
exclude_section_from_property_tables (segT
);
10495 static bfd_boolean
section_has_property (segT
, frag_predicate
);
10496 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
10497 static void add_xt_block_frags
10498 (segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
10499 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
10500 static void xtensa_frag_flags_init (frag_flags
*);
10501 static void get_frag_property_flags (const fragS
*, frag_flags
*);
10502 static flagword
frag_flags_to_number (const frag_flags
*);
10503 static void add_xt_prop_frags (segT
, xtensa_block_info
**, frag_flags_fn
);
10505 /* Set up property tables after relaxation. */
10508 xtensa_post_relax_hook (void)
10510 xtensa_move_seg_list_to_beginning (literal_head
);
10512 xtensa_find_unmarked_state_frags ();
10513 xtensa_mark_frags_for_org ();
10514 xtensa_mark_difference_of_two_symbols ();
10516 xtensa_create_property_segments (get_frag_is_literal
,
10518 XTENSA_LIT_SEC_NAME
,
10520 xtensa_create_xproperty_segments (get_frag_property_flags
,
10521 XTENSA_PROP_SEC_NAME
,
10524 if (warn_unaligned_branch_targets
)
10525 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
10526 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
10530 /* This function is only meaningful after xtensa_move_literals. */
10533 get_frag_is_literal (const fragS
*fragP
)
10535 gas_assert (fragP
!= NULL
);
10536 return fragP
->tc_frag_data
.is_literal
;
10541 xtensa_create_property_segments (frag_predicate property_function
,
10542 frag_predicate end_property_function
,
10543 const char *section_name_base
,
10544 xt_section_type sec_type
)
10548 /* Walk over all of the current segments.
10549 Walk over each fragment
10550 For each non-empty fragment,
10551 Build a property record (append where possible). */
10553 for (seclist
= &stdoutput
->sections
;
10554 seclist
&& *seclist
;
10555 seclist
= &(*seclist
)->next
)
10557 segT sec
= *seclist
;
10559 if (exclude_section_from_property_tables (sec
))
10562 if (section_has_property (sec
, property_function
))
10564 segment_info_type
*xt_seg_info
;
10565 xtensa_block_info
**xt_blocks
;
10566 segT prop_sec
= xtensa_make_property_section (sec
, section_name_base
);
10568 prop_sec
->output_section
= prop_sec
;
10569 subseg_set (prop_sec
, 0);
10570 xt_seg_info
= seg_info (prop_sec
);
10571 xt_blocks
= &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10573 /* Walk over all of the frchains here and add new sections. */
10574 add_xt_block_frags (sec
, xt_blocks
, property_function
,
10575 end_property_function
);
10579 /* Now we fill them out.... */
10581 for (seclist
= &stdoutput
->sections
;
10582 seclist
&& *seclist
;
10583 seclist
= &(*seclist
)->next
)
10585 segment_info_type
*seginfo
;
10586 xtensa_block_info
*block
;
10587 segT sec
= *seclist
;
10589 seginfo
= seg_info (sec
);
10590 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10594 xtensa_block_info
*cur_block
;
10596 bfd_size_type rec_size
;
10598 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10601 rec_size
= num_recs
* 8;
10602 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10609 subseg_set (sec
, 0);
10610 frag_data
= frag_more (rec_size
);
10612 for (i
= 0; i
< num_recs
; i
++)
10616 /* Write the fixup. */
10617 gas_assert (cur_block
);
10618 fix
= fix_new (frag_now
, i
* 8, 4,
10619 section_symbol (cur_block
->sec
),
10621 FALSE
, BFD_RELOC_32
);
10622 fix
->fx_file
= "<internal>";
10625 /* Write the length. */
10626 md_number_to_chars (&frag_data
[4 + i
* 8],
10627 cur_block
->size
, 4);
10628 cur_block
= cur_block
->next
;
10630 frag_wane (frag_now
);
10632 frag_wane (frag_now
);
10640 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
10641 const char *section_name_base
,
10642 xt_section_type sec_type
)
10646 /* Walk over all of the current segments.
10647 Walk over each fragment.
10648 For each fragment that has instructions,
10649 build an instruction record (append where possible). */
10651 for (seclist
= &stdoutput
->sections
;
10652 seclist
&& *seclist
;
10653 seclist
= &(*seclist
)->next
)
10655 segT sec
= *seclist
;
10657 if (exclude_section_from_property_tables (sec
))
10660 if (section_has_xproperty (sec
, flag_fn
))
10662 segment_info_type
*xt_seg_info
;
10663 xtensa_block_info
**xt_blocks
;
10664 segT prop_sec
= xtensa_make_property_section (sec
, section_name_base
);
10666 prop_sec
->output_section
= prop_sec
;
10667 subseg_set (prop_sec
, 0);
10668 xt_seg_info
= seg_info (prop_sec
);
10669 xt_blocks
= &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10671 /* Walk over all of the frchains here and add new sections. */
10672 add_xt_prop_frags (sec
, xt_blocks
, flag_fn
);
10676 /* Now we fill them out.... */
10678 for (seclist
= &stdoutput
->sections
;
10679 seclist
&& *seclist
;
10680 seclist
= &(*seclist
)->next
)
10682 segment_info_type
*seginfo
;
10683 xtensa_block_info
*block
;
10684 segT sec
= *seclist
;
10686 seginfo
= seg_info (sec
);
10687 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10691 xtensa_block_info
*cur_block
;
10693 bfd_size_type rec_size
;
10695 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10698 rec_size
= num_recs
* (8 + 4);
10699 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10700 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
10707 subseg_set (sec
, 0);
10708 frag_data
= frag_more (rec_size
);
10710 for (i
= 0; i
< num_recs
; i
++)
10714 /* Write the fixup. */
10715 gas_assert (cur_block
);
10716 fix
= fix_new (frag_now
, i
* 12, 4,
10717 section_symbol (cur_block
->sec
),
10719 FALSE
, BFD_RELOC_32
);
10720 fix
->fx_file
= "<internal>";
10723 /* Write the length. */
10724 md_number_to_chars (&frag_data
[4 + i
* 12],
10725 cur_block
->size
, 4);
10726 md_number_to_chars (&frag_data
[8 + i
* 12],
10727 frag_flags_to_number (&cur_block
->flags
),
10728 sizeof (flagword
));
10729 cur_block
= cur_block
->next
;
10731 frag_wane (frag_now
);
10733 frag_wane (frag_now
);
10741 exclude_section_from_property_tables (segT sec
)
10743 flagword flags
= bfd_get_section_flags (stdoutput
, sec
);
10745 /* Sections that don't contribute to the memory footprint are excluded. */
10746 if ((flags
& SEC_DEBUGGING
)
10747 || !(flags
& SEC_ALLOC
)
10748 || (flags
& SEC_MERGE
))
10751 /* Linker cie and fde optimizations mess up property entries for
10752 eh_frame sections, but there is nothing inside them relevant to
10753 property tables anyway. */
10754 if (strcmp (sec
->name
, ".eh_frame") == 0)
10762 section_has_property (segT sec
, frag_predicate property_function
)
10764 segment_info_type
*seginfo
= seg_info (sec
);
10767 if (seginfo
&& seginfo
->frchainP
)
10769 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10771 if (property_function (fragP
)
10772 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10781 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
10783 segment_info_type
*seginfo
= seg_info (sec
);
10786 if (seginfo
&& seginfo
->frchainP
)
10788 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10790 frag_flags prop_flags
;
10791 property_function (fragP
, &prop_flags
);
10792 if (!xtensa_frag_flags_is_empty (&prop_flags
))
10800 /* Two types of block sections exist right now: literal and insns. */
10803 add_xt_block_frags (segT sec
,
10804 xtensa_block_info
**xt_block
,
10805 frag_predicate property_function
,
10806 frag_predicate end_property_function
)
10810 /* Build it if needed. */
10811 while (*xt_block
!= NULL
)
10812 xt_block
= &(*xt_block
)->next
;
10813 /* We are either at NULL at the beginning or at the end. */
10815 /* Walk through the frags. */
10816 if (seg_info (sec
)->frchainP
)
10818 for (fragP
= seg_info (sec
)->frchainP
->frch_root
;
10820 fragP
= fragP
->fr_next
)
10822 if (property_function (fragP
)
10823 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10825 if (*xt_block
!= NULL
)
10827 if ((*xt_block
)->offset
+ (*xt_block
)->size
10828 == fragP
->fr_address
)
10829 (*xt_block
)->size
+= fragP
->fr_fix
;
10831 xt_block
= &((*xt_block
)->next
);
10833 if (*xt_block
== NULL
)
10835 xtensa_block_info
*new_block
= (xtensa_block_info
*)
10836 xmalloc (sizeof (xtensa_block_info
));
10837 new_block
->sec
= sec
;
10838 new_block
->offset
= fragP
->fr_address
;
10839 new_block
->size
= fragP
->fr_fix
;
10840 new_block
->next
= NULL
;
10841 xtensa_frag_flags_init (&new_block
->flags
);
10842 *xt_block
= new_block
;
10844 if (end_property_function
10845 && end_property_function (fragP
))
10847 xt_block
= &((*xt_block
)->next
);
10855 /* Break the encapsulation of add_xt_prop_frags here. */
10858 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
10860 if (prop_flags
->is_literal
10861 || prop_flags
->is_insn
10862 || prop_flags
->is_data
10863 || prop_flags
->is_unreachable
)
10870 xtensa_frag_flags_init (frag_flags
*prop_flags
)
10872 memset (prop_flags
, 0, sizeof (frag_flags
));
10877 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
10879 xtensa_frag_flags_init (prop_flags
);
10880 if (fragP
->tc_frag_data
.is_literal
)
10881 prop_flags
->is_literal
= TRUE
;
10882 if (fragP
->tc_frag_data
.is_specific_opcode
10883 || fragP
->tc_frag_data
.is_no_transform
)
10885 prop_flags
->is_no_transform
= TRUE
;
10886 if (xtensa_frag_flags_is_empty (prop_flags
))
10887 prop_flags
->is_data
= TRUE
;
10889 if (fragP
->tc_frag_data
.is_unreachable
)
10890 prop_flags
->is_unreachable
= TRUE
;
10891 else if (fragP
->tc_frag_data
.is_insn
)
10893 prop_flags
->is_insn
= TRUE
;
10894 if (fragP
->tc_frag_data
.is_loop_target
)
10895 prop_flags
->insn
.is_loop_target
= TRUE
;
10896 if (fragP
->tc_frag_data
.is_branch_target
)
10897 prop_flags
->insn
.is_branch_target
= TRUE
;
10898 if (fragP
->tc_frag_data
.is_no_density
)
10899 prop_flags
->insn
.is_no_density
= TRUE
;
10900 if (fragP
->tc_frag_data
.use_absolute_literals
)
10901 prop_flags
->insn
.is_abslit
= TRUE
;
10903 if (fragP
->tc_frag_data
.is_align
)
10905 prop_flags
->is_align
= TRUE
;
10906 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
10907 if (xtensa_frag_flags_is_empty (prop_flags
))
10908 prop_flags
->is_data
= TRUE
;
10914 frag_flags_to_number (const frag_flags
*prop_flags
)
10917 if (prop_flags
->is_literal
)
10918 num
|= XTENSA_PROP_LITERAL
;
10919 if (prop_flags
->is_insn
)
10920 num
|= XTENSA_PROP_INSN
;
10921 if (prop_flags
->is_data
)
10922 num
|= XTENSA_PROP_DATA
;
10923 if (prop_flags
->is_unreachable
)
10924 num
|= XTENSA_PROP_UNREACHABLE
;
10925 if (prop_flags
->insn
.is_loop_target
)
10926 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
10927 if (prop_flags
->insn
.is_branch_target
)
10929 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
10930 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
10933 if (prop_flags
->insn
.is_no_density
)
10934 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
10935 if (prop_flags
->is_no_transform
)
10936 num
|= XTENSA_PROP_NO_TRANSFORM
;
10937 if (prop_flags
->insn
.is_no_reorder
)
10938 num
|= XTENSA_PROP_INSN_NO_REORDER
;
10939 if (prop_flags
->insn
.is_abslit
)
10940 num
|= XTENSA_PROP_INSN_ABSLIT
;
10942 if (prop_flags
->is_align
)
10944 num
|= XTENSA_PROP_ALIGN
;
10945 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
10953 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
10954 const frag_flags
*prop_flags_2
)
10956 /* Cannot combine with an end marker. */
10958 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
10960 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
10962 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
10965 if (prop_flags_1
->is_insn
)
10967 /* Properties of the beginning of the frag. */
10968 if (prop_flags_2
->insn
.is_loop_target
)
10970 if (prop_flags_2
->insn
.is_branch_target
)
10972 if (prop_flags_1
->insn
.is_no_density
!=
10973 prop_flags_2
->insn
.is_no_density
)
10975 if (prop_flags_1
->is_no_transform
!=
10976 prop_flags_2
->is_no_transform
)
10978 if (prop_flags_1
->insn
.is_no_reorder
!=
10979 prop_flags_2
->insn
.is_no_reorder
)
10981 if (prop_flags_1
->insn
.is_abslit
!=
10982 prop_flags_2
->insn
.is_abslit
)
10986 if (prop_flags_1
->is_align
)
10994 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
10997 unsigned align_bits
;
10999 if (!xt_block
->flags
.is_align
)
11000 return xt_block
->size
;
11002 end_addr
= xt_block
->offset
+ xt_block
->size
;
11003 align_bits
= xt_block
->flags
.alignment
;
11004 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
11005 return end_addr
- xt_block
->offset
;
11010 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
11011 const xtensa_block_info
*xt_block_2
)
11013 if (xt_block
->sec
!= xt_block_2
->sec
)
11015 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
11016 != xt_block_2
->offset
)
11019 if (xt_block_2
->size
== 0
11020 && (!xt_block_2
->flags
.is_unreachable
11021 || xt_block
->flags
.is_unreachable
))
11023 if (xt_block_2
->flags
.is_align
11024 && xt_block
->flags
.is_align
)
11026 /* Nothing needed. */
11027 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
11032 if (xt_block_2
->flags
.is_align
)
11034 /* Push alignment to previous entry. */
11035 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
11036 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
11041 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
11042 &xt_block_2
->flags
))
11045 xt_block
->size
+= xt_block_2
->size
;
11047 if (xt_block_2
->flags
.is_align
)
11049 xt_block
->flags
.is_align
= TRUE
;
11050 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
11058 add_xt_prop_frags (segT sec
,
11059 xtensa_block_info
**xt_block
,
11060 frag_flags_fn property_function
)
11064 /* Build it if needed. */
11065 while (*xt_block
!= NULL
)
11067 xt_block
= &(*xt_block
)->next
;
11069 /* We are either at NULL at the beginning or at the end. */
11071 /* Walk through the frags. */
11072 if (seg_info (sec
)->frchainP
)
11074 for (fragP
= seg_info (sec
)->frchainP
->frch_root
; fragP
;
11075 fragP
= fragP
->fr_next
)
11077 xtensa_block_info tmp_block
;
11078 tmp_block
.sec
= sec
;
11079 tmp_block
.offset
= fragP
->fr_address
;
11080 tmp_block
.size
= fragP
->fr_fix
;
11081 tmp_block
.next
= NULL
;
11082 property_function (fragP
, &tmp_block
.flags
);
11084 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
11085 /* && fragP->fr_fix != 0) */
11087 if ((*xt_block
) == NULL
11088 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
11090 xtensa_block_info
*new_block
;
11091 if ((*xt_block
) != NULL
)
11092 xt_block
= &(*xt_block
)->next
;
11093 new_block
= (xtensa_block_info
*)
11094 xmalloc (sizeof (xtensa_block_info
));
11095 *new_block
= tmp_block
;
11096 *xt_block
= new_block
;
11104 /* op_placement_info_table */
11106 /* op_placement_info makes it easier to determine which
11107 ops can go in which slots. */
11110 init_op_placement_info_table (void)
11112 xtensa_isa isa
= xtensa_default_isa
;
11113 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
11114 xtensa_opcode opcode
;
11117 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
11119 op_placement_table
= (op_placement_info_table
)
11120 xmalloc (sizeof (op_placement_info
) * num_opcodes
);
11121 gas_assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
11123 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
11125 op_placement_info
*opi
= &op_placement_table
[opcode
];
11126 /* FIXME: Make tinsn allocation dynamic. */
11127 if (xtensa_opcode_num_operands (isa
, opcode
) > MAX_INSN_ARGS
)
11128 as_fatal (_("too many operands in instruction"));
11129 opi
->narrowest
= XTENSA_UNDEFINED
;
11130 opi
->narrowest_size
= 0x7F;
11131 opi
->narrowest_slot
= 0;
11133 opi
->num_formats
= 0;
11135 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
11137 opi
->slots
[fmt
] = 0;
11138 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
11140 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
11142 int fmt_length
= xtensa_format_length (isa
, fmt
);
11144 set_bit (fmt
, opi
->formats
);
11145 set_bit (slot
, opi
->slots
[fmt
]);
11146 if (fmt_length
< opi
->narrowest_size
11147 || (fmt_length
== opi
->narrowest_size
11148 && (xtensa_format_num_slots (isa
, fmt
)
11149 < xtensa_format_num_slots (isa
,
11152 opi
->narrowest
= fmt
;
11153 opi
->narrowest_size
= fmt_length
;
11154 opi
->narrowest_slot
= slot
;
11159 opi
->num_formats
++;
11162 xtensa_insnbuf_free (isa
, ibuf
);
11167 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
11169 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
11173 /* If the opcode is available in a single slot format, return its size. */
11176 xg_get_single_size (xtensa_opcode opcode
)
11178 return op_placement_table
[opcode
].narrowest_size
;
11182 static xtensa_format
11183 xg_get_single_format (xtensa_opcode opcode
)
11185 return op_placement_table
[opcode
].narrowest
;
11190 xg_get_single_slot (xtensa_opcode opcode
)
11192 return op_placement_table
[opcode
].narrowest_slot
;
11196 /* Instruction Stack Functions (from "xtensa-istack.h"). */
11199 istack_init (IStack
*stack
)
11201 memset (stack
, 0, sizeof (IStack
));
11207 istack_empty (IStack
*stack
)
11209 return (stack
->ninsn
== 0);
11214 istack_full (IStack
*stack
)
11216 return (stack
->ninsn
== MAX_ISTACK
);
11220 /* Return a pointer to the top IStack entry.
11221 It is an error to call this if istack_empty () is TRUE. */
11224 istack_top (IStack
*stack
)
11226 int rec
= stack
->ninsn
- 1;
11227 gas_assert (!istack_empty (stack
));
11228 return &stack
->insn
[rec
];
11232 /* Add a new TInsn to an IStack.
11233 It is an error to call this if istack_full () is TRUE. */
11236 istack_push (IStack
*stack
, TInsn
*insn
)
11238 int rec
= stack
->ninsn
;
11239 gas_assert (!istack_full (stack
));
11240 stack
->insn
[rec
] = *insn
;
11245 /* Clear space for the next TInsn on the IStack and return a pointer
11246 to it. It is an error to call this if istack_full () is TRUE. */
11249 istack_push_space (IStack
*stack
)
11251 int rec
= stack
->ninsn
;
11253 gas_assert (!istack_full (stack
));
11254 insn
= &stack
->insn
[rec
];
11261 /* Remove the last pushed instruction. It is an error to call this if
11262 istack_empty () returns TRUE. */
11265 istack_pop (IStack
*stack
)
11267 int rec
= stack
->ninsn
- 1;
11268 gas_assert (!istack_empty (stack
));
11270 tinsn_init (&stack
->insn
[rec
]);
11274 /* TInsn functions. */
11277 tinsn_init (TInsn
*dst
)
11279 memset (dst
, 0, sizeof (TInsn
));
11283 /* Return TRUE if ANY of the operands in the insn are symbolic. */
11286 tinsn_has_symbolic_operands (const TInsn
*insn
)
11289 int n
= insn
->ntok
;
11291 gas_assert (insn
->insn_type
== ITYPE_INSN
);
11293 for (i
= 0; i
< n
; ++i
)
11295 switch (insn
->tok
[i
].X_op
)
11309 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
11311 xtensa_isa isa
= xtensa_default_isa
;
11313 int n
= insn
->ntok
;
11315 gas_assert (insn
->insn_type
== ITYPE_INSN
);
11317 for (i
= 0; i
< n
; ++i
)
11319 switch (insn
->tok
[i
].X_op
)
11327 /* Errors for these types are caught later. */
11332 /* Symbolic immediates are only allowed on the last immediate
11333 operand. At this time, CONST16 is the only opcode where we
11334 support non-PC-relative relocations. */
11335 if (i
!= get_relaxable_immed (insn
->opcode
)
11336 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
11337 && insn
->opcode
!= xtensa_const16_opcode
))
11339 as_bad (_("invalid symbolic operand"));
11348 /* For assembly code with complex expressions (e.g. subtraction),
11349 we have to build them in the literal pool so that
11350 their results are calculated correctly after relaxation.
11351 The relaxation only handles expressions that
11352 boil down to SYMBOL + OFFSET. */
11355 tinsn_has_complex_operands (const TInsn
*insn
)
11358 int n
= insn
->ntok
;
11359 gas_assert (insn
->insn_type
== ITYPE_INSN
);
11360 for (i
= 0; i
< n
; ++i
)
11362 switch (insn
->tok
[i
].X_op
)
11378 /* Encode a TInsn opcode and its constant operands into slotbuf.
11379 Return TRUE if there is a symbol in the immediate field. This
11380 function assumes that:
11381 1) The number of operands are correct.
11382 2) The insn_type is ITYPE_INSN.
11383 3) The opcode can be encoded in the specified format and slot.
11384 4) Operands are either O_constant or O_symbol, and all constants fit. */
11387 tinsn_to_slotbuf (xtensa_format fmt
,
11390 xtensa_insnbuf slotbuf
)
11392 xtensa_isa isa
= xtensa_default_isa
;
11393 xtensa_opcode opcode
= tinsn
->opcode
;
11394 bfd_boolean has_fixup
= FALSE
;
11395 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11398 gas_assert (tinsn
->insn_type
== ITYPE_INSN
);
11399 if (noperands
!= tinsn
->ntok
)
11400 as_fatal (_("operand number mismatch"));
11402 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
11404 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
11405 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
11409 for (i
= 0; i
< noperands
; i
++)
11411 expressionS
*expr
= &tinsn
->tok
[i
];
11417 switch (expr
->X_op
)
11420 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11422 /* The register number has already been checked in
11423 expression_maybe_register, so we don't need to check here. */
11424 opnd_value
= expr
->X_add_number
;
11425 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11426 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
11429 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
11433 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11435 as_where (&file_name
, &line
);
11436 /* It is a constant and we called this function
11437 then we have to try to fit it. */
11438 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
11439 expr
->X_add_number
, file_name
, line
);
11452 /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded
11453 into a multi-slot instruction, fill the other slots with NOPs.
11454 Return TRUE if there is a symbol in the immediate field. See also the
11455 assumptions listed for tinsn_to_slotbuf. */
11458 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
11460 static xtensa_insnbuf slotbuf
= 0;
11461 static vliw_insn vinsn
;
11462 xtensa_isa isa
= xtensa_default_isa
;
11463 bfd_boolean has_fixup
= FALSE
;
11468 slotbuf
= xtensa_insnbuf_alloc (isa
);
11469 xg_init_vinsn (&vinsn
);
11472 xg_clear_vinsn (&vinsn
);
11474 bundle_tinsn (tinsn
, &vinsn
);
11476 xtensa_format_encode (isa
, vinsn
.format
, insnbuf
);
11478 for (i
= 0; i
< vinsn
.num_slots
; i
++)
11480 /* Only one slot may have a fix-up because the rest contains NOPs. */
11482 tinsn_to_slotbuf (vinsn
.format
, i
, &vinsn
.slots
[i
], vinsn
.slotbuf
[i
]);
11483 xtensa_format_set_slot (isa
, vinsn
.format
, i
, insnbuf
, vinsn
.slotbuf
[i
]);
11490 /* Check the instruction arguments. Return TRUE on failure. */
11493 tinsn_check_arguments (const TInsn
*insn
)
11495 xtensa_isa isa
= xtensa_default_isa
;
11496 xtensa_opcode opcode
= insn
->opcode
;
11497 xtensa_regfile t1_regfile
, t2_regfile
;
11498 int t1_reg
, t2_reg
;
11499 int t1_base_reg
, t1_last_reg
;
11500 int t2_base_reg
, t2_last_reg
;
11501 char t1_inout
, t2_inout
;
11504 if (opcode
== XTENSA_UNDEFINED
)
11506 as_bad (_("invalid opcode"));
11510 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
11512 as_bad (_("too few operands"));
11516 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
11518 as_bad (_("too many operands"));
11522 /* Check registers. */
11523 for (j
= 0; j
< insn
->ntok
; j
++)
11525 if (xtensa_operand_is_register (isa
, insn
->opcode
, j
) != 1)
11528 t2_regfile
= xtensa_operand_regfile (isa
, insn
->opcode
, j
);
11529 t2_base_reg
= insn
->tok
[j
].X_add_number
;
11531 = t2_base_reg
+ xtensa_operand_num_regs (isa
, insn
->opcode
, j
);
11533 for (i
= 0; i
< insn
->ntok
; i
++)
11538 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) != 1)
11541 t1_regfile
= xtensa_operand_regfile (isa
, insn
->opcode
, i
);
11543 if (t1_regfile
!= t2_regfile
)
11546 t1_inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
11547 t2_inout
= xtensa_operand_inout (isa
, insn
->opcode
, j
);
11549 t1_base_reg
= insn
->tok
[i
].X_add_number
;
11550 t1_last_reg
= (t1_base_reg
11551 + xtensa_operand_num_regs (isa
, insn
->opcode
, i
));
11553 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
11555 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
11557 if (t1_reg
!= t2_reg
)
11560 if (t1_inout
!= 'i' && t2_inout
!= 'i')
11562 as_bad (_("multiple writes to the same register"));
11573 /* Load an instruction from its encoded form. */
11576 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
11580 xg_init_vinsn (&vinsn
);
11581 vinsn_from_chars (&vinsn
, f
);
11583 *tinsn
= vinsn
.slots
[slot
];
11584 xg_free_vinsn (&vinsn
);
11589 tinsn_from_insnbuf (TInsn
*tinsn
,
11590 xtensa_insnbuf slotbuf
,
11595 xtensa_isa isa
= xtensa_default_isa
;
11597 /* Find the immed. */
11598 tinsn_init (tinsn
);
11599 tinsn
->insn_type
= ITYPE_INSN
;
11600 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
11601 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
11602 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
11603 for (i
= 0; i
< tinsn
->ntok
; i
++)
11605 set_expr_const (&tinsn
->tok
[i
],
11606 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
11607 tinsn
->opcode
, i
));
11612 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
11615 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
11617 xtensa_opcode opcode
= tinsn
->opcode
;
11620 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
11622 opnum
= get_relaxable_immed (opcode
);
11623 gas_assert (opnum
>= 0);
11624 set_expr_symbol_offset (&tinsn
->tok
[opnum
],
11625 fragP
->tc_frag_data
.slot_symbols
[slot
],
11626 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11628 tinsn
->extra_arg
= fragP
->tc_frag_data
.free_reg
[slot
];
11633 get_num_stack_text_bytes (IStack
*istack
)
11636 int text_bytes
= 0;
11638 for (i
= 0; i
< istack
->ninsn
; i
++)
11640 TInsn
*tinsn
= &istack
->insn
[i
];
11641 if (tinsn
->insn_type
== ITYPE_INSN
)
11642 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
11649 get_num_stack_literal_bytes (IStack
*istack
)
11654 for (i
= 0; i
< istack
->ninsn
; i
++)
11656 TInsn
*tinsn
= &istack
->insn
[i
];
11657 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
11664 /* vliw_insn functions. */
11667 xg_init_vinsn (vliw_insn
*v
)
11670 xtensa_isa isa
= xtensa_default_isa
;
11672 xg_clear_vinsn (v
);
11674 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
11675 if (v
->insnbuf
== NULL
)
11676 as_fatal (_("out of memory"));
11678 for (i
= 0; i
< MAX_SLOTS
; i
++)
11680 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
11681 if (v
->slotbuf
[i
] == NULL
)
11682 as_fatal (_("out of memory"));
11688 xg_clear_vinsn (vliw_insn
*v
)
11692 memset (v
, 0, offsetof (vliw_insn
, insnbuf
));
11694 v
->format
= XTENSA_UNDEFINED
;
11696 v
->inside_bundle
= FALSE
;
11698 if (xt_saved_debug_type
!= DEBUG_NONE
)
11699 debug_type
= xt_saved_debug_type
;
11701 for (i
= 0; i
< MAX_SLOTS
; i
++)
11702 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
11707 xg_copy_vinsn (vliw_insn
*dst
, vliw_insn
*src
)
11710 offsetof(vliw_insn
, slots
) + src
->num_slots
* sizeof(TInsn
));
11711 dst
->insnbuf
= src
->insnbuf
;
11712 memcpy (dst
->slotbuf
, src
->slotbuf
, src
->num_slots
* sizeof(xtensa_insnbuf
));
11717 vinsn_has_specific_opcodes (vliw_insn
*v
)
11721 for (i
= 0; i
< v
->num_slots
; i
++)
11723 if (v
->slots
[i
].is_specific_opcode
)
11731 xg_free_vinsn (vliw_insn
*v
)
11734 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
11735 for (i
= 0; i
< MAX_SLOTS
; i
++)
11736 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
11740 /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic
11741 operands. See also the assumptions listed for tinsn_to_slotbuf. */
11744 vinsn_to_insnbuf (vliw_insn
*vinsn
,
11747 bfd_boolean record_fixup
)
11749 xtensa_isa isa
= xtensa_default_isa
;
11750 xtensa_format fmt
= vinsn
->format
;
11751 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
11753 bfd_boolean has_fixup
= FALSE
;
11755 xtensa_format_encode (isa
, fmt
, insnbuf
);
11757 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
11759 TInsn
*tinsn
= &vinsn
->slots
[slot
];
11760 expressionS
*extra_arg
= &tinsn
->extra_arg
;
11761 bfd_boolean tinsn_has_fixup
=
11762 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
11763 vinsn
->slotbuf
[slot
]);
11765 xtensa_format_set_slot (isa
, fmt
, slot
,
11766 insnbuf
, vinsn
->slotbuf
[slot
]);
11767 if (extra_arg
->X_op
!= O_illegal
&& extra_arg
->X_op
!= O_register
)
11769 if (vinsn
->num_slots
!= 1)
11770 as_bad (_("TLS relocation not allowed in FLIX bundle"));
11771 else if (record_fixup
)
11772 /* Instructions that generate TLS relocations should always be
11773 relaxed in the front-end. If "record_fixup" is set, then this
11774 function is being called during back-end relaxation, so flag
11775 the unexpected behavior as an error. */
11776 as_bad (_("unexpected TLS relocation"));
11778 fix_new (fragP
, frag_offset
- fragP
->fr_literal
,
11779 xtensa_format_length (isa
, fmt
),
11780 extra_arg
->X_add_symbol
, extra_arg
->X_add_number
,
11781 FALSE
, map_operator_to_reloc (extra_arg
->X_op
, FALSE
));
11783 if (tinsn_has_fixup
)
11786 xtensa_opcode opcode
= tinsn
->opcode
;
11787 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11790 for (i
= 0; i
< noperands
; i
++)
11792 expressionS
* expr
= &tinsn
->tok
[i
];
11793 switch (expr
->X_op
)
11798 if (get_relaxable_immed (opcode
) == i
)
11800 /* Add a fix record for the instruction, except if this
11801 function is being called prior to relaxation, i.e.,
11802 if record_fixup is false, and the instruction might
11803 be relaxed later. */
11805 || tinsn
->is_specific_opcode
11806 || !xg_is_relaxable_insn (tinsn
, 0))
11808 xg_add_opcode_fix (tinsn
, i
, fmt
, slot
, expr
, fragP
,
11809 frag_offset
- fragP
->fr_literal
);
11813 if (expr
->X_op
!= O_symbol
)
11814 as_bad (_("invalid operand"));
11815 tinsn
->symbol
= expr
->X_add_symbol
;
11816 tinsn
->offset
= expr
->X_add_number
;
11820 as_bad (_("symbolic operand not allowed"));
11828 as_bad (_("expression too complex"));
11840 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
11842 static xtensa_insnbuf insnbuf
= NULL
;
11843 static xtensa_insnbuf slotbuf
= NULL
;
11846 xtensa_isa isa
= xtensa_default_isa
;
11850 insnbuf
= xtensa_insnbuf_alloc (isa
);
11851 slotbuf
= xtensa_insnbuf_alloc (isa
);
11854 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) f
, 0);
11855 fmt
= xtensa_format_decode (isa
, insnbuf
);
11856 if (fmt
== XTENSA_UNDEFINED
)
11857 as_fatal (_("cannot decode instruction format"));
11858 vinsn
->format
= fmt
;
11859 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
11861 for (i
= 0; i
< vinsn
->num_slots
; i
++)
11863 TInsn
*tinsn
= &vinsn
->slots
[i
];
11864 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
11865 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
11870 /* Expression utilities. */
11872 /* Return TRUE if the expression is an integer constant. */
11875 expr_is_const (const expressionS
*s
)
11877 return (s
->X_op
== O_constant
);
11881 /* Get the expression constant.
11882 Calling this is illegal if expr_is_const () returns TRUE. */
11885 get_expr_const (const expressionS
*s
)
11887 gas_assert (expr_is_const (s
));
11888 return s
->X_add_number
;
11892 /* Set the expression to a constant value. */
11895 set_expr_const (expressionS
*s
, offsetT val
)
11897 s
->X_op
= O_constant
;
11898 s
->X_add_number
= val
;
11899 s
->X_add_symbol
= NULL
;
11900 s
->X_op_symbol
= NULL
;
11905 expr_is_register (const expressionS
*s
)
11907 return (s
->X_op
== O_register
);
11911 /* Get the expression constant.
11912 Calling this is illegal if expr_is_const () returns TRUE. */
11915 get_expr_register (const expressionS
*s
)
11917 gas_assert (expr_is_register (s
));
11918 return s
->X_add_number
;
11922 /* Set the expression to a symbol + constant offset. */
11925 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
11927 s
->X_op
= O_symbol
;
11928 s
->X_add_symbol
= sym
;
11929 s
->X_op_symbol
= NULL
; /* unused */
11930 s
->X_add_number
= offset
;
11934 /* Return TRUE if the two expressions are equal. */
11937 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
11939 if (s1
->X_op
!= s2
->X_op
)
11941 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
11943 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
11945 if (s1
->X_add_number
!= s2
->X_add_number
)
11952 copy_expr (expressionS
*dst
, const expressionS
*src
)
11954 memcpy (dst
, src
, sizeof (expressionS
));
11958 /* Support for the "--rename-section" option. */
11960 struct rename_section_struct
11964 struct rename_section_struct
*next
;
11967 static struct rename_section_struct
*section_rename
;
11970 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
11971 entries to the section_rename list. Note: Specifying multiple
11972 renamings separated by colons is not documented and is retained only
11973 for backward compatibility. */
11976 build_section_rename (const char *arg
)
11978 struct rename_section_struct
*r
;
11979 char *this_arg
= NULL
;
11980 char *next_arg
= NULL
;
11982 for (this_arg
= xstrdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
11984 char *old_name
, *new_name
;
11988 next_arg
= strchr (this_arg
, ':');
11996 old_name
= this_arg
;
11997 new_name
= strchr (this_arg
, '=');
11999 if (*old_name
== '\0')
12001 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
12004 if (!new_name
|| new_name
[1] == '\0')
12006 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
12013 /* Check for invalid section renaming. */
12014 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
12016 if (strcmp (r
->old_name
, old_name
) == 0)
12017 as_bad (_("section %s renamed multiple times"), old_name
);
12018 if (strcmp (r
->new_name
, new_name
) == 0)
12019 as_bad (_("multiple sections remapped to output section %s"),
12024 r
= (struct rename_section_struct
*)
12025 xmalloc (sizeof (struct rename_section_struct
));
12026 r
->old_name
= xstrdup (old_name
);
12027 r
->new_name
= xstrdup (new_name
);
12028 r
->next
= section_rename
;
12029 section_rename
= r
;
12035 xtensa_section_rename (char *name
)
12037 struct rename_section_struct
*r
= section_rename
;
12039 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
12041 if (strcmp (r
->old_name
, name
) == 0)
12042 return r
->new_name
;