1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright 2003, 2004, 2005 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330, Boston,
19 MA 02111-1307, USA. */
25 #include "safe-ctype.h"
26 #include "tc-xtensa.h"
29 #include "xtensa-relax.h"
30 #include "xtensa-istack.h"
31 #include "dwarf2dbg.h"
32 #include "struc-symbol.h"
33 #include "xtensa-config.h"
36 #define uint32 unsigned int
39 #define int32 signed int
44 Naming conventions (used somewhat inconsistently):
45 The xtensa_ functions are exported
46 The xg_ functions are internal
48 We also have a couple of different extensibility mechanisms.
49 1) The idiom replacement:
50 This is used when a line is first parsed to
51 replace an instruction pattern with another instruction
52 It is currently limited to replacements of instructions
53 with constant operands.
54 2) The xtensa-relax.c mechanism that has stronger instruction
55 replacement patterns. When an instruction's immediate field
56 does not fit the next instruction sequence is attempted.
57 In addition, "narrow" opcodes are supported this way. */
60 /* Define characters with special meanings to GAS. */
61 const char comment_chars
[] = "#";
62 const char line_comment_chars
[] = "#";
63 const char line_separator_chars
[] = ";";
64 const char EXP_CHARS
[] = "eE";
65 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
68 /* Flags to indicate whether the hardware supports the density and
69 absolute literals options. */
71 bfd_boolean density_supported
= XCHAL_HAVE_DENSITY
;
72 bfd_boolean absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
74 /* Maximum width we would pad an unreachable frag to get alignment. */
75 #define UNREACHABLE_MAX_WIDTH 8
77 static vliw_insn cur_vinsn
;
79 unsigned xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
81 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
83 /* Some functions are only valid in the front end. This variable
84 allows us to assert that we haven't crossed over into the
86 static bfd_boolean past_xtensa_end
= FALSE
;
88 /* Flags for properties of the last instruction in a segment. */
89 #define FLAG_IS_A0_WRITER 0x1
90 #define FLAG_IS_BAD_LOOPEND 0x2
93 /* We define a special segment names ".literal" to place literals
94 into. The .fini and .init sections are special because they
95 contain code that is moved together by the linker. We give them
96 their own special .fini.literal and .init.literal sections. */
98 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
99 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
100 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
101 #define INIT_SECTION_NAME xtensa_section_rename (".init")
102 #define FINI_LITERAL_SECTION_NAME xtensa_section_rename (".fini.literal")
103 #define INIT_LITERAL_SECTION_NAME xtensa_section_rename (".init.literal")
106 /* This type is used for the directive_stack to keep track of the
107 state of the literal collection pools. */
109 typedef struct lit_state_struct
111 const char *lit_seg_name
;
112 const char *lit4_seg_name
;
113 const char *init_lit_seg_name
;
114 const char *fini_lit_seg_name
;
121 static lit_state default_lit_sections
;
124 /* We keep lists of literal segments. The seg_list type is the node
125 for such a list. The *_literal_head locals are the heads of the
126 various lists. All of these lists have a dummy node at the start. */
128 typedef struct seg_list_struct
130 struct seg_list_struct
*next
;
134 static seg_list literal_head_h
;
135 static seg_list
*literal_head
= &literal_head_h
;
136 static seg_list init_literal_head_h
;
137 static seg_list
*init_literal_head
= &init_literal_head_h
;
138 static seg_list fini_literal_head_h
;
139 static seg_list
*fini_literal_head
= &fini_literal_head_h
;
142 /* Lists of symbols. We keep a list of symbols that label the current
143 instruction, so that we can adjust the symbols when inserting alignment
144 for various instructions. We also keep a list of all the symbols on
145 literals, so that we can fix up those symbols when the literals are
146 later moved into the text sections. */
148 typedef struct sym_list_struct
150 struct sym_list_struct
*next
;
154 static sym_list
*insn_labels
= NULL
;
155 static sym_list
*free_insn_labels
= NULL
;
156 static sym_list
*saved_insn_labels
= NULL
;
158 static sym_list
*literal_syms
;
161 /* Flags to determine whether to prefer const16 or l32r
162 if both options are available. */
163 int prefer_const16
= 0;
166 /* Global flag to indicate when we are emitting literals. */
167 int generating_literals
= 0;
169 /* The following PROPERTY table definitions are copied from
170 <elf/xtensa.h> and must be kept in sync with the code there. */
172 /* Flags in the property tables to specify whether blocks of memory
173 are literals, instructions, data, or unreachable. For
174 instructions, blocks that begin loop targets and branch targets are
175 designated. Blocks that do not allow density, instruction
176 reordering or transformation are also specified. Finally, for
177 branch targets, branch target alignment priority is included.
178 Alignment of the next block is specified in the current block
179 and the size of the current block does not include any fill required
180 to align to the next block. */
182 #define XTENSA_PROP_LITERAL 0x00000001
183 #define XTENSA_PROP_INSN 0x00000002
184 #define XTENSA_PROP_DATA 0x00000004
185 #define XTENSA_PROP_UNREACHABLE 0x00000008
186 /* Instruction only properties at beginning of code. */
187 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
188 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
189 /* Instruction only properties about code. */
190 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
191 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
192 #define XTENSA_PROP_INSN_NO_TRANSFORM 0x00000100
194 /* Branch target alignment information. This transmits information
195 to the linker optimization about the priority of aligning a
196 particular block for branch target alignment: None, low priority,
197 high priority, or required. These only need to be checked in
198 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
201 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
202 case XTENSA_PROP_BT_ALIGN_NONE:
203 case XTENSA_PROP_BT_ALIGN_LOW:
204 case XTENSA_PROP_BT_ALIGN_HIGH:
205 case XTENSA_PROP_BT_ALIGN_REQUIRE:
207 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
209 /* No branch target alignment. */
210 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
211 /* Low priority branch target alignment. */
212 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
213 /* High priority branch target alignment. */
214 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
215 /* Required branch target alignment. */
216 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
218 #define GET_XTENSA_PROP_BT_ALIGN(flag) \
219 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
220 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
221 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
222 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
225 /* Alignment is specified in the block BEFORE the one that needs
226 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
227 get the required alignment specified as a power of 2. Use
228 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
229 alignment. Be careful of side effects since the SET will evaluate
230 flags twice. Also, note that the SIZE of a block in the property
231 table does not include the alignment size, so the alignment fill
232 must be calculated to determine if two blocks are contiguous.
233 TEXT_ALIGN is not currently implemented but is a placeholder for a
234 possible future implementation. */
236 #define XTENSA_PROP_ALIGN 0x00000800
238 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
240 #define GET_XTENSA_PROP_ALIGNMENT(flag) \
241 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
242 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
243 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
244 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
246 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
249 /* Structure for saving instruction and alignment per-fragment data
250 that will be written to the object file. This structure is
251 equivalent to the actual data that will be written out to the file
252 but is easier to use. We provide a conversion to file flags
253 in frag_flags_to_number. */
255 typedef struct frag_flags_struct frag_flags
;
257 struct frag_flags_struct
259 /* is_literal should only be used after xtensa_move_literals.
260 If you need to check if you are generating a literal fragment,
261 then use the generating_literals global. */
263 unsigned is_literal
: 1;
264 unsigned is_insn
: 1;
265 unsigned is_data
: 1;
266 unsigned is_unreachable
: 1;
270 unsigned is_loop_target
: 1;
271 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
272 unsigned bt_align_priority
: 2;
274 unsigned is_no_density
: 1;
275 /* no_longcalls flag does not need to be placed in the object file. */
276 /* is_specific_opcode implies no_transform. */
277 unsigned is_no_transform
: 1;
279 unsigned is_no_reorder
: 1;
281 /* Uses absolute literal addressing for l32r. */
282 unsigned is_abslit
: 1;
284 unsigned is_align
: 1;
285 unsigned alignment
: 5;
289 /* Structure for saving information about a block of property data
290 for frags that have the same flags. */
291 struct xtensa_block_info_struct
297 struct xtensa_block_info_struct
*next
;
301 /* Structure for saving the current state before emitting literals. */
302 typedef struct emit_state_struct
307 int generating_literals
;
311 /* Opcode placement information */
313 typedef unsigned long long bitfield
;
314 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
315 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
316 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
318 #define MAX_FORMATS 32
320 typedef struct op_placement_info_struct
323 /* A number describing how restrictive the issue is for this
324 opcode. For example, an opcode that fits lots of different
325 formats has a high freedom, as does an opcode that fits
326 only one format but many slots in that format. The most
327 restrictive is the opcode that fits only one slot in one
330 /* The single format (i.e., if the op can live in a bundle by itself),
331 narrowest format, and widest format the op can be bundled in
333 xtensa_format single
;
334 xtensa_format narrowest
;
335 xtensa_format widest
;
340 /* formats is a bitfield with the Nth bit set
341 if the opcode fits in the Nth xtensa_format. */
344 /* slots[N]'s Mth bit is set if the op fits in the
345 Mth slot of the Nth xtensa_format. */
346 bitfield slots
[MAX_FORMATS
];
348 /* A count of the number of slots in a given format
349 an op can fit (i.e., the bitcount of the slot field above). */
350 char slots_in_format
[MAX_FORMATS
];
352 } op_placement_info
, *op_placement_info_table
;
354 op_placement_info_table op_placement_table
;
357 /* Extra expression types. */
359 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
360 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
361 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
374 directive_literal_prefix
,
376 directive_absolute_literals
,
377 directive_last_directive
383 bfd_boolean can_be_negated
;
386 const directive_infoS directive_info
[] =
389 { "literal", FALSE
},
391 { "transform", TRUE
},
392 { "freeregs", FALSE
},
393 { "longcalls", TRUE
},
394 { "literal_prefix", FALSE
},
395 { "schedule", TRUE
},
396 { "absolute-literals", TRUE
}
399 bfd_boolean directive_state
[] =
403 #if !XCHAL_HAVE_DENSITY
408 TRUE
, /* transform */
409 FALSE
, /* freeregs */
410 FALSE
, /* longcalls */
411 FALSE
, /* literal_prefix */
413 #if XSHAL_USE_ABSOLUTE_LITERALS
414 TRUE
/* absolute_literals */
416 FALSE
/* absolute_literals */
421 /* Directive functions. */
423 static void xtensa_begin_directive (int);
424 static void xtensa_end_directive (int);
425 static void xtensa_dwarf2_directive_loc (int);
426 static void xtensa_literal_prefix (char const *, int);
427 static void xtensa_literal_position (int);
428 static void xtensa_literal_pseudo (int);
429 static void xtensa_frequency_pseudo (int);
430 static void xtensa_elf_cons (int);
432 /* Parsing and Idiom Translation. */
434 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
436 /* Various Other Internal Functions. */
438 static void xtensa_mark_literal_pool_location (void);
439 static addressT
get_expanded_loop_offset (xtensa_opcode
);
440 static fragS
*get_literal_pool_location (segT
);
441 static void set_literal_pool_location (segT
, fragS
*);
442 static void xtensa_set_frag_assembly_state (fragS
*);
443 static void finish_vinsn (vliw_insn
*);
444 static bfd_boolean
emit_single_op (TInsn
*);
445 static int total_frag_text_expansion (fragS
*);
447 /* Alignment Functions. */
449 static int get_text_align_power (unsigned);
450 static int get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
451 static int branch_align_power (segT
);
453 /* Helpers for xtensa_relax_frag(). */
455 static long relax_frag_add_nop (fragS
*);
457 /* Accessors for additional per-subsegment information. */
459 static unsigned get_last_insn_flags (segT
, subsegT
);
460 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
461 static float get_subseg_total_freq (segT
, subsegT
);
462 static float get_subseg_target_freq (segT
, subsegT
);
463 static void set_subseg_freq (segT
, subsegT
, float, float);
465 /* Segment list functions. */
467 static void xtensa_move_literals (void);
468 static void xtensa_reorder_segments (void);
469 static void xtensa_switch_to_literal_fragment (emit_state
*);
470 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
471 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
472 static void xtensa_restore_emit_state (emit_state
*);
473 static void cache_literal_section
474 (seg_list
*, const char *, segT
*, bfd_boolean
);
476 /* Import from elf32-xtensa.c in BFD library. */
478 extern char *xtensa_get_property_section_name (asection
*, const char *);
480 /* op_placement_info functions. */
482 static void init_op_placement_info_table (void);
483 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
484 static int xg_get_single_size (xtensa_opcode
);
485 static xtensa_format
xg_get_single_format (xtensa_opcode
);
487 /* TInsn and IStack functions. */
489 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
490 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
491 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
492 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
493 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
494 static void tinsn_from_chars (TInsn
*, char *, int);
495 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
496 static int get_num_stack_text_bytes (IStack
*);
497 static int get_num_stack_literal_bytes (IStack
*);
499 /* vliw_insn functions. */
501 static void xg_init_vinsn (vliw_insn
*);
502 static void xg_clear_vinsn (vliw_insn
*);
503 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
504 static void xg_free_vinsn (vliw_insn
*);
505 static bfd_boolean vinsn_to_insnbuf
506 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
507 static void vinsn_from_chars (vliw_insn
*, char *);
509 /* Expression Utilities. */
511 bfd_boolean
expr_is_const (const expressionS
*);
512 offsetT
get_expr_const (const expressionS
*);
513 void set_expr_const (expressionS
*, offsetT
);
514 bfd_boolean
expr_is_register (const expressionS
*);
515 offsetT
get_expr_register (const expressionS
*);
516 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
517 static void set_expr_symbol_offset_diff
518 (expressionS
*, symbolS
*, symbolS
*, offsetT
);
519 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
520 static void copy_expr (expressionS
*, const expressionS
*);
522 /* Section renaming. */
524 static void build_section_rename (const char *);
527 /* ISA imported from bfd. */
528 extern xtensa_isa xtensa_default_isa
;
530 extern int target_big_endian
;
532 static xtensa_opcode xtensa_addi_opcode
;
533 static xtensa_opcode xtensa_addmi_opcode
;
534 static xtensa_opcode xtensa_call0_opcode
;
535 static xtensa_opcode xtensa_call4_opcode
;
536 static xtensa_opcode xtensa_call8_opcode
;
537 static xtensa_opcode xtensa_call12_opcode
;
538 static xtensa_opcode xtensa_callx0_opcode
;
539 static xtensa_opcode xtensa_callx4_opcode
;
540 static xtensa_opcode xtensa_callx8_opcode
;
541 static xtensa_opcode xtensa_callx12_opcode
;
542 static xtensa_opcode xtensa_const16_opcode
;
543 static xtensa_opcode xtensa_entry_opcode
;
544 static xtensa_opcode xtensa_movi_opcode
;
545 static xtensa_opcode xtensa_movi_n_opcode
;
546 static xtensa_opcode xtensa_isync_opcode
;
547 static xtensa_opcode xtensa_jx_opcode
;
548 static xtensa_opcode xtensa_l32r_opcode
;
549 static xtensa_opcode xtensa_loop_opcode
;
550 static xtensa_opcode xtensa_loopnez_opcode
;
551 static xtensa_opcode xtensa_loopgtz_opcode
;
552 static xtensa_opcode xtensa_nop_opcode
;
553 static xtensa_opcode xtensa_nop_n_opcode
;
554 static xtensa_opcode xtensa_or_opcode
;
555 static xtensa_opcode xtensa_ret_opcode
;
556 static xtensa_opcode xtensa_ret_n_opcode
;
557 static xtensa_opcode xtensa_retw_opcode
;
558 static xtensa_opcode xtensa_retw_n_opcode
;
559 static xtensa_opcode xtensa_rsr_lcount_opcode
;
560 static xtensa_opcode xtensa_waiti_opcode
;
563 /* Command-line Options. */
565 bfd_boolean use_literal_section
= TRUE
;
566 static bfd_boolean align_targets
= TRUE
;
567 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
568 static bfd_boolean has_a0_b_retw
= FALSE
;
569 static bfd_boolean workaround_a0_b_retw
= FALSE
;
570 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
571 static bfd_boolean workaround_short_loop
= FALSE
;
572 static bfd_boolean maybe_has_short_loop
= FALSE
;
573 static bfd_boolean workaround_close_loop_end
= FALSE
;
574 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
576 /* When workaround_short_loops is TRUE, all loops with early exits must
577 have at least 3 instructions. workaround_all_short_loops is a modifier
578 to the workaround_short_loop flag. In addition to the
579 workaround_short_loop actions, all straightline loopgtz and loopnez
580 must have at least 3 instructions. */
582 static bfd_boolean workaround_all_short_loops
= FALSE
;
586 xtensa_setup_hw_workarounds (int earliest
, int latest
)
588 if (earliest
> latest
)
589 as_fatal (_("illegal range of target hardware versions"));
591 /* Enable all workarounds for pre-T1050.0 hardware. */
592 if (earliest
< 105000 || latest
< 105000)
594 workaround_a0_b_retw
|= TRUE
;
595 workaround_b_j_loop_end
|= TRUE
;
596 workaround_short_loop
|= TRUE
;
597 workaround_close_loop_end
|= TRUE
;
598 workaround_all_short_loops
|= TRUE
;
605 option_density
= OPTION_MD_BASE
,
612 option_no_link_relax
,
620 option_text_section_literals
,
621 option_no_text_section_literals
,
623 option_absolute_literals
,
624 option_no_absolute_literals
,
626 option_align_targets
,
627 option_no_align_targets
,
629 option_warn_unaligned_targets
,
634 option_workaround_a0_b_retw
,
635 option_no_workaround_a0_b_retw
,
637 option_workaround_b_j_loop_end
,
638 option_no_workaround_b_j_loop_end
,
640 option_workaround_short_loop
,
641 option_no_workaround_short_loop
,
643 option_workaround_all_short_loops
,
644 option_no_workaround_all_short_loops
,
646 option_workaround_close_loop_end
,
647 option_no_workaround_close_loop_end
,
649 option_no_workarounds
,
651 option_rename_section_name
,
654 option_prefer_const16
,
656 option_target_hardware
659 const char *md_shortopts
= "";
661 struct option md_longopts
[] =
663 { "density", no_argument
, NULL
, option_density
},
664 { "no-density", no_argument
, NULL
, option_no_density
},
666 /* Both "relax" and "generics" are deprecated and treated as equivalent
667 to the "transform" option. */
668 { "relax", no_argument
, NULL
, option_relax
},
669 { "no-relax", no_argument
, NULL
, option_no_relax
},
670 { "generics", no_argument
, NULL
, option_generics
},
671 { "no-generics", no_argument
, NULL
, option_no_generics
},
673 { "transform", no_argument
, NULL
, option_transform
},
674 { "no-transform", no_argument
, NULL
, option_no_transform
},
675 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
676 { "no-text-section-literals", no_argument
, NULL
,
677 option_no_text_section_literals
},
678 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
679 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
680 /* This option was changed from -align-target to -target-align
681 because it conflicted with the "-al" option. */
682 { "target-align", no_argument
, NULL
, option_align_targets
},
683 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
684 { "warn-unaligned-targets", no_argument
, NULL
,
685 option_warn_unaligned_targets
},
686 { "longcalls", no_argument
, NULL
, option_longcalls
},
687 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
689 { "no-workaround-a0-b-retw", no_argument
, NULL
,
690 option_no_workaround_a0_b_retw
},
691 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
693 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
694 option_no_workaround_b_j_loop_end
},
695 { "workaround-b-j-loop-end", no_argument
, NULL
,
696 option_workaround_b_j_loop_end
},
698 { "no-workaround-short-loops", no_argument
, NULL
,
699 option_no_workaround_short_loop
},
700 { "workaround-short-loops", no_argument
, NULL
,
701 option_workaround_short_loop
},
703 { "no-workaround-all-short-loops", no_argument
, NULL
,
704 option_no_workaround_all_short_loops
},
705 { "workaround-all-short-loop", no_argument
, NULL
,
706 option_workaround_all_short_loops
},
708 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
709 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
711 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
713 { "no-workaround-close-loop-end", no_argument
, NULL
,
714 option_no_workaround_close_loop_end
},
715 { "workaround-close-loop-end", no_argument
, NULL
,
716 option_workaround_close_loop_end
},
718 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
720 { "link-relax", no_argument
, NULL
, option_link_relax
},
721 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
723 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
725 { NULL
, no_argument
, NULL
, 0 }
728 size_t md_longopts_size
= sizeof md_longopts
;
732 md_parse_option (int c
, char *arg
)
737 as_warn (_("--density option is ignored"));
739 case option_no_density
:
740 as_warn (_("--no-density option is ignored"));
742 case option_link_relax
:
745 case option_no_link_relax
:
748 case option_generics
:
749 as_warn (_("--generics is deprecated; use --transform instead"));
750 return md_parse_option (option_transform
, arg
);
751 case option_no_generics
:
752 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
753 return md_parse_option (option_no_transform
, arg
);
755 as_warn (_("--relax is deprecated; use --transform instead"));
756 return md_parse_option (option_transform
, arg
);
757 case option_no_relax
:
758 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
759 return md_parse_option (option_no_transform
, arg
);
760 case option_longcalls
:
761 directive_state
[directive_longcalls
] = TRUE
;
763 case option_no_longcalls
:
764 directive_state
[directive_longcalls
] = FALSE
;
766 case option_text_section_literals
:
767 use_literal_section
= FALSE
;
769 case option_no_text_section_literals
:
770 use_literal_section
= TRUE
;
772 case option_absolute_literals
:
773 if (!absolute_literals_supported
)
775 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
778 directive_state
[directive_absolute_literals
] = TRUE
;
780 case option_no_absolute_literals
:
781 directive_state
[directive_absolute_literals
] = FALSE
;
784 case option_workaround_a0_b_retw
:
785 workaround_a0_b_retw
= TRUE
;
787 case option_no_workaround_a0_b_retw
:
788 workaround_a0_b_retw
= FALSE
;
790 case option_workaround_b_j_loop_end
:
791 workaround_b_j_loop_end
= TRUE
;
793 case option_no_workaround_b_j_loop_end
:
794 workaround_b_j_loop_end
= FALSE
;
797 case option_workaround_short_loop
:
798 workaround_short_loop
= TRUE
;
800 case option_no_workaround_short_loop
:
801 workaround_short_loop
= FALSE
;
804 case option_workaround_all_short_loops
:
805 workaround_all_short_loops
= TRUE
;
807 case option_no_workaround_all_short_loops
:
808 workaround_all_short_loops
= FALSE
;
811 case option_workaround_close_loop_end
:
812 workaround_close_loop_end
= TRUE
;
814 case option_no_workaround_close_loop_end
:
815 workaround_close_loop_end
= FALSE
;
818 case option_no_workarounds
:
819 workaround_a0_b_retw
= FALSE
;
820 workaround_b_j_loop_end
= FALSE
;
821 workaround_short_loop
= FALSE
;
822 workaround_all_short_loops
= FALSE
;
823 workaround_close_loop_end
= FALSE
;
826 case option_align_targets
:
827 align_targets
= TRUE
;
829 case option_no_align_targets
:
830 align_targets
= FALSE
;
833 case option_warn_unaligned_targets
:
834 warn_unaligned_branch_targets
= TRUE
;
837 case option_rename_section_name
:
838 build_section_rename (arg
);
842 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
843 should be emitted or not. FIXME: Not implemented. */
846 case option_prefer_l32r
:
848 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
852 case option_prefer_const16
:
854 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
858 case option_target_hardware
:
860 int earliest
, latest
= 0;
861 if (*arg
== 0 || *arg
== '-')
862 as_fatal (_("invalid target hardware version"));
864 earliest
= strtol (arg
, &arg
, 0);
868 else if (*arg
== '-')
871 as_fatal (_("invalid target hardware version"));
872 latest
= strtol (arg
, &arg
, 0);
875 as_fatal (_("invalid target hardware version"));
877 xtensa_setup_hw_workarounds (earliest
, latest
);
881 case option_transform
:
882 /* This option has no affect other than to use the defaults,
883 which are already set. */
886 case option_no_transform
:
887 /* This option turns off all transformations of any kind.
888 However, because we want to preserve the state of other
889 directives, we only change its own field. Thus, before
890 you perform any transformation, always check if transform
891 is available. If you use the functions we provide for this
892 purpose, you will be ok. */
893 directive_state
[directive_transform
] = FALSE
;
903 md_show_usage (FILE *stream
)
907 --[no-]text-section-literals\n\
908 [Do not] put literals in the text section\n\
909 --[no-]absolute-literals\n\
910 [Do not] default to use non-PC-relative literals\n\
911 --[no-]target-align [Do not] try to align branch targets\n\
912 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
913 --[no-]transform [Do not] transform instructions\n\
914 --rename-section old=new Rename section 'old' to 'new'\n", stream
);
918 /* Functions related to the list of current label symbols. */
921 xtensa_add_insn_label (symbolS
*sym
)
925 if (!free_insn_labels
)
926 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
929 l
= free_insn_labels
;
930 free_insn_labels
= l
->next
;
934 l
->next
= insn_labels
;
940 xtensa_clear_insn_labels (void)
944 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
951 /* The "loops_ok" argument is provided to allow ignoring labels that
952 define loop ends. This fixes a bug where the NOPs to align a
953 loop opcode were included in a previous zero-cost loop:
972 This argument is used to prevent moving the NOP to before the
973 loop-end label, which is what you want in this special case. */
976 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
, bfd_boolean loops_ok
)
980 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
982 symbolS
*lit_sym
= lit
->sym
;
983 if (loops_ok
|| ! symbol_get_tc (lit_sym
)->is_loop_target
)
985 S_SET_VALUE (lit_sym
, new_offset
);
986 symbol_set_frag (lit_sym
, new_frag
);
992 /* Directive data and functions. */
994 typedef struct state_stackS_struct
996 directiveE directive
;
998 bfd_boolean old_state
;
1002 struct state_stackS_struct
*prev
;
1005 state_stackS
*directive_state_stack
;
1007 const pseudo_typeS md_pseudo_table
[] =
1009 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
1010 { "literal_position", xtensa_literal_position
, 0 },
1011 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
1012 { "long", xtensa_elf_cons
, 4 },
1013 { "word", xtensa_elf_cons
, 4 },
1014 { "short", xtensa_elf_cons
, 2 },
1015 { "begin", xtensa_begin_directive
, 0 },
1016 { "end", xtensa_end_directive
, 0 },
1017 { "loc", xtensa_dwarf2_directive_loc
, 0 },
1018 { "literal", xtensa_literal_pseudo
, 0 },
1019 { "frequency", xtensa_frequency_pseudo
, 0 },
1025 use_transform (void)
1027 /* After md_end, you should be checking frag by frag, rather
1028 than state directives. */
1029 assert (!past_xtensa_end
);
1030 return directive_state
[directive_transform
];
1035 do_align_targets (void)
1037 /* Do not use this function after md_end; just look at align_targets
1038 instead. There is no target-align directive, so alignment is either
1039 enabled for all frags or not done at all. */
1040 assert (!past_xtensa_end
);
1041 return align_targets
&& use_transform ();
1046 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1050 state_stackS
*stack
= (state_stackS
*) xmalloc (sizeof (state_stackS
));
1052 as_where (&file
, &line
);
1054 stack
->directive
= directive
;
1055 stack
->negated
= negated
;
1056 stack
->old_state
= directive_state
[directive
];
1059 stack
->datum
= datum
;
1060 stack
->prev
= directive_state_stack
;
1061 directive_state_stack
= stack
;
1063 directive_state
[directive
] = !negated
;
1068 directive_pop (directiveE
*directive
,
1069 bfd_boolean
*negated
,
1074 state_stackS
*top
= directive_state_stack
;
1076 if (!directive_state_stack
)
1078 as_bad (_("unmatched end directive"));
1079 *directive
= directive_none
;
1083 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1084 *directive
= top
->directive
;
1085 *negated
= top
->negated
;
1088 *datum
= top
->datum
;
1089 directive_state_stack
= top
->prev
;
1095 directive_balance (void)
1097 while (directive_state_stack
)
1099 directiveE directive
;
1100 bfd_boolean negated
;
1105 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1106 as_warn_where ((char *) file
, line
,
1107 _(".begin directive with no matching .end directive"));
1113 inside_directive (directiveE dir
)
1115 state_stackS
*top
= directive_state_stack
;
1117 while (top
&& top
->directive
!= dir
)
1120 return (top
!= NULL
);
1125 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1129 char *directive_string
;
1131 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1136 input_line_pointer
+= 3;
1139 len
= strspn (input_line_pointer
,
1140 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1142 /* This code is a hack to make .begin [no-][generics|relax] exactly
1143 equivalent to .begin [no-]transform. We should remove it when
1144 we stop accepting those options. */
1146 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1148 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1149 directive_string
= "transform";
1151 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1153 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1154 directive_string
= "transform";
1157 directive_string
= input_line_pointer
;
1159 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1161 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1163 input_line_pointer
+= len
;
1164 *directive
= (directiveE
) i
;
1165 if (*negated
&& !directive_info
[i
].can_be_negated
)
1166 as_bad (_("directive %s cannot be negated"),
1167 directive_info
[i
].name
);
1172 as_bad (_("unknown directive"));
1173 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1178 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1180 directiveE directive
;
1181 bfd_boolean negated
;
1186 get_directive (&directive
, &negated
);
1187 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1189 discard_rest_of_line ();
1193 if (cur_vinsn
.inside_bundle
)
1194 as_bad (_("directives are not valid inside bundles"));
1198 case directive_literal
:
1199 if (!inside_directive (directive_literal
))
1201 /* Previous labels go with whatever follows this directive, not with
1202 the literal, so save them now. */
1203 saved_insn_labels
= insn_labels
;
1206 as_warn (_(".begin literal is deprecated; use .literal instead"));
1207 state
= (emit_state
*) xmalloc (sizeof (emit_state
));
1208 xtensa_switch_to_literal_fragment (state
);
1209 directive_push (directive_literal
, negated
, state
);
1212 case directive_literal_prefix
:
1213 /* Have to flush pending output because a movi relaxed to an l32r
1214 might produce a literal. */
1215 md_flush_pending_output ();
1216 /* Check to see if the current fragment is a literal
1217 fragment. If it is, then this operation is not allowed. */
1218 if (generating_literals
)
1220 as_bad (_("cannot set literal_prefix inside literal fragment"));
1224 /* Allocate the literal state for this section and push
1225 onto the directive stack. */
1226 ls
= xmalloc (sizeof (lit_state
));
1229 *ls
= default_lit_sections
;
1231 directive_push (directive_literal_prefix
, negated
, ls
);
1233 /* Parse the new prefix from the input_line_pointer. */
1235 len
= strspn (input_line_pointer
,
1236 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1237 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1239 /* Process the new prefix. */
1240 xtensa_literal_prefix (input_line_pointer
, len
);
1242 /* Skip the name in the input line. */
1243 input_line_pointer
+= len
;
1246 case directive_freeregs
:
1247 /* This information is currently unused, but we'll accept the statement
1248 and just discard the rest of the line. This won't check the syntax,
1249 but it will accept every correct freeregs directive. */
1250 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1251 directive_push (directive_freeregs
, negated
, 0);
1254 case directive_schedule
:
1255 md_flush_pending_output ();
1256 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1257 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1258 directive_push (directive_schedule
, negated
, 0);
1259 xtensa_set_frag_assembly_state (frag_now
);
1262 case directive_density
:
1263 as_warn (_(".begin [no-]density is ignored"));
1266 case directive_absolute_literals
:
1267 md_flush_pending_output ();
1268 if (!absolute_literals_supported
&& !negated
)
1270 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1273 xtensa_set_frag_assembly_state (frag_now
);
1274 directive_push (directive
, negated
, 0);
1278 md_flush_pending_output ();
1279 xtensa_set_frag_assembly_state (frag_now
);
1280 directive_push (directive
, negated
, 0);
1284 demand_empty_rest_of_line ();
1289 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1291 directiveE begin_directive
, end_directive
;
1292 bfd_boolean begin_negated
, end_negated
;
1296 emit_state
**state_ptr
;
1299 if (cur_vinsn
.inside_bundle
)
1300 as_bad (_("directives are not valid inside bundles"));
1302 get_directive (&end_directive
, &end_negated
);
1304 md_flush_pending_output ();
1306 switch (end_directive
)
1308 case (directiveE
) XTENSA_UNDEFINED
:
1309 discard_rest_of_line ();
1312 case directive_density
:
1313 as_warn (_(".end [no-]density is ignored"));
1314 demand_empty_rest_of_line ();
1317 case directive_absolute_literals
:
1318 if (!absolute_literals_supported
&& !end_negated
)
1320 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1321 demand_empty_rest_of_line ();
1330 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1331 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1332 (const void **) state_ptr
);
1334 if (begin_directive
!= directive_none
)
1336 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1338 as_bad (_("does not match begin %s%s at %s:%d"),
1339 begin_negated
? "no-" : "",
1340 directive_info
[begin_directive
].name
, file
, line
);
1344 switch (end_directive
)
1346 case directive_literal
:
1347 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1348 xtensa_restore_emit_state (state
);
1349 xtensa_set_frag_assembly_state (frag_now
);
1351 if (!inside_directive (directive_literal
))
1353 /* Restore the list of current labels. */
1354 xtensa_clear_insn_labels ();
1355 insn_labels
= saved_insn_labels
;
1359 case directive_literal_prefix
:
1360 /* Restore the default collection sections from saved state. */
1361 s
= (lit_state
*) state
;
1364 if (use_literal_section
)
1365 default_lit_sections
= *s
;
1367 /* free the state storage */
1371 case directive_schedule
:
1372 case directive_freeregs
:
1376 xtensa_set_frag_assembly_state (frag_now
);
1382 demand_empty_rest_of_line ();
1386 /* Wrap dwarf2 functions so that we correctly support the .loc directive. */
1388 static bfd_boolean xtensa_loc_directive_seen
= FALSE
;
1391 xtensa_dwarf2_directive_loc (int x
)
1393 xtensa_loc_directive_seen
= TRUE
;
1394 dwarf2_directive_loc (x
);
1399 xtensa_dwarf2_emit_insn (int size
, struct dwarf2_line_info
*loc
)
1401 if (debug_type
!= DEBUG_DWARF2
&& ! xtensa_loc_directive_seen
)
1403 xtensa_loc_directive_seen
= FALSE
;
1404 dwarf2_gen_line_info (frag_now_fix () - size
, loc
);
1408 /* Place an aligned literal fragment at the current location. */
1411 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1413 md_flush_pending_output ();
1415 if (inside_directive (directive_literal
))
1416 as_warn (_(".literal_position inside literal directive; ignoring"));
1417 xtensa_mark_literal_pool_location ();
1419 demand_empty_rest_of_line ();
1420 xtensa_clear_insn_labels ();
1424 /* Support .literal label, expr, ... */
1427 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1430 char *p
, *base_name
;
1434 if (inside_directive (directive_literal
))
1436 as_bad (_(".literal not allowed inside .begin literal region"));
1437 ignore_rest_of_line ();
1441 md_flush_pending_output ();
1443 /* Previous labels go with whatever follows this directive, not with
1444 the literal, so save them now. */
1445 saved_insn_labels
= insn_labels
;
1448 /* If we are using text-section literals, then this is the right value... */
1451 base_name
= input_line_pointer
;
1453 xtensa_switch_to_literal_fragment (&state
);
1455 /* ...but if we aren't using text-section-literals, then we
1456 need to put them in the section we just switched to. */
1457 if (use_literal_section
|| directive_state
[directive_absolute_literals
])
1460 /* All literals are aligned to four-byte boundaries. */
1461 frag_align (2, 0, 0);
1462 record_alignment (now_seg
, 2);
1464 c
= get_symbol_end ();
1465 /* Just after name is now '\0'. */
1466 p
= input_line_pointer
;
1470 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1472 as_bad (_("expected comma or colon after symbol name; "
1473 "rest of line ignored"));
1474 ignore_rest_of_line ();
1475 xtensa_restore_emit_state (&state
);
1483 input_line_pointer
++; /* skip ',' or ':' */
1485 xtensa_elf_cons (4);
1487 xtensa_restore_emit_state (&state
);
1489 /* Restore the list of current labels. */
1490 xtensa_clear_insn_labels ();
1491 insn_labels
= saved_insn_labels
;
1496 xtensa_literal_prefix (char const *start
, int len
)
1498 char *name
, *linkonce_suffix
;
1499 char *newname
, *newname4
;
1500 size_t linkonce_len
;
1502 /* Get a null-terminated copy of the name. */
1503 name
= xmalloc (len
+ 1);
1506 strncpy (name
, start
, len
);
1509 /* Allocate the sections (interesting note: the memory pointing to
1510 the name is actually used for the name by the new section). */
1512 newname
= xmalloc (len
+ strlen (".literal") + 1);
1513 newname4
= xmalloc (len
+ strlen (".lit4") + 1);
1515 linkonce_len
= sizeof (".gnu.linkonce.") - 1;
1516 if (strncmp (name
, ".gnu.linkonce.", linkonce_len
) == 0
1517 && (linkonce_suffix
= strchr (name
+ linkonce_len
, '.')) != 0)
1519 strcpy (newname
, ".gnu.linkonce.literal");
1520 strcpy (newname4
, ".gnu.linkonce.lit4");
1522 strcat (newname
, linkonce_suffix
);
1523 strcat (newname4
, linkonce_suffix
);
1527 int suffix_pos
= len
;
1529 /* If the section name ends with ".text", then replace that suffix
1530 instead of appending an additional suffix. */
1531 if (len
>= 5 && strcmp (name
+ len
- 5, ".text") == 0)
1534 strcpy (newname
, name
);
1535 strcpy (newname4
, name
);
1537 strcpy (newname
+ suffix_pos
, ".literal");
1538 strcpy (newname4
+ suffix_pos
, ".lit4");
1541 /* Note that cache_literal_section does not create a segment if
1542 it already exists. */
1543 default_lit_sections
.lit_seg
= NULL
;
1544 default_lit_sections
.lit4_seg
= NULL
;
1546 /* Canonicalizing section names allows renaming literal
1547 sections to occur correctly. */
1548 default_lit_sections
.lit_seg_name
= tc_canonicalize_symbol_name (newname
);
1549 default_lit_sections
.lit4_seg_name
= tc_canonicalize_symbol_name (newname4
);
1555 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1558 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1560 float fall_through_f
, target_f
;
1562 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1563 if (fall_through_f
< 0)
1565 as_bad (_("fall through frequency must be greater than 0"));
1566 ignore_rest_of_line ();
1570 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1573 as_bad (_("branch target frequency must be greater than 0"));
1574 ignore_rest_of_line ();
1578 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1580 demand_empty_rest_of_line ();
1584 /* Like normal .long/.short/.word, except support @plt, etc.
1585 Clobbers input_line_pointer, checks end-of-line. */
1588 xtensa_elf_cons (int nbytes
)
1591 bfd_reloc_code_real_type reloc
;
1593 md_flush_pending_output ();
1595 if (cur_vinsn
.inside_bundle
)
1596 as_bad (_("directives are not valid inside bundles"));
1598 if (is_it_end_of_statement ())
1600 demand_empty_rest_of_line ();
1607 if (exp
.X_op
== O_symbol
1608 && *input_line_pointer
== '@'
1609 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1612 reloc_howto_type
*reloc_howto
=
1613 bfd_reloc_type_lookup (stdoutput
, reloc
);
1615 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1616 as_bad (_("unsupported relocation"));
1617 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1618 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1619 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1620 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1621 as_bad (_("opcode-specific %s relocation used outside "
1622 "an instruction"), reloc_howto
->name
);
1623 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1624 as_bad (_("%s relocations do not fit in %d bytes"),
1625 reloc_howto
->name
, nbytes
);
1628 char *p
= frag_more ((int) nbytes
);
1629 xtensa_set_frag_assembly_state (frag_now
);
1630 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1631 nbytes
, &exp
, 0, reloc
);
1635 emit_expr (&exp
, (unsigned int) nbytes
);
1637 while (*input_line_pointer
++ == ',');
1639 input_line_pointer
--; /* Put terminator back into stream. */
1640 demand_empty_rest_of_line ();
1644 /* Parsing and Idiom Translation. */
1646 /* Parse @plt, etc. and return the desired relocation. */
1647 static bfd_reloc_code_real_type
1648 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1654 bfd_reloc_code_real_type reloc
;
1662 struct map_bfd
*ptr
;
1664 #define MAP(str,reloc) { str, sizeof (str) - 1, reloc }
1666 static struct map_bfd mapping
[] =
1668 MAP ("l", BFD_RELOC_LO16
),
1669 MAP ("h", BFD_RELOC_HI16
),
1670 MAP ("plt", BFD_RELOC_XTENSA_PLT
),
1671 { (char *) 0, 0, BFD_RELOC_UNUSED
}
1675 return BFD_RELOC_NONE
;
1677 for (ch
= *str
, str2
= ident
;
1678 (str2
< ident
+ sizeof (ident
) - 1
1679 && (ISALNUM (ch
) || ch
== '@'));
1682 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1689 for (ptr
= &mapping
[0]; ptr
->length
> 0; ptr
++)
1690 if (ch
== ptr
->string
[0]
1691 && len
== ptr
->length
1692 && memcmp (ident
, ptr
->string
, ptr
->length
) == 0)
1694 /* Now check for "identifier@suffix+constant". */
1695 if (*str
== '-' || *str
== '+')
1697 char *orig_line
= input_line_pointer
;
1698 expressionS new_exp
;
1700 input_line_pointer
= str
;
1701 expression (&new_exp
);
1702 if (new_exp
.X_op
== O_constant
)
1704 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1705 str
= input_line_pointer
;
1708 if (&input_line_pointer
!= str_p
)
1709 input_line_pointer
= orig_line
;
1716 return BFD_RELOC_UNUSED
;
1721 expression_end (const char *name
)
1744 #define ERROR_REG_NUM ((unsigned) -1)
1747 tc_get_register (const char *prefix
)
1750 const char *next_expr
;
1751 const char *old_line_pointer
;
1754 old_line_pointer
= input_line_pointer
;
1756 if (*input_line_pointer
== '$')
1757 ++input_line_pointer
;
1759 /* Accept "sp" as a synonym for "a1". */
1760 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1761 && expression_end (input_line_pointer
+ 2))
1763 input_line_pointer
+= 2;
1764 return 1; /* AR[1] */
1767 while (*input_line_pointer
++ == *prefix
++)
1769 --input_line_pointer
;
1774 as_bad (_("bad register name: %s"), old_line_pointer
);
1775 return ERROR_REG_NUM
;
1778 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1780 as_bad (_("bad register number: %s"), input_line_pointer
);
1781 return ERROR_REG_NUM
;
1786 while (ISDIGIT ((int) *input_line_pointer
))
1787 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1789 if (!(next_expr
= expression_end (input_line_pointer
)))
1791 as_bad (_("bad register name: %s"), old_line_pointer
);
1792 return ERROR_REG_NUM
;
1795 input_line_pointer
= (char *) next_expr
;
1802 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1804 xtensa_isa isa
= xtensa_default_isa
;
1806 /* Check if this is an immediate operand. */
1807 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1809 bfd_reloc_code_real_type reloc
;
1810 segT t
= expression (tok
);
1811 if (t
== absolute_section
1812 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1814 assert (tok
->X_op
== O_constant
);
1815 tok
->X_op
= O_symbol
;
1816 tok
->X_add_symbol
= &abs_symbol
;
1819 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1820 && (reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1821 && (reloc
!= BFD_RELOC_NONE
))
1826 case BFD_RELOC_UNUSED
:
1827 as_bad (_("unsupported relocation"));
1830 case BFD_RELOC_XTENSA_PLT
:
1831 tok
->X_op
= O_pltrel
;
1834 case BFD_RELOC_LO16
:
1835 if (tok
->X_op
== O_constant
)
1836 tok
->X_add_number
&= 0xffff;
1841 case BFD_RELOC_HI16
:
1842 if (tok
->X_op
== O_constant
)
1843 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1852 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1853 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1855 if (reg
!= ERROR_REG_NUM
) /* Already errored */
1858 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
1859 as_bad (_("register number out of range"));
1862 tok
->X_op
= O_register
;
1863 tok
->X_add_symbol
= 0;
1864 tok
->X_add_number
= reg
;
1869 /* Split up the arguments for an opcode or pseudo-op. */
1872 tokenize_arguments (char **args
, char *str
)
1874 char *old_input_line_pointer
;
1875 bfd_boolean saw_comma
= FALSE
;
1876 bfd_boolean saw_arg
= FALSE
;
1877 bfd_boolean saw_colon
= FALSE
;
1879 char *arg_end
, *arg
;
1882 /* Save and restore input_line_pointer around this function. */
1883 old_input_line_pointer
= input_line_pointer
;
1884 input_line_pointer
= str
;
1886 while (*input_line_pointer
)
1889 switch (*input_line_pointer
)
1896 input_line_pointer
++;
1897 if (saw_comma
|| saw_colon
|| !saw_arg
)
1903 input_line_pointer
++;
1904 if (saw_comma
|| saw_colon
|| !saw_arg
)
1910 if (!saw_comma
&& !saw_colon
&& saw_arg
)
1913 arg_end
= input_line_pointer
+ 1;
1914 while (!expression_end (arg_end
))
1917 arg_len
= arg_end
- input_line_pointer
;
1918 arg
= (char *) xmalloc ((saw_colon
? 1 : 0) + arg_len
+ 1);
1919 args
[num_args
] = arg
;
1923 strncpy (arg
, input_line_pointer
, arg_len
);
1924 arg
[arg_len
] = '\0';
1926 input_line_pointer
= arg_end
;
1936 if (saw_comma
|| saw_colon
)
1938 input_line_pointer
= old_input_line_pointer
;
1943 as_bad (_("extra comma"));
1945 as_bad (_("extra colon"));
1947 as_bad (_("missing argument"));
1949 as_bad (_("missing comma or colon"));
1950 input_line_pointer
= old_input_line_pointer
;
1955 /* Parse the arguments to an opcode. Return TRUE on error. */
1958 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
1960 expressionS
*tok
, *last_tok
;
1961 xtensa_opcode opcode
= insn
->opcode
;
1962 bfd_boolean had_error
= TRUE
;
1963 xtensa_isa isa
= xtensa_default_isa
;
1964 int n
, num_regs
= 0;
1965 int opcode_operand_count
;
1966 int opnd_cnt
, last_opnd_cnt
;
1967 unsigned int next_reg
= 0;
1968 char *old_input_line_pointer
;
1970 if (insn
->insn_type
== ITYPE_LITERAL
)
1971 opcode_operand_count
= 1;
1973 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
1976 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
1978 /* Save and restore input_line_pointer around this function. */
1979 old_input_line_pointer
= input_line_pointer
;
1985 /* Skip invisible operands. */
1986 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
1992 for (n
= 0; n
< num_args
; n
++)
1994 input_line_pointer
= arg_strings
[n
];
1995 if (*input_line_pointer
== ':')
1997 xtensa_regfile opnd_rf
;
1998 input_line_pointer
++;
2001 assert (opnd_cnt
> 0);
2003 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
2005 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
2006 as_warn (_("incorrect register number, ignoring"));
2011 if (opnd_cnt
>= opcode_operand_count
)
2013 as_warn (_("too many arguments"));
2016 assert (opnd_cnt
< MAX_INSN_ARGS
);
2018 expression_maybe_register (opcode
, opnd_cnt
, tok
);
2019 next_reg
= tok
->X_add_number
+ 1;
2021 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
2023 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
2025 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
2026 /* minus 1 because we are seeing one right now */
2032 last_opnd_cnt
= opnd_cnt
;
2039 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
2043 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
2046 insn
->ntok
= tok
- insn
->tok
;
2050 input_line_pointer
= old_input_line_pointer
;
2056 get_invisible_operands (TInsn
*insn
)
2058 xtensa_isa isa
= xtensa_default_isa
;
2059 static xtensa_insnbuf slotbuf
= NULL
;
2061 xtensa_opcode opc
= insn
->opcode
;
2062 int slot
, opnd
, fmt_found
;
2066 slotbuf
= xtensa_insnbuf_alloc (isa
);
2068 /* Find format/slot where this can be encoded. */
2071 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2073 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2075 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2081 if (fmt_found
) break;
2086 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2090 /* First encode all the visible operands
2091 (to deal with shared field operands). */
2092 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2094 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2095 && (insn
->tok
[opnd
].X_op
== O_register
2096 || insn
->tok
[opnd
].X_op
== O_constant
))
2098 val
= insn
->tok
[opnd
].X_add_number
;
2099 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2100 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2104 /* Then pull out the values for the invisible ones. */
2105 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2107 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2109 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2110 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2111 insn
->tok
[opnd
].X_add_number
= val
;
2112 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2113 insn
->tok
[opnd
].X_op
= O_register
;
2115 insn
->tok
[opnd
].X_op
= O_constant
;
2124 xg_reverse_shift_count (char **cnt_argp
)
2126 char *cnt_arg
, *new_arg
;
2127 cnt_arg
= *cnt_argp
;
2129 /* replace the argument with "31-(argument)" */
2130 new_arg
= (char *) xmalloc (strlen (cnt_arg
) + 6);
2131 sprintf (new_arg
, "31-(%s)", cnt_arg
);
2134 *cnt_argp
= new_arg
;
2138 /* If "arg" is a constant expression, return non-zero with the value
2142 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2145 char *save_ptr
= input_line_pointer
;
2147 input_line_pointer
= arg
;
2149 input_line_pointer
= save_ptr
;
2151 if (exp
.X_op
== O_constant
)
2153 *valp
= exp
.X_add_number
;
2162 xg_replace_opname (char **popname
, char *newop
)
2165 *popname
= (char *) xmalloc (strlen (newop
) + 1);
2166 strcpy (*popname
, newop
);
2171 xg_check_num_args (int *pnum_args
,
2176 int num_args
= *pnum_args
;
2178 if (num_args
< expected_num
)
2180 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2181 num_args
, opname
, expected_num
);
2185 if (num_args
> expected_num
)
2187 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2188 num_args
, opname
, expected_num
);
2189 while (num_args
-- > expected_num
)
2191 free (arg_strings
[num_args
]);
2192 arg_strings
[num_args
] = 0;
2194 *pnum_args
= expected_num
;
2202 /* If the register is not specified as part of the opcode,
2203 then get it from the operand and move it to the opcode. */
2206 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2208 xtensa_isa isa
= xtensa_default_isa
;
2210 char *opname
, *new_opname
;
2211 const char *sr_name
;
2212 int is_user
, is_write
;
2213 bfd_boolean has_underbar
= FALSE
;
2218 has_underbar
= TRUE
;
2221 is_user
= (opname
[1] == 'u');
2222 is_write
= (opname
[0] == 'w');
2224 /* Opname == [rw]ur or [rwx]sr... */
2226 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2229 /* Check if the argument is a symbolic register name. */
2230 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2231 /* Handle WSR to "INTSET" as a special case. */
2232 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2233 && !strcasecmp (arg_strings
[1], "intset"))
2234 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2235 if (sr
== XTENSA_UNDEFINED
2236 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2238 /* Maybe it's a register number.... */
2240 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2242 as_bad (_("invalid register '%s' for '%s' instruction"),
2243 arg_strings
[1], opname
);
2246 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2247 if (sr
== XTENSA_UNDEFINED
)
2249 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2250 (long) val
, opname
);
2255 /* Remove the last argument, which is now part of the opcode. */
2256 free (arg_strings
[1]);
2260 /* Translate the opcode. */
2261 sr_name
= xtensa_sysreg_name (isa
, sr
);
2262 /* Another special case for "WSR.INTSET".... */
2263 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2265 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2266 sprintf (new_opname
, "%s%s.%s", (has_underbar
? "_" : ""),
2269 *popname
= new_opname
;
2276 xtensa_translate_old_userreg_ops (char **popname
)
2278 xtensa_isa isa
= xtensa_default_isa
;
2280 char *opname
, *new_opname
;
2281 const char *sr_name
;
2282 bfd_boolean has_underbar
= FALSE
;
2285 if (opname
[0] == '_')
2287 has_underbar
= TRUE
;
2291 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2292 if (sr
!= XTENSA_UNDEFINED
)
2294 /* The new default name ("nnn") is different from the old default
2295 name ("URnnn"). The old default is handled below, and we don't
2296 want to recognize [RW]nnn, so do nothing if the name is the (new)
2298 static char namebuf
[10];
2299 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2300 if (strcmp (namebuf
, opname
+ 1) == 0)
2308 /* Only continue if the reg name is "URnnn". */
2309 if (opname
[1] != 'u' || opname
[2] != 'r')
2311 val
= strtoul (opname
+ 3, &end
, 10);
2315 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2316 if (sr
== XTENSA_UNDEFINED
)
2318 as_bad (_("invalid register number (%ld) for '%s'"),
2319 (long) val
, opname
);
2324 /* Translate the opcode. */
2325 sr_name
= xtensa_sysreg_name (isa
, sr
);
2326 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2327 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2328 opname
[0], sr_name
);
2330 *popname
= new_opname
;
2337 xtensa_translate_zero_immed (char *old_op
,
2347 assert (opname
[0] != '_');
2349 if (strcmp (opname
, old_op
) != 0)
2352 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2354 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2356 xg_replace_opname (popname
, new_op
);
2357 free (arg_strings
[1]);
2358 arg_strings
[1] = arg_strings
[2];
2367 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2368 Returns non-zero if an error was found. */
2371 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2373 char *opname
= *popname
;
2374 bfd_boolean has_underbar
= FALSE
;
2376 if (cur_vinsn
.inside_bundle
)
2381 has_underbar
= TRUE
;
2385 if (strcmp (opname
, "mov") == 0)
2387 if (use_transform () && !has_underbar
&& density_supported
)
2388 xg_replace_opname (popname
, "mov.n");
2391 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2393 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2394 arg_strings
[2] = (char *) xmalloc (strlen (arg_strings
[1]) + 1);
2395 strcpy (arg_strings
[2], arg_strings
[1]);
2401 if (strcmp (opname
, "bbsi.l") == 0)
2403 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2405 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2406 if (target_big_endian
)
2407 xg_reverse_shift_count (&arg_strings
[1]);
2411 if (strcmp (opname
, "bbci.l") == 0)
2413 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2415 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2416 if (target_big_endian
)
2417 xg_reverse_shift_count (&arg_strings
[1]);
2421 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
2422 && strcmp (opname
, "nop") == 0)
2424 if (use_transform () && !has_underbar
&& density_supported
)
2425 xg_replace_opname (popname
, "nop.n");
2428 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2430 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2431 arg_strings
[0] = (char *) xmalloc (3);
2432 arg_strings
[1] = (char *) xmalloc (3);
2433 arg_strings
[2] = (char *) xmalloc (3);
2434 strcpy (arg_strings
[0], "a1");
2435 strcpy (arg_strings
[1], "a1");
2436 strcpy (arg_strings
[2], "a1");
2442 /* Recognize [RW]UR and [RWX]SR. */
2443 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2444 && (opname
[1] == 'u' || opname
[1] == 's'))
2445 || (opname
[0] == 'x' && opname
[1] == 's'))
2447 && opname
[3] == '\0')
2448 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2450 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2451 [RW]<name> if <name> is the non-default name of a user register. */
2452 if ((opname
[0] == 'r' || opname
[0] == 'w')
2453 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2454 return xtensa_translate_old_userreg_ops (popname
);
2456 /* Relax branches that don't allow comparisons against an immediate value
2457 of zero to the corresponding branches with implicit zero immediates. */
2458 if (!has_underbar
&& use_transform ())
2460 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2461 pnum_args
, arg_strings
))
2464 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2465 pnum_args
, arg_strings
))
2468 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2469 pnum_args
, arg_strings
))
2472 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2473 pnum_args
, arg_strings
))
2481 /* Functions for dealing with the Xtensa ISA. */
2483 /* Currently the assembler only allows us to use a single target per
2484 fragment. Because of this, only one operand for a given
2485 instruction may be symbolic. If there is a PC-relative operand,
2486 the last one is chosen. Otherwise, the result is the number of the
2487 last immediate operand, and if there are none of those, we fail and
2491 get_relaxable_immed (xtensa_opcode opcode
)
2493 int last_immed
= -1;
2496 if (opcode
== XTENSA_UNDEFINED
)
2499 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2500 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2502 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2504 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2506 if (last_immed
== -1
2507 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2514 static xtensa_opcode
2515 get_opcode_from_buf (const char *buf
, int slot
)
2517 static xtensa_insnbuf insnbuf
= NULL
;
2518 static xtensa_insnbuf slotbuf
= NULL
;
2519 xtensa_isa isa
= xtensa_default_isa
;
2524 insnbuf
= xtensa_insnbuf_alloc (isa
);
2525 slotbuf
= xtensa_insnbuf_alloc (isa
);
2528 xtensa_insnbuf_from_chars (isa
, insnbuf
, (const unsigned char *) buf
, 0);
2529 fmt
= xtensa_format_decode (isa
, insnbuf
);
2530 if (fmt
== XTENSA_UNDEFINED
)
2531 return XTENSA_UNDEFINED
;
2533 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2534 return XTENSA_UNDEFINED
;
2536 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2537 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2541 #ifdef TENSILICA_DEBUG
2543 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2546 xtensa_print_insn_table (void)
2548 int num_opcodes
, num_operands
;
2549 xtensa_opcode opcode
;
2550 xtensa_isa isa
= xtensa_default_isa
;
2552 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2553 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2556 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2557 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2558 for (opn
= 0; opn
< num_operands
; opn
++)
2560 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2562 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2564 xtensa_regfile opnd_rf
=
2565 xtensa_operand_regfile (isa
, opcode
, opn
);
2566 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2568 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2569 fputs ("[lLr] ", stderr
);
2571 fputs ("i ", stderr
);
2573 fprintf (stderr
, "\n");
2579 print_vliw_insn (xtensa_insnbuf vbuf
)
2581 xtensa_isa isa
= xtensa_default_isa
;
2582 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2583 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2586 fprintf (stderr
, "format = %d\n", f
);
2588 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2590 xtensa_opcode opcode
;
2594 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2595 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2596 opname
= xtensa_opcode_name (isa
, opcode
);
2598 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2599 fprintf (stderr
, " operands = ");
2601 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2605 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2607 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2608 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2609 fprintf (stderr
, "%d ", val
);
2611 fprintf (stderr
, "\n");
2613 xtensa_insnbuf_free (isa
, sbuf
);
2616 #endif /* TENSILICA_DEBUG */
2620 is_direct_call_opcode (xtensa_opcode opcode
)
2622 xtensa_isa isa
= xtensa_default_isa
;
2623 int n
, num_operands
;
2625 if (xtensa_opcode_is_call (isa
, opcode
) == 0)
2628 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2629 for (n
= 0; n
< num_operands
; n
++)
2631 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2632 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2639 /* Convert from BFD relocation type code to slot and operand number.
2640 Returns non-zero on failure. */
2643 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2645 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2646 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2648 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2651 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2652 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2654 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2664 /* Convert from slot number to BFD relocation type code for the
2665 standard PC-relative relocations. Return BFD_RELOC_NONE on
2668 static bfd_reloc_code_real_type
2669 encode_reloc (int slot
)
2671 if (slot
< 0 || slot
> 14)
2672 return BFD_RELOC_NONE
;
2674 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2678 /* Convert from slot numbers to BFD relocation type code for the
2679 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2681 static bfd_reloc_code_real_type
2682 encode_alt_reloc (int slot
)
2684 if (slot
< 0 || slot
> 14)
2685 return BFD_RELOC_NONE
;
2687 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2692 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2695 xtensa_opcode opcode
,
2701 uint32 valbuf
= value
;
2703 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2705 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2707 as_bad_where ((char *) file
, line
,
2708 _("operand %u is out of range for '%s'"), value
,
2709 xtensa_opcode_name (xtensa_default_isa
, opcode
));
2711 as_bad_where ((char *) file
, line
,
2712 _("operand %u is invalid for '%s'"), value
,
2713 xtensa_opcode_name (xtensa_default_isa
, opcode
));
2717 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2723 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2726 xtensa_opcode opcode
,
2730 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2731 fmt
, slot
, slotbuf
, &val
);
2732 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2737 /* Checks for rules from xtensa-relax tables. */
2739 /* The routine xg_instruction_matches_option_term must return TRUE
2740 when a given option term is true. The meaning of all of the option
2741 terms is given interpretation by this function. This is needed when
2742 an option depends on the state of a directive, but there are no such
2743 options in use right now. */
2746 xg_instruction_matches_option_term (TInsn
*insn ATTRIBUTE_UNUSED
,
2747 const ReqOrOption
*option
)
2749 if (strcmp (option
->option_name
, "realnop") == 0
2750 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2752 /* These conditions were evaluated statically when building the
2753 relaxation table. There's no need to reevaluate them now. */
2758 as_fatal (_("internal error: unknown option name '%s'"),
2759 option
->option_name
);
2765 xg_instruction_matches_or_options (TInsn
*insn
,
2766 const ReqOrOptionList
*or_option
)
2768 const ReqOrOption
*option
;
2769 /* Must match each of the AND terms. */
2770 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2772 if (xg_instruction_matches_option_term (insn
, option
))
2780 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2782 const ReqOption
*req_options
;
2783 /* Must match each of the AND terms. */
2784 for (req_options
= options
;
2785 req_options
!= NULL
;
2786 req_options
= req_options
->next
)
2788 /* Must match one of the OR clauses. */
2789 if (!xg_instruction_matches_or_options (insn
,
2790 req_options
->or_option_terms
))
2797 /* Return the transition rule that matches or NULL if none matches. */
2800 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2802 PreconditionList
*condition_l
;
2804 if (rule
->opcode
!= insn
->opcode
)
2807 for (condition_l
= rule
->conditions
;
2808 condition_l
!= NULL
;
2809 condition_l
= condition_l
->next
)
2813 Precondition
*cond
= condition_l
->precond
;
2818 /* The expression must be the constant. */
2819 assert (cond
->op_num
< insn
->ntok
);
2820 exp1
= &insn
->tok
[cond
->op_num
];
2821 if (expr_is_const (exp1
))
2826 if (get_expr_const (exp1
) != cond
->op_data
)
2830 if (get_expr_const (exp1
) == cond
->op_data
)
2837 else if (expr_is_register (exp1
))
2842 if (get_expr_register (exp1
) != cond
->op_data
)
2846 if (get_expr_register (exp1
) == cond
->op_data
)
2858 assert (cond
->op_num
< insn
->ntok
);
2859 assert (cond
->op_data
< insn
->ntok
);
2860 exp1
= &insn
->tok
[cond
->op_num
];
2861 exp2
= &insn
->tok
[cond
->op_data
];
2866 if (!expr_is_equal (exp1
, exp2
))
2870 if (expr_is_equal (exp1
, exp2
))
2882 if (!xg_instruction_matches_options (insn
, rule
->options
))
2890 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
2892 bfd_boolean a_greater
= FALSE
;
2893 bfd_boolean b_greater
= FALSE
;
2895 ReqOptionList
*l_a
= a
->options
;
2896 ReqOptionList
*l_b
= b
->options
;
2898 /* We only care if they both are the same except for
2899 a const16 vs. an l32r. */
2901 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2903 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
2904 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
2905 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2907 if (l_or_a
->is_true
!= l_or_b
->is_true
)
2909 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
2911 /* This is the case we care about. */
2912 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
2913 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
2920 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
2921 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
2931 l_or_a
= l_or_a
->next
;
2932 l_or_b
= l_or_b
->next
;
2934 if (l_or_a
|| l_or_b
)
2943 /* Incomparable if the substitution was used differently in two cases. */
2944 if (a_greater
&& b_greater
)
2956 static TransitionRule
*
2957 xg_instruction_match (TInsn
*insn
)
2959 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
2961 assert (insn
->opcode
< table
->num_opcodes
);
2963 /* Walk through all of the possible transitions. */
2964 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2966 TransitionRule
*rule
= l
->rule
;
2967 if (xg_instruction_matches_rule (insn
, rule
))
2974 /* Various Other Internal Functions. */
2977 is_unique_insn_expansion (TransitionRule
*r
)
2979 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
2981 if (r
->to_instr
->typ
!= INSTR_INSTR
)
2988 xg_get_build_instr_size (BuildInstr
*insn
)
2990 assert (insn
->typ
== INSTR_INSTR
);
2991 return xg_get_single_size (insn
->opcode
);
2996 xg_is_narrow_insn (TInsn
*insn
)
2998 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3001 assert (insn
->insn_type
== ITYPE_INSN
);
3002 assert (insn
->opcode
< table
->num_opcodes
);
3004 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3006 TransitionRule
*rule
= l
->rule
;
3008 if (xg_instruction_matches_rule (insn
, rule
)
3009 && is_unique_insn_expansion (rule
))
3011 /* It only generates one instruction... */
3012 assert (insn
->insn_type
== ITYPE_INSN
);
3013 /* ...and it is a larger instruction. */
3014 if (xg_get_single_size (insn
->opcode
)
3015 < xg_get_build_instr_size (rule
->to_instr
))
3023 return (num_match
== 1);
3028 xg_is_single_relaxable_insn (TInsn
*insn
)
3030 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3033 assert (insn
->insn_type
== ITYPE_INSN
);
3034 assert (insn
->opcode
< table
->num_opcodes
);
3036 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3038 TransitionRule
*rule
= l
->rule
;
3040 if (xg_instruction_matches_rule (insn
, rule
)
3041 && is_unique_insn_expansion (rule
))
3043 /* It only generates one instruction... */
3044 assert (insn
->insn_type
== ITYPE_INSN
);
3045 /* ... and it is a larger instruction. */
3046 if (xg_get_single_size (insn
->opcode
)
3047 <= xg_get_build_instr_size (rule
->to_instr
))
3055 return (num_match
== 1);
3059 /* Return the maximum number of bytes this opcode can expand to. */
3062 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
3064 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3066 int max_size
= xg_get_single_size (opcode
);
3068 assert (opcode
< table
->num_opcodes
);
3070 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3072 TransitionRule
*rule
= l
->rule
;
3073 BuildInstr
*build_list
;
3078 build_list
= rule
->to_instr
;
3079 if (is_unique_insn_expansion (rule
))
3081 assert (build_list
->typ
== INSTR_INSTR
);
3082 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
3085 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3087 switch (build_list
->typ
)
3090 this_size
+= xg_get_single_size (build_list
->opcode
);
3092 case INSTR_LITERAL_DEF
:
3093 case INSTR_LABEL_DEF
:
3098 if (this_size
> max_size
)
3099 max_size
= this_size
;
3105 /* Return the maximum number of literal bytes this opcode can generate. */
3108 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3110 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3114 assert (opcode
< table
->num_opcodes
);
3116 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3118 TransitionRule
*rule
= l
->rule
;
3119 BuildInstr
*build_list
;
3124 build_list
= rule
->to_instr
;
3125 if (is_unique_insn_expansion (rule
))
3127 assert (build_list
->typ
== INSTR_INSTR
);
3128 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3131 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3133 switch (build_list
->typ
)
3135 case INSTR_LITERAL_DEF
:
3136 /* Hard-coded 4-byte literal. */
3140 case INSTR_LABEL_DEF
:
3145 if (this_size
> max_size
)
3146 max_size
= this_size
;
3153 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3155 int steps_taken
= 0;
3156 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3159 assert (insn
->insn_type
== ITYPE_INSN
);
3160 assert (insn
->opcode
< table
->num_opcodes
);
3162 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3164 TransitionRule
*rule
= l
->rule
;
3166 if (xg_instruction_matches_rule (insn
, rule
))
3168 if (steps_taken
== lateral_steps
)
3178 get_special_literal_symbol (void)
3180 static symbolS
*sym
= NULL
;
3183 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3189 get_special_label_symbol (void)
3191 static symbolS
*sym
= NULL
;
3194 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3200 xg_valid_literal_expression (const expressionS
*exp
)
3217 /* This will check to see if the value can be converted into the
3218 operand type. It will return TRUE if it does not fit. */
3221 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3223 uint32 valbuf
= value
;
3224 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3230 /* Assumes: All immeds are constants. Check that all constants fit
3231 into their immeds; return FALSE if not. */
3234 xg_immeds_fit (const TInsn
*insn
)
3236 xtensa_isa isa
= xtensa_default_isa
;
3240 assert (insn
->insn_type
== ITYPE_INSN
);
3241 for (i
= 0; i
< n
; ++i
)
3243 const expressionS
*expr
= &insn
->tok
[i
];
3244 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3251 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3256 /* The symbol should have a fixup associated with it. */
3265 /* This should only be called after we have an initial
3266 estimate of the addresses. */
3269 xg_symbolic_immeds_fit (const TInsn
*insn
,
3275 xtensa_isa isa
= xtensa_default_isa
;
3283 assert (insn
->insn_type
== ITYPE_INSN
);
3285 for (i
= 0; i
< n
; ++i
)
3287 const expressionS
*expr
= &insn
->tok
[i
];
3288 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3295 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3301 /* Check for the worst case. */
3302 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3307 /* We only allow symbols for PC-relative references.
3308 If pc_frag == 0, then we don't have frag locations yet. */
3310 || xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0)
3313 /* If it is a weak symbol, then assume it won't reach. */
3314 if (S_IS_WEAK (expr
->X_add_symbol
))
3317 if (is_direct_call_opcode (insn
->opcode
)
3318 && ! pc_frag
->tc_frag_data
.use_longcalls
)
3320 /* If callee is undefined or in a different segment, be
3321 optimistic and assume it will be in range. */
3322 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3326 /* Only references within a segment can be known to fit in the
3327 operands at assembly time. */
3328 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3331 symbolP
= expr
->X_add_symbol
;
3332 sym_frag
= symbol_get_frag (symbolP
);
3333 target
= S_GET_VALUE (symbolP
) + expr
->X_add_number
;
3334 pc
= pc_frag
->fr_address
+ pc_offset
;
3336 /* If frag has yet to be reached on this pass, assume it
3337 will move by STRETCH just as we did. If this is not so,
3338 it will be because some frag between grows, and that will
3339 force another pass. Beware zero-length frags. There
3340 should be a faster way to do this. */
3343 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3344 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3349 new_offset
= target
;
3350 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3351 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3356 /* The symbol should have a fixup associated with it. */
3365 /* Return TRUE on success. */
3368 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3373 memset (targ
, 0, sizeof (TInsn
));
3374 targ
->loc
= insn
->loc
;
3379 targ
->opcode
= bi
->opcode
;
3380 targ
->insn_type
= ITYPE_INSN
;
3381 targ
->is_specific_opcode
= FALSE
;
3383 for (; op
!= NULL
; op
= op
->next
)
3385 int op_num
= op
->op_num
;
3386 int op_data
= op
->op_data
;
3388 assert (op
->op_num
< MAX_INSN_ARGS
);
3390 if (targ
->ntok
<= op_num
)
3391 targ
->ntok
= op_num
+ 1;
3396 set_expr_const (&targ
->tok
[op_num
], op_data
);
3399 assert (op_data
< insn
->ntok
);
3400 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3403 sym
= get_special_literal_symbol ();
3404 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3407 sym
= get_special_label_symbol ();
3408 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3410 case OP_OPERAND_HI16U
:
3411 case OP_OPERAND_LOW16U
:
3412 assert (op_data
< insn
->ntok
);
3413 if (expr_is_const (&insn
->tok
[op_data
]))
3416 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3417 val
= xg_apply_userdef_op_fn (op
->typ
,
3420 targ
->tok
[op_num
].X_add_number
= val
;
3424 /* For const16 we can create relocations for these. */
3425 if (targ
->opcode
== XTENSA_UNDEFINED
3426 || (targ
->opcode
!= xtensa_const16_opcode
))
3428 assert (op_data
< insn
->ntok
);
3429 /* Need to build a O_lo16 or O_hi16. */
3430 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3431 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3433 if (op
->typ
== OP_OPERAND_HI16U
)
3434 targ
->tok
[op_num
].X_op
= O_hi16
;
3435 else if (op
->typ
== OP_OPERAND_LOW16U
)
3436 targ
->tok
[op_num
].X_op
= O_lo16
;
3443 /* currently handles:
3446 OP_OPERAND_F32MINUS */
3447 if (xg_has_userdef_op_fn (op
->typ
))
3449 assert (op_data
< insn
->ntok
);
3450 if (expr_is_const (&insn
->tok
[op_data
]))
3453 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3454 val
= xg_apply_userdef_op_fn (op
->typ
,
3457 targ
->tok
[op_num
].X_add_number
= val
;
3460 return FALSE
; /* We cannot use a relocation for this. */
3469 case INSTR_LITERAL_DEF
:
3471 targ
->opcode
= XTENSA_UNDEFINED
;
3472 targ
->insn_type
= ITYPE_LITERAL
;
3473 targ
->is_specific_opcode
= FALSE
;
3474 for (; op
!= NULL
; op
= op
->next
)
3476 int op_num
= op
->op_num
;
3477 int op_data
= op
->op_data
;
3478 assert (op
->op_num
< MAX_INSN_ARGS
);
3480 if (targ
->ntok
<= op_num
)
3481 targ
->ntok
= op_num
+ 1;
3486 assert (op_data
< insn
->ntok
);
3487 /* We can only pass resolvable literals through. */
3488 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3490 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3502 case INSTR_LABEL_DEF
:
3504 targ
->opcode
= XTENSA_UNDEFINED
;
3505 targ
->insn_type
= ITYPE_LABEL
;
3506 targ
->is_specific_opcode
= FALSE
;
3507 /* Literal with no ops is a label? */
3508 assert (op
== NULL
);
3519 /* Return TRUE on success. */
3522 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3524 for (; bi
!= NULL
; bi
= bi
->next
)
3526 TInsn
*next_insn
= istack_push_space (istack
);
3528 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3535 /* Return TRUE on valid expansion. */
3538 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3540 int stack_size
= istack
->ninsn
;
3541 int steps_taken
= 0;
3542 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3545 assert (insn
->insn_type
== ITYPE_INSN
);
3546 assert (insn
->opcode
< table
->num_opcodes
);
3548 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3550 TransitionRule
*rule
= l
->rule
;
3552 if (xg_instruction_matches_rule (insn
, rule
))
3554 if (lateral_steps
== steps_taken
)
3558 /* This is it. Expand the rule to the stack. */
3559 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3562 /* Check to see if it fits. */
3563 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3565 TInsn
*insn
= &istack
->insn
[i
];
3567 if (insn
->insn_type
== ITYPE_INSN
3568 && !tinsn_has_symbolic_operands (insn
)
3569 && !xg_immeds_fit (insn
))
3571 istack
->ninsn
= stack_size
;
3585 xg_expand_narrow (TInsn
*targ
, TInsn
*insn
)
3587 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3590 assert (insn
->insn_type
== ITYPE_INSN
);
3591 assert (insn
->opcode
< table
->num_opcodes
);
3593 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3595 TransitionRule
*rule
= l
->rule
;
3596 if (xg_instruction_matches_rule (insn
, rule
)
3597 && is_unique_insn_expansion (rule
))
3599 /* Is it a larger instruction? */
3600 if (xg_get_single_size (insn
->opcode
)
3601 <= xg_get_build_instr_size (rule
->to_instr
))
3603 xg_build_to_insn (targ
, insn
, rule
->to_instr
);
3612 /* Relax the assembly instruction at least "min_steps".
3613 Return the number of steps taken. */
3616 xg_assembly_relax (IStack
*istack
,
3619 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3620 offsetT pc_offset
, /* offset in fragment */
3621 int min_steps
, /* minimum conversion steps */
3622 long stretch
) /* number of bytes stretched so far */
3624 int steps_taken
= 0;
3626 /* assert (has no symbolic operands)
3627 Some of its immeds don't fit.
3628 Try to build a relaxed version.
3629 This may go through a couple of stages
3630 of single instruction transformations before
3633 TInsn single_target
;
3635 int lateral_steps
= 0;
3636 int istack_size
= istack
->ninsn
;
3638 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3639 && steps_taken
>= min_steps
)
3641 istack_push (istack
, insn
);
3644 current_insn
= *insn
;
3646 /* Walk through all of the single instruction expansions. */
3647 while (xg_is_single_relaxable_insn (¤t_insn
))
3649 int error_val
= xg_expand_narrow (&single_target
, ¤t_insn
);
3651 assert (!error_val
);
3653 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3657 if (steps_taken
>= min_steps
)
3659 istack_push (istack
, &single_target
);
3663 current_insn
= single_target
;
3666 /* Now check for a multi-instruction expansion. */
3667 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3669 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3672 if (steps_taken
>= min_steps
)
3674 istack_push (istack
, ¤t_insn
);
3679 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3681 if (steps_taken
>= min_steps
)
3685 istack
->ninsn
= istack_size
;
3688 /* It's not going to work -- use the original. */
3689 istack_push (istack
, insn
);
3695 xg_force_frag_space (int size
)
3697 /* This may have the side effect of creating a new fragment for the
3698 space to go into. I just do not like the name of the "frag"
3705 xg_finish_frag (char *last_insn
,
3706 enum xtensa_relax_statesE frag_state
,
3707 enum xtensa_relax_statesE slot0_state
,
3709 bfd_boolean is_insn
)
3711 /* Finish off this fragment so that it has at LEAST the desired
3712 max_growth. If it doesn't fit in this fragment, close this one
3713 and start a new one. In either case, return a pointer to the
3714 beginning of the growth area. */
3718 xg_force_frag_space (max_growth
);
3720 old_frag
= frag_now
;
3722 frag_now
->fr_opcode
= last_insn
;
3724 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3726 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3727 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3729 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3730 xtensa_set_frag_assembly_state (frag_now
);
3732 /* Just to make sure that we did not split it up. */
3733 assert (old_frag
->fr_next
== frag_now
);
3737 /* Return TRUE if the target frag is one of the next non-empty frags. */
3740 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3745 for (; fragP
; fragP
= fragP
->fr_next
)
3747 if (fragP
== target
)
3749 if (fragP
->fr_fix
!= 0)
3751 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3753 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3754 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3756 if (fragP
->fr_type
== rs_space
)
3764 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3766 xtensa_isa isa
= xtensa_default_isa
;
3768 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3773 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 0
3774 && xtensa_opcode_is_jump (isa
, insn
->opcode
) == 0)
3777 for (i
= 0; i
< num_ops
; i
++)
3779 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3785 if (target_op
== -1)
3788 if (insn
->ntok
<= target_op
)
3791 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3794 sym
= insn
->tok
[target_op
].X_add_symbol
;
3798 if (insn
->tok
[target_op
].X_add_number
!= 0)
3801 target_frag
= symbol_get_frag (sym
);
3802 if (target_frag
== NULL
)
3805 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3806 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3814 xg_add_branch_and_loop_targets (TInsn
*insn
)
3816 xtensa_isa isa
= xtensa_default_isa
;
3817 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3819 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3822 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3823 && insn
->tok
[i
].X_op
== O_symbol
)
3824 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3828 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3829 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3833 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3835 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3836 && insn
->tok
[i
].X_op
== O_symbol
)
3838 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3839 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3840 if (S_IS_DEFINED (sym
))
3841 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3848 /* Return FALSE if no error. */
3851 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3856 switch (instr_spec
->typ
)
3859 new_insn
->insn_type
= ITYPE_INSN
;
3860 new_insn
->opcode
= instr_spec
->opcode
;
3861 new_insn
->is_specific_opcode
= FALSE
;
3862 new_insn
->loc
= old_insn
->loc
;
3864 case INSTR_LITERAL_DEF
:
3865 new_insn
->insn_type
= ITYPE_LITERAL
;
3866 new_insn
->opcode
= XTENSA_UNDEFINED
;
3867 new_insn
->is_specific_opcode
= FALSE
;
3868 new_insn
->loc
= old_insn
->loc
;
3870 case INSTR_LABEL_DEF
:
3871 as_bad (_("INSTR_LABEL_DEF not supported yet"));
3875 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3878 const expressionS
*src_exp
;
3884 /* The expression must be the constant. */
3885 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3886 exp
= &new_insn
->tok
[b_op
->op_num
];
3887 set_expr_const (exp
, b_op
->op_data
);
3891 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3892 assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
3893 src_exp
= &old_insn
->tok
[b_op
->op_data
];
3894 exp
= &new_insn
->tok
[b_op
->op_num
];
3895 copy_expr (exp
, src_exp
);
3900 as_bad (_("can't handle generation of literal/labels yet"));
3904 as_bad (_("can't handle undefined OP TYPE"));
3909 new_insn
->ntok
= num_ops
;
3914 /* Return TRUE if it was simplified. */
3917 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
3919 TransitionRule
*rule
;
3920 BuildInstr
*insn_spec
;
3922 if (old_insn
->is_specific_opcode
|| !density_supported
)
3925 rule
= xg_instruction_match (old_insn
);
3929 insn_spec
= rule
->to_instr
;
3930 /* There should only be one. */
3931 assert (insn_spec
!= NULL
);
3932 assert (insn_spec
->next
== NULL
);
3933 if (insn_spec
->next
!= NULL
)
3936 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
3942 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3943 l32i.n. (2) Check the number of operands. (3) Place the instruction
3944 tokens into the stack or relax it and place multiple
3945 instructions/literals onto the stack. Return FALSE if no error. */
3948 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
3952 bfd_boolean do_expand
;
3954 memset (&new_insn
, 0, sizeof (TInsn
));
3956 /* Narrow it if we can. xg_simplify_insn now does all the
3957 appropriate checking (e.g., for the density option). */
3958 if (xg_simplify_insn (orig_insn
, &new_insn
))
3959 orig_insn
= &new_insn
;
3961 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
3963 if (orig_insn
->ntok
< noperands
)
3965 as_bad (_("found %d operands for '%s': Expected %d"),
3967 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3971 if (orig_insn
->ntok
> noperands
)
3972 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
3974 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3977 /* If there are not enough operands, we will assert above. If there
3978 are too many, just cut out the extras here. */
3979 orig_insn
->ntok
= noperands
;
3981 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
3984 /* If the instruction will definitely need to be relaxed, it is better
3985 to expand it now for better scheduling. Decide whether to expand
3987 do_expand
= (!orig_insn
->is_specific_opcode
&& use_transform ());
3989 /* Calls should be expanded to longcalls only in the backend relaxation
3990 so that the assembly scheduler will keep the L32R/CALLX instructions
3992 if (is_direct_call_opcode (orig_insn
->opcode
))
3995 if (tinsn_has_symbolic_operands (orig_insn
))
3997 /* The values of symbolic operands are not known yet, so only expand
3998 now if an operand is "complex" (e.g., difference of symbols) and
3999 will have to be stored as a literal regardless of the value. */
4000 if (!tinsn_has_complex_operands (orig_insn
))
4003 else if (xg_immeds_fit (orig_insn
))
4007 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
4009 istack_push (istack
, orig_insn
);
4015 /* Return TRUE if the section flags are marked linkonce
4016 or the name is .gnu.linkonce*. */
4019 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
4021 flagword flags
, link_once_flags
;
4023 flags
= bfd_get_section_flags (abfd
, sec
);
4024 link_once_flags
= (flags
& SEC_LINK_ONCE
);
4026 /* Flags might not be set yet. */
4027 if (!link_once_flags
)
4029 static size_t len
= sizeof ".gnu.linkonce.t.";
4031 if (strncmp (segment_name (sec
), ".gnu.linkonce.t.", len
- 1) == 0)
4032 link_once_flags
= SEC_LINK_ONCE
;
4034 return (link_once_flags
!= 0);
4039 xtensa_add_literal_sym (symbolS
*sym
)
4043 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
4045 l
->next
= literal_syms
;
4051 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
4053 static int lit_num
= 0;
4054 static char name
[256];
4057 sprintf (name
, ".L_lit_sym%d", lit_num
);
4059 /* Create a local symbol. If it is in a linkonce section, we have to
4060 be careful to make sure that if it is used in a relocation that the
4061 symbol will be in the output file. */
4062 if (get_is_linkonce_section (stdoutput
, sec
))
4064 symbolP
= symbol_new (name
, sec
, 0, frag
);
4065 S_CLEAR_EXTERNAL (symbolP
);
4066 /* symbolP->local = 1; */
4069 symbolP
= symbol_new (name
, sec
, 0, frag
);
4071 xtensa_add_literal_sym (symbolP
);
4073 frag
->tc_frag_data
.is_literal
= TRUE
;
4079 /* Currently all literals that are generated here are 32-bit L32R targets. */
4082 xg_assemble_literal (/* const */ TInsn
*insn
)
4085 symbolS
*lit_sym
= NULL
;
4087 /* size = 4 for L32R. It could easily be larger when we move to
4088 larger constants. Add a parameter later. */
4089 offsetT litsize
= 4;
4090 offsetT litalign
= 2; /* 2^2 = 4 */
4091 expressionS saved_loc
;
4092 expressionS
* emit_val
;
4094 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
4096 assert (insn
->insn_type
== ITYPE_LITERAL
);
4097 assert (insn
->ntok
== 1); /* must be only one token here */
4099 xtensa_switch_to_literal_fragment (&state
);
4101 emit_val
= &insn
->tok
[0];
4102 if (emit_val
->X_op
== O_big
)
4104 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
4107 /* This happens when someone writes a "movi a2, big_number". */
4108 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4109 _("invalid immediate"));
4110 xtensa_restore_emit_state (&state
);
4115 /* Force a 4-byte align here. Note that this opens a new frag, so all
4116 literals done with this function have a frag to themselves. That's
4117 important for the way text section literals work. */
4118 frag_align (litalign
, 0, 0);
4119 record_alignment (now_seg
, litalign
);
4121 if (emit_val
->X_op
== O_pltrel
)
4123 char *p
= frag_more (litsize
);
4124 xtensa_set_frag_assembly_state (frag_now
);
4125 if (emit_val
->X_add_symbol
)
4126 emit_val
->X_op
= O_symbol
;
4128 emit_val
->X_op
= O_constant
;
4129 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
4130 litsize
, emit_val
, 0, BFD_RELOC_XTENSA_PLT
);
4133 emit_expr (emit_val
, litsize
);
4135 assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
4136 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4137 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4138 lit_sym
= frag_now
->fr_symbol
;
4139 frag_now
->tc_frag_data
.is_literal
= TRUE
;
4142 xtensa_restore_emit_state (&state
);
4148 xg_assemble_literal_space (/* const */ int size
, int slot
)
4151 /* We might have to do something about this alignment. It only
4152 takes effect if something is placed here. */
4153 offsetT litalign
= 2; /* 2^2 = 4 */
4154 fragS
*lit_saved_frag
;
4156 assert (size
% 4 == 0);
4158 xtensa_switch_to_literal_fragment (&state
);
4160 /* Force a 4-byte align here. */
4161 frag_align (litalign
, 0, 0);
4162 record_alignment (now_seg
, litalign
);
4164 xg_force_frag_space (size
);
4166 lit_saved_frag
= frag_now
;
4167 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4168 frag_now
->tc_frag_data
.is_literal
= TRUE
;
4169 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4170 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4173 xtensa_restore_emit_state (&state
);
4174 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4178 /* Put in a fixup record based on the opcode.
4179 Return TRUE on success. */
4182 xg_add_opcode_fix (TInsn
*tinsn
,
4190 xtensa_opcode opcode
= tinsn
->opcode
;
4191 bfd_reloc_code_real_type reloc
;
4192 reloc_howto_type
*howto
;
4196 reloc
= BFD_RELOC_NONE
;
4198 /* First try the special cases for "alternate" relocs. */
4199 if (opcode
== xtensa_l32r_opcode
)
4201 if (fragP
->tc_frag_data
.use_absolute_literals
)
4202 reloc
= encode_alt_reloc (slot
);
4204 else if (opcode
== xtensa_const16_opcode
)
4206 if (expr
->X_op
== O_lo16
)
4208 reloc
= encode_reloc (slot
);
4209 expr
->X_op
= O_symbol
;
4211 else if (expr
->X_op
== O_hi16
)
4213 reloc
= encode_alt_reloc (slot
);
4214 expr
->X_op
= O_symbol
;
4218 if (opnum
!= get_relaxable_immed (opcode
))
4220 as_bad (_("invalid relocation for operand %i of '%s'"),
4221 opnum
, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4225 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4226 into the symbol table where the generic portions of the assembler
4227 won't know what to do with them. */
4228 if (expr
->X_op
== O_lo16
|| expr
->X_op
== O_hi16
)
4230 as_bad (_("invalid expression for operand %i of '%s'"),
4231 opnum
, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4235 /* Next try the generic relocs. */
4236 if (reloc
== BFD_RELOC_NONE
)
4237 reloc
= encode_reloc (slot
);
4238 if (reloc
== BFD_RELOC_NONE
)
4240 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4244 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4247 as_bad (_("undefined symbol for opcode \"%s\""),
4248 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4252 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4253 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, expr
,
4254 howto
->pc_relative
, reloc
);
4255 the_fix
->fx_no_overflow
= 1;
4257 if (expr
->X_add_symbol
4258 && (S_IS_EXTERNAL (expr
->X_add_symbol
)
4259 || S_IS_WEAK (expr
->X_add_symbol
)))
4260 the_fix
->fx_plt
= TRUE
;
4262 the_fix
->tc_fix_data
.X_add_symbol
= expr
->X_add_symbol
;
4263 the_fix
->tc_fix_data
.X_add_number
= expr
->X_add_number
;
4264 the_fix
->tc_fix_data
.slot
= slot
;
4271 xg_emit_insn_to_buf (TInsn
*tinsn
,
4276 bfd_boolean build_fix
)
4278 static xtensa_insnbuf insnbuf
= NULL
;
4279 bfd_boolean has_symbolic_immed
= FALSE
;
4280 bfd_boolean ok
= TRUE
;
4282 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4284 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4285 if (has_symbolic_immed
&& build_fix
)
4288 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4289 expressionS
*exp
= &tinsn
->tok
[opnum
];
4291 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, 0, exp
, fragP
, offset
))
4294 fragP
->tc_frag_data
.is_insn
= TRUE
;
4295 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4296 (unsigned char *) buf
, 0);
4302 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4304 symbolS
*sym
= get_special_literal_symbol ();
4308 assert (insn
->insn_type
== ITYPE_INSN
);
4309 for (i
= 0; i
< insn
->ntok
; i
++)
4310 if (insn
->tok
[i
].X_add_symbol
== sym
)
4311 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4317 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4319 symbolS
*sym
= get_special_label_symbol ();
4321 /* assert (!insn->is_literal); */
4322 for (i
= 0; i
< insn
->ntok
; i
++)
4323 if (insn
->tok
[i
].X_add_symbol
== sym
)
4324 insn
->tok
[i
].X_add_symbol
= label_sym
;
4329 /* Return TRUE if the instruction can write to the specified
4330 integer register. */
4333 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4337 xtensa_isa isa
= xtensa_default_isa
;
4339 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4341 for (i
= 0; i
< num_ops
; i
++)
4344 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4345 if ((inout
== 'o' || inout
== 'm')
4346 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4348 xtensa_regfile opnd_rf
=
4349 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4350 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4352 if ((insn
->tok
[i
].X_op
== O_register
)
4353 && (insn
->tok
[i
].X_add_number
== regnum
))
4363 is_bad_loopend_opcode (const TInsn
*tinsn
)
4365 xtensa_opcode opcode
= tinsn
->opcode
;
4367 if (opcode
== XTENSA_UNDEFINED
)
4370 if (opcode
== xtensa_call0_opcode
4371 || opcode
== xtensa_callx0_opcode
4372 || opcode
== xtensa_call4_opcode
4373 || opcode
== xtensa_callx4_opcode
4374 || opcode
== xtensa_call8_opcode
4375 || opcode
== xtensa_callx8_opcode
4376 || opcode
== xtensa_call12_opcode
4377 || opcode
== xtensa_callx12_opcode
4378 || opcode
== xtensa_isync_opcode
4379 || opcode
== xtensa_ret_opcode
4380 || opcode
== xtensa_ret_n_opcode
4381 || opcode
== xtensa_retw_opcode
4382 || opcode
== xtensa_retw_n_opcode
4383 || opcode
== xtensa_waiti_opcode
4384 || opcode
== xtensa_rsr_lcount_opcode
)
4391 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4392 This allows the debugger to add unaligned labels.
4393 Also, the assembler generates stabs labels that need
4394 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4397 is_unaligned_label (symbolS
*sym
)
4399 const char *name
= S_GET_NAME (sym
);
4400 static size_t fake_size
= 0;
4404 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4407 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4409 fake_size
= strlen (FAKE_LABEL_NAME
);
4412 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4413 && (name
[fake_size
] == 'F'
4414 || name
[fake_size
] == 'L'
4415 || (name
[fake_size
] == 'e'
4416 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4424 next_non_empty_frag (const fragS
*fragP
)
4426 fragS
*next_fragP
= fragP
->fr_next
;
4428 /* Sometimes an empty will end up here due storage allocation issues.
4429 So we have to skip until we find something legit. */
4430 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4431 next_fragP
= next_fragP
->fr_next
;
4433 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4441 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4443 xtensa_opcode out_opcode
;
4444 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4446 if (next_fragP
== NULL
)
4449 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4450 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4452 *opcode
= out_opcode
;
4460 frag_format_size (const fragS
*fragP
)
4462 static xtensa_insnbuf insnbuf
= NULL
;
4463 xtensa_isa isa
= xtensa_default_isa
;
4468 insnbuf
= xtensa_insnbuf_alloc (isa
);
4471 return XTENSA_UNDEFINED
;
4473 xtensa_insnbuf_from_chars (isa
, insnbuf
,
4474 (unsigned char *) fragP
->fr_literal
, 0);
4476 fmt
= xtensa_format_decode (isa
, insnbuf
);
4477 if (fmt
== XTENSA_UNDEFINED
)
4478 return XTENSA_UNDEFINED
;
4479 fmt_size
= xtensa_format_length (isa
, fmt
);
4481 /* If the next format won't be changing due to relaxation, just
4482 return the length of the first format. */
4483 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4486 /* If during relaxation we have to pull an instruction out of a
4487 multi-slot instruction, we will return the more conservative
4488 number. This works because alignment on bigger instructions
4489 is more restrictive than alignment on smaller instructions.
4490 This is more conservative than we would like, but it happens
4493 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4496 /* If we aren't doing one of our own relaxations or it isn't
4497 slot-based, then the insn size won't change. */
4498 if (fragP
->fr_type
!= rs_machine_dependent
)
4500 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4503 /* If an instruction is about to grow, return the longer size. */
4504 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4505 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
)
4508 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4509 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4516 next_frag_format_size (const fragS
*fragP
)
4518 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4519 return frag_format_size (next_fragP
);
4523 /* If the next legit fragment is an end-of-loop marker,
4524 switch its state so it will instantiate a NOP. */
4527 update_next_frag_state (fragS
*fragP
)
4529 fragS
*next_fragP
= fragP
->fr_next
;
4530 fragS
*new_target
= NULL
;
4534 /* We are guaranteed there will be one of these... */
4535 while (!(next_fragP
->fr_type
== rs_machine_dependent
4536 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4537 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4538 next_fragP
= next_fragP
->fr_next
;
4540 assert (next_fragP
->fr_type
== rs_machine_dependent
4541 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4542 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4544 /* ...and one of these. */
4545 new_target
= next_fragP
->fr_next
;
4546 while (!(new_target
->fr_type
== rs_machine_dependent
4547 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4548 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4549 new_target
= new_target
->fr_next
;
4551 assert (new_target
->fr_type
== rs_machine_dependent
4552 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4553 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4556 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4558 if (next_fragP
->fr_type
== rs_machine_dependent
4559 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4561 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4565 next_fragP
= next_fragP
->fr_next
;
4571 next_frag_is_branch_target (const fragS
*fragP
)
4573 /* Sometimes an empty will end up here due to storage allocation issues,
4574 so we have to skip until we find something legit. */
4575 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4577 if (fragP
->tc_frag_data
.is_branch_target
)
4579 if (fragP
->fr_fix
!= 0)
4587 next_frag_is_loop_target (const fragS
*fragP
)
4589 /* Sometimes an empty will end up here due storage allocation issues.
4590 So we have to skip until we find something legit. */
4591 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4593 if (fragP
->tc_frag_data
.is_loop_target
)
4595 if (fragP
->fr_fix
!= 0)
4603 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4605 const fragS
*next_fragp
= fragp
->fr_next
;
4606 xtensa_opcode next_opcode
;
4608 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4611 /* Sometimes an empty will end up here due to storage allocation issues,
4612 so we have to skip until we find something legit. */
4613 while (next_fragp
->fr_fix
== 0)
4614 next_fragp
= next_fragp
->fr_next
;
4616 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4619 /* There is some implicit knowledge encoded in here.
4620 The LOOP instructions that are NOT RELAX_IMMED have
4621 been relaxed. Note that we can assume that the LOOP
4622 instruction is in slot 0 because loops aren't bundleable. */
4623 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4624 return get_expanded_loop_offset (next_opcode
);
4630 /* Mark a location where we can later insert literal frags. Update
4631 the section's literal_pool_loc, so subsequent literals can be
4632 placed nearest to their use. */
4635 xtensa_mark_literal_pool_location (void)
4637 /* Any labels pointing to the current location need
4638 to be adjusted to after the literal pool. */
4640 fragS
*pool_location
;
4642 if (use_literal_section
&& !directive_state
[directive_absolute_literals
])
4645 frag_align (2, 0, 0);
4646 record_alignment (now_seg
, 2);
4648 /* We stash info in these frags so we can later move the literal's
4649 fixes into this frchain's fix list. */
4650 pool_location
= frag_now
;
4651 frag_now
->tc_frag_data
.lit_frchain
= frchain_now
;
4652 frag_variant (rs_machine_dependent
, 0, 0,
4653 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4654 xtensa_set_frag_assembly_state (frag_now
);
4655 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
4656 frag_variant (rs_machine_dependent
, 0, 0,
4657 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4658 xtensa_set_frag_assembly_state (frag_now
);
4660 /* Now put a frag into the literal pool that points to this location. */
4661 set_literal_pool_location (now_seg
, pool_location
);
4662 xtensa_switch_to_non_abs_literal_fragment (&s
);
4663 frag_align (2, 0, 0);
4664 record_alignment (now_seg
, 2);
4666 /* Close whatever frag is there. */
4667 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4668 xtensa_set_frag_assembly_state (frag_now
);
4669 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
4670 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4671 xtensa_restore_emit_state (&s
);
4672 xtensa_set_frag_assembly_state (frag_now
);
4676 /* Build a nop of the correct size into tinsn. */
4679 build_nop (TInsn
*tinsn
, int size
)
4685 tinsn
->opcode
= xtensa_nop_n_opcode
;
4687 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4688 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4692 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4694 tinsn
->opcode
= xtensa_or_opcode
;
4695 set_expr_const (&tinsn
->tok
[0], 1);
4696 set_expr_const (&tinsn
->tok
[1], 1);
4697 set_expr_const (&tinsn
->tok
[2], 1);
4701 tinsn
->opcode
= xtensa_nop_opcode
;
4703 assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4708 /* Assemble a NOP of the requested size in the buffer. User must have
4709 allocated "buf" with at least "size" bytes. */
4712 assemble_nop (int size
, char *buf
)
4714 static xtensa_insnbuf insnbuf
= NULL
;
4717 build_nop (&tinsn
, size
);
4720 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4722 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4723 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4724 (unsigned char *) buf
, 0);
4728 /* Return the number of bytes for the offset of the expanded loop
4729 instruction. This should be incorporated into the relaxation
4730 specification but is hard-coded here. This is used to auto-align
4731 the loop instruction. It is invalid to call this function if the
4732 configuration does not have loops or if the opcode is not a loop
4736 get_expanded_loop_offset (xtensa_opcode opcode
)
4738 /* This is the OFFSET of the loop instruction in the expanded loop.
4739 This MUST correspond directly to the specification of the loop
4740 expansion. It will be validated on fragment conversion. */
4741 assert (opcode
!= XTENSA_UNDEFINED
);
4742 if (opcode
== xtensa_loop_opcode
)
4744 if (opcode
== xtensa_loopnez_opcode
)
4746 if (opcode
== xtensa_loopgtz_opcode
)
4748 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4754 get_literal_pool_location (segT seg
)
4756 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4761 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4763 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4767 /* Set frag assembly state should be called when a new frag is
4768 opened and after a frag has been closed. */
4771 xtensa_set_frag_assembly_state (fragS
*fragP
)
4773 if (!density_supported
)
4774 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4776 /* This function is called from subsegs_finish, which is called
4777 after xtensa_end, so we can't use "use_transform" or
4778 "use_schedule" here. */
4779 if (!directive_state
[directive_transform
])
4780 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4781 if (directive_state
[directive_longcalls
])
4782 fragP
->tc_frag_data
.use_longcalls
= TRUE
;
4783 fragP
->tc_frag_data
.use_absolute_literals
=
4784 directive_state
[directive_absolute_literals
];
4785 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4790 relaxable_section (asection
*sec
)
4792 return (sec
->flags
& SEC_DEBUGGING
) == 0;
4797 xtensa_find_unmarked_state_frags (void)
4801 /* Walk over each fragment of all of the current segments. For each
4802 unmarked fragment, mark it with the same info as the previous
4804 for (seclist
= &stdoutput
->sections
;
4805 seclist
&& *seclist
;
4806 seclist
= &(*seclist
)->next
)
4808 segT sec
= *seclist
;
4809 segment_info_type
*seginfo
;
4812 flags
= bfd_get_section_flags (stdoutput
, sec
);
4813 if (flags
& SEC_DEBUGGING
)
4815 if (!(flags
& SEC_ALLOC
))
4818 seginfo
= seg_info (sec
);
4819 if (seginfo
&& seginfo
->frchainP
)
4821 fragS
*last_fragP
= 0;
4822 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4823 fragP
= fragP
->fr_next
)
4825 if (fragP
->fr_fix
!= 0
4826 && !fragP
->tc_frag_data
.is_assembly_state_set
)
4828 if (last_fragP
== 0)
4830 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
4831 _("assembly state not set for first frag in section %s"),
4836 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4837 fragP
->tc_frag_data
.is_no_density
=
4838 last_fragP
->tc_frag_data
.is_no_density
;
4839 fragP
->tc_frag_data
.is_no_transform
=
4840 last_fragP
->tc_frag_data
.is_no_transform
;
4841 fragP
->tc_frag_data
.use_longcalls
=
4842 last_fragP
->tc_frag_data
.use_longcalls
;
4843 fragP
->tc_frag_data
.use_absolute_literals
=
4844 last_fragP
->tc_frag_data
.use_absolute_literals
;
4847 if (fragP
->tc_frag_data
.is_assembly_state_set
)
4856 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
4858 void *unused ATTRIBUTE_UNUSED
)
4860 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4861 segment_info_type
*seginfo
= seg_info (sec
);
4862 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4864 if (flags
& SEC_CODE
)
4866 xtensa_isa isa
= xtensa_default_isa
;
4867 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4868 while (frag
!= NULL
)
4870 if (frag
->tc_frag_data
.is_branch_target
)
4873 addressT branch_align
, frag_addr
;
4876 xtensa_insnbuf_from_chars
4877 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4878 fmt
= xtensa_format_decode (isa
, insnbuf
);
4879 op_size
= xtensa_format_length (isa
, fmt
);
4880 branch_align
= 1 << branch_align_power (sec
);
4881 frag_addr
= frag
->fr_address
% branch_align
;
4882 if (frag_addr
+ op_size
> branch_align
)
4883 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4884 _("unaligned branch target: %d bytes at 0x%lx"),
4885 op_size
, (long) frag
->fr_address
);
4887 frag
= frag
->fr_next
;
4889 xtensa_insnbuf_free (isa
, insnbuf
);
4895 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
4897 void *unused ATTRIBUTE_UNUSED
)
4899 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4900 segment_info_type
*seginfo
= seg_info (sec
);
4901 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4902 xtensa_isa isa
= xtensa_default_isa
;
4904 if (flags
& SEC_CODE
)
4906 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4907 while (frag
!= NULL
)
4909 if (frag
->tc_frag_data
.is_first_loop_insn
)
4915 xtensa_insnbuf_from_chars
4916 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4917 fmt
= xtensa_format_decode (isa
, insnbuf
);
4918 op_size
= xtensa_format_length (isa
, fmt
);
4919 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
4921 if (frag_addr
+ op_size
> xtensa_fetch_width
)
4922 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4923 _("unaligned loop: %d bytes at 0x%lx"),
4924 op_size
, (long) frag
->fr_address
);
4926 frag
= frag
->fr_next
;
4928 xtensa_insnbuf_free (isa
, insnbuf
);
4934 xg_apply_fix_value (fixS
*fixP
, valueT val
)
4936 xtensa_isa isa
= xtensa_default_isa
;
4937 static xtensa_insnbuf insnbuf
= NULL
;
4938 static xtensa_insnbuf slotbuf
= NULL
;
4941 bfd_boolean alt_reloc
;
4942 xtensa_opcode opcode
;
4943 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
4945 (void) decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
);
4947 as_fatal (_("unexpected fix"));
4951 insnbuf
= xtensa_insnbuf_alloc (isa
);
4952 slotbuf
= xtensa_insnbuf_alloc (isa
);
4955 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4956 fmt
= xtensa_format_decode (isa
, insnbuf
);
4957 if (fmt
== XTENSA_UNDEFINED
)
4958 as_fatal (_("undecodable fix"));
4959 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4960 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
4961 if (opcode
== XTENSA_UNDEFINED
)
4962 as_fatal (_("undecodable fix"));
4964 /* CONST16 immediates are not PC-relative, despite the fact that we
4965 reuse the normal PC-relative operand relocations for the low part
4966 of a CONST16 operand. */
4967 if (opcode
== xtensa_const16_opcode
)
4970 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
4971 get_relaxable_immed (opcode
), val
,
4972 fixP
->fx_file
, fixP
->fx_line
);
4974 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4975 xtensa_insnbuf_to_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4981 /* External Functions and Other GAS Hooks. */
4984 xtensa_target_format (void)
4986 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
4991 xtensa_file_arch_init (bfd
*abfd
)
4993 bfd_set_private_flags (abfd
, 0x100 | 0x200);
4998 md_number_to_chars (char *buf
, valueT val
, int n
)
5000 if (target_big_endian
)
5001 number_to_chars_bigendian (buf
, val
, n
);
5003 number_to_chars_littleendian (buf
, val
, n
);
5007 /* This function is called once, at assembler startup time. It should
5008 set up all the tables, etc. that the MD part of the assembler will
5014 segT current_section
= now_seg
;
5015 int current_subsec
= now_subseg
;
5018 xtensa_default_isa
= xtensa_isa_init (0, 0);
5019 isa
= xtensa_default_isa
;
5023 /* Set up the .literal, .fini.literal and .init.literal sections. */
5024 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
5025 default_lit_sections
.init_lit_seg_name
= INIT_LITERAL_SECTION_NAME
;
5026 default_lit_sections
.fini_lit_seg_name
= FINI_LITERAL_SECTION_NAME
;
5027 default_lit_sections
.lit_seg_name
= LITERAL_SECTION_NAME
;
5028 default_lit_sections
.lit4_seg_name
= LIT4_SECTION_NAME
;
5030 subseg_set (current_section
, current_subsec
);
5032 xg_init_vinsn (&cur_vinsn
);
5034 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
5035 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
5036 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
5037 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
5038 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
5039 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
5040 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
5041 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
5042 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
5043 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
5044 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
5045 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
5046 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
5047 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
5048 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
5049 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
5050 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
5051 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
5052 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
5053 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
5054 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
5055 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
5056 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
5057 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
5058 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
5059 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
5060 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
5061 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
5062 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
5064 init_op_placement_info_table ();
5066 /* Set up the assembly state. */
5067 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5068 xtensa_set_frag_assembly_state (frag_now
);
5072 /* TC_INIT_FIX_DATA hook */
5075 xtensa_init_fix_data (fixS
*x
)
5077 x
->tc_fix_data
.slot
= 0;
5078 x
->tc_fix_data
.X_add_symbol
= NULL
;
5079 x
->tc_fix_data
.X_add_number
= 0;
5083 /* tc_frob_label hook */
5086 xtensa_frob_label (symbolS
*sym
)
5088 float freq
= get_subseg_target_freq (now_seg
, now_subseg
);
5090 /* Since the label was already attached to a frag associated with the
5091 previous basic block, it now needs to be reset to the current frag. */
5092 symbol_set_frag (sym
, frag_now
);
5093 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5095 if (generating_literals
)
5096 xtensa_add_literal_sym (sym
);
5098 xtensa_add_insn_label (sym
);
5100 if (symbol_get_tc (sym
)->is_loop_target
)
5102 if ((get_last_insn_flags (now_seg
, now_subseg
)
5103 & FLAG_IS_BAD_LOOPEND
) != 0)
5104 as_bad (_("invalid last instruction for a zero-overhead loop"));
5106 xtensa_set_frag_assembly_state (frag_now
);
5107 frag_var (rs_machine_dependent
, 4, 4, RELAX_LOOP_END
,
5108 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5110 xtensa_set_frag_assembly_state (frag_now
);
5111 xtensa_move_labels (frag_now
, 0, TRUE
);
5114 /* No target aligning in the absolute section. */
5115 if (now_seg
!= absolute_section
5116 && do_align_targets ()
5117 && !is_unaligned_label (sym
)
5118 && !generating_literals
)
5120 xtensa_set_frag_assembly_state (frag_now
);
5122 frag_var (rs_machine_dependent
,
5124 RELAX_DESIRE_ALIGN_IF_TARGET
,
5125 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5126 xtensa_set_frag_assembly_state (frag_now
);
5127 xtensa_move_labels (frag_now
, 0, TRUE
);
5130 /* We need to mark the following properties even if we aren't aligning. */
5132 /* If the label is already known to be a branch target, i.e., a
5133 forward branch, mark the frag accordingly. Backward branches
5134 are handled by xg_add_branch_and_loop_targets. */
5135 if (symbol_get_tc (sym
)->is_branch_target
)
5136 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5138 /* Loops only go forward, so they can be identified here. */
5139 if (symbol_get_tc (sym
)->is_loop_target
)
5140 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5144 /* tc_unrecognized_line hook */
5147 xtensa_unrecognized_line (int ch
)
5152 if (cur_vinsn
.inside_bundle
== 0)
5154 /* PR8110: Cannot emit line number info inside a FLIX bundle
5155 when using --gstabs. Temporarily disable debug info. */
5156 generate_lineno_debug ();
5157 if (debug_type
== DEBUG_STABS
)
5159 xt_saved_debug_type
= debug_type
;
5160 debug_type
= DEBUG_NONE
;
5163 cur_vinsn
.inside_bundle
= 1;
5167 as_bad (_("extra opening brace"));
5173 if (cur_vinsn
.inside_bundle
)
5174 finish_vinsn (&cur_vinsn
);
5177 as_bad (_("extra closing brace"));
5182 as_bad (_("syntax error"));
5189 /* md_flush_pending_output hook */
5192 xtensa_flush_pending_output (void)
5194 if (cur_vinsn
.inside_bundle
)
5195 as_bad (_("missing closing brace"));
5197 /* If there is a non-zero instruction fragment, close it. */
5198 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5200 frag_wane (frag_now
);
5202 xtensa_set_frag_assembly_state (frag_now
);
5204 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5206 xtensa_clear_insn_labels ();
5210 /* We had an error while parsing an instruction. The string might look
5211 like this: "insn arg1, arg2 }". If so, we need to see the closing
5212 brace and reset some fields. Otherwise, the vinsn never gets closed
5213 and the num_slots field will grow past the end of the array of slots,
5214 and bad things happen. */
5217 error_reset_cur_vinsn (void)
5219 if (cur_vinsn
.inside_bundle
)
5221 if (*input_line_pointer
== '}'
5222 || *(input_line_pointer
- 1) == '}'
5223 || *(input_line_pointer
- 2) == '}')
5224 xg_clear_vinsn (&cur_vinsn
);
5230 md_assemble (char *str
)
5232 xtensa_isa isa
= xtensa_default_isa
;
5235 bfd_boolean has_underbar
= FALSE
;
5236 char *arg_strings
[MAX_INSN_ARGS
];
5238 TInsn orig_insn
; /* Original instruction from the input. */
5240 tinsn_init (&orig_insn
);
5242 /* Split off the opcode. */
5243 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5244 opname
= xmalloc (opnamelen
+ 1);
5245 memcpy (opname
, str
, opnamelen
);
5246 opname
[opnamelen
] = '\0';
5248 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5251 as_bad (_("syntax error"));
5255 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5258 /* Check for an underbar prefix. */
5261 has_underbar
= TRUE
;
5265 orig_insn
.insn_type
= ITYPE_INSN
;
5267 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5269 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5270 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5272 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5273 if (fmt
== XTENSA_UNDEFINED
)
5275 as_bad (_("unknown opcode or format name '%s'"), opname
);
5276 error_reset_cur_vinsn ();
5279 if (!cur_vinsn
.inside_bundle
)
5281 as_bad (_("format names only valid inside bundles"));
5282 error_reset_cur_vinsn ();
5285 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5286 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5288 cur_vinsn
.format
= fmt
;
5289 free (has_underbar
? opname
- 1 : opname
);
5290 error_reset_cur_vinsn ();
5294 /* Parse the arguments. */
5295 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5297 as_bad (_("syntax error"));
5298 error_reset_cur_vinsn ();
5302 /* Free the opcode and argument strings, now that they've been parsed. */
5303 free (has_underbar
? opname
- 1 : opname
);
5305 while (num_args
-- > 0)
5306 free (arg_strings
[num_args
]);
5308 /* Get expressions for invisible operands. */
5309 if (get_invisible_operands (&orig_insn
))
5311 error_reset_cur_vinsn ();
5315 /* Check for the right number and type of arguments. */
5316 if (tinsn_check_arguments (&orig_insn
))
5318 error_reset_cur_vinsn ();
5322 dwarf2_where (&orig_insn
.loc
);
5324 xg_add_branch_and_loop_targets (&orig_insn
);
5326 /* Special-case for "entry" instruction. */
5327 if (orig_insn
.opcode
== xtensa_entry_opcode
)
5329 /* Check that the third opcode (#2) is >= 16. */
5330 if (orig_insn
.ntok
>= 3)
5332 expressionS
*exp
= &orig_insn
.tok
[2];
5336 if (exp
->X_add_number
< 16)
5337 as_warn (_("entry instruction with stack decrement < 16"));
5341 as_warn (_("entry instruction with non-constant decrement"));
5347 assemble_tokens (opcode, tok, ntok);
5348 expand the tokens from the orig_insn into the
5349 stack of instructions that will not expand
5350 unless required at relaxation time. */
5352 if (!cur_vinsn
.inside_bundle
)
5353 emit_single_op (&orig_insn
);
5354 else /* We are inside a bundle. */
5356 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5357 cur_vinsn
.num_slots
++;
5358 if (*input_line_pointer
== '}'
5359 || *(input_line_pointer
- 1) == '}'
5360 || *(input_line_pointer
- 2) == '}')
5361 finish_vinsn (&cur_vinsn
);
5364 /* We've just emitted a new instruction so clear the list of labels. */
5365 xtensa_clear_insn_labels ();
5369 /* HANDLE_ALIGN hook */
5371 /* For a .align directive, we mark the previous block with the alignment
5372 information. This will be placed in the object file in the
5373 property section corresponding to this section. */
5376 xtensa_handle_align (fragS
*fragP
)
5379 && ! fragP
->tc_frag_data
.is_literal
5380 && (fragP
->fr_type
== rs_align
5381 || fragP
->fr_type
== rs_align_code
)
5382 && fragP
->fr_address
+ fragP
->fr_fix
> 0
5383 && fragP
->fr_offset
> 0
5384 && now_seg
!= bss_section
)
5386 fragP
->tc_frag_data
.is_align
= TRUE
;
5387 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5390 if (fragP
->fr_type
== rs_align_test
)
5393 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5395 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5396 _("unaligned entry instruction"));
5401 /* TC_FRAG_INIT hook */
5404 xtensa_frag_init (fragS
*frag
)
5406 xtensa_set_frag_assembly_state (frag
);
5411 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5417 /* Round up a section size to the appropriate boundary. */
5420 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5422 return size
; /* Byte alignment is fine. */
5427 md_pcrel_from (fixS
*fixP
)
5430 static xtensa_insnbuf insnbuf
= NULL
;
5431 static xtensa_insnbuf slotbuf
= NULL
;
5434 xtensa_opcode opcode
;
5437 xtensa_isa isa
= xtensa_default_isa
;
5438 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5439 bfd_boolean alt_reloc
;
5441 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5446 insnbuf
= xtensa_insnbuf_alloc (isa
);
5447 slotbuf
= xtensa_insnbuf_alloc (isa
);
5450 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5451 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) insn_p
, 0);
5452 fmt
= xtensa_format_decode (isa
, insnbuf
);
5454 if (fmt
== XTENSA_UNDEFINED
)
5455 as_fatal (_("bad instruction format"));
5457 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5458 as_fatal (_("invalid relocation"));
5460 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5461 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5463 /* Check for "alternate" relocations (operand not specified). None
5464 of the current uses for these are really PC-relative. */
5465 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5467 if (opcode
!= xtensa_l32r_opcode
5468 && opcode
!= xtensa_const16_opcode
)
5469 as_fatal (_("invalid relocation for '%s' instruction"),
5470 xtensa_opcode_name (isa
, opcode
));
5474 opnum
= get_relaxable_immed (opcode
);
5476 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5477 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5479 as_bad_where (fixP
->fx_file
,
5481 _("invalid relocation for operand %d of '%s'"),
5482 opnum
, xtensa_opcode_name (isa
, opcode
));
5485 return 0 - opnd_value
;
5489 /* TC_FORCE_RELOCATION hook */
5492 xtensa_force_relocation (fixS
*fix
)
5494 switch (fix
->fx_r_type
)
5496 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5497 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5498 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5499 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5500 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5501 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5502 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5503 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5504 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5505 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5506 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5507 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5508 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5509 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5510 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5511 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5517 if (linkrelax
&& fix
->fx_addsy
5518 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5521 return generic_force_reloc (fix
);
5525 /* TC_VALIDATE_FIX_SUB hook */
5528 xtensa_validate_fix_sub (fixS
*fix
)
5530 segT add_symbol_segment
, sub_symbol_segment
;
5532 /* The difference of two symbols should be resolved by the assembler when
5533 linkrelax is not set. If the linker may relax the section containing
5534 the symbols, then an Xtensa DIFF relocation must be generated so that
5535 the linker knows to adjust the difference value. */
5536 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
5539 /* Make sure both symbols are in the same segment, and that segment is
5540 "normal" and relaxable. If the segment is not "normal", then the
5541 fix is not valid. If the segment is not "relaxable", then the fix
5542 should have been handled earlier. */
5543 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
5544 if (! SEG_NORMAL (add_symbol_segment
) ||
5545 ! relaxable_section (add_symbol_segment
))
5547 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
5548 return (sub_symbol_segment
== add_symbol_segment
);
5552 /* NO_PSEUDO_DOT hook */
5554 /* This function has nothing to do with pseudo dots, but this is the
5555 nearest macro to where the check needs to take place. FIXME: This
5559 xtensa_check_inside_bundle (void)
5561 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5562 as_bad (_("directives are not valid inside bundles"));
5564 /* This function must always return FALSE because it is called via a
5565 macro that has nothing to do with bundling. */
5570 /* md_elf_section_change_hook */
5573 xtensa_elf_section_change_hook (void)
5575 /* Set up the assembly state. */
5576 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5577 xtensa_set_frag_assembly_state (frag_now
);
5581 /* tc_fix_adjustable hook */
5584 xtensa_fix_adjustable (fixS
*fixP
)
5586 /* An offset is not allowed in combination with the difference of two
5587 symbols, but that cannot be easily detected after a local symbol
5588 has been adjusted to a (section+offset) form. Return 0 so that such
5589 an fix will not be adjusted. */
5590 if (fixP
->fx_subsy
&& fixP
->fx_addsy
&& fixP
->fx_offset
5591 && relaxable_section (S_GET_SEGMENT (fixP
->fx_subsy
)))
5594 /* We need the symbol name for the VTABLE entries. */
5595 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5596 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5604 md_apply_fix3 (fixS
*fixP
, valueT
*valP
, segT seg
)
5606 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5609 switch (fixP
->fx_r_type
)
5614 if (linkrelax
&& fixP
->fx_subsy
)
5616 switch (fixP
->fx_r_type
)
5619 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF8
;
5622 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF16
;
5625 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF32
;
5631 /* An offset is only allowed when it results from adjusting a
5632 local symbol into a section-relative offset. If the offset
5633 came from the original expression, tc_fix_adjustable will have
5634 prevented the fix from being converted to a section-relative
5635 form so that we can flag the error here. */
5636 if (fixP
->fx_offset
!= 0 && !symbol_section_p (fixP
->fx_addsy
))
5637 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5638 _("cannot represent subtraction with an offset"));
5640 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5641 - S_GET_VALUE (fixP
->fx_subsy
));
5643 /* The difference value gets written out, and the DIFF reloc
5644 identifies the address of the subtracted symbol (i.e., the one
5645 with the lowest address). */
5647 fixP
->fx_offset
-= val
;
5648 fixP
->fx_subsy
= NULL
;
5650 else if (! fixP
->fx_addsy
)
5657 md_number_to_chars (fixpos
, val
, fixP
->fx_size
);
5658 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5661 case BFD_RELOC_XTENSA_SLOT0_OP
:
5662 case BFD_RELOC_XTENSA_SLOT1_OP
:
5663 case BFD_RELOC_XTENSA_SLOT2_OP
:
5664 case BFD_RELOC_XTENSA_SLOT3_OP
:
5665 case BFD_RELOC_XTENSA_SLOT4_OP
:
5666 case BFD_RELOC_XTENSA_SLOT5_OP
:
5667 case BFD_RELOC_XTENSA_SLOT6_OP
:
5668 case BFD_RELOC_XTENSA_SLOT7_OP
:
5669 case BFD_RELOC_XTENSA_SLOT8_OP
:
5670 case BFD_RELOC_XTENSA_SLOT9_OP
:
5671 case BFD_RELOC_XTENSA_SLOT10_OP
:
5672 case BFD_RELOC_XTENSA_SLOT11_OP
:
5673 case BFD_RELOC_XTENSA_SLOT12_OP
:
5674 case BFD_RELOC_XTENSA_SLOT13_OP
:
5675 case BFD_RELOC_XTENSA_SLOT14_OP
:
5678 /* Write the tentative value of a PC-relative relocation to a
5679 local symbol into the instruction. The value will be ignored
5680 by the linker, and it makes the object file disassembly
5681 readable when all branch targets are encoded in relocations. */
5683 assert (fixP
->fx_addsy
);
5684 if (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
&& !fixP
->fx_plt
5685 && !S_FORCE_RELOC (fixP
->fx_addsy
, 1))
5687 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5688 - md_pcrel_from (fixP
));
5689 (void) xg_apply_fix_value (fixP
, val
);
5692 else if (! fixP
->fx_addsy
)
5695 if (xg_apply_fix_value (fixP
, val
))
5700 case BFD_RELOC_XTENSA_PLT
:
5701 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5702 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5703 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5704 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5705 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5706 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5707 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5708 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5709 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5710 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5711 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5712 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5713 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5714 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5715 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5716 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5717 /* These all need to be resolved at link-time. Do nothing now. */
5720 case BFD_RELOC_VTABLE_INHERIT
:
5721 case BFD_RELOC_VTABLE_ENTRY
:
5726 as_bad (_("unhandled local relocation fix %s"),
5727 bfd_get_reloc_code_name (fixP
->fx_r_type
));
5733 md_atof (int type
, char *litP
, int *sizeP
)
5736 LITTLENUM_TYPE words
[4];
5752 return "bad call to md_atof";
5755 t
= atof_ieee (input_line_pointer
, type
, words
);
5757 input_line_pointer
= t
;
5761 for (i
= prec
- 1; i
>= 0; i
--)
5764 if (target_big_endian
)
5765 idx
= (prec
- 1 - i
);
5767 md_number_to_chars (litP
, (valueT
) words
[idx
], 2);
5776 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
5778 return total_frag_text_expansion (fragP
);
5782 /* Translate internal representation of relocation info to BFD target
5786 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
5790 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
5791 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5792 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5793 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5795 /* Make sure none of our internal relocations make it this far.
5796 They'd better have been fully resolved by this point. */
5797 assert ((int) fixp
->fx_r_type
> 0);
5799 reloc
->addend
= fixp
->fx_offset
;
5801 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
5802 if (reloc
->howto
== NULL
)
5804 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5805 _("cannot represent `%s' relocation in object file"),
5806 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5807 free (reloc
->sym_ptr_ptr
);
5812 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
5813 as_fatal (_("internal error? cannot generate `%s' relocation"),
5814 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5820 /* Checks for resource conflicts between instructions. */
5822 /* The func unit stuff could be implemented as bit-vectors rather
5823 than the iterative approach here. If it ends up being too
5824 slow, we will switch it. */
5827 new_resource_table (void *data
,
5830 unit_num_copies_func uncf
,
5831 opcode_num_units_func onuf
,
5832 opcode_funcUnit_use_unit_func ouuf
,
5833 opcode_funcUnit_use_stage_func ousf
)
5836 resource_table
*rt
= (resource_table
*) xmalloc (sizeof (resource_table
));
5838 rt
->cycles
= cycles
;
5839 rt
->allocated_cycles
= cycles
;
5841 rt
->unit_num_copies
= uncf
;
5842 rt
->opcode_num_units
= onuf
;
5843 rt
->opcode_unit_use
= ouuf
;
5844 rt
->opcode_unit_stage
= ousf
;
5846 rt
->units
= (char **) xcalloc (cycles
, sizeof (char *));
5847 for (i
= 0; i
< cycles
; i
++)
5848 rt
->units
[i
] = (char *) xcalloc (nu
, sizeof (char));
5855 clear_resource_table (resource_table
*rt
)
5858 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
5859 for (j
= 0; j
< rt
->num_units
; j
++)
5860 rt
->units
[i
][j
] = 0;
5864 /* We never shrink it, just fake it into thinking so. */
5867 resize_resource_table (resource_table
*rt
, int cycles
)
5871 rt
->cycles
= cycles
;
5872 if (cycles
<= rt
->allocated_cycles
)
5875 old_cycles
= rt
->allocated_cycles
;
5876 rt
->allocated_cycles
= cycles
;
5878 rt
->units
= xrealloc (rt
->units
, sizeof (char *) * rt
->allocated_cycles
);
5879 for (i
= 0; i
< old_cycles
; i
++)
5880 rt
->units
[i
] = xrealloc (rt
->units
[i
], sizeof (char) * rt
->num_units
);
5881 for (i
= old_cycles
; i
< cycles
; i
++)
5882 rt
->units
[i
] = xcalloc (rt
->num_units
, sizeof (char));
5887 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5890 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5892 for (i
= 0; i
< uses
; i
++)
5894 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5895 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5896 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
5897 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
5898 if (copies_in_use
>= copies
)
5906 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5909 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5911 for (i
= 0; i
< uses
; i
++)
5913 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5914 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5915 /* Note that this allows resources to be oversubscribed. That's
5916 essential to the way the optional scheduler works.
5917 resources_available reports when a resource is over-subscribed,
5918 so it's easy to tell. */
5919 rt
->units
[stage
+ cycle
][unit
]++;
5925 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5928 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5930 for (i
= 0; i
< uses
; i
++)
5932 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5933 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5934 rt
->units
[stage
+ cycle
][unit
]--;
5935 assert (rt
->units
[stage
+ cycle
][unit
] >= 0);
5940 /* Wrapper functions make parameterized resource reservation
5944 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
5946 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5952 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
5954 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5959 /* Note that this function does not check issue constraints, but
5960 solely whether the hardware is available to execute the given
5961 instructions together. It also doesn't check if the tinsns
5962 write the same state, or access the same tieports. That is
5963 checked by check_t1_t2_reads_and_writes. */
5966 resources_conflict (vliw_insn
*vinsn
)
5969 static resource_table
*rt
= NULL
;
5971 /* This is the most common case by far. Optimize it. */
5972 if (vinsn
->num_slots
== 1)
5977 xtensa_isa isa
= xtensa_default_isa
;
5978 rt
= new_resource_table
5979 (isa
, xtensa_isa_num_pipe_stages (isa
),
5980 xtensa_isa_num_funcUnits (isa
),
5981 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
5982 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
5983 opcode_funcUnit_use_unit
,
5984 opcode_funcUnit_use_stage
);
5987 clear_resource_table (rt
);
5989 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5991 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
5993 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
6000 /* finish_vinsn, emit_single_op and helper functions. */
6002 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
6003 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
6004 static void bundle_single_op (TInsn
*);
6005 static void xg_assemble_vliw_tokens (vliw_insn
*);
6008 /* We have reached the end of a bundle; emit into the frag. */
6011 finish_vinsn (vliw_insn
*vinsn
)
6018 if (find_vinsn_conflicts (vinsn
))
6020 xg_clear_vinsn (vinsn
);
6024 /* First, find a format that works. */
6025 if (vinsn
->format
== XTENSA_UNDEFINED
)
6026 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6028 if (vinsn
->format
== XTENSA_UNDEFINED
)
6030 as_where (&file_name
, &line
);
6031 as_bad_where (file_name
, line
,
6032 _("couldn't find a valid instruction format"));
6033 fprintf (stderr
, _(" ops were: "));
6034 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6035 fprintf (stderr
, _(" %s;"),
6036 xtensa_opcode_name (xtensa_default_isa
,
6037 vinsn
->slots
[i
].opcode
));
6038 fprintf (stderr
, _("\n"));
6039 xg_clear_vinsn (vinsn
);
6043 if (vinsn
->num_slots
6044 != xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
))
6046 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
6047 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
6048 xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
),
6050 xg_clear_vinsn (vinsn
);
6054 if (resources_conflict (vinsn
))
6056 as_where (&file_name
, &line
);
6057 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6058 fprintf (stderr
, " ops were: ");
6059 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6060 fprintf (stderr
, " %s;",
6061 xtensa_opcode_name (xtensa_default_isa
,
6062 vinsn
->slots
[i
].opcode
));
6063 fprintf (stderr
, "\n");
6064 xg_clear_vinsn (vinsn
);
6068 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6070 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
6072 symbolS
*lit_sym
= NULL
;
6074 bfd_boolean e
= FALSE
;
6075 bfd_boolean saved_density
= density_supported
;
6077 /* We don't want to narrow ops inside multi-slot bundles. */
6078 if (vinsn
->num_slots
> 1)
6079 density_supported
= FALSE
;
6081 istack_init (&slotstack
);
6082 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
6084 vinsn
->slots
[i
].opcode
=
6085 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6087 vinsn
->slots
[i
].ntok
= 0;
6090 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
6096 density_supported
= saved_density
;
6100 xg_clear_vinsn (vinsn
);
6104 for (j
= 0; j
< slotstack
.ninsn
; j
++)
6106 TInsn
*insn
= &slotstack
.insn
[j
];
6107 if (insn
->insn_type
== ITYPE_LITERAL
)
6109 assert (lit_sym
== NULL
);
6110 lit_sym
= xg_assemble_literal (insn
);
6114 assert (insn
->insn_type
== ITYPE_INSN
);
6116 xg_resolve_literals (insn
, lit_sym
);
6117 if (j
!= slotstack
.ninsn
- 1)
6118 emit_single_op (insn
);
6122 if (vinsn
->num_slots
> 1)
6124 if (opcode_fits_format_slot
6125 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6128 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6132 bundle_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6133 if (vinsn
->format
== XTENSA_UNDEFINED
)
6134 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6136 vinsn
->slots
[i
].opcode
6137 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6140 vinsn
->slots
[i
].ntok
= 0;
6145 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6146 vinsn
->format
= XTENSA_UNDEFINED
;
6151 /* Now check resource conflicts on the modified bundle. */
6152 if (resources_conflict (vinsn
))
6154 as_where (&file_name
, &line
);
6155 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6156 fprintf (stderr
, " ops were: ");
6157 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6158 fprintf (stderr
, " %s;",
6159 xtensa_opcode_name (xtensa_default_isa
,
6160 vinsn
->slots
[i
].opcode
));
6161 fprintf (stderr
, "\n");
6162 xg_clear_vinsn (vinsn
);
6166 /* First, find a format that works. */
6167 if (vinsn
->format
== XTENSA_UNDEFINED
)
6168 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6170 xg_assemble_vliw_tokens (vinsn
);
6172 xg_clear_vinsn (vinsn
);
6176 /* Given an vliw instruction, what conflicts are there in register
6177 usage and in writes to states and queues?
6179 This function does two things:
6180 1. Reports an error when a vinsn contains illegal combinations
6181 of writes to registers states or queues.
6182 2. Marks individual tinsns as not relaxable if the combination
6183 contains antidependencies.
6185 Job 2 handles things like swap semantics in instructions that need
6186 to be relaxed. For example,
6190 normally would be relaxed to
6195 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6197 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6199 then we can't relax it into
6202 { add a0, a1, a0 ; add a2, a0, a4 ; }
6204 because the value of a0 is trashed before the second add can read it. */
6206 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6209 find_vinsn_conflicts (vliw_insn
*vinsn
)
6213 xtensa_isa isa
= xtensa_default_isa
;
6215 assert (!past_xtensa_end
);
6217 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6219 TInsn
*op1
= &vinsn
->slots
[i
];
6220 if (op1
->is_specific_opcode
)
6221 op1
->keep_wide
= TRUE
;
6223 op1
->keep_wide
= FALSE
;
6226 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6228 TInsn
*op1
= &vinsn
->slots
[i
];
6230 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6233 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6237 TInsn
*op2
= &vinsn
->slots
[j
];
6238 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6239 switch (conflict_type
)
6242 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6243 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6244 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6247 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6248 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6249 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6252 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same queue"),
6253 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6254 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6257 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile queue accesses"),
6258 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6259 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6262 /* Everything is OK. */
6265 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6266 || conflict_type
== 'a');
6273 as_bad (_("multiple branches or jumps in the same bundle"));
6281 /* Check how the state used by t1 and t2 relate.
6284 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6285 case B: no relationship between what is read and written (both could
6286 read the same reg though)
6287 case C: t1 writes a register t2 writes (a register conflict within a
6289 case D: t1 writes a state that t2 also writes
6290 case E: t1 writes a tie queue that t2 also writes
6291 case F: two volatile queue accesses
6295 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6297 xtensa_isa isa
= xtensa_default_isa
;
6298 xtensa_regfile t1_regfile
, t2_regfile
;
6300 int t1_base_reg
, t1_last_reg
;
6301 int t2_base_reg
, t2_last_reg
;
6302 char t1_inout
, t2_inout
;
6304 char conflict
= 'b';
6309 bfd_boolean t1_volatile
= FALSE
;
6310 bfd_boolean t2_volatile
= FALSE
;
6312 /* Check registers. */
6313 for (j
= 0; j
< t2
->ntok
; j
++)
6315 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6318 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6319 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6320 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6322 for (i
= 0; i
< t1
->ntok
; i
++)
6324 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6327 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6329 if (t1_regfile
!= t2_regfile
)
6332 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6333 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6335 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6336 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6338 if (t1_inout
== 'm' || t1_inout
== 'o'
6339 || t2_inout
== 'm' || t2_inout
== 'o')
6346 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6347 t1_last_reg
= (t1_base_reg
6348 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6350 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6352 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6354 if (t1_reg
!= t2_reg
)
6357 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6363 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6369 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6377 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6378 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6379 for (j
= 0; j
< t2_states
; j
++)
6381 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6382 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6383 for (i
= 0; i
< t1_states
; i
++)
6385 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6386 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6390 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6396 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6402 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6407 /* Check tieports. */
6408 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6409 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6410 for (j
= 0; j
< t2_interfaces
; j
++)
6412 xtensa_interface t2_int
6413 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6414 int t2_class
= xtensa_interface_class_id (isa
, t2_int
);
6416 t2_inout
= xtensa_interface_inout (isa
, j
);
6417 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1)
6420 for (i
= 0; i
< t1_interfaces
; i
++)
6422 xtensa_interface t1_int
6423 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6424 int t1_class
= xtensa_interface_class_id (isa
, t1_int
);
6426 t1_inout
= xtensa_interface_inout (isa
, i
);
6427 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1)
6430 if (t1_volatile
&& t2_volatile
&& (t1_class
== t2_class
))
6433 if (t1_int
!= t2_int
)
6436 if (t2_inout
== 'i' && t1_inout
== 'o')
6442 if (t1_inout
== 'i' && t2_inout
== 'o')
6448 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6457 static xtensa_format
6458 xg_find_narrowest_format (vliw_insn
*vinsn
)
6460 /* Right now we assume that the ops within the vinsn are properly
6461 ordered for the slots that the programmer wanted them in. In
6462 other words, we don't rearrange the ops in hopes of finding a
6463 better format. The scheduler handles that. */
6465 xtensa_isa isa
= xtensa_default_isa
;
6466 xtensa_format format
;
6467 vliw_insn v_copy
= *vinsn
;
6468 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6470 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6473 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6477 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6479 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6481 v_copy
.slots
[slot
].opcode
=
6482 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6483 v_copy
.slots
[slot
].ntok
= 0;
6486 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6489 else if (v_copy
.num_slots
> 1)
6492 /* Try the widened version. */
6493 if (!v_copy
.slots
[slot
].keep_wide
6494 && !v_copy
.slots
[slot
].is_specific_opcode
6495 && xg_is_narrow_insn (&v_copy
.slots
[slot
])
6496 && !xg_expand_narrow (&widened
, &v_copy
.slots
[slot
])
6497 && opcode_fits_format_slot (widened
.opcode
,
6500 /* The xg_is_narrow clause requires some explanation:
6502 addi can be "widened" to an addmi, which is then
6503 expanded to an addmi/addi pair if the immediate
6504 requires it, but here we must have a single widen
6507 xg_is_narrow tells us that addi isn't really
6508 narrow. The widen_spec_list says that there are
6511 v_copy
.slots
[slot
] = widened
;
6516 if (fit
== v_copy
.num_slots
)
6519 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6520 vinsn
->format
= format
;
6526 if (format
== xtensa_isa_num_formats (isa
))
6527 return XTENSA_UNDEFINED
;
6533 /* Return the additional space needed in a frag
6534 for possible relaxations of any ops in a VLIW insn.
6535 Also fill out the relaxations that might be required of
6536 each tinsn in the vinsn. */
6539 relaxation_requirements (vliw_insn
*vinsn
)
6541 int extra_space
= 0;
6544 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6546 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6547 if (!tinsn_has_symbolic_operands (tinsn
))
6549 /* A narrow instruction could be widened later to help
6550 alignment issues. */
6551 if (xg_is_narrow_insn (tinsn
)
6552 && !tinsn
->is_specific_opcode
6553 && vinsn
->num_slots
== 1)
6555 /* Difference in bytes between narrow and wide insns... */
6557 tinsn
->subtype
= RELAX_NARROW
;
6558 tinsn
->record_fix
= TRUE
;
6563 tinsn
->record_fix
= FALSE
;
6564 /* No extra_space needed. */
6569 if (workaround_b_j_loop_end
6570 && tinsn
->opcode
== xtensa_jx_opcode
6571 && use_transform ())
6573 /* Add 2 of these. */
6574 extra_space
+= 3; /* for the nop size */
6575 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6578 /* Need to assemble it with space for the relocation. */
6579 if (xg_is_relaxable_insn (tinsn
, 0)
6580 && !tinsn
->is_specific_opcode
)
6582 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6583 int max_literal_size
=
6584 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6586 tinsn
->literal_space
= max_literal_size
;
6588 tinsn
->subtype
= RELAX_IMMED
;
6589 tinsn
->record_fix
= FALSE
;
6590 extra_space
+= max_size
;
6594 tinsn
->record_fix
= TRUE
;
6595 /* No extra space needed. */
6604 bundle_single_op (TInsn
*orig_insn
)
6606 xtensa_isa isa
= xtensa_default_isa
;
6611 v
.format
= op_placement_table
[orig_insn
->opcode
].narrowest
;
6612 assert (v
.format
!= XTENSA_UNDEFINED
);
6613 v
.num_slots
= xtensa_format_num_slots (isa
, v
.format
);
6616 !opcode_fits_format_slot (orig_insn
->opcode
, v
.format
, slot
);
6619 v
.slots
[slot
].opcode
=
6620 xtensa_format_slot_nop_opcode (isa
, v
.format
, slot
);
6621 v
.slots
[slot
].ntok
= 0;
6622 v
.slots
[slot
].insn_type
= ITYPE_INSN
;
6625 v
.slots
[slot
] = *orig_insn
;
6628 for ( ; slot
< v
.num_slots
; slot
++)
6630 v
.slots
[slot
].opcode
=
6631 xtensa_format_slot_nop_opcode (isa
, v
.format
, slot
);
6632 v
.slots
[slot
].ntok
= 0;
6633 v
.slots
[slot
].insn_type
= ITYPE_INSN
;
6642 emit_single_op (TInsn
*orig_insn
)
6645 IStack istack
; /* put instructions into here */
6646 symbolS
*lit_sym
= NULL
;
6647 symbolS
*label_sym
= NULL
;
6649 istack_init (&istack
);
6651 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6652 Because the scheduling and bundling characteristics of movi and
6653 l32r or const16 are so different, we can do much better if we relax
6654 it prior to scheduling and bundling, rather than after. */
6655 if ((orig_insn
->opcode
== xtensa_movi_opcode
6656 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
6657 && !cur_vinsn
.inside_bundle
6658 && (orig_insn
->tok
[1].X_op
== O_symbol
6659 || orig_insn
->tok
[1].X_op
== O_pltrel
))
6660 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
6662 if (xg_expand_assembly_insn (&istack
, orig_insn
))
6665 for (i
= 0; i
< istack
.ninsn
; i
++)
6667 TInsn
*insn
= &istack
.insn
[i
];
6668 switch (insn
->insn_type
)
6671 assert (lit_sym
== NULL
);
6672 lit_sym
= xg_assemble_literal (insn
);
6676 static int relaxed_sym_idx
= 0;
6677 char *label
= xmalloc (strlen (FAKE_LABEL_NAME
) + 12);
6678 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
6680 assert (label_sym
== NULL
);
6681 label_sym
= symbol_find_or_make (label
);
6688 xg_resolve_literals (insn
, lit_sym
);
6690 xg_resolve_labels (insn
, label_sym
);
6691 bundle_single_op (insn
);
6703 total_frag_text_expansion (fragS
*fragP
)
6706 int total_expansion
= 0;
6708 for (slot
= 0; slot
< MAX_SLOTS
; slot
++)
6709 total_expansion
+= fragP
->tc_frag_data
.text_expansion
[slot
];
6711 return total_expansion
;
6715 /* Emit a vliw instruction to the current fragment. */
6718 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
6720 bfd_boolean finish_frag
= FALSE
;
6721 bfd_boolean is_jump
= FALSE
;
6722 bfd_boolean is_branch
= FALSE
;
6723 xtensa_isa isa
= xtensa_default_isa
;
6729 struct dwarf2_line_info best_loc
;
6731 best_loc
.line
= INT_MAX
;
6733 if (generating_literals
)
6735 static int reported
= 0;
6737 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
6738 _("cannot assemble into a literal fragment"));
6745 if (frag_now_fix () != 0
6746 && (! frag_now
->tc_frag_data
.is_insn
6747 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6748 || !use_transform () != frag_now
->tc_frag_data
.is_no_transform
6749 || (directive_state
[directive_longcalls
]
6750 != frag_now
->tc_frag_data
.use_longcalls
)
6751 || (directive_state
[directive_absolute_literals
]
6752 != frag_now
->tc_frag_data
.use_absolute_literals
)))
6754 frag_wane (frag_now
);
6756 xtensa_set_frag_assembly_state (frag_now
);
6759 if (workaround_a0_b_retw
6760 && vinsn
->num_slots
== 1
6761 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
6762 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
6763 && use_transform ())
6765 has_a0_b_retw
= TRUE
;
6767 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
6768 After the first assembly pass we will check all of them and
6769 add a nop if needed. */
6770 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6771 frag_var (rs_machine_dependent
, 4, 4,
6772 RELAX_ADD_NOP_IF_A0_B_RETW
,
6773 frag_now
->fr_symbol
,
6774 frag_now
->fr_offset
,
6776 xtensa_set_frag_assembly_state (frag_now
);
6777 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6778 frag_var (rs_machine_dependent
, 4, 4,
6779 RELAX_ADD_NOP_IF_A0_B_RETW
,
6780 frag_now
->fr_symbol
,
6781 frag_now
->fr_offset
,
6783 xtensa_set_frag_assembly_state (frag_now
);
6786 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6788 /* See if the instruction implies an aligned section. */
6789 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[i
].opcode
) == 1)
6790 record_alignment (now_seg
, 2);
6792 /* Also determine the best line number for debug info. */
6793 best_loc
= vinsn
->slots
[i
].loc
.line
< best_loc
.line
6794 ? vinsn
->slots
[i
].loc
: best_loc
;
6797 /* Special cases for instructions that force an alignment... */
6798 /* None of these opcodes are bundle-able. */
6799 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
6803 xtensa_set_frag_assembly_state (frag_now
);
6804 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6806 max_fill
= get_text_align_max_fill_size
6807 (get_text_align_power (xtensa_fetch_width
),
6808 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
6810 if (use_transform ())
6811 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
6812 RELAX_ALIGN_NEXT_OPCODE
,
6813 frag_now
->fr_symbol
,
6814 frag_now
->fr_offset
,
6817 frag_var (rs_machine_dependent
, 0, 0,
6818 RELAX_CHECK_ALIGN_NEXT_OPCODE
, 0, 0, NULL
);
6819 xtensa_set_frag_assembly_state (frag_now
);
6821 xtensa_move_labels (frag_now
, 0, FALSE
);
6824 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
6825 && !vinsn
->slots
[0].is_specific_opcode
)
6827 xtensa_mark_literal_pool_location ();
6828 xtensa_move_labels (frag_now
, 0, TRUE
);
6829 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
6832 if (vinsn
->num_slots
== 1)
6834 if (workaround_a0_b_retw
&& use_transform ())
6835 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
6836 is_register_writer (&vinsn
->slots
[0], "a", 0));
6838 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
6839 is_bad_loopend_opcode (&vinsn
->slots
[0]));
6842 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
6844 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
6846 extra_space
= relaxation_requirements (vinsn
);
6848 /* vinsn_to_insnbuf will produce the error. */
6849 if (vinsn
->format
!= XTENSA_UNDEFINED
)
6851 f
= frag_more (insn_size
+ extra_space
);
6852 xtensa_set_frag_assembly_state (frag_now
);
6853 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6856 vinsn_to_insnbuf (vinsn
, f
, frag_now
, TRUE
);
6857 if (vinsn
->format
== XTENSA_UNDEFINED
)
6860 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, (unsigned char *) f
, 0);
6862 xtensa_dwarf2_emit_insn (insn_size
- extra_space
, &best_loc
);
6864 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6866 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6867 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
6868 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
6869 frag_now
->tc_frag_data
.slot_sub_symbols
[slot
] = tinsn
->sub_symbol
;
6870 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
6871 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
6872 if (tinsn
->literal_space
!= 0)
6873 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
6875 if (tinsn
->subtype
== RELAX_NARROW
)
6876 assert (vinsn
->num_slots
== 1);
6877 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
6879 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
6882 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->record_fix
6883 || tinsn
->offset
|| tinsn
->literal_frag
|| is_jump
|| is_branch
)
6887 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6888 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
6892 frag_variant (rs_machine_dependent
,
6893 extra_space
, extra_space
, RELAX_SLOTS
,
6894 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
6895 xtensa_set_frag_assembly_state (frag_now
);
6898 /* Special cases for loops:
6899 close_loop_end should be inserted AFTER short_loop.
6900 Make sure that CLOSE loops are processed BEFORE short_loops
6901 when converting them. */
6903 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
6904 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
)
6905 && !vinsn
->slots
[0].is_specific_opcode
)
6907 if (workaround_short_loop
&& use_transform ())
6909 maybe_has_short_loop
= TRUE
;
6910 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6911 frag_var (rs_machine_dependent
, 4, 4,
6912 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6913 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6914 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6915 frag_var (rs_machine_dependent
, 4, 4,
6916 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6917 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6920 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
6921 loop at least 12 bytes away from another loop's end. */
6922 if (workaround_close_loop_end
&& use_transform ())
6924 maybe_has_close_loop_end
= TRUE
;
6925 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6926 frag_var (rs_machine_dependent
, 12, 12,
6927 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
6928 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6932 if (use_transform ())
6936 assert (finish_frag
);
6937 frag_var (rs_machine_dependent
,
6938 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6940 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6941 xtensa_set_frag_assembly_state (frag_now
);
6943 else if (is_branch
&& do_align_targets ())
6945 assert (finish_frag
);
6946 frag_var (rs_machine_dependent
,
6947 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6948 RELAX_MAYBE_UNREACHABLE
,
6949 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6950 xtensa_set_frag_assembly_state (frag_now
);
6951 frag_var (rs_machine_dependent
,
6953 RELAX_MAYBE_DESIRE_ALIGN
,
6954 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6955 xtensa_set_frag_assembly_state (frag_now
);
6959 /* Now, if the original opcode was a call... */
6960 if (do_align_targets ()
6961 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
6963 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
6964 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6965 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
6966 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6967 xtensa_set_frag_assembly_state (frag_now
);
6970 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6972 frag_wane (frag_now
);
6974 xtensa_set_frag_assembly_state (frag_now
);
6979 /* xtensa_end and helper functions. */
6981 static void xtensa_cleanup_align_frags (void);
6982 static void xtensa_fix_target_frags (void);
6983 static void xtensa_mark_narrow_branches (void);
6984 static void xtensa_mark_zcl_first_insns (void);
6985 static void xtensa_fix_a0_b_retw_frags (void);
6986 static void xtensa_fix_b_j_loop_end_frags (void);
6987 static void xtensa_fix_close_loop_end_frags (void);
6988 static void xtensa_fix_short_loop_frags (void);
6989 static void xtensa_sanity_check (void);
6994 directive_balance ();
6995 xtensa_flush_pending_output ();
6997 past_xtensa_end
= TRUE
;
6999 xtensa_move_literals ();
7001 xtensa_reorder_segments ();
7002 xtensa_cleanup_align_frags ();
7003 xtensa_fix_target_frags ();
7004 if (workaround_a0_b_retw
&& has_a0_b_retw
)
7005 xtensa_fix_a0_b_retw_frags ();
7006 if (workaround_b_j_loop_end
)
7007 xtensa_fix_b_j_loop_end_frags ();
7009 /* "close_loop_end" should be processed BEFORE "short_loop". */
7010 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
7011 xtensa_fix_close_loop_end_frags ();
7013 if (workaround_short_loop
&& maybe_has_short_loop
)
7014 xtensa_fix_short_loop_frags ();
7015 xtensa_mark_narrow_branches ();
7016 xtensa_mark_zcl_first_insns ();
7018 xtensa_sanity_check ();
7023 xtensa_cleanup_align_frags (void)
7027 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7030 /* Walk over all of the fragments in a subsection. */
7031 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7033 if ((fragP
->fr_type
== rs_align
7034 || fragP
->fr_type
== rs_align_code
7035 || (fragP
->fr_type
== rs_machine_dependent
7036 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
7037 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
7038 && fragP
->fr_fix
== 0)
7040 fragS
*next
= fragP
->fr_next
;
7043 && next
->fr_fix
== 0
7044 && next
->fr_type
== rs_machine_dependent
7045 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7048 next
= next
->fr_next
;
7051 /* If we don't widen branch targets, then they
7052 will be easier to align. */
7053 if (fragP
->tc_frag_data
.is_branch_target
7054 && fragP
->fr_opcode
== fragP
->fr_literal
7055 && fragP
->fr_type
== rs_machine_dependent
7056 && fragP
->fr_subtype
== RELAX_SLOTS
7057 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
7059 if (fragP
->fr_type
== rs_machine_dependent
7060 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
7061 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
7067 /* Re-process all of the fragments looking to convert all of the
7068 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
7069 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7070 Otherwise, convert to a .fill 0. */
7073 xtensa_fix_target_frags (void)
7077 /* When this routine is called, all of the subsections are still intact
7078 so we walk over subsections instead of sections. */
7079 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7083 /* Walk over all of the fragments in a subsection. */
7084 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7086 if (fragP
->fr_type
== rs_machine_dependent
7087 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7089 if (next_frag_is_branch_target (fragP
))
7090 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7099 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
7102 xtensa_mark_narrow_branches (void)
7106 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7109 /* Walk over all of the fragments in a subsection. */
7110 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7112 if (fragP
->fr_type
== rs_machine_dependent
7113 && fragP
->fr_subtype
== RELAX_SLOTS
7114 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7117 const expressionS
*expr
;
7120 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7121 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
7123 expr
= &vinsn
.slots
[0].tok
[1];
7124 symbolP
= expr
->X_add_symbol
;
7126 if (vinsn
.num_slots
== 1
7127 && xtensa_opcode_is_branch (xtensa_default_isa
,
7128 vinsn
.slots
[0].opcode
)
7129 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
7130 && is_narrow_branch_guaranteed_in_range (fragP
,
7133 fragP
->fr_subtype
= RELAX_SLOTS
;
7134 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
7142 /* A branch is typically widened only when its target is out of
7143 range. However, we would like to widen them to align a subsequent
7144 branch target when possible.
7146 Because the branch relaxation code is so convoluted, the optimal solution
7147 (combining the two cases) is difficult to get right in all circumstances.
7148 We therefore go with an "almost as good" solution, where we only
7149 use for alignment narrow branches that definitely will not expand to a
7150 jump and a branch. These functions find and mark these cases. */
7152 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
7153 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7154 We start counting beginning with the frag after the 2-byte branch, so the
7155 maximum offset is (4 - 2) + 63 = 65. */
7156 #define MAX_IMMED6 65
7158 static offsetT
unrelaxed_frag_max_size (fragS
*);
7161 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
7163 const expressionS
*expr
= &tinsn
->tok
[1];
7164 symbolS
*symbolP
= expr
->X_add_symbol
;
7165 fragS
*target_frag
= symbol_get_frag (symbolP
);
7166 offsetT max_distance
= expr
->X_add_number
;
7167 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
7168 if (is_branch_jmp_to_next (tinsn
, fragP
))
7171 /* The branch doesn't branch over it's own frag,
7172 but over the subsequent ones. */
7173 fragP
= fragP
->fr_next
;
7174 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
7176 max_distance
+= unrelaxed_frag_max_size (fragP
);
7177 fragP
= fragP
->fr_next
;
7179 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
7186 xtensa_mark_zcl_first_insns (void)
7190 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7193 /* Walk over all of the fragments in a subsection. */
7194 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7196 if (fragP
->fr_type
== rs_machine_dependent
7197 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7198 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7200 /* Find the loop frag. */
7201 fragS
*targ_frag
= next_non_empty_frag (fragP
);
7202 /* Find the first insn frag. */
7203 targ_frag
= next_non_empty_frag (targ_frag
);
7205 /* Of course, sometimes (mostly for toy test cases) a
7206 zero-cost loop instruction is the last in a section. */
7209 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
7210 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
7219 /* Re-process all of the fragments looking to convert all of the
7220 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7221 conditional branch or a retw/retw.n, convert this frag to one that
7222 will generate a NOP. In any case close it off with a .fill 0. */
7224 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
7227 xtensa_fix_a0_b_retw_frags (void)
7231 /* When this routine is called, all of the subsections are still intact
7232 so we walk over subsections instead of sections. */
7233 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7237 /* Walk over all of the fragments in a subsection. */
7238 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7240 if (fragP
->fr_type
== rs_machine_dependent
7241 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
7243 if (next_instrs_are_b_retw (fragP
))
7245 if (fragP
->tc_frag_data
.is_no_transform
)
7246 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7248 relax_frag_add_nop (fragP
);
7258 next_instrs_are_b_retw (fragS
*fragP
)
7260 xtensa_opcode opcode
;
7262 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
7263 static xtensa_insnbuf insnbuf
= NULL
;
7264 static xtensa_insnbuf slotbuf
= NULL
;
7265 xtensa_isa isa
= xtensa_default_isa
;
7268 bfd_boolean branch_seen
= FALSE
;
7272 insnbuf
= xtensa_insnbuf_alloc (isa
);
7273 slotbuf
= xtensa_insnbuf_alloc (isa
);
7276 if (next_fragP
== NULL
)
7279 /* Check for the conditional branch. */
7280 xtensa_insnbuf_from_chars
7281 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7282 fmt
= xtensa_format_decode (isa
, insnbuf
);
7283 if (fmt
== XTENSA_UNDEFINED
)
7286 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7288 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
7289 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
7291 branch_seen
= (branch_seen
7292 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
7298 offset
+= xtensa_format_length (isa
, fmt
);
7299 if (offset
== next_fragP
->fr_fix
)
7301 next_fragP
= next_non_empty_frag (next_fragP
);
7305 if (next_fragP
== NULL
)
7308 /* Check for the retw/retw.n. */
7309 xtensa_insnbuf_from_chars
7310 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7311 fmt
= xtensa_format_decode (isa
, insnbuf
);
7313 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
7314 have no problems. */
7315 if (fmt
== XTENSA_UNDEFINED
7316 || xtensa_format_num_slots (isa
, fmt
) != 1)
7319 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
7320 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
7322 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
7329 /* Re-process all of the fragments looking to convert all of the
7330 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
7331 loop end label, convert this frag to one that will generate a NOP.
7332 In any case close it off with a .fill 0. */
7334 static bfd_boolean
next_instr_is_loop_end (fragS
*);
7337 xtensa_fix_b_j_loop_end_frags (void)
7341 /* When this routine is called, all of the subsections are still intact
7342 so we walk over subsections instead of sections. */
7343 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7347 /* Walk over all of the fragments in a subsection. */
7348 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7350 if (fragP
->fr_type
== rs_machine_dependent
7351 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
7353 if (next_instr_is_loop_end (fragP
))
7355 if (fragP
->tc_frag_data
.is_no_transform
)
7356 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
7358 relax_frag_add_nop (fragP
);
7368 next_instr_is_loop_end (fragS
*fragP
)
7370 const fragS
*next_fragP
;
7372 if (next_frag_is_loop_target (fragP
))
7375 next_fragP
= next_non_empty_frag (fragP
);
7376 if (next_fragP
== NULL
)
7379 if (!next_frag_is_loop_target (next_fragP
))
7382 /* If the size is >= 3 then there is more than one instruction here.
7383 The hardware bug will not fire. */
7384 if (next_fragP
->fr_fix
> 3)
7391 /* Re-process all of the fragments looking to convert all of the
7392 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
7393 not MY loop's loop end within 12 bytes, add enough nops here to
7394 make it at least 12 bytes away. In any case close it off with a
7397 static offsetT min_bytes_to_other_loop_end
7398 (fragS
*, fragS
*, offsetT
, offsetT
);
7401 xtensa_fix_close_loop_end_frags (void)
7405 /* When this routine is called, all of the subsections are still intact
7406 so we walk over subsections instead of sections. */
7407 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7411 fragS
*current_target
= NULL
;
7412 offsetT current_offset
= 0;
7414 /* Walk over all of the fragments in a subsection. */
7415 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7417 if (fragP
->fr_type
== rs_machine_dependent
7418 && ((fragP
->fr_subtype
== RELAX_IMMED
)
7419 || ((fragP
->fr_subtype
== RELAX_SLOTS
)
7420 && (fragP
->tc_frag_data
.slot_subtypes
[0]
7423 /* Read it. If the instruction is a loop, get the target. */
7425 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7426 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7427 t_insn
.opcode
) == 1)
7429 /* Get the current fragment target. */
7430 if (fragP
->tc_frag_data
.slot_symbols
[0])
7432 symbolS
*sym
= fragP
->tc_frag_data
.slot_symbols
[0];
7433 current_target
= symbol_get_frag (sym
);
7434 current_offset
= fragP
->fr_offset
;
7440 && fragP
->fr_type
== rs_machine_dependent
7441 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
7444 int bytes_added
= 0;
7446 #define REQUIRED_LOOP_DIVIDING_BYTES 12
7447 /* Max out at 12. */
7448 min_bytes
= min_bytes_to_other_loop_end
7449 (fragP
->fr_next
, current_target
, current_offset
,
7450 REQUIRED_LOOP_DIVIDING_BYTES
);
7452 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
7454 if (fragP
->tc_frag_data
.is_no_transform
)
7455 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
7458 while (min_bytes
+ bytes_added
7459 < REQUIRED_LOOP_DIVIDING_BYTES
)
7463 if (fragP
->fr_var
< length
)
7464 as_fatal (_("fr_var %lu < length %d"),
7465 (long) fragP
->fr_var
, length
);
7468 assemble_nop (length
,
7469 fragP
->fr_literal
+ fragP
->fr_fix
);
7470 fragP
->fr_fix
+= length
;
7471 fragP
->fr_var
-= length
;
7473 bytes_added
+= length
;
7479 assert (fragP
->fr_type
!= rs_machine_dependent
7480 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
7486 static offsetT
unrelaxed_frag_min_size (fragS
*);
7489 min_bytes_to_other_loop_end (fragS
*fragP
,
7490 fragS
*current_target
,
7491 offsetT current_offset
,
7495 fragS
*current_fragP
;
7497 for (current_fragP
= fragP
;
7499 current_fragP
= current_fragP
->fr_next
)
7501 if (current_fragP
->tc_frag_data
.is_loop_target
7502 && current_fragP
!= current_target
)
7503 return offset
+ current_offset
;
7505 offset
+= unrelaxed_frag_min_size (current_fragP
);
7507 if (offset
+ current_offset
>= max_size
)
7515 unrelaxed_frag_min_size (fragS
*fragP
)
7517 offsetT size
= fragP
->fr_fix
;
7519 /* Add fill size. */
7520 if (fragP
->fr_type
== rs_fill
)
7521 size
+= fragP
->fr_offset
;
7528 unrelaxed_frag_max_size (fragS
*fragP
)
7530 offsetT size
= fragP
->fr_fix
;
7531 switch (fragP
->fr_type
)
7534 /* Empty frags created by the obstack allocation scheme
7535 end up with type 0. */
7540 size
+= fragP
->fr_offset
;
7548 /* No further adjustments needed. */
7550 case rs_machine_dependent
:
7551 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
7552 size
+= fragP
->fr_var
;
7555 /* We had darn well better know how big it is. */
7564 /* Re-process all of the fragments looking to convert all
7565 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
7568 1) the instruction size count to the loop end label
7569 is too short (<= 2 instructions),
7570 2) loop has a jump or branch in it
7573 1) workaround_all_short_loops is TRUE
7574 2) The generating loop was a 'loopgtz' or 'loopnez'
7575 3) the instruction size count to the loop end label is too short
7577 then convert this frag (and maybe the next one) to generate a NOP.
7578 In any case close it off with a .fill 0. */
7580 static int count_insns_to_loop_end (fragS
*, bfd_boolean
, int);
7581 static bfd_boolean
branch_before_loop_end (fragS
*);
7584 xtensa_fix_short_loop_frags (void)
7588 /* When this routine is called, all of the subsections are still intact
7589 so we walk over subsections instead of sections. */
7590 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7593 fragS
*current_target
= NULL
;
7594 offsetT current_offset
= 0;
7595 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
7597 /* Walk over all of the fragments in a subsection. */
7598 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7600 /* Check on the current loop. */
7601 if (fragP
->fr_type
== rs_machine_dependent
7602 && ((fragP
->fr_subtype
== RELAX_IMMED
)
7603 || ((fragP
->fr_subtype
== RELAX_SLOTS
)
7604 && (fragP
->tc_frag_data
.slot_subtypes
[0]
7609 /* Read it. If the instruction is a loop, get the target. */
7610 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7611 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7612 t_insn
.opcode
) == 1)
7614 /* Get the current fragment target. */
7615 if (fragP
->tc_frag_data
.slot_symbols
[0])
7617 symbolS
*sym
= fragP
->tc_frag_data
.slot_symbols
[0];
7618 current_target
= symbol_get_frag (sym
);
7619 current_offset
= fragP
->fr_offset
;
7620 current_opcode
= t_insn
.opcode
;
7625 if (fragP
->fr_type
== rs_machine_dependent
7626 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7628 if (count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3) < 3
7629 && (branch_before_loop_end (fragP
->fr_next
)
7630 || (workaround_all_short_loops
7631 && current_opcode
!= XTENSA_UNDEFINED
7632 && current_opcode
!= xtensa_loop_opcode
)))
7634 if (fragP
->tc_frag_data
.is_no_transform
)
7635 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
7637 relax_frag_add_nop (fragP
);
7646 static int unrelaxed_frag_min_insn_count (fragS
*);
7649 count_insns_to_loop_end (fragS
*base_fragP
,
7650 bfd_boolean count_relax_add
,
7653 fragS
*fragP
= NULL
;
7658 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
7660 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
7661 if (insn_count
>= max_count
)
7664 if (count_relax_add
)
7666 if (fragP
->fr_type
== rs_machine_dependent
7667 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7669 /* In order to add the appropriate number of
7670 NOPs, we count an instruction for downstream
7673 if (insn_count
>= max_count
)
7683 unrelaxed_frag_min_insn_count (fragS
*fragP
)
7685 xtensa_isa isa
= xtensa_default_isa
;
7686 static xtensa_insnbuf insnbuf
= NULL
;
7690 if (!fragP
->tc_frag_data
.is_insn
)
7694 insnbuf
= xtensa_insnbuf_alloc (isa
);
7696 /* Decode the fixed instructions. */
7697 while (offset
< fragP
->fr_fix
)
7701 xtensa_insnbuf_from_chars
7702 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7703 fmt
= xtensa_format_decode (isa
, insnbuf
);
7705 if (fmt
== XTENSA_UNDEFINED
)
7707 as_fatal (_("undecodable instruction in instruction frag"));
7710 offset
+= xtensa_format_length (isa
, fmt
);
7718 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
7721 branch_before_loop_end (fragS
*base_fragP
)
7725 for (fragP
= base_fragP
;
7726 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
7727 fragP
= fragP
->fr_next
)
7729 if (unrelaxed_frag_has_b_j (fragP
))
7737 unrelaxed_frag_has_b_j (fragS
*fragP
)
7739 static xtensa_insnbuf insnbuf
= NULL
;
7740 xtensa_isa isa
= xtensa_default_isa
;
7743 if (!fragP
->tc_frag_data
.is_insn
)
7747 insnbuf
= xtensa_insnbuf_alloc (isa
);
7749 /* Decode the fixed instructions. */
7750 while (offset
< fragP
->fr_fix
)
7755 xtensa_insnbuf_from_chars
7756 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7757 fmt
= xtensa_format_decode (isa
, insnbuf
);
7758 if (fmt
== XTENSA_UNDEFINED
)
7761 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7763 xtensa_opcode opcode
=
7764 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
7765 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
7766 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
7769 offset
+= xtensa_format_length (isa
, fmt
);
7775 /* Checks to be made after initial assembly but before relaxation. */
7777 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
7778 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
7781 xtensa_sanity_check (void)
7788 as_where (&file_name
, &line
);
7789 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7793 /* Walk over all of the fragments in a subsection. */
7794 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7796 /* Currently we only check for empty loops here. */
7797 if (fragP
->fr_type
== rs_machine_dependent
7798 && fragP
->fr_subtype
== RELAX_IMMED
)
7800 static xtensa_insnbuf insnbuf
= NULL
;
7803 if (fragP
->fr_opcode
!= NULL
)
7806 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7807 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7808 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
7810 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7811 t_insn
.opcode
) == 1)
7813 if (is_empty_loop (&t_insn
, fragP
))
7815 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7816 as_bad (_("invalid empty loop"));
7818 if (!is_local_forward_loop (&t_insn
, fragP
))
7820 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7821 as_bad (_("loop target does not follow "
7822 "loop instruction in section"));
7829 new_logical_line (file_name
, line
);
7833 #define LOOP_IMMED_OPN 1
7835 /* Return TRUE if the loop target is the next non-zero fragment. */
7838 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
7840 const expressionS
*expr
;
7844 if (insn
->insn_type
!= ITYPE_INSN
)
7847 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
7850 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7853 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7855 if (expr
->X_op
!= O_symbol
)
7858 symbolP
= expr
->X_add_symbol
;
7862 if (symbol_get_frag (symbolP
) == NULL
)
7865 if (S_GET_VALUE (symbolP
) != 0)
7868 /* Walk through the zero-size fragments from this one. If we find
7869 the target fragment, then this is a zero-size loop. */
7871 for (next_fragP
= fragP
->fr_next
;
7873 next_fragP
= next_fragP
->fr_next
)
7875 if (next_fragP
== symbol_get_frag (symbolP
))
7877 if (next_fragP
->fr_fix
!= 0)
7885 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
7887 const expressionS
*expr
;
7891 if (insn
->insn_type
!= ITYPE_INSN
)
7894 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) == 0)
7897 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7900 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7902 if (expr
->X_op
!= O_symbol
)
7905 symbolP
= expr
->X_add_symbol
;
7909 if (symbol_get_frag (symbolP
) == NULL
)
7912 /* Walk through fragments until we find the target.
7913 If we do not find the target, then this is an invalid loop. */
7915 for (next_fragP
= fragP
->fr_next
;
7917 next_fragP
= next_fragP
->fr_next
)
7919 if (next_fragP
== symbol_get_frag (symbolP
))
7927 /* Alignment Functions. */
7930 get_text_align_power (unsigned target_size
)
7935 assert (target_size
<= INT_MAX
);
7936 while (target_size
> power
)
7946 get_text_align_max_fill_size (int align_pow
,
7947 bfd_boolean use_nops
,
7948 bfd_boolean use_no_density
)
7951 return (1 << align_pow
);
7953 return 3 * (1 << align_pow
);
7955 return 1 + (1 << align_pow
);
7959 /* Calculate the minimum bytes of fill needed at "address" to align a
7960 target instruction of size "target_size" so that it does not cross a
7961 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE,
7962 the fill can be an arbitrary number of bytes. Otherwise, the space must
7963 be filled by NOP instructions. */
7966 get_text_align_fill_size (addressT address
,
7969 bfd_boolean use_nops
,
7970 bfd_boolean use_no_density
)
7972 addressT alignment
, fill
, fill_limit
, fill_step
;
7973 bfd_boolean skip_one
= FALSE
;
7975 alignment
= (1 << align_pow
);
7976 assert (target_size
> 0 && alignment
>= (addressT
) target_size
);
7980 fill_limit
= alignment
;
7983 else if (!use_no_density
)
7985 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */
7986 fill_limit
= alignment
* 2;
7992 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */
7993 fill_limit
= alignment
* 3;
7997 /* Try all fill sizes until finding one that works. */
7998 for (fill
= 0; fill
< fill_limit
; fill
+= fill_step
)
8000 if (skip_one
&& fill
== 1)
8002 if ((address
+ fill
) >> align_pow
8003 == (address
+ fill
+ target_size
- 1) >> align_pow
)
8012 branch_align_power (segT sec
)
8014 /* If the Xtensa processor has a fetch width of 8 bytes, and the section
8015 is aligned to at least an 8-byte boundary, then a branch target need
8016 only fit within an 8-byte aligned block of memory to avoid a stall.
8017 Otherwise, try to fit branch targets within 4-byte aligned blocks
8018 (which may be insufficient, e.g., if the section has no alignment, but
8019 it's good enough). */
8020 if (xtensa_fetch_width
== 8)
8022 if (get_recorded_alignment (sec
) >= 3)
8026 assert (xtensa_fetch_width
== 4);
8032 /* This will assert if it is not possible. */
8035 get_text_align_nop_count (offsetT fill_size
, bfd_boolean use_no_density
)
8041 assert (fill_size
% 3 == 0);
8042 return (fill_size
/ 3);
8045 assert (fill_size
!= 1); /* Bad argument. */
8047 while (fill_size
> 1)
8050 if (fill_size
== 2 || fill_size
== 4)
8052 fill_size
-= insn_size
;
8055 assert (fill_size
!= 1); /* Bad algorithm. */
8061 get_text_align_nth_nop_size (offsetT fill_size
,
8063 bfd_boolean use_no_density
)
8070 assert (fill_size
!= 1); /* Bad argument. */
8072 while (fill_size
> 1)
8075 if (fill_size
== 2 || fill_size
== 4)
8077 fill_size
-= insn_size
;
8087 /* For the given fragment, find the appropriate address
8088 for it to begin at if we are using NOPs to align it. */
8091 get_noop_aligned_address (fragS
*fragP
, addressT address
)
8093 /* The rule is: get next fragment's FIRST instruction. Find
8094 the smallest number of bytes that need to be added to
8095 ensure that the next fragment's FIRST instruction will fit
8098 E.G., 2 bytes : 0, 1, 2 mod 4
8101 If the FIRST instruction MIGHT be relaxed,
8102 assume that it will become a 3-byte instruction.
8104 Note again here that LOOP instructions are not bundleable,
8105 and this relaxation only applies to LOOP opcodes. */
8108 int first_insn_size
;
8110 addressT pre_opcode_bytes
;
8113 xtensa_opcode opcode
;
8114 bfd_boolean is_loop
;
8116 assert (fragP
->fr_type
== rs_machine_dependent
);
8117 assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
8119 /* Find the loop frag. */
8120 first_insn
= next_non_empty_frag (fragP
);
8121 /* Now find the first insn frag. */
8122 first_insn
= next_non_empty_frag (first_insn
);
8124 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
8126 loop_insn_size
= xg_get_single_size (opcode
);
8128 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
8129 pre_opcode_bytes
+= loop_insn_size
;
8131 /* For loops, the alignment depends on the size of the
8132 instruction following the loop, not the LOOP instruction. */
8134 if (first_insn
== NULL
)
8137 assert (first_insn
->tc_frag_data
.is_first_loop_insn
);
8139 first_insn_size
= frag_format_size (first_insn
);
8141 if (first_insn_size
== 2 || first_insn_size
== XTENSA_UNDEFINED
)
8142 first_insn_size
= 3; /* ISA specifies this */
8144 /* If it was 8, then we'll need a larger alignment for the section. */
8145 align_power
= get_text_align_power (first_insn_size
);
8146 record_alignment (now_seg
, align_power
);
8148 fill_size
= get_text_align_fill_size
8149 (address
+ pre_opcode_bytes
, align_power
, first_insn_size
, TRUE
,
8150 fragP
->tc_frag_data
.is_no_density
);
8152 return address
+ fill_size
;
8156 /* 3 mechanisms for relaxing an alignment:
8158 Align to a power of 2.
8159 Align so the next fragment's instruction does not cross a word boundary.
8160 Align the current instruction so that if the next instruction
8161 were 3 bytes, it would not cross a word boundary.
8165 zeros - This is easy; always insert zeros.
8166 nops - 3-byte and 2-byte instructions
8170 >=5 : 3-byte instruction + fn (n-3)
8171 widening - widen previous instructions. */
8174 get_aligned_diff (fragS
*fragP
, addressT address
, offsetT
*max_diff
)
8176 addressT target_address
, loop_insn_offset
;
8178 xtensa_opcode loop_opcode
;
8179 bfd_boolean is_loop
;
8182 addressT branch_align
;
8184 assert (fragP
->fr_type
== rs_machine_dependent
);
8185 switch (fragP
->fr_subtype
)
8187 case RELAX_DESIRE_ALIGN
:
8188 target_size
= next_frag_format_size (fragP
);
8189 if (target_size
== XTENSA_UNDEFINED
)
8191 align_power
= branch_align_power (now_seg
);
8192 branch_align
= 1 << align_power
;
8193 opt_diff
= get_text_align_fill_size (address
, align_power
,
8194 target_size
, FALSE
, FALSE
);
8196 *max_diff
= (opt_diff
+ branch_align
8197 - (target_size
+ ((address
+ opt_diff
) % branch_align
)));
8198 assert (*max_diff
>= opt_diff
);
8201 case RELAX_ALIGN_NEXT_OPCODE
:
8202 target_size
= next_frag_format_size (fragP
);
8203 loop_insn_offset
= 0;
8204 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
8207 /* If the loop has been expanded then the LOOP instruction
8208 could be at an offset from this fragment. */
8209 if (next_non_empty_frag(fragP
)->tc_frag_data
.slot_subtypes
[0]
8211 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
8213 if (target_size
== 2)
8214 target_size
= 3; /* ISA specifies this */
8216 /* In an ideal world, which is what we are shooting for here,
8217 we wouldn't need to use any NOPs immediately prior to the
8218 LOOP instruction. If this approach fails, relax_frag_loop_align
8219 will call get_noop_aligned_address. */
8221 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
8222 align_power
= get_text_align_power (target_size
),
8223 opt_diff
= get_text_align_fill_size (target_address
, align_power
,
8224 target_size
, FALSE
, FALSE
);
8226 *max_diff
= xtensa_fetch_width
8227 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
8228 - target_size
+ opt_diff
;
8229 assert (*max_diff
>= opt_diff
);
8240 /* md_relax_frag Hook and Helper Functions. */
8242 static long relax_frag_loop_align (fragS
*, long);
8243 static long relax_frag_for_align (fragS
*, long);
8244 static long relax_frag_immed
8245 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
8248 /* Return the number of bytes added to this fragment, given that the
8249 input has been stretched already by "stretch". */
8252 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
8254 xtensa_isa isa
= xtensa_default_isa
;
8255 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
8256 long new_stretch
= 0;
8260 static xtensa_insnbuf vbuf
= NULL
;
8261 int slot
, num_slots
;
8264 as_where (&file_name
, &line
);
8265 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8267 fragP
->tc_frag_data
.unreported_expansion
= 0;
8269 switch (fragP
->fr_subtype
)
8271 case RELAX_ALIGN_NEXT_OPCODE
:
8272 /* Always convert. */
8273 if (fragP
->tc_frag_data
.relax_seen
)
8274 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
8277 case RELAX_LOOP_END
:
8281 case RELAX_LOOP_END_ADD_NOP
:
8282 /* Add a NOP and switch to .fill 0. */
8283 new_stretch
= relax_frag_add_nop (fragP
);
8287 case RELAX_DESIRE_ALIGN
:
8288 /* Do nothing. The narrowing before this frag will either align
8293 case RELAX_LITERAL_FINAL
:
8296 case RELAX_LITERAL_NR
:
8298 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
8299 assert (unreported
== lit_size
);
8300 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
8301 fragP
->fr_var
-= lit_size
;
8302 fragP
->fr_fix
+= lit_size
;
8308 vbuf
= xtensa_insnbuf_alloc (isa
);
8310 xtensa_insnbuf_from_chars
8311 (isa
, vbuf
, (unsigned char *) fragP
->fr_opcode
, 0);
8312 fmt
= xtensa_format_decode (isa
, vbuf
);
8313 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8315 for (slot
= 0; slot
< num_slots
; slot
++)
8317 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
8320 if (fragP
->tc_frag_data
.relax_seen
)
8321 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8325 case RELAX_IMMED_STEP1
:
8326 case RELAX_IMMED_STEP2
:
8327 /* Place the immediate. */
8328 new_stretch
+= relax_frag_immed
8329 (now_seg
, fragP
, stretch
,
8330 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8331 fmt
, slot
, stretched_p
, FALSE
);
8335 /* This is OK; see the note in xg_assemble_vliw_tokens. */
8341 case RELAX_LITERAL_POOL_BEGIN
:
8342 case RELAX_LITERAL_POOL_END
:
8343 case RELAX_MAYBE_UNREACHABLE
:
8344 case RELAX_MAYBE_DESIRE_ALIGN
:
8345 /* No relaxation required. */
8348 case RELAX_FILL_NOP
:
8349 case RELAX_UNREACHABLE
:
8350 if (fragP
->tc_frag_data
.relax_seen
)
8351 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8355 as_bad (_("bad relaxation state"));
8358 /* Tell gas we need another relaxation pass. */
8359 if (! fragP
->tc_frag_data
.relax_seen
)
8361 fragP
->tc_frag_data
.relax_seen
= TRUE
;
8365 new_logical_line (file_name
, line
);
8371 relax_frag_loop_align (fragS
*fragP
, long stretch
)
8373 addressT old_address
, old_next_address
, old_size
;
8374 addressT new_address
, new_next_address
, new_size
;
8377 /* All the frags with relax_frag_for_alignment prior to this one in the
8378 section have been done, hopefully eliminating the need for a NOP here.
8379 But, this will put it in if necessary. */
8381 /* Calculate the old address of this fragment and the next fragment. */
8382 old_address
= fragP
->fr_address
- stretch
;
8383 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
8384 fragP
->tc_frag_data
.text_expansion
[0]);
8385 old_size
= old_next_address
- old_address
;
8387 /* Calculate the new address of this fragment and the next fragment. */
8388 new_address
= fragP
->fr_address
;
8390 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
8391 new_size
= new_next_address
- new_address
;
8393 growth
= new_size
- old_size
;
8395 /* Fix up the text_expansion field and return the new growth. */
8396 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
8401 /* Add a NOP instruction. */
8404 relax_frag_add_nop (fragS
*fragP
)
8406 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
8407 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
8408 assemble_nop (length
, nop_buf
);
8409 fragP
->tc_frag_data
.is_insn
= TRUE
;
8411 if (fragP
->fr_var
< length
)
8413 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP
->fr_var
, length
);
8417 fragP
->fr_fix
+= length
;
8418 fragP
->fr_var
-= length
;
8423 static long future_alignment_required (fragS
*, long);
8426 relax_frag_for_align (fragS
*fragP
, long stretch
)
8428 /* Overview of the relaxation procedure for alignment:
8429 We can widen with NOPs or by widening instructions or by filling
8430 bytes after jump instructions. Find the opportune places and widen
8431 them if necessary. */
8436 assert (fragP
->fr_subtype
== RELAX_FILL_NOP
8437 || fragP
->fr_subtype
== RELAX_UNREACHABLE
8438 || (fragP
->fr_subtype
== RELAX_SLOTS
8439 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
8441 stretch_me
= future_alignment_required (fragP
, stretch
);
8442 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
8448 /* We expanded on a previous pass. Can we shrink now? */
8449 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
8450 if (shrink
<= stretch
&& stretch
> 0)
8452 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8458 /* Below here, diff > 0. */
8459 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8465 /* Return the address of the next frag that should be aligned.
8467 By "address" we mean the address it _would_ be at if there
8468 is no action taken to align it between here and the target frag.
8469 In other words, if no narrows and no fill nops are used between
8470 here and the frag to align, _even_if_ some of the frags we use
8471 to align targets have already expanded on a previous relaxation
8474 Also, count each frag that may be used to help align the target.
8476 Return 0 if there are no frags left in the chain that need to be
8480 find_address_of_next_align_frag (fragS
**fragPP
,
8484 bfd_boolean
*paddable
)
8486 fragS
*fragP
= *fragPP
;
8487 addressT address
= fragP
->fr_address
;
8489 /* Do not reset the counts to 0. */
8493 /* Limit this to a small search. */
8499 address
+= fragP
->fr_fix
;
8501 if (fragP
->fr_type
== rs_fill
)
8502 address
+= fragP
->fr_offset
* fragP
->fr_var
;
8503 else if (fragP
->fr_type
== rs_machine_dependent
)
8505 switch (fragP
->fr_subtype
)
8507 case RELAX_UNREACHABLE
:
8511 case RELAX_FILL_NOP
:
8513 if (!fragP
->tc_frag_data
.is_no_density
)
8518 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8523 address
+= total_frag_text_expansion (fragP
);;
8527 address
+= fragP
->tc_frag_data
.text_expansion
[0];
8530 case RELAX_ALIGN_NEXT_OPCODE
:
8531 case RELAX_DESIRE_ALIGN
:
8535 case RELAX_MAYBE_UNREACHABLE
:
8536 case RELAX_MAYBE_DESIRE_ALIGN
:
8541 /* Just punt if we don't know the type. */
8548 /* Just punt if we don't know the type. */
8552 fragP
= fragP
->fr_next
;
8560 static long bytes_to_stretch (fragS
*, int, int, int, int);
8562 /* Undefine LOOKAHEAD_ALIGNER to get the older behavior.
8563 I'll leave this in until I am more confident this works. */
8565 #define LOOKAHEAD_ALIGNER 1
8568 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
8570 fragS
*this_frag
= fragP
;
8574 int narrow_nops
= 0;
8575 bfd_boolean paddable
= FALSE
;
8576 offsetT local_opt_diff
;
8579 int stretch_amount
= 0;
8580 int local_stretch_amount
;
8581 int global_stretch_amount
;
8583 address
= find_address_of_next_align_frag
8584 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
8588 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
8589 opt_diff
= local_opt_diff
;
8590 assert (opt_diff
>= 0);
8591 assert (max_diff
>= opt_diff
);
8594 #ifdef LOOKAHEAD_ALIGNER
8596 fragP
= fragP
->fr_next
;
8598 while (fragP
&& opt_diff
< max_diff
&& address
)
8600 /* We only use these to determine if we can exit early
8601 because there will be plenty of ways to align future
8603 int glob_widens
= 0;
8606 bfd_boolean glob_pad
= 0;
8607 address
= find_address_of_next_align_frag
8608 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
8609 /* If there is a padable portion, then skip. */
8610 if (glob_pad
|| glob_widens
>= (1 << branch_align_power (now_seg
)))
8615 offsetT next_m_diff
;
8616 offsetT next_o_diff
;
8618 /* Downrange frags haven't had stretch added to them yet. */
8621 /* The address also includes any text expansion from this
8622 frag in a previous pass, but we don't want that. */
8623 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
8625 /* Assume we are going to move at least opt_diff. In
8626 reality, we might not be able to, but assuming that
8627 we will helps catch cases where moving opt_diff pushes
8628 the next target from aligned to unaligned. */
8629 address
+= opt_diff
;
8631 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
8633 /* Now cleanup for the adjustments to address. */
8634 next_o_diff
+= opt_diff
;
8635 next_m_diff
+= opt_diff
;
8636 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
8637 opt_diff
= next_o_diff
;
8638 if (next_m_diff
< max_diff
)
8639 max_diff
= next_m_diff
;
8640 fragP
= fragP
->fr_next
;
8643 #endif /* LOOKAHEAD_ALIGNER */
8644 /* If there are enough wideners in between, do it. */
8647 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
8649 assert (opt_diff
<= UNREACHABLE_MAX_WIDTH
);
8654 local_stretch_amount
8655 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8656 num_widens
, local_opt_diff
);
8657 #ifdef LOOKAHEAD_ALIGNER
8658 global_stretch_amount
8659 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8660 num_widens
, opt_diff
);
8661 /* If the condition below is true, then the frag couldn't
8662 stretch the correct amount for the global case, so we just
8663 optimize locally. We'll rely on the subsequent frags to get
8664 the correct alignment in the global case. */
8665 if (global_stretch_amount
< local_stretch_amount
)
8666 stretch_amount
= local_stretch_amount
;
8668 stretch_amount
= global_stretch_amount
;
8669 #else /* ! LOOKAHEAD_ALIGNER */
8670 stretch_amount
= local_stretch_amount
;
8671 #endif /* ! LOOKAHEAD_ALIGNER */
8672 if (this_frag
->fr_subtype
== RELAX_SLOTS
8673 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8674 assert (stretch_amount
<= 1);
8675 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8677 if (this_frag
->tc_frag_data
.is_no_density
)
8678 assert (stretch_amount
== 3 || stretch_amount
== 0);
8680 assert (stretch_amount
<= 3);
8683 return stretch_amount
;
8687 /* The idea: widen everything you can to get a target or loop aligned,
8688 then start using NOPs.
8690 When we must have a NOP, here is a table of how we decide
8691 (so you don't have to fight through the control flow below):
8693 wide_nops = the number of wide NOPs available for aligning
8694 narrow_nops = the number of narrow NOPs available for aligning
8695 (a subset of wide_nops)
8696 widens = the number of narrow instructions that should be widened
8703 b 0 1 1 (case 3a makes this case unnecessary)
8706 c 0 1 2 (case 4a makes this case unnecessary)
8709 c 0 2 1 (case 5b makes this case unnecessary)
8712 c 0 1 4 (case 6b makes this case unneccesary)
8713 d 1 1 1 (case 6a makes this case unnecessary)
8714 e 0 2 2 (case 6a makes this case unnecessary)
8715 f 0 3 0 (case 6a makes this case unnecessary)
8718 c 1 1 2 (case 7b makes this case unnecessary)
8719 d 0 1 5 (case 7a makes this case unnecessary)
8720 e 0 2 3 (case 7b makes this case unnecessary)
8721 f 0 3 1 (case 7b makes this case unnecessary)
8722 g 1 2 1 (case 7b makes this case unnecessary)
8726 bytes_to_stretch (fragS
*this_frag
,
8732 int bytes_short
= desired_diff
- num_widens
;
8734 assert (desired_diff
>= 0 && desired_diff
< 8);
8735 if (desired_diff
== 0)
8738 assert (wide_nops
> 0 || num_widens
> 0);
8740 /* Always prefer widening to NOP-filling. */
8741 if (bytes_short
< 0)
8743 /* There are enough RELAX_NARROW frags after this one
8744 to align the target without widening this frag in any way. */
8748 if (bytes_short
== 0)
8750 /* Widen every narrow between here and the align target
8751 and the align target will be properly aligned. */
8752 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8758 /* From here we will need at least one NOP to get an alignment.
8759 However, we may not be able to align at all, in which case,
8761 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8763 switch (desired_diff
)
8768 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 1)
8769 return 2; /* case 2 */
8775 return 3; /* case 3a */
8777 if (num_widens
>= 1 && wide_nops
== 1)
8778 return 3; /* case 4a */
8779 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 2)
8780 return 2; /* case 4b */
8783 if (num_widens
>= 2 && wide_nops
== 1)
8784 return 3; /* case 5a */
8785 /* We will need two nops. Are there enough nops
8786 between here and the align target? */
8787 if (wide_nops
< 2 || narrow_nops
== 0)
8789 /* Are there other nops closer that can serve instead? */
8790 if (wide_nops
> 2 && narrow_nops
> 1)
8792 /* Take the density one first, because there might not be
8793 another density one available. */
8794 if (!this_frag
->tc_frag_data
.is_no_density
)
8795 return 2; /* case 5b narrow */
8797 return 3; /* case 5b wide */
8801 return 3; /* case 6a */
8802 else if (num_widens
>= 3 && wide_nops
== 1)
8803 return 3; /* case 6b */
8806 if (wide_nops
== 1 && num_widens
>= 4)
8807 return 3; /* case 7a */
8808 else if (wide_nops
== 2 && num_widens
>= 1)
8809 return 3; /* case 7b */
8817 /* We will need a NOP no matter what, but should we widen
8818 this instruction to help?
8820 This is a RELAX_FRAG_NARROW frag. */
8821 switch (desired_diff
)
8830 if (wide_nops
>= 1 && num_widens
== 1)
8831 return 1; /* case 4a */
8834 if (wide_nops
>= 1 && num_widens
== 2)
8835 return 1; /* case 5a */
8839 return 0; /* case 6a */
8840 else if (wide_nops
>= 1 && num_widens
== 3)
8841 return 1; /* case 6b */
8844 if (wide_nops
>= 1 && num_widens
== 4)
8845 return 1; /* case 7a */
8846 else if (wide_nops
>= 2 && num_widens
== 1)
8847 return 1; /* case 7b */
8860 relax_frag_immed (segT segP
,
8867 bfd_boolean estimate_only
)
8870 vliw_insn orig_vinsn
;
8872 bfd_boolean negatable_branch
= FALSE
;
8873 bfd_boolean branch_jmp_to_next
= FALSE
;
8874 bfd_boolean wide_insn
= FALSE
;
8875 xtensa_isa isa
= xtensa_default_isa
;
8877 offsetT frag_offset
;
8880 int num_text_bytes
, num_literal_bytes
;
8881 int literal_diff
, total_text_diff
, this_text_diff
, first
;
8883 assert (fragP
->fr_opcode
!= NULL
);
8885 xg_init_vinsn (&orig_vinsn
);
8886 vinsn_from_chars (&orig_vinsn
, fragP
->fr_opcode
);
8887 if (xtensa_format_num_slots (isa
, fmt
) > 1)
8890 tinsn
= orig_vinsn
.slots
[slot
];
8891 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
8893 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
))
8896 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
8897 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
8899 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
8901 old_size
= xtensa_format_length (isa
, fmt
);
8903 /* Special case: replace a branch to the next instruction with a NOP.
8904 This is required to work around a hardware bug in T1040.0 and also
8905 serves as an optimization. */
8907 if (branch_jmp_to_next
8908 && ((old_size
== 2) || (old_size
== 3))
8909 && !next_frag_is_loop_target (fragP
))
8912 /* Here is the fun stuff: Get the immediate field from this
8913 instruction. If it fits, we are done. If not, find the next
8914 instruction sequence that fits. */
8916 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
8917 istack_init (&istack
);
8918 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
8919 min_steps
, stretch
);
8920 if (num_steps
< min_steps
)
8922 as_fatal (_("internal error: relaxation failed"));
8926 if (num_steps
> RELAX_IMMED_MAXSTEPS
)
8928 as_fatal (_("internal error: relaxation requires too many steps"));
8932 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
8934 /* Figure out the number of bytes needed. */
8936 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
8938 num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
8940 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
8942 num_text_bytes
= get_num_stack_text_bytes (&istack
);
8945 num_text_bytes
+= old_size
;
8946 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
8947 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
8949 total_text_diff
= num_text_bytes
- old_size
;
8950 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
8952 /* It MUST get larger. If not, we could get an infinite loop. */
8953 assert (num_text_bytes
>= 0);
8954 assert (literal_diff
>= 0);
8955 assert (total_text_diff
>= 0);
8957 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
8958 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
8959 assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
8960 assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
8962 /* Find the associated expandable literal for this. */
8963 if (literal_diff
!= 0)
8965 lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
8968 assert (literal_diff
== 4);
8969 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
8971 /* We expect that the literal section state has NOT been
8973 assert (lit_fragP
->fr_type
== rs_machine_dependent
8974 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
8975 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
8977 /* We need to mark this section for another iteration
8983 if (negatable_branch
&& istack
.ninsn
> 1)
8984 update_next_frag_state (fragP
);
8986 return this_text_diff
;
8990 /* md_convert_frag Hook and Helper Functions. */
8992 static void convert_frag_align_next_opcode (fragS
*);
8993 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
8994 static void convert_frag_fill_nop (fragS
*);
8995 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
8998 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
9000 static xtensa_insnbuf vbuf
= NULL
;
9001 xtensa_isa isa
= xtensa_default_isa
;
9008 as_where (&file_name
, &line
);
9009 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
9011 switch (fragp
->fr_subtype
)
9013 case RELAX_ALIGN_NEXT_OPCODE
:
9014 /* Always convert. */
9015 convert_frag_align_next_opcode (fragp
);
9018 case RELAX_DESIRE_ALIGN
:
9019 /* Do nothing. If not aligned already, too bad. */
9023 case RELAX_LITERAL_FINAL
:
9028 vbuf
= xtensa_insnbuf_alloc (isa
);
9030 xtensa_insnbuf_from_chars
9031 (isa
, vbuf
, (unsigned char *) fragp
->fr_opcode
, 0);
9032 fmt
= xtensa_format_decode (isa
, vbuf
);
9033 num_slots
= xtensa_format_num_slots (isa
, fmt
);
9035 for (slot
= 0; slot
< num_slots
; slot
++)
9037 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
9040 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
9044 case RELAX_IMMED_STEP1
:
9045 case RELAX_IMMED_STEP2
:
9046 /* Place the immediate. */
9049 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
9054 /* This is OK because some slots could have
9055 relaxations and others have none. */
9061 case RELAX_UNREACHABLE
:
9062 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
9063 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
9064 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
9068 case RELAX_MAYBE_UNREACHABLE
:
9069 case RELAX_MAYBE_DESIRE_ALIGN
:
9073 case RELAX_FILL_NOP
:
9074 convert_frag_fill_nop (fragp
);
9077 case RELAX_LITERAL_NR
:
9078 if (use_literal_section
)
9080 /* This should have been handled during relaxation. When
9081 relaxing a code segment, literals sometimes need to be
9082 added to the corresponding literal segment. If that
9083 literal segment has already been relaxed, then we end up
9084 in this situation. Marking the literal segments as data
9085 would make this happen less often (since GAS always relaxes
9086 code before data), but we could still get into trouble if
9087 there are instructions in a segment that is not marked as
9088 containing code. Until we can implement a better solution,
9089 cheat and adjust the addresses of all the following frags.
9090 This could break subsequent alignments, but the linker's
9091 literal coalescing will do that anyway. */
9094 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
9095 assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
9096 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
9099 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
9103 as_bad (_("invalid relaxation fragment result"));
9108 new_logical_line (file_name
, line
);
9113 convert_frag_align_next_opcode (fragS
*fragp
)
9115 char *nop_buf
; /* Location for Writing. */
9116 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
9117 addressT aligned_address
;
9121 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
9123 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
9124 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
9125 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
9127 for (nop
= 0; nop
< nop_count
; nop
++)
9130 nop_size
= get_text_align_nth_nop_size (fill_size
, nop
, use_no_density
);
9132 assemble_nop (nop_size
, nop_buf
);
9133 nop_buf
+= nop_size
;
9136 fragp
->fr_fix
+= fill_size
;
9137 fragp
->fr_var
-= fill_size
;
9142 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
9144 TInsn tinsn
, single_target
;
9145 xtensa_format single_fmt
;
9146 int size
, old_size
, diff
, error_val
;
9147 offsetT frag_offset
;
9150 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
9152 if (xtensa_opcode_is_branch (xtensa_default_isa
, tinsn
.opcode
) == 1)
9154 assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
9155 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
9156 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
9161 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
9163 /* No conversion. */
9168 assert (fragP
->fr_opcode
!= NULL
);
9170 /* Frags in this relaxation state should only contain
9171 single instruction bundles. */
9172 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
9174 /* Just convert it to a wide form.... */
9176 old_size
= xg_get_single_size (tinsn
.opcode
);
9178 tinsn_init (&single_target
);
9179 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9181 error_val
= xg_expand_narrow (&single_target
, &tinsn
);
9184 as_bad (_("unable to widen instruction"));
9188 size
= xg_get_single_size (single_target
.opcode
);
9189 single_fmt
= xg_get_single_format (single_target
.opcode
);
9191 xg_emit_insn_to_buf (&single_target
, single_fmt
, fragP
->fr_opcode
,
9192 fragP
, frag_offset
, TRUE
);
9194 diff
= size
- old_size
;
9196 assert (diff
<= fragP
->fr_var
);
9197 fragP
->fr_var
-= diff
;
9198 fragP
->fr_fix
+= diff
;
9206 convert_frag_fill_nop (fragS
*fragP
)
9208 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
9209 int size
= fragP
->tc_frag_data
.text_expansion
[0];
9210 assert ((unsigned) size
== (fragP
->fr_next
->fr_address
9211 - fragP
->fr_address
- fragP
->fr_fix
));
9214 /* No conversion. */
9218 assemble_nop (size
, loc
);
9219 fragP
->tc_frag_data
.is_insn
= TRUE
;
9220 fragP
->fr_var
-= size
;
9221 fragP
->fr_fix
+= size
;
9226 static fixS
*fix_new_exp_in_seg
9227 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
9228 bfd_reloc_code_real_type
);
9229 static void convert_frag_immed_finish_loop (segT
, fragS
*, TInsn
*);
9232 convert_frag_immed (segT segP
,
9238 char *immed_instr
= fragP
->fr_opcode
;
9240 bfd_boolean expanded
= FALSE
;
9241 bfd_boolean branch_jmp_to_next
= FALSE
;
9242 char *fr_opcode
= fragP
->fr_opcode
;
9243 vliw_insn orig_vinsn
;
9244 xtensa_isa isa
= xtensa_default_isa
;
9245 bfd_boolean wide_insn
= FALSE
;
9247 bfd_boolean is_loop
;
9249 assert (fr_opcode
!= NULL
);
9251 xg_init_vinsn (&orig_vinsn
);
9253 vinsn_from_chars (&orig_vinsn
, fr_opcode
);
9254 if (xtensa_format_num_slots (isa
, fmt
) > 1)
9257 orig_tinsn
= orig_vinsn
.slots
[slot
];
9258 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
9260 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
9262 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9263 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
9265 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
9267 /* Conversion just inserts a NOP and marks the fix as completed. */
9268 bytes
= xtensa_format_length (isa
, fmt
);
9271 orig_vinsn
.slots
[slot
].opcode
=
9272 xtensa_format_slot_nop_opcode (isa
, orig_vinsn
.format
, slot
);
9273 orig_vinsn
.slots
[slot
].ntok
= 0;
9277 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
9278 assert (bytes
== 2 || bytes
== 3);
9279 build_nop (&orig_vinsn
.slots
[0], bytes
);
9280 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
9282 vinsn_to_insnbuf (&orig_vinsn
, fr_opcode
, frag_now
, FALSE
);
9283 xtensa_insnbuf_to_chars
9284 (isa
, orig_vinsn
.insnbuf
, (unsigned char *) fr_opcode
, 0);
9289 /* Here is the fun stuff: Get the immediate field from this
9290 instruction. If it fits, we're done. If not, find the next
9291 instruction sequence that fits. */
9295 symbolS
*lit_sym
= NULL
;
9297 int target_offset
= 0;
9300 symbolS
*gen_label
= NULL
;
9301 offsetT frag_offset
;
9302 bfd_boolean first
= TRUE
;
9303 bfd_boolean last_is_jump
;
9305 /* It does not fit. Find something that does and
9306 convert immediately. */
9307 frag_offset
= fr_opcode
- fragP
->fr_literal
;
9308 istack_init (&istack
);
9309 xg_assembly_relax (&istack
, &orig_tinsn
,
9310 segP
, fragP
, frag_offset
, min_steps
, 0);
9312 old_size
= xtensa_format_length (isa
, fmt
);
9314 /* Assemble this right inline. */
9316 /* First, create the mapping from a label name to the REAL label. */
9318 for (i
= 0; i
< istack
.ninsn
; i
++)
9320 TInsn
*tinsn
= &istack
.insn
[i
];
9323 switch (tinsn
->insn_type
)
9326 if (lit_sym
!= NULL
)
9327 as_bad (_("multiple literals in expansion"));
9328 /* First find the appropriate space in the literal pool. */
9329 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9330 if (lit_frag
== NULL
)
9331 as_bad (_("no registered fragment for literal"));
9332 if (tinsn
->ntok
!= 1)
9333 as_bad (_("number of literal tokens != 1"));
9335 /* Set the literal symbol and add a fixup. */
9336 lit_sym
= lit_frag
->fr_symbol
;
9340 if (align_targets
&& !is_loop
)
9342 fragS
*unreach
= fragP
->fr_next
;
9343 while (!(unreach
->fr_type
== rs_machine_dependent
9344 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9345 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
9347 unreach
= unreach
->fr_next
;
9350 assert (unreach
->fr_type
== rs_machine_dependent
9351 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9352 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
9354 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
9356 assert (gen_label
== NULL
);
9357 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
9358 fr_opcode
- fragP
->fr_literal
9359 + target_offset
, fragP
);
9363 if (first
&& wide_insn
)
9365 target_offset
+= xtensa_format_length (isa
, fmt
);
9367 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9368 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9371 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9378 last_is_jump
= FALSE
;
9379 for (i
= 0; i
< istack
.ninsn
; i
++)
9381 TInsn
*tinsn
= &istack
.insn
[i
];
9385 bfd_reloc_code_real_type reloc_type
;
9387 switch (tinsn
->insn_type
)
9390 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9391 /* Already checked. */
9392 assert (lit_frag
!= NULL
);
9393 assert (lit_sym
!= NULL
);
9394 assert (tinsn
->ntok
== 1);
9396 target_seg
= S_GET_SEGMENT (lit_sym
);
9397 assert (target_seg
);
9398 if (tinsn
->tok
[0].X_op
== O_pltrel
)
9399 reloc_type
= BFD_RELOC_XTENSA_PLT
;
9401 reloc_type
= BFD_RELOC_32
;
9402 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
9403 &tinsn
->tok
[0], FALSE
, reloc_type
);
9410 xg_resolve_labels (tinsn
, gen_label
);
9411 xg_resolve_literals (tinsn
, lit_sym
);
9412 if (wide_insn
&& first
)
9415 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9417 tinsn
->record_fix
= TRUE
;
9418 orig_vinsn
.slots
[slot
] = *tinsn
;
9422 orig_vinsn
.slots
[slot
].opcode
=
9423 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
9424 orig_vinsn
.slots
[slot
].ntok
= 0;
9425 orig_vinsn
.slots
[slot
].record_fix
= FALSE
;
9427 vinsn_to_insnbuf (&orig_vinsn
, immed_instr
, fragP
, TRUE
);
9428 xtensa_insnbuf_to_chars (isa
, orig_vinsn
.insnbuf
,
9429 (unsigned char *) immed_instr
, 0);
9430 fragP
->tc_frag_data
.is_insn
= TRUE
;
9431 size
= xtensa_format_length (isa
, fmt
);
9432 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9434 xtensa_format single_fmt
=
9435 xg_get_single_format (tinsn
->opcode
);
9438 (tinsn
, single_fmt
, immed_instr
+ size
, fragP
,
9439 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
9440 size
+= xg_get_single_size (tinsn
->opcode
);
9445 xtensa_format single_format
;
9446 size
= xg_get_single_size (tinsn
->opcode
);
9447 single_format
= xg_get_single_format (tinsn
->opcode
);
9448 xg_emit_insn_to_buf (tinsn
, single_format
, immed_instr
,
9450 immed_instr
- fragP
->fr_literal
, TRUE
);
9452 immed_instr
+= size
;
9458 diff
= total_size
- old_size
;
9462 assert (diff
<= fragP
->fr_var
);
9463 fragP
->fr_var
-= diff
;
9464 fragP
->fr_fix
+= diff
;
9468 xg_free_vinsn (&orig_vinsn
);
9470 /* Check for undefined immediates in LOOP instructions. */
9474 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
9475 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9477 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9480 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
9481 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9483 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9488 if (expanded
&& xtensa_opcode_is_loop (isa
, orig_tinsn
.opcode
) == 1)
9489 convert_frag_immed_finish_loop (segP
, fragP
, &orig_tinsn
);
9491 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
9493 /* Add an expansion note on the expanded instruction. */
9494 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
9495 &orig_tinsn
.tok
[0], TRUE
,
9496 BFD_RELOC_XTENSA_ASM_EXPAND
);
9501 /* Add a new fix expression into the desired segment. We have to
9502 switch to that segment to do this. */
9505 fix_new_exp_in_seg (segT new_seg
,
9512 bfd_reloc_code_real_type r_type
)
9516 subsegT subseg
= now_subseg
;
9518 assert (new_seg
!= 0);
9519 subseg_set (new_seg
, new_subseg
);
9521 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
9522 subseg_set (seg
, subseg
);
9527 /* Relax a loop instruction so that it can span loop >256 bytes.
9533 addi as, as, lo8 (label-.L1)
9534 addmi as, as, mid8 (label-.L1)
9545 convert_frag_immed_finish_loop (segT segP
, fragS
*fragP
, TInsn
*tinsn
)
9550 unsigned long target
;
9551 static xtensa_insnbuf insnbuf
= NULL
;
9552 unsigned int loop_length
, loop_length_hi
, loop_length_lo
;
9553 xtensa_isa isa
= xtensa_default_isa
;
9554 addressT loop_offset
;
9555 addressT addi_offset
= 9;
9556 addressT addmi_offset
= 12;
9561 insnbuf
= xtensa_insnbuf_alloc (isa
);
9563 /* Get the loop offset. */
9564 loop_offset
= get_expanded_loop_offset (tinsn
->opcode
);
9566 /* Validate that there really is a LOOP at the loop_offset. Because
9567 loops are not bundleable, we can assume that the instruction will be
9569 tinsn_from_chars (&loop_insn
, fragP
->fr_opcode
+ loop_offset
, 0);
9570 tinsn_immed_from_frag (&loop_insn
, fragP
, 0);
9572 assert (xtensa_opcode_is_loop (isa
, loop_insn
.opcode
) == 1);
9573 addi_offset
+= loop_offset
;
9574 addmi_offset
+= loop_offset
;
9576 assert (tinsn
->ntok
== 2);
9577 if (tinsn
->tok
[1].X_op
== O_constant
)
9578 target
= tinsn
->tok
[1].X_add_number
;
9579 else if (tinsn
->tok
[1].X_op
== O_symbol
)
9581 /* Find the fragment. */
9582 symbolS
*sym
= tinsn
->tok
[1].X_add_symbol
;
9583 assert (S_GET_SEGMENT (sym
) == segP
9584 || S_GET_SEGMENT (sym
) == absolute_section
);
9585 target
= (S_GET_VALUE (sym
) + tinsn
->tok
[1].X_add_number
);
9589 as_bad (_("invalid expression evaluation type %d"), tinsn
->tok
[1].X_op
);
9594 know (symbolP
->sy_frag
);
9595 know (!(S_GET_SEGMENT (symbolP
) == absolute_section
)
9596 || symbol_get_frag (symbolP
) == &zero_address_frag
);
9598 loop_length
= target
- (fragP
->fr_address
+ fragP
->fr_fix
);
9599 loop_length_hi
= loop_length
& ~0x0ff;
9600 loop_length_lo
= loop_length
& 0x0ff;
9601 if (loop_length_lo
>= 128)
9603 loop_length_lo
-= 256;
9604 loop_length_hi
+= 256;
9607 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
9608 32512. If the loop is larger than that, then we just fail. */
9609 if (loop_length_hi
> 32512)
9610 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9611 _("loop too long for LOOP instruction"));
9613 tinsn_from_chars (&addi_insn
, fragP
->fr_opcode
+ addi_offset
, 0);
9614 assert (addi_insn
.opcode
== xtensa_addi_opcode
);
9616 tinsn_from_chars (&addmi_insn
, fragP
->fr_opcode
+ addmi_offset
, 0);
9617 assert (addmi_insn
.opcode
== xtensa_addmi_opcode
);
9619 set_expr_const (&addi_insn
.tok
[2], loop_length_lo
);
9620 tinsn_to_insnbuf (&addi_insn
, insnbuf
);
9622 fragP
->tc_frag_data
.is_insn
= TRUE
;
9623 xtensa_insnbuf_to_chars
9624 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addi_offset
, 0);
9626 set_expr_const (&addmi_insn
.tok
[2], loop_length_hi
);
9627 tinsn_to_insnbuf (&addmi_insn
, insnbuf
);
9628 xtensa_insnbuf_to_chars
9629 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addmi_offset
, 0);
9631 /* Walk through all of the frags from here to the loop end
9632 and mark them as no_transform to keep them from being modified
9633 by the linker. If we ever have a relocation for the
9634 addi/addmi of the difference of two symbols we can remove this. */
9637 for (next_fragP
= fragP
; next_fragP
!= NULL
;
9638 next_fragP
= next_fragP
->fr_next
)
9640 next_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
9641 if (next_fragP
->tc_frag_data
.is_loop_target
)
9643 if (target_count
== 2)
9649 /* A map that keeps information on a per-subsegment basis. This is
9650 maintained during initial assembly, but is invalid once the
9651 subsegments are smashed together. I.E., it cannot be used during
9654 typedef struct subseg_map_struct
9662 float total_freq
; /* fall-through + branch target frequency */
9663 float target_freq
; /* branch target frequency alone */
9665 struct subseg_map_struct
*next
;
9669 static subseg_map
*sseg_map
= NULL
;
9672 get_subseg_info (segT seg
, subsegT subseg
)
9674 subseg_map
*subseg_e
;
9676 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
9678 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
9686 add_subseg_info (segT seg
, subsegT subseg
)
9688 subseg_map
*subseg_e
= (subseg_map
*) xmalloc (sizeof (subseg_map
));
9689 memset (subseg_e
, 0, sizeof (subseg_map
));
9690 subseg_e
->seg
= seg
;
9691 subseg_e
->subseg
= subseg
;
9692 subseg_e
->flags
= 0;
9693 /* Start off considering every branch target very important. */
9694 subseg_e
->target_freq
= 1.0;
9695 subseg_e
->total_freq
= 1.0;
9696 subseg_e
->next
= sseg_map
;
9697 sseg_map
= subseg_e
;
9703 get_last_insn_flags (segT seg
, subsegT subseg
)
9705 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9707 return subseg_e
->flags
;
9713 set_last_insn_flags (segT seg
,
9718 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9720 subseg_e
= add_subseg_info (seg
, subseg
);
9722 subseg_e
->flags
|= fl
;
9724 subseg_e
->flags
&= ~fl
;
9729 get_subseg_total_freq (segT seg
, subsegT subseg
)
9731 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9733 return subseg_e
->total_freq
;
9739 get_subseg_target_freq (segT seg
, subsegT subseg
)
9741 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9743 return subseg_e
->target_freq
;
9749 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
9751 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9753 subseg_e
= add_subseg_info (seg
, subseg
);
9754 subseg_e
->total_freq
= total_f
;
9755 subseg_e
->target_freq
= target_f
;
9759 /* Segment Lists and emit_state Stuff. */
9761 /* Remove the segment from the global sections list. */
9764 xtensa_remove_section (segT sec
)
9766 /* Handle brain-dead bfd_section_list_remove macro, which
9767 expect the address of the prior section's "next" field, not
9768 just the address of the section to remove. */
9770 segT
*ps_next_ptr
= &stdoutput
->sections
;
9771 while (*ps_next_ptr
!= sec
&& *ps_next_ptr
!= NULL
)
9772 ps_next_ptr
= &(*ps_next_ptr
)->next
;
9774 assert (*ps_next_ptr
!= NULL
);
9776 bfd_section_list_remove (stdoutput
, ps_next_ptr
);
9781 xtensa_insert_section (segT after_sec
, segT sec
)
9783 segT
*after_sec_next
;
9784 if (after_sec
== NULL
)
9785 after_sec_next
= &stdoutput
->sections
;
9787 after_sec_next
= &after_sec
->next
;
9789 bfd_section_list_insert (stdoutput
, after_sec_next
, sec
);
9794 xtensa_move_seg_list_to_beginning (seg_list
*head
)
9799 segT literal_section
= head
->seg
;
9801 /* Move the literal section to the front of the section list. */
9802 assert (literal_section
);
9803 xtensa_remove_section (literal_section
);
9804 xtensa_insert_section (NULL
, literal_section
);
9811 static void mark_literal_frags (seg_list
*);
9814 xtensa_move_literals (void)
9817 frchainS
*frchain_from
, *frchain_to
;
9818 fragS
*search_frag
, *next_frag
, *last_frag
, *literal_pool
, *insert_after
;
9819 fragS
**frag_splice
;
9822 fixS
*fix
, *next_fix
, **fix_splice
;
9825 mark_literal_frags (literal_head
->next
);
9826 mark_literal_frags (init_literal_head
->next
);
9827 mark_literal_frags (fini_literal_head
->next
);
9829 if (use_literal_section
)
9832 segment
= literal_head
->next
;
9835 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9836 search_frag
= frchain_from
->frch_root
;
9837 literal_pool
= NULL
;
9839 frag_splice
= &(frchain_from
->frch_root
);
9841 while (!search_frag
->tc_frag_data
.literal_frag
)
9843 assert (search_frag
->fr_fix
== 0
9844 || search_frag
->fr_type
== rs_align
);
9845 search_frag
= search_frag
->fr_next
;
9848 assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
9849 == RELAX_LITERAL_POOL_BEGIN
);
9850 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
9852 /* Make sure that all the frags in this series are closed, and
9853 that there is at least one left over of zero-size. This
9854 prevents us from making a segment with an frchain without any
9856 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9857 xtensa_set_frag_assembly_state (frag_now
);
9858 last_frag
= frag_now
;
9859 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9860 xtensa_set_frag_assembly_state (frag_now
);
9862 while (search_frag
!= frag_now
)
9864 next_frag
= search_frag
->fr_next
;
9866 /* First, move the frag out of the literal section and
9867 to the appropriate place. */
9868 if (search_frag
->tc_frag_data
.literal_frag
)
9870 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
9871 assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
9872 frchain_to
= literal_pool
->tc_frag_data
.lit_frchain
;
9873 assert (frchain_to
);
9875 insert_after
= literal_pool
;
9877 while (insert_after
->fr_next
->fr_subtype
!= RELAX_LITERAL_POOL_END
)
9878 insert_after
= insert_after
->fr_next
;
9880 dest_seg
= insert_after
->fr_next
->tc_frag_data
.lit_seg
;
9882 *frag_splice
= next_frag
;
9883 search_frag
->fr_next
= insert_after
->fr_next
;
9884 insert_after
->fr_next
= search_frag
;
9885 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
9887 /* Now move any fixups associated with this frag to the
9889 fix
= frchain_from
->fix_root
;
9890 fix_splice
= &(frchain_from
->fix_root
);
9893 next_fix
= fix
->fx_next
;
9894 if (fix
->fx_frag
== search_frag
)
9896 *fix_splice
= next_fix
;
9897 fix
->fx_next
= frchain_to
->fix_root
;
9898 frchain_to
->fix_root
= fix
;
9899 if (frchain_to
->fix_tail
== NULL
)
9900 frchain_to
->fix_tail
= fix
;
9903 fix_splice
= &(fix
->fx_next
);
9906 search_frag
= next_frag
;
9909 if (frchain_from
->fix_root
!= NULL
)
9911 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9912 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
9914 assert (frchain_from
->fix_root
== NULL
);
9916 frchain_from
->fix_tail
= NULL
;
9917 xtensa_restore_emit_state (&state
);
9918 segment
= segment
->next
;
9921 /* Now fix up the SEGMENT value for all the literal symbols. */
9922 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
9924 symbolS
*lit_sym
= lit
->sym
;
9925 segT dest_seg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
9927 S_SET_SEGMENT (lit_sym
, dest_seg
);
9932 /* Walk over all the frags for segments in a list and mark them as
9933 containing literals. As clunky as this is, we can't rely on frag_var
9934 and frag_variant to get called in all situations. */
9937 mark_literal_frags (seg_list
*segment
)
9939 frchainS
*frchain_from
;
9944 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9945 search_frag
= frchain_from
->frch_root
;
9948 search_frag
->tc_frag_data
.is_literal
= TRUE
;
9949 search_frag
= search_frag
->fr_next
;
9951 segment
= segment
->next
;
9957 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
9959 /* Move all of the sections in the section list to come
9960 after "after" in the gnu segment list. */
9965 segT literal_section
= head
->seg
;
9967 /* Move the literal section after "after". */
9968 assert (literal_section
);
9969 if (literal_section
!= after
)
9971 xtensa_remove_section (literal_section
);
9972 xtensa_insert_section (after
, literal_section
);
9980 /* Push all the literal segments to the end of the gnu list. */
9983 xtensa_reorder_segments (void)
9990 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
9996 /* Now that we have the last section, push all the literal
9997 sections to the end. */
9998 xtensa_reorder_seg_list (literal_head
, last_sec
);
9999 xtensa_reorder_seg_list (init_literal_head
, last_sec
);
10000 xtensa_reorder_seg_list (fini_literal_head
, last_sec
);
10002 /* Now perform the final error check. */
10003 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
10005 assert (new_count
== old_count
);
10009 /* Change the emit state (seg, subseg, and frag related stuff) to the
10010 correct location. Return a emit_state which can be passed to
10011 xtensa_restore_emit_state to return to current fragment. */
10014 xtensa_switch_to_literal_fragment (emit_state
*result
)
10016 if (directive_state
[directive_absolute_literals
])
10018 cache_literal_section (0, default_lit_sections
.lit4_seg_name
,
10019 &default_lit_sections
.lit4_seg
, FALSE
);
10020 xtensa_switch_section_emit_state (result
,
10021 default_lit_sections
.lit4_seg
, 0);
10024 xtensa_switch_to_non_abs_literal_fragment (result
);
10026 /* Do a 4-byte align here. */
10027 frag_align (2, 0, 0);
10028 record_alignment (now_seg
, 2);
10033 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
10035 /* When we mark a literal pool location, we want to put a frag in
10036 the literal pool that points to it. But to do that, we want to
10037 switch_to_literal_fragment. But literal sections don't have
10038 literal pools, so their location is always null, so we would
10039 recurse forever. This is kind of hacky, but it works. */
10041 static bfd_boolean recursive
= FALSE
;
10042 fragS
*pool_location
= get_literal_pool_location (now_seg
);
10043 bfd_boolean is_init
=
10044 (now_seg
&& !strcmp (segment_name (now_seg
), INIT_SECTION_NAME
));
10046 bfd_boolean is_fini
=
10047 (now_seg
&& !strcmp (segment_name (now_seg
), FINI_SECTION_NAME
));
10049 if (pool_location
== NULL
10050 && !use_literal_section
10052 && !is_init
&& ! is_fini
)
10054 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
10056 xtensa_mark_literal_pool_location ();
10060 /* Special case: If we are in the ".fini" or ".init" section, then
10061 we will ALWAYS be generating to the ".fini.literal" and
10062 ".init.literal" sections. */
10066 cache_literal_section (init_literal_head
,
10067 default_lit_sections
.init_lit_seg_name
,
10068 &default_lit_sections
.init_lit_seg
, TRUE
);
10069 xtensa_switch_section_emit_state (result
,
10070 default_lit_sections
.init_lit_seg
, 0);
10074 cache_literal_section (fini_literal_head
,
10075 default_lit_sections
.fini_lit_seg_name
,
10076 &default_lit_sections
.fini_lit_seg
, TRUE
);
10077 xtensa_switch_section_emit_state (result
,
10078 default_lit_sections
.fini_lit_seg
, 0);
10082 cache_literal_section (literal_head
,
10083 default_lit_sections
.lit_seg_name
,
10084 &default_lit_sections
.lit_seg
, TRUE
);
10085 xtensa_switch_section_emit_state (result
,
10086 default_lit_sections
.lit_seg
, 0);
10089 if (!use_literal_section
10090 && !is_init
&& !is_fini
10091 && get_literal_pool_location (now_seg
) != pool_location
)
10093 /* Close whatever frag is there. */
10094 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10095 xtensa_set_frag_assembly_state (frag_now
);
10096 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
10097 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10098 xtensa_set_frag_assembly_state (frag_now
);
10103 /* Call this function before emitting data into the literal section.
10104 This is a helper function for xtensa_switch_to_literal_fragment.
10105 This is similar to a .section new_now_seg subseg. */
10108 xtensa_switch_section_emit_state (emit_state
*state
,
10110 subsegT new_now_subseg
)
10112 state
->name
= now_seg
->name
;
10113 state
->now_seg
= now_seg
;
10114 state
->now_subseg
= now_subseg
;
10115 state
->generating_literals
= generating_literals
;
10116 generating_literals
++;
10117 subseg_set (new_now_seg
, new_now_subseg
);
10121 /* Use to restore the emitting into the normal place. */
10124 xtensa_restore_emit_state (emit_state
*state
)
10126 generating_literals
= state
->generating_literals
;
10127 subseg_set (state
->now_seg
, state
->now_subseg
);
10131 /* Get a segment of a given name. If the segment is already
10132 present, return it; otherwise, create a new one. */
10135 cache_literal_section (seg_list
*head
,
10138 bfd_boolean is_code
)
10140 segT current_section
= now_seg
;
10141 int current_subsec
= now_subseg
;
10147 /* Check if the named section exists. */
10148 for (seg
= stdoutput
->sections
; seg
; seg
= seg
->next
)
10150 if (!strcmp (segment_name (seg
), name
))
10156 /* Create a new literal section. */
10157 seg
= subseg_new (name
, (subsegT
) 0);
10160 /* Add the newly created literal segment to the specified list. */
10161 seg_list
*n
= (seg_list
*) xmalloc (sizeof (seg_list
));
10163 n
->next
= head
->next
;
10166 bfd_set_section_flags (stdoutput
, seg
, SEC_HAS_CONTENTS
|
10167 SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
10168 | (is_code
? SEC_CODE
: SEC_DATA
));
10169 bfd_set_section_alignment (stdoutput
, seg
, 2);
10173 subseg_set (current_section
, current_subsec
);
10177 /* Property Tables Stuff. */
10179 #define XTENSA_INSN_SEC_NAME ".xt.insn"
10180 #define XTENSA_LIT_SEC_NAME ".xt.lit"
10181 #define XTENSA_PROP_SEC_NAME ".xt.prop"
10183 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
10184 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
10186 static bfd_boolean
get_frag_is_literal (const fragS
*);
10187 static void xtensa_create_property_segments
10188 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
10189 static void xtensa_create_xproperty_segments
10190 (frag_flags_fn
, const char *, xt_section_type
);
10191 static segment_info_type
*retrieve_segment_info (segT
);
10192 static segT
retrieve_xtensa_section (char *);
10193 static bfd_boolean
section_has_property (segT
, frag_predicate
);
10194 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
10195 static void add_xt_block_frags
10196 (segT
, segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
10197 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
10198 static void xtensa_frag_flags_init (frag_flags
*);
10199 static void get_frag_property_flags (const fragS
*, frag_flags
*);
10200 static bfd_vma
frag_flags_to_number (const frag_flags
*);
10201 static void add_xt_prop_frags
10202 (segT
, segT
, xtensa_block_info
**, frag_flags_fn
);
10204 /* Set up property tables after relaxation. */
10207 xtensa_post_relax_hook (void)
10209 xtensa_move_seg_list_to_beginning (literal_head
);
10210 xtensa_move_seg_list_to_beginning (init_literal_head
);
10211 xtensa_move_seg_list_to_beginning (fini_literal_head
);
10213 xtensa_find_unmarked_state_frags ();
10215 if (use_literal_section
)
10216 xtensa_create_property_segments (get_frag_is_literal
,
10218 XTENSA_LIT_SEC_NAME
,
10220 xtensa_create_xproperty_segments (get_frag_property_flags
,
10221 XTENSA_PROP_SEC_NAME
,
10224 if (warn_unaligned_branch_targets
)
10225 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
10226 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
10230 /* This function is only meaningful after xtensa_move_literals. */
10233 get_frag_is_literal (const fragS
*fragP
)
10235 assert (fragP
!= NULL
);
10236 return fragP
->tc_frag_data
.is_literal
;
10241 xtensa_create_property_segments (frag_predicate property_function
,
10242 frag_predicate end_property_function
,
10243 const char *section_name_base
,
10244 xt_section_type sec_type
)
10248 /* Walk over all of the current segments.
10249 Walk over each fragment
10250 For each non-empty fragment,
10251 Build a property record (append where possible). */
10253 for (seclist
= &stdoutput
->sections
;
10254 seclist
&& *seclist
;
10255 seclist
= &(*seclist
)->next
)
10257 segT sec
= *seclist
;
10260 flags
= bfd_get_section_flags (stdoutput
, sec
);
10261 if (flags
& SEC_DEBUGGING
)
10263 if (!(flags
& SEC_ALLOC
))
10266 if (section_has_property (sec
, property_function
))
10268 char *property_section_name
=
10269 xtensa_get_property_section_name (sec
, section_name_base
);
10270 segT insn_sec
= retrieve_xtensa_section (property_section_name
);
10271 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10272 xtensa_block_info
**xt_blocks
=
10273 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10274 /* Walk over all of the frchains here and add new sections. */
10275 add_xt_block_frags (sec
, insn_sec
, xt_blocks
, property_function
,
10276 end_property_function
);
10280 /* Now we fill them out.... */
10282 for (seclist
= &stdoutput
->sections
;
10283 seclist
&& *seclist
;
10284 seclist
= &(*seclist
)->next
)
10286 segment_info_type
*seginfo
;
10287 xtensa_block_info
*block
;
10288 segT sec
= *seclist
;
10290 seginfo
= seg_info (sec
);
10291 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10295 xtensa_block_info
*cur_block
;
10296 /* This is a section with some data. */
10298 bfd_size_type rec_size
;
10300 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10303 rec_size
= num_recs
* 8;
10304 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10306 /* In order to make this work with the assembler, we have to
10307 build some frags and then build the "fixups" for it. It
10308 would be easier to just set the contents then set the
10313 /* Allocate a fragment and leak it. */
10315 bfd_size_type frag_size
;
10317 frchainS
*frchainP
;
10321 frag_size
= sizeof (fragS
) + rec_size
;
10322 fragP
= (fragS
*) xmalloc (frag_size
);
10324 memset (fragP
, 0, frag_size
);
10325 fragP
->fr_address
= 0;
10326 fragP
->fr_next
= NULL
;
10327 fragP
->fr_fix
= rec_size
;
10329 fragP
->fr_type
= rs_fill
;
10330 /* The rest are zeros. */
10332 frchainP
= seginfo
->frchainP
;
10333 frchainP
->frch_root
= fragP
;
10334 frchainP
->frch_last
= fragP
;
10336 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10337 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10339 seginfo
->fix_root
= fixes
;
10340 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10342 frag_data
= &fragP
->fr_literal
[0];
10343 for (i
= 0; i
< num_recs
; i
++)
10345 fixS
*fix
= &fixes
[i
];
10346 assert (cur_block
);
10348 /* Write the fixup. */
10349 if (i
!= num_recs
- 1)
10350 fix
->fx_next
= &fixes
[i
+ 1];
10352 fix
->fx_next
= NULL
;
10355 fix
->fx_frag
= fragP
;
10356 fix
->fx_where
= i
* 8;
10357 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10358 fix
->fx_offset
= cur_block
->offset
;
10359 fix
->fx_r_type
= BFD_RELOC_32
;
10360 fix
->fx_file
= "Internal Assembly";
10363 /* Write the length. */
10364 md_number_to_chars (&frag_data
[4 + 8 * i
],
10365 cur_block
->size
, 4);
10366 cur_block
= cur_block
->next
;
10375 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
10376 const char *section_name_base
,
10377 xt_section_type sec_type
)
10381 /* Walk over all of the current segments.
10382 Walk over each fragment.
10383 For each fragment that has instructions,
10384 build an instruction record (append where possible). */
10386 for (seclist
= &stdoutput
->sections
;
10387 seclist
&& *seclist
;
10388 seclist
= &(*seclist
)->next
)
10390 segT sec
= *seclist
;
10393 flags
= bfd_get_section_flags (stdoutput
, sec
);
10394 if ((flags
& SEC_DEBUGGING
)
10395 || !(flags
& SEC_ALLOC
)
10396 || (flags
& SEC_MERGE
))
10399 if (section_has_xproperty (sec
, flag_fn
))
10401 char *property_section_name
=
10402 xtensa_get_property_section_name (sec
, section_name_base
);
10403 segT insn_sec
= retrieve_xtensa_section (property_section_name
);
10404 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10405 xtensa_block_info
**xt_blocks
=
10406 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10407 /* Walk over all of the frchains here and add new sections. */
10408 add_xt_prop_frags (sec
, insn_sec
, xt_blocks
, flag_fn
);
10412 /* Now we fill them out.... */
10414 for (seclist
= &stdoutput
->sections
;
10415 seclist
&& *seclist
;
10416 seclist
= &(*seclist
)->next
)
10418 segment_info_type
*seginfo
;
10419 xtensa_block_info
*block
;
10420 segT sec
= *seclist
;
10422 seginfo
= seg_info (sec
);
10423 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10427 xtensa_block_info
*cur_block
;
10428 /* This is a section with some data. */
10430 bfd_size_type rec_size
;
10432 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10435 rec_size
= num_recs
* (8 + 4);
10436 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10438 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
10440 /* In order to make this work with the assembler, we have to build
10441 some frags then build the "fixups" for it. It would be easier to
10442 just set the contents then set the arlents. */
10446 /* Allocate a fragment and (unfortunately) leak it. */
10448 bfd_size_type frag_size
;
10450 frchainS
*frchainP
;
10454 frag_size
= sizeof (fragS
) + rec_size
;
10455 fragP
= (fragS
*) xmalloc (frag_size
);
10457 memset (fragP
, 0, frag_size
);
10458 fragP
->fr_address
= 0;
10459 fragP
->fr_next
= NULL
;
10460 fragP
->fr_fix
= rec_size
;
10462 fragP
->fr_type
= rs_fill
;
10463 /* The rest are zeros. */
10465 frchainP
= seginfo
->frchainP
;
10466 frchainP
->frch_root
= fragP
;
10467 frchainP
->frch_last
= fragP
;
10469 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10470 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10472 seginfo
->fix_root
= fixes
;
10473 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10475 frag_data
= &fragP
->fr_literal
[0];
10476 for (i
= 0; i
< num_recs
; i
++)
10478 fixS
*fix
= &fixes
[i
];
10479 assert (cur_block
);
10481 /* Write the fixup. */
10482 if (i
!= num_recs
- 1)
10483 fix
->fx_next
= &fixes
[i
+ 1];
10485 fix
->fx_next
= NULL
;
10488 fix
->fx_frag
= fragP
;
10489 fix
->fx_where
= i
* (8 + 4);
10490 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10491 fix
->fx_offset
= cur_block
->offset
;
10492 fix
->fx_r_type
= BFD_RELOC_32
;
10493 fix
->fx_file
= "Internal Assembly";
10496 /* Write the length. */
10497 md_number_to_chars (&frag_data
[4 + (8+4) * i
],
10498 cur_block
->size
, 4);
10499 md_number_to_chars (&frag_data
[8 + (8+4) * i
],
10500 frag_flags_to_number (&cur_block
->flags
),
10502 cur_block
= cur_block
->next
;
10510 static segment_info_type
*
10511 retrieve_segment_info (segT seg
)
10513 segment_info_type
*seginfo
;
10514 seginfo
= (segment_info_type
*) bfd_get_section_userdata (stdoutput
, seg
);
10517 frchainS
*frchainP
;
10519 seginfo
= (segment_info_type
*) xmalloc (sizeof (*seginfo
));
10520 memset ((void *) seginfo
, 0, sizeof (*seginfo
));
10521 seginfo
->fix_root
= NULL
;
10522 seginfo
->fix_tail
= NULL
;
10523 seginfo
->bfd_section
= seg
;
10525 /* We will not be dealing with these, only our special ones. */
10526 bfd_set_section_userdata (stdoutput
, seg
, (void *) seginfo
);
10528 frchainP
= (frchainS
*) xmalloc (sizeof (frchainS
));
10529 frchainP
->frch_root
= NULL
;
10530 frchainP
->frch_last
= NULL
;
10531 frchainP
->frch_next
= NULL
;
10532 frchainP
->frch_seg
= seg
;
10533 frchainP
->frch_subseg
= 0;
10534 frchainP
->fix_root
= NULL
;
10535 frchainP
->fix_tail
= NULL
;
10536 /* Do not init the objstack. */
10537 /* obstack_begin (&frchainP->frch_obstack, chunksize); */
10538 /* frchainP->frch_frag_now = fragP; */
10539 frchainP
->frch_frag_now
= NULL
;
10541 seginfo
->frchainP
= frchainP
;
10549 retrieve_xtensa_section (char *sec_name
)
10551 bfd
*abfd
= stdoutput
;
10552 flagword flags
, out_flags
, link_once_flags
;
10555 flags
= bfd_get_section_flags (abfd
, now_seg
);
10556 link_once_flags
= (flags
& SEC_LINK_ONCE
);
10557 if (link_once_flags
)
10558 link_once_flags
|= (flags
& SEC_LINK_DUPLICATES
);
10559 out_flags
= (SEC_RELOC
| SEC_HAS_CONTENTS
| SEC_READONLY
| link_once_flags
);
10561 s
= bfd_make_section_old_way (abfd
, sec_name
);
10563 as_bad (_("could not create section %s"), sec_name
);
10564 if (!bfd_set_section_flags (abfd
, s
, out_flags
))
10565 as_bad (_("invalid flag combination on section %s"), sec_name
);
10572 section_has_property (segT sec
, frag_predicate property_function
)
10574 segment_info_type
*seginfo
= seg_info (sec
);
10577 if (seginfo
&& seginfo
->frchainP
)
10579 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10581 if (property_function (fragP
)
10582 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10591 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
10593 segment_info_type
*seginfo
= seg_info (sec
);
10596 if (seginfo
&& seginfo
->frchainP
)
10598 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10600 frag_flags prop_flags
;
10601 property_function (fragP
, &prop_flags
);
10602 if (!xtensa_frag_flags_is_empty (&prop_flags
))
10610 /* Two types of block sections exist right now: literal and insns. */
10613 add_xt_block_frags (segT sec
,
10615 xtensa_block_info
**xt_block
,
10616 frag_predicate property_function
,
10617 frag_predicate end_property_function
)
10619 segment_info_type
*seg_info
;
10620 segment_info_type
*xt_seg_info
;
10621 bfd_vma seg_offset
;
10624 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
10625 seg_info
= retrieve_segment_info (sec
);
10627 /* Build it if needed. */
10628 while (*xt_block
!= NULL
)
10629 xt_block
= &(*xt_block
)->next
;
10630 /* We are either at NULL at the beginning or at the end. */
10632 /* Walk through the frags. */
10635 if (seg_info
->frchainP
)
10637 for (fragP
= seg_info
->frchainP
->frch_root
;
10639 fragP
= fragP
->fr_next
)
10641 if (property_function (fragP
)
10642 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10644 if (*xt_block
!= NULL
)
10646 if ((*xt_block
)->offset
+ (*xt_block
)->size
10647 == fragP
->fr_address
)
10648 (*xt_block
)->size
+= fragP
->fr_fix
;
10650 xt_block
= &((*xt_block
)->next
);
10652 if (*xt_block
== NULL
)
10654 xtensa_block_info
*new_block
= (xtensa_block_info
*)
10655 xmalloc (sizeof (xtensa_block_info
));
10656 new_block
->sec
= sec
;
10657 new_block
->offset
= fragP
->fr_address
;
10658 new_block
->size
= fragP
->fr_fix
;
10659 new_block
->next
= NULL
;
10660 xtensa_frag_flags_init (&new_block
->flags
);
10661 *xt_block
= new_block
;
10663 if (end_property_function
10664 && end_property_function (fragP
))
10666 xt_block
= &((*xt_block
)->next
);
10674 /* Break the encapsulation of add_xt_prop_frags here. */
10677 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
10679 if (prop_flags
->is_literal
10680 || prop_flags
->is_insn
10681 || prop_flags
->is_data
10682 || prop_flags
->is_unreachable
)
10689 xtensa_frag_flags_init (frag_flags
*prop_flags
)
10691 memset (prop_flags
, 0, sizeof (frag_flags
));
10696 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
10698 xtensa_frag_flags_init (prop_flags
);
10699 if (fragP
->tc_frag_data
.is_literal
)
10700 prop_flags
->is_literal
= TRUE
;
10701 if (fragP
->tc_frag_data
.is_unreachable
)
10702 prop_flags
->is_unreachable
= TRUE
;
10703 else if (fragP
->tc_frag_data
.is_insn
)
10705 prop_flags
->is_insn
= TRUE
;
10706 if (fragP
->tc_frag_data
.is_loop_target
)
10707 prop_flags
->insn
.is_loop_target
= TRUE
;
10708 if (fragP
->tc_frag_data
.is_branch_target
)
10709 prop_flags
->insn
.is_branch_target
= TRUE
;
10710 if (fragP
->tc_frag_data
.is_specific_opcode
10711 || fragP
->tc_frag_data
.is_no_transform
)
10712 prop_flags
->insn
.is_no_transform
= TRUE
;
10713 if (fragP
->tc_frag_data
.is_no_density
)
10714 prop_flags
->insn
.is_no_density
= TRUE
;
10715 if (fragP
->tc_frag_data
.use_absolute_literals
)
10716 prop_flags
->insn
.is_abslit
= TRUE
;
10718 if (fragP
->tc_frag_data
.is_align
)
10720 prop_flags
->is_align
= TRUE
;
10721 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
10722 if (xtensa_frag_flags_is_empty (prop_flags
))
10723 prop_flags
->is_data
= TRUE
;
10729 frag_flags_to_number (const frag_flags
*prop_flags
)
10732 if (prop_flags
->is_literal
)
10733 num
|= XTENSA_PROP_LITERAL
;
10734 if (prop_flags
->is_insn
)
10735 num
|= XTENSA_PROP_INSN
;
10736 if (prop_flags
->is_data
)
10737 num
|= XTENSA_PROP_DATA
;
10738 if (prop_flags
->is_unreachable
)
10739 num
|= XTENSA_PROP_UNREACHABLE
;
10740 if (prop_flags
->insn
.is_loop_target
)
10741 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
10742 if (prop_flags
->insn
.is_branch_target
)
10744 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
10745 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
10748 if (prop_flags
->insn
.is_no_density
)
10749 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
10750 if (prop_flags
->insn
.is_no_transform
)
10751 num
|= XTENSA_PROP_INSN_NO_TRANSFORM
;
10752 if (prop_flags
->insn
.is_no_reorder
)
10753 num
|= XTENSA_PROP_INSN_NO_REORDER
;
10754 if (prop_flags
->insn
.is_abslit
)
10755 num
|= XTENSA_PROP_INSN_ABSLIT
;
10757 if (prop_flags
->is_align
)
10759 num
|= XTENSA_PROP_ALIGN
;
10760 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
10768 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
10769 const frag_flags
*prop_flags_2
)
10771 /* Cannot combine with an end marker. */
10773 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
10775 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
10777 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
10780 if (prop_flags_1
->is_insn
)
10782 /* Properties of the beginning of the frag. */
10783 if (prop_flags_2
->insn
.is_loop_target
)
10785 if (prop_flags_2
->insn
.is_branch_target
)
10787 if (prop_flags_1
->insn
.is_no_density
!=
10788 prop_flags_2
->insn
.is_no_density
)
10790 if (prop_flags_1
->insn
.is_no_transform
!=
10791 prop_flags_2
->insn
.is_no_transform
)
10793 if (prop_flags_1
->insn
.is_no_reorder
!=
10794 prop_flags_2
->insn
.is_no_reorder
)
10796 if (prop_flags_1
->insn
.is_abslit
!=
10797 prop_flags_2
->insn
.is_abslit
)
10801 if (prop_flags_1
->is_align
)
10809 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
10812 unsigned align_bits
;
10814 if (!xt_block
->flags
.is_align
)
10815 return xt_block
->size
;
10817 end_addr
= xt_block
->offset
+ xt_block
->size
;
10818 align_bits
= xt_block
->flags
.alignment
;
10819 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
10820 return end_addr
- xt_block
->offset
;
10825 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
10826 const xtensa_block_info
*xt_block_2
)
10828 if (xt_block
->sec
!= xt_block_2
->sec
)
10830 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
10831 != xt_block_2
->offset
)
10834 if (xt_block_2
->size
== 0
10835 && (!xt_block_2
->flags
.is_unreachable
10836 || xt_block
->flags
.is_unreachable
))
10838 if (xt_block_2
->flags
.is_align
10839 && xt_block
->flags
.is_align
)
10841 /* Nothing needed. */
10842 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
10847 if (xt_block_2
->flags
.is_align
)
10849 /* Push alignment to previous entry. */
10850 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
10851 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10856 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
10857 &xt_block_2
->flags
))
10860 xt_block
->size
+= xt_block_2
->size
;
10862 if (xt_block_2
->flags
.is_align
)
10864 xt_block
->flags
.is_align
= TRUE
;
10865 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10873 add_xt_prop_frags (segT sec
,
10875 xtensa_block_info
**xt_block
,
10876 frag_flags_fn property_function
)
10878 segment_info_type
*seg_info
;
10879 segment_info_type
*xt_seg_info
;
10880 bfd_vma seg_offset
;
10883 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
10884 seg_info
= retrieve_segment_info (sec
);
10885 /* Build it if needed. */
10886 while (*xt_block
!= NULL
)
10888 xt_block
= &(*xt_block
)->next
;
10890 /* We are either at NULL at the beginning or at the end. */
10892 /* Walk through the frags. */
10895 if (seg_info
->frchainP
)
10897 for (fragP
= seg_info
->frchainP
->frch_root
; fragP
;
10898 fragP
= fragP
->fr_next
)
10900 xtensa_block_info tmp_block
;
10901 tmp_block
.sec
= sec
;
10902 tmp_block
.offset
= fragP
->fr_address
;
10903 tmp_block
.size
= fragP
->fr_fix
;
10904 tmp_block
.next
= NULL
;
10905 property_function (fragP
, &tmp_block
.flags
);
10907 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
10908 /* && fragP->fr_fix != 0) */
10910 if ((*xt_block
) == NULL
10911 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
10913 xtensa_block_info
*new_block
;
10914 if ((*xt_block
) != NULL
)
10915 xt_block
= &(*xt_block
)->next
;
10916 new_block
= (xtensa_block_info
*)
10917 xmalloc (sizeof (xtensa_block_info
));
10918 *new_block
= tmp_block
;
10919 *xt_block
= new_block
;
10927 /* op_placement_info_table */
10929 /* op_placement_info makes it easier to determine which
10930 ops can go in which slots. */
10933 init_op_placement_info_table (void)
10935 xtensa_isa isa
= xtensa_default_isa
;
10936 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
10937 xtensa_opcode opcode
;
10940 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
10942 op_placement_table
= (op_placement_info_table
)
10943 xmalloc (sizeof (op_placement_info
) * num_opcodes
);
10944 assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
10946 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
10948 op_placement_info
*opi
= &op_placement_table
[opcode
];
10949 /* FIXME: Make tinsn allocation dynamic. */
10950 if (xtensa_opcode_num_operands (isa
, opcode
) >= MAX_INSN_ARGS
)
10951 as_fatal (_("too many operands in instruction"));
10952 opi
->single
= XTENSA_UNDEFINED
;
10953 opi
->single_size
= 0;
10954 opi
->widest
= XTENSA_UNDEFINED
;
10955 opi
->widest_size
= 0;
10956 opi
->narrowest
= XTENSA_UNDEFINED
;
10957 opi
->narrowest_size
= 0x7F;
10959 opi
->num_formats
= 0;
10961 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
10963 opi
->slots
[fmt
] = 0;
10964 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
10966 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
10968 int fmt_length
= xtensa_format_length (isa
, fmt
);
10970 set_bit (fmt
, opi
->formats
);
10971 set_bit (slot
, opi
->slots
[fmt
]);
10972 /* opi->slot_count[fmt]++; */
10973 if (fmt_length
< opi
->narrowest_size
)
10975 opi
->narrowest
= fmt
;
10976 opi
->narrowest_size
= fmt_length
;
10978 if (fmt_length
> opi
->widest_size
)
10981 opi
->widest_size
= fmt_length
;
10983 if (xtensa_format_num_slots (isa
, fmt
) == 1)
10985 if (opi
->single_size
== 0
10986 || fmt_length
< opi
->single_size
)
10989 opi
->single_size
= fmt_length
;
10995 opi
->num_formats
++;
10998 xtensa_insnbuf_free (isa
, ibuf
);
11003 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
11005 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
11009 /* If the opcode is available in a single slot format, return its size. */
11012 xg_get_single_size (xtensa_opcode opcode
)
11014 assert (op_placement_table
[opcode
].single
!= XTENSA_UNDEFINED
);
11015 return op_placement_table
[opcode
].single_size
;
11019 static xtensa_format
11020 xg_get_single_format (xtensa_opcode opcode
)
11022 return op_placement_table
[opcode
].single
;
11026 /* Instruction Stack Functions (from "xtensa-istack.h"). */
11029 istack_init (IStack
*stack
)
11031 memset (stack
, 0, sizeof (IStack
));
11037 istack_empty (IStack
*stack
)
11039 return (stack
->ninsn
== 0);
11044 istack_full (IStack
*stack
)
11046 return (stack
->ninsn
== MAX_ISTACK
);
11050 /* Return a pointer to the top IStack entry.
11051 It is an error to call this if istack_empty () is TRUE. */
11054 istack_top (IStack
*stack
)
11056 int rec
= stack
->ninsn
- 1;
11057 assert (!istack_empty (stack
));
11058 return &stack
->insn
[rec
];
11062 /* Add a new TInsn to an IStack.
11063 It is an error to call this if istack_full () is TRUE. */
11066 istack_push (IStack
*stack
, TInsn
*insn
)
11068 int rec
= stack
->ninsn
;
11069 assert (!istack_full (stack
));
11070 stack
->insn
[rec
] = *insn
;
11075 /* Clear space for the next TInsn on the IStack and return a pointer
11076 to it. It is an error to call this if istack_full () is TRUE. */
11079 istack_push_space (IStack
*stack
)
11081 int rec
= stack
->ninsn
;
11083 assert (!istack_full (stack
));
11084 insn
= &stack
->insn
[rec
];
11085 memset (insn
, 0, sizeof (TInsn
));
11091 /* Remove the last pushed instruction. It is an error to call this if
11092 istack_empty () returns TRUE. */
11095 istack_pop (IStack
*stack
)
11097 int rec
= stack
->ninsn
- 1;
11098 assert (!istack_empty (stack
));
11100 memset (&stack
->insn
[rec
], 0, sizeof (TInsn
));
11104 /* TInsn functions. */
11107 tinsn_init (TInsn
*dst
)
11109 memset (dst
, 0, sizeof (TInsn
));
11113 /* Get the ``num''th token of the TInsn.
11114 It is illegal to call this if num > insn->ntoks. */
11117 tinsn_get_tok (TInsn
*insn
, int num
)
11119 assert (num
< insn
->ntok
);
11120 return &insn
->tok
[num
];
11124 /* Return TRUE if ANY of the operands in the insn are symbolic. */
11127 tinsn_has_symbolic_operands (const TInsn
*insn
)
11130 int n
= insn
->ntok
;
11132 assert (insn
->insn_type
== ITYPE_INSN
);
11134 for (i
= 0; i
< n
; ++i
)
11136 switch (insn
->tok
[i
].X_op
)
11150 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
11152 xtensa_isa isa
= xtensa_default_isa
;
11154 int n
= insn
->ntok
;
11156 assert (insn
->insn_type
== ITYPE_INSN
);
11158 for (i
= 0; i
< n
; ++i
)
11160 switch (insn
->tok
[i
].X_op
)
11168 /* Errors for these types are caught later. */
11173 /* Symbolic immediates are only allowed on the last immediate
11174 operand. At this time, CONST16 is the only opcode where we
11175 support non-PC-relative relocations. (It isn't necessary
11176 to complain about non-PC-relative relocations here, but
11177 otherwise, no error is reported until the relocations are
11178 generated, and the assembler won't get that far if there
11179 are any other errors. It's nice to see all the problems
11181 if (i
!= get_relaxable_immed (insn
->opcode
)
11182 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
11183 && insn
->opcode
!= xtensa_const16_opcode
))
11185 as_bad (_("invalid symbolic operand %d on '%s'"),
11186 i
, xtensa_opcode_name (isa
, insn
->opcode
));
11195 /* For assembly code with complex expressions (e.g. subtraction),
11196 we have to build them in the literal pool so that
11197 their results are calculated correctly after relaxation.
11198 The relaxation only handles expressions that
11199 boil down to SYMBOL + OFFSET. */
11202 tinsn_has_complex_operands (const TInsn
*insn
)
11205 int n
= insn
->ntok
;
11206 assert (insn
->insn_type
== ITYPE_INSN
);
11207 for (i
= 0; i
< n
; ++i
)
11209 switch (insn
->tok
[i
].X_op
)
11225 /* Convert the constant operands in the tinsn to insnbuf.
11226 Return TRUE if there is a symbol in the immediate field.
11228 Before this is called,
11229 1) the number of operands are correct
11230 2) the tinsn is a ITYPE_INSN
11231 3) ONLY the relaxable_ is built
11232 4) All operands are O_constant, O_symbol. All constants fit
11233 The return value tells whether there are any remaining O_symbols. */
11236 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
11238 static xtensa_insnbuf slotbuf
= 0;
11239 xtensa_isa isa
= xtensa_default_isa
;
11240 xtensa_opcode opcode
= tinsn
->opcode
;
11241 xtensa_format fmt
= xg_get_single_format (opcode
);
11242 bfd_boolean has_fixup
= FALSE
;
11243 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11250 slotbuf
= xtensa_insnbuf_alloc (isa
);
11252 assert (tinsn
->insn_type
== ITYPE_INSN
);
11253 if (noperands
!= tinsn
->ntok
)
11254 as_fatal (_("operand number mismatch"));
11256 if (xtensa_opcode_encode (isa
, fmt
, 0, slotbuf
, opcode
))
11257 as_fatal (_("cannot encode opcode"));
11259 for (i
= 0; i
< noperands
; ++i
)
11261 expressionS
*expr
= &tinsn
->tok
[i
];
11262 switch (expr
->X_op
)
11265 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11267 /* The register number has already been checked in
11268 expression_maybe_register, so we don't need to check here. */
11269 opnd_value
= expr
->X_add_number
;
11270 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11271 xtensa_operand_set_field (isa
, opcode
, i
, fmt
, 0,
11272 slotbuf
, opnd_value
);
11276 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11278 as_where (&file_name
, &line
);
11279 /* It is a constant and we called this function,
11280 then we have to try to fit it. */
11281 xtensa_insnbuf_set_operand (slotbuf
, fmt
, 0, opcode
, i
,
11282 expr
->X_add_number
, file_name
, line
);
11291 xtensa_format_encode (isa
, fmt
, insnbuf
);
11292 xtensa_format_set_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
11298 /* Convert the constant operands in the tinsn to slotbuf.
11299 Return TRUE if there is a symbol in the immediate field.
11300 (Eventually this should replace tinsn_to_insnbuf.) */
11302 /* Before this is called,
11303 1) the number of operands are correct
11304 2) the tinsn is a ITYPE_INSN
11305 3) ONLY the relaxable_ is built
11306 4) All operands are
11307 O_constant, O_symbol
11310 The return value tells whether there are any remaining O_symbols. */
11313 tinsn_to_slotbuf (xtensa_format fmt
,
11316 xtensa_insnbuf slotbuf
)
11318 xtensa_isa isa
= xtensa_default_isa
;
11319 xtensa_opcode opcode
= tinsn
->opcode
;
11320 bfd_boolean has_fixup
= FALSE
;
11321 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11324 *((int *) &slotbuf
[0]) = 0;
11325 *((int *) &slotbuf
[1]) = 0;
11326 assert (tinsn
->insn_type
== ITYPE_INSN
);
11327 if (noperands
!= tinsn
->ntok
)
11328 as_fatal (_("operand number mismatch"));
11330 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
11332 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
11333 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
11337 for (i
= 0; i
< noperands
; i
++)
11339 expressionS
*expr
= &tinsn
->tok
[i
];
11345 switch (expr
->X_op
)
11348 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11350 /* The register number has already been checked in
11351 expression_maybe_register, so we don't need to check here. */
11352 opnd_value
= expr
->X_add_number
;
11353 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11354 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
11357 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
11361 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11363 as_where (&file_name
, &line
);
11364 /* It is a constant and we called this function
11365 then we have to try to fit it. */
11366 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
11367 expr
->X_add_number
, file_name
, line
);
11380 /* Check the instruction arguments. Return TRUE on failure. */
11383 tinsn_check_arguments (const TInsn
*insn
)
11385 xtensa_isa isa
= xtensa_default_isa
;
11386 xtensa_opcode opcode
= insn
->opcode
;
11388 if (opcode
== XTENSA_UNDEFINED
)
11390 as_bad (_("invalid opcode"));
11394 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
11396 as_bad (_("too few operands"));
11400 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
11402 as_bad (_("too many operands"));
11409 /* Load an instruction from its encoded form. */
11412 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
11416 xg_init_vinsn (&vinsn
);
11417 vinsn_from_chars (&vinsn
, f
);
11419 *tinsn
= vinsn
.slots
[slot
];
11420 xg_free_vinsn (&vinsn
);
11425 tinsn_from_insnbuf (TInsn
*tinsn
,
11426 xtensa_insnbuf slotbuf
,
11431 xtensa_isa isa
= xtensa_default_isa
;
11433 /* Find the immed. */
11434 tinsn_init (tinsn
);
11435 tinsn
->insn_type
= ITYPE_INSN
;
11436 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
11437 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
11438 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
11439 for (i
= 0; i
< tinsn
->ntok
; i
++)
11441 set_expr_const (&tinsn
->tok
[i
],
11442 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
11443 tinsn
->opcode
, i
));
11448 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
11451 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
11453 xtensa_opcode opcode
= tinsn
->opcode
;
11456 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
11458 opnum
= get_relaxable_immed (opcode
);
11459 assert (opnum
>= 0);
11460 if (fragP
->tc_frag_data
.slot_sub_symbols
[slot
])
11462 set_expr_symbol_offset_diff
11463 (&tinsn
->tok
[opnum
],
11464 fragP
->tc_frag_data
.slot_symbols
[slot
],
11465 fragP
->tc_frag_data
.slot_sub_symbols
[slot
],
11466 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11470 set_expr_symbol_offset
11471 (&tinsn
->tok
[opnum
],
11472 fragP
->tc_frag_data
.slot_symbols
[slot
],
11473 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11480 get_num_stack_text_bytes (IStack
*istack
)
11483 int text_bytes
= 0;
11485 for (i
= 0; i
< istack
->ninsn
; i
++)
11487 TInsn
*tinsn
= &istack
->insn
[i
];
11488 if (tinsn
->insn_type
== ITYPE_INSN
)
11489 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
11496 get_num_stack_literal_bytes (IStack
*istack
)
11501 for (i
= 0; i
< istack
->ninsn
; i
++)
11503 TInsn
*tinsn
= &istack
->insn
[i
];
11504 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
11511 /* vliw_insn functions. */
11514 xg_init_vinsn (vliw_insn
*v
)
11517 xtensa_isa isa
= xtensa_default_isa
;
11519 xg_clear_vinsn (v
);
11521 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
11522 if (v
->insnbuf
== NULL
)
11523 as_fatal (_("out of memory"));
11525 for (i
= 0; i
< MAX_SLOTS
; i
++)
11527 tinsn_init (&v
->slots
[i
]);
11528 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
11529 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
11530 if (v
->slotbuf
[i
] == NULL
)
11531 as_fatal (_("out of memory"));
11537 xg_clear_vinsn (vliw_insn
*v
)
11540 v
->format
= XTENSA_UNDEFINED
;
11542 v
->inside_bundle
= FALSE
;
11544 if (xt_saved_debug_type
!= DEBUG_NONE
)
11545 debug_type
= xt_saved_debug_type
;
11547 for (i
= 0; i
< MAX_SLOTS
; i
++)
11549 memset (&v
->slots
[i
], 0, sizeof (TInsn
));
11550 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
11556 vinsn_has_specific_opcodes (vliw_insn
*v
)
11560 for (i
= 0; i
< v
->num_slots
; i
++)
11562 if (v
->slots
[i
].is_specific_opcode
)
11570 xg_free_vinsn (vliw_insn
*v
)
11573 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
11574 for (i
= 0; i
< MAX_SLOTS
; i
++)
11575 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
11579 /* Before this is called, we should have
11580 filled out the following fields:
11582 1) the number of operands for each opcode are correct
11583 2) the tinsn in the slots are ITYPE_INSN
11584 3) ONLY the relaxable_ is built
11585 4) All operands are
11586 O_constant, O_symbol
11589 The return value tells whether there are any remaining O_symbols. */
11592 vinsn_to_insnbuf (vliw_insn
*vinsn
,
11595 bfd_boolean record_fixup
)
11597 xtensa_isa isa
= xtensa_default_isa
;
11598 xtensa_format fmt
= vinsn
->format
;
11599 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
11601 bfd_boolean has_fixup
= FALSE
;
11603 xtensa_format_encode (isa
, fmt
, insnbuf
);
11605 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
11607 TInsn
*tinsn
= &vinsn
->slots
[slot
];
11608 bfd_boolean tinsn_has_fixup
=
11609 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
11610 vinsn
->slotbuf
[slot
]);
11612 xtensa_format_set_slot (isa
, fmt
, slot
,
11613 insnbuf
, vinsn
->slotbuf
[slot
]);
11614 /* tinsn_has_fixup tracks if there is a fixup at all.
11615 record_fixup controls globally. I.E., we use this
11616 function from several places, some of which are after
11617 fixups have already been recorded. Finally,
11618 tinsn->record_fixup controls based on the individual ops,
11619 which may or may not need it based on the relaxation
11621 if (tinsn_has_fixup
&& record_fixup
)
11624 xtensa_opcode opcode
= tinsn
->opcode
;
11625 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11628 for (i
= 0; i
< noperands
; i
++)
11630 expressionS
* expr
= &tinsn
->tok
[i
];
11631 switch (expr
->X_op
)
11636 if (get_relaxable_immed (opcode
) == i
)
11638 if (tinsn
->record_fix
|| expr
->X_op
!= O_symbol
)
11640 if (!xg_add_opcode_fix
11641 (tinsn
, i
, fmt
, slot
, expr
, fragP
,
11642 frag_offset
- fragP
->fr_literal
))
11643 as_bad (_("instruction with constant operands does not fit"));
11647 tinsn
->symbol
= expr
->X_add_symbol
;
11648 tinsn
->offset
= expr
->X_add_number
;
11652 as_bad (_("invalid operand %d on '%s'"),
11653 i
, xtensa_opcode_name (isa
, opcode
));
11661 if (get_relaxable_immed (opcode
) == i
)
11663 if (tinsn
->record_fix
)
11664 as_bad (_("invalid subtract operand"));
11667 tinsn
->symbol
= expr
->X_add_symbol
;
11668 tinsn
->sub_symbol
= expr
->X_op_symbol
;
11669 tinsn
->offset
= expr
->X_add_number
;
11673 as_bad (_("invalid operand %d on '%s'"),
11674 i
, xtensa_opcode_name (isa
, opcode
));
11678 as_bad (_("invalid expression for operand %d on '%s'"),
11679 i
, xtensa_opcode_name (isa
, opcode
));
11691 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
11693 static xtensa_insnbuf insnbuf
= NULL
;
11694 static xtensa_insnbuf slotbuf
= NULL
;
11697 xtensa_isa isa
= xtensa_default_isa
;
11701 insnbuf
= xtensa_insnbuf_alloc (isa
);
11702 slotbuf
= xtensa_insnbuf_alloc (isa
);
11705 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) f
, 0);
11706 fmt
= xtensa_format_decode (isa
, insnbuf
);
11707 if (fmt
== XTENSA_UNDEFINED
)
11708 as_fatal (_("cannot decode instruction format"));
11709 vinsn
->format
= fmt
;
11710 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
11712 for (i
= 0; i
< vinsn
->num_slots
; i
++)
11714 TInsn
*tinsn
= &vinsn
->slots
[i
];
11715 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
11716 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
11721 /* Expression utilities. */
11723 /* Return TRUE if the expression is an integer constant. */
11726 expr_is_const (const expressionS
*s
)
11728 return (s
->X_op
== O_constant
);
11732 /* Get the expression constant.
11733 Calling this is illegal if expr_is_const () returns TRUE. */
11736 get_expr_const (const expressionS
*s
)
11738 assert (expr_is_const (s
));
11739 return s
->X_add_number
;
11743 /* Set the expression to a constant value. */
11746 set_expr_const (expressionS
*s
, offsetT val
)
11748 s
->X_op
= O_constant
;
11749 s
->X_add_number
= val
;
11750 s
->X_add_symbol
= NULL
;
11751 s
->X_op_symbol
= NULL
;
11756 expr_is_register (const expressionS
*s
)
11758 return (s
->X_op
== O_register
);
11762 /* Get the expression constant.
11763 Calling this is illegal if expr_is_const () returns TRUE. */
11766 get_expr_register (const expressionS
*s
)
11768 assert (expr_is_register (s
));
11769 return s
->X_add_number
;
11773 /* Set the expression to a symbol + constant offset. */
11776 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
11778 s
->X_op
= O_symbol
;
11779 s
->X_add_symbol
= sym
;
11780 s
->X_op_symbol
= NULL
; /* unused */
11781 s
->X_add_number
= offset
;
11785 /* Set the expression to symbol - minus_sym + offset. */
11788 set_expr_symbol_offset_diff (expressionS
*s
,
11790 symbolS
*minus_sym
,
11793 s
->X_op
= O_subtract
;
11794 s
->X_add_symbol
= sym
;
11795 s
->X_op_symbol
= minus_sym
; /* unused */
11796 s
->X_add_number
= offset
;
11800 /* Return TRUE if the two expressions are equal. */
11803 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
11805 if (s1
->X_op
!= s2
->X_op
)
11807 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
11809 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
11811 if (s1
->X_add_number
!= s2
->X_add_number
)
11818 copy_expr (expressionS
*dst
, const expressionS
*src
)
11820 memcpy (dst
, src
, sizeof (expressionS
));
11824 /* Support for the "--rename-section" option. */
11826 struct rename_section_struct
11830 struct rename_section_struct
*next
;
11833 static struct rename_section_struct
*section_rename
;
11836 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
11837 entries to the section_rename list. Note: Specifying multiple
11838 renamings separated by colons is not documented and is retained only
11839 for backward compatibility. */
11842 build_section_rename (const char *arg
)
11844 struct rename_section_struct
*r
;
11845 char *this_arg
= NULL
;
11846 char *next_arg
= NULL
;
11848 for (this_arg
= xstrdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
11850 char *old_name
, *new_name
;
11854 next_arg
= strchr (this_arg
, ':');
11862 old_name
= this_arg
;
11863 new_name
= strchr (this_arg
, '=');
11865 if (*old_name
== '\0')
11867 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
11870 if (!new_name
|| new_name
[1] == '\0')
11872 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
11879 /* Check for invalid section renaming. */
11880 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11882 if (strcmp (r
->old_name
, old_name
) == 0)
11883 as_bad (_("section %s renamed multiple times"), old_name
);
11884 if (strcmp (r
->new_name
, new_name
) == 0)
11885 as_bad (_("multiple sections remapped to output section %s"),
11890 r
= (struct rename_section_struct
*)
11891 xmalloc (sizeof (struct rename_section_struct
));
11892 r
->old_name
= xstrdup (old_name
);
11893 r
->new_name
= xstrdup (new_name
);
11894 r
->next
= section_rename
;
11895 section_rename
= r
;
11901 xtensa_section_rename (char *name
)
11903 struct rename_section_struct
*r
= section_rename
;
11905 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11907 if (strcmp (r
->old_name
, name
) == 0)
11908 return r
->new_name
;