1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
24 #include "safe-ctype.h"
25 #include "tc-xtensa.h"
27 #include "xtensa-relax.h"
28 #include "xtensa-istack.h"
29 #include "dwarf2dbg.h"
30 #include "struc-symbol.h"
31 #include "xtensa-config.h"
34 #define uint32 unsigned int
37 #define int32 signed int
42 Naming conventions (used somewhat inconsistently):
43 The xtensa_ functions are exported
44 The xg_ functions are internal
46 We also have a couple of different extensibility mechanisms.
47 1) The idiom replacement:
48 This is used when a line is first parsed to
49 replace an instruction pattern with another instruction
50 It is currently limited to replacements of instructions
51 with constant operands.
52 2) The xtensa-relax.c mechanism that has stronger instruction
53 replacement patterns. When an instruction's immediate field
54 does not fit the next instruction sequence is attempted.
55 In addition, "narrow" opcodes are supported this way. */
58 /* Define characters with special meanings to GAS. */
59 const char comment_chars
[] = "#";
60 const char line_comment_chars
[] = "#";
61 const char line_separator_chars
[] = ";";
62 const char EXP_CHARS
[] = "eE";
63 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
66 /* Flags to indicate whether the hardware supports the density and
67 absolute literals options. */
69 bfd_boolean density_supported
= XCHAL_HAVE_DENSITY
;
70 bfd_boolean absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
72 /* Maximum width we would pad an unreachable frag to get alignment. */
73 #define UNREACHABLE_MAX_WIDTH 8
75 static vliw_insn cur_vinsn
;
77 unsigned xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
79 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
81 /* Some functions are only valid in the front end. This variable
82 allows us to assert that we haven't crossed over into the
84 static bfd_boolean past_xtensa_end
= FALSE
;
86 /* Flags for properties of the last instruction in a segment. */
87 #define FLAG_IS_A0_WRITER 0x1
88 #define FLAG_IS_BAD_LOOPEND 0x2
91 /* We define a special segment names ".literal" to place literals
92 into. The .fini and .init sections are special because they
93 contain code that is moved together by the linker. We give them
94 their own special .fini.literal and .init.literal sections. */
96 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
97 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
98 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
99 #define INIT_SECTION_NAME xtensa_section_rename (".init")
100 #define FINI_LITERAL_SECTION_NAME xtensa_section_rename (".fini.literal")
101 #define INIT_LITERAL_SECTION_NAME xtensa_section_rename (".init.literal")
104 /* This type is used for the directive_stack to keep track of the
105 state of the literal collection pools. */
107 typedef struct lit_state_struct
109 const char *lit_seg_name
;
110 const char *lit4_seg_name
;
111 const char *init_lit_seg_name
;
112 const char *fini_lit_seg_name
;
119 static lit_state default_lit_sections
;
122 /* We keep lists of literal segments. The seg_list type is the node
123 for such a list. The *_literal_head locals are the heads of the
124 various lists. All of these lists have a dummy node at the start. */
126 typedef struct seg_list_struct
128 struct seg_list_struct
*next
;
132 static seg_list literal_head_h
;
133 static seg_list
*literal_head
= &literal_head_h
;
134 static seg_list init_literal_head_h
;
135 static seg_list
*init_literal_head
= &init_literal_head_h
;
136 static seg_list fini_literal_head_h
;
137 static seg_list
*fini_literal_head
= &fini_literal_head_h
;
140 /* Lists of symbols. We keep a list of symbols that label the current
141 instruction, so that we can adjust the symbols when inserting alignment
142 for various instructions. We also keep a list of all the symbols on
143 literals, so that we can fix up those symbols when the literals are
144 later moved into the text sections. */
146 typedef struct sym_list_struct
148 struct sym_list_struct
*next
;
152 static sym_list
*insn_labels
= NULL
;
153 static sym_list
*free_insn_labels
= NULL
;
154 static sym_list
*saved_insn_labels
= NULL
;
156 static sym_list
*literal_syms
;
159 /* Flags to determine whether to prefer const16 or l32r
160 if both options are available. */
161 int prefer_const16
= 0;
164 /* Global flag to indicate when we are emitting literals. */
165 int generating_literals
= 0;
167 /* The following PROPERTY table definitions are copied from
168 <elf/xtensa.h> and must be kept in sync with the code there. */
170 /* Flags in the property tables to specify whether blocks of memory
171 are literals, instructions, data, or unreachable. For
172 instructions, blocks that begin loop targets and branch targets are
173 designated. Blocks that do not allow density, instruction
174 reordering or transformation are also specified. Finally, for
175 branch targets, branch target alignment priority is included.
176 Alignment of the next block is specified in the current block
177 and the size of the current block does not include any fill required
178 to align to the next block. */
180 #define XTENSA_PROP_LITERAL 0x00000001
181 #define XTENSA_PROP_INSN 0x00000002
182 #define XTENSA_PROP_DATA 0x00000004
183 #define XTENSA_PROP_UNREACHABLE 0x00000008
184 /* Instruction only properties at beginning of code. */
185 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
186 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
187 /* Instruction only properties about code. */
188 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
189 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
190 #define XTENSA_PROP_INSN_NO_TRANSFORM 0x00000100
192 /* Branch target alignment information. This transmits information
193 to the linker optimization about the priority of aligning a
194 particular block for branch target alignment: None, low priority,
195 high priority, or required. These only need to be checked in
196 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
199 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
200 case XTENSA_PROP_BT_ALIGN_NONE:
201 case XTENSA_PROP_BT_ALIGN_LOW:
202 case XTENSA_PROP_BT_ALIGN_HIGH:
203 case XTENSA_PROP_BT_ALIGN_REQUIRE:
205 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
207 /* No branch target alignment. */
208 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
209 /* Low priority branch target alignment. */
210 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
211 /* High priority branch target alignment. */
212 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
213 /* Required branch target alignment. */
214 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
216 #define GET_XTENSA_PROP_BT_ALIGN(flag) \
217 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
218 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
219 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
220 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
223 /* Alignment is specified in the block BEFORE the one that needs
224 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
225 get the required alignment specified as a power of 2. Use
226 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
227 alignment. Be careful of side effects since the SET will evaluate
228 flags twice. Also, note that the SIZE of a block in the property
229 table does not include the alignment size, so the alignment fill
230 must be calculated to determine if two blocks are contiguous.
231 TEXT_ALIGN is not currently implemented but is a placeholder for a
232 possible future implementation. */
234 #define XTENSA_PROP_ALIGN 0x00000800
236 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
238 #define GET_XTENSA_PROP_ALIGNMENT(flag) \
239 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
240 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
241 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
242 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
244 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
247 /* Structure for saving instruction and alignment per-fragment data
248 that will be written to the object file. This structure is
249 equivalent to the actual data that will be written out to the file
250 but is easier to use. We provide a conversion to file flags
251 in frag_flags_to_number. */
253 typedef struct frag_flags_struct frag_flags
;
255 struct frag_flags_struct
257 /* is_literal should only be used after xtensa_move_literals.
258 If you need to check if you are generating a literal fragment,
259 then use the generating_literals global. */
261 unsigned is_literal
: 1;
262 unsigned is_insn
: 1;
263 unsigned is_data
: 1;
264 unsigned is_unreachable
: 1;
268 unsigned is_loop_target
: 1;
269 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
270 unsigned bt_align_priority
: 2;
272 unsigned is_no_density
: 1;
273 /* no_longcalls flag does not need to be placed in the object file. */
274 /* is_specific_opcode implies no_transform. */
275 unsigned is_no_transform
: 1;
277 unsigned is_no_reorder
: 1;
279 /* Uses absolute literal addressing for l32r. */
280 unsigned is_abslit
: 1;
282 unsigned is_align
: 1;
283 unsigned alignment
: 5;
287 /* Structure for saving information about a block of property data
288 for frags that have the same flags. */
289 struct xtensa_block_info_struct
295 struct xtensa_block_info_struct
*next
;
299 /* Structure for saving the current state before emitting literals. */
300 typedef struct emit_state_struct
305 int generating_literals
;
309 /* Opcode placement information */
311 typedef unsigned long long bitfield
;
312 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
313 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
314 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
316 #define MAX_FORMATS 32
318 typedef struct op_placement_info_struct
321 /* A number describing how restrictive the issue is for this
322 opcode. For example, an opcode that fits lots of different
323 formats has a high freedom, as does an opcode that fits
324 only one format but many slots in that format. The most
325 restrictive is the opcode that fits only one slot in one
328 xtensa_format narrowest
;
332 /* formats is a bitfield with the Nth bit set
333 if the opcode fits in the Nth xtensa_format. */
336 /* slots[N]'s Mth bit is set if the op fits in the
337 Mth slot of the Nth xtensa_format. */
338 bitfield slots
[MAX_FORMATS
];
340 /* A count of the number of slots in a given format
341 an op can fit (i.e., the bitcount of the slot field above). */
342 char slots_in_format
[MAX_FORMATS
];
344 } op_placement_info
, *op_placement_info_table
;
346 op_placement_info_table op_placement_table
;
349 /* Extra expression types. */
351 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
352 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
353 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
366 directive_literal_prefix
,
368 directive_absolute_literals
,
369 directive_last_directive
375 bfd_boolean can_be_negated
;
378 const directive_infoS directive_info
[] =
381 { "literal", FALSE
},
383 { "transform", TRUE
},
384 { "freeregs", FALSE
},
385 { "longcalls", TRUE
},
386 { "literal_prefix", FALSE
},
387 { "schedule", TRUE
},
388 { "absolute-literals", TRUE
}
391 bfd_boolean directive_state
[] =
395 #if !XCHAL_HAVE_DENSITY
400 TRUE
, /* transform */
401 FALSE
, /* freeregs */
402 FALSE
, /* longcalls */
403 FALSE
, /* literal_prefix */
405 #if XSHAL_USE_ABSOLUTE_LITERALS
406 TRUE
/* absolute_literals */
408 FALSE
/* absolute_literals */
413 /* Directive functions. */
415 static void xtensa_begin_directive (int);
416 static void xtensa_end_directive (int);
417 static void xtensa_literal_prefix (char const *, int);
418 static void xtensa_literal_position (int);
419 static void xtensa_literal_pseudo (int);
420 static void xtensa_frequency_pseudo (int);
421 static void xtensa_elf_cons (int);
423 /* Parsing and Idiom Translation. */
425 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
427 /* Various Other Internal Functions. */
429 extern bfd_boolean
xg_is_single_relaxable_insn (TInsn
*, TInsn
*, bfd_boolean
);
430 static bfd_boolean
xg_build_to_insn (TInsn
*, TInsn
*, BuildInstr
*);
431 static void xtensa_mark_literal_pool_location (void);
432 static addressT
get_expanded_loop_offset (xtensa_opcode
);
433 static fragS
*get_literal_pool_location (segT
);
434 static void set_literal_pool_location (segT
, fragS
*);
435 static void xtensa_set_frag_assembly_state (fragS
*);
436 static void finish_vinsn (vliw_insn
*);
437 static bfd_boolean
emit_single_op (TInsn
*);
438 static int total_frag_text_expansion (fragS
*);
440 /* Alignment Functions. */
442 static int get_text_align_power (unsigned);
443 static int get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
444 static int branch_align_power (segT
);
446 /* Helpers for xtensa_relax_frag(). */
448 static long relax_frag_add_nop (fragS
*);
450 /* Accessors for additional per-subsegment information. */
452 static unsigned get_last_insn_flags (segT
, subsegT
);
453 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
454 static float get_subseg_total_freq (segT
, subsegT
);
455 static float get_subseg_target_freq (segT
, subsegT
);
456 static void set_subseg_freq (segT
, subsegT
, float, float);
458 /* Segment list functions. */
460 static void xtensa_move_literals (void);
461 static void xtensa_reorder_segments (void);
462 static void xtensa_switch_to_literal_fragment (emit_state
*);
463 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
464 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
465 static void xtensa_restore_emit_state (emit_state
*);
466 static void cache_literal_section
467 (seg_list
*, const char *, segT
*, bfd_boolean
);
469 /* Import from elf32-xtensa.c in BFD library. */
471 extern char *xtensa_get_property_section_name (asection
*, const char *);
473 /* op_placement_info functions. */
475 static void init_op_placement_info_table (void);
476 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
477 static int xg_get_single_size (xtensa_opcode
);
478 static xtensa_format
xg_get_single_format (xtensa_opcode
);
479 static int xg_get_single_slot (xtensa_opcode
);
481 /* TInsn and IStack functions. */
483 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
484 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
485 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
486 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
487 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
488 static void tinsn_from_chars (TInsn
*, char *, int);
489 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
490 static int get_num_stack_text_bytes (IStack
*);
491 static int get_num_stack_literal_bytes (IStack
*);
493 /* vliw_insn functions. */
495 static void xg_init_vinsn (vliw_insn
*);
496 static void xg_clear_vinsn (vliw_insn
*);
497 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
498 static void xg_free_vinsn (vliw_insn
*);
499 static bfd_boolean vinsn_to_insnbuf
500 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
501 static void vinsn_from_chars (vliw_insn
*, char *);
503 /* Expression Utilities. */
505 bfd_boolean
expr_is_const (const expressionS
*);
506 offsetT
get_expr_const (const expressionS
*);
507 void set_expr_const (expressionS
*, offsetT
);
508 bfd_boolean
expr_is_register (const expressionS
*);
509 offsetT
get_expr_register (const expressionS
*);
510 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
511 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
512 static void copy_expr (expressionS
*, const expressionS
*);
514 /* Section renaming. */
516 static void build_section_rename (const char *);
519 /* ISA imported from bfd. */
520 extern xtensa_isa xtensa_default_isa
;
522 extern int target_big_endian
;
524 static xtensa_opcode xtensa_addi_opcode
;
525 static xtensa_opcode xtensa_addmi_opcode
;
526 static xtensa_opcode xtensa_call0_opcode
;
527 static xtensa_opcode xtensa_call4_opcode
;
528 static xtensa_opcode xtensa_call8_opcode
;
529 static xtensa_opcode xtensa_call12_opcode
;
530 static xtensa_opcode xtensa_callx0_opcode
;
531 static xtensa_opcode xtensa_callx4_opcode
;
532 static xtensa_opcode xtensa_callx8_opcode
;
533 static xtensa_opcode xtensa_callx12_opcode
;
534 static xtensa_opcode xtensa_const16_opcode
;
535 static xtensa_opcode xtensa_entry_opcode
;
536 static xtensa_opcode xtensa_movi_opcode
;
537 static xtensa_opcode xtensa_movi_n_opcode
;
538 static xtensa_opcode xtensa_isync_opcode
;
539 static xtensa_opcode xtensa_jx_opcode
;
540 static xtensa_opcode xtensa_l32r_opcode
;
541 static xtensa_opcode xtensa_loop_opcode
;
542 static xtensa_opcode xtensa_loopnez_opcode
;
543 static xtensa_opcode xtensa_loopgtz_opcode
;
544 static xtensa_opcode xtensa_nop_opcode
;
545 static xtensa_opcode xtensa_nop_n_opcode
;
546 static xtensa_opcode xtensa_or_opcode
;
547 static xtensa_opcode xtensa_ret_opcode
;
548 static xtensa_opcode xtensa_ret_n_opcode
;
549 static xtensa_opcode xtensa_retw_opcode
;
550 static xtensa_opcode xtensa_retw_n_opcode
;
551 static xtensa_opcode xtensa_rsr_lcount_opcode
;
552 static xtensa_opcode xtensa_waiti_opcode
;
555 /* Command-line Options. */
557 bfd_boolean use_literal_section
= TRUE
;
558 static bfd_boolean align_targets
= TRUE
;
559 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
560 static bfd_boolean has_a0_b_retw
= FALSE
;
561 static bfd_boolean workaround_a0_b_retw
= FALSE
;
562 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
563 static bfd_boolean workaround_short_loop
= FALSE
;
564 static bfd_boolean maybe_has_short_loop
= FALSE
;
565 static bfd_boolean workaround_close_loop_end
= FALSE
;
566 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
567 static bfd_boolean enforce_three_byte_loop_align
= FALSE
;
569 /* When workaround_short_loops is TRUE, all loops with early exits must
570 have at least 3 instructions. workaround_all_short_loops is a modifier
571 to the workaround_short_loop flag. In addition to the
572 workaround_short_loop actions, all straightline loopgtz and loopnez
573 must have at least 3 instructions. */
575 static bfd_boolean workaround_all_short_loops
= FALSE
;
579 xtensa_setup_hw_workarounds (int earliest
, int latest
)
581 if (earliest
> latest
)
582 as_fatal (_("illegal range of target hardware versions"));
584 /* Enable all workarounds for pre-T1050.0 hardware. */
585 if (earliest
< 105000 || latest
< 105000)
587 workaround_a0_b_retw
|= TRUE
;
588 workaround_b_j_loop_end
|= TRUE
;
589 workaround_short_loop
|= TRUE
;
590 workaround_close_loop_end
|= TRUE
;
591 workaround_all_short_loops
|= TRUE
;
592 enforce_three_byte_loop_align
= TRUE
;
599 option_density
= OPTION_MD_BASE
,
606 option_no_link_relax
,
614 option_text_section_literals
,
615 option_no_text_section_literals
,
617 option_absolute_literals
,
618 option_no_absolute_literals
,
620 option_align_targets
,
621 option_no_align_targets
,
623 option_warn_unaligned_targets
,
628 option_workaround_a0_b_retw
,
629 option_no_workaround_a0_b_retw
,
631 option_workaround_b_j_loop_end
,
632 option_no_workaround_b_j_loop_end
,
634 option_workaround_short_loop
,
635 option_no_workaround_short_loop
,
637 option_workaround_all_short_loops
,
638 option_no_workaround_all_short_loops
,
640 option_workaround_close_loop_end
,
641 option_no_workaround_close_loop_end
,
643 option_no_workarounds
,
645 option_rename_section_name
,
648 option_prefer_const16
,
650 option_target_hardware
653 const char *md_shortopts
= "";
655 struct option md_longopts
[] =
657 { "density", no_argument
, NULL
, option_density
},
658 { "no-density", no_argument
, NULL
, option_no_density
},
660 /* Both "relax" and "generics" are deprecated and treated as equivalent
661 to the "transform" option. */
662 { "relax", no_argument
, NULL
, option_relax
},
663 { "no-relax", no_argument
, NULL
, option_no_relax
},
664 { "generics", no_argument
, NULL
, option_generics
},
665 { "no-generics", no_argument
, NULL
, option_no_generics
},
667 { "transform", no_argument
, NULL
, option_transform
},
668 { "no-transform", no_argument
, NULL
, option_no_transform
},
669 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
670 { "no-text-section-literals", no_argument
, NULL
,
671 option_no_text_section_literals
},
672 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
673 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
674 /* This option was changed from -align-target to -target-align
675 because it conflicted with the "-al" option. */
676 { "target-align", no_argument
, NULL
, option_align_targets
},
677 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
678 { "warn-unaligned-targets", no_argument
, NULL
,
679 option_warn_unaligned_targets
},
680 { "longcalls", no_argument
, NULL
, option_longcalls
},
681 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
683 { "no-workaround-a0-b-retw", no_argument
, NULL
,
684 option_no_workaround_a0_b_retw
},
685 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
687 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
688 option_no_workaround_b_j_loop_end
},
689 { "workaround-b-j-loop-end", no_argument
, NULL
,
690 option_workaround_b_j_loop_end
},
692 { "no-workaround-short-loops", no_argument
, NULL
,
693 option_no_workaround_short_loop
},
694 { "workaround-short-loops", no_argument
, NULL
,
695 option_workaround_short_loop
},
697 { "no-workaround-all-short-loops", no_argument
, NULL
,
698 option_no_workaround_all_short_loops
},
699 { "workaround-all-short-loop", no_argument
, NULL
,
700 option_workaround_all_short_loops
},
702 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
703 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
705 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
707 { "no-workaround-close-loop-end", no_argument
, NULL
,
708 option_no_workaround_close_loop_end
},
709 { "workaround-close-loop-end", no_argument
, NULL
,
710 option_workaround_close_loop_end
},
712 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
714 { "link-relax", no_argument
, NULL
, option_link_relax
},
715 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
717 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
719 { NULL
, no_argument
, NULL
, 0 }
722 size_t md_longopts_size
= sizeof md_longopts
;
726 md_parse_option (int c
, char *arg
)
731 as_warn (_("--density option is ignored"));
733 case option_no_density
:
734 as_warn (_("--no-density option is ignored"));
736 case option_link_relax
:
739 case option_no_link_relax
:
742 case option_generics
:
743 as_warn (_("--generics is deprecated; use --transform instead"));
744 return md_parse_option (option_transform
, arg
);
745 case option_no_generics
:
746 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
747 return md_parse_option (option_no_transform
, arg
);
749 as_warn (_("--relax is deprecated; use --transform instead"));
750 return md_parse_option (option_transform
, arg
);
751 case option_no_relax
:
752 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
753 return md_parse_option (option_no_transform
, arg
);
754 case option_longcalls
:
755 directive_state
[directive_longcalls
] = TRUE
;
757 case option_no_longcalls
:
758 directive_state
[directive_longcalls
] = FALSE
;
760 case option_text_section_literals
:
761 use_literal_section
= FALSE
;
763 case option_no_text_section_literals
:
764 use_literal_section
= TRUE
;
766 case option_absolute_literals
:
767 if (!absolute_literals_supported
)
769 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
772 directive_state
[directive_absolute_literals
] = TRUE
;
774 case option_no_absolute_literals
:
775 directive_state
[directive_absolute_literals
] = FALSE
;
778 case option_workaround_a0_b_retw
:
779 workaround_a0_b_retw
= TRUE
;
781 case option_no_workaround_a0_b_retw
:
782 workaround_a0_b_retw
= FALSE
;
784 case option_workaround_b_j_loop_end
:
785 workaround_b_j_loop_end
= TRUE
;
787 case option_no_workaround_b_j_loop_end
:
788 workaround_b_j_loop_end
= FALSE
;
791 case option_workaround_short_loop
:
792 workaround_short_loop
= TRUE
;
794 case option_no_workaround_short_loop
:
795 workaround_short_loop
= FALSE
;
798 case option_workaround_all_short_loops
:
799 workaround_all_short_loops
= TRUE
;
801 case option_no_workaround_all_short_loops
:
802 workaround_all_short_loops
= FALSE
;
805 case option_workaround_close_loop_end
:
806 workaround_close_loop_end
= TRUE
;
808 case option_no_workaround_close_loop_end
:
809 workaround_close_loop_end
= FALSE
;
812 case option_no_workarounds
:
813 workaround_a0_b_retw
= FALSE
;
814 workaround_b_j_loop_end
= FALSE
;
815 workaround_short_loop
= FALSE
;
816 workaround_all_short_loops
= FALSE
;
817 workaround_close_loop_end
= FALSE
;
820 case option_align_targets
:
821 align_targets
= TRUE
;
823 case option_no_align_targets
:
824 align_targets
= FALSE
;
827 case option_warn_unaligned_targets
:
828 warn_unaligned_branch_targets
= TRUE
;
831 case option_rename_section_name
:
832 build_section_rename (arg
);
836 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
837 should be emitted or not. FIXME: Not implemented. */
840 case option_prefer_l32r
:
842 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
846 case option_prefer_const16
:
848 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
852 case option_target_hardware
:
854 int earliest
, latest
= 0;
855 if (*arg
== 0 || *arg
== '-')
856 as_fatal (_("invalid target hardware version"));
858 earliest
= strtol (arg
, &arg
, 0);
862 else if (*arg
== '-')
865 as_fatal (_("invalid target hardware version"));
866 latest
= strtol (arg
, &arg
, 0);
869 as_fatal (_("invalid target hardware version"));
871 xtensa_setup_hw_workarounds (earliest
, latest
);
875 case option_transform
:
876 /* This option has no affect other than to use the defaults,
877 which are already set. */
880 case option_no_transform
:
881 /* This option turns off all transformations of any kind.
882 However, because we want to preserve the state of other
883 directives, we only change its own field. Thus, before
884 you perform any transformation, always check if transform
885 is available. If you use the functions we provide for this
886 purpose, you will be ok. */
887 directive_state
[directive_transform
] = FALSE
;
897 md_show_usage (FILE *stream
)
901 --[no-]text-section-literals\n\
902 [Do not] put literals in the text section\n\
903 --[no-]absolute-literals\n\
904 [Do not] default to use non-PC-relative literals\n\
905 --[no-]target-align [Do not] try to align branch targets\n\
906 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
907 --[no-]transform [Do not] transform instructions\n\
908 --rename-section old=new Rename section 'old' to 'new'\n", stream
);
912 /* Functions related to the list of current label symbols. */
915 xtensa_add_insn_label (symbolS
*sym
)
919 if (!free_insn_labels
)
920 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
923 l
= free_insn_labels
;
924 free_insn_labels
= l
->next
;
928 l
->next
= insn_labels
;
934 xtensa_clear_insn_labels (void)
938 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
945 /* The "loops_ok" argument is provided to allow ignoring labels that
946 define loop ends. This fixes a bug where the NOPs to align a
947 loop opcode were included in a previous zero-cost loop:
966 This argument is used to prevent moving the NOP to before the
967 loop-end label, which is what you want in this special case. */
970 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
, bfd_boolean loops_ok
)
974 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
976 symbolS
*lit_sym
= lit
->sym
;
977 if (loops_ok
|| ! symbol_get_tc (lit_sym
)->is_loop_target
)
979 S_SET_VALUE (lit_sym
, new_offset
);
980 symbol_set_frag (lit_sym
, new_frag
);
986 /* Directive data and functions. */
988 typedef struct state_stackS_struct
990 directiveE directive
;
992 bfd_boolean old_state
;
996 struct state_stackS_struct
*prev
;
999 state_stackS
*directive_state_stack
;
1001 const pseudo_typeS md_pseudo_table
[] =
1003 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
1004 { "literal_position", xtensa_literal_position
, 0 },
1005 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
1006 { "long", xtensa_elf_cons
, 4 },
1007 { "word", xtensa_elf_cons
, 4 },
1008 { "short", xtensa_elf_cons
, 2 },
1009 { "begin", xtensa_begin_directive
, 0 },
1010 { "end", xtensa_end_directive
, 0 },
1011 { "literal", xtensa_literal_pseudo
, 0 },
1012 { "frequency", xtensa_frequency_pseudo
, 0 },
1018 use_transform (void)
1020 /* After md_end, you should be checking frag by frag, rather
1021 than state directives. */
1022 assert (!past_xtensa_end
);
1023 return directive_state
[directive_transform
];
1028 do_align_targets (void)
1030 /* Do not use this function after md_end; just look at align_targets
1031 instead. There is no target-align directive, so alignment is either
1032 enabled for all frags or not done at all. */
1033 assert (!past_xtensa_end
);
1034 return align_targets
&& use_transform ();
1039 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1043 state_stackS
*stack
= (state_stackS
*) xmalloc (sizeof (state_stackS
));
1045 as_where (&file
, &line
);
1047 stack
->directive
= directive
;
1048 stack
->negated
= negated
;
1049 stack
->old_state
= directive_state
[directive
];
1052 stack
->datum
= datum
;
1053 stack
->prev
= directive_state_stack
;
1054 directive_state_stack
= stack
;
1056 directive_state
[directive
] = !negated
;
1061 directive_pop (directiveE
*directive
,
1062 bfd_boolean
*negated
,
1067 state_stackS
*top
= directive_state_stack
;
1069 if (!directive_state_stack
)
1071 as_bad (_("unmatched end directive"));
1072 *directive
= directive_none
;
1076 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1077 *directive
= top
->directive
;
1078 *negated
= top
->negated
;
1081 *datum
= top
->datum
;
1082 directive_state_stack
= top
->prev
;
1088 directive_balance (void)
1090 while (directive_state_stack
)
1092 directiveE directive
;
1093 bfd_boolean negated
;
1098 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1099 as_warn_where ((char *) file
, line
,
1100 _(".begin directive with no matching .end directive"));
1106 inside_directive (directiveE dir
)
1108 state_stackS
*top
= directive_state_stack
;
1110 while (top
&& top
->directive
!= dir
)
1113 return (top
!= NULL
);
1118 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1122 char *directive_string
;
1124 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1129 input_line_pointer
+= 3;
1132 len
= strspn (input_line_pointer
,
1133 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1135 /* This code is a hack to make .begin [no-][generics|relax] exactly
1136 equivalent to .begin [no-]transform. We should remove it when
1137 we stop accepting those options. */
1139 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1141 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1142 directive_string
= "transform";
1144 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1146 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1147 directive_string
= "transform";
1150 directive_string
= input_line_pointer
;
1152 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1154 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1156 input_line_pointer
+= len
;
1157 *directive
= (directiveE
) i
;
1158 if (*negated
&& !directive_info
[i
].can_be_negated
)
1159 as_bad (_("directive %s cannot be negated"),
1160 directive_info
[i
].name
);
1165 as_bad (_("unknown directive"));
1166 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1171 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1173 directiveE directive
;
1174 bfd_boolean negated
;
1179 get_directive (&directive
, &negated
);
1180 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1182 discard_rest_of_line ();
1186 if (cur_vinsn
.inside_bundle
)
1187 as_bad (_("directives are not valid inside bundles"));
1191 case directive_literal
:
1192 if (!inside_directive (directive_literal
))
1194 /* Previous labels go with whatever follows this directive, not with
1195 the literal, so save them now. */
1196 saved_insn_labels
= insn_labels
;
1199 as_warn (_(".begin literal is deprecated; use .literal instead"));
1200 state
= (emit_state
*) xmalloc (sizeof (emit_state
));
1201 xtensa_switch_to_literal_fragment (state
);
1202 directive_push (directive_literal
, negated
, state
);
1205 case directive_literal_prefix
:
1206 /* Have to flush pending output because a movi relaxed to an l32r
1207 might produce a literal. */
1208 md_flush_pending_output ();
1209 /* Check to see if the current fragment is a literal
1210 fragment. If it is, then this operation is not allowed. */
1211 if (generating_literals
)
1213 as_bad (_("cannot set literal_prefix inside literal fragment"));
1217 /* Allocate the literal state for this section and push
1218 onto the directive stack. */
1219 ls
= xmalloc (sizeof (lit_state
));
1222 *ls
= default_lit_sections
;
1224 directive_push (directive_literal_prefix
, negated
, ls
);
1226 /* Parse the new prefix from the input_line_pointer. */
1228 len
= strspn (input_line_pointer
,
1229 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1230 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1232 /* Process the new prefix. */
1233 xtensa_literal_prefix (input_line_pointer
, len
);
1235 /* Skip the name in the input line. */
1236 input_line_pointer
+= len
;
1239 case directive_freeregs
:
1240 /* This information is currently unused, but we'll accept the statement
1241 and just discard the rest of the line. This won't check the syntax,
1242 but it will accept every correct freeregs directive. */
1243 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1244 directive_push (directive_freeregs
, negated
, 0);
1247 case directive_schedule
:
1248 md_flush_pending_output ();
1249 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1250 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1251 directive_push (directive_schedule
, negated
, 0);
1252 xtensa_set_frag_assembly_state (frag_now
);
1255 case directive_density
:
1256 as_warn (_(".begin [no-]density is ignored"));
1259 case directive_absolute_literals
:
1260 md_flush_pending_output ();
1261 if (!absolute_literals_supported
&& !negated
)
1263 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1266 xtensa_set_frag_assembly_state (frag_now
);
1267 directive_push (directive
, negated
, 0);
1271 md_flush_pending_output ();
1272 xtensa_set_frag_assembly_state (frag_now
);
1273 directive_push (directive
, negated
, 0);
1277 demand_empty_rest_of_line ();
1282 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1284 directiveE begin_directive
, end_directive
;
1285 bfd_boolean begin_negated
, end_negated
;
1289 emit_state
**state_ptr
;
1292 if (cur_vinsn
.inside_bundle
)
1293 as_bad (_("directives are not valid inside bundles"));
1295 get_directive (&end_directive
, &end_negated
);
1297 md_flush_pending_output ();
1299 switch (end_directive
)
1301 case (directiveE
) XTENSA_UNDEFINED
:
1302 discard_rest_of_line ();
1305 case directive_density
:
1306 as_warn (_(".end [no-]density is ignored"));
1307 demand_empty_rest_of_line ();
1310 case directive_absolute_literals
:
1311 if (!absolute_literals_supported
&& !end_negated
)
1313 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1314 demand_empty_rest_of_line ();
1323 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1324 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1325 (const void **) state_ptr
);
1327 if (begin_directive
!= directive_none
)
1329 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1331 as_bad (_("does not match begin %s%s at %s:%d"),
1332 begin_negated
? "no-" : "",
1333 directive_info
[begin_directive
].name
, file
, line
);
1337 switch (end_directive
)
1339 case directive_literal
:
1340 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1341 xtensa_restore_emit_state (state
);
1342 xtensa_set_frag_assembly_state (frag_now
);
1344 if (!inside_directive (directive_literal
))
1346 /* Restore the list of current labels. */
1347 xtensa_clear_insn_labels ();
1348 insn_labels
= saved_insn_labels
;
1352 case directive_literal_prefix
:
1353 /* Restore the default collection sections from saved state. */
1354 s
= (lit_state
*) state
;
1357 default_lit_sections
= *s
;
1359 /* free the state storage */
1363 case directive_schedule
:
1364 case directive_freeregs
:
1368 xtensa_set_frag_assembly_state (frag_now
);
1374 demand_empty_rest_of_line ();
1378 /* Place an aligned literal fragment at the current location. */
1381 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1383 md_flush_pending_output ();
1385 if (inside_directive (directive_literal
))
1386 as_warn (_(".literal_position inside literal directive; ignoring"));
1387 xtensa_mark_literal_pool_location ();
1389 demand_empty_rest_of_line ();
1390 xtensa_clear_insn_labels ();
1394 /* Support .literal label, expr, ... */
1397 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1400 char *p
, *base_name
;
1404 if (inside_directive (directive_literal
))
1406 as_bad (_(".literal not allowed inside .begin literal region"));
1407 ignore_rest_of_line ();
1411 md_flush_pending_output ();
1413 /* Previous labels go with whatever follows this directive, not with
1414 the literal, so save them now. */
1415 saved_insn_labels
= insn_labels
;
1418 /* If we are using text-section literals, then this is the right value... */
1421 base_name
= input_line_pointer
;
1423 xtensa_switch_to_literal_fragment (&state
);
1425 /* ...but if we aren't using text-section-literals, then we
1426 need to put them in the section we just switched to. */
1427 if (use_literal_section
|| directive_state
[directive_absolute_literals
])
1430 /* All literals are aligned to four-byte boundaries. */
1431 frag_align (2, 0, 0);
1432 record_alignment (now_seg
, 2);
1434 c
= get_symbol_end ();
1435 /* Just after name is now '\0'. */
1436 p
= input_line_pointer
;
1440 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1442 as_bad (_("expected comma or colon after symbol name; "
1443 "rest of line ignored"));
1444 ignore_rest_of_line ();
1445 xtensa_restore_emit_state (&state
);
1453 input_line_pointer
++; /* skip ',' or ':' */
1455 xtensa_elf_cons (4);
1457 xtensa_restore_emit_state (&state
);
1459 /* Restore the list of current labels. */
1460 xtensa_clear_insn_labels ();
1461 insn_labels
= saved_insn_labels
;
1466 xtensa_literal_prefix (char const *start
, int len
)
1468 char *name
, *linkonce_suffix
;
1469 char *newname
, *newname4
;
1470 size_t linkonce_len
;
1472 /* Get a null-terminated copy of the name. */
1473 name
= xmalloc (len
+ 1);
1476 strncpy (name
, start
, len
);
1479 /* Allocate the sections (interesting note: the memory pointing to
1480 the name is actually used for the name by the new section). */
1482 newname
= xmalloc (len
+ strlen (".literal") + 1);
1483 newname4
= xmalloc (len
+ strlen (".lit4") + 1);
1485 linkonce_len
= sizeof (".gnu.linkonce.") - 1;
1486 if (strncmp (name
, ".gnu.linkonce.", linkonce_len
) == 0
1487 && (linkonce_suffix
= strchr (name
+ linkonce_len
, '.')) != 0)
1489 strcpy (newname
, ".gnu.linkonce.literal");
1490 strcpy (newname4
, ".gnu.linkonce.lit4");
1492 strcat (newname
, linkonce_suffix
);
1493 strcat (newname4
, linkonce_suffix
);
1497 int suffix_pos
= len
;
1499 /* If the section name ends with ".text", then replace that suffix
1500 instead of appending an additional suffix. */
1501 if (len
>= 5 && strcmp (name
+ len
- 5, ".text") == 0)
1504 strcpy (newname
, name
);
1505 strcpy (newname4
, name
);
1507 strcpy (newname
+ suffix_pos
, ".literal");
1508 strcpy (newname4
+ suffix_pos
, ".lit4");
1511 /* Note that cache_literal_section does not create a segment if
1512 it already exists. */
1513 default_lit_sections
.lit_seg
= NULL
;
1514 default_lit_sections
.lit4_seg
= NULL
;
1516 /* Canonicalizing section names allows renaming literal
1517 sections to occur correctly. */
1518 default_lit_sections
.lit_seg_name
= tc_canonicalize_symbol_name (newname
);
1519 default_lit_sections
.lit4_seg_name
= tc_canonicalize_symbol_name (newname4
);
1525 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1528 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1530 float fall_through_f
, target_f
;
1532 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1533 if (fall_through_f
< 0)
1535 as_bad (_("fall through frequency must be greater than 0"));
1536 ignore_rest_of_line ();
1540 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1543 as_bad (_("branch target frequency must be greater than 0"));
1544 ignore_rest_of_line ();
1548 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1550 demand_empty_rest_of_line ();
1554 /* Like normal .long/.short/.word, except support @plt, etc.
1555 Clobbers input_line_pointer, checks end-of-line. */
1558 xtensa_elf_cons (int nbytes
)
1561 bfd_reloc_code_real_type reloc
;
1563 md_flush_pending_output ();
1565 if (cur_vinsn
.inside_bundle
)
1566 as_bad (_("directives are not valid inside bundles"));
1568 if (is_it_end_of_statement ())
1570 demand_empty_rest_of_line ();
1577 if (exp
.X_op
== O_symbol
1578 && *input_line_pointer
== '@'
1579 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1582 reloc_howto_type
*reloc_howto
=
1583 bfd_reloc_type_lookup (stdoutput
, reloc
);
1585 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1586 as_bad (_("unsupported relocation"));
1587 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1588 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1589 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1590 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1591 as_bad (_("opcode-specific %s relocation used outside "
1592 "an instruction"), reloc_howto
->name
);
1593 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1594 as_bad (_("%s relocations do not fit in %d bytes"),
1595 reloc_howto
->name
, nbytes
);
1598 char *p
= frag_more ((int) nbytes
);
1599 xtensa_set_frag_assembly_state (frag_now
);
1600 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1601 nbytes
, &exp
, 0, reloc
);
1605 emit_expr (&exp
, (unsigned int) nbytes
);
1607 while (*input_line_pointer
++ == ',');
1609 input_line_pointer
--; /* Put terminator back into stream. */
1610 demand_empty_rest_of_line ();
1614 /* Parsing and Idiom Translation. */
1616 /* Parse @plt, etc. and return the desired relocation. */
1617 static bfd_reloc_code_real_type
1618 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1624 bfd_reloc_code_real_type reloc
;
1632 struct map_bfd
*ptr
;
1634 #define MAP(str,reloc) { str, sizeof (str) - 1, reloc }
1636 static struct map_bfd mapping
[] =
1638 MAP ("l", BFD_RELOC_LO16
),
1639 MAP ("h", BFD_RELOC_HI16
),
1640 MAP ("plt", BFD_RELOC_XTENSA_PLT
),
1641 { (char *) 0, 0, BFD_RELOC_UNUSED
}
1645 return BFD_RELOC_NONE
;
1647 for (ch
= *str
, str2
= ident
;
1648 (str2
< ident
+ sizeof (ident
) - 1
1649 && (ISALNUM (ch
) || ch
== '@'));
1652 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1659 for (ptr
= &mapping
[0]; ptr
->length
> 0; ptr
++)
1660 if (ch
== ptr
->string
[0]
1661 && len
== ptr
->length
1662 && memcmp (ident
, ptr
->string
, ptr
->length
) == 0)
1664 /* Now check for "identifier@suffix+constant". */
1665 if (*str
== '-' || *str
== '+')
1667 char *orig_line
= input_line_pointer
;
1668 expressionS new_exp
;
1670 input_line_pointer
= str
;
1671 expression (&new_exp
);
1672 if (new_exp
.X_op
== O_constant
)
1674 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1675 str
= input_line_pointer
;
1678 if (&input_line_pointer
!= str_p
)
1679 input_line_pointer
= orig_line
;
1686 return BFD_RELOC_UNUSED
;
1691 expression_end (const char *name
)
1714 #define ERROR_REG_NUM ((unsigned) -1)
1717 tc_get_register (const char *prefix
)
1720 const char *next_expr
;
1721 const char *old_line_pointer
;
1724 old_line_pointer
= input_line_pointer
;
1726 if (*input_line_pointer
== '$')
1727 ++input_line_pointer
;
1729 /* Accept "sp" as a synonym for "a1". */
1730 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1731 && expression_end (input_line_pointer
+ 2))
1733 input_line_pointer
+= 2;
1734 return 1; /* AR[1] */
1737 while (*input_line_pointer
++ == *prefix
++)
1739 --input_line_pointer
;
1744 as_bad (_("bad register name: %s"), old_line_pointer
);
1745 return ERROR_REG_NUM
;
1748 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1750 as_bad (_("bad register number: %s"), input_line_pointer
);
1751 return ERROR_REG_NUM
;
1756 while (ISDIGIT ((int) *input_line_pointer
))
1757 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1759 if (!(next_expr
= expression_end (input_line_pointer
)))
1761 as_bad (_("bad register name: %s"), old_line_pointer
);
1762 return ERROR_REG_NUM
;
1765 input_line_pointer
= (char *) next_expr
;
1772 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1774 xtensa_isa isa
= xtensa_default_isa
;
1776 /* Check if this is an immediate operand. */
1777 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1779 bfd_reloc_code_real_type reloc
;
1780 segT t
= expression (tok
);
1781 if (t
== absolute_section
1782 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1784 assert (tok
->X_op
== O_constant
);
1785 tok
->X_op
= O_symbol
;
1786 tok
->X_add_symbol
= &abs_symbol
;
1789 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1790 && (reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1791 && (reloc
!= BFD_RELOC_NONE
))
1796 case BFD_RELOC_UNUSED
:
1797 as_bad (_("unsupported relocation"));
1800 case BFD_RELOC_XTENSA_PLT
:
1801 tok
->X_op
= O_pltrel
;
1804 case BFD_RELOC_LO16
:
1805 if (tok
->X_op
== O_constant
)
1806 tok
->X_add_number
&= 0xffff;
1811 case BFD_RELOC_HI16
:
1812 if (tok
->X_op
== O_constant
)
1813 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1822 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1823 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1825 if (reg
!= ERROR_REG_NUM
) /* Already errored */
1828 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
1829 as_bad (_("register number out of range"));
1832 tok
->X_op
= O_register
;
1833 tok
->X_add_symbol
= 0;
1834 tok
->X_add_number
= reg
;
1839 /* Split up the arguments for an opcode or pseudo-op. */
1842 tokenize_arguments (char **args
, char *str
)
1844 char *old_input_line_pointer
;
1845 bfd_boolean saw_comma
= FALSE
;
1846 bfd_boolean saw_arg
= FALSE
;
1847 bfd_boolean saw_colon
= FALSE
;
1849 char *arg_end
, *arg
;
1852 /* Save and restore input_line_pointer around this function. */
1853 old_input_line_pointer
= input_line_pointer
;
1854 input_line_pointer
= str
;
1856 while (*input_line_pointer
)
1859 switch (*input_line_pointer
)
1866 input_line_pointer
++;
1867 if (saw_comma
|| saw_colon
|| !saw_arg
)
1873 input_line_pointer
++;
1874 if (saw_comma
|| saw_colon
|| !saw_arg
)
1880 if (!saw_comma
&& !saw_colon
&& saw_arg
)
1883 arg_end
= input_line_pointer
+ 1;
1884 while (!expression_end (arg_end
))
1887 arg_len
= arg_end
- input_line_pointer
;
1888 arg
= (char *) xmalloc ((saw_colon
? 1 : 0) + arg_len
+ 1);
1889 args
[num_args
] = arg
;
1893 strncpy (arg
, input_line_pointer
, arg_len
);
1894 arg
[arg_len
] = '\0';
1896 input_line_pointer
= arg_end
;
1906 if (saw_comma
|| saw_colon
)
1908 input_line_pointer
= old_input_line_pointer
;
1913 as_bad (_("extra comma"));
1915 as_bad (_("extra colon"));
1917 as_bad (_("missing argument"));
1919 as_bad (_("missing comma or colon"));
1920 input_line_pointer
= old_input_line_pointer
;
1925 /* Parse the arguments to an opcode. Return TRUE on error. */
1928 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
1930 expressionS
*tok
, *last_tok
;
1931 xtensa_opcode opcode
= insn
->opcode
;
1932 bfd_boolean had_error
= TRUE
;
1933 xtensa_isa isa
= xtensa_default_isa
;
1934 int n
, num_regs
= 0;
1935 int opcode_operand_count
;
1936 int opnd_cnt
, last_opnd_cnt
;
1937 unsigned int next_reg
= 0;
1938 char *old_input_line_pointer
;
1940 if (insn
->insn_type
== ITYPE_LITERAL
)
1941 opcode_operand_count
= 1;
1943 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
1946 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
1948 /* Save and restore input_line_pointer around this function. */
1949 old_input_line_pointer
= input_line_pointer
;
1955 /* Skip invisible operands. */
1956 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
1962 for (n
= 0; n
< num_args
; n
++)
1964 input_line_pointer
= arg_strings
[n
];
1965 if (*input_line_pointer
== ':')
1967 xtensa_regfile opnd_rf
;
1968 input_line_pointer
++;
1971 assert (opnd_cnt
> 0);
1973 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
1975 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
1976 as_warn (_("incorrect register number, ignoring"));
1981 if (opnd_cnt
>= opcode_operand_count
)
1983 as_warn (_("too many arguments"));
1986 assert (opnd_cnt
< MAX_INSN_ARGS
);
1988 expression_maybe_register (opcode
, opnd_cnt
, tok
);
1989 next_reg
= tok
->X_add_number
+ 1;
1991 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
1993 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
1995 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
1996 /* minus 1 because we are seeing one right now */
2002 last_opnd_cnt
= opnd_cnt
;
2009 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
2013 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
2016 insn
->ntok
= tok
- insn
->tok
;
2020 input_line_pointer
= old_input_line_pointer
;
2026 get_invisible_operands (TInsn
*insn
)
2028 xtensa_isa isa
= xtensa_default_isa
;
2029 static xtensa_insnbuf slotbuf
= NULL
;
2031 xtensa_opcode opc
= insn
->opcode
;
2032 int slot
, opnd
, fmt_found
;
2036 slotbuf
= xtensa_insnbuf_alloc (isa
);
2038 /* Find format/slot where this can be encoded. */
2041 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2043 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2045 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2051 if (fmt_found
) break;
2056 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2060 /* First encode all the visible operands
2061 (to deal with shared field operands). */
2062 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2064 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2065 && (insn
->tok
[opnd
].X_op
== O_register
2066 || insn
->tok
[opnd
].X_op
== O_constant
))
2068 val
= insn
->tok
[opnd
].X_add_number
;
2069 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2070 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2074 /* Then pull out the values for the invisible ones. */
2075 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2077 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2079 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2080 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2081 insn
->tok
[opnd
].X_add_number
= val
;
2082 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2083 insn
->tok
[opnd
].X_op
= O_register
;
2085 insn
->tok
[opnd
].X_op
= O_constant
;
2094 xg_reverse_shift_count (char **cnt_argp
)
2096 char *cnt_arg
, *new_arg
;
2097 cnt_arg
= *cnt_argp
;
2099 /* replace the argument with "31-(argument)" */
2100 new_arg
= (char *) xmalloc (strlen (cnt_arg
) + 6);
2101 sprintf (new_arg
, "31-(%s)", cnt_arg
);
2104 *cnt_argp
= new_arg
;
2108 /* If "arg" is a constant expression, return non-zero with the value
2112 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2115 char *save_ptr
= input_line_pointer
;
2117 input_line_pointer
= arg
;
2119 input_line_pointer
= save_ptr
;
2121 if (exp
.X_op
== O_constant
)
2123 *valp
= exp
.X_add_number
;
2132 xg_replace_opname (char **popname
, char *newop
)
2135 *popname
= (char *) xmalloc (strlen (newop
) + 1);
2136 strcpy (*popname
, newop
);
2141 xg_check_num_args (int *pnum_args
,
2146 int num_args
= *pnum_args
;
2148 if (num_args
< expected_num
)
2150 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2151 num_args
, opname
, expected_num
);
2155 if (num_args
> expected_num
)
2157 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2158 num_args
, opname
, expected_num
);
2159 while (num_args
-- > expected_num
)
2161 free (arg_strings
[num_args
]);
2162 arg_strings
[num_args
] = 0;
2164 *pnum_args
= expected_num
;
2172 /* If the register is not specified as part of the opcode,
2173 then get it from the operand and move it to the opcode. */
2176 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2178 xtensa_isa isa
= xtensa_default_isa
;
2180 char *opname
, *new_opname
;
2181 const char *sr_name
;
2182 int is_user
, is_write
;
2187 is_user
= (opname
[1] == 'u');
2188 is_write
= (opname
[0] == 'w');
2190 /* Opname == [rw]ur or [rwx]sr... */
2192 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2195 /* Check if the argument is a symbolic register name. */
2196 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2197 /* Handle WSR to "INTSET" as a special case. */
2198 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2199 && !strcasecmp (arg_strings
[1], "intset"))
2200 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2201 if (sr
== XTENSA_UNDEFINED
2202 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2204 /* Maybe it's a register number.... */
2206 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2208 as_bad (_("invalid register '%s' for '%s' instruction"),
2209 arg_strings
[1], opname
);
2212 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2213 if (sr
== XTENSA_UNDEFINED
)
2215 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2216 (long) val
, opname
);
2221 /* Remove the last argument, which is now part of the opcode. */
2222 free (arg_strings
[1]);
2226 /* Translate the opcode. */
2227 sr_name
= xtensa_sysreg_name (isa
, sr
);
2228 /* Another special case for "WSR.INTSET".... */
2229 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2231 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2232 sprintf (new_opname
, "%s.%s", *popname
, sr_name
);
2234 *popname
= new_opname
;
2241 xtensa_translate_old_userreg_ops (char **popname
)
2243 xtensa_isa isa
= xtensa_default_isa
;
2245 char *opname
, *new_opname
;
2246 const char *sr_name
;
2247 bfd_boolean has_underbar
= FALSE
;
2250 if (opname
[0] == '_')
2252 has_underbar
= TRUE
;
2256 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2257 if (sr
!= XTENSA_UNDEFINED
)
2259 /* The new default name ("nnn") is different from the old default
2260 name ("URnnn"). The old default is handled below, and we don't
2261 want to recognize [RW]nnn, so do nothing if the name is the (new)
2263 static char namebuf
[10];
2264 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2265 if (strcmp (namebuf
, opname
+ 1) == 0)
2273 /* Only continue if the reg name is "URnnn". */
2274 if (opname
[1] != 'u' || opname
[2] != 'r')
2276 val
= strtoul (opname
+ 3, &end
, 10);
2280 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2281 if (sr
== XTENSA_UNDEFINED
)
2283 as_bad (_("invalid register number (%ld) for '%s'"),
2284 (long) val
, opname
);
2289 /* Translate the opcode. */
2290 sr_name
= xtensa_sysreg_name (isa
, sr
);
2291 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2292 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2293 opname
[0], sr_name
);
2295 *popname
= new_opname
;
2302 xtensa_translate_zero_immed (char *old_op
,
2312 assert (opname
[0] != '_');
2314 if (strcmp (opname
, old_op
) != 0)
2317 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2319 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2321 xg_replace_opname (popname
, new_op
);
2322 free (arg_strings
[1]);
2323 arg_strings
[1] = arg_strings
[2];
2332 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2333 Returns non-zero if an error was found. */
2336 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2338 char *opname
= *popname
;
2339 bfd_boolean has_underbar
= FALSE
;
2341 if (cur_vinsn
.inside_bundle
)
2346 has_underbar
= TRUE
;
2350 if (strcmp (opname
, "mov") == 0)
2352 if (use_transform () && !has_underbar
&& density_supported
)
2353 xg_replace_opname (popname
, "mov.n");
2356 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2358 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2359 arg_strings
[2] = (char *) xmalloc (strlen (arg_strings
[1]) + 1);
2360 strcpy (arg_strings
[2], arg_strings
[1]);
2366 if (strcmp (opname
, "bbsi.l") == 0)
2368 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2370 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2371 if (target_big_endian
)
2372 xg_reverse_shift_count (&arg_strings
[1]);
2376 if (strcmp (opname
, "bbci.l") == 0)
2378 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2380 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2381 if (target_big_endian
)
2382 xg_reverse_shift_count (&arg_strings
[1]);
2386 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
2387 && strcmp (opname
, "nop") == 0)
2389 if (use_transform () && !has_underbar
&& density_supported
)
2390 xg_replace_opname (popname
, "nop.n");
2393 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2395 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2396 arg_strings
[0] = (char *) xmalloc (3);
2397 arg_strings
[1] = (char *) xmalloc (3);
2398 arg_strings
[2] = (char *) xmalloc (3);
2399 strcpy (arg_strings
[0], "a1");
2400 strcpy (arg_strings
[1], "a1");
2401 strcpy (arg_strings
[2], "a1");
2407 /* Recognize [RW]UR and [RWX]SR. */
2408 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2409 && (opname
[1] == 'u' || opname
[1] == 's'))
2410 || (opname
[0] == 'x' && opname
[1] == 's'))
2412 && opname
[3] == '\0')
2413 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2415 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2416 [RW]<name> if <name> is the non-default name of a user register. */
2417 if ((opname
[0] == 'r' || opname
[0] == 'w')
2418 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2419 return xtensa_translate_old_userreg_ops (popname
);
2421 /* Relax branches that don't allow comparisons against an immediate value
2422 of zero to the corresponding branches with implicit zero immediates. */
2423 if (!has_underbar
&& use_transform ())
2425 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2426 pnum_args
, arg_strings
))
2429 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2430 pnum_args
, arg_strings
))
2433 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2434 pnum_args
, arg_strings
))
2437 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2438 pnum_args
, arg_strings
))
2446 /* Functions for dealing with the Xtensa ISA. */
2448 /* Currently the assembler only allows us to use a single target per
2449 fragment. Because of this, only one operand for a given
2450 instruction may be symbolic. If there is a PC-relative operand,
2451 the last one is chosen. Otherwise, the result is the number of the
2452 last immediate operand, and if there are none of those, we fail and
2456 get_relaxable_immed (xtensa_opcode opcode
)
2458 int last_immed
= -1;
2461 if (opcode
== XTENSA_UNDEFINED
)
2464 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2465 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2467 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2469 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2471 if (last_immed
== -1
2472 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2479 static xtensa_opcode
2480 get_opcode_from_buf (const char *buf
, int slot
)
2482 static xtensa_insnbuf insnbuf
= NULL
;
2483 static xtensa_insnbuf slotbuf
= NULL
;
2484 xtensa_isa isa
= xtensa_default_isa
;
2489 insnbuf
= xtensa_insnbuf_alloc (isa
);
2490 slotbuf
= xtensa_insnbuf_alloc (isa
);
2493 xtensa_insnbuf_from_chars (isa
, insnbuf
, (const unsigned char *) buf
, 0);
2494 fmt
= xtensa_format_decode (isa
, insnbuf
);
2495 if (fmt
== XTENSA_UNDEFINED
)
2496 return XTENSA_UNDEFINED
;
2498 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2499 return XTENSA_UNDEFINED
;
2501 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2502 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2506 #ifdef TENSILICA_DEBUG
2508 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2511 xtensa_print_insn_table (void)
2513 int num_opcodes
, num_operands
;
2514 xtensa_opcode opcode
;
2515 xtensa_isa isa
= xtensa_default_isa
;
2517 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2518 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2521 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2522 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2523 for (opn
= 0; opn
< num_operands
; opn
++)
2525 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2527 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2529 xtensa_regfile opnd_rf
=
2530 xtensa_operand_regfile (isa
, opcode
, opn
);
2531 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2533 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2534 fputs ("[lLr] ", stderr
);
2536 fputs ("i ", stderr
);
2538 fprintf (stderr
, "\n");
2544 print_vliw_insn (xtensa_insnbuf vbuf
)
2546 xtensa_isa isa
= xtensa_default_isa
;
2547 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2548 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2551 fprintf (stderr
, "format = %d\n", f
);
2553 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2555 xtensa_opcode opcode
;
2559 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2560 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2561 opname
= xtensa_opcode_name (isa
, opcode
);
2563 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2564 fprintf (stderr
, " operands = ");
2566 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2570 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2572 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2573 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2574 fprintf (stderr
, "%d ", val
);
2576 fprintf (stderr
, "\n");
2578 xtensa_insnbuf_free (isa
, sbuf
);
2581 #endif /* TENSILICA_DEBUG */
2585 is_direct_call_opcode (xtensa_opcode opcode
)
2587 xtensa_isa isa
= xtensa_default_isa
;
2588 int n
, num_operands
;
2590 if (xtensa_opcode_is_call (isa
, opcode
) != 1)
2593 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2594 for (n
= 0; n
< num_operands
; n
++)
2596 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2597 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2604 /* Convert from BFD relocation type code to slot and operand number.
2605 Returns non-zero on failure. */
2608 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2610 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2611 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2613 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2616 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2617 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2619 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2629 /* Convert from slot number to BFD relocation type code for the
2630 standard PC-relative relocations. Return BFD_RELOC_NONE on
2633 static bfd_reloc_code_real_type
2634 encode_reloc (int slot
)
2636 if (slot
< 0 || slot
> 14)
2637 return BFD_RELOC_NONE
;
2639 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2643 /* Convert from slot numbers to BFD relocation type code for the
2644 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2646 static bfd_reloc_code_real_type
2647 encode_alt_reloc (int slot
)
2649 if (slot
< 0 || slot
> 14)
2650 return BFD_RELOC_NONE
;
2652 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2657 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2660 xtensa_opcode opcode
,
2666 uint32 valbuf
= value
;
2668 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2670 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2672 as_bad_where ((char *) file
, line
,
2673 _("operand %d of '%s' has out of range value '%u'"),
2675 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2678 as_bad_where ((char *) file
, line
,
2679 _("operand %d of '%s' has invalid value '%u'"),
2681 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2686 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2692 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2695 xtensa_opcode opcode
,
2699 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2700 fmt
, slot
, slotbuf
, &val
);
2701 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2706 /* Checks for rules from xtensa-relax tables. */
2708 /* The routine xg_instruction_matches_option_term must return TRUE
2709 when a given option term is true. The meaning of all of the option
2710 terms is given interpretation by this function. This is needed when
2711 an option depends on the state of a directive, but there are no such
2712 options in use right now. */
2715 xg_instruction_matches_option_term (TInsn
*insn ATTRIBUTE_UNUSED
,
2716 const ReqOrOption
*option
)
2718 if (strcmp (option
->option_name
, "realnop") == 0
2719 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2721 /* These conditions were evaluated statically when building the
2722 relaxation table. There's no need to reevaluate them now. */
2727 as_fatal (_("internal error: unknown option name '%s'"),
2728 option
->option_name
);
2734 xg_instruction_matches_or_options (TInsn
*insn
,
2735 const ReqOrOptionList
*or_option
)
2737 const ReqOrOption
*option
;
2738 /* Must match each of the AND terms. */
2739 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2741 if (xg_instruction_matches_option_term (insn
, option
))
2749 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2751 const ReqOption
*req_options
;
2752 /* Must match each of the AND terms. */
2753 for (req_options
= options
;
2754 req_options
!= NULL
;
2755 req_options
= req_options
->next
)
2757 /* Must match one of the OR clauses. */
2758 if (!xg_instruction_matches_or_options (insn
,
2759 req_options
->or_option_terms
))
2766 /* Return the transition rule that matches or NULL if none matches. */
2769 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2771 PreconditionList
*condition_l
;
2773 if (rule
->opcode
!= insn
->opcode
)
2776 for (condition_l
= rule
->conditions
;
2777 condition_l
!= NULL
;
2778 condition_l
= condition_l
->next
)
2782 Precondition
*cond
= condition_l
->precond
;
2787 /* The expression must be the constant. */
2788 assert (cond
->op_num
< insn
->ntok
);
2789 exp1
= &insn
->tok
[cond
->op_num
];
2790 if (expr_is_const (exp1
))
2795 if (get_expr_const (exp1
) != cond
->op_data
)
2799 if (get_expr_const (exp1
) == cond
->op_data
)
2806 else if (expr_is_register (exp1
))
2811 if (get_expr_register (exp1
) != cond
->op_data
)
2815 if (get_expr_register (exp1
) == cond
->op_data
)
2827 assert (cond
->op_num
< insn
->ntok
);
2828 assert (cond
->op_data
< insn
->ntok
);
2829 exp1
= &insn
->tok
[cond
->op_num
];
2830 exp2
= &insn
->tok
[cond
->op_data
];
2835 if (!expr_is_equal (exp1
, exp2
))
2839 if (expr_is_equal (exp1
, exp2
))
2851 if (!xg_instruction_matches_options (insn
, rule
->options
))
2859 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
2861 bfd_boolean a_greater
= FALSE
;
2862 bfd_boolean b_greater
= FALSE
;
2864 ReqOptionList
*l_a
= a
->options
;
2865 ReqOptionList
*l_b
= b
->options
;
2867 /* We only care if they both are the same except for
2868 a const16 vs. an l32r. */
2870 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2872 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
2873 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
2874 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2876 if (l_or_a
->is_true
!= l_or_b
->is_true
)
2878 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
2880 /* This is the case we care about. */
2881 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
2882 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
2889 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
2890 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
2900 l_or_a
= l_or_a
->next
;
2901 l_or_b
= l_or_b
->next
;
2903 if (l_or_a
|| l_or_b
)
2912 /* Incomparable if the substitution was used differently in two cases. */
2913 if (a_greater
&& b_greater
)
2925 static TransitionRule
*
2926 xg_instruction_match (TInsn
*insn
)
2928 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
2930 assert (insn
->opcode
< table
->num_opcodes
);
2932 /* Walk through all of the possible transitions. */
2933 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2935 TransitionRule
*rule
= l
->rule
;
2936 if (xg_instruction_matches_rule (insn
, rule
))
2943 /* Various Other Internal Functions. */
2946 is_unique_insn_expansion (TransitionRule
*r
)
2948 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
2950 if (r
->to_instr
->typ
!= INSTR_INSTR
)
2956 /* Check if there is exactly one relaxation for INSN that converts it to
2957 another instruction of equal or larger size. If so, and if TARG is
2958 non-null, go ahead and generate the relaxed instruction into TARG. If
2959 NARROW_ONLY is true, then only consider relaxations that widen a narrow
2960 instruction, i.e., ignore relaxations that convert to an instruction of
2961 equal size. In some contexts where this function is used, only
2962 a single widening is allowed and the NARROW_ONLY argument is used to
2963 exclude cases like ADDI being "widened" to an ADDMI, which may
2964 later be relaxed to an ADDMI/ADDI pair. */
2967 xg_is_single_relaxable_insn (TInsn
*insn
, TInsn
*targ
, bfd_boolean narrow_only
)
2969 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
2971 TransitionRule
*match
= 0;
2973 assert (insn
->insn_type
== ITYPE_INSN
);
2974 assert (insn
->opcode
< table
->num_opcodes
);
2976 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2978 TransitionRule
*rule
= l
->rule
;
2980 if (xg_instruction_matches_rule (insn
, rule
)
2981 && is_unique_insn_expansion (rule
)
2982 && (xg_get_single_size (insn
->opcode
) + (narrow_only
? 1 : 0)
2983 <= xg_get_single_size (rule
->to_instr
->opcode
)))
2994 xg_build_to_insn (targ
, insn
, match
->to_instr
);
2999 /* Return the maximum number of bytes this opcode can expand to. */
3002 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
3004 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3006 int max_size
= xg_get_single_size (opcode
);
3008 assert (opcode
< table
->num_opcodes
);
3010 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3012 TransitionRule
*rule
= l
->rule
;
3013 BuildInstr
*build_list
;
3018 build_list
= rule
->to_instr
;
3019 if (is_unique_insn_expansion (rule
))
3021 assert (build_list
->typ
== INSTR_INSTR
);
3022 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
3025 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3027 switch (build_list
->typ
)
3030 this_size
+= xg_get_single_size (build_list
->opcode
);
3032 case INSTR_LITERAL_DEF
:
3033 case INSTR_LABEL_DEF
:
3038 if (this_size
> max_size
)
3039 max_size
= this_size
;
3045 /* Return the maximum number of literal bytes this opcode can generate. */
3048 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3050 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3054 assert (opcode
< table
->num_opcodes
);
3056 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3058 TransitionRule
*rule
= l
->rule
;
3059 BuildInstr
*build_list
;
3064 build_list
= rule
->to_instr
;
3065 if (is_unique_insn_expansion (rule
))
3067 assert (build_list
->typ
== INSTR_INSTR
);
3068 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3071 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3073 switch (build_list
->typ
)
3075 case INSTR_LITERAL_DEF
:
3076 /* Hard-coded 4-byte literal. */
3080 case INSTR_LABEL_DEF
:
3085 if (this_size
> max_size
)
3086 max_size
= this_size
;
3093 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3095 int steps_taken
= 0;
3096 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3099 assert (insn
->insn_type
== ITYPE_INSN
);
3100 assert (insn
->opcode
< table
->num_opcodes
);
3102 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3104 TransitionRule
*rule
= l
->rule
;
3106 if (xg_instruction_matches_rule (insn
, rule
))
3108 if (steps_taken
== lateral_steps
)
3118 get_special_literal_symbol (void)
3120 static symbolS
*sym
= NULL
;
3123 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3129 get_special_label_symbol (void)
3131 static symbolS
*sym
= NULL
;
3134 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3140 xg_valid_literal_expression (const expressionS
*exp
)
3157 /* This will check to see if the value can be converted into the
3158 operand type. It will return TRUE if it does not fit. */
3161 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3163 uint32 valbuf
= value
;
3164 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3170 /* Assumes: All immeds are constants. Check that all constants fit
3171 into their immeds; return FALSE if not. */
3174 xg_immeds_fit (const TInsn
*insn
)
3176 xtensa_isa isa
= xtensa_default_isa
;
3180 assert (insn
->insn_type
== ITYPE_INSN
);
3181 for (i
= 0; i
< n
; ++i
)
3183 const expressionS
*expr
= &insn
->tok
[i
];
3184 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3191 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3196 /* The symbol should have a fixup associated with it. */
3205 /* This should only be called after we have an initial
3206 estimate of the addresses. */
3209 xg_symbolic_immeds_fit (const TInsn
*insn
,
3215 xtensa_isa isa
= xtensa_default_isa
;
3223 assert (insn
->insn_type
== ITYPE_INSN
);
3225 for (i
= 0; i
< n
; ++i
)
3227 const expressionS
*expr
= &insn
->tok
[i
];
3228 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3235 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3241 /* Check for the worst case. */
3242 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3247 /* We only allow symbols for PC-relative references.
3248 If pc_frag == 0, then we don't have frag locations yet. */
3250 || xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0)
3253 /* If it is a weak symbol, then assume it won't reach. */
3254 if (S_IS_WEAK (expr
->X_add_symbol
))
3257 if (is_direct_call_opcode (insn
->opcode
)
3258 && ! pc_frag
->tc_frag_data
.use_longcalls
)
3260 /* If callee is undefined or in a different segment, be
3261 optimistic and assume it will be in range. */
3262 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3266 /* Only references within a segment can be known to fit in the
3267 operands at assembly time. */
3268 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3271 symbolP
= expr
->X_add_symbol
;
3272 sym_frag
= symbol_get_frag (symbolP
);
3273 target
= S_GET_VALUE (symbolP
) + expr
->X_add_number
;
3274 pc
= pc_frag
->fr_address
+ pc_offset
;
3276 /* If frag has yet to be reached on this pass, assume it
3277 will move by STRETCH just as we did. If this is not so,
3278 it will be because some frag between grows, and that will
3279 force another pass. Beware zero-length frags. There
3280 should be a faster way to do this. */
3283 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3284 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3289 new_offset
= target
;
3290 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3291 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3296 /* The symbol should have a fixup associated with it. */
3305 /* Return TRUE on success. */
3308 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3313 memset (targ
, 0, sizeof (TInsn
));
3314 targ
->linenum
= insn
->linenum
;
3319 targ
->opcode
= bi
->opcode
;
3320 targ
->insn_type
= ITYPE_INSN
;
3321 targ
->is_specific_opcode
= FALSE
;
3323 for (; op
!= NULL
; op
= op
->next
)
3325 int op_num
= op
->op_num
;
3326 int op_data
= op
->op_data
;
3328 assert (op
->op_num
< MAX_INSN_ARGS
);
3330 if (targ
->ntok
<= op_num
)
3331 targ
->ntok
= op_num
+ 1;
3336 set_expr_const (&targ
->tok
[op_num
], op_data
);
3339 assert (op_data
< insn
->ntok
);
3340 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3343 sym
= get_special_literal_symbol ();
3344 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3347 sym
= get_special_label_symbol ();
3348 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3350 case OP_OPERAND_HI16U
:
3351 case OP_OPERAND_LOW16U
:
3352 assert (op_data
< insn
->ntok
);
3353 if (expr_is_const (&insn
->tok
[op_data
]))
3356 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3357 val
= xg_apply_userdef_op_fn (op
->typ
,
3360 targ
->tok
[op_num
].X_add_number
= val
;
3364 /* For const16 we can create relocations for these. */
3365 if (targ
->opcode
== XTENSA_UNDEFINED
3366 || (targ
->opcode
!= xtensa_const16_opcode
))
3368 assert (op_data
< insn
->ntok
);
3369 /* Need to build a O_lo16 or O_hi16. */
3370 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3371 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3373 if (op
->typ
== OP_OPERAND_HI16U
)
3374 targ
->tok
[op_num
].X_op
= O_hi16
;
3375 else if (op
->typ
== OP_OPERAND_LOW16U
)
3376 targ
->tok
[op_num
].X_op
= O_lo16
;
3383 /* currently handles:
3386 OP_OPERAND_F32MINUS */
3387 if (xg_has_userdef_op_fn (op
->typ
))
3389 assert (op_data
< insn
->ntok
);
3390 if (expr_is_const (&insn
->tok
[op_data
]))
3393 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3394 val
= xg_apply_userdef_op_fn (op
->typ
,
3397 targ
->tok
[op_num
].X_add_number
= val
;
3400 return FALSE
; /* We cannot use a relocation for this. */
3409 case INSTR_LITERAL_DEF
:
3411 targ
->opcode
= XTENSA_UNDEFINED
;
3412 targ
->insn_type
= ITYPE_LITERAL
;
3413 targ
->is_specific_opcode
= FALSE
;
3414 for (; op
!= NULL
; op
= op
->next
)
3416 int op_num
= op
->op_num
;
3417 int op_data
= op
->op_data
;
3418 assert (op
->op_num
< MAX_INSN_ARGS
);
3420 if (targ
->ntok
<= op_num
)
3421 targ
->ntok
= op_num
+ 1;
3426 assert (op_data
< insn
->ntok
);
3427 /* We can only pass resolvable literals through. */
3428 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3430 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3442 case INSTR_LABEL_DEF
:
3444 targ
->opcode
= XTENSA_UNDEFINED
;
3445 targ
->insn_type
= ITYPE_LABEL
;
3446 targ
->is_specific_opcode
= FALSE
;
3447 /* Literal with no ops is a label? */
3448 assert (op
== NULL
);
3459 /* Return TRUE on success. */
3462 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3464 for (; bi
!= NULL
; bi
= bi
->next
)
3466 TInsn
*next_insn
= istack_push_space (istack
);
3468 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3475 /* Return TRUE on valid expansion. */
3478 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3480 int stack_size
= istack
->ninsn
;
3481 int steps_taken
= 0;
3482 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3485 assert (insn
->insn_type
== ITYPE_INSN
);
3486 assert (insn
->opcode
< table
->num_opcodes
);
3488 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3490 TransitionRule
*rule
= l
->rule
;
3492 if (xg_instruction_matches_rule (insn
, rule
))
3494 if (lateral_steps
== steps_taken
)
3498 /* This is it. Expand the rule to the stack. */
3499 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3502 /* Check to see if it fits. */
3503 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3505 TInsn
*insn
= &istack
->insn
[i
];
3507 if (insn
->insn_type
== ITYPE_INSN
3508 && !tinsn_has_symbolic_operands (insn
)
3509 && !xg_immeds_fit (insn
))
3511 istack
->ninsn
= stack_size
;
3524 /* Relax the assembly instruction at least "min_steps".
3525 Return the number of steps taken. */
3528 xg_assembly_relax (IStack
*istack
,
3531 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3532 offsetT pc_offset
, /* offset in fragment */
3533 int min_steps
, /* minimum conversion steps */
3534 long stretch
) /* number of bytes stretched so far */
3536 int steps_taken
= 0;
3538 /* assert (has no symbolic operands)
3539 Some of its immeds don't fit.
3540 Try to build a relaxed version.
3541 This may go through a couple of stages
3542 of single instruction transformations before
3545 TInsn single_target
;
3547 int lateral_steps
= 0;
3548 int istack_size
= istack
->ninsn
;
3550 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3551 && steps_taken
>= min_steps
)
3553 istack_push (istack
, insn
);
3556 current_insn
= *insn
;
3558 /* Walk through all of the single instruction expansions. */
3559 while (xg_is_single_relaxable_insn (¤t_insn
, &single_target
, FALSE
))
3562 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3565 if (steps_taken
>= min_steps
)
3567 istack_push (istack
, &single_target
);
3571 current_insn
= single_target
;
3574 /* Now check for a multi-instruction expansion. */
3575 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3577 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3580 if (steps_taken
>= min_steps
)
3582 istack_push (istack
, ¤t_insn
);
3587 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3589 if (steps_taken
>= min_steps
)
3593 istack
->ninsn
= istack_size
;
3596 /* It's not going to work -- use the original. */
3597 istack_push (istack
, insn
);
3603 xg_force_frag_space (int size
)
3605 /* This may have the side effect of creating a new fragment for the
3606 space to go into. I just do not like the name of the "frag"
3613 xg_finish_frag (char *last_insn
,
3614 enum xtensa_relax_statesE frag_state
,
3615 enum xtensa_relax_statesE slot0_state
,
3617 bfd_boolean is_insn
)
3619 /* Finish off this fragment so that it has at LEAST the desired
3620 max_growth. If it doesn't fit in this fragment, close this one
3621 and start a new one. In either case, return a pointer to the
3622 beginning of the growth area. */
3626 xg_force_frag_space (max_growth
);
3628 old_frag
= frag_now
;
3630 frag_now
->fr_opcode
= last_insn
;
3632 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3634 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3635 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3637 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3638 xtensa_set_frag_assembly_state (frag_now
);
3640 /* Just to make sure that we did not split it up. */
3641 assert (old_frag
->fr_next
== frag_now
);
3645 /* Return TRUE if the target frag is one of the next non-empty frags. */
3648 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3653 for (; fragP
; fragP
= fragP
->fr_next
)
3655 if (fragP
== target
)
3657 if (fragP
->fr_fix
!= 0)
3659 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3661 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3662 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3664 if (fragP
->fr_type
== rs_space
)
3672 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3674 xtensa_isa isa
= xtensa_default_isa
;
3676 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3681 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) != 1
3682 && xtensa_opcode_is_jump (isa
, insn
->opcode
) != 1)
3685 for (i
= 0; i
< num_ops
; i
++)
3687 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3693 if (target_op
== -1)
3696 if (insn
->ntok
<= target_op
)
3699 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3702 sym
= insn
->tok
[target_op
].X_add_symbol
;
3706 if (insn
->tok
[target_op
].X_add_number
!= 0)
3709 target_frag
= symbol_get_frag (sym
);
3710 if (target_frag
== NULL
)
3713 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3714 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3722 xg_add_branch_and_loop_targets (TInsn
*insn
)
3724 xtensa_isa isa
= xtensa_default_isa
;
3725 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3727 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3730 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3731 && insn
->tok
[i
].X_op
== O_symbol
)
3732 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3736 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3737 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3741 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3743 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3744 && insn
->tok
[i
].X_op
== O_symbol
)
3746 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3747 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3748 if (S_IS_DEFINED (sym
))
3749 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3756 /* Return FALSE if no error. */
3759 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3764 switch (instr_spec
->typ
)
3767 new_insn
->insn_type
= ITYPE_INSN
;
3768 new_insn
->opcode
= instr_spec
->opcode
;
3769 new_insn
->is_specific_opcode
= FALSE
;
3770 new_insn
->linenum
= old_insn
->linenum
;
3772 case INSTR_LITERAL_DEF
:
3773 new_insn
->insn_type
= ITYPE_LITERAL
;
3774 new_insn
->opcode
= XTENSA_UNDEFINED
;
3775 new_insn
->is_specific_opcode
= FALSE
;
3776 new_insn
->linenum
= old_insn
->linenum
;
3778 case INSTR_LABEL_DEF
:
3779 as_bad (_("INSTR_LABEL_DEF not supported yet"));
3783 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3786 const expressionS
*src_exp
;
3792 /* The expression must be the constant. */
3793 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3794 exp
= &new_insn
->tok
[b_op
->op_num
];
3795 set_expr_const (exp
, b_op
->op_data
);
3799 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3800 assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
3801 src_exp
= &old_insn
->tok
[b_op
->op_data
];
3802 exp
= &new_insn
->tok
[b_op
->op_num
];
3803 copy_expr (exp
, src_exp
);
3808 as_bad (_("can't handle generation of literal/labels yet"));
3812 as_bad (_("can't handle undefined OP TYPE"));
3817 new_insn
->ntok
= num_ops
;
3822 /* Return TRUE if it was simplified. */
3825 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
3827 TransitionRule
*rule
;
3828 BuildInstr
*insn_spec
;
3830 if (old_insn
->is_specific_opcode
|| !density_supported
)
3833 rule
= xg_instruction_match (old_insn
);
3837 insn_spec
= rule
->to_instr
;
3838 /* There should only be one. */
3839 assert (insn_spec
!= NULL
);
3840 assert (insn_spec
->next
== NULL
);
3841 if (insn_spec
->next
!= NULL
)
3844 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
3850 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3851 l32i.n. (2) Check the number of operands. (3) Place the instruction
3852 tokens into the stack or relax it and place multiple
3853 instructions/literals onto the stack. Return FALSE if no error. */
3856 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
3860 bfd_boolean do_expand
;
3862 memset (&new_insn
, 0, sizeof (TInsn
));
3864 /* Narrow it if we can. xg_simplify_insn now does all the
3865 appropriate checking (e.g., for the density option). */
3866 if (xg_simplify_insn (orig_insn
, &new_insn
))
3867 orig_insn
= &new_insn
;
3869 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
3871 if (orig_insn
->ntok
< noperands
)
3873 as_bad (_("found %d operands for '%s': Expected %d"),
3875 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3879 if (orig_insn
->ntok
> noperands
)
3880 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
3882 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3885 /* If there are not enough operands, we will assert above. If there
3886 are too many, just cut out the extras here. */
3887 orig_insn
->ntok
= noperands
;
3889 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
3892 /* If the instruction will definitely need to be relaxed, it is better
3893 to expand it now for better scheduling. Decide whether to expand
3895 do_expand
= (!orig_insn
->is_specific_opcode
&& use_transform ());
3897 /* Calls should be expanded to longcalls only in the backend relaxation
3898 so that the assembly scheduler will keep the L32R/CALLX instructions
3900 if (is_direct_call_opcode (orig_insn
->opcode
))
3903 if (tinsn_has_symbolic_operands (orig_insn
))
3905 /* The values of symbolic operands are not known yet, so only expand
3906 now if an operand is "complex" (e.g., difference of symbols) and
3907 will have to be stored as a literal regardless of the value. */
3908 if (!tinsn_has_complex_operands (orig_insn
))
3911 else if (xg_immeds_fit (orig_insn
))
3915 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
3917 istack_push (istack
, orig_insn
);
3923 /* Return TRUE if the section flags are marked linkonce
3924 or the name is .gnu.linkonce*. */
3927 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
3929 flagword flags
, link_once_flags
;
3931 flags
= bfd_get_section_flags (abfd
, sec
);
3932 link_once_flags
= (flags
& SEC_LINK_ONCE
);
3934 /* Flags might not be set yet. */
3935 if (!link_once_flags
)
3937 static size_t len
= sizeof ".gnu.linkonce.t.";
3939 if (strncmp (segment_name (sec
), ".gnu.linkonce.t.", len
- 1) == 0)
3940 link_once_flags
= SEC_LINK_ONCE
;
3942 return (link_once_flags
!= 0);
3947 xtensa_add_literal_sym (symbolS
*sym
)
3951 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
3953 l
->next
= literal_syms
;
3959 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
3961 static int lit_num
= 0;
3962 static char name
[256];
3965 sprintf (name
, ".L_lit_sym%d", lit_num
);
3967 /* Create a local symbol. If it is in a linkonce section, we have to
3968 be careful to make sure that if it is used in a relocation that the
3969 symbol will be in the output file. */
3970 if (get_is_linkonce_section (stdoutput
, sec
))
3972 symbolP
= symbol_new (name
, sec
, 0, frag
);
3973 S_CLEAR_EXTERNAL (symbolP
);
3974 /* symbolP->local = 1; */
3977 symbolP
= symbol_new (name
, sec
, 0, frag
);
3979 xtensa_add_literal_sym (symbolP
);
3986 /* Currently all literals that are generated here are 32-bit L32R targets. */
3989 xg_assemble_literal (/* const */ TInsn
*insn
)
3992 symbolS
*lit_sym
= NULL
;
3994 /* size = 4 for L32R. It could easily be larger when we move to
3995 larger constants. Add a parameter later. */
3996 offsetT litsize
= 4;
3997 offsetT litalign
= 2; /* 2^2 = 4 */
3998 expressionS saved_loc
;
3999 expressionS
* emit_val
;
4001 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
4003 assert (insn
->insn_type
== ITYPE_LITERAL
);
4004 assert (insn
->ntok
== 1); /* must be only one token here */
4006 xtensa_switch_to_literal_fragment (&state
);
4008 emit_val
= &insn
->tok
[0];
4009 if (emit_val
->X_op
== O_big
)
4011 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
4014 /* This happens when someone writes a "movi a2, big_number". */
4015 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4016 _("invalid immediate"));
4017 xtensa_restore_emit_state (&state
);
4022 /* Force a 4-byte align here. Note that this opens a new frag, so all
4023 literals done with this function have a frag to themselves. That's
4024 important for the way text section literals work. */
4025 frag_align (litalign
, 0, 0);
4026 record_alignment (now_seg
, litalign
);
4028 if (emit_val
->X_op
== O_pltrel
)
4030 char *p
= frag_more (litsize
);
4031 xtensa_set_frag_assembly_state (frag_now
);
4032 if (emit_val
->X_add_symbol
)
4033 emit_val
->X_op
= O_symbol
;
4035 emit_val
->X_op
= O_constant
;
4036 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
4037 litsize
, emit_val
, 0, BFD_RELOC_XTENSA_PLT
);
4040 emit_expr (emit_val
, litsize
);
4042 assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
4043 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4044 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4045 lit_sym
= frag_now
->fr_symbol
;
4048 xtensa_restore_emit_state (&state
);
4054 xg_assemble_literal_space (/* const */ int size
, int slot
)
4057 /* We might have to do something about this alignment. It only
4058 takes effect if something is placed here. */
4059 offsetT litalign
= 2; /* 2^2 = 4 */
4060 fragS
*lit_saved_frag
;
4062 assert (size
% 4 == 0);
4064 xtensa_switch_to_literal_fragment (&state
);
4066 /* Force a 4-byte align here. */
4067 frag_align (litalign
, 0, 0);
4068 record_alignment (now_seg
, litalign
);
4070 xg_force_frag_space (size
);
4072 lit_saved_frag
= frag_now
;
4073 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4074 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4075 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4078 xtensa_restore_emit_state (&state
);
4079 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4083 /* Put in a fixup record based on the opcode.
4084 Return TRUE on success. */
4087 xg_add_opcode_fix (TInsn
*tinsn
,
4095 xtensa_opcode opcode
= tinsn
->opcode
;
4096 bfd_reloc_code_real_type reloc
;
4097 reloc_howto_type
*howto
;
4101 reloc
= BFD_RELOC_NONE
;
4103 /* First try the special cases for "alternate" relocs. */
4104 if (opcode
== xtensa_l32r_opcode
)
4106 if (fragP
->tc_frag_data
.use_absolute_literals
)
4107 reloc
= encode_alt_reloc (slot
);
4109 else if (opcode
== xtensa_const16_opcode
)
4111 if (expr
->X_op
== O_lo16
)
4113 reloc
= encode_reloc (slot
);
4114 expr
->X_op
= O_symbol
;
4116 else if (expr
->X_op
== O_hi16
)
4118 reloc
= encode_alt_reloc (slot
);
4119 expr
->X_op
= O_symbol
;
4123 if (opnum
!= get_relaxable_immed (opcode
))
4125 as_bad (_("invalid relocation for operand %i of '%s'"),
4126 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4130 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4131 into the symbol table where the generic portions of the assembler
4132 won't know what to do with them. */
4133 if (expr
->X_op
== O_lo16
|| expr
->X_op
== O_hi16
)
4135 as_bad (_("invalid expression for operand %i of '%s'"),
4136 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4140 /* Next try the generic relocs. */
4141 if (reloc
== BFD_RELOC_NONE
)
4142 reloc
= encode_reloc (slot
);
4143 if (reloc
== BFD_RELOC_NONE
)
4145 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4149 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4152 as_bad (_("undefined symbol for opcode \"%s\""),
4153 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4157 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4158 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, expr
,
4159 howto
->pc_relative
, reloc
);
4160 the_fix
->fx_no_overflow
= 1;
4162 if (expr
->X_add_symbol
4163 && (S_IS_EXTERNAL (expr
->X_add_symbol
)
4164 || S_IS_WEAK (expr
->X_add_symbol
)))
4165 the_fix
->fx_plt
= TRUE
;
4167 the_fix
->tc_fix_data
.X_add_symbol
= expr
->X_add_symbol
;
4168 the_fix
->tc_fix_data
.X_add_number
= expr
->X_add_number
;
4169 the_fix
->tc_fix_data
.slot
= slot
;
4176 xg_emit_insn_to_buf (TInsn
*tinsn
,
4180 bfd_boolean build_fix
)
4182 static xtensa_insnbuf insnbuf
= NULL
;
4183 bfd_boolean has_symbolic_immed
= FALSE
;
4184 bfd_boolean ok
= TRUE
;
4187 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4189 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4190 if (has_symbolic_immed
&& build_fix
)
4193 xtensa_format fmt
= xg_get_single_format (tinsn
->opcode
);
4194 int slot
= xg_get_single_slot (tinsn
->opcode
);
4195 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4196 expressionS
*exp
= &tinsn
->tok
[opnum
];
4198 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, slot
, exp
, fragP
, offset
))
4201 fragP
->tc_frag_data
.is_insn
= TRUE
;
4202 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4203 (unsigned char *) buf
, 0);
4209 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4211 symbolS
*sym
= get_special_literal_symbol ();
4215 assert (insn
->insn_type
== ITYPE_INSN
);
4216 for (i
= 0; i
< insn
->ntok
; i
++)
4217 if (insn
->tok
[i
].X_add_symbol
== sym
)
4218 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4224 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4226 symbolS
*sym
= get_special_label_symbol ();
4228 for (i
= 0; i
< insn
->ntok
; i
++)
4229 if (insn
->tok
[i
].X_add_symbol
== sym
)
4230 insn
->tok
[i
].X_add_symbol
= label_sym
;
4235 /* Return TRUE if the instruction can write to the specified
4236 integer register. */
4239 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4243 xtensa_isa isa
= xtensa_default_isa
;
4245 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4247 for (i
= 0; i
< num_ops
; i
++)
4250 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4251 if ((inout
== 'o' || inout
== 'm')
4252 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4254 xtensa_regfile opnd_rf
=
4255 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4256 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4258 if ((insn
->tok
[i
].X_op
== O_register
)
4259 && (insn
->tok
[i
].X_add_number
== regnum
))
4269 is_bad_loopend_opcode (const TInsn
*tinsn
)
4271 xtensa_opcode opcode
= tinsn
->opcode
;
4273 if (opcode
== XTENSA_UNDEFINED
)
4276 if (opcode
== xtensa_call0_opcode
4277 || opcode
== xtensa_callx0_opcode
4278 || opcode
== xtensa_call4_opcode
4279 || opcode
== xtensa_callx4_opcode
4280 || opcode
== xtensa_call8_opcode
4281 || opcode
== xtensa_callx8_opcode
4282 || opcode
== xtensa_call12_opcode
4283 || opcode
== xtensa_callx12_opcode
4284 || opcode
== xtensa_isync_opcode
4285 || opcode
== xtensa_ret_opcode
4286 || opcode
== xtensa_ret_n_opcode
4287 || opcode
== xtensa_retw_opcode
4288 || opcode
== xtensa_retw_n_opcode
4289 || opcode
== xtensa_waiti_opcode
4290 || opcode
== xtensa_rsr_lcount_opcode
)
4297 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4298 This allows the debugger to add unaligned labels.
4299 Also, the assembler generates stabs labels that need
4300 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4303 is_unaligned_label (symbolS
*sym
)
4305 const char *name
= S_GET_NAME (sym
);
4306 static size_t fake_size
= 0;
4310 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4313 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4315 fake_size
= strlen (FAKE_LABEL_NAME
);
4318 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4319 && (name
[fake_size
] == 'F'
4320 || name
[fake_size
] == 'L'
4321 || (name
[fake_size
] == 'e'
4322 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4330 next_non_empty_frag (const fragS
*fragP
)
4332 fragS
*next_fragP
= fragP
->fr_next
;
4334 /* Sometimes an empty will end up here due storage allocation issues.
4335 So we have to skip until we find something legit. */
4336 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4337 next_fragP
= next_fragP
->fr_next
;
4339 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4347 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4349 xtensa_opcode out_opcode
;
4350 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4352 if (next_fragP
== NULL
)
4355 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4356 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4358 *opcode
= out_opcode
;
4366 frag_format_size (const fragS
*fragP
)
4368 static xtensa_insnbuf insnbuf
= NULL
;
4369 xtensa_isa isa
= xtensa_default_isa
;
4374 insnbuf
= xtensa_insnbuf_alloc (isa
);
4377 return XTENSA_UNDEFINED
;
4379 xtensa_insnbuf_from_chars (isa
, insnbuf
,
4380 (unsigned char *) fragP
->fr_literal
, 0);
4382 fmt
= xtensa_format_decode (isa
, insnbuf
);
4383 if (fmt
== XTENSA_UNDEFINED
)
4384 return XTENSA_UNDEFINED
;
4385 fmt_size
= xtensa_format_length (isa
, fmt
);
4387 /* If the next format won't be changing due to relaxation, just
4388 return the length of the first format. */
4389 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4392 /* If during relaxation we have to pull an instruction out of a
4393 multi-slot instruction, we will return the more conservative
4394 number. This works because alignment on bigger instructions
4395 is more restrictive than alignment on smaller instructions.
4396 This is more conservative than we would like, but it happens
4399 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4402 /* If we aren't doing one of our own relaxations or it isn't
4403 slot-based, then the insn size won't change. */
4404 if (fragP
->fr_type
!= rs_machine_dependent
)
4406 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4409 /* If an instruction is about to grow, return the longer size. */
4410 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4411 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
)
4414 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4415 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4422 next_frag_format_size (const fragS
*fragP
)
4424 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4425 return frag_format_size (next_fragP
);
4429 /* In early Xtensa Processors, for reasons that are unclear, the ISA
4430 required two-byte instructions to be treated as three-byte instructions
4431 for loop instruction alignment. This restriction was removed beginning
4432 with Xtensa LX. Now the only requirement on loop instruction alignment
4433 is that the first instruction of the loop must appear at an address that
4434 does not cross a fetch boundary. */
4437 get_loop_align_size (int insn_size
)
4439 if (insn_size
== XTENSA_UNDEFINED
)
4440 return xtensa_fetch_width
;
4442 if (enforce_three_byte_loop_align
&& insn_size
== 2)
4449 /* If the next legit fragment is an end-of-loop marker,
4450 switch its state so it will instantiate a NOP. */
4453 update_next_frag_state (fragS
*fragP
)
4455 fragS
*next_fragP
= fragP
->fr_next
;
4456 fragS
*new_target
= NULL
;
4460 /* We are guaranteed there will be one of these... */
4461 while (!(next_fragP
->fr_type
== rs_machine_dependent
4462 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4463 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4464 next_fragP
= next_fragP
->fr_next
;
4466 assert (next_fragP
->fr_type
== rs_machine_dependent
4467 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4468 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4470 /* ...and one of these. */
4471 new_target
= next_fragP
->fr_next
;
4472 while (!(new_target
->fr_type
== rs_machine_dependent
4473 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4474 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4475 new_target
= new_target
->fr_next
;
4477 assert (new_target
->fr_type
== rs_machine_dependent
4478 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4479 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4482 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4484 if (next_fragP
->fr_type
== rs_machine_dependent
4485 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4487 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4491 next_fragP
= next_fragP
->fr_next
;
4497 next_frag_is_branch_target (const fragS
*fragP
)
4499 /* Sometimes an empty will end up here due to storage allocation issues,
4500 so we have to skip until we find something legit. */
4501 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4503 if (fragP
->tc_frag_data
.is_branch_target
)
4505 if (fragP
->fr_fix
!= 0)
4513 next_frag_is_loop_target (const fragS
*fragP
)
4515 /* Sometimes an empty will end up here due storage allocation issues.
4516 So we have to skip until we find something legit. */
4517 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4519 if (fragP
->tc_frag_data
.is_loop_target
)
4521 if (fragP
->fr_fix
!= 0)
4529 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4531 const fragS
*next_fragp
= fragp
->fr_next
;
4532 xtensa_opcode next_opcode
;
4534 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4537 /* Sometimes an empty will end up here due to storage allocation issues,
4538 so we have to skip until we find something legit. */
4539 while (next_fragp
->fr_fix
== 0)
4540 next_fragp
= next_fragp
->fr_next
;
4542 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4545 /* There is some implicit knowledge encoded in here.
4546 The LOOP instructions that are NOT RELAX_IMMED have
4547 been relaxed. Note that we can assume that the LOOP
4548 instruction is in slot 0 because loops aren't bundleable. */
4549 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4550 return get_expanded_loop_offset (next_opcode
);
4556 /* Mark a location where we can later insert literal frags. Update
4557 the section's literal_pool_loc, so subsequent literals can be
4558 placed nearest to their use. */
4561 xtensa_mark_literal_pool_location (void)
4563 /* Any labels pointing to the current location need
4564 to be adjusted to after the literal pool. */
4566 fragS
*pool_location
;
4568 if (use_literal_section
&& !directive_state
[directive_absolute_literals
])
4571 frag_align (2, 0, 0);
4572 record_alignment (now_seg
, 2);
4574 /* We stash info in these frags so we can later move the literal's
4575 fixes into this frchain's fix list. */
4576 pool_location
= frag_now
;
4577 frag_now
->tc_frag_data
.lit_frchain
= frchain_now
;
4578 frag_variant (rs_machine_dependent
, 0, 0,
4579 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4580 xtensa_set_frag_assembly_state (frag_now
);
4581 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
4582 frag_variant (rs_machine_dependent
, 0, 0,
4583 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4584 xtensa_set_frag_assembly_state (frag_now
);
4586 /* Now put a frag into the literal pool that points to this location. */
4587 set_literal_pool_location (now_seg
, pool_location
);
4588 xtensa_switch_to_non_abs_literal_fragment (&s
);
4589 frag_align (2, 0, 0);
4590 record_alignment (now_seg
, 2);
4592 /* Close whatever frag is there. */
4593 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4594 xtensa_set_frag_assembly_state (frag_now
);
4595 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
4596 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4597 xtensa_restore_emit_state (&s
);
4598 xtensa_set_frag_assembly_state (frag_now
);
4602 /* Build a nop of the correct size into tinsn. */
4605 build_nop (TInsn
*tinsn
, int size
)
4611 tinsn
->opcode
= xtensa_nop_n_opcode
;
4613 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4614 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4618 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4620 tinsn
->opcode
= xtensa_or_opcode
;
4621 set_expr_const (&tinsn
->tok
[0], 1);
4622 set_expr_const (&tinsn
->tok
[1], 1);
4623 set_expr_const (&tinsn
->tok
[2], 1);
4627 tinsn
->opcode
= xtensa_nop_opcode
;
4629 assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4634 /* Assemble a NOP of the requested size in the buffer. User must have
4635 allocated "buf" with at least "size" bytes. */
4638 assemble_nop (int size
, char *buf
)
4640 static xtensa_insnbuf insnbuf
= NULL
;
4643 build_nop (&tinsn
, size
);
4646 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4648 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4649 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4650 (unsigned char *) buf
, 0);
4654 /* Return the number of bytes for the offset of the expanded loop
4655 instruction. This should be incorporated into the relaxation
4656 specification but is hard-coded here. This is used to auto-align
4657 the loop instruction. It is invalid to call this function if the
4658 configuration does not have loops or if the opcode is not a loop
4662 get_expanded_loop_offset (xtensa_opcode opcode
)
4664 /* This is the OFFSET of the loop instruction in the expanded loop.
4665 This MUST correspond directly to the specification of the loop
4666 expansion. It will be validated on fragment conversion. */
4667 assert (opcode
!= XTENSA_UNDEFINED
);
4668 if (opcode
== xtensa_loop_opcode
)
4670 if (opcode
== xtensa_loopnez_opcode
)
4672 if (opcode
== xtensa_loopgtz_opcode
)
4674 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4680 get_literal_pool_location (segT seg
)
4682 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4687 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4689 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4693 /* Set frag assembly state should be called when a new frag is
4694 opened and after a frag has been closed. */
4697 xtensa_set_frag_assembly_state (fragS
*fragP
)
4699 if (!density_supported
)
4700 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4702 /* This function is called from subsegs_finish, which is called
4703 after xtensa_end, so we can't use "use_transform" or
4704 "use_schedule" here. */
4705 if (!directive_state
[directive_transform
])
4706 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4707 if (directive_state
[directive_longcalls
])
4708 fragP
->tc_frag_data
.use_longcalls
= TRUE
;
4709 fragP
->tc_frag_data
.use_absolute_literals
=
4710 directive_state
[directive_absolute_literals
];
4711 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4716 relaxable_section (asection
*sec
)
4718 return (sec
->flags
& SEC_DEBUGGING
) == 0;
4723 xtensa_find_unmarked_state_frags (void)
4727 /* Walk over each fragment of all of the current segments. For each
4728 unmarked fragment, mark it with the same info as the previous
4730 for (seclist
= &stdoutput
->sections
;
4731 seclist
&& *seclist
;
4732 seclist
= &(*seclist
)->next
)
4734 segT sec
= *seclist
;
4735 segment_info_type
*seginfo
;
4738 flags
= bfd_get_section_flags (stdoutput
, sec
);
4739 if (flags
& SEC_DEBUGGING
)
4741 if (!(flags
& SEC_ALLOC
))
4744 seginfo
= seg_info (sec
);
4745 if (seginfo
&& seginfo
->frchainP
)
4747 fragS
*last_fragP
= 0;
4748 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4749 fragP
= fragP
->fr_next
)
4751 if (fragP
->fr_fix
!= 0
4752 && !fragP
->tc_frag_data
.is_assembly_state_set
)
4754 if (last_fragP
== 0)
4756 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
4757 _("assembly state not set for first frag in section %s"),
4762 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4763 fragP
->tc_frag_data
.is_no_density
=
4764 last_fragP
->tc_frag_data
.is_no_density
;
4765 fragP
->tc_frag_data
.is_no_transform
=
4766 last_fragP
->tc_frag_data
.is_no_transform
;
4767 fragP
->tc_frag_data
.use_longcalls
=
4768 last_fragP
->tc_frag_data
.use_longcalls
;
4769 fragP
->tc_frag_data
.use_absolute_literals
=
4770 last_fragP
->tc_frag_data
.use_absolute_literals
;
4773 if (fragP
->tc_frag_data
.is_assembly_state_set
)
4782 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
4784 void *unused ATTRIBUTE_UNUSED
)
4786 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4787 segment_info_type
*seginfo
= seg_info (sec
);
4788 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4790 if (flags
& SEC_CODE
)
4792 xtensa_isa isa
= xtensa_default_isa
;
4793 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4794 while (frag
!= NULL
)
4796 if (frag
->tc_frag_data
.is_branch_target
)
4799 addressT branch_align
, frag_addr
;
4802 xtensa_insnbuf_from_chars
4803 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4804 fmt
= xtensa_format_decode (isa
, insnbuf
);
4805 op_size
= xtensa_format_length (isa
, fmt
);
4806 branch_align
= 1 << branch_align_power (sec
);
4807 frag_addr
= frag
->fr_address
% branch_align
;
4808 if (frag_addr
+ op_size
> branch_align
)
4809 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4810 _("unaligned branch target: %d bytes at 0x%lx"),
4811 op_size
, (long) frag
->fr_address
);
4813 frag
= frag
->fr_next
;
4815 xtensa_insnbuf_free (isa
, insnbuf
);
4821 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
4823 void *unused ATTRIBUTE_UNUSED
)
4825 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4826 segment_info_type
*seginfo
= seg_info (sec
);
4827 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4828 xtensa_isa isa
= xtensa_default_isa
;
4830 if (flags
& SEC_CODE
)
4832 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4833 while (frag
!= NULL
)
4835 if (frag
->tc_frag_data
.is_first_loop_insn
)
4841 xtensa_insnbuf_from_chars
4842 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4843 fmt
= xtensa_format_decode (isa
, insnbuf
);
4844 op_size
= xtensa_format_length (isa
, fmt
);
4845 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
4847 if (frag_addr
+ op_size
> xtensa_fetch_width
)
4848 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4849 _("unaligned loop: %d bytes at 0x%lx"),
4850 op_size
, (long) frag
->fr_address
);
4852 frag
= frag
->fr_next
;
4854 xtensa_insnbuf_free (isa
, insnbuf
);
4860 xg_apply_fix_value (fixS
*fixP
, valueT val
)
4862 xtensa_isa isa
= xtensa_default_isa
;
4863 static xtensa_insnbuf insnbuf
= NULL
;
4864 static xtensa_insnbuf slotbuf
= NULL
;
4867 bfd_boolean alt_reloc
;
4868 xtensa_opcode opcode
;
4869 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
4871 (void) decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
);
4873 as_fatal (_("unexpected fix"));
4877 insnbuf
= xtensa_insnbuf_alloc (isa
);
4878 slotbuf
= xtensa_insnbuf_alloc (isa
);
4881 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4882 fmt
= xtensa_format_decode (isa
, insnbuf
);
4883 if (fmt
== XTENSA_UNDEFINED
)
4884 as_fatal (_("undecodable fix"));
4885 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4886 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
4887 if (opcode
== XTENSA_UNDEFINED
)
4888 as_fatal (_("undecodable fix"));
4890 /* CONST16 immediates are not PC-relative, despite the fact that we
4891 reuse the normal PC-relative operand relocations for the low part
4892 of a CONST16 operand. */
4893 if (opcode
== xtensa_const16_opcode
)
4896 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
4897 get_relaxable_immed (opcode
), val
,
4898 fixP
->fx_file
, fixP
->fx_line
);
4900 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4901 xtensa_insnbuf_to_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4907 /* External Functions and Other GAS Hooks. */
4910 xtensa_target_format (void)
4912 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
4917 xtensa_file_arch_init (bfd
*abfd
)
4919 bfd_set_private_flags (abfd
, 0x100 | 0x200);
4924 md_number_to_chars (char *buf
, valueT val
, int n
)
4926 if (target_big_endian
)
4927 number_to_chars_bigendian (buf
, val
, n
);
4929 number_to_chars_littleendian (buf
, val
, n
);
4933 /* This function is called once, at assembler startup time. It should
4934 set up all the tables, etc. that the MD part of the assembler will
4940 segT current_section
= now_seg
;
4941 int current_subsec
= now_subseg
;
4944 xtensa_default_isa
= xtensa_isa_init (0, 0);
4945 isa
= xtensa_default_isa
;
4949 /* Set up the .literal, .fini.literal and .init.literal sections. */
4950 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
4951 default_lit_sections
.init_lit_seg_name
= INIT_LITERAL_SECTION_NAME
;
4952 default_lit_sections
.fini_lit_seg_name
= FINI_LITERAL_SECTION_NAME
;
4953 default_lit_sections
.lit_seg_name
= LITERAL_SECTION_NAME
;
4954 default_lit_sections
.lit4_seg_name
= LIT4_SECTION_NAME
;
4956 subseg_set (current_section
, current_subsec
);
4958 xg_init_vinsn (&cur_vinsn
);
4960 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
4961 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
4962 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
4963 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
4964 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
4965 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
4966 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
4967 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
4968 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
4969 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
4970 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
4971 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
4972 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
4973 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
4974 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
4975 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
4976 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
4977 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
4978 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
4979 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
4980 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
4981 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
4982 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
4983 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
4984 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
4985 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
4986 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
4987 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
4988 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
4990 init_op_placement_info_table ();
4992 /* Set up the assembly state. */
4993 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
4994 xtensa_set_frag_assembly_state (frag_now
);
4998 /* TC_INIT_FIX_DATA hook */
5001 xtensa_init_fix_data (fixS
*x
)
5003 x
->tc_fix_data
.slot
= 0;
5004 x
->tc_fix_data
.X_add_symbol
= NULL
;
5005 x
->tc_fix_data
.X_add_number
= 0;
5009 /* tc_frob_label hook */
5012 xtensa_frob_label (symbolS
*sym
)
5016 if (cur_vinsn
.inside_bundle
)
5018 as_bad (_("labels are not valid inside bundles"));
5022 freq
= get_subseg_target_freq (now_seg
, now_subseg
);
5024 /* Since the label was already attached to a frag associated with the
5025 previous basic block, it now needs to be reset to the current frag. */
5026 symbol_set_frag (sym
, frag_now
);
5027 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5029 if (generating_literals
)
5030 xtensa_add_literal_sym (sym
);
5032 xtensa_add_insn_label (sym
);
5034 if (symbol_get_tc (sym
)->is_loop_target
)
5036 if ((get_last_insn_flags (now_seg
, now_subseg
)
5037 & FLAG_IS_BAD_LOOPEND
) != 0)
5038 as_bad (_("invalid last instruction for a zero-overhead loop"));
5040 xtensa_set_frag_assembly_state (frag_now
);
5041 frag_var (rs_machine_dependent
, 4, 4, RELAX_LOOP_END
,
5042 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5044 xtensa_set_frag_assembly_state (frag_now
);
5045 xtensa_move_labels (frag_now
, 0, TRUE
);
5048 /* No target aligning in the absolute section. */
5049 if (now_seg
!= absolute_section
5050 && do_align_targets ()
5051 && !is_unaligned_label (sym
)
5052 && !generating_literals
)
5054 xtensa_set_frag_assembly_state (frag_now
);
5056 frag_var (rs_machine_dependent
,
5058 RELAX_DESIRE_ALIGN_IF_TARGET
,
5059 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5060 xtensa_set_frag_assembly_state (frag_now
);
5061 xtensa_move_labels (frag_now
, 0, TRUE
);
5064 /* We need to mark the following properties even if we aren't aligning. */
5066 /* If the label is already known to be a branch target, i.e., a
5067 forward branch, mark the frag accordingly. Backward branches
5068 are handled by xg_add_branch_and_loop_targets. */
5069 if (symbol_get_tc (sym
)->is_branch_target
)
5070 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5072 /* Loops only go forward, so they can be identified here. */
5073 if (symbol_get_tc (sym
)->is_loop_target
)
5074 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5076 dwarf2_emit_label (sym
);
5080 /* tc_unrecognized_line hook */
5083 xtensa_unrecognized_line (int ch
)
5088 if (cur_vinsn
.inside_bundle
== 0)
5090 /* PR8110: Cannot emit line number info inside a FLIX bundle
5091 when using --gstabs. Temporarily disable debug info. */
5092 generate_lineno_debug ();
5093 if (debug_type
== DEBUG_STABS
)
5095 xt_saved_debug_type
= debug_type
;
5096 debug_type
= DEBUG_NONE
;
5099 cur_vinsn
.inside_bundle
= 1;
5103 as_bad (_("extra opening brace"));
5109 if (cur_vinsn
.inside_bundle
)
5110 finish_vinsn (&cur_vinsn
);
5113 as_bad (_("extra closing brace"));
5118 as_bad (_("syntax error"));
5125 /* md_flush_pending_output hook */
5128 xtensa_flush_pending_output (void)
5130 if (cur_vinsn
.inside_bundle
)
5131 as_bad (_("missing closing brace"));
5133 /* If there is a non-zero instruction fragment, close it. */
5134 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5136 frag_wane (frag_now
);
5138 xtensa_set_frag_assembly_state (frag_now
);
5140 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5142 xtensa_clear_insn_labels ();
5146 /* We had an error while parsing an instruction. The string might look
5147 like this: "insn arg1, arg2 }". If so, we need to see the closing
5148 brace and reset some fields. Otherwise, the vinsn never gets closed
5149 and the num_slots field will grow past the end of the array of slots,
5150 and bad things happen. */
5153 error_reset_cur_vinsn (void)
5155 if (cur_vinsn
.inside_bundle
)
5157 if (*input_line_pointer
== '}'
5158 || *(input_line_pointer
- 1) == '}'
5159 || *(input_line_pointer
- 2) == '}')
5160 xg_clear_vinsn (&cur_vinsn
);
5166 md_assemble (char *str
)
5168 xtensa_isa isa
= xtensa_default_isa
;
5169 char *opname
, *file_name
;
5171 bfd_boolean has_underbar
= FALSE
;
5172 char *arg_strings
[MAX_INSN_ARGS
];
5174 TInsn orig_insn
; /* Original instruction from the input. */
5176 tinsn_init (&orig_insn
);
5178 /* Split off the opcode. */
5179 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5180 opname
= xmalloc (opnamelen
+ 1);
5181 memcpy (opname
, str
, opnamelen
);
5182 opname
[opnamelen
] = '\0';
5184 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5187 as_bad (_("syntax error"));
5191 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5194 /* Check for an underbar prefix. */
5197 has_underbar
= TRUE
;
5201 orig_insn
.insn_type
= ITYPE_INSN
;
5203 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5205 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5206 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5208 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5209 if (fmt
== XTENSA_UNDEFINED
)
5211 as_bad (_("unknown opcode or format name '%s'"), opname
);
5212 error_reset_cur_vinsn ();
5215 if (!cur_vinsn
.inside_bundle
)
5217 as_bad (_("format names only valid inside bundles"));
5218 error_reset_cur_vinsn ();
5221 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5222 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5224 cur_vinsn
.format
= fmt
;
5225 free (has_underbar
? opname
- 1 : opname
);
5226 error_reset_cur_vinsn ();
5230 /* Parse the arguments. */
5231 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5233 as_bad (_("syntax error"));
5234 error_reset_cur_vinsn ();
5238 /* Free the opcode and argument strings, now that they've been parsed. */
5239 free (has_underbar
? opname
- 1 : opname
);
5241 while (num_args
-- > 0)
5242 free (arg_strings
[num_args
]);
5244 /* Get expressions for invisible operands. */
5245 if (get_invisible_operands (&orig_insn
))
5247 error_reset_cur_vinsn ();
5251 /* Check for the right number and type of arguments. */
5252 if (tinsn_check_arguments (&orig_insn
))
5254 error_reset_cur_vinsn ();
5258 /* A FLIX bundle may be spread across multiple input lines. We want to
5259 report the first such line in the debug information. Record the line
5260 number for each TInsn (assume the file name doesn't change), so the
5261 first line can be found later. */
5262 as_where (&file_name
, &orig_insn
.linenum
);
5264 xg_add_branch_and_loop_targets (&orig_insn
);
5266 /* Check that immediate value for ENTRY is >= 16. */
5267 if (orig_insn
.opcode
== xtensa_entry_opcode
&& orig_insn
.ntok
>= 3)
5269 expressionS
*exp
= &orig_insn
.tok
[2];
5270 if (exp
->X_op
== O_constant
&& exp
->X_add_number
< 16)
5271 as_warn (_("entry instruction with stack decrement < 16"));
5275 assemble_tokens (opcode, tok, ntok);
5276 expand the tokens from the orig_insn into the
5277 stack of instructions that will not expand
5278 unless required at relaxation time. */
5280 if (!cur_vinsn
.inside_bundle
)
5281 emit_single_op (&orig_insn
);
5282 else /* We are inside a bundle. */
5284 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5285 cur_vinsn
.num_slots
++;
5286 if (*input_line_pointer
== '}'
5287 || *(input_line_pointer
- 1) == '}'
5288 || *(input_line_pointer
- 2) == '}')
5289 finish_vinsn (&cur_vinsn
);
5292 /* We've just emitted a new instruction so clear the list of labels. */
5293 xtensa_clear_insn_labels ();
5297 /* HANDLE_ALIGN hook */
5299 /* For a .align directive, we mark the previous block with the alignment
5300 information. This will be placed in the object file in the
5301 property section corresponding to this section. */
5304 xtensa_handle_align (fragS
*fragP
)
5307 && ! fragP
->tc_frag_data
.is_literal
5308 && (fragP
->fr_type
== rs_align
5309 || fragP
->fr_type
== rs_align_code
)
5310 && fragP
->fr_address
+ fragP
->fr_fix
> 0
5311 && fragP
->fr_offset
> 0
5312 && now_seg
!= bss_section
)
5314 fragP
->tc_frag_data
.is_align
= TRUE
;
5315 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5318 if (fragP
->fr_type
== rs_align_test
)
5321 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5323 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5324 _("unaligned entry instruction"));
5329 /* TC_FRAG_INIT hook */
5332 xtensa_frag_init (fragS
*frag
)
5334 xtensa_set_frag_assembly_state (frag
);
5339 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5345 /* Round up a section size to the appropriate boundary. */
5348 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5350 return size
; /* Byte alignment is fine. */
5355 md_pcrel_from (fixS
*fixP
)
5358 static xtensa_insnbuf insnbuf
= NULL
;
5359 static xtensa_insnbuf slotbuf
= NULL
;
5362 xtensa_opcode opcode
;
5365 xtensa_isa isa
= xtensa_default_isa
;
5366 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5367 bfd_boolean alt_reloc
;
5369 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5374 insnbuf
= xtensa_insnbuf_alloc (isa
);
5375 slotbuf
= xtensa_insnbuf_alloc (isa
);
5378 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5379 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) insn_p
, 0);
5380 fmt
= xtensa_format_decode (isa
, insnbuf
);
5382 if (fmt
== XTENSA_UNDEFINED
)
5383 as_fatal (_("bad instruction format"));
5385 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5386 as_fatal (_("invalid relocation"));
5388 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5389 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5391 /* Check for "alternate" relocations (operand not specified). None
5392 of the current uses for these are really PC-relative. */
5393 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5395 if (opcode
!= xtensa_l32r_opcode
5396 && opcode
!= xtensa_const16_opcode
)
5397 as_fatal (_("invalid relocation for '%s' instruction"),
5398 xtensa_opcode_name (isa
, opcode
));
5402 opnum
= get_relaxable_immed (opcode
);
5404 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5405 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5407 as_bad_where (fixP
->fx_file
,
5409 _("invalid relocation for operand %d of '%s'"),
5410 opnum
, xtensa_opcode_name (isa
, opcode
));
5413 return 0 - opnd_value
;
5417 /* TC_FORCE_RELOCATION hook */
5420 xtensa_force_relocation (fixS
*fix
)
5422 switch (fix
->fx_r_type
)
5424 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5425 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5426 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5427 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5428 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5429 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5430 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5431 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5432 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5433 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5434 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5435 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5436 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5437 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5438 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5439 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5445 if (linkrelax
&& fix
->fx_addsy
5446 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5449 return generic_force_reloc (fix
);
5453 /* TC_VALIDATE_FIX_SUB hook */
5456 xtensa_validate_fix_sub (fixS
*fix
)
5458 segT add_symbol_segment
, sub_symbol_segment
;
5460 /* The difference of two symbols should be resolved by the assembler when
5461 linkrelax is not set. If the linker may relax the section containing
5462 the symbols, then an Xtensa DIFF relocation must be generated so that
5463 the linker knows to adjust the difference value. */
5464 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
5467 /* Make sure both symbols are in the same segment, and that segment is
5468 "normal" and relaxable. If the segment is not "normal", then the
5469 fix is not valid. If the segment is not "relaxable", then the fix
5470 should have been handled earlier. */
5471 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
5472 if (! SEG_NORMAL (add_symbol_segment
) ||
5473 ! relaxable_section (add_symbol_segment
))
5475 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
5476 return (sub_symbol_segment
== add_symbol_segment
);
5480 /* NO_PSEUDO_DOT hook */
5482 /* This function has nothing to do with pseudo dots, but this is the
5483 nearest macro to where the check needs to take place. FIXME: This
5487 xtensa_check_inside_bundle (void)
5489 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5490 as_bad (_("directives are not valid inside bundles"));
5492 /* This function must always return FALSE because it is called via a
5493 macro that has nothing to do with bundling. */
5498 /* md_elf_section_change_hook */
5501 xtensa_elf_section_change_hook (void)
5503 /* Set up the assembly state. */
5504 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5505 xtensa_set_frag_assembly_state (frag_now
);
5509 /* tc_fix_adjustable hook */
5512 xtensa_fix_adjustable (fixS
*fixP
)
5514 /* An offset is not allowed in combination with the difference of two
5515 symbols, but that cannot be easily detected after a local symbol
5516 has been adjusted to a (section+offset) form. Return 0 so that such
5517 an fix will not be adjusted. */
5518 if (fixP
->fx_subsy
&& fixP
->fx_addsy
&& fixP
->fx_offset
5519 && relaxable_section (S_GET_SEGMENT (fixP
->fx_subsy
)))
5522 /* We need the symbol name for the VTABLE entries. */
5523 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5524 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5532 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg
)
5534 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5537 /* Subtracted symbols are only allowed for a few relocation types, and
5538 unless linkrelax is enabled, they should not make it to this point. */
5539 if (fixP
->fx_subsy
&& !(linkrelax
&& (fixP
->fx_r_type
== BFD_RELOC_32
5540 || fixP
->fx_r_type
== BFD_RELOC_16
5541 || fixP
->fx_r_type
== BFD_RELOC_8
)))
5542 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("expression too complex"));
5544 switch (fixP
->fx_r_type
)
5551 switch (fixP
->fx_r_type
)
5554 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF8
;
5557 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF16
;
5560 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF32
;
5566 /* An offset is only allowed when it results from adjusting a
5567 local symbol into a section-relative offset. If the offset
5568 came from the original expression, tc_fix_adjustable will have
5569 prevented the fix from being converted to a section-relative
5570 form so that we can flag the error here. */
5571 if (fixP
->fx_offset
!= 0 && !symbol_section_p (fixP
->fx_addsy
))
5572 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5573 _("cannot represent subtraction with an offset"));
5575 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5576 - S_GET_VALUE (fixP
->fx_subsy
));
5578 /* The difference value gets written out, and the DIFF reloc
5579 identifies the address of the subtracted symbol (i.e., the one
5580 with the lowest address). */
5582 fixP
->fx_offset
-= val
;
5583 fixP
->fx_subsy
= NULL
;
5585 else if (! fixP
->fx_addsy
)
5592 case BFD_RELOC_XTENSA_PLT
:
5593 md_number_to_chars (fixpos
, val
, fixP
->fx_size
);
5594 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5597 case BFD_RELOC_XTENSA_SLOT0_OP
:
5598 case BFD_RELOC_XTENSA_SLOT1_OP
:
5599 case BFD_RELOC_XTENSA_SLOT2_OP
:
5600 case BFD_RELOC_XTENSA_SLOT3_OP
:
5601 case BFD_RELOC_XTENSA_SLOT4_OP
:
5602 case BFD_RELOC_XTENSA_SLOT5_OP
:
5603 case BFD_RELOC_XTENSA_SLOT6_OP
:
5604 case BFD_RELOC_XTENSA_SLOT7_OP
:
5605 case BFD_RELOC_XTENSA_SLOT8_OP
:
5606 case BFD_RELOC_XTENSA_SLOT9_OP
:
5607 case BFD_RELOC_XTENSA_SLOT10_OP
:
5608 case BFD_RELOC_XTENSA_SLOT11_OP
:
5609 case BFD_RELOC_XTENSA_SLOT12_OP
:
5610 case BFD_RELOC_XTENSA_SLOT13_OP
:
5611 case BFD_RELOC_XTENSA_SLOT14_OP
:
5614 /* Write the tentative value of a PC-relative relocation to a
5615 local symbol into the instruction. The value will be ignored
5616 by the linker, and it makes the object file disassembly
5617 readable when all branch targets are encoded in relocations. */
5619 assert (fixP
->fx_addsy
);
5620 if (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
&& !fixP
->fx_plt
5621 && !S_FORCE_RELOC (fixP
->fx_addsy
, 1))
5623 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5624 - md_pcrel_from (fixP
));
5625 (void) xg_apply_fix_value (fixP
, val
);
5628 else if (! fixP
->fx_addsy
)
5631 if (xg_apply_fix_value (fixP
, val
))
5636 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5637 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5638 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5639 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5640 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5641 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5642 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5643 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5644 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5645 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5646 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5647 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5648 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5649 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5650 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5651 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5652 /* These all need to be resolved at link-time. Do nothing now. */
5655 case BFD_RELOC_VTABLE_INHERIT
:
5656 case BFD_RELOC_VTABLE_ENTRY
:
5661 as_bad (_("unhandled local relocation fix %s"),
5662 bfd_get_reloc_code_name (fixP
->fx_r_type
));
5668 md_atof (int type
, char *litP
, int *sizeP
)
5671 LITTLENUM_TYPE words
[4];
5687 return "bad call to md_atof";
5690 t
= atof_ieee (input_line_pointer
, type
, words
);
5692 input_line_pointer
= t
;
5696 for (i
= prec
- 1; i
>= 0; i
--)
5699 if (target_big_endian
)
5700 idx
= (prec
- 1 - i
);
5702 md_number_to_chars (litP
, (valueT
) words
[idx
], 2);
5711 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
5713 return total_frag_text_expansion (fragP
);
5717 /* Translate internal representation of relocation info to BFD target
5721 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
5725 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
5726 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5727 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5728 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5730 /* Make sure none of our internal relocations make it this far.
5731 They'd better have been fully resolved by this point. */
5732 assert ((int) fixp
->fx_r_type
> 0);
5734 reloc
->addend
= fixp
->fx_offset
;
5736 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
5737 if (reloc
->howto
== NULL
)
5739 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5740 _("cannot represent `%s' relocation in object file"),
5741 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5742 free (reloc
->sym_ptr_ptr
);
5747 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
5748 as_fatal (_("internal error? cannot generate `%s' relocation"),
5749 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5755 /* Checks for resource conflicts between instructions. */
5757 /* The func unit stuff could be implemented as bit-vectors rather
5758 than the iterative approach here. If it ends up being too
5759 slow, we will switch it. */
5762 new_resource_table (void *data
,
5765 unit_num_copies_func uncf
,
5766 opcode_num_units_func onuf
,
5767 opcode_funcUnit_use_unit_func ouuf
,
5768 opcode_funcUnit_use_stage_func ousf
)
5771 resource_table
*rt
= (resource_table
*) xmalloc (sizeof (resource_table
));
5773 rt
->cycles
= cycles
;
5774 rt
->allocated_cycles
= cycles
;
5776 rt
->unit_num_copies
= uncf
;
5777 rt
->opcode_num_units
= onuf
;
5778 rt
->opcode_unit_use
= ouuf
;
5779 rt
->opcode_unit_stage
= ousf
;
5781 rt
->units
= (unsigned char **) xcalloc (cycles
, sizeof (unsigned char *));
5782 for (i
= 0; i
< cycles
; i
++)
5783 rt
->units
[i
] = (unsigned char *) xcalloc (nu
, sizeof (unsigned char));
5790 clear_resource_table (resource_table
*rt
)
5793 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
5794 for (j
= 0; j
< rt
->num_units
; j
++)
5795 rt
->units
[i
][j
] = 0;
5799 /* We never shrink it, just fake it into thinking so. */
5802 resize_resource_table (resource_table
*rt
, int cycles
)
5806 rt
->cycles
= cycles
;
5807 if (cycles
<= rt
->allocated_cycles
)
5810 old_cycles
= rt
->allocated_cycles
;
5811 rt
->allocated_cycles
= cycles
;
5813 rt
->units
= xrealloc (rt
->units
,
5814 rt
->allocated_cycles
* sizeof (unsigned char *));
5815 for (i
= 0; i
< old_cycles
; i
++)
5816 rt
->units
[i
] = xrealloc (rt
->units
[i
],
5817 rt
->num_units
* sizeof (unsigned char));
5818 for (i
= old_cycles
; i
< cycles
; i
++)
5819 rt
->units
[i
] = xcalloc (rt
->num_units
, sizeof (unsigned char));
5824 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5827 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5829 for (i
= 0; i
< uses
; i
++)
5831 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5832 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5833 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
5834 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
5835 if (copies_in_use
>= copies
)
5843 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5846 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5848 for (i
= 0; i
< uses
; i
++)
5850 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5851 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5852 /* Note that this allows resources to be oversubscribed. That's
5853 essential to the way the optional scheduler works.
5854 resources_available reports when a resource is over-subscribed,
5855 so it's easy to tell. */
5856 rt
->units
[stage
+ cycle
][unit
]++;
5862 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5865 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5867 for (i
= 0; i
< uses
; i
++)
5869 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5870 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5871 assert (rt
->units
[stage
+ cycle
][unit
] > 0);
5872 rt
->units
[stage
+ cycle
][unit
]--;
5877 /* Wrapper functions make parameterized resource reservation
5881 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
5883 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5889 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
5891 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5896 /* Note that this function does not check issue constraints, but
5897 solely whether the hardware is available to execute the given
5898 instructions together. It also doesn't check if the tinsns
5899 write the same state, or access the same tieports. That is
5900 checked by check_t1_t2_reads_and_writes. */
5903 resources_conflict (vliw_insn
*vinsn
)
5906 static resource_table
*rt
= NULL
;
5908 /* This is the most common case by far. Optimize it. */
5909 if (vinsn
->num_slots
== 1)
5914 xtensa_isa isa
= xtensa_default_isa
;
5915 rt
= new_resource_table
5916 (isa
, xtensa_isa_num_pipe_stages (isa
),
5917 xtensa_isa_num_funcUnits (isa
),
5918 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
5919 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
5920 opcode_funcUnit_use_unit
,
5921 opcode_funcUnit_use_stage
);
5924 clear_resource_table (rt
);
5926 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5928 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
5930 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
5937 /* finish_vinsn, emit_single_op and helper functions. */
5939 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
5940 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
5941 static void xg_assemble_vliw_tokens (vliw_insn
*);
5944 /* We have reached the end of a bundle; emit into the frag. */
5947 finish_vinsn (vliw_insn
*vinsn
)
5954 if (find_vinsn_conflicts (vinsn
))
5956 xg_clear_vinsn (vinsn
);
5960 /* First, find a format that works. */
5961 if (vinsn
->format
== XTENSA_UNDEFINED
)
5962 vinsn
->format
= xg_find_narrowest_format (vinsn
);
5964 if (vinsn
->format
== XTENSA_UNDEFINED
)
5966 as_where (&file_name
, &line
);
5967 as_bad_where (file_name
, line
,
5968 _("couldn't find a valid instruction format"));
5969 fprintf (stderr
, _(" ops were: "));
5970 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5971 fprintf (stderr
, _(" %s;"),
5972 xtensa_opcode_name (xtensa_default_isa
,
5973 vinsn
->slots
[i
].opcode
));
5974 fprintf (stderr
, _("\n"));
5975 xg_clear_vinsn (vinsn
);
5979 if (vinsn
->num_slots
5980 != xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
))
5982 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
5983 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
5984 xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
),
5986 xg_clear_vinsn (vinsn
);
5990 if (resources_conflict (vinsn
))
5992 as_where (&file_name
, &line
);
5993 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
5994 fprintf (stderr
, " ops were: ");
5995 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5996 fprintf (stderr
, " %s;",
5997 xtensa_opcode_name (xtensa_default_isa
,
5998 vinsn
->slots
[i
].opcode
));
5999 fprintf (stderr
, "\n");
6000 xg_clear_vinsn (vinsn
);
6004 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6006 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
6008 symbolS
*lit_sym
= NULL
;
6010 bfd_boolean e
= FALSE
;
6011 bfd_boolean saved_density
= density_supported
;
6013 /* We don't want to narrow ops inside multi-slot bundles. */
6014 if (vinsn
->num_slots
> 1)
6015 density_supported
= FALSE
;
6017 istack_init (&slotstack
);
6018 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
6020 vinsn
->slots
[i
].opcode
=
6021 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6023 vinsn
->slots
[i
].ntok
= 0;
6026 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
6032 density_supported
= saved_density
;
6036 xg_clear_vinsn (vinsn
);
6040 for (j
= 0; j
< slotstack
.ninsn
; j
++)
6042 TInsn
*insn
= &slotstack
.insn
[j
];
6043 if (insn
->insn_type
== ITYPE_LITERAL
)
6045 assert (lit_sym
== NULL
);
6046 lit_sym
= xg_assemble_literal (insn
);
6050 assert (insn
->insn_type
== ITYPE_INSN
);
6052 xg_resolve_literals (insn
, lit_sym
);
6053 if (j
!= slotstack
.ninsn
- 1)
6054 emit_single_op (insn
);
6058 if (vinsn
->num_slots
> 1)
6060 if (opcode_fits_format_slot
6061 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6064 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6068 emit_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6069 if (vinsn
->format
== XTENSA_UNDEFINED
)
6070 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6072 vinsn
->slots
[i
].opcode
6073 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6076 vinsn
->slots
[i
].ntok
= 0;
6081 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6082 vinsn
->format
= XTENSA_UNDEFINED
;
6087 /* Now check resource conflicts on the modified bundle. */
6088 if (resources_conflict (vinsn
))
6090 as_where (&file_name
, &line
);
6091 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6092 fprintf (stderr
, " ops were: ");
6093 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6094 fprintf (stderr
, " %s;",
6095 xtensa_opcode_name (xtensa_default_isa
,
6096 vinsn
->slots
[i
].opcode
));
6097 fprintf (stderr
, "\n");
6098 xg_clear_vinsn (vinsn
);
6102 /* First, find a format that works. */
6103 if (vinsn
->format
== XTENSA_UNDEFINED
)
6104 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6106 xg_assemble_vliw_tokens (vinsn
);
6108 xg_clear_vinsn (vinsn
);
6112 /* Given an vliw instruction, what conflicts are there in register
6113 usage and in writes to states and queues?
6115 This function does two things:
6116 1. Reports an error when a vinsn contains illegal combinations
6117 of writes to registers states or queues.
6118 2. Marks individual tinsns as not relaxable if the combination
6119 contains antidependencies.
6121 Job 2 handles things like swap semantics in instructions that need
6122 to be relaxed. For example,
6126 normally would be relaxed to
6131 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6133 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6135 then we can't relax it into
6138 { add a0, a1, a0 ; add a2, a0, a4 ; }
6140 because the value of a0 is trashed before the second add can read it. */
6142 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6145 find_vinsn_conflicts (vliw_insn
*vinsn
)
6149 xtensa_isa isa
= xtensa_default_isa
;
6151 assert (!past_xtensa_end
);
6153 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6155 TInsn
*op1
= &vinsn
->slots
[i
];
6156 if (op1
->is_specific_opcode
)
6157 op1
->keep_wide
= TRUE
;
6159 op1
->keep_wide
= FALSE
;
6162 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6164 TInsn
*op1
= &vinsn
->slots
[i
];
6166 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6169 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6173 TInsn
*op2
= &vinsn
->slots
[j
];
6174 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6175 switch (conflict_type
)
6178 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6179 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6180 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6183 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6184 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6185 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6188 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"),
6189 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6190 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6193 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"),
6194 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6195 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6198 /* Everything is OK. */
6201 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6202 || conflict_type
== 'a');
6209 as_bad (_("multiple branches or jumps in the same bundle"));
6217 /* Check how the state used by t1 and t2 relate.
6220 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6221 case B: no relationship between what is read and written (both could
6222 read the same reg though)
6223 case C: t1 writes a register t2 writes (a register conflict within a
6225 case D: t1 writes a state that t2 also writes
6226 case E: t1 writes a tie queue that t2 also writes
6227 case F: two volatile queue accesses
6231 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6233 xtensa_isa isa
= xtensa_default_isa
;
6234 xtensa_regfile t1_regfile
, t2_regfile
;
6236 int t1_base_reg
, t1_last_reg
;
6237 int t2_base_reg
, t2_last_reg
;
6238 char t1_inout
, t2_inout
;
6240 char conflict
= 'b';
6245 bfd_boolean t1_volatile
= FALSE
;
6246 bfd_boolean t2_volatile
= FALSE
;
6248 /* Check registers. */
6249 for (j
= 0; j
< t2
->ntok
; j
++)
6251 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6254 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6255 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6256 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6258 for (i
= 0; i
< t1
->ntok
; i
++)
6260 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6263 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6265 if (t1_regfile
!= t2_regfile
)
6268 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6269 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6271 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6272 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6274 if (t1_inout
== 'm' || t1_inout
== 'o'
6275 || t2_inout
== 'm' || t2_inout
== 'o')
6282 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6283 t1_last_reg
= (t1_base_reg
6284 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6286 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6288 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6290 if (t1_reg
!= t2_reg
)
6293 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6299 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6305 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6313 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6314 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6315 for (j
= 0; j
< t2_states
; j
++)
6317 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6318 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6319 for (i
= 0; i
< t1_states
; i
++)
6321 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6322 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6326 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6332 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6338 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6343 /* Check tieports. */
6344 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6345 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6346 for (j
= 0; j
< t2_interfaces
; j
++)
6348 xtensa_interface t2_int
6349 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6350 int t2_class
= xtensa_interface_class_id (isa
, t2_int
);
6352 t2_inout
= xtensa_interface_inout (isa
, t2_int
);
6353 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1)
6356 for (i
= 0; i
< t1_interfaces
; i
++)
6358 xtensa_interface t1_int
6359 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6360 int t1_class
= xtensa_interface_class_id (isa
, t1_int
);
6362 t1_inout
= xtensa_interface_inout (isa
, t1_int
);
6363 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1)
6366 if (t1_volatile
&& t2_volatile
&& (t1_class
== t2_class
))
6369 if (t1_int
!= t2_int
)
6372 if (t2_inout
== 'i' && t1_inout
== 'o')
6378 if (t1_inout
== 'i' && t2_inout
== 'o')
6384 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6393 static xtensa_format
6394 xg_find_narrowest_format (vliw_insn
*vinsn
)
6396 /* Right now we assume that the ops within the vinsn are properly
6397 ordered for the slots that the programmer wanted them in. In
6398 other words, we don't rearrange the ops in hopes of finding a
6399 better format. The scheduler handles that. */
6401 xtensa_isa isa
= xtensa_default_isa
;
6402 xtensa_format format
;
6403 vliw_insn v_copy
= *vinsn
;
6404 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6406 if (vinsn
->num_slots
== 1)
6407 return xg_get_single_format (vinsn
->slots
[0].opcode
);
6409 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6412 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6416 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6418 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6420 v_copy
.slots
[slot
].opcode
=
6421 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6422 v_copy
.slots
[slot
].ntok
= 0;
6425 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6428 else if (v_copy
.num_slots
> 1)
6431 /* Try the widened version. */
6432 if (!v_copy
.slots
[slot
].keep_wide
6433 && !v_copy
.slots
[slot
].is_specific_opcode
6434 && xg_is_single_relaxable_insn (&v_copy
.slots
[slot
],
6436 && opcode_fits_format_slot (widened
.opcode
,
6439 v_copy
.slots
[slot
] = widened
;
6444 if (fit
== v_copy
.num_slots
)
6447 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6448 vinsn
->format
= format
;
6454 if (format
== xtensa_isa_num_formats (isa
))
6455 return XTENSA_UNDEFINED
;
6461 /* Return the additional space needed in a frag
6462 for possible relaxations of any ops in a VLIW insn.
6463 Also fill out the relaxations that might be required of
6464 each tinsn in the vinsn. */
6467 relaxation_requirements (vliw_insn
*vinsn
, bfd_boolean
*pfinish_frag
)
6469 bfd_boolean finish_frag
= FALSE
;
6470 int extra_space
= 0;
6473 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6475 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6476 if (!tinsn_has_symbolic_operands (tinsn
))
6478 /* A narrow instruction could be widened later to help
6479 alignment issues. */
6480 if (xg_is_single_relaxable_insn (tinsn
, 0, TRUE
)
6481 && !tinsn
->is_specific_opcode
6482 && vinsn
->num_slots
== 1)
6484 /* Difference in bytes between narrow and wide insns... */
6486 tinsn
->subtype
= RELAX_NARROW
;
6491 if (workaround_b_j_loop_end
6492 && tinsn
->opcode
== xtensa_jx_opcode
6493 && use_transform ())
6495 /* Add 2 of these. */
6496 extra_space
+= 3; /* for the nop size */
6497 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6500 /* Need to assemble it with space for the relocation. */
6501 if (xg_is_relaxable_insn (tinsn
, 0)
6502 && !tinsn
->is_specific_opcode
)
6504 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6505 int max_literal_size
=
6506 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6508 tinsn
->literal_space
= max_literal_size
;
6510 tinsn
->subtype
= RELAX_IMMED
;
6511 extra_space
+= max_size
;
6515 /* A fix record will be added for this instruction prior
6516 to relaxation, so make it end the frag. */
6521 *pfinish_frag
= finish_frag
;
6527 bundle_tinsn (TInsn
*tinsn
, vliw_insn
*vinsn
)
6529 xtensa_isa isa
= xtensa_default_isa
;
6530 int slot
, chosen_slot
;
6532 vinsn
->format
= xg_get_single_format (tinsn
->opcode
);
6533 assert (vinsn
->format
!= XTENSA_UNDEFINED
);
6534 vinsn
->num_slots
= xtensa_format_num_slots (isa
, vinsn
->format
);
6536 chosen_slot
= xg_get_single_slot (tinsn
->opcode
);
6537 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6539 if (slot
== chosen_slot
)
6540 vinsn
->slots
[slot
] = *tinsn
;
6543 vinsn
->slots
[slot
].opcode
=
6544 xtensa_format_slot_nop_opcode (isa
, vinsn
->format
, slot
);
6545 vinsn
->slots
[slot
].ntok
= 0;
6546 vinsn
->slots
[slot
].insn_type
= ITYPE_INSN
;
6553 emit_single_op (TInsn
*orig_insn
)
6556 IStack istack
; /* put instructions into here */
6557 symbolS
*lit_sym
= NULL
;
6558 symbolS
*label_sym
= NULL
;
6560 istack_init (&istack
);
6562 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6563 Because the scheduling and bundling characteristics of movi and
6564 l32r or const16 are so different, we can do much better if we relax
6565 it prior to scheduling and bundling, rather than after. */
6566 if ((orig_insn
->opcode
== xtensa_movi_opcode
6567 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
6568 && !cur_vinsn
.inside_bundle
6569 && (orig_insn
->tok
[1].X_op
== O_symbol
6570 || orig_insn
->tok
[1].X_op
== O_pltrel
)
6571 && !orig_insn
->is_specific_opcode
&& use_transform ())
6572 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
6574 if (xg_expand_assembly_insn (&istack
, orig_insn
))
6577 for (i
= 0; i
< istack
.ninsn
; i
++)
6579 TInsn
*insn
= &istack
.insn
[i
];
6580 switch (insn
->insn_type
)
6583 assert (lit_sym
== NULL
);
6584 lit_sym
= xg_assemble_literal (insn
);
6588 static int relaxed_sym_idx
= 0;
6589 char *label
= xmalloc (strlen (FAKE_LABEL_NAME
) + 12);
6590 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
6592 assert (label_sym
== NULL
);
6593 label_sym
= symbol_find_or_make (label
);
6602 xg_resolve_literals (insn
, lit_sym
);
6604 xg_resolve_labels (insn
, label_sym
);
6606 bundle_tinsn (insn
, &v
);
6621 total_frag_text_expansion (fragS
*fragP
)
6624 int total_expansion
= 0;
6626 for (slot
= 0; slot
< MAX_SLOTS
; slot
++)
6627 total_expansion
+= fragP
->tc_frag_data
.text_expansion
[slot
];
6629 return total_expansion
;
6633 /* Emit a vliw instruction to the current fragment. */
6636 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
6638 bfd_boolean finish_frag
;
6639 bfd_boolean is_jump
= FALSE
;
6640 bfd_boolean is_branch
= FALSE
;
6641 xtensa_isa isa
= xtensa_default_isa
;
6647 unsigned current_line
, best_linenum
;
6650 best_linenum
= UINT_MAX
;
6652 if (generating_literals
)
6654 static int reported
= 0;
6656 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
6657 _("cannot assemble into a literal fragment"));
6664 if (frag_now_fix () != 0
6665 && (! frag_now
->tc_frag_data
.is_insn
6666 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6667 || !use_transform () != frag_now
->tc_frag_data
.is_no_transform
6668 || (directive_state
[directive_longcalls
]
6669 != frag_now
->tc_frag_data
.use_longcalls
)
6670 || (directive_state
[directive_absolute_literals
]
6671 != frag_now
->tc_frag_data
.use_absolute_literals
)))
6673 frag_wane (frag_now
);
6675 xtensa_set_frag_assembly_state (frag_now
);
6678 if (workaround_a0_b_retw
6679 && vinsn
->num_slots
== 1
6680 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
6681 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
6682 && use_transform ())
6684 has_a0_b_retw
= TRUE
;
6686 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
6687 After the first assembly pass we will check all of them and
6688 add a nop if needed. */
6689 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6690 frag_var (rs_machine_dependent
, 4, 4,
6691 RELAX_ADD_NOP_IF_A0_B_RETW
,
6692 frag_now
->fr_symbol
,
6693 frag_now
->fr_offset
,
6695 xtensa_set_frag_assembly_state (frag_now
);
6696 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6697 frag_var (rs_machine_dependent
, 4, 4,
6698 RELAX_ADD_NOP_IF_A0_B_RETW
,
6699 frag_now
->fr_symbol
,
6700 frag_now
->fr_offset
,
6702 xtensa_set_frag_assembly_state (frag_now
);
6705 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6707 /* See if the instruction implies an aligned section. */
6708 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[i
].opcode
) == 1)
6709 record_alignment (now_seg
, 2);
6711 /* Also determine the best line number for debug info. */
6712 best_linenum
= vinsn
->slots
[i
].linenum
< best_linenum
6713 ? vinsn
->slots
[i
].linenum
: best_linenum
;
6716 /* Special cases for instructions that force an alignment... */
6717 /* None of these opcodes are bundle-able. */
6718 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
6722 /* Remember the symbol that marks the end of the loop in the frag
6723 that marks the start of the loop. This way we can easily find
6724 the end of the loop at the beginning, without adding special code
6725 to mark the loop instructions themselves. */
6726 symbolS
*target_sym
= NULL
;
6727 if (vinsn
->slots
[0].tok
[1].X_op
== O_symbol
)
6728 target_sym
= vinsn
->slots
[0].tok
[1].X_add_symbol
;
6730 xtensa_set_frag_assembly_state (frag_now
);
6731 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6733 max_fill
= get_text_align_max_fill_size
6734 (get_text_align_power (xtensa_fetch_width
),
6735 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
6737 if (use_transform ())
6738 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
6739 RELAX_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
6741 frag_var (rs_machine_dependent
, 0, 0,
6742 RELAX_CHECK_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
6743 xtensa_set_frag_assembly_state (frag_now
);
6745 xtensa_move_labels (frag_now
, 0, FALSE
);
6748 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
6749 && !vinsn
->slots
[0].is_specific_opcode
)
6751 xtensa_mark_literal_pool_location ();
6752 xtensa_move_labels (frag_now
, 0, TRUE
);
6753 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
6756 if (vinsn
->num_slots
== 1)
6758 if (workaround_a0_b_retw
&& use_transform ())
6759 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
6760 is_register_writer (&vinsn
->slots
[0], "a", 0));
6762 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
6763 is_bad_loopend_opcode (&vinsn
->slots
[0]));
6766 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
6768 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
6770 extra_space
= relaxation_requirements (vinsn
, &finish_frag
);
6772 /* vinsn_to_insnbuf will produce the error. */
6773 if (vinsn
->format
!= XTENSA_UNDEFINED
)
6775 f
= frag_more (insn_size
+ extra_space
);
6776 xtensa_set_frag_assembly_state (frag_now
);
6777 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6780 vinsn_to_insnbuf (vinsn
, f
, frag_now
, FALSE
);
6781 if (vinsn
->format
== XTENSA_UNDEFINED
)
6784 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, (unsigned char *) f
, 0);
6786 /* Temporarily set the logical line number to the one we want to appear
6787 in the debug information. */
6788 as_where (¤t_file
, ¤t_line
);
6789 new_logical_line (current_file
, best_linenum
);
6790 dwarf2_emit_insn (insn_size
+ extra_space
);
6791 new_logical_line (current_file
, current_line
);
6793 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6795 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6796 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
6797 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
6798 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
6799 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
6800 if (tinsn
->literal_space
!= 0)
6801 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
6803 if (tinsn
->subtype
== RELAX_NARROW
)
6804 assert (vinsn
->num_slots
== 1);
6805 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
6807 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
6810 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->offset
6811 || tinsn
->literal_frag
|| is_jump
|| is_branch
)
6815 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6816 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
6820 frag_variant (rs_machine_dependent
,
6821 extra_space
, extra_space
, RELAX_SLOTS
,
6822 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
6823 xtensa_set_frag_assembly_state (frag_now
);
6826 /* Special cases for loops:
6827 close_loop_end should be inserted AFTER short_loop.
6828 Make sure that CLOSE loops are processed BEFORE short_loops
6829 when converting them. */
6831 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
6832 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1
6833 && !vinsn
->slots
[0].is_specific_opcode
)
6835 if (workaround_short_loop
&& use_transform ())
6837 maybe_has_short_loop
= TRUE
;
6838 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6839 frag_var (rs_machine_dependent
, 4, 4,
6840 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6841 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6842 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6843 frag_var (rs_machine_dependent
, 4, 4,
6844 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6845 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6848 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
6849 loop at least 12 bytes away from another loop's end. */
6850 if (workaround_close_loop_end
&& use_transform ())
6852 maybe_has_close_loop_end
= TRUE
;
6853 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6854 frag_var (rs_machine_dependent
, 12, 12,
6855 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
6856 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6860 if (use_transform ())
6864 assert (finish_frag
);
6865 frag_var (rs_machine_dependent
,
6866 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6868 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6869 xtensa_set_frag_assembly_state (frag_now
);
6871 else if (is_branch
&& do_align_targets ())
6873 assert (finish_frag
);
6874 frag_var (rs_machine_dependent
,
6875 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6876 RELAX_MAYBE_UNREACHABLE
,
6877 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6878 xtensa_set_frag_assembly_state (frag_now
);
6879 frag_var (rs_machine_dependent
,
6881 RELAX_MAYBE_DESIRE_ALIGN
,
6882 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6883 xtensa_set_frag_assembly_state (frag_now
);
6887 /* Now, if the original opcode was a call... */
6888 if (do_align_targets ()
6889 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
6891 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
6892 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6893 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
6894 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6895 xtensa_set_frag_assembly_state (frag_now
);
6898 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6900 frag_wane (frag_now
);
6902 xtensa_set_frag_assembly_state (frag_now
);
6907 /* xtensa_end and helper functions. */
6909 static void xtensa_cleanup_align_frags (void);
6910 static void xtensa_fix_target_frags (void);
6911 static void xtensa_mark_narrow_branches (void);
6912 static void xtensa_mark_zcl_first_insns (void);
6913 static void xtensa_fix_a0_b_retw_frags (void);
6914 static void xtensa_fix_b_j_loop_end_frags (void);
6915 static void xtensa_fix_close_loop_end_frags (void);
6916 static void xtensa_fix_short_loop_frags (void);
6917 static void xtensa_sanity_check (void);
6922 directive_balance ();
6923 xtensa_flush_pending_output ();
6925 past_xtensa_end
= TRUE
;
6927 xtensa_move_literals ();
6929 xtensa_reorder_segments ();
6930 xtensa_cleanup_align_frags ();
6931 xtensa_fix_target_frags ();
6932 if (workaround_a0_b_retw
&& has_a0_b_retw
)
6933 xtensa_fix_a0_b_retw_frags ();
6934 if (workaround_b_j_loop_end
)
6935 xtensa_fix_b_j_loop_end_frags ();
6937 /* "close_loop_end" should be processed BEFORE "short_loop". */
6938 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
6939 xtensa_fix_close_loop_end_frags ();
6941 if (workaround_short_loop
&& maybe_has_short_loop
)
6942 xtensa_fix_short_loop_frags ();
6944 xtensa_mark_narrow_branches ();
6945 xtensa_mark_zcl_first_insns ();
6947 xtensa_sanity_check ();
6952 xtensa_cleanup_align_frags (void)
6957 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
6958 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
6961 /* Walk over all of the fragments in a subsection. */
6962 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
6964 if ((fragP
->fr_type
== rs_align
6965 || fragP
->fr_type
== rs_align_code
6966 || (fragP
->fr_type
== rs_machine_dependent
6967 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
6968 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
6969 && fragP
->fr_fix
== 0)
6971 fragS
*next
= fragP
->fr_next
;
6974 && next
->fr_fix
== 0
6975 && next
->fr_type
== rs_machine_dependent
6976 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
6979 next
= next
->fr_next
;
6982 /* If we don't widen branch targets, then they
6983 will be easier to align. */
6984 if (fragP
->tc_frag_data
.is_branch_target
6985 && fragP
->fr_opcode
== fragP
->fr_literal
6986 && fragP
->fr_type
== rs_machine_dependent
6987 && fragP
->fr_subtype
== RELAX_SLOTS
6988 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
6990 if (fragP
->fr_type
== rs_machine_dependent
6991 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
6992 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
6998 /* Re-process all of the fragments looking to convert all of the
6999 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
7000 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7001 Otherwise, convert to a .fill 0. */
7004 xtensa_fix_target_frags (void)
7009 /* When this routine is called, all of the subsections are still intact
7010 so we walk over subsections instead of sections. */
7011 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7012 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7016 /* Walk over all of the fragments in a subsection. */
7017 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7019 if (fragP
->fr_type
== rs_machine_dependent
7020 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7022 if (next_frag_is_branch_target (fragP
))
7023 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7032 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
7035 xtensa_mark_narrow_branches (void)
7040 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7041 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7044 /* Walk over all of the fragments in a subsection. */
7045 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7047 if (fragP
->fr_type
== rs_machine_dependent
7048 && fragP
->fr_subtype
== RELAX_SLOTS
7049 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7053 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7054 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
7056 if (vinsn
.num_slots
== 1
7057 && xtensa_opcode_is_branch (xtensa_default_isa
,
7058 vinsn
.slots
[0].opcode
) == 1
7059 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
7060 && is_narrow_branch_guaranteed_in_range (fragP
,
7063 fragP
->fr_subtype
= RELAX_SLOTS
;
7064 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
7065 fragP
->tc_frag_data
.is_aligning_branch
= 1;
7073 /* A branch is typically widened only when its target is out of
7074 range. However, we would like to widen them to align a subsequent
7075 branch target when possible.
7077 Because the branch relaxation code is so convoluted, the optimal solution
7078 (combining the two cases) is difficult to get right in all circumstances.
7079 We therefore go with an "almost as good" solution, where we only
7080 use for alignment narrow branches that definitely will not expand to a
7081 jump and a branch. These functions find and mark these cases. */
7083 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
7084 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7085 We start counting beginning with the frag after the 2-byte branch, so the
7086 maximum offset is (4 - 2) + 63 = 65. */
7087 #define MAX_IMMED6 65
7089 static offsetT
unrelaxed_frag_max_size (fragS
*);
7092 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
7094 const expressionS
*expr
= &tinsn
->tok
[1];
7095 symbolS
*symbolP
= expr
->X_add_symbol
;
7096 offsetT max_distance
= expr
->X_add_number
;
7099 if (expr
->X_op
!= O_symbol
)
7102 target_frag
= symbol_get_frag (symbolP
);
7104 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
7105 if (is_branch_jmp_to_next (tinsn
, fragP
))
7108 /* The branch doesn't branch over it's own frag,
7109 but over the subsequent ones. */
7110 fragP
= fragP
->fr_next
;
7111 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
7113 max_distance
+= unrelaxed_frag_max_size (fragP
);
7114 fragP
= fragP
->fr_next
;
7116 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
7123 xtensa_mark_zcl_first_insns (void)
7128 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7129 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7132 /* Walk over all of the fragments in a subsection. */
7133 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7135 if (fragP
->fr_type
== rs_machine_dependent
7136 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7137 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7139 /* Find the loop frag. */
7140 fragS
*targ_frag
= next_non_empty_frag (fragP
);
7141 /* Find the first insn frag. */
7142 targ_frag
= next_non_empty_frag (targ_frag
);
7144 /* Of course, sometimes (mostly for toy test cases) a
7145 zero-cost loop instruction is the last in a section. */
7148 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
7149 /* Do not widen a frag that is the first instruction of a
7150 zero-cost loop. It makes that loop harder to align. */
7151 if (targ_frag
->fr_type
== rs_machine_dependent
7152 && targ_frag
->fr_subtype
== RELAX_SLOTS
7153 && (targ_frag
->tc_frag_data
.slot_subtypes
[0]
7156 if (targ_frag
->tc_frag_data
.is_aligning_branch
)
7157 targ_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
7160 frag_wane (targ_frag
);
7161 targ_frag
->tc_frag_data
.slot_subtypes
[0] = 0;
7165 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
7173 /* Re-process all of the fragments looking to convert all of the
7174 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7175 conditional branch or a retw/retw.n, convert this frag to one that
7176 will generate a NOP. In any case close it off with a .fill 0. */
7178 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
7181 xtensa_fix_a0_b_retw_frags (void)
7186 /* When this routine is called, all of the subsections are still intact
7187 so we walk over subsections instead of sections. */
7188 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7189 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7193 /* Walk over all of the fragments in a subsection. */
7194 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7196 if (fragP
->fr_type
== rs_machine_dependent
7197 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
7199 if (next_instrs_are_b_retw (fragP
))
7201 if (fragP
->tc_frag_data
.is_no_transform
)
7202 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7204 relax_frag_add_nop (fragP
);
7214 next_instrs_are_b_retw (fragS
*fragP
)
7216 xtensa_opcode opcode
;
7218 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
7219 static xtensa_insnbuf insnbuf
= NULL
;
7220 static xtensa_insnbuf slotbuf
= NULL
;
7221 xtensa_isa isa
= xtensa_default_isa
;
7224 bfd_boolean branch_seen
= FALSE
;
7228 insnbuf
= xtensa_insnbuf_alloc (isa
);
7229 slotbuf
= xtensa_insnbuf_alloc (isa
);
7232 if (next_fragP
== NULL
)
7235 /* Check for the conditional branch. */
7236 xtensa_insnbuf_from_chars
7237 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7238 fmt
= xtensa_format_decode (isa
, insnbuf
);
7239 if (fmt
== XTENSA_UNDEFINED
)
7242 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7244 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
7245 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
7247 branch_seen
= (branch_seen
7248 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
7254 offset
+= xtensa_format_length (isa
, fmt
);
7255 if (offset
== next_fragP
->fr_fix
)
7257 next_fragP
= next_non_empty_frag (next_fragP
);
7261 if (next_fragP
== NULL
)
7264 /* Check for the retw/retw.n. */
7265 xtensa_insnbuf_from_chars
7266 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7267 fmt
= xtensa_format_decode (isa
, insnbuf
);
7269 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
7270 have no problems. */
7271 if (fmt
== XTENSA_UNDEFINED
7272 || xtensa_format_num_slots (isa
, fmt
) != 1)
7275 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
7276 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
7278 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
7285 /* Re-process all of the fragments looking to convert all of the
7286 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
7287 loop end label, convert this frag to one that will generate a NOP.
7288 In any case close it off with a .fill 0. */
7290 static bfd_boolean
next_instr_is_loop_end (fragS
*);
7293 xtensa_fix_b_j_loop_end_frags (void)
7298 /* When this routine is called, all of the subsections are still intact
7299 so we walk over subsections instead of sections. */
7300 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7301 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7305 /* Walk over all of the fragments in a subsection. */
7306 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7308 if (fragP
->fr_type
== rs_machine_dependent
7309 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
7311 if (next_instr_is_loop_end (fragP
))
7313 if (fragP
->tc_frag_data
.is_no_transform
)
7314 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
7316 relax_frag_add_nop (fragP
);
7326 next_instr_is_loop_end (fragS
*fragP
)
7328 const fragS
*next_fragP
;
7330 if (next_frag_is_loop_target (fragP
))
7333 next_fragP
= next_non_empty_frag (fragP
);
7334 if (next_fragP
== NULL
)
7337 if (!next_frag_is_loop_target (next_fragP
))
7340 /* If the size is >= 3 then there is more than one instruction here.
7341 The hardware bug will not fire. */
7342 if (next_fragP
->fr_fix
> 3)
7349 /* Re-process all of the fragments looking to convert all of the
7350 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
7351 not MY loop's loop end within 12 bytes, add enough nops here to
7352 make it at least 12 bytes away. In any case close it off with a
7355 static offsetT min_bytes_to_other_loop_end
7356 (fragS
*, fragS
*, offsetT
);
7359 xtensa_fix_close_loop_end_frags (void)
7364 /* When this routine is called, all of the subsections are still intact
7365 so we walk over subsections instead of sections. */
7366 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7367 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7371 fragS
*current_target
= NULL
;
7373 /* Walk over all of the fragments in a subsection. */
7374 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7376 if (fragP
->fr_type
== rs_machine_dependent
7377 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7378 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7379 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7382 && fragP
->fr_type
== rs_machine_dependent
7383 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
7386 int bytes_added
= 0;
7388 #define REQUIRED_LOOP_DIVIDING_BYTES 12
7389 /* Max out at 12. */
7390 min_bytes
= min_bytes_to_other_loop_end
7391 (fragP
->fr_next
, current_target
, REQUIRED_LOOP_DIVIDING_BYTES
);
7393 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
7395 if (fragP
->tc_frag_data
.is_no_transform
)
7396 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
7399 while (min_bytes
+ bytes_added
7400 < REQUIRED_LOOP_DIVIDING_BYTES
)
7404 if (fragP
->fr_var
< length
)
7405 as_fatal (_("fr_var %lu < length %d"),
7406 (long) fragP
->fr_var
, length
);
7409 assemble_nop (length
,
7410 fragP
->fr_literal
+ fragP
->fr_fix
);
7411 fragP
->fr_fix
+= length
;
7412 fragP
->fr_var
-= length
;
7414 bytes_added
+= length
;
7420 assert (fragP
->fr_type
!= rs_machine_dependent
7421 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
7427 static offsetT
unrelaxed_frag_min_size (fragS
*);
7430 min_bytes_to_other_loop_end (fragS
*fragP
,
7431 fragS
*current_target
,
7435 fragS
*current_fragP
;
7437 for (current_fragP
= fragP
;
7439 current_fragP
= current_fragP
->fr_next
)
7441 if (current_fragP
->tc_frag_data
.is_loop_target
7442 && current_fragP
!= current_target
)
7445 offset
+= unrelaxed_frag_min_size (current_fragP
);
7447 if (offset
>= max_size
)
7455 unrelaxed_frag_min_size (fragS
*fragP
)
7457 offsetT size
= fragP
->fr_fix
;
7459 /* Add fill size. */
7460 if (fragP
->fr_type
== rs_fill
)
7461 size
+= fragP
->fr_offset
;
7468 unrelaxed_frag_max_size (fragS
*fragP
)
7470 offsetT size
= fragP
->fr_fix
;
7471 switch (fragP
->fr_type
)
7474 /* Empty frags created by the obstack allocation scheme
7475 end up with type 0. */
7480 size
+= fragP
->fr_offset
;
7488 /* No further adjustments needed. */
7490 case rs_machine_dependent
:
7491 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
7492 size
+= fragP
->fr_var
;
7495 /* We had darn well better know how big it is. */
7504 /* Re-process all of the fragments looking to convert all
7505 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
7508 1) the instruction size count to the loop end label
7509 is too short (<= 2 instructions),
7510 2) loop has a jump or branch in it
7513 1) workaround_all_short_loops is TRUE
7514 2) The generating loop was a 'loopgtz' or 'loopnez'
7515 3) the instruction size count to the loop end label is too short
7517 then convert this frag (and maybe the next one) to generate a NOP.
7518 In any case close it off with a .fill 0. */
7520 static int count_insns_to_loop_end (fragS
*, bfd_boolean
, int);
7521 static bfd_boolean
branch_before_loop_end (fragS
*);
7524 xtensa_fix_short_loop_frags (void)
7529 /* When this routine is called, all of the subsections are still intact
7530 so we walk over subsections instead of sections. */
7531 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7532 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7535 fragS
*current_target
= NULL
;
7536 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
7538 /* Walk over all of the fragments in a subsection. */
7539 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7541 if (fragP
->fr_type
== rs_machine_dependent
7542 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7543 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7546 fragS
*loop_frag
= next_non_empty_frag (fragP
);
7547 tinsn_from_chars (&t_insn
, loop_frag
->fr_opcode
, 0);
7548 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7549 current_opcode
= t_insn
.opcode
;
7550 assert (xtensa_opcode_is_loop (xtensa_default_isa
,
7551 current_opcode
) == 1);
7554 if (fragP
->fr_type
== rs_machine_dependent
7555 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7557 if (count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3) < 3
7558 && (branch_before_loop_end (fragP
->fr_next
)
7559 || (workaround_all_short_loops
7560 && current_opcode
!= XTENSA_UNDEFINED
7561 && current_opcode
!= xtensa_loop_opcode
)))
7563 if (fragP
->tc_frag_data
.is_no_transform
)
7564 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
7566 relax_frag_add_nop (fragP
);
7575 static int unrelaxed_frag_min_insn_count (fragS
*);
7578 count_insns_to_loop_end (fragS
*base_fragP
,
7579 bfd_boolean count_relax_add
,
7582 fragS
*fragP
= NULL
;
7587 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
7589 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
7590 if (insn_count
>= max_count
)
7593 if (count_relax_add
)
7595 if (fragP
->fr_type
== rs_machine_dependent
7596 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7598 /* In order to add the appropriate number of
7599 NOPs, we count an instruction for downstream
7602 if (insn_count
>= max_count
)
7612 unrelaxed_frag_min_insn_count (fragS
*fragP
)
7614 xtensa_isa isa
= xtensa_default_isa
;
7615 static xtensa_insnbuf insnbuf
= NULL
;
7619 if (!fragP
->tc_frag_data
.is_insn
)
7623 insnbuf
= xtensa_insnbuf_alloc (isa
);
7625 /* Decode the fixed instructions. */
7626 while (offset
< fragP
->fr_fix
)
7630 xtensa_insnbuf_from_chars
7631 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7632 fmt
= xtensa_format_decode (isa
, insnbuf
);
7634 if (fmt
== XTENSA_UNDEFINED
)
7636 as_fatal (_("undecodable instruction in instruction frag"));
7639 offset
+= xtensa_format_length (isa
, fmt
);
7647 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
7650 branch_before_loop_end (fragS
*base_fragP
)
7654 for (fragP
= base_fragP
;
7655 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
7656 fragP
= fragP
->fr_next
)
7658 if (unrelaxed_frag_has_b_j (fragP
))
7666 unrelaxed_frag_has_b_j (fragS
*fragP
)
7668 static xtensa_insnbuf insnbuf
= NULL
;
7669 xtensa_isa isa
= xtensa_default_isa
;
7672 if (!fragP
->tc_frag_data
.is_insn
)
7676 insnbuf
= xtensa_insnbuf_alloc (isa
);
7678 /* Decode the fixed instructions. */
7679 while (offset
< fragP
->fr_fix
)
7684 xtensa_insnbuf_from_chars
7685 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7686 fmt
= xtensa_format_decode (isa
, insnbuf
);
7687 if (fmt
== XTENSA_UNDEFINED
)
7690 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7692 xtensa_opcode opcode
=
7693 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
7694 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
7695 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
7698 offset
+= xtensa_format_length (isa
, fmt
);
7704 /* Checks to be made after initial assembly but before relaxation. */
7706 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
7707 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
7710 xtensa_sanity_check (void)
7717 as_where (&file_name
, &line
);
7718 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7719 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7723 /* Walk over all of the fragments in a subsection. */
7724 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7726 /* Currently we only check for empty loops here. */
7727 if (fragP
->fr_type
== rs_machine_dependent
7728 && fragP
->fr_subtype
== RELAX_IMMED
)
7730 static xtensa_insnbuf insnbuf
= NULL
;
7733 if (fragP
->fr_opcode
!= NULL
)
7736 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7737 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7738 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
7740 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7741 t_insn
.opcode
) == 1)
7743 if (is_empty_loop (&t_insn
, fragP
))
7745 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7746 as_bad (_("invalid empty loop"));
7748 if (!is_local_forward_loop (&t_insn
, fragP
))
7750 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7751 as_bad (_("loop target does not follow "
7752 "loop instruction in section"));
7759 new_logical_line (file_name
, line
);
7763 #define LOOP_IMMED_OPN 1
7765 /* Return TRUE if the loop target is the next non-zero fragment. */
7768 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
7770 const expressionS
*expr
;
7774 if (insn
->insn_type
!= ITYPE_INSN
)
7777 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
7780 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7783 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7785 if (expr
->X_op
!= O_symbol
)
7788 symbolP
= expr
->X_add_symbol
;
7792 if (symbol_get_frag (symbolP
) == NULL
)
7795 if (S_GET_VALUE (symbolP
) != 0)
7798 /* Walk through the zero-size fragments from this one. If we find
7799 the target fragment, then this is a zero-size loop. */
7801 for (next_fragP
= fragP
->fr_next
;
7803 next_fragP
= next_fragP
->fr_next
)
7805 if (next_fragP
== symbol_get_frag (symbolP
))
7807 if (next_fragP
->fr_fix
!= 0)
7815 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
7817 const expressionS
*expr
;
7821 if (insn
->insn_type
!= ITYPE_INSN
)
7824 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
7827 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7830 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7832 if (expr
->X_op
!= O_symbol
)
7835 symbolP
= expr
->X_add_symbol
;
7839 if (symbol_get_frag (symbolP
) == NULL
)
7842 /* Walk through fragments until we find the target.
7843 If we do not find the target, then this is an invalid loop. */
7845 for (next_fragP
= fragP
->fr_next
;
7847 next_fragP
= next_fragP
->fr_next
)
7849 if (next_fragP
== symbol_get_frag (symbolP
))
7857 /* Alignment Functions. */
7860 get_text_align_power (unsigned target_size
)
7862 if (target_size
<= 4)
7864 assert (target_size
== 8);
7870 get_text_align_max_fill_size (int align_pow
,
7871 bfd_boolean use_nops
,
7872 bfd_boolean use_no_density
)
7875 return (1 << align_pow
);
7877 return 3 * (1 << align_pow
);
7879 return 1 + (1 << align_pow
);
7883 /* Calculate the minimum bytes of fill needed at "address" to align a
7884 target instruction of size "target_size" so that it does not cross a
7885 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE,
7886 the fill can be an arbitrary number of bytes. Otherwise, the space must
7887 be filled by NOP instructions. */
7890 get_text_align_fill_size (addressT address
,
7893 bfd_boolean use_nops
,
7894 bfd_boolean use_no_density
)
7896 addressT alignment
, fill
, fill_limit
, fill_step
;
7897 bfd_boolean skip_one
= FALSE
;
7899 alignment
= (1 << align_pow
);
7900 assert (target_size
> 0 && alignment
>= (addressT
) target_size
);
7904 fill_limit
= alignment
;
7907 else if (!use_no_density
)
7909 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */
7910 fill_limit
= alignment
* 2;
7916 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */
7917 fill_limit
= alignment
* 3;
7921 /* Try all fill sizes until finding one that works. */
7922 for (fill
= 0; fill
< fill_limit
; fill
+= fill_step
)
7924 if (skip_one
&& fill
== 1)
7926 if ((address
+ fill
) >> align_pow
7927 == (address
+ fill
+ target_size
- 1) >> align_pow
)
7936 branch_align_power (segT sec
)
7938 /* If the Xtensa processor has a fetch width of 8 bytes, and the section
7939 is aligned to at least an 8-byte boundary, then a branch target need
7940 only fit within an 8-byte aligned block of memory to avoid a stall.
7941 Otherwise, try to fit branch targets within 4-byte aligned blocks
7942 (which may be insufficient, e.g., if the section has no alignment, but
7943 it's good enough). */
7944 if (xtensa_fetch_width
== 8)
7946 if (get_recorded_alignment (sec
) >= 3)
7950 assert (xtensa_fetch_width
== 4);
7956 /* This will assert if it is not possible. */
7959 get_text_align_nop_count (offsetT fill_size
, bfd_boolean use_no_density
)
7965 assert (fill_size
% 3 == 0);
7966 return (fill_size
/ 3);
7969 assert (fill_size
!= 1); /* Bad argument. */
7971 while (fill_size
> 1)
7974 if (fill_size
== 2 || fill_size
== 4)
7976 fill_size
-= insn_size
;
7979 assert (fill_size
!= 1); /* Bad algorithm. */
7985 get_text_align_nth_nop_size (offsetT fill_size
,
7987 bfd_boolean use_no_density
)
7994 assert (fill_size
!= 1); /* Bad argument. */
7996 while (fill_size
> 1)
7999 if (fill_size
== 2 || fill_size
== 4)
8001 fill_size
-= insn_size
;
8011 /* For the given fragment, find the appropriate address
8012 for it to begin at if we are using NOPs to align it. */
8015 get_noop_aligned_address (fragS
*fragP
, addressT address
)
8017 /* The rule is: get next fragment's FIRST instruction. Find
8018 the smallest number of bytes that need to be added to
8019 ensure that the next fragment's FIRST instruction will fit
8022 E.G., 2 bytes : 0, 1, 2 mod 4
8025 If the FIRST instruction MIGHT be relaxed,
8026 assume that it will become a 3-byte instruction.
8028 Note again here that LOOP instructions are not bundleable,
8029 and this relaxation only applies to LOOP opcodes. */
8032 int first_insn_size
;
8034 addressT pre_opcode_bytes
;
8037 xtensa_opcode opcode
;
8038 bfd_boolean is_loop
;
8040 assert (fragP
->fr_type
== rs_machine_dependent
);
8041 assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
8043 /* Find the loop frag. */
8044 first_insn
= next_non_empty_frag (fragP
);
8045 /* Now find the first insn frag. */
8046 first_insn
= next_non_empty_frag (first_insn
);
8048 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
8050 loop_insn_size
= xg_get_single_size (opcode
);
8052 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
8053 pre_opcode_bytes
+= loop_insn_size
;
8055 /* For loops, the alignment depends on the size of the
8056 instruction following the loop, not the LOOP instruction. */
8058 if (first_insn
== NULL
)
8059 first_insn_size
= xtensa_fetch_width
;
8061 first_insn_size
= get_loop_align_size (frag_format_size (first_insn
));
8063 /* If it was 8, then we'll need a larger alignment for the section. */
8064 align_power
= get_text_align_power (first_insn_size
);
8065 record_alignment (now_seg
, align_power
);
8067 fill_size
= get_text_align_fill_size
8068 (address
+ pre_opcode_bytes
, align_power
, first_insn_size
, TRUE
,
8069 fragP
->tc_frag_data
.is_no_density
);
8071 return address
+ fill_size
;
8075 /* 3 mechanisms for relaxing an alignment:
8077 Align to a power of 2.
8078 Align so the next fragment's instruction does not cross a word boundary.
8079 Align the current instruction so that if the next instruction
8080 were 3 bytes, it would not cross a word boundary.
8084 zeros - This is easy; always insert zeros.
8085 nops - 3-byte and 2-byte instructions
8089 >=5 : 3-byte instruction + fn (n-3)
8090 widening - widen previous instructions. */
8093 get_aligned_diff (fragS
*fragP
, addressT address
, offsetT
*max_diff
)
8095 addressT target_address
, loop_insn_offset
;
8097 xtensa_opcode loop_opcode
;
8098 bfd_boolean is_loop
;
8101 offsetT branch_align
;
8103 assert (fragP
->fr_type
== rs_machine_dependent
);
8104 switch (fragP
->fr_subtype
)
8106 case RELAX_DESIRE_ALIGN
:
8107 target_size
= next_frag_format_size (fragP
);
8108 if (target_size
== XTENSA_UNDEFINED
)
8110 align_power
= branch_align_power (now_seg
);
8111 branch_align
= 1 << align_power
;
8112 /* Don't count on the section alignment being as large as the target. */
8113 if (target_size
> branch_align
)
8114 target_size
= branch_align
;
8115 opt_diff
= get_text_align_fill_size (address
, align_power
,
8116 target_size
, FALSE
, FALSE
);
8118 *max_diff
= (opt_diff
+ branch_align
8119 - (target_size
+ ((address
+ opt_diff
) % branch_align
)));
8120 assert (*max_diff
>= opt_diff
);
8123 case RELAX_ALIGN_NEXT_OPCODE
:
8124 target_size
= get_loop_align_size (next_frag_format_size (fragP
));
8125 loop_insn_offset
= 0;
8126 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
8129 /* If the loop has been expanded then the LOOP instruction
8130 could be at an offset from this fragment. */
8131 if (next_non_empty_frag(fragP
)->tc_frag_data
.slot_subtypes
[0]
8133 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
8135 /* In an ideal world, which is what we are shooting for here,
8136 we wouldn't need to use any NOPs immediately prior to the
8137 LOOP instruction. If this approach fails, relax_frag_loop_align
8138 will call get_noop_aligned_address. */
8140 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
8141 align_power
= get_text_align_power (target_size
),
8142 opt_diff
= get_text_align_fill_size (target_address
, align_power
,
8143 target_size
, FALSE
, FALSE
);
8145 *max_diff
= xtensa_fetch_width
8146 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
8147 - target_size
+ opt_diff
;
8148 assert (*max_diff
>= opt_diff
);
8159 /* md_relax_frag Hook and Helper Functions. */
8161 static long relax_frag_loop_align (fragS
*, long);
8162 static long relax_frag_for_align (fragS
*, long);
8163 static long relax_frag_immed
8164 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
8167 /* Return the number of bytes added to this fragment, given that the
8168 input has been stretched already by "stretch". */
8171 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
8173 xtensa_isa isa
= xtensa_default_isa
;
8174 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
8175 long new_stretch
= 0;
8179 static xtensa_insnbuf vbuf
= NULL
;
8180 int slot
, num_slots
;
8183 as_where (&file_name
, &line
);
8184 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8186 fragP
->tc_frag_data
.unreported_expansion
= 0;
8188 switch (fragP
->fr_subtype
)
8190 case RELAX_ALIGN_NEXT_OPCODE
:
8191 /* Always convert. */
8192 if (fragP
->tc_frag_data
.relax_seen
)
8193 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
8196 case RELAX_LOOP_END
:
8200 case RELAX_LOOP_END_ADD_NOP
:
8201 /* Add a NOP and switch to .fill 0. */
8202 new_stretch
= relax_frag_add_nop (fragP
);
8206 case RELAX_DESIRE_ALIGN
:
8207 /* Do nothing. The narrowing before this frag will either align
8212 case RELAX_LITERAL_FINAL
:
8215 case RELAX_LITERAL_NR
:
8217 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
8218 assert (unreported
== lit_size
);
8219 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
8220 fragP
->fr_var
-= lit_size
;
8221 fragP
->fr_fix
+= lit_size
;
8227 vbuf
= xtensa_insnbuf_alloc (isa
);
8229 xtensa_insnbuf_from_chars
8230 (isa
, vbuf
, (unsigned char *) fragP
->fr_opcode
, 0);
8231 fmt
= xtensa_format_decode (isa
, vbuf
);
8232 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8234 for (slot
= 0; slot
< num_slots
; slot
++)
8236 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
8239 if (fragP
->tc_frag_data
.relax_seen
)
8240 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8244 case RELAX_IMMED_STEP1
:
8245 case RELAX_IMMED_STEP2
:
8246 /* Place the immediate. */
8247 new_stretch
+= relax_frag_immed
8248 (now_seg
, fragP
, stretch
,
8249 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8250 fmt
, slot
, stretched_p
, FALSE
);
8254 /* This is OK; see the note in xg_assemble_vliw_tokens. */
8260 case RELAX_LITERAL_POOL_BEGIN
:
8261 case RELAX_LITERAL_POOL_END
:
8262 case RELAX_MAYBE_UNREACHABLE
:
8263 case RELAX_MAYBE_DESIRE_ALIGN
:
8264 /* No relaxation required. */
8267 case RELAX_FILL_NOP
:
8268 case RELAX_UNREACHABLE
:
8269 if (fragP
->tc_frag_data
.relax_seen
)
8270 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8274 as_bad (_("bad relaxation state"));
8277 /* Tell gas we need another relaxation pass. */
8278 if (! fragP
->tc_frag_data
.relax_seen
)
8280 fragP
->tc_frag_data
.relax_seen
= TRUE
;
8284 new_logical_line (file_name
, line
);
8290 relax_frag_loop_align (fragS
*fragP
, long stretch
)
8292 addressT old_address
, old_next_address
, old_size
;
8293 addressT new_address
, new_next_address
, new_size
;
8296 /* All the frags with relax_frag_for_alignment prior to this one in the
8297 section have been done, hopefully eliminating the need for a NOP here.
8298 But, this will put it in if necessary. */
8300 /* Calculate the old address of this fragment and the next fragment. */
8301 old_address
= fragP
->fr_address
- stretch
;
8302 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
8303 fragP
->tc_frag_data
.text_expansion
[0]);
8304 old_size
= old_next_address
- old_address
;
8306 /* Calculate the new address of this fragment and the next fragment. */
8307 new_address
= fragP
->fr_address
;
8309 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
8310 new_size
= new_next_address
- new_address
;
8312 growth
= new_size
- old_size
;
8314 /* Fix up the text_expansion field and return the new growth. */
8315 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
8320 /* Add a NOP instruction. */
8323 relax_frag_add_nop (fragS
*fragP
)
8325 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
8326 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
8327 assemble_nop (length
, nop_buf
);
8328 fragP
->tc_frag_data
.is_insn
= TRUE
;
8330 if (fragP
->fr_var
< length
)
8332 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP
->fr_var
, length
);
8336 fragP
->fr_fix
+= length
;
8337 fragP
->fr_var
-= length
;
8342 static long future_alignment_required (fragS
*, long);
8345 relax_frag_for_align (fragS
*fragP
, long stretch
)
8347 /* Overview of the relaxation procedure for alignment:
8348 We can widen with NOPs or by widening instructions or by filling
8349 bytes after jump instructions. Find the opportune places and widen
8350 them if necessary. */
8355 assert (fragP
->fr_subtype
== RELAX_FILL_NOP
8356 || fragP
->fr_subtype
== RELAX_UNREACHABLE
8357 || (fragP
->fr_subtype
== RELAX_SLOTS
8358 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
8360 stretch_me
= future_alignment_required (fragP
, stretch
);
8361 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
8367 /* We expanded on a previous pass. Can we shrink now? */
8368 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
8369 if (shrink
<= stretch
&& stretch
> 0)
8371 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8377 /* Below here, diff > 0. */
8378 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8384 /* Return the address of the next frag that should be aligned.
8386 By "address" we mean the address it _would_ be at if there
8387 is no action taken to align it between here and the target frag.
8388 In other words, if no narrows and no fill nops are used between
8389 here and the frag to align, _even_if_ some of the frags we use
8390 to align targets have already expanded on a previous relaxation
8393 Also, count each frag that may be used to help align the target.
8395 Return 0 if there are no frags left in the chain that need to be
8399 find_address_of_next_align_frag (fragS
**fragPP
,
8403 bfd_boolean
*paddable
)
8405 fragS
*fragP
= *fragPP
;
8406 addressT address
= fragP
->fr_address
;
8408 /* Do not reset the counts to 0. */
8412 /* Limit this to a small search. */
8413 if (*widens
>= (int) xtensa_fetch_width
)
8418 address
+= fragP
->fr_fix
;
8420 if (fragP
->fr_type
== rs_fill
)
8421 address
+= fragP
->fr_offset
* fragP
->fr_var
;
8422 else if (fragP
->fr_type
== rs_machine_dependent
)
8424 switch (fragP
->fr_subtype
)
8426 case RELAX_UNREACHABLE
:
8430 case RELAX_FILL_NOP
:
8432 if (!fragP
->tc_frag_data
.is_no_density
)
8437 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8442 address
+= total_frag_text_expansion (fragP
);;
8446 address
+= fragP
->tc_frag_data
.text_expansion
[0];
8449 case RELAX_ALIGN_NEXT_OPCODE
:
8450 case RELAX_DESIRE_ALIGN
:
8454 case RELAX_MAYBE_UNREACHABLE
:
8455 case RELAX_MAYBE_DESIRE_ALIGN
:
8460 /* Just punt if we don't know the type. */
8467 /* Just punt if we don't know the type. */
8471 fragP
= fragP
->fr_next
;
8479 static long bytes_to_stretch (fragS
*, int, int, int, int);
8482 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
8484 fragS
*this_frag
= fragP
;
8488 int narrow_nops
= 0;
8489 bfd_boolean paddable
= FALSE
;
8490 offsetT local_opt_diff
;
8493 int stretch_amount
= 0;
8494 int local_stretch_amount
;
8495 int global_stretch_amount
;
8497 address
= find_address_of_next_align_frag
8498 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
8502 if (this_frag
->tc_frag_data
.is_aligning_branch
)
8503 this_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
8505 frag_wane (this_frag
);
8509 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
8510 opt_diff
= local_opt_diff
;
8511 assert (opt_diff
>= 0);
8512 assert (max_diff
>= opt_diff
);
8517 fragP
= fragP
->fr_next
;
8519 while (fragP
&& opt_diff
< max_diff
&& address
)
8521 /* We only use these to determine if we can exit early
8522 because there will be plenty of ways to align future
8524 int glob_widens
= 0;
8527 bfd_boolean glob_pad
= 0;
8528 address
= find_address_of_next_align_frag
8529 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
8530 /* If there is a padable portion, then skip. */
8531 if (glob_pad
|| glob_widens
>= (1 << branch_align_power (now_seg
)))
8536 offsetT next_m_diff
;
8537 offsetT next_o_diff
;
8539 /* Downrange frags haven't had stretch added to them yet. */
8542 /* The address also includes any text expansion from this
8543 frag in a previous pass, but we don't want that. */
8544 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
8546 /* Assume we are going to move at least opt_diff. In
8547 reality, we might not be able to, but assuming that
8548 we will helps catch cases where moving opt_diff pushes
8549 the next target from aligned to unaligned. */
8550 address
+= opt_diff
;
8552 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
8554 /* Now cleanup for the adjustments to address. */
8555 next_o_diff
+= opt_diff
;
8556 next_m_diff
+= opt_diff
;
8557 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
8558 opt_diff
= next_o_diff
;
8559 if (next_m_diff
< max_diff
)
8560 max_diff
= next_m_diff
;
8561 fragP
= fragP
->fr_next
;
8565 /* If there are enough wideners in between, do it. */
8568 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
8570 assert (opt_diff
<= UNREACHABLE_MAX_WIDTH
);
8575 local_stretch_amount
8576 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8577 num_widens
, local_opt_diff
);
8578 global_stretch_amount
8579 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8580 num_widens
, opt_diff
);
8581 /* If the condition below is true, then the frag couldn't
8582 stretch the correct amount for the global case, so we just
8583 optimize locally. We'll rely on the subsequent frags to get
8584 the correct alignment in the global case. */
8585 if (global_stretch_amount
< local_stretch_amount
)
8586 stretch_amount
= local_stretch_amount
;
8588 stretch_amount
= global_stretch_amount
;
8590 if (this_frag
->fr_subtype
== RELAX_SLOTS
8591 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8592 assert (stretch_amount
<= 1);
8593 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8595 if (this_frag
->tc_frag_data
.is_no_density
)
8596 assert (stretch_amount
== 3 || stretch_amount
== 0);
8598 assert (stretch_amount
<= 3);
8601 return stretch_amount
;
8605 /* The idea: widen everything you can to get a target or loop aligned,
8606 then start using NOPs.
8608 When we must have a NOP, here is a table of how we decide
8609 (so you don't have to fight through the control flow below):
8611 wide_nops = the number of wide NOPs available for aligning
8612 narrow_nops = the number of narrow NOPs available for aligning
8613 (a subset of wide_nops)
8614 widens = the number of narrow instructions that should be widened
8621 b 0 1 1 (case 3a makes this case unnecessary)
8624 c 0 1 2 (case 4a makes this case unnecessary)
8627 c 0 2 1 (case 5b makes this case unnecessary)
8630 c 0 1 4 (case 6b makes this case unnecessary)
8631 d 1 1 1 (case 6a makes this case unnecessary)
8632 e 0 2 2 (case 6a makes this case unnecessary)
8633 f 0 3 0 (case 6a makes this case unnecessary)
8636 c 1 1 2 (case 7b makes this case unnecessary)
8637 d 0 1 5 (case 7a makes this case unnecessary)
8638 e 0 2 3 (case 7b makes this case unnecessary)
8639 f 0 3 1 (case 7b makes this case unnecessary)
8640 g 1 2 1 (case 7b makes this case unnecessary)
8644 bytes_to_stretch (fragS
*this_frag
,
8650 int bytes_short
= desired_diff
- num_widens
;
8652 assert (desired_diff
>= 0 && desired_diff
< 8);
8653 if (desired_diff
== 0)
8656 assert (wide_nops
> 0 || num_widens
> 0);
8658 /* Always prefer widening to NOP-filling. */
8659 if (bytes_short
< 0)
8661 /* There are enough RELAX_NARROW frags after this one
8662 to align the target without widening this frag in any way. */
8666 if (bytes_short
== 0)
8668 /* Widen every narrow between here and the align target
8669 and the align target will be properly aligned. */
8670 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8676 /* From here we will need at least one NOP to get an alignment.
8677 However, we may not be able to align at all, in which case,
8679 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8681 switch (desired_diff
)
8686 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 1)
8687 return 2; /* case 2 */
8693 return 3; /* case 3a */
8695 if (num_widens
>= 1 && wide_nops
== 1)
8696 return 3; /* case 4a */
8697 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 2)
8698 return 2; /* case 4b */
8701 if (num_widens
>= 2 && wide_nops
== 1)
8702 return 3; /* case 5a */
8703 /* We will need two nops. Are there enough nops
8704 between here and the align target? */
8705 if (wide_nops
< 2 || narrow_nops
== 0)
8707 /* Are there other nops closer that can serve instead? */
8708 if (wide_nops
> 2 && narrow_nops
> 1)
8710 /* Take the density one first, because there might not be
8711 another density one available. */
8712 if (!this_frag
->tc_frag_data
.is_no_density
)
8713 return 2; /* case 5b narrow */
8715 return 3; /* case 5b wide */
8719 return 3; /* case 6a */
8720 else if (num_widens
>= 3 && wide_nops
== 1)
8721 return 3; /* case 6b */
8724 if (wide_nops
== 1 && num_widens
>= 4)
8725 return 3; /* case 7a */
8726 else if (wide_nops
== 2 && num_widens
>= 1)
8727 return 3; /* case 7b */
8735 /* We will need a NOP no matter what, but should we widen
8736 this instruction to help?
8738 This is a RELAX_NARROW frag. */
8739 switch (desired_diff
)
8748 if (wide_nops
>= 1 && num_widens
== 1)
8749 return 1; /* case 4a */
8752 if (wide_nops
>= 1 && num_widens
== 2)
8753 return 1; /* case 5a */
8757 return 0; /* case 6a */
8758 else if (wide_nops
>= 1 && num_widens
== 3)
8759 return 1; /* case 6b */
8762 if (wide_nops
>= 1 && num_widens
== 4)
8763 return 1; /* case 7a */
8764 else if (wide_nops
>= 2 && num_widens
== 1)
8765 return 1; /* case 7b */
8778 relax_frag_immed (segT segP
,
8785 bfd_boolean estimate_only
)
8789 bfd_boolean negatable_branch
= FALSE
;
8790 bfd_boolean branch_jmp_to_next
= FALSE
;
8791 bfd_boolean wide_insn
= FALSE
;
8792 xtensa_isa isa
= xtensa_default_isa
;
8794 offsetT frag_offset
;
8797 int num_text_bytes
, num_literal_bytes
;
8798 int literal_diff
, total_text_diff
, this_text_diff
, first
;
8800 assert (fragP
->fr_opcode
!= NULL
);
8802 xg_clear_vinsn (&cur_vinsn
);
8803 vinsn_from_chars (&cur_vinsn
, fragP
->fr_opcode
);
8804 if (cur_vinsn
.num_slots
> 1)
8807 tinsn
= cur_vinsn
.slots
[slot
];
8808 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
8810 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
) == 1)
8813 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
8814 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
8816 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
8818 old_size
= xtensa_format_length (isa
, fmt
);
8820 /* Special case: replace a branch to the next instruction with a NOP.
8821 This is required to work around a hardware bug in T1040.0 and also
8822 serves as an optimization. */
8824 if (branch_jmp_to_next
8825 && ((old_size
== 2) || (old_size
== 3))
8826 && !next_frag_is_loop_target (fragP
))
8829 /* Here is the fun stuff: Get the immediate field from this
8830 instruction. If it fits, we are done. If not, find the next
8831 instruction sequence that fits. */
8833 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
8834 istack_init (&istack
);
8835 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
8836 min_steps
, stretch
);
8837 if (num_steps
< min_steps
)
8839 as_fatal (_("internal error: relaxation failed"));
8843 if (num_steps
> RELAX_IMMED_MAXSTEPS
)
8845 as_fatal (_("internal error: relaxation requires too many steps"));
8849 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
8851 /* Figure out the number of bytes needed. */
8853 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
8855 num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
8857 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
8859 num_text_bytes
= get_num_stack_text_bytes (&istack
);
8862 num_text_bytes
+= old_size
;
8863 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
8864 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
8866 total_text_diff
= num_text_bytes
- old_size
;
8867 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
8869 /* It MUST get larger. If not, we could get an infinite loop. */
8870 assert (num_text_bytes
>= 0);
8871 assert (literal_diff
>= 0);
8872 assert (total_text_diff
>= 0);
8874 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
8875 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
8876 assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
8877 assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
8879 /* Find the associated expandable literal for this. */
8880 if (literal_diff
!= 0)
8882 lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
8885 assert (literal_diff
== 4);
8886 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
8888 /* We expect that the literal section state has NOT been
8890 assert (lit_fragP
->fr_type
== rs_machine_dependent
8891 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
8892 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
8894 /* We need to mark this section for another iteration
8900 if (negatable_branch
&& istack
.ninsn
> 1)
8901 update_next_frag_state (fragP
);
8903 return this_text_diff
;
8907 /* md_convert_frag Hook and Helper Functions. */
8909 static void convert_frag_align_next_opcode (fragS
*);
8910 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
8911 static void convert_frag_fill_nop (fragS
*);
8912 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
8915 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
8917 static xtensa_insnbuf vbuf
= NULL
;
8918 xtensa_isa isa
= xtensa_default_isa
;
8925 as_where (&file_name
, &line
);
8926 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
8928 switch (fragp
->fr_subtype
)
8930 case RELAX_ALIGN_NEXT_OPCODE
:
8931 /* Always convert. */
8932 convert_frag_align_next_opcode (fragp
);
8935 case RELAX_DESIRE_ALIGN
:
8936 /* Do nothing. If not aligned already, too bad. */
8940 case RELAX_LITERAL_FINAL
:
8945 vbuf
= xtensa_insnbuf_alloc (isa
);
8947 xtensa_insnbuf_from_chars
8948 (isa
, vbuf
, (unsigned char *) fragp
->fr_opcode
, 0);
8949 fmt
= xtensa_format_decode (isa
, vbuf
);
8950 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8952 for (slot
= 0; slot
< num_slots
; slot
++)
8954 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
8957 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
8961 case RELAX_IMMED_STEP1
:
8962 case RELAX_IMMED_STEP2
:
8963 /* Place the immediate. */
8966 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8971 /* This is OK because some slots could have
8972 relaxations and others have none. */
8978 case RELAX_UNREACHABLE
:
8979 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
8980 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
8981 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
8985 case RELAX_MAYBE_UNREACHABLE
:
8986 case RELAX_MAYBE_DESIRE_ALIGN
:
8990 case RELAX_FILL_NOP
:
8991 convert_frag_fill_nop (fragp
);
8994 case RELAX_LITERAL_NR
:
8995 if (use_literal_section
)
8997 /* This should have been handled during relaxation. When
8998 relaxing a code segment, literals sometimes need to be
8999 added to the corresponding literal segment. If that
9000 literal segment has already been relaxed, then we end up
9001 in this situation. Marking the literal segments as data
9002 would make this happen less often (since GAS always relaxes
9003 code before data), but we could still get into trouble if
9004 there are instructions in a segment that is not marked as
9005 containing code. Until we can implement a better solution,
9006 cheat and adjust the addresses of all the following frags.
9007 This could break subsequent alignments, but the linker's
9008 literal coalescing will do that anyway. */
9011 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
9012 assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
9013 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
9016 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
9020 as_bad (_("invalid relaxation fragment result"));
9025 new_logical_line (file_name
, line
);
9030 convert_frag_align_next_opcode (fragS
*fragp
)
9032 char *nop_buf
; /* Location for Writing. */
9033 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
9034 addressT aligned_address
;
9038 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
9040 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
9041 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
9042 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
9044 for (nop
= 0; nop
< nop_count
; nop
++)
9047 nop_size
= get_text_align_nth_nop_size (fill_size
, nop
, use_no_density
);
9049 assemble_nop (nop_size
, nop_buf
);
9050 nop_buf
+= nop_size
;
9053 fragp
->fr_fix
+= fill_size
;
9054 fragp
->fr_var
-= fill_size
;
9059 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
9061 TInsn tinsn
, single_target
;
9062 int size
, old_size
, diff
;
9063 offsetT frag_offset
;
9066 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
9068 if (fragP
->tc_frag_data
.is_aligning_branch
== 1)
9070 assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
9071 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
9072 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
9077 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
9079 /* No conversion. */
9084 assert (fragP
->fr_opcode
!= NULL
);
9086 /* Frags in this relaxation state should only contain
9087 single instruction bundles. */
9088 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
9090 /* Just convert it to a wide form.... */
9092 old_size
= xg_get_single_size (tinsn
.opcode
);
9094 tinsn_init (&single_target
);
9095 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9097 if (! xg_is_single_relaxable_insn (&tinsn
, &single_target
, FALSE
))
9099 as_bad (_("unable to widen instruction"));
9103 size
= xg_get_single_size (single_target
.opcode
);
9104 xg_emit_insn_to_buf (&single_target
, fragP
->fr_opcode
, fragP
,
9107 diff
= size
- old_size
;
9109 assert (diff
<= fragP
->fr_var
);
9110 fragP
->fr_var
-= diff
;
9111 fragP
->fr_fix
+= diff
;
9119 convert_frag_fill_nop (fragS
*fragP
)
9121 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
9122 int size
= fragP
->tc_frag_data
.text_expansion
[0];
9123 assert ((unsigned) size
== (fragP
->fr_next
->fr_address
9124 - fragP
->fr_address
- fragP
->fr_fix
));
9127 /* No conversion. */
9131 assemble_nop (size
, loc
);
9132 fragP
->tc_frag_data
.is_insn
= TRUE
;
9133 fragP
->fr_var
-= size
;
9134 fragP
->fr_fix
+= size
;
9139 static fixS
*fix_new_exp_in_seg
9140 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
9141 bfd_reloc_code_real_type
);
9142 static void convert_frag_immed_finish_loop (segT
, fragS
*, TInsn
*);
9145 convert_frag_immed (segT segP
,
9151 char *immed_instr
= fragP
->fr_opcode
;
9153 bfd_boolean expanded
= FALSE
;
9154 bfd_boolean branch_jmp_to_next
= FALSE
;
9155 char *fr_opcode
= fragP
->fr_opcode
;
9156 xtensa_isa isa
= xtensa_default_isa
;
9157 bfd_boolean wide_insn
= FALSE
;
9159 bfd_boolean is_loop
;
9161 assert (fr_opcode
!= NULL
);
9163 xg_clear_vinsn (&cur_vinsn
);
9165 vinsn_from_chars (&cur_vinsn
, fr_opcode
);
9166 if (cur_vinsn
.num_slots
> 1)
9169 orig_tinsn
= cur_vinsn
.slots
[slot
];
9170 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
9172 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
9174 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9175 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
9177 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
9179 /* Conversion just inserts a NOP and marks the fix as completed. */
9180 bytes
= xtensa_format_length (isa
, fmt
);
9183 cur_vinsn
.slots
[slot
].opcode
=
9184 xtensa_format_slot_nop_opcode (isa
, cur_vinsn
.format
, slot
);
9185 cur_vinsn
.slots
[slot
].ntok
= 0;
9189 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
9190 assert (bytes
== 2 || bytes
== 3);
9191 build_nop (&cur_vinsn
.slots
[0], bytes
);
9192 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
9194 vinsn_to_insnbuf (&cur_vinsn
, fr_opcode
, frag_now
, TRUE
);
9195 xtensa_insnbuf_to_chars
9196 (isa
, cur_vinsn
.insnbuf
, (unsigned char *) fr_opcode
, 0);
9201 /* Here is the fun stuff: Get the immediate field from this
9202 instruction. If it fits, we're done. If not, find the next
9203 instruction sequence that fits. */
9207 symbolS
*lit_sym
= NULL
;
9209 int target_offset
= 0;
9212 symbolS
*gen_label
= NULL
;
9213 offsetT frag_offset
;
9214 bfd_boolean first
= TRUE
;
9215 bfd_boolean last_is_jump
;
9217 /* It does not fit. Find something that does and
9218 convert immediately. */
9219 frag_offset
= fr_opcode
- fragP
->fr_literal
;
9220 istack_init (&istack
);
9221 xg_assembly_relax (&istack
, &orig_tinsn
,
9222 segP
, fragP
, frag_offset
, min_steps
, 0);
9224 old_size
= xtensa_format_length (isa
, fmt
);
9226 /* Assemble this right inline. */
9228 /* First, create the mapping from a label name to the REAL label. */
9230 for (i
= 0; i
< istack
.ninsn
; i
++)
9232 TInsn
*tinsn
= &istack
.insn
[i
];
9235 switch (tinsn
->insn_type
)
9238 if (lit_sym
!= NULL
)
9239 as_bad (_("multiple literals in expansion"));
9240 /* First find the appropriate space in the literal pool. */
9241 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9242 if (lit_frag
== NULL
)
9243 as_bad (_("no registered fragment for literal"));
9244 if (tinsn
->ntok
!= 1)
9245 as_bad (_("number of literal tokens != 1"));
9247 /* Set the literal symbol and add a fixup. */
9248 lit_sym
= lit_frag
->fr_symbol
;
9252 if (align_targets
&& !is_loop
)
9254 fragS
*unreach
= fragP
->fr_next
;
9255 while (!(unreach
->fr_type
== rs_machine_dependent
9256 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9257 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
9259 unreach
= unreach
->fr_next
;
9262 assert (unreach
->fr_type
== rs_machine_dependent
9263 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9264 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
9266 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
9268 assert (gen_label
== NULL
);
9269 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
9270 fr_opcode
- fragP
->fr_literal
9271 + target_offset
, fragP
);
9275 if (first
&& wide_insn
)
9277 target_offset
+= xtensa_format_length (isa
, fmt
);
9279 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9280 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9283 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9290 last_is_jump
= FALSE
;
9291 for (i
= 0; i
< istack
.ninsn
; i
++)
9293 TInsn
*tinsn
= &istack
.insn
[i
];
9297 bfd_reloc_code_real_type reloc_type
;
9299 switch (tinsn
->insn_type
)
9302 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9303 /* Already checked. */
9304 assert (lit_frag
!= NULL
);
9305 assert (lit_sym
!= NULL
);
9306 assert (tinsn
->ntok
== 1);
9308 target_seg
= S_GET_SEGMENT (lit_sym
);
9309 assert (target_seg
);
9310 if (tinsn
->tok
[0].X_op
== O_pltrel
)
9311 reloc_type
= BFD_RELOC_XTENSA_PLT
;
9313 reloc_type
= BFD_RELOC_32
;
9314 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
9315 &tinsn
->tok
[0], FALSE
, reloc_type
);
9322 xg_resolve_labels (tinsn
, gen_label
);
9323 xg_resolve_literals (tinsn
, lit_sym
);
9324 if (wide_insn
&& first
)
9327 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9329 cur_vinsn
.slots
[slot
] = *tinsn
;
9333 cur_vinsn
.slots
[slot
].opcode
=
9334 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
9335 cur_vinsn
.slots
[slot
].ntok
= 0;
9337 vinsn_to_insnbuf (&cur_vinsn
, immed_instr
, fragP
, TRUE
);
9338 xtensa_insnbuf_to_chars (isa
, cur_vinsn
.insnbuf
,
9339 (unsigned char *) immed_instr
, 0);
9340 fragP
->tc_frag_data
.is_insn
= TRUE
;
9341 size
= xtensa_format_length (isa
, fmt
);
9342 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9345 (tinsn
, immed_instr
+ size
, fragP
,
9346 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
9347 size
+= xg_get_single_size (tinsn
->opcode
);
9352 size
= xg_get_single_size (tinsn
->opcode
);
9353 xg_emit_insn_to_buf (tinsn
, immed_instr
, fragP
,
9354 immed_instr
- fragP
->fr_literal
, TRUE
);
9356 immed_instr
+= size
;
9362 diff
= total_size
- old_size
;
9366 assert (diff
<= fragP
->fr_var
);
9367 fragP
->fr_var
-= diff
;
9368 fragP
->fr_fix
+= diff
;
9371 /* Check for undefined immediates in LOOP instructions. */
9375 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
9376 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9378 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9381 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
9382 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9384 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9389 if (expanded
&& xtensa_opcode_is_loop (isa
, orig_tinsn
.opcode
) == 1)
9390 convert_frag_immed_finish_loop (segP
, fragP
, &orig_tinsn
);
9392 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
9394 /* Add an expansion note on the expanded instruction. */
9395 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
9396 &orig_tinsn
.tok
[0], TRUE
,
9397 BFD_RELOC_XTENSA_ASM_EXPAND
);
9402 /* Add a new fix expression into the desired segment. We have to
9403 switch to that segment to do this. */
9406 fix_new_exp_in_seg (segT new_seg
,
9413 bfd_reloc_code_real_type r_type
)
9417 subsegT subseg
= now_subseg
;
9419 assert (new_seg
!= 0);
9420 subseg_set (new_seg
, new_subseg
);
9422 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
9423 subseg_set (seg
, subseg
);
9428 /* Relax a loop instruction so that it can span loop >256 bytes.
9434 addi as, as, lo8 (label-.L1)
9435 addmi as, as, mid8 (label-.L1)
9446 convert_frag_immed_finish_loop (segT segP
, fragS
*fragP
, TInsn
*tinsn
)
9451 unsigned long target
;
9452 static xtensa_insnbuf insnbuf
= NULL
;
9453 unsigned int loop_length
, loop_length_hi
, loop_length_lo
;
9454 xtensa_isa isa
= xtensa_default_isa
;
9455 addressT loop_offset
;
9456 addressT addi_offset
= 9;
9457 addressT addmi_offset
= 12;
9462 insnbuf
= xtensa_insnbuf_alloc (isa
);
9464 /* Get the loop offset. */
9465 loop_offset
= get_expanded_loop_offset (tinsn
->opcode
);
9467 /* Validate that there really is a LOOP at the loop_offset. Because
9468 loops are not bundleable, we can assume that the instruction will be
9470 tinsn_from_chars (&loop_insn
, fragP
->fr_opcode
+ loop_offset
, 0);
9471 tinsn_immed_from_frag (&loop_insn
, fragP
, 0);
9473 assert (xtensa_opcode_is_loop (isa
, loop_insn
.opcode
) == 1);
9474 addi_offset
+= loop_offset
;
9475 addmi_offset
+= loop_offset
;
9477 assert (tinsn
->ntok
== 2);
9478 if (tinsn
->tok
[1].X_op
== O_constant
)
9479 target
= tinsn
->tok
[1].X_add_number
;
9480 else if (tinsn
->tok
[1].X_op
== O_symbol
)
9482 /* Find the fragment. */
9483 symbolS
*sym
= tinsn
->tok
[1].X_add_symbol
;
9484 assert (S_GET_SEGMENT (sym
) == segP
9485 || S_GET_SEGMENT (sym
) == absolute_section
);
9486 target
= (S_GET_VALUE (sym
) + tinsn
->tok
[1].X_add_number
);
9490 as_bad (_("invalid expression evaluation type %d"), tinsn
->tok
[1].X_op
);
9495 know (symbolP
->sy_frag
);
9496 know (!(S_GET_SEGMENT (symbolP
) == absolute_section
)
9497 || symbol_get_frag (symbolP
) == &zero_address_frag
);
9499 loop_length
= target
- (fragP
->fr_address
+ fragP
->fr_fix
);
9500 loop_length_hi
= loop_length
& ~0x0ff;
9501 loop_length_lo
= loop_length
& 0x0ff;
9502 if (loop_length_lo
>= 128)
9504 loop_length_lo
-= 256;
9505 loop_length_hi
+= 256;
9508 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
9509 32512. If the loop is larger than that, then we just fail. */
9510 if (loop_length_hi
> 32512)
9511 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9512 _("loop too long for LOOP instruction"));
9514 tinsn_from_chars (&addi_insn
, fragP
->fr_opcode
+ addi_offset
, 0);
9515 assert (addi_insn
.opcode
== xtensa_addi_opcode
);
9517 tinsn_from_chars (&addmi_insn
, fragP
->fr_opcode
+ addmi_offset
, 0);
9518 assert (addmi_insn
.opcode
== xtensa_addmi_opcode
);
9520 set_expr_const (&addi_insn
.tok
[2], loop_length_lo
);
9521 tinsn_to_insnbuf (&addi_insn
, insnbuf
);
9523 fragP
->tc_frag_data
.is_insn
= TRUE
;
9524 xtensa_insnbuf_to_chars
9525 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addi_offset
, 0);
9527 set_expr_const (&addmi_insn
.tok
[2], loop_length_hi
);
9528 tinsn_to_insnbuf (&addmi_insn
, insnbuf
);
9529 xtensa_insnbuf_to_chars
9530 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addmi_offset
, 0);
9532 /* Walk through all of the frags from here to the loop end
9533 and mark them as no_transform to keep them from being modified
9534 by the linker. If we ever have a relocation for the
9535 addi/addmi of the difference of two symbols we can remove this. */
9538 for (next_fragP
= fragP
; next_fragP
!= NULL
;
9539 next_fragP
= next_fragP
->fr_next
)
9541 next_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
9542 if (next_fragP
->tc_frag_data
.is_loop_target
)
9544 if (target_count
== 2)
9550 /* A map that keeps information on a per-subsegment basis. This is
9551 maintained during initial assembly, but is invalid once the
9552 subsegments are smashed together. I.E., it cannot be used during
9555 typedef struct subseg_map_struct
9563 float total_freq
; /* fall-through + branch target frequency */
9564 float target_freq
; /* branch target frequency alone */
9566 struct subseg_map_struct
*next
;
9570 static subseg_map
*sseg_map
= NULL
;
9573 get_subseg_info (segT seg
, subsegT subseg
)
9575 subseg_map
*subseg_e
;
9577 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
9579 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
9587 add_subseg_info (segT seg
, subsegT subseg
)
9589 subseg_map
*subseg_e
= (subseg_map
*) xmalloc (sizeof (subseg_map
));
9590 memset (subseg_e
, 0, sizeof (subseg_map
));
9591 subseg_e
->seg
= seg
;
9592 subseg_e
->subseg
= subseg
;
9593 subseg_e
->flags
= 0;
9594 /* Start off considering every branch target very important. */
9595 subseg_e
->target_freq
= 1.0;
9596 subseg_e
->total_freq
= 1.0;
9597 subseg_e
->next
= sseg_map
;
9598 sseg_map
= subseg_e
;
9604 get_last_insn_flags (segT seg
, subsegT subseg
)
9606 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9608 return subseg_e
->flags
;
9614 set_last_insn_flags (segT seg
,
9619 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9621 subseg_e
= add_subseg_info (seg
, subseg
);
9623 subseg_e
->flags
|= fl
;
9625 subseg_e
->flags
&= ~fl
;
9630 get_subseg_total_freq (segT seg
, subsegT subseg
)
9632 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9634 return subseg_e
->total_freq
;
9640 get_subseg_target_freq (segT seg
, subsegT subseg
)
9642 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9644 return subseg_e
->target_freq
;
9650 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
9652 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9654 subseg_e
= add_subseg_info (seg
, subseg
);
9655 subseg_e
->total_freq
= total_f
;
9656 subseg_e
->target_freq
= target_f
;
9660 /* Segment Lists and emit_state Stuff. */
9663 xtensa_move_seg_list_to_beginning (seg_list
*head
)
9668 segT literal_section
= head
->seg
;
9670 /* Move the literal section to the front of the section list. */
9671 assert (literal_section
);
9672 if (literal_section
!= stdoutput
->sections
)
9674 bfd_section_list_remove (stdoutput
, literal_section
);
9675 bfd_section_list_prepend (stdoutput
, literal_section
);
9682 static void mark_literal_frags (seg_list
*);
9685 xtensa_move_literals (void)
9688 frchainS
*frchain_from
, *frchain_to
;
9689 fragS
*search_frag
, *next_frag
, *last_frag
, *literal_pool
, *insert_after
;
9690 fragS
**frag_splice
;
9693 fixS
*fix
, *next_fix
, **fix_splice
;
9696 mark_literal_frags (literal_head
->next
);
9697 mark_literal_frags (init_literal_head
->next
);
9698 mark_literal_frags (fini_literal_head
->next
);
9700 if (use_literal_section
)
9703 segment
= literal_head
->next
;
9706 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9707 search_frag
= frchain_from
->frch_root
;
9708 literal_pool
= NULL
;
9710 frag_splice
= &(frchain_from
->frch_root
);
9712 while (!search_frag
->tc_frag_data
.literal_frag
)
9714 assert (search_frag
->fr_fix
== 0
9715 || search_frag
->fr_type
== rs_align
);
9716 search_frag
= search_frag
->fr_next
;
9719 assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
9720 == RELAX_LITERAL_POOL_BEGIN
);
9721 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
9723 /* Make sure that all the frags in this series are closed, and
9724 that there is at least one left over of zero-size. This
9725 prevents us from making a segment with an frchain without any
9727 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9728 xtensa_set_frag_assembly_state (frag_now
);
9729 last_frag
= frag_now
;
9730 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9731 xtensa_set_frag_assembly_state (frag_now
);
9733 while (search_frag
!= frag_now
)
9735 next_frag
= search_frag
->fr_next
;
9737 /* First, move the frag out of the literal section and
9738 to the appropriate place. */
9739 if (search_frag
->tc_frag_data
.literal_frag
)
9741 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
9742 assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
9743 frchain_to
= literal_pool
->tc_frag_data
.lit_frchain
;
9744 assert (frchain_to
);
9746 insert_after
= literal_pool
;
9748 while (insert_after
->fr_next
->fr_subtype
!= RELAX_LITERAL_POOL_END
)
9749 insert_after
= insert_after
->fr_next
;
9751 dest_seg
= insert_after
->fr_next
->tc_frag_data
.lit_seg
;
9753 *frag_splice
= next_frag
;
9754 search_frag
->fr_next
= insert_after
->fr_next
;
9755 insert_after
->fr_next
= search_frag
;
9756 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
9758 /* Now move any fixups associated with this frag to the
9760 fix
= frchain_from
->fix_root
;
9761 fix_splice
= &(frchain_from
->fix_root
);
9764 next_fix
= fix
->fx_next
;
9765 if (fix
->fx_frag
== search_frag
)
9767 *fix_splice
= next_fix
;
9768 fix
->fx_next
= frchain_to
->fix_root
;
9769 frchain_to
->fix_root
= fix
;
9770 if (frchain_to
->fix_tail
== NULL
)
9771 frchain_to
->fix_tail
= fix
;
9774 fix_splice
= &(fix
->fx_next
);
9777 search_frag
= next_frag
;
9780 if (frchain_from
->fix_root
!= NULL
)
9782 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9783 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
9785 assert (frchain_from
->fix_root
== NULL
);
9787 frchain_from
->fix_tail
= NULL
;
9788 xtensa_restore_emit_state (&state
);
9789 segment
= segment
->next
;
9792 /* Now fix up the SEGMENT value for all the literal symbols. */
9793 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
9795 symbolS
*lit_sym
= lit
->sym
;
9796 segT dest_seg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
9798 S_SET_SEGMENT (lit_sym
, dest_seg
);
9803 /* Walk over all the frags for segments in a list and mark them as
9804 containing literals. As clunky as this is, we can't rely on frag_var
9805 and frag_variant to get called in all situations. */
9808 mark_literal_frags (seg_list
*segment
)
9810 frchainS
*frchain_from
;
9815 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9816 search_frag
= frchain_from
->frch_root
;
9819 search_frag
->tc_frag_data
.is_literal
= TRUE
;
9820 search_frag
= search_frag
->fr_next
;
9822 segment
= segment
->next
;
9828 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
9830 /* Move all of the sections in the section list to come
9831 after "after" in the gnu segment list. */
9836 segT literal_section
= head
->seg
;
9838 /* Move the literal section after "after". */
9839 assert (literal_section
);
9840 if (literal_section
!= after
)
9842 bfd_section_list_remove (stdoutput
, literal_section
);
9843 bfd_section_list_insert_after (stdoutput
, after
, literal_section
);
9851 /* Push all the literal segments to the end of the gnu list. */
9854 xtensa_reorder_segments (void)
9861 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
9867 /* Now that we have the last section, push all the literal
9868 sections to the end. */
9869 xtensa_reorder_seg_list (literal_head
, last_sec
);
9870 xtensa_reorder_seg_list (init_literal_head
, last_sec
);
9871 xtensa_reorder_seg_list (fini_literal_head
, last_sec
);
9873 /* Now perform the final error check. */
9874 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
9876 assert (new_count
== old_count
);
9880 /* Change the emit state (seg, subseg, and frag related stuff) to the
9881 correct location. Return a emit_state which can be passed to
9882 xtensa_restore_emit_state to return to current fragment. */
9885 xtensa_switch_to_literal_fragment (emit_state
*result
)
9887 if (directive_state
[directive_absolute_literals
])
9889 cache_literal_section (0, default_lit_sections
.lit4_seg_name
,
9890 &default_lit_sections
.lit4_seg
, FALSE
);
9891 xtensa_switch_section_emit_state (result
,
9892 default_lit_sections
.lit4_seg
, 0);
9895 xtensa_switch_to_non_abs_literal_fragment (result
);
9897 /* Do a 4-byte align here. */
9898 frag_align (2, 0, 0);
9899 record_alignment (now_seg
, 2);
9904 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
9906 /* When we mark a literal pool location, we want to put a frag in
9907 the literal pool that points to it. But to do that, we want to
9908 switch_to_literal_fragment. But literal sections don't have
9909 literal pools, so their location is always null, so we would
9910 recurse forever. This is kind of hacky, but it works. */
9912 static bfd_boolean recursive
= FALSE
;
9913 fragS
*pool_location
= get_literal_pool_location (now_seg
);
9914 bfd_boolean is_init
=
9915 (now_seg
&& !strcmp (segment_name (now_seg
), INIT_SECTION_NAME
));
9917 bfd_boolean is_fini
=
9918 (now_seg
&& !strcmp (segment_name (now_seg
), FINI_SECTION_NAME
));
9920 if (pool_location
== NULL
9921 && !use_literal_section
9923 && !is_init
&& ! is_fini
)
9925 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
9927 xtensa_mark_literal_pool_location ();
9931 /* Special case: If we are in the ".fini" or ".init" section, then
9932 we will ALWAYS be generating to the ".fini.literal" and
9933 ".init.literal" sections. */
9937 cache_literal_section (init_literal_head
,
9938 default_lit_sections
.init_lit_seg_name
,
9939 &default_lit_sections
.init_lit_seg
, TRUE
);
9940 xtensa_switch_section_emit_state (result
,
9941 default_lit_sections
.init_lit_seg
, 0);
9945 cache_literal_section (fini_literal_head
,
9946 default_lit_sections
.fini_lit_seg_name
,
9947 &default_lit_sections
.fini_lit_seg
, TRUE
);
9948 xtensa_switch_section_emit_state (result
,
9949 default_lit_sections
.fini_lit_seg
, 0);
9953 cache_literal_section (literal_head
,
9954 default_lit_sections
.lit_seg_name
,
9955 &default_lit_sections
.lit_seg
, TRUE
);
9956 xtensa_switch_section_emit_state (result
,
9957 default_lit_sections
.lit_seg
, 0);
9960 if (!use_literal_section
9961 && !is_init
&& !is_fini
9962 && get_literal_pool_location (now_seg
) != pool_location
)
9964 /* Close whatever frag is there. */
9965 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9966 xtensa_set_frag_assembly_state (frag_now
);
9967 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
9968 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9969 xtensa_set_frag_assembly_state (frag_now
);
9974 /* Call this function before emitting data into the literal section.
9975 This is a helper function for xtensa_switch_to_literal_fragment.
9976 This is similar to a .section new_now_seg subseg. */
9979 xtensa_switch_section_emit_state (emit_state
*state
,
9981 subsegT new_now_subseg
)
9983 state
->name
= now_seg
->name
;
9984 state
->now_seg
= now_seg
;
9985 state
->now_subseg
= now_subseg
;
9986 state
->generating_literals
= generating_literals
;
9987 generating_literals
++;
9988 subseg_set (new_now_seg
, new_now_subseg
);
9992 /* Use to restore the emitting into the normal place. */
9995 xtensa_restore_emit_state (emit_state
*state
)
9997 generating_literals
= state
->generating_literals
;
9998 subseg_set (state
->now_seg
, state
->now_subseg
);
10002 /* Get a segment of a given name. If the segment is already
10003 present, return it; otherwise, create a new one. */
10006 cache_literal_section (seg_list
*head
,
10009 bfd_boolean is_code
)
10011 segT current_section
= now_seg
;
10012 int current_subsec
= now_subseg
;
10018 /* Check if the named section exists. */
10019 for (seg
= stdoutput
->sections
; seg
; seg
= seg
->next
)
10021 if (!strcmp (segment_name (seg
), name
))
10027 /* Create a new literal section. */
10028 seg
= subseg_new (name
, (subsegT
) 0);
10031 /* Add the newly created literal segment to the specified list. */
10032 seg_list
*n
= (seg_list
*) xmalloc (sizeof (seg_list
));
10034 n
->next
= head
->next
;
10037 bfd_set_section_flags (stdoutput
, seg
, SEC_HAS_CONTENTS
|
10038 SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
10039 | (is_code
? SEC_CODE
: SEC_DATA
));
10040 bfd_set_section_alignment (stdoutput
, seg
, 2);
10044 subseg_set (current_section
, current_subsec
);
10048 /* Property Tables Stuff. */
10050 #define XTENSA_INSN_SEC_NAME ".xt.insn"
10051 #define XTENSA_LIT_SEC_NAME ".xt.lit"
10052 #define XTENSA_PROP_SEC_NAME ".xt.prop"
10054 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
10055 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
10057 static bfd_boolean
get_frag_is_literal (const fragS
*);
10058 static void xtensa_create_property_segments
10059 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
10060 static void xtensa_create_xproperty_segments
10061 (frag_flags_fn
, const char *, xt_section_type
);
10062 static segment_info_type
*retrieve_segment_info (segT
);
10063 static segT
retrieve_xtensa_section (char *);
10064 static bfd_boolean
section_has_property (segT
, frag_predicate
);
10065 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
10066 static void add_xt_block_frags
10067 (segT
, segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
10068 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
10069 static void xtensa_frag_flags_init (frag_flags
*);
10070 static void get_frag_property_flags (const fragS
*, frag_flags
*);
10071 static bfd_vma
frag_flags_to_number (const frag_flags
*);
10072 static void add_xt_prop_frags
10073 (segT
, segT
, xtensa_block_info
**, frag_flags_fn
);
10075 /* Set up property tables after relaxation. */
10078 xtensa_post_relax_hook (void)
10080 xtensa_move_seg_list_to_beginning (literal_head
);
10081 xtensa_move_seg_list_to_beginning (init_literal_head
);
10082 xtensa_move_seg_list_to_beginning (fini_literal_head
);
10084 xtensa_find_unmarked_state_frags ();
10086 xtensa_create_property_segments (get_frag_is_literal
,
10088 XTENSA_LIT_SEC_NAME
,
10090 xtensa_create_xproperty_segments (get_frag_property_flags
,
10091 XTENSA_PROP_SEC_NAME
,
10094 if (warn_unaligned_branch_targets
)
10095 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
10096 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
10100 /* This function is only meaningful after xtensa_move_literals. */
10103 get_frag_is_literal (const fragS
*fragP
)
10105 assert (fragP
!= NULL
);
10106 return fragP
->tc_frag_data
.is_literal
;
10111 xtensa_create_property_segments (frag_predicate property_function
,
10112 frag_predicate end_property_function
,
10113 const char *section_name_base
,
10114 xt_section_type sec_type
)
10118 /* Walk over all of the current segments.
10119 Walk over each fragment
10120 For each non-empty fragment,
10121 Build a property record (append where possible). */
10123 for (seclist
= &stdoutput
->sections
;
10124 seclist
&& *seclist
;
10125 seclist
= &(*seclist
)->next
)
10127 segT sec
= *seclist
;
10130 flags
= bfd_get_section_flags (stdoutput
, sec
);
10131 if (flags
& SEC_DEBUGGING
)
10133 if (!(flags
& SEC_ALLOC
))
10136 if (section_has_property (sec
, property_function
))
10138 char *property_section_name
=
10139 xtensa_get_property_section_name (sec
, section_name_base
);
10140 segT insn_sec
= retrieve_xtensa_section (property_section_name
);
10141 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10142 xtensa_block_info
**xt_blocks
=
10143 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10144 /* Walk over all of the frchains here and add new sections. */
10145 add_xt_block_frags (sec
, insn_sec
, xt_blocks
, property_function
,
10146 end_property_function
);
10150 /* Now we fill them out.... */
10152 for (seclist
= &stdoutput
->sections
;
10153 seclist
&& *seclist
;
10154 seclist
= &(*seclist
)->next
)
10156 segment_info_type
*seginfo
;
10157 xtensa_block_info
*block
;
10158 segT sec
= *seclist
;
10160 seginfo
= seg_info (sec
);
10161 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10165 xtensa_block_info
*cur_block
;
10166 /* This is a section with some data. */
10168 bfd_size_type rec_size
;
10170 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10173 rec_size
= num_recs
* 8;
10174 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10176 /* In order to make this work with the assembler, we have to
10177 build some frags and then build the "fixups" for it. It
10178 would be easier to just set the contents then set the
10183 /* Allocate a fragment and leak it. */
10185 bfd_size_type frag_size
;
10187 frchainS
*frchainP
;
10191 frag_size
= sizeof (fragS
) + rec_size
;
10192 fragP
= (fragS
*) xmalloc (frag_size
);
10194 memset (fragP
, 0, frag_size
);
10195 fragP
->fr_address
= 0;
10196 fragP
->fr_next
= NULL
;
10197 fragP
->fr_fix
= rec_size
;
10199 fragP
->fr_type
= rs_fill
;
10200 /* The rest are zeros. */
10202 frchainP
= seginfo
->frchainP
;
10203 frchainP
->frch_root
= fragP
;
10204 frchainP
->frch_last
= fragP
;
10206 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10207 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10209 seginfo
->fix_root
= fixes
;
10210 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10212 frag_data
= &fragP
->fr_literal
[0];
10213 for (i
= 0; i
< num_recs
; i
++)
10215 fixS
*fix
= &fixes
[i
];
10216 assert (cur_block
);
10218 /* Write the fixup. */
10219 if (i
!= num_recs
- 1)
10220 fix
->fx_next
= &fixes
[i
+ 1];
10222 fix
->fx_next
= NULL
;
10225 fix
->fx_frag
= fragP
;
10226 fix
->fx_where
= i
* 8;
10227 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10228 fix
->fx_offset
= cur_block
->offset
;
10229 fix
->fx_r_type
= BFD_RELOC_32
;
10230 fix
->fx_file
= "Internal Assembly";
10233 /* Write the length. */
10234 md_number_to_chars (&frag_data
[4 + 8 * i
],
10235 cur_block
->size
, 4);
10236 cur_block
= cur_block
->next
;
10245 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
10246 const char *section_name_base
,
10247 xt_section_type sec_type
)
10251 /* Walk over all of the current segments.
10252 Walk over each fragment.
10253 For each fragment that has instructions,
10254 build an instruction record (append where possible). */
10256 for (seclist
= &stdoutput
->sections
;
10257 seclist
&& *seclist
;
10258 seclist
= &(*seclist
)->next
)
10260 segT sec
= *seclist
;
10263 flags
= bfd_get_section_flags (stdoutput
, sec
);
10264 if ((flags
& SEC_DEBUGGING
)
10265 || !(flags
& SEC_ALLOC
)
10266 || (flags
& SEC_MERGE
))
10269 if (section_has_xproperty (sec
, flag_fn
))
10271 char *property_section_name
=
10272 xtensa_get_property_section_name (sec
, section_name_base
);
10273 segT insn_sec
= retrieve_xtensa_section (property_section_name
);
10274 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10275 xtensa_block_info
**xt_blocks
=
10276 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10277 /* Walk over all of the frchains here and add new sections. */
10278 add_xt_prop_frags (sec
, insn_sec
, xt_blocks
, flag_fn
);
10282 /* Now we fill them out.... */
10284 for (seclist
= &stdoutput
->sections
;
10285 seclist
&& *seclist
;
10286 seclist
= &(*seclist
)->next
)
10288 segment_info_type
*seginfo
;
10289 xtensa_block_info
*block
;
10290 segT sec
= *seclist
;
10292 seginfo
= seg_info (sec
);
10293 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10297 xtensa_block_info
*cur_block
;
10298 /* This is a section with some data. */
10300 bfd_size_type rec_size
;
10302 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10305 rec_size
= num_recs
* (8 + 4);
10306 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10308 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
10310 /* In order to make this work with the assembler, we have to build
10311 some frags then build the "fixups" for it. It would be easier to
10312 just set the contents then set the arlents. */
10316 /* Allocate a fragment and (unfortunately) leak it. */
10318 bfd_size_type frag_size
;
10320 frchainS
*frchainP
;
10324 frag_size
= sizeof (fragS
) + rec_size
;
10325 fragP
= (fragS
*) xmalloc (frag_size
);
10327 memset (fragP
, 0, frag_size
);
10328 fragP
->fr_address
= 0;
10329 fragP
->fr_next
= NULL
;
10330 fragP
->fr_fix
= rec_size
;
10332 fragP
->fr_type
= rs_fill
;
10333 /* The rest are zeros. */
10335 frchainP
= seginfo
->frchainP
;
10336 frchainP
->frch_root
= fragP
;
10337 frchainP
->frch_last
= fragP
;
10339 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10340 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10342 seginfo
->fix_root
= fixes
;
10343 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10345 frag_data
= &fragP
->fr_literal
[0];
10346 for (i
= 0; i
< num_recs
; i
++)
10348 fixS
*fix
= &fixes
[i
];
10349 assert (cur_block
);
10351 /* Write the fixup. */
10352 if (i
!= num_recs
- 1)
10353 fix
->fx_next
= &fixes
[i
+ 1];
10355 fix
->fx_next
= NULL
;
10358 fix
->fx_frag
= fragP
;
10359 fix
->fx_where
= i
* (8 + 4);
10360 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10361 fix
->fx_offset
= cur_block
->offset
;
10362 fix
->fx_r_type
= BFD_RELOC_32
;
10363 fix
->fx_file
= "Internal Assembly";
10366 /* Write the length. */
10367 md_number_to_chars (&frag_data
[4 + (8+4) * i
],
10368 cur_block
->size
, 4);
10369 md_number_to_chars (&frag_data
[8 + (8+4) * i
],
10370 frag_flags_to_number (&cur_block
->flags
),
10372 cur_block
= cur_block
->next
;
10380 static segment_info_type
*
10381 retrieve_segment_info (segT seg
)
10383 segment_info_type
*seginfo
;
10384 seginfo
= (segment_info_type
*) bfd_get_section_userdata (stdoutput
, seg
);
10387 frchainS
*frchainP
;
10389 seginfo
= (segment_info_type
*) xmalloc (sizeof (*seginfo
));
10390 memset ((void *) seginfo
, 0, sizeof (*seginfo
));
10391 seginfo
->fix_root
= NULL
;
10392 seginfo
->fix_tail
= NULL
;
10393 seginfo
->bfd_section
= seg
;
10395 /* We will not be dealing with these, only our special ones. */
10396 bfd_set_section_userdata (stdoutput
, seg
, (void *) seginfo
);
10398 frchainP
= (frchainS
*) xmalloc (sizeof (frchainS
));
10399 frchainP
->frch_root
= NULL
;
10400 frchainP
->frch_last
= NULL
;
10401 frchainP
->frch_next
= NULL
;
10402 frchainP
->frch_subseg
= 0;
10403 frchainP
->fix_root
= NULL
;
10404 frchainP
->fix_tail
= NULL
;
10405 /* Do not init the objstack. */
10406 /* obstack_begin (&frchainP->frch_obstack, chunksize); */
10407 /* frchainP->frch_frag_now = fragP; */
10408 frchainP
->frch_frag_now
= NULL
;
10410 seginfo
->frchainP
= frchainP
;
10418 retrieve_xtensa_section (char *sec_name
)
10420 bfd
*abfd
= stdoutput
;
10421 flagword flags
, out_flags
, link_once_flags
;
10424 flags
= bfd_get_section_flags (abfd
, now_seg
);
10425 link_once_flags
= (flags
& SEC_LINK_ONCE
);
10426 if (link_once_flags
)
10427 link_once_flags
|= (flags
& SEC_LINK_DUPLICATES
);
10428 out_flags
= (SEC_RELOC
| SEC_HAS_CONTENTS
| SEC_READONLY
| link_once_flags
);
10430 s
= bfd_make_section_old_way (abfd
, sec_name
);
10432 as_bad (_("could not create section %s"), sec_name
);
10433 if (!bfd_set_section_flags (abfd
, s
, out_flags
))
10434 as_bad (_("invalid flag combination on section %s"), sec_name
);
10441 section_has_property (segT sec
, frag_predicate property_function
)
10443 segment_info_type
*seginfo
= seg_info (sec
);
10446 if (seginfo
&& seginfo
->frchainP
)
10448 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10450 if (property_function (fragP
)
10451 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10460 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
10462 segment_info_type
*seginfo
= seg_info (sec
);
10465 if (seginfo
&& seginfo
->frchainP
)
10467 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10469 frag_flags prop_flags
;
10470 property_function (fragP
, &prop_flags
);
10471 if (!xtensa_frag_flags_is_empty (&prop_flags
))
10479 /* Two types of block sections exist right now: literal and insns. */
10482 add_xt_block_frags (segT sec
,
10484 xtensa_block_info
**xt_block
,
10485 frag_predicate property_function
,
10486 frag_predicate end_property_function
)
10488 segment_info_type
*seg_info
;
10489 segment_info_type
*xt_seg_info
;
10490 bfd_vma seg_offset
;
10493 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
10494 seg_info
= retrieve_segment_info (sec
);
10496 /* Build it if needed. */
10497 while (*xt_block
!= NULL
)
10498 xt_block
= &(*xt_block
)->next
;
10499 /* We are either at NULL at the beginning or at the end. */
10501 /* Walk through the frags. */
10504 if (seg_info
->frchainP
)
10506 for (fragP
= seg_info
->frchainP
->frch_root
;
10508 fragP
= fragP
->fr_next
)
10510 if (property_function (fragP
)
10511 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10513 if (*xt_block
!= NULL
)
10515 if ((*xt_block
)->offset
+ (*xt_block
)->size
10516 == fragP
->fr_address
)
10517 (*xt_block
)->size
+= fragP
->fr_fix
;
10519 xt_block
= &((*xt_block
)->next
);
10521 if (*xt_block
== NULL
)
10523 xtensa_block_info
*new_block
= (xtensa_block_info
*)
10524 xmalloc (sizeof (xtensa_block_info
));
10525 new_block
->sec
= sec
;
10526 new_block
->offset
= fragP
->fr_address
;
10527 new_block
->size
= fragP
->fr_fix
;
10528 new_block
->next
= NULL
;
10529 xtensa_frag_flags_init (&new_block
->flags
);
10530 *xt_block
= new_block
;
10532 if (end_property_function
10533 && end_property_function (fragP
))
10535 xt_block
= &((*xt_block
)->next
);
10543 /* Break the encapsulation of add_xt_prop_frags here. */
10546 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
10548 if (prop_flags
->is_literal
10549 || prop_flags
->is_insn
10550 || prop_flags
->is_data
10551 || prop_flags
->is_unreachable
)
10558 xtensa_frag_flags_init (frag_flags
*prop_flags
)
10560 memset (prop_flags
, 0, sizeof (frag_flags
));
10565 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
10567 xtensa_frag_flags_init (prop_flags
);
10568 if (fragP
->tc_frag_data
.is_literal
)
10569 prop_flags
->is_literal
= TRUE
;
10570 if (fragP
->tc_frag_data
.is_unreachable
)
10571 prop_flags
->is_unreachable
= TRUE
;
10572 else if (fragP
->tc_frag_data
.is_insn
)
10574 prop_flags
->is_insn
= TRUE
;
10575 if (fragP
->tc_frag_data
.is_loop_target
)
10576 prop_flags
->insn
.is_loop_target
= TRUE
;
10577 if (fragP
->tc_frag_data
.is_branch_target
)
10578 prop_flags
->insn
.is_branch_target
= TRUE
;
10579 if (fragP
->tc_frag_data
.is_specific_opcode
10580 || fragP
->tc_frag_data
.is_no_transform
)
10581 prop_flags
->insn
.is_no_transform
= TRUE
;
10582 if (fragP
->tc_frag_data
.is_no_density
)
10583 prop_flags
->insn
.is_no_density
= TRUE
;
10584 if (fragP
->tc_frag_data
.use_absolute_literals
)
10585 prop_flags
->insn
.is_abslit
= TRUE
;
10587 if (fragP
->tc_frag_data
.is_align
)
10589 prop_flags
->is_align
= TRUE
;
10590 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
10591 if (xtensa_frag_flags_is_empty (prop_flags
))
10592 prop_flags
->is_data
= TRUE
;
10598 frag_flags_to_number (const frag_flags
*prop_flags
)
10601 if (prop_flags
->is_literal
)
10602 num
|= XTENSA_PROP_LITERAL
;
10603 if (prop_flags
->is_insn
)
10604 num
|= XTENSA_PROP_INSN
;
10605 if (prop_flags
->is_data
)
10606 num
|= XTENSA_PROP_DATA
;
10607 if (prop_flags
->is_unreachable
)
10608 num
|= XTENSA_PROP_UNREACHABLE
;
10609 if (prop_flags
->insn
.is_loop_target
)
10610 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
10611 if (prop_flags
->insn
.is_branch_target
)
10613 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
10614 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
10617 if (prop_flags
->insn
.is_no_density
)
10618 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
10619 if (prop_flags
->insn
.is_no_transform
)
10620 num
|= XTENSA_PROP_INSN_NO_TRANSFORM
;
10621 if (prop_flags
->insn
.is_no_reorder
)
10622 num
|= XTENSA_PROP_INSN_NO_REORDER
;
10623 if (prop_flags
->insn
.is_abslit
)
10624 num
|= XTENSA_PROP_INSN_ABSLIT
;
10626 if (prop_flags
->is_align
)
10628 num
|= XTENSA_PROP_ALIGN
;
10629 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
10637 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
10638 const frag_flags
*prop_flags_2
)
10640 /* Cannot combine with an end marker. */
10642 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
10644 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
10646 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
10649 if (prop_flags_1
->is_insn
)
10651 /* Properties of the beginning of the frag. */
10652 if (prop_flags_2
->insn
.is_loop_target
)
10654 if (prop_flags_2
->insn
.is_branch_target
)
10656 if (prop_flags_1
->insn
.is_no_density
!=
10657 prop_flags_2
->insn
.is_no_density
)
10659 if (prop_flags_1
->insn
.is_no_transform
!=
10660 prop_flags_2
->insn
.is_no_transform
)
10662 if (prop_flags_1
->insn
.is_no_reorder
!=
10663 prop_flags_2
->insn
.is_no_reorder
)
10665 if (prop_flags_1
->insn
.is_abslit
!=
10666 prop_flags_2
->insn
.is_abslit
)
10670 if (prop_flags_1
->is_align
)
10678 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
10681 unsigned align_bits
;
10683 if (!xt_block
->flags
.is_align
)
10684 return xt_block
->size
;
10686 end_addr
= xt_block
->offset
+ xt_block
->size
;
10687 align_bits
= xt_block
->flags
.alignment
;
10688 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
10689 return end_addr
- xt_block
->offset
;
10694 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
10695 const xtensa_block_info
*xt_block_2
)
10697 if (xt_block
->sec
!= xt_block_2
->sec
)
10699 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
10700 != xt_block_2
->offset
)
10703 if (xt_block_2
->size
== 0
10704 && (!xt_block_2
->flags
.is_unreachable
10705 || xt_block
->flags
.is_unreachable
))
10707 if (xt_block_2
->flags
.is_align
10708 && xt_block
->flags
.is_align
)
10710 /* Nothing needed. */
10711 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
10716 if (xt_block_2
->flags
.is_align
)
10718 /* Push alignment to previous entry. */
10719 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
10720 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10725 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
10726 &xt_block_2
->flags
))
10729 xt_block
->size
+= xt_block_2
->size
;
10731 if (xt_block_2
->flags
.is_align
)
10733 xt_block
->flags
.is_align
= TRUE
;
10734 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10742 add_xt_prop_frags (segT sec
,
10744 xtensa_block_info
**xt_block
,
10745 frag_flags_fn property_function
)
10747 segment_info_type
*seg_info
;
10748 segment_info_type
*xt_seg_info
;
10749 bfd_vma seg_offset
;
10752 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
10753 seg_info
= retrieve_segment_info (sec
);
10754 /* Build it if needed. */
10755 while (*xt_block
!= NULL
)
10757 xt_block
= &(*xt_block
)->next
;
10759 /* We are either at NULL at the beginning or at the end. */
10761 /* Walk through the frags. */
10764 if (seg_info
->frchainP
)
10766 for (fragP
= seg_info
->frchainP
->frch_root
; fragP
;
10767 fragP
= fragP
->fr_next
)
10769 xtensa_block_info tmp_block
;
10770 tmp_block
.sec
= sec
;
10771 tmp_block
.offset
= fragP
->fr_address
;
10772 tmp_block
.size
= fragP
->fr_fix
;
10773 tmp_block
.next
= NULL
;
10774 property_function (fragP
, &tmp_block
.flags
);
10776 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
10777 /* && fragP->fr_fix != 0) */
10779 if ((*xt_block
) == NULL
10780 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
10782 xtensa_block_info
*new_block
;
10783 if ((*xt_block
) != NULL
)
10784 xt_block
= &(*xt_block
)->next
;
10785 new_block
= (xtensa_block_info
*)
10786 xmalloc (sizeof (xtensa_block_info
));
10787 *new_block
= tmp_block
;
10788 *xt_block
= new_block
;
10796 /* op_placement_info_table */
10798 /* op_placement_info makes it easier to determine which
10799 ops can go in which slots. */
10802 init_op_placement_info_table (void)
10804 xtensa_isa isa
= xtensa_default_isa
;
10805 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
10806 xtensa_opcode opcode
;
10809 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
10811 op_placement_table
= (op_placement_info_table
)
10812 xmalloc (sizeof (op_placement_info
) * num_opcodes
);
10813 assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
10815 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
10817 op_placement_info
*opi
= &op_placement_table
[opcode
];
10818 /* FIXME: Make tinsn allocation dynamic. */
10819 if (xtensa_opcode_num_operands (isa
, opcode
) >= MAX_INSN_ARGS
)
10820 as_fatal (_("too many operands in instruction"));
10821 opi
->narrowest
= XTENSA_UNDEFINED
;
10822 opi
->narrowest_size
= 0x7F;
10823 opi
->narrowest_slot
= 0;
10825 opi
->num_formats
= 0;
10827 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
10829 opi
->slots
[fmt
] = 0;
10830 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
10832 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
10834 int fmt_length
= xtensa_format_length (isa
, fmt
);
10836 set_bit (fmt
, opi
->formats
);
10837 set_bit (slot
, opi
->slots
[fmt
]);
10838 if (fmt_length
< opi
->narrowest_size
10839 || (fmt_length
== opi
->narrowest_size
10840 && (xtensa_format_num_slots (isa
, fmt
)
10841 < xtensa_format_num_slots (isa
,
10844 opi
->narrowest
= fmt
;
10845 opi
->narrowest_size
= fmt_length
;
10846 opi
->narrowest_slot
= slot
;
10851 opi
->num_formats
++;
10854 xtensa_insnbuf_free (isa
, ibuf
);
10859 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
10861 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
10865 /* If the opcode is available in a single slot format, return its size. */
10868 xg_get_single_size (xtensa_opcode opcode
)
10870 return op_placement_table
[opcode
].narrowest_size
;
10874 static xtensa_format
10875 xg_get_single_format (xtensa_opcode opcode
)
10877 return op_placement_table
[opcode
].narrowest
;
10882 xg_get_single_slot (xtensa_opcode opcode
)
10884 return op_placement_table
[opcode
].narrowest_slot
;
10888 /* Instruction Stack Functions (from "xtensa-istack.h"). */
10891 istack_init (IStack
*stack
)
10893 memset (stack
, 0, sizeof (IStack
));
10899 istack_empty (IStack
*stack
)
10901 return (stack
->ninsn
== 0);
10906 istack_full (IStack
*stack
)
10908 return (stack
->ninsn
== MAX_ISTACK
);
10912 /* Return a pointer to the top IStack entry.
10913 It is an error to call this if istack_empty () is TRUE. */
10916 istack_top (IStack
*stack
)
10918 int rec
= stack
->ninsn
- 1;
10919 assert (!istack_empty (stack
));
10920 return &stack
->insn
[rec
];
10924 /* Add a new TInsn to an IStack.
10925 It is an error to call this if istack_full () is TRUE. */
10928 istack_push (IStack
*stack
, TInsn
*insn
)
10930 int rec
= stack
->ninsn
;
10931 assert (!istack_full (stack
));
10932 stack
->insn
[rec
] = *insn
;
10937 /* Clear space for the next TInsn on the IStack and return a pointer
10938 to it. It is an error to call this if istack_full () is TRUE. */
10941 istack_push_space (IStack
*stack
)
10943 int rec
= stack
->ninsn
;
10945 assert (!istack_full (stack
));
10946 insn
= &stack
->insn
[rec
];
10947 memset (insn
, 0, sizeof (TInsn
));
10953 /* Remove the last pushed instruction. It is an error to call this if
10954 istack_empty () returns TRUE. */
10957 istack_pop (IStack
*stack
)
10959 int rec
= stack
->ninsn
- 1;
10960 assert (!istack_empty (stack
));
10962 memset (&stack
->insn
[rec
], 0, sizeof (TInsn
));
10966 /* TInsn functions. */
10969 tinsn_init (TInsn
*dst
)
10971 memset (dst
, 0, sizeof (TInsn
));
10975 /* Get the ``num''th token of the TInsn.
10976 It is illegal to call this if num > insn->ntoks. */
10979 tinsn_get_tok (TInsn
*insn
, int num
)
10981 assert (num
< insn
->ntok
);
10982 return &insn
->tok
[num
];
10986 /* Return TRUE if ANY of the operands in the insn are symbolic. */
10989 tinsn_has_symbolic_operands (const TInsn
*insn
)
10992 int n
= insn
->ntok
;
10994 assert (insn
->insn_type
== ITYPE_INSN
);
10996 for (i
= 0; i
< n
; ++i
)
10998 switch (insn
->tok
[i
].X_op
)
11012 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
11014 xtensa_isa isa
= xtensa_default_isa
;
11016 int n
= insn
->ntok
;
11018 assert (insn
->insn_type
== ITYPE_INSN
);
11020 for (i
= 0; i
< n
; ++i
)
11022 switch (insn
->tok
[i
].X_op
)
11030 /* Errors for these types are caught later. */
11035 /* Symbolic immediates are only allowed on the last immediate
11036 operand. At this time, CONST16 is the only opcode where we
11037 support non-PC-relative relocations. */
11038 if (i
!= get_relaxable_immed (insn
->opcode
)
11039 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
11040 && insn
->opcode
!= xtensa_const16_opcode
))
11042 as_bad (_("invalid symbolic operand"));
11051 /* For assembly code with complex expressions (e.g. subtraction),
11052 we have to build them in the literal pool so that
11053 their results are calculated correctly after relaxation.
11054 The relaxation only handles expressions that
11055 boil down to SYMBOL + OFFSET. */
11058 tinsn_has_complex_operands (const TInsn
*insn
)
11061 int n
= insn
->ntok
;
11062 assert (insn
->insn_type
== ITYPE_INSN
);
11063 for (i
= 0; i
< n
; ++i
)
11065 switch (insn
->tok
[i
].X_op
)
11081 /* Encode a TInsn opcode and its constant operands into slotbuf.
11082 Return TRUE if there is a symbol in the immediate field. This
11083 function assumes that:
11084 1) The number of operands are correct.
11085 2) The insn_type is ITYPE_INSN.
11086 3) The opcode can be encoded in the specified format and slot.
11087 4) Operands are either O_constant or O_symbol, and all constants fit. */
11090 tinsn_to_slotbuf (xtensa_format fmt
,
11093 xtensa_insnbuf slotbuf
)
11095 xtensa_isa isa
= xtensa_default_isa
;
11096 xtensa_opcode opcode
= tinsn
->opcode
;
11097 bfd_boolean has_fixup
= FALSE
;
11098 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11101 assert (tinsn
->insn_type
== ITYPE_INSN
);
11102 if (noperands
!= tinsn
->ntok
)
11103 as_fatal (_("operand number mismatch"));
11105 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
11107 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
11108 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
11112 for (i
= 0; i
< noperands
; i
++)
11114 expressionS
*expr
= &tinsn
->tok
[i
];
11120 switch (expr
->X_op
)
11123 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11125 /* The register number has already been checked in
11126 expression_maybe_register, so we don't need to check here. */
11127 opnd_value
= expr
->X_add_number
;
11128 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11129 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
11132 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
11136 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11138 as_where (&file_name
, &line
);
11139 /* It is a constant and we called this function
11140 then we have to try to fit it. */
11141 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
11142 expr
->X_add_number
, file_name
, line
);
11155 /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded
11156 into a multi-slot instruction, fill the other slots with NOPs.
11157 Return TRUE if there is a symbol in the immediate field. See also the
11158 assumptions listed for tinsn_to_slotbuf. */
11161 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
11163 static xtensa_insnbuf slotbuf
= 0;
11164 static vliw_insn vinsn
;
11165 xtensa_isa isa
= xtensa_default_isa
;
11166 bfd_boolean has_fixup
= FALSE
;
11171 slotbuf
= xtensa_insnbuf_alloc (isa
);
11172 xg_init_vinsn (&vinsn
);
11175 xg_clear_vinsn (&vinsn
);
11177 bundle_tinsn (tinsn
, &vinsn
);
11179 xtensa_format_encode (isa
, vinsn
.format
, insnbuf
);
11181 for (i
= 0; i
< vinsn
.num_slots
; i
++)
11183 /* Only one slot may have a fix-up because the rest contains NOPs. */
11185 tinsn_to_slotbuf (vinsn
.format
, i
, &vinsn
.slots
[i
], vinsn
.slotbuf
[i
]);
11186 xtensa_format_set_slot (isa
, vinsn
.format
, i
, insnbuf
, vinsn
.slotbuf
[i
]);
11193 /* Check the instruction arguments. Return TRUE on failure. */
11196 tinsn_check_arguments (const TInsn
*insn
)
11198 xtensa_isa isa
= xtensa_default_isa
;
11199 xtensa_opcode opcode
= insn
->opcode
;
11201 if (opcode
== XTENSA_UNDEFINED
)
11203 as_bad (_("invalid opcode"));
11207 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
11209 as_bad (_("too few operands"));
11213 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
11215 as_bad (_("too many operands"));
11222 /* Load an instruction from its encoded form. */
11225 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
11229 xg_init_vinsn (&vinsn
);
11230 vinsn_from_chars (&vinsn
, f
);
11232 *tinsn
= vinsn
.slots
[slot
];
11233 xg_free_vinsn (&vinsn
);
11238 tinsn_from_insnbuf (TInsn
*tinsn
,
11239 xtensa_insnbuf slotbuf
,
11244 xtensa_isa isa
= xtensa_default_isa
;
11246 /* Find the immed. */
11247 tinsn_init (tinsn
);
11248 tinsn
->insn_type
= ITYPE_INSN
;
11249 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
11250 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
11251 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
11252 for (i
= 0; i
< tinsn
->ntok
; i
++)
11254 set_expr_const (&tinsn
->tok
[i
],
11255 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
11256 tinsn
->opcode
, i
));
11261 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
11264 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
11266 xtensa_opcode opcode
= tinsn
->opcode
;
11269 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
11271 opnum
= get_relaxable_immed (opcode
);
11272 assert (opnum
>= 0);
11273 set_expr_symbol_offset (&tinsn
->tok
[opnum
],
11274 fragP
->tc_frag_data
.slot_symbols
[slot
],
11275 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11281 get_num_stack_text_bytes (IStack
*istack
)
11284 int text_bytes
= 0;
11286 for (i
= 0; i
< istack
->ninsn
; i
++)
11288 TInsn
*tinsn
= &istack
->insn
[i
];
11289 if (tinsn
->insn_type
== ITYPE_INSN
)
11290 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
11297 get_num_stack_literal_bytes (IStack
*istack
)
11302 for (i
= 0; i
< istack
->ninsn
; i
++)
11304 TInsn
*tinsn
= &istack
->insn
[i
];
11305 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
11312 /* vliw_insn functions. */
11315 xg_init_vinsn (vliw_insn
*v
)
11318 xtensa_isa isa
= xtensa_default_isa
;
11320 xg_clear_vinsn (v
);
11322 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
11323 if (v
->insnbuf
== NULL
)
11324 as_fatal (_("out of memory"));
11326 for (i
= 0; i
< MAX_SLOTS
; i
++)
11328 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
11329 if (v
->slotbuf
[i
] == NULL
)
11330 as_fatal (_("out of memory"));
11336 xg_clear_vinsn (vliw_insn
*v
)
11340 memset (v
, 0, offsetof (vliw_insn
, insnbuf
));
11342 v
->format
= XTENSA_UNDEFINED
;
11344 v
->inside_bundle
= FALSE
;
11346 if (xt_saved_debug_type
!= DEBUG_NONE
)
11347 debug_type
= xt_saved_debug_type
;
11349 for (i
= 0; i
< MAX_SLOTS
; i
++)
11350 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
11355 vinsn_has_specific_opcodes (vliw_insn
*v
)
11359 for (i
= 0; i
< v
->num_slots
; i
++)
11361 if (v
->slots
[i
].is_specific_opcode
)
11369 xg_free_vinsn (vliw_insn
*v
)
11372 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
11373 for (i
= 0; i
< MAX_SLOTS
; i
++)
11374 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
11378 /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic
11379 operands. See also the assumptions listed for tinsn_to_slotbuf. */
11382 vinsn_to_insnbuf (vliw_insn
*vinsn
,
11385 bfd_boolean record_fixup
)
11387 xtensa_isa isa
= xtensa_default_isa
;
11388 xtensa_format fmt
= vinsn
->format
;
11389 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
11391 bfd_boolean has_fixup
= FALSE
;
11393 xtensa_format_encode (isa
, fmt
, insnbuf
);
11395 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
11397 TInsn
*tinsn
= &vinsn
->slots
[slot
];
11398 bfd_boolean tinsn_has_fixup
=
11399 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
11400 vinsn
->slotbuf
[slot
]);
11402 xtensa_format_set_slot (isa
, fmt
, slot
,
11403 insnbuf
, vinsn
->slotbuf
[slot
]);
11404 if (tinsn_has_fixup
)
11407 xtensa_opcode opcode
= tinsn
->opcode
;
11408 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11411 for (i
= 0; i
< noperands
; i
++)
11413 expressionS
* expr
= &tinsn
->tok
[i
];
11414 switch (expr
->X_op
)
11419 if (get_relaxable_immed (opcode
) == i
)
11421 /* Add a fix record for the instruction, except if this
11422 function is being called prior to relaxation, i.e.,
11423 if record_fixup is false, and the instruction might
11424 be relaxed later. */
11426 || tinsn
->is_specific_opcode
11427 || !xg_is_relaxable_insn (tinsn
, 0))
11429 xg_add_opcode_fix (tinsn
, i
, fmt
, slot
, expr
, fragP
,
11430 frag_offset
- fragP
->fr_literal
);
11434 if (expr
->X_op
!= O_symbol
)
11435 as_bad (_("invalid operand"));
11436 tinsn
->symbol
= expr
->X_add_symbol
;
11437 tinsn
->offset
= expr
->X_add_number
;
11441 as_bad (_("symbolic operand not allowed"));
11449 as_bad (_("expression too complex"));
11461 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
11463 static xtensa_insnbuf insnbuf
= NULL
;
11464 static xtensa_insnbuf slotbuf
= NULL
;
11467 xtensa_isa isa
= xtensa_default_isa
;
11471 insnbuf
= xtensa_insnbuf_alloc (isa
);
11472 slotbuf
= xtensa_insnbuf_alloc (isa
);
11475 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) f
, 0);
11476 fmt
= xtensa_format_decode (isa
, insnbuf
);
11477 if (fmt
== XTENSA_UNDEFINED
)
11478 as_fatal (_("cannot decode instruction format"));
11479 vinsn
->format
= fmt
;
11480 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
11482 for (i
= 0; i
< vinsn
->num_slots
; i
++)
11484 TInsn
*tinsn
= &vinsn
->slots
[i
];
11485 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
11486 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
11491 /* Expression utilities. */
11493 /* Return TRUE if the expression is an integer constant. */
11496 expr_is_const (const expressionS
*s
)
11498 return (s
->X_op
== O_constant
);
11502 /* Get the expression constant.
11503 Calling this is illegal if expr_is_const () returns TRUE. */
11506 get_expr_const (const expressionS
*s
)
11508 assert (expr_is_const (s
));
11509 return s
->X_add_number
;
11513 /* Set the expression to a constant value. */
11516 set_expr_const (expressionS
*s
, offsetT val
)
11518 s
->X_op
= O_constant
;
11519 s
->X_add_number
= val
;
11520 s
->X_add_symbol
= NULL
;
11521 s
->X_op_symbol
= NULL
;
11526 expr_is_register (const expressionS
*s
)
11528 return (s
->X_op
== O_register
);
11532 /* Get the expression constant.
11533 Calling this is illegal if expr_is_const () returns TRUE. */
11536 get_expr_register (const expressionS
*s
)
11538 assert (expr_is_register (s
));
11539 return s
->X_add_number
;
11543 /* Set the expression to a symbol + constant offset. */
11546 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
11548 s
->X_op
= O_symbol
;
11549 s
->X_add_symbol
= sym
;
11550 s
->X_op_symbol
= NULL
; /* unused */
11551 s
->X_add_number
= offset
;
11555 /* Return TRUE if the two expressions are equal. */
11558 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
11560 if (s1
->X_op
!= s2
->X_op
)
11562 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
11564 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
11566 if (s1
->X_add_number
!= s2
->X_add_number
)
11573 copy_expr (expressionS
*dst
, const expressionS
*src
)
11575 memcpy (dst
, src
, sizeof (expressionS
));
11579 /* Support for the "--rename-section" option. */
11581 struct rename_section_struct
11585 struct rename_section_struct
*next
;
11588 static struct rename_section_struct
*section_rename
;
11591 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
11592 entries to the section_rename list. Note: Specifying multiple
11593 renamings separated by colons is not documented and is retained only
11594 for backward compatibility. */
11597 build_section_rename (const char *arg
)
11599 struct rename_section_struct
*r
;
11600 char *this_arg
= NULL
;
11601 char *next_arg
= NULL
;
11603 for (this_arg
= xstrdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
11605 char *old_name
, *new_name
;
11609 next_arg
= strchr (this_arg
, ':');
11617 old_name
= this_arg
;
11618 new_name
= strchr (this_arg
, '=');
11620 if (*old_name
== '\0')
11622 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
11625 if (!new_name
|| new_name
[1] == '\0')
11627 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
11634 /* Check for invalid section renaming. */
11635 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11637 if (strcmp (r
->old_name
, old_name
) == 0)
11638 as_bad (_("section %s renamed multiple times"), old_name
);
11639 if (strcmp (r
->new_name
, new_name
) == 0)
11640 as_bad (_("multiple sections remapped to output section %s"),
11645 r
= (struct rename_section_struct
*)
11646 xmalloc (sizeof (struct rename_section_struct
));
11647 r
->old_name
= xstrdup (old_name
);
11648 r
->new_name
= xstrdup (new_name
);
11649 r
->next
= section_rename
;
11650 section_rename
= r
;
11656 xtensa_section_rename (char *name
)
11658 struct rename_section_struct
*r
= section_rename
;
11660 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11662 if (strcmp (r
->old_name
, name
) == 0)
11663 return r
->new_name
;