1 /* tc-z80.c -- Assemble code for the Zilog Z80, Z180, EZ80 and ASCII R800
2 Copyright (C) 2005-2022 Free Software Foundation, Inc.
3 Contributed by Arnold Metselaar <arnold_m@operamail.com>
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 #include "safe-ctype.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
29 /* Exported constants. */
30 const char comment_chars
[] = ";\0";
31 const char line_comment_chars
[] = "#;\0";
32 const char line_separator_chars
[] = "\0";
33 const char EXP_CHARS
[] = "eE\0";
34 const char FLT_CHARS
[] = "RrDdFfSsHh\0";
36 /* For machine specific options. */
37 const char * md_shortopts
= ""; /* None yet. */
41 OPTION_MARCH
= OPTION_MD_BASE
,
55 OPTION_FP_SINGLE_FORMAT
,
56 OPTION_FP_DOUBLE_FORMAT
,
57 OPTION_COMPAT_LL_PREFIX
,
58 OPTION_COMPAT_COLONLESS
,
62 #define INS_Z80 (1 << 0)
63 #define INS_R800 (1 << 1)
64 #define INS_GBZ80 (1 << 2)
65 #define INS_Z180 (1 << 3)
66 #define INS_EZ80 (1 << 4)
67 #define INS_Z80N (1 << 5)
68 #define INS_MARCH_MASK 0xffff
70 #define INS_IDX_HALF (1 << 16)
71 #define INS_IN_F_C (1 << 17)
72 #define INS_OUT_C_0 (1 << 18)
73 #define INS_SLI (1 << 19)
74 #define INS_ROT_II_LD (1 << 20) /* instructions like SLA (ii+d),r; which is: LD r,(ii+d); SLA r; LD (ii+d),r */
75 #define INS_TUNE_MASK 0xffff0000
77 #define INS_NOT_GBZ80 (INS_Z80 | INS_Z180 | INS_R800 | INS_EZ80 | INS_Z80N)
80 #define INS_UNDOC (INS_IDX_HALF | INS_IN_F_C)
81 #define INS_UNPORT (INS_OUT_C_0 | INS_SLI | INS_ROT_II_LD)
83 struct option md_longopts
[] =
85 { "march", required_argument
, NULL
, OPTION_MARCH
},
86 { "z80", no_argument
, NULL
, OPTION_MACH_Z80
},
87 { "r800", no_argument
, NULL
, OPTION_MACH_R800
},
88 { "z180", no_argument
, NULL
, OPTION_MACH_Z180
},
89 { "ez80", no_argument
, NULL
, OPTION_MACH_EZ80_Z80
},
90 { "ez80-adl", no_argument
, NULL
, OPTION_MACH_EZ80_ADL
},
91 { "fp-s", required_argument
, NULL
, OPTION_FP_SINGLE_FORMAT
},
92 { "fp-d", required_argument
, NULL
, OPTION_FP_DOUBLE_FORMAT
},
93 { "strict", no_argument
, NULL
, OPTION_MACH_FUD
},
94 { "full", no_argument
, NULL
, OPTION_MACH_IUP
},
95 { "with-inst", required_argument
, NULL
, OPTION_MACH_INST
},
96 { "Wnins", required_argument
, NULL
, OPTION_MACH_INST
},
97 { "without-inst", required_argument
, NULL
, OPTION_MACH_NO_INST
},
98 { "local-prefix", required_argument
, NULL
, OPTION_COMPAT_LL_PREFIX
},
99 { "colonless", no_argument
, NULL
, OPTION_COMPAT_COLONLESS
},
100 { "sdcc", no_argument
, NULL
, OPTION_COMPAT_SDCC
},
101 { "Fins", required_argument
, NULL
, OPTION_MACH_NO_INST
},
102 { "ignore-undocumented-instructions", no_argument
, NULL
, OPTION_MACH_IUD
},
103 { "Wnud", no_argument
, NULL
, OPTION_MACH_IUD
},
104 { "warn-undocumented-instructions", no_argument
, NULL
, OPTION_MACH_WUD
},
105 { "Wud", no_argument
, NULL
, OPTION_MACH_WUD
},
106 { "forbid-undocumented-instructions", no_argument
, NULL
, OPTION_MACH_FUD
},
107 { "Fud", no_argument
, NULL
, OPTION_MACH_FUD
},
108 { "ignore-unportable-instructions", no_argument
, NULL
, OPTION_MACH_IUP
},
109 { "Wnup", no_argument
, NULL
, OPTION_MACH_IUP
},
110 { "warn-unportable-instructions", no_argument
, NULL
, OPTION_MACH_WUP
},
111 { "Wup", no_argument
, NULL
, OPTION_MACH_WUP
},
112 { "forbid-unportable-instructions", no_argument
, NULL
, OPTION_MACH_FUP
},
113 { "Fup", no_argument
, NULL
, OPTION_MACH_FUP
},
115 { NULL
, no_argument
, NULL
, 0 }
118 size_t md_longopts_size
= sizeof (md_longopts
);
120 extern int coff_flags
;
121 /* Instruction classes that silently assembled. */
122 static int ins_ok
= INS_Z80
| INS_UNDOC
;
123 /* Instruction classes that generate errors. */
124 static int ins_err
= ~(INS_Z80
| INS_UNDOC
);
125 /* eZ80 CPU mode (ADL or Z80) */
126 static int cpu_mode
= 0; /* 0 - Z80, 1 - ADL */
127 /* accept SDCC specific instruction encoding */
128 static int sdcc_compat
= 0;
129 /* accept colonless labels */
130 static int colonless_labels
= 0;
131 /* local label prefix (NULL - default) */
132 static const char *local_label_prefix
= NULL
;
133 /* floating point support */
134 typedef const char *(*str_to_float_t
)(char *litP
, int *sizeP
);
135 static str_to_float_t str_to_float
;
136 static str_to_float_t str_to_double
;
138 /* mode of current instruction */
139 #define INST_MODE_S 0 /* short data mode */
140 #define INST_MODE_IS 0 /* short instruction mode */
141 #define INST_MODE_L 2 /* long data mode */
142 #define INST_MODE_IL 1 /* long instruction mode */
143 #define INST_MODE_FORCED 4 /* CPU mode changed by instruction suffix*/
144 static char inst_mode
;
155 static const struct match_info
158 {"z80", INS_Z80
, 0, 0, "Zilog Z80" },
159 {"ez80", INS_EZ80
, 0, 0, "Zilog eZ80" },
160 {"gbz80", INS_GBZ80
, INS_UNDOC
|INS_UNPORT
, 0, "GameBoy Z80" },
161 {"r800", INS_R800
, INS_UNPORT
, 0, "Ascii R800" },
162 {"z180", INS_Z180
, INS_UNDOC
|INS_UNPORT
, 0, "Zilog Z180" },
163 {"z80n", INS_Z80N
, 0, 0, "Z80 Next" }
166 static const struct match_info
169 {"full", INS_UNDOC
|INS_UNPORT
, 0, 0, "assemble all known instructions" },
170 {"adl", 0, 0, 1, "eZ80 ADL mode by default" },
171 {"xyhl", INS_IDX_HALF
, 0, 0, "instructions with halves of index registers" },
172 {"infc", INS_IN_F_C
, 0, 0, "instruction IN F,(C)" },
173 {"outc0", INS_OUT_C_0
, 0, 0, "instruction OUT (C),0" },
174 {"sli", INS_SLI
, 0, 0, "instruction known as SLI, SLL, or SL1" },
175 {"xdcb", INS_ROT_II_LD
, 0, 0, "instructions like RL (IX+d),R (DD/FD CB dd oo)" }
179 static int signed_overflow (signed long value
, unsigned bitsize
);
180 static int unsigned_overflow (unsigned long value
, unsigned bitsize
);
181 static int is_overflow (long value
, unsigned bitsize
);
184 setup_march (const char *name
, int *ok
, int *err
, int *mode
)
187 size_t len
= strcspn (name
, "+-");
188 for (i
= 0; i
< ARRAY_SIZE (match_cpu_table
); ++i
)
189 if (!strncasecmp (name
, match_cpu_table
[i
].name
, len
)
190 && strlen (match_cpu_table
[i
].name
) == len
)
192 *ok
= match_cpu_table
[i
].ins_ok
;
193 *err
= match_cpu_table
[i
].ins_err
;
194 *mode
= match_cpu_table
[i
].cpu_mode
;
198 if (i
>= ARRAY_SIZE (match_cpu_table
))
199 as_fatal (_("Invalid CPU is specified: %s"), name
);
203 name
= &name
[len
+ 1];
204 len
= strcspn (name
, "+-");
205 for (i
= 0; i
< ARRAY_SIZE (match_ext_table
); ++i
)
206 if (!strncasecmp (name
, match_ext_table
[i
].name
, len
)
207 && strlen (match_ext_table
[i
].name
) == len
)
211 *ok
|= match_ext_table
[i
].ins_ok
;
212 *err
&= ~match_ext_table
[i
].ins_ok
;
213 *mode
|= match_ext_table
[i
].cpu_mode
;
217 *ok
&= ~match_ext_table
[i
].ins_ok
;
218 *err
|= match_ext_table
[i
].ins_ok
;
219 *mode
&= ~match_ext_table
[i
].cpu_mode
;
223 if (i
>= ARRAY_SIZE (match_ext_table
))
224 as_fatal (_("Invalid EXTENSION is specified: %s"), name
);
229 setup_instruction (const char *inst
, int *add
, int *sub
)
232 if (!strcmp (inst
, "idx-reg-halves"))
234 else if (!strcmp (inst
, "sli"))
236 else if (!strcmp (inst
, "op-ii-ld"))
238 else if (!strcmp (inst
, "in-f-c"))
240 else if (!strcmp (inst
, "out-c-0"))
250 str_to_zeda32 (char *litP
, int *sizeP
);
252 str_to_float48 (char *litP
, int *sizeP
);
254 str_to_ieee754_h (char *litP
, int *sizeP
);
256 str_to_ieee754_s (char *litP
, int *sizeP
);
258 str_to_ieee754_d (char *litP
, int *sizeP
);
260 static str_to_float_t
261 get_str_to_float (const char *arg
)
263 if (strcasecmp (arg
, "zeda32") == 0)
264 return str_to_zeda32
;
266 if (strcasecmp (arg
, "math48") == 0)
267 return str_to_float48
;
269 if (strcasecmp (arg
, "half") != 0)
270 return str_to_ieee754_h
;
272 if (strcasecmp (arg
, "single") != 0)
273 return str_to_ieee754_s
;
275 if (strcasecmp (arg
, "double") != 0)
276 return str_to_ieee754_d
;
278 if (strcasecmp (arg
, "ieee754") == 0)
279 as_fatal (_("invalid floating point numbers type `%s'"), arg
);
284 setup_instruction_list (const char *list
, int *add
, int *sub
)
291 for (b
= list
; *b
!= '\0';)
298 if (sz
== 0 || sz
>= (int)sizeof (buf
))
300 as_bad (_("invalid INST in command line: %s"), b
);
305 if (setup_instruction (buf
, add
, sub
))
309 as_bad (_("invalid INST in command line: %s"), buf
);
320 md_parse_option (int c
, const char* arg
)
327 setup_march (arg
, & ins_ok
, & ins_err
, & cpu_mode
);
329 case OPTION_MACH_Z80
:
330 setup_march ("z80", & ins_ok
, & ins_err
, & cpu_mode
);
332 case OPTION_MACH_R800
:
333 setup_march ("r800", & ins_ok
, & ins_err
, & cpu_mode
);
335 case OPTION_MACH_Z180
:
336 setup_march ("z180", & ins_ok
, & ins_err
, & cpu_mode
);
338 case OPTION_MACH_EZ80_Z80
:
339 setup_march ("ez80", & ins_ok
, & ins_err
, & cpu_mode
);
341 case OPTION_MACH_EZ80_ADL
:
342 setup_march ("ez80+adl", & ins_ok
, & ins_err
, & cpu_mode
);
344 case OPTION_FP_SINGLE_FORMAT
:
345 str_to_float
= get_str_to_float (arg
);
347 case OPTION_FP_DOUBLE_FORMAT
:
348 str_to_double
= get_str_to_float (arg
);
350 case OPTION_MACH_INST
:
351 if ((ins_ok
& INS_GBZ80
) == 0)
352 return setup_instruction_list (arg
, & ins_ok
, & ins_err
);
354 case OPTION_MACH_NO_INST
:
355 if ((ins_ok
& INS_GBZ80
) == 0)
356 return setup_instruction_list (arg
, & ins_err
, & ins_ok
);
358 case OPTION_MACH_WUD
:
359 case OPTION_MACH_IUD
:
360 if ((ins_ok
& INS_GBZ80
) == 0)
363 ins_err
&= ~INS_UNDOC
;
366 case OPTION_MACH_WUP
:
367 case OPTION_MACH_IUP
:
368 if ((ins_ok
& INS_GBZ80
) == 0)
370 ins_ok
|= INS_UNDOC
| INS_UNPORT
;
371 ins_err
&= ~(INS_UNDOC
| INS_UNPORT
);
374 case OPTION_MACH_FUD
:
375 if ((ins_ok
& (INS_R800
| INS_GBZ80
)) == 0)
377 ins_ok
&= (INS_UNDOC
| INS_UNPORT
);
378 ins_err
|= INS_UNDOC
| INS_UNPORT
;
381 case OPTION_MACH_FUP
:
382 ins_ok
&= ~INS_UNPORT
;
383 ins_err
|= INS_UNPORT
;
385 case OPTION_COMPAT_LL_PREFIX
:
386 local_label_prefix
= (arg
&& *arg
) ? arg
: NULL
;
388 case OPTION_COMPAT_SDCC
:
391 case OPTION_COMPAT_COLONLESS
:
392 colonless_labels
= 1;
400 md_show_usage (FILE * f
)
404 CPU model options:\n\
405 -march=CPU[+EXT...][-EXT...]\n\
406 \t\t\t generate code for CPU, where CPU is one of:\n"));
407 for (i
= 0; i
< ARRAY_SIZE(match_cpu_table
); ++i
)
408 fprintf (f
, " %-8s\t\t %s\n", match_cpu_table
[i
].name
, match_cpu_table
[i
].comment
);
409 fprintf (f
, _("And EXT is combination (+EXT - add, -EXT - remove) of:\n"));
410 for (i
= 0; i
< ARRAY_SIZE(match_ext_table
); ++i
)
411 fprintf (f
, " %-8s\t\t %s\n", match_ext_table
[i
].name
, match_ext_table
[i
].comment
);
413 Compatibility options:\n\
414 -local-prefix=TEXT\t treat labels prefixed by TEXT as local\n\
415 -colonless\t\t permit colonless labels\n\
416 -sdcc\t\t\t accept SDCC specific instruction syntax\n\
417 -fp-s=FORMAT\t\t set single precision FP numbers format\n\
418 -fp-d=FORMAT\t\t set double precision FP numbers format\n\
419 Where FORMAT one of:\n\
420 ieee754\t\t IEEE754 compatible (depends on directive)\n\
421 half\t\t\t IEEE754 half precision (16 bit)\n\
422 single\t\t IEEE754 single precision (32 bit)\n\
423 double\t\t IEEE754 double precision (64 bit)\n\
424 zeda32\t\t Zeda z80float library 32 bit format\n\
425 math48\t\t 48 bit format from Math48 library\n\
427 Default: -march=z80+xyhl+infc\n"));
430 static symbolS
* zero
;
438 #define R_STACKABLE (0x80)
439 #define R_ARITH (0x40)
442 #define R_INDEX (R_IX | R_IY)
451 #define REG_F (6 | 8)
456 #define REG_AF (3 | R_STACKABLE)
457 #define REG_BC (0 | R_STACKABLE | R_ARITH)
458 #define REG_DE (1 | R_STACKABLE | R_ARITH)
459 #define REG_HL (2 | R_STACKABLE | R_ARITH)
460 #define REG_IX (REG_HL | R_IX)
461 #define REG_IY (REG_HL | R_IY)
462 #define REG_SP (3 | R_ARITH)
464 static const struct reg_entry regtable
[] =
466 {"a", REG_A
, INS_ALL
},
467 {"af", REG_AF
, INS_ALL
},
468 {"b", REG_B
, INS_ALL
},
469 {"bc", REG_BC
, INS_ALL
},
470 {"c", REG_C
, INS_ALL
},
471 {"d", REG_D
, INS_ALL
},
472 {"de", REG_DE
, INS_ALL
},
473 {"e", REG_E
, INS_ALL
},
474 {"f", REG_F
, INS_IN_F_C
| INS_Z80N
| INS_R800
},
475 {"h", REG_H
, INS_ALL
},
476 {"hl", REG_HL
, INS_ALL
},
477 {"i", REG_I
, INS_NOT_GBZ80
},
478 {"ix", REG_IX
, INS_NOT_GBZ80
},
479 {"ixh", REG_H
| R_IX
, INS_IDX_HALF
| INS_EZ80
| INS_R800
| INS_Z80N
},
480 {"ixl", REG_L
| R_IX
, INS_IDX_HALF
| INS_EZ80
| INS_R800
| INS_Z80N
},
481 {"iy", REG_IY
, INS_NOT_GBZ80
},
482 {"iyh", REG_H
| R_IY
, INS_IDX_HALF
| INS_EZ80
| INS_R800
| INS_Z80N
},
483 {"iyl", REG_L
| R_IY
, INS_IDX_HALF
| INS_EZ80
| INS_R800
| INS_Z80N
},
484 {"l", REG_L
, INS_ALL
},
485 {"mb", REG_MB
, INS_EZ80
},
486 {"r", REG_R
, INS_NOT_GBZ80
},
487 {"sp", REG_SP
, INS_ALL
},
490 #define BUFLEN 8 /* Large enough for any keyword. */
495 expressionS nul
, reg
;
497 unsigned int i
, j
, k
;
500 memset (®
, 0, sizeof (reg
));
501 memset (&nul
, 0, sizeof (nul
));
503 if (ins_ok
& INS_EZ80
) /* if select EZ80 cpu then */
504 listing_lhs_width
= 6; /* use 6 bytes per line in the listing */
506 reg
.X_op
= O_register
;
508 reg
.X_add_symbol
= reg
.X_op_symbol
= 0;
509 for ( i
= 0 ; i
< ARRAY_SIZE ( regtable
) ; ++i
)
511 if (regtable
[i
].isa
&& !(regtable
[i
].isa
& ins_ok
))
513 reg
.X_add_number
= regtable
[i
].number
;
514 k
= strlen ( regtable
[i
].name
);
518 for ( j
= ( 1<<k
) ; j
; --j
)
520 for ( k
= 0 ; regtable
[i
].name
[k
] ; ++k
)
522 buf
[k
] = ( j
& ( 1<<k
) ) ? TOUPPER (regtable
[i
].name
[k
]) : regtable
[i
].name
[k
];
524 symbolS
* psym
= symbol_find_or_make (buf
);
525 S_SET_SEGMENT (psym
, reg_section
);
526 symbol_set_value_expression (psym
, ®
);
530 p
= input_line_pointer
;
531 input_line_pointer
= (char *) "0";
534 input_line_pointer
= p
;
535 zero
= make_expr_symbol (& nul
);
536 /* We do not use relaxation (yet). */
545 switch (ins_ok
& INS_MARCH_MASK
)
548 mach_type
= bfd_mach_z80
;
551 mach_type
= bfd_mach_r800
;
554 mach_type
= bfd_mach_z180
;
557 mach_type
= bfd_mach_gbz80
;
560 mach_type
= cpu_mode
? bfd_mach_ez80_adl
: bfd_mach_ez80_z80
;
563 mach_type
= bfd_mach_z80n
;
568 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach_type
);
571 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
573 z80_elf_final_processing (void)
574 {/* nothing to do, all is done by BFD itself */
577 elf_elfheader (stdoutput)->e_flags = elf_flags;
583 skip_space (const char *s
)
585 while (*s
== ' ' || *s
== '\t')
590 /* A non-zero return-value causes a continue in the
591 function read_a_source_file () in ../read.c. */
593 z80_start_line_hook (void)
598 /* Convert one character constants. */
599 for (p
= input_line_pointer
; *p
&& *p
!= '\n'; ++p
)
604 if (p
[1] != 0 && p
[1] != '\'' && p
[2] == '\'')
606 snprintf (buf
, 4, "%3d", (unsigned char)p
[1]);
614 for (quote
= *p
++; quote
!= *p
&& '\n' != *p
; ++p
)
618 as_bad (_("-- unterminated string"));
619 ignore_rest_of_line ();
623 case '#': /* force to use next expression as immediate value in SDCC */
626 if (ISSPACE(p
[1]) && *skip_space (p
+ 1) == '(')
627 { /* ld a,# (expr)... -> ld a,0+(expr)... */
631 else /* ld a,#(expr)... -> ld a,+(expr); ld a,#expr -> ld a, expr */
632 *p
= (p
[1] == '(') ? '+' : ' ';
636 /* Check for <label>[:] =|([.](EQU|DEFL)) <value>. */
637 if (is_name_beginner (*input_line_pointer
))
640 char c
, *rest
, *line_start
;
643 line_start
= input_line_pointer
;
646 c
= get_symbol_name (&name
);
647 rest
= input_line_pointer
+ 1;
648 if (c
== ':' && *rest
== ':')
650 /* remove second colon if SDCC compatibility enabled */
655 rest
= (char*)skip_space (rest
);
657 len
= (rest
[1] == '=') ? 2 : 1;
662 if (strncasecmp (rest
, "EQU", 3) == 0)
664 else if (strncasecmp (rest
, "DEFL", 4) == 0)
669 if (len
&& (len
<= 2 || !ISALPHA (rest
[len
])))
671 /* Handle assignment here. */
672 if (line_start
[-1] == '\n')
674 bump_line_counters ();
677 input_line_pointer
= rest
+ len
- 1;
678 /* Allow redefining with "DEFL" (len == 4), but not with "EQU". */
681 case 1: /* label = expr */
682 case 4: /* label DEFL expr */
685 case 2: /* label == expr */
686 case 3: /* label EQU expr */
694 /* Restore line and pointer. */
695 (void) restore_line_pointer (c
);
696 input_line_pointer
= line_start
;
703 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
709 md_atof (int type
, char *litP
, int *sizeP
)
718 return str_to_float (litP
, sizeP
);
725 return str_to_double (litP
, sizeP
);
728 return ieee_md_atof (type
, litP
, sizeP
, false);
732 md_section_align (segT seg ATTRIBUTE_UNUSED
, valueT size
)
738 md_pcrel_from (fixS
* fixp
)
740 return fixp
->fx_where
+ fixp
->fx_frag
->fr_address
;
743 typedef const char * (asfunc
)(char, char, const char*);
745 typedef struct _table_t
748 unsigned char prefix
;
749 unsigned char opcode
;
751 unsigned inss
; /*0 - all CPU types or list of supported INS_* */
754 /* Compares the key for structs that start with a char * to the key. */
756 key_cmp (const void * a
, const void * b
)
758 const char *str_a
, *str_b
;
760 str_a
= *((const char**)a
);
761 str_b
= *((const char**)b
);
762 return strcmp (str_a
, str_b
);
766 const char *key
= buf
;
768 /* Prevent an error on a line from also generating
769 a "junk at end of line" error message. */
770 static char err_flag
;
773 error (const char * message
)
778 as_bad ("%s", message
);
785 error (_("illegal operand"));
789 wrong_mach (int ins_type
)
791 if (ins_type
& ins_err
)
794 as_warn (_("undocumented instruction"));
798 check_mach (int ins_type
)
800 if ((ins_type
& ins_ok
) == 0)
801 wrong_mach (ins_type
);
804 /* Check whether an expression is indirect. */
806 is_indir (const char *s
)
812 /* Indirection is indicated with parentheses. */
815 for (p
= s
, depth
= 0; *p
&& *p
!= ','; ++p
)
821 for (quote
= *p
++; quote
!= *p
&& *p
!= '\n'; ++p
)
822 if (*p
== '\\' && p
[1])
832 p
= skip_space (p
+ 1);
838 error (_("mismatched parentheses"));
844 error (_("mismatched parentheses"));
849 /* Check whether a symbol involves a register. */
851 contains_register (symbolS
*sym
)
855 expressionS
* ex
= symbol_get_value_expression (sym
);
864 if (ex
->X_op_symbol
&& contains_register (ex
->X_op_symbol
))
869 if (ex
->X_add_symbol
&& contains_register (ex
->X_add_symbol
))
881 /* Parse general expression, not looking for indexed addressing. */
883 parse_exp_not_indexed (const char *s
, expressionS
*op
)
889 memset (op
, 0, sizeof (*op
));
891 if (sdcc_compat
&& (*p
== '<' || *p
== '>'))
895 case '<': /* LSB request */
898 case '>': /* MSB request */
899 make_shift
= cpu_mode
? 16 : 8;
906 if (make_shift
== -1)
907 indir
= is_indir (p
);
911 if (indir
&& (ins_ok
& INS_GBZ80
))
912 { /* check for instructions like ld a,(hl+), ld (hl-),a */
913 p
= skip_space (p
+1);
914 if (!strncasecmp (p
, "hl", 2))
917 if (*skip_space(p
+1) == ')' && (*p
== '+' || *p
== '-'))
920 op
->X_add_symbol
= NULL
;
921 op
->X_add_number
= (*p
== '+') ? REG_HL
: -REG_HL
;
922 input_line_pointer
= (char*)skip_space(p
+ 1) + 1;
923 return input_line_pointer
;
927 input_line_pointer
= (char*) s
;
932 error (_("missing operand"));
935 error (_("bad expression syntax"));
943 /* replace [op] by [op >> shift] */
945 op
->X_add_symbol
= make_expr_symbol (op
);
946 op
->X_add_number
= 0;
947 op
->X_op
= O_right_shift
;
948 memset (&data
, 0, sizeof (data
));
949 data
.X_op
= O_constant
;
950 data
.X_add_number
= make_shift
;
951 op
->X_op_symbol
= make_expr_symbol (&data
);
953 return input_line_pointer
;
957 unify_indexed (expressionS
*op
)
959 if (O_register
!= symbol_get_value_expression (op
->X_add_symbol
)->X_op
)
962 int rnum
= symbol_get_value_expression (op
->X_add_symbol
)->X_add_number
;
963 if ( ((REG_IX
!= rnum
) && (REG_IY
!= rnum
)) || contains_register (op
->X_op_symbol
))
969 /* Convert subtraction to addition of negative value. */
970 if (O_subtract
== op
->X_op
)
973 memset (&minus
, 0, sizeof (minus
));
974 minus
.X_op
= O_uminus
;
975 minus
.X_add_symbol
= op
->X_op_symbol
;
976 op
->X_op_symbol
= make_expr_symbol (&minus
);
980 /* Clear X_add_number of the expression. */
981 if (op
->X_add_number
!= 0)
984 memset (&add
, 0, sizeof (add
));
986 add
.X_add_number
= op
->X_add_number
;
987 add
.X_add_symbol
= op
->X_op_symbol
;
988 op
->X_add_symbol
= make_expr_symbol (&add
);
991 op
->X_add_symbol
= op
->X_op_symbol
;
993 op
->X_add_number
= rnum
;
998 /* Parse expression, change operator to O_md1 for indexed addressing. */
1000 parse_exp (const char *s
, expressionS
*op
)
1002 const char* res
= parse_exp_not_indexed (s
, op
);
1007 if (unify_indexed (op
) && op
->X_md
)
1011 if (op
->X_md
&& ((REG_IX
== op
->X_add_number
) || (REG_IY
== op
->X_add_number
)))
1013 op
->X_add_symbol
= zero
;
1018 /* parse SDCC syntax where index register offset placed before parentheses */
1019 if (sdcc_compat
&& is_indir (res
))
1023 res
= parse_exp (res
, op
);
1024 if (op
->X_op
!= O_md1
|| op
->X_add_symbol
!= zero
)
1027 op
->X_add_symbol
= make_expr_symbol (&off
);
1036 /* Condition codes, including some synonyms provided by HiTech zas. */
1037 static const struct reg_entry cc_tab
[] =
1039 { "age", 6 << 3, INS_ALL
},
1040 { "alt", 7 << 3, INS_ALL
},
1041 { "c", 3 << 3, INS_ALL
},
1042 { "di", 4 << 3, INS_ALL
},
1043 { "ei", 5 << 3, INS_ALL
},
1044 { "lge", 2 << 3, INS_ALL
},
1045 { "llt", 3 << 3, INS_ALL
},
1046 { "m", 7 << 3, INS_ALL
},
1047 { "nc", 2 << 3, INS_ALL
},
1048 { "nz", 0 << 3, INS_ALL
},
1049 { "p", 6 << 3, INS_ALL
},
1050 { "pe", 5 << 3, INS_ALL
},
1051 { "po", 4 << 3, INS_ALL
},
1052 { "z", 1 << 3, INS_ALL
},
1055 /* Parse condition code. */
1057 parse_cc (const char *s
, char * op
)
1061 struct reg_entry
* cc_p
;
1063 for (i
= 0; i
< BUFLEN
; ++i
)
1065 if (!ISALPHA (s
[i
])) /* Condition codes consist of letters only. */
1067 buf
[i
] = TOLOWER (s
[i
]);
1071 && ((s
[i
] == 0) || (s
[i
] == ',')))
1074 cc_p
= bsearch (&key
, cc_tab
, ARRAY_SIZE (cc_tab
),
1075 sizeof (cc_tab
[0]), key_cmp
);
1092 emit_insn (char prefix
, char opcode
, const char * args
)
1107 void z80_cons_fix_new (fragS
*frag_p
, int offset
, int nbytes
, expressionS
*exp
)
1109 bfd_reloc_code_real_type r
[4] =
1117 if (nbytes
< 1 || nbytes
> 4)
1119 as_bad (_("unsupported BFD relocation size %u"), nbytes
);
1123 fix_new_exp (frag_p
, offset
, nbytes
, exp
, 0, r
[nbytes
-1]);
1128 emit_data_val (expressionS
* val
, int size
)
1131 bfd_reloc_code_real_type r_type
;
1133 p
= frag_more (size
);
1134 if (val
->X_op
== O_constant
)
1139 Check for overflow, but ignore values that were generated by bit
1140 manipulation operators (eg ~0xe6 and -7). This does mean that
1141 manipluated overlarge values will not be reported (eg ~0x1234),
1142 but it does help to maintain compatibility with earlier versions
1143 of the assembler. */
1144 if (! val
->X_extrabit
1145 && is_overflow (val
->X_add_number
, size
*8))
1146 as_warn ( _("%d-bit overflow (%+ld)"), size
*8, val
->X_add_number
);
1147 for (i
= 0; i
< size
; ++i
)
1148 p
[i
] = (char)(val
->X_add_number
>> (i
*8));
1154 case 1: r_type
= BFD_RELOC_8
; break;
1155 case 2: r_type
= BFD_RELOC_16
; break;
1156 case 3: r_type
= BFD_RELOC_24
; break;
1157 case 4: r_type
= BFD_RELOC_32
; break;
1158 case 8: r_type
= BFD_RELOC_64
; break;
1160 as_fatal (_("invalid data size %d"), size
);
1163 if ( (val
->X_op
== O_register
)
1164 || (val
->X_op
== O_md1
)
1165 || contains_register (val
->X_add_symbol
)
1166 || contains_register (val
->X_op_symbol
))
1169 if (size
<= 2 && val
->X_op_symbol
)
1171 bool simplify
= true;
1172 int shift
= symbol_get_value_expression (val
->X_op_symbol
)->X_add_number
;
1173 if (val
->X_op
== O_bit_and
&& shift
== (1 << (size
*8))-1)
1175 else if (val
->X_op
!= O_right_shift
)
1182 case 0: r_type
= BFD_RELOC_Z80_BYTE0
; break;
1183 case 8: r_type
= BFD_RELOC_Z80_BYTE1
; break;
1184 case 16: r_type
= BFD_RELOC_Z80_BYTE2
; break;
1185 case 24: r_type
= BFD_RELOC_Z80_BYTE3
; break;
1186 default: simplify
= false;
1189 else /* if (size == 2) */
1193 case 0: r_type
= BFD_RELOC_Z80_WORD0
; break;
1194 case 16: r_type
= BFD_RELOC_Z80_WORD1
; break;
1196 case 24: /* add two byte fixups */
1197 val
->X_op
= O_symbol
;
1198 val
->X_op_symbol
= NULL
;
1199 val
->X_add_number
= 0;
1202 fix_new_exp (frag_now
, p
++ - frag_now
->fr_literal
, 1, val
, false,
1203 BFD_RELOC_Z80_BYTE1
);
1204 /* prepare to next byte */
1205 r_type
= BFD_RELOC_Z80_BYTE2
;
1208 r_type
= BFD_RELOC_Z80_BYTE3
; /* high byte will be 0 */
1212 default: simplify
= false;
1218 val
->X_op
= O_symbol
;
1219 val
->X_op_symbol
= NULL
;
1220 val
->X_add_number
= 0;
1224 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
, val
, false, r_type
);
1228 emit_byte (expressionS
* val
, bfd_reloc_code_real_type r_type
)
1232 if (r_type
== BFD_RELOC_8
)
1234 emit_data_val (val
, 1);
1238 *p
= val
->X_add_number
;
1239 if (contains_register (val
->X_add_symbol
) || contains_register (val
->X_op_symbol
))
1243 else if ((r_type
== BFD_RELOC_8_PCREL
) && (val
->X_op
== O_constant
))
1245 as_bad (_("cannot make a relative jump to an absolute location"));
1247 else if (val
->X_op
== O_constant
)
1249 if ((val
->X_add_number
< -128) || (val
->X_add_number
>= 128))
1251 if (r_type
== BFD_RELOC_Z80_DISP8
)
1252 as_bad (_("index overflow (%+ld)"), val
->X_add_number
);
1254 as_bad (_("offset overflow (%+ld)"), val
->X_add_number
);
1259 /* For symbols only, constants are stored at begin of function. */
1260 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 1, val
,
1261 r_type
== BFD_RELOC_8_PCREL
, r_type
);
1266 emit_word (expressionS
* val
)
1268 emit_data_val (val
, (inst_mode
& INST_MODE_IL
) ? 3 : 2);
1272 emit_mx (char prefix
, char opcode
, int shift
, expressionS
* arg
)
1273 /* The operand m may be r, (hl), (ix+d), (iy+d),
1274 if 0 == prefix m may also be ixl, ixh, iyl, iyh. */
1279 rnum
= arg
->X_add_number
;
1295 if ((prefix
== 0) && (rnum
& R_INDEX
))
1297 prefix
= (rnum
& R_IX
) ? 0xDD : 0xFD;
1298 if (!(ins_ok
& (INS_EZ80
|INS_R800
|INS_Z80N
)))
1299 check_mach (INS_IDX_HALF
);
1308 q
= frag_more (prefix
? 2 : 1);
1311 * q
++ = opcode
+ (rnum
<< shift
);
1314 if (ins_ok
& INS_GBZ80
)
1320 *q
++ = (rnum
& R_IX
) ? 0xDD : 0xFD;
1321 *q
= (prefix
) ? prefix
: (opcode
+ (6 << shift
));
1323 expressionS offset
= *arg
;
1324 offset
.X_op
= O_symbol
;
1325 offset
.X_add_number
= 0;
1326 emit_byte (&offset
, BFD_RELOC_Z80_DISP8
);
1331 *q
= opcode
+(6<<shift
);
1339 /* The operand m may be r, (hl), (ix+d), (iy+d),
1340 if 0 = prefix m may also be ixl, ixh, iyl, iyh. */
1342 emit_m (char prefix
, char opcode
, const char *args
)
1347 p
= parse_exp (args
, &arg_m
);
1352 emit_mx (prefix
, opcode
, 0, &arg_m
);
1360 /* The operand m may be as above or one of the undocumented
1361 combinations (ix+d),r and (iy+d),r (if unportable instructions
1365 emit_mr (char prefix
, char opcode
, const char *args
)
1367 expressionS arg_m
, arg_r
;
1370 p
= parse_exp (args
, & arg_m
);
1377 p
= parse_exp (p
+ 1, & arg_r
);
1379 if ((arg_r
.X_md
== 0)
1380 && (arg_r
.X_op
== O_register
)
1381 && (arg_r
.X_add_number
< 8))
1382 opcode
+= arg_r
.X_add_number
- 6; /* Emit_mx () will add 6. */
1388 if (!(ins_ok
& INS_Z80N
))
1389 check_mach (INS_ROT_II_LD
);
1393 emit_mx (prefix
, opcode
, 0, & arg_m
);
1402 emit_sx (char prefix
, char opcode
, expressionS
* arg_p
)
1406 switch (arg_p
->X_op
)
1410 emit_mx (prefix
, opcode
, 0, arg_p
);
1417 q
= frag_more (prefix
? 2 : 1);
1421 emit_byte (arg_p
, BFD_RELOC_8
);
1426 /* The operand s may be r, (hl), (ix+d), (iy+d), n. */
1428 emit_s (char prefix
, char opcode
, const char *args
)
1433 p
= parse_exp (args
, & arg_s
);
1434 if (*p
== ',' && arg_s
.X_md
== 0 && arg_s
.X_op
== O_register
&& arg_s
.X_add_number
== REG_A
)
1435 { /* possible instruction in generic format op A,x */
1436 if (!(ins_ok
& INS_EZ80
) && !sdcc_compat
)
1439 p
= parse_exp (p
, & arg_s
);
1441 emit_sx (prefix
, opcode
, & arg_s
);
1446 emit_sub (char prefix
, char opcode
, const char *args
)
1451 if (!(ins_ok
& INS_GBZ80
))
1452 return emit_s (prefix
, opcode
, args
);
1453 p
= parse_exp (args
, & arg_s
);
1456 error (_("bad instruction syntax"));
1460 if (arg_s
.X_md
!= 0 || arg_s
.X_op
!= O_register
|| arg_s
.X_add_number
!= REG_A
)
1463 p
= parse_exp (p
, & arg_s
);
1465 emit_sx (prefix
, opcode
, & arg_s
);
1470 emit_swap (char prefix
, char opcode
, const char *args
)
1476 if (!(ins_ok
& INS_Z80N
))
1477 return emit_mr (prefix
, opcode
, args
);
1479 /* check for alias swap a for swapnib of Z80N */
1480 p
= parse_exp (args
, ®
);
1481 if (reg
.X_md
!= 0 || reg
.X_op
!= O_register
|| reg
.X_add_number
!= REG_A
)
1491 emit_call (char prefix ATTRIBUTE_UNUSED
, char opcode
, const char * args
)
1494 const char *p
; char *q
;
1496 p
= parse_exp_not_indexed (args
, &addr
);
1508 /* Operand may be rr, r, (hl), (ix+d), (iy+d). */
1510 emit_incdec (char prefix
, char opcode
, const char * args
)
1512 expressionS operand
;
1514 const char *p
; char *q
;
1516 p
= parse_exp (args
, &operand
);
1517 rnum
= operand
.X_add_number
;
1518 if ((! operand
.X_md
)
1519 && (operand
.X_op
== O_register
)
1522 q
= frag_more ((rnum
& R_INDEX
) ? 2 : 1);
1524 *q
++ = (rnum
& R_IX
) ? 0xDD : 0xFD;
1525 *q
= prefix
+ ((rnum
& 3) << 4);
1529 if ((operand
.X_op
== O_md1
) || (operand
.X_op
== O_register
))
1530 emit_mx (0, opcode
, 3, & operand
);
1538 emit_jr (char prefix ATTRIBUTE_UNUSED
, char opcode
, const char * args
)
1544 p
= parse_exp_not_indexed (args
, &addr
);
1551 addr
.X_add_number
--; /* pcrel computes after offset code */
1552 emit_byte (&addr
, BFD_RELOC_8_PCREL
);
1558 emit_jp (char prefix
, char opcode
, const char * args
)
1565 p
= parse_exp_not_indexed (args
, & addr
);
1568 rnum
= addr
.X_add_number
;
1569 if ((O_register
== addr
.X_op
) && (REG_HL
== (rnum
& ~R_INDEX
)))
1571 q
= frag_more ((rnum
& R_INDEX
) ? 2 : 1);
1573 *q
++ = (rnum
& R_IX
) ? 0xDD : 0xFD;
1576 else if (addr
.X_op
== O_register
&& rnum
== REG_C
&& (ins_ok
& INS_Z80N
))
1595 emit_im (char prefix
, char opcode
, const char * args
)
1601 p
= parse_exp (args
, & mode
);
1602 if (mode
.X_md
|| (mode
.X_op
!= O_constant
))
1605 switch (mode
.X_add_number
)
1609 ++mode
.X_add_number
;
1614 *q
= opcode
+ 8*mode
.X_add_number
;
1623 emit_pop (char prefix ATTRIBUTE_UNUSED
, char opcode
, const char * args
)
1629 p
= parse_exp (args
, & regp
);
1631 && (regp
.X_op
== O_register
)
1632 && (regp
.X_add_number
& R_STACKABLE
))
1636 rnum
= regp
.X_add_number
;
1640 *q
++ = (rnum
&R_IX
)?0xDD:0xFD;
1644 *q
= opcode
+ ((rnum
& 3) << 4);
1653 emit_push (char prefix
, char opcode
, const char * args
)
1659 p
= parse_exp (args
, & arg
);
1660 if (arg
.X_op
== O_register
)
1661 return emit_pop (prefix
, opcode
, args
);
1663 if (arg
.X_md
|| arg
.X_op
== O_md1
|| !(ins_ok
& INS_Z80N
))
1671 fix_new_exp (frag_now
, q
- frag_now
->fr_literal
, 2, &arg
, false,
1672 BFD_RELOC_Z80_16_BE
);
1678 emit_retcc (char prefix ATTRIBUTE_UNUSED
, char opcode
, const char * args
)
1683 p
= parse_cc (args
, &cc
);
1689 return p
? p
: args
;
1693 emit_adc (char prefix
, char opcode
, const char * args
)
1700 p
= parse_exp (args
, &term
);
1703 error (_("bad instruction syntax"));
1707 if ((term
.X_md
) || (term
.X_op
!= O_register
))
1710 switch (term
.X_add_number
)
1713 p
= emit_s (0, prefix
, p
);
1716 p
= parse_exp (p
, &term
);
1717 if ((!term
.X_md
) && (term
.X_op
== O_register
))
1719 rnum
= term
.X_add_number
;
1720 if (R_ARITH
== (rnum
& (R_ARITH
| R_INDEX
)))
1724 *q
= opcode
+ ((rnum
& 3) << 4);
1736 emit_add (char prefix
, char opcode
, const char * args
)
1743 p
= parse_exp (args
, &term
);
1746 error (_("bad instruction syntax"));
1750 if ((term
.X_md
) || (term
.X_op
!= O_register
))
1753 switch (term
.X_add_number
)
1756 p
= emit_s (0, prefix
, p
);
1759 p
= parse_exp (p
, &term
);
1760 if (!(ins_ok
& INS_GBZ80
) || term
.X_md
|| term
.X_op
== O_register
)
1764 emit_byte (&term
, BFD_RELOC_Z80_DISP8
);
1768 if (!(ins_ok
& INS_Z80N
))
1777 lhs
= term
.X_add_number
;
1778 p
= parse_exp (p
, &term
);
1779 rhs
= term
.X_add_number
;
1780 if (term
.X_md
!= 0 || term
.X_op
== O_md1
)
1782 else if ((term
.X_op
== O_register
) && (rhs
& R_ARITH
) && (rhs
== lhs
|| (rhs
& ~R_INDEX
) != REG_HL
))
1786 q
= frag_more ((lhs
& R_INDEX
) ? 2 : 1);
1788 *q
++ = (lhs
& R_IX
) ? 0xDD : 0xFD;
1789 *q
= opcode
+ ((rhs
& 3) << 4);
1793 else if (!(lhs
& R_INDEX
) && (ins_ok
& INS_Z80N
))
1795 if (term
.X_op
== O_register
&& rhs
== REG_A
)
1796 { /* ADD BC/DE/HL,A */
1799 *q
= 0x33 - (lhs
& 3);
1802 else if (term
.X_op
!= O_register
&& term
.X_op
!= O_md1
)
1803 { /* ADD BC/DE/HL,nn */
1806 *q
= 0x36 - (lhs
& 3);
1819 emit_bit (char prefix
, char opcode
, const char * args
)
1825 p
= parse_exp (args
, &b
);
1827 error (_("bad instruction syntax"));
1829 bn
= b
.X_add_number
;
1831 && (b
.X_op
== O_constant
)
1836 /* Bit : no optional third operand. */
1837 p
= emit_m (prefix
, opcode
+ (bn
<< 3), p
);
1839 /* Set, res : resulting byte can be copied to register. */
1840 p
= emit_mr (prefix
, opcode
+ (bn
<< 3), p
);
1847 /* BSLA DE,B; BSRA DE,B; BSRL DE,B; BSRF DE,B; BRLC DE,B (Z80N only) */
1849 emit_bshft (char prefix
, char opcode
, const char * args
)
1855 p
= parse_exp (args
, & r1
);
1857 error (_("bad instruction syntax"));
1858 p
= parse_exp (p
, & r2
);
1859 if (r1
.X_md
|| r1
.X_op
!= O_register
|| r1
.X_add_number
!= REG_DE
||
1860 r2
.X_md
|| r2
.X_op
!= O_register
|| r2
.X_add_number
!= REG_B
)
1869 emit_jpcc (char prefix
, char opcode
, const char * args
)
1874 p
= parse_cc (args
, & cc
);
1875 if (p
&& *p
++ == ',')
1876 p
= emit_call (0, opcode
+ cc
, p
);
1878 p
= (prefix
== (char)0xC3)
1879 ? emit_jp (0xE9, prefix
, args
)
1880 : emit_call (0, prefix
, args
);
1885 emit_jrcc (char prefix
, char opcode
, const char * args
)
1890 p
= parse_cc (args
, &cc
);
1891 if (p
&& *p
++ == ',')
1894 error (_("condition code invalid for jr"));
1896 p
= emit_jr (0, opcode
+ cc
, p
);
1899 p
= emit_jr (0, prefix
, args
);
1905 emit_ex (char prefix_in ATTRIBUTE_UNUSED
,
1906 char opcode_in ATTRIBUTE_UNUSED
, const char * args
)
1910 char prefix
, opcode
;
1912 p
= parse_exp_not_indexed (args
, &op
);
1916 error (_("bad instruction syntax"));
1920 prefix
= opcode
= 0;
1921 if (op
.X_op
== O_register
)
1922 switch (op
.X_add_number
| (op
.X_md
? 0x8000 : 0))
1925 if (TOLOWER (*p
++) == 'a' && TOLOWER (*p
++) == 'f')
1927 /* The scrubber changes '\'' to '`' in this context. */
1934 if (TOLOWER (*p
++) == 'h' && TOLOWER (*p
++) == 'l')
1938 p
= parse_exp (p
, & op
);
1939 if (op
.X_op
== O_register
1941 && (op
.X_add_number
& ~R_INDEX
) == REG_HL
)
1944 if (R_INDEX
& op
.X_add_number
)
1945 prefix
= (R_IX
& op
.X_add_number
) ? 0xDD : 0xFD;
1950 emit_insn (prefix
, opcode
, p
);
1958 emit_in (char prefix ATTRIBUTE_UNUSED
, char opcode ATTRIBUTE_UNUSED
,
1961 expressionS reg
, port
;
1965 p
= parse_exp (args
, ®
);
1966 if (reg
.X_md
&& reg
.X_op
== O_register
&& reg
.X_add_number
== REG_C
)
1967 { /* permit instruction in (c) as alias for in f,(c) */
1970 reg
.X_add_number
= REG_F
;
1976 error (_("bad instruction syntax"));
1979 p
= parse_exp (p
, &port
);
1982 && reg
.X_op
== O_register
1983 && (reg
.X_add_number
<= 7 || reg
.X_add_number
== REG_F
)
1986 if (port
.X_op
!= O_md1
&& port
.X_op
!= O_register
)
1988 if (REG_A
== reg
.X_add_number
)
1992 emit_byte (&port
, BFD_RELOC_8
);
1999 if (port
.X_add_number
== REG_C
|| port
.X_add_number
== REG_BC
)
2001 if (port
.X_add_number
== REG_BC
&& !(ins_ok
& INS_EZ80
))
2003 else if (reg
.X_add_number
== REG_F
&& !(ins_ok
& (INS_R800
|INS_Z80N
)))
2004 check_mach (INS_IN_F_C
);
2007 *q
= 0x40|((reg
.X_add_number
&7)<<3);
2019 emit_in0 (char prefix ATTRIBUTE_UNUSED
, char opcode ATTRIBUTE_UNUSED
,
2022 expressionS reg
, port
;
2026 p
= parse_exp (args
, ®
);
2029 error (_("bad instruction syntax"));
2033 p
= parse_exp (p
, &port
);
2035 && reg
.X_op
== O_register
2036 && reg
.X_add_number
<= 7
2038 && port
.X_op
!= O_md1
2039 && port
.X_op
!= O_register
)
2043 *q
= 0x00|(reg
.X_add_number
<< 3);
2044 emit_byte (&port
, BFD_RELOC_8
);
2052 emit_out (char prefix ATTRIBUTE_UNUSED
, char opcode ATTRIBUTE_UNUSED
,
2055 expressionS reg
, port
;
2059 p
= parse_exp (args
, & port
);
2062 error (_("bad instruction syntax"));
2065 p
= parse_exp (p
, ®
);
2067 { ill_op (); return p
; }
2068 /* Allow "out (c), 0" as unportable instruction. */
2069 if (reg
.X_op
== O_constant
&& reg
.X_add_number
== 0)
2071 if (!(ins_ok
& INS_Z80N
))
2072 check_mach (INS_OUT_C_0
);
2073 reg
.X_op
= O_register
;
2074 reg
.X_add_number
= 6;
2077 || reg
.X_op
!= O_register
2078 || reg
.X_add_number
> 7)
2081 if (port
.X_op
!= O_register
&& port
.X_op
!= O_md1
)
2083 if (REG_A
== reg
.X_add_number
)
2087 emit_byte (&port
, BFD_RELOC_8
);
2094 if (REG_C
== port
.X_add_number
|| port
.X_add_number
== REG_BC
)
2096 if (port
.X_add_number
== REG_BC
&& !(ins_ok
& INS_EZ80
))
2100 *q
= 0x41 | (reg
.X_add_number
<< 3);
2109 emit_out0 (char prefix ATTRIBUTE_UNUSED
, char opcode ATTRIBUTE_UNUSED
,
2112 expressionS reg
, port
;
2116 p
= parse_exp (args
, & port
);
2119 error (_("bad instruction syntax"));
2122 p
= parse_exp (p
, ®
);
2124 && port
.X_op
!= O_register
2125 && port
.X_op
!= O_md1
2127 && reg
.X_op
== O_register
2128 && reg
.X_add_number
<= 7)
2132 *q
= 0x01 | (reg
.X_add_number
<< 3);
2133 emit_byte (&port
, BFD_RELOC_8
);
2141 emit_rst (char prefix ATTRIBUTE_UNUSED
, char opcode
, const char * args
)
2147 p
= parse_exp_not_indexed (args
, &addr
);
2148 if (addr
.X_op
!= O_constant
)
2150 error ("rst needs constant address");
2154 if (addr
.X_add_number
& ~(7 << 3))
2159 *q
= opcode
+ (addr
.X_add_number
& (7 << 3));
2164 /* For 8-bit indirect load to memory instructions like: LD (HL),n or LD (ii+d),n. */
2166 emit_ld_m_n (expressionS
*dst
, expressionS
*src
)
2170 expressionS dst_offset
;
2172 switch (dst
->X_add_number
)
2174 case REG_HL
: prefix
= 0x00; break;
2175 case REG_IX
: prefix
= 0xDD; break;
2176 case REG_IY
: prefix
= 0xFD; break;
2182 q
= frag_more (prefix
? 2 : 1);
2189 dst_offset
.X_op
= O_symbol
;
2190 dst_offset
.X_add_number
= 0;
2191 emit_byte (& dst_offset
, BFD_RELOC_Z80_DISP8
);
2193 emit_byte (src
, BFD_RELOC_8
);
2196 /* For 8-bit load register to memory instructions: LD (<expression>),r. */
2198 emit_ld_m_r (expressionS
*dst
, expressionS
*src
)
2202 expressionS dst_offset
;
2207 if (ins_ok
& INS_GBZ80
)
2208 { /* LD (HL+),A or LD (HL-),A */
2209 if (src
->X_op
!= O_register
|| src
->X_add_number
!= REG_A
)
2211 *frag_more (1) = (dst
->X_add_number
== REG_HL
) ? 0x22 : 0x32;
2215 prefix
= (dst
->X_add_number
== REG_IX
) ? 0xDD : 0xFD;
2218 switch (dst
->X_add_number
)
2220 case REG_BC
: /* LD (BC),A */
2221 case REG_DE
: /* LD (DE),A */
2222 if (src
->X_add_number
== REG_A
)
2225 *q
= 0x02 | ((dst
->X_add_number
& 3) << 4);
2231 case REG_HL
: /* LD (HL),r or LD (ii+d),r */
2232 if (src
->X_add_number
<= 7)
2234 q
= frag_more (prefix
? 2 : 1);
2237 *q
= 0x70 | src
->X_add_number
;
2241 dst_offset
.X_op
= O_symbol
;
2242 dst_offset
.X_add_number
= 0;
2243 emit_byte (& dst_offset
, BFD_RELOC_Z80_DISP8
);
2251 default: /* LD (nn),A */
2252 if (src
->X_add_number
== REG_A
)
2255 *q
= (ins_ok
& INS_GBZ80
) ? 0xEA : 0x32;
2264 /* For 16-bit load register to memory instructions: LD (<expression>),rr. */
2266 emit_ld_m_rr (expressionS
*dst
, expressionS
*src
)
2271 expressionS dst_offset
;
2275 case O_md1
: /* eZ80 instructions LD (ii+d),rr */
2276 case O_register
: /* eZ80 instructions LD (HL),rr */
2277 if (!(ins_ok
& INS_EZ80
)) /* 16-bit indirect load group is supported by eZ80 only */
2279 switch (dst
->X_add_number
)
2281 case REG_IX
: prefix
= 0xDD; break;
2282 case REG_IY
: prefix
= 0xFD; break;
2283 case REG_HL
: prefix
= 0xED; break;
2287 switch (src
->X_add_number
)
2289 case REG_BC
: opcode
= 0x0F; break;
2290 case REG_DE
: opcode
= 0x1F; break;
2291 case REG_HL
: opcode
= 0x2F; break;
2292 case REG_IX
: opcode
= (prefix
!= 0xFD) ? 0x3F : 0x3E; break;
2293 case REG_IY
: opcode
= (prefix
!= 0xFD) ? 0x3E : 0x3F; break;
2297 q
= frag_more (prefix
? 2 : 1);
2300 if (prefix
== 0xFD || prefix
== 0xDD)
2303 dst_offset
.X_op
= O_symbol
;
2304 dst_offset
.X_add_number
= 0;
2305 emit_byte (& dst_offset
, BFD_RELOC_Z80_DISP8
);
2308 default: /* LD (nn),rr */
2309 if (ins_ok
& INS_GBZ80
)
2311 /* GBZ80 supports only LD (nn),SP */
2312 if (src
->X_add_number
== REG_SP
)
2322 switch (src
->X_add_number
)
2324 case REG_BC
: prefix
= 0xED; opcode
= 0x43; break;
2325 case REG_DE
: prefix
= 0xED; opcode
= 0x53; break;
2326 case REG_HL
: prefix
= 0x00; opcode
= 0x22; break;
2327 case REG_IX
: prefix
= 0xDD; opcode
= 0x22; break;
2328 case REG_IY
: prefix
= 0xFD; opcode
= 0x22; break;
2329 case REG_SP
: prefix
= 0xED; opcode
= 0x73; break;
2334 q
= frag_more (prefix
? 2 : 1);
2343 emit_ld_r_m (expressionS
*dst
, expressionS
*src
)
2344 { /* for 8-bit memory load to register: LD r,(xxx) */
2348 expressionS src_offset
;
2350 if (dst
->X_add_number
== REG_A
&& src
->X_op
== O_register
)
2351 { /* LD A,(BC) or LD A,(DE) */
2352 switch (src
->X_add_number
)
2354 case REG_BC
: opcode
= 0x0A; break;
2355 case REG_DE
: opcode
= 0x1A; break;
2369 if (ins_ok
& INS_GBZ80
)
2370 { /* LD A,(HL+) or LD A,(HL-) */
2371 if (dst
->X_op
== O_register
&& dst
->X_add_number
== REG_A
)
2372 *frag_more (1) = (src
->X_add_number
== REG_HL
) ? 0x2A : 0x3A;
2379 if (dst
->X_add_number
> 7)
2381 opcode
= 0x46; /* LD B,(HL) */
2382 switch (src
->X_add_number
)
2384 case REG_HL
: prefix
= 0x00; break;
2385 case REG_IX
: prefix
= 0xDD; break;
2386 case REG_IY
: prefix
= 0xFD; break;
2390 q
= frag_more (prefix
? 2 : 1);
2393 *q
= opcode
| ((dst
->X_add_number
& 7) << 3);
2397 src_offset
.X_op
= O_symbol
;
2398 src_offset
.X_add_number
= 0;
2399 emit_byte (& src_offset
, BFD_RELOC_Z80_DISP8
);
2402 default: /* LD A,(nn) */
2403 if (dst
->X_add_number
== REG_A
)
2406 *q
= (ins_ok
& INS_GBZ80
) ? 0xFA : 0x3A;
2415 emit_ld_r_n (expressionS
*dst
, expressionS
*src
)
2416 { /* for 8-bit immediate value load to register: LD r,n */
2420 switch (dst
->X_add_number
)
2442 q
= frag_more (prefix
? 2 : 1);
2445 if (ins_ok
& INS_GBZ80
)
2447 else if (!(ins_ok
& (INS_EZ80
|INS_R800
|INS_Z80N
)))
2448 check_mach (INS_IDX_HALF
);
2451 *q
= 0x06 | ((dst
->X_add_number
& 7) << 3);
2452 emit_byte (src
, BFD_RELOC_8
);
2456 emit_ld_r_r (expressionS
*dst
, expressionS
*src
)
2457 { /* mostly 8-bit load register from register instructions: LD r,r */
2458 /* there are some exceptions: LD SP,HL/IX/IY; LD I,HL and LD HL,I */
2464 switch (dst
->X_add_number
)
2467 switch (src
->X_add_number
)
2469 case REG_HL
: prefix
= 0x00; break;
2470 case REG_IX
: prefix
= 0xDD; break;
2471 case REG_IY
: prefix
= 0xFD; break;
2478 if (!(ins_ok
& INS_EZ80
))
2480 if (src
->X_add_number
!= REG_I
)
2483 error (_("ADL mode instruction"));
2489 if (src
->X_add_number
== REG_HL
)
2491 if (!(ins_ok
& INS_EZ80
))
2494 error (_("ADL mode instruction"));
2498 else if (src
->X_add_number
== REG_A
)
2507 if (!(ins_ok
& INS_EZ80
) || (src
->X_add_number
!= REG_A
))
2510 error (_("ADL mode instruction"));
2515 if (src
->X_add_number
== REG_A
) /* LD R,A */
2524 if (src
->X_add_number
== REG_I
) /* LD A,I */
2530 else if (src
->X_add_number
== REG_R
) /* LD A,R */
2536 else if (src
->X_add_number
== REG_MB
) /* LD A,MB */
2538 if (!(ins_ok
& INS_EZ80
))
2543 error (_("ADL mode instruction"));
2574 switch (src
->X_add_number
)
2585 ill_op (); /* LD iiH/L,H/L are not permitted */
2589 if (prefix
== 0xFD || dst
->X_add_number
== REG_H
|| dst
->X_add_number
== REG_L
)
2590 ill_op (); /* LD IYL,IXL and LD H,IXH are not permitted */
2596 if (prefix
== 0xDD || dst
->X_add_number
== REG_H
|| dst
->X_add_number
== REG_L
)
2597 ill_op (); /* LD IXH,IYH and LD L,IYL are not permitted */
2604 opcode
= 0x40 + ((dst
->X_add_number
& 7) << 3) + (src
->X_add_number
& 7);
2606 if ((ins_ok
& INS_GBZ80
) && prefix
!= 0)
2608 if (ii_halves
&& !(ins_ok
& (INS_EZ80
|INS_R800
|INS_Z80N
)))
2609 check_mach (INS_IDX_HALF
);
2610 if (prefix
== 0 && (ins_ok
& INS_EZ80
))
2614 case 0x40: /* SIS prefix, in Z80 it is LD B,B */
2615 case 0x49: /* LIS prefix, in Z80 it is LD C,C */
2616 case 0x52: /* SIL prefix, in Z80 it is LD D,D */
2617 case 0x5B: /* LIL prefix, in Z80 it is LD E,E */
2618 as_warn (_("unsupported instruction, assembled as NOP"));
2624 q
= frag_more (prefix
? 2 : 1);
2631 emit_ld_rr_m (expressionS
*dst
, expressionS
*src
)
2632 { /* for 16-bit indirect load from memory to register: LD rr,(xxx) */
2636 expressionS src_offset
;
2638 /* GBZ80 has no support for 16-bit load from memory instructions */
2639 if (ins_ok
& INS_GBZ80
)
2645 case O_md1
: /* LD rr,(ii+d) */
2646 prefix
= (src
->X_add_number
== REG_IX
) ? 0xDD : 0xFD;
2648 case O_register
: /* LD rr,(HL) */
2649 /* currently only EZ80 has support for 16bit indirect memory load instructions */
2650 if (!(ins_ok
& INS_EZ80
))
2652 switch (dst
->X_add_number
)
2654 case REG_BC
: opcode
= 0x07; break;
2655 case REG_DE
: opcode
= 0x17; break;
2656 case REG_HL
: opcode
= 0x27; break;
2657 case REG_IX
: opcode
= (prefix
== 0xED || prefix
== 0xDD) ? 0x37 : 0x31; break;
2658 case REG_IY
: opcode
= (prefix
== 0xED || prefix
== 0xDD) ? 0x31 : 0x37; break;
2668 src_offset
.X_op
= O_symbol
;
2669 src_offset
.X_add_number
= 0;
2670 emit_byte (& src_offset
, BFD_RELOC_Z80_DISP8
);
2673 default: /* LD rr,(nn) */
2674 switch (dst
->X_add_number
)
2676 case REG_BC
: prefix
= 0xED; opcode
= 0x4B; break;
2677 case REG_DE
: prefix
= 0xED; opcode
= 0x5B; break;
2678 case REG_HL
: prefix
= 0x00; opcode
= 0x2A; break;
2679 case REG_SP
: prefix
= 0xED; opcode
= 0x7B; break;
2680 case REG_IX
: prefix
= 0xDD; opcode
= 0x2A; break;
2681 case REG_IY
: prefix
= 0xFD; opcode
= 0x2A; break;
2685 q
= frag_more (prefix
? 2 : 1);
2695 emit_ld_rr_nn (expressionS
*dst
, expressionS
*src
)
2696 { /* mostly load imediate value to multibyte register instructions: LD rr,nn */
2699 int opcode
= 0x21; /* LD HL,nn */
2700 switch (dst
->X_add_number
)
2713 opcode
= 0x01 + ((dst
->X_add_number
& 3) << 4);
2719 if (prefix
&& (ins_ok
& INS_GBZ80
))
2721 q
= frag_more (prefix
? 2 : 1);
2729 emit_ld (char prefix_in ATTRIBUTE_UNUSED
, char opcode_in ATTRIBUTE_UNUSED
,
2732 expressionS dst
, src
;
2735 p
= parse_exp (args
, & dst
);
2737 error (_("bad instruction syntax"));
2738 p
= parse_exp (p
, & src
);
2742 if (src
.X_op
== O_register
)
2744 if (src
.X_add_number
<= 7)
2745 emit_ld_m_r (& dst
, & src
); /* LD (xxx),r */
2747 emit_ld_m_rr (& dst
, & src
); /* LD (xxx),rr */
2750 emit_ld_m_n (& dst
, & src
); /* LD (hl),n or LD (ix/y+r),n */
2752 else if (dst
.X_op
== O_register
)
2756 if (dst
.X_add_number
<= 7)
2757 emit_ld_r_m (& dst
, & src
);
2759 emit_ld_rr_m (& dst
, & src
);
2761 else if (src
.X_op
== O_register
)
2762 emit_ld_r_r (& dst
, & src
);
2763 else if ((dst
.X_add_number
& ~R_INDEX
) <= 7)
2764 emit_ld_r_n (& dst
, & src
);
2766 emit_ld_rr_nn (& dst
, & src
);
2775 emit_lddldi (char prefix
, char opcode
, const char * args
)
2777 expressionS dst
, src
;
2781 if (!(ins_ok
& INS_GBZ80
))
2782 return emit_insn (prefix
, opcode
, args
);
2784 p
= parse_exp (args
, & dst
);
2786 error (_("bad instruction syntax"));
2787 p
= parse_exp (p
, & src
);
2789 if (dst
.X_op
!= O_register
|| src
.X_op
!= O_register
)
2792 /* convert opcode 0xA0 . 0x22, 0xA8 . 0x32 */
2793 opcode
= (opcode
& 0x08) * 2 + 0x22;
2796 && dst
.X_add_number
== REG_HL
2798 && src
.X_add_number
== REG_A
)
2799 opcode
|= 0x00; /* LDx (HL),A */
2800 else if (dst
.X_md
== 0
2801 && dst
.X_add_number
== REG_A
2803 && src
.X_add_number
== REG_HL
)
2804 opcode
|= 0x08; /* LDx A,(HL) */
2814 emit_ldh (char prefix ATTRIBUTE_UNUSED
, char opcode ATTRIBUTE_UNUSED
,
2817 expressionS dst
, src
;
2821 p
= parse_exp (args
, & dst
);
2824 error (_("bad instruction syntax"));
2828 p
= parse_exp (p
, & src
);
2830 && dst
.X_op
== O_register
2831 && dst
.X_add_number
== REG_A
2833 && src
.X_op
!= O_md1
)
2835 if (src
.X_op
!= O_register
)
2839 emit_byte (& src
, BFD_RELOC_8
);
2841 else if (src
.X_add_number
== REG_C
)
2842 *frag_more (1) = 0xF2;
2846 else if (dst
.X_md
!= 0
2847 && dst
.X_op
!= O_md1
2849 && src
.X_op
== O_register
2850 && src
.X_add_number
== REG_A
)
2852 if (dst
.X_op
== O_register
)
2854 if (dst
.X_add_number
== REG_C
)
2866 emit_byte (& dst
, BFD_RELOC_8
);
2876 emit_ldhl (char prefix ATTRIBUTE_UNUSED
, char opcode
, const char * args
)
2878 expressionS dst
, src
;
2881 p
= parse_exp (args
, & dst
);
2884 error (_("bad instruction syntax"));
2888 p
= parse_exp (p
, & src
);
2889 if (dst
.X_md
|| dst
.X_op
!= O_register
|| dst
.X_add_number
!= REG_SP
2890 || src
.X_md
|| src
.X_op
== O_register
|| src
.X_op
== O_md1
)
2894 emit_byte (& src
, BFD_RELOC_Z80_DISP8
);
2899 parse_lea_pea_args (const char * args
, expressionS
*op
)
2902 p
= parse_exp (args
, op
);
2903 if (sdcc_compat
&& *p
== ',' && op
->X_op
== O_register
)
2906 p
= parse_exp (p
+ 1, &off
);
2908 op
->X_add_symbol
= make_expr_symbol (&off
);
2914 emit_lea (char prefix
, char opcode
, const char * args
)
2916 expressionS dst
, src
;
2921 p
= parse_exp (args
, & dst
);
2922 if (dst
.X_md
!= 0 || dst
.X_op
!= O_register
)
2925 rnum
= dst
.X_add_number
;
2931 opcode
= 0x02 | ((rnum
& 0x03) << 4);
2934 opcode
= 0x32; /* lea ix,ix+d has opcode 0x32; lea ix,iy+d has opcode 0x54 */
2937 opcode
= 0x33; /* lea iy,iy+d has opcode 0x33; lea iy,ix+d has opcode 0x55 */
2944 error (_("bad instruction syntax"));
2946 p
= parse_lea_pea_args (p
, & src
);
2947 if (src
.X_md
!= 0 || src
.X_op
!= O_add
/*&& src.X_op != O_register*/)
2950 rnum
= src
.X_add_number
;
2955 case O_register
: /* permit instructions like LEA rr,IX without displacement specified */
2956 src
.X_add_symbol
= zero
;
2965 opcode
= (opcode
== (char)0x33) ? 0x55 : (opcode
|0x00);
2968 opcode
= (opcode
== (char)0x32) ? 0x54 : (opcode
|0x01);
2975 src
.X_op
= O_symbol
;
2976 src
.X_add_number
= 0;
2977 emit_byte (& src
, BFD_RELOC_Z80_DISP8
);
2983 emit_mlt (char prefix
, char opcode
, const char * args
)
2989 p
= parse_exp (args
, & arg
);
2990 if (arg
.X_md
!= 0 || arg
.X_op
!= O_register
|| !(arg
.X_add_number
& R_ARITH
))
2994 if (ins_ok
& INS_Z80N
)
2996 if (arg
.X_add_number
!= REG_DE
)
3004 *q
= opcode
| ((arg
.X_add_number
& 3) << 4);
3010 /* MUL D,E (Z80N only) */
3012 emit_mul (char prefix
, char opcode
, const char * args
)
3018 p
= parse_exp (args
, & r1
);
3020 error (_("bad instruction syntax"));
3021 p
= parse_exp (p
, & r2
);
3023 if (r1
.X_md
!= 0 || r1
.X_op
!= O_register
|| r1
.X_add_number
!= REG_D
||
3024 r2
.X_md
!= 0 || r2
.X_op
!= O_register
|| r2
.X_add_number
!= REG_E
)
3035 emit_nextreg (char prefix
, char opcode ATTRIBUTE_UNUSED
, const char * args
)
3041 p
= parse_exp (args
, & rr
);
3043 error (_("bad instruction syntax"));
3044 p
= parse_exp (p
, & nn
);
3045 if (rr
.X_md
!= 0 || rr
.X_op
== O_register
|| rr
.X_op
== O_md1
||
3046 nn
.X_md
!= 0 || nn
.X_op
== O_md1
)
3050 emit_byte (&rr
, BFD_RELOC_8
);
3051 if (nn
.X_op
== O_register
&& nn
.X_add_number
== REG_A
)
3053 else if (nn
.X_op
!= O_register
)
3056 emit_byte (&nn
, BFD_RELOC_8
);
3064 emit_pea (char prefix
, char opcode
, const char * args
)
3070 p
= parse_lea_pea_args (args
, & arg
);
3072 || (/*arg.X_op != O_register &&*/ arg
.X_op
!= O_add
)
3073 || !(arg
.X_add_number
& R_INDEX
))
3075 /* PEA ii without displacement is mostly typo,
3076 because there is PUSH instruction which is shorter and faster */
3077 /*if (arg.X_op == O_register)
3078 as_warn (_("PEA is used without displacement, use PUSH instead"));*/
3082 *q
= opcode
+ (arg
.X_add_number
== REG_IY
? 1 : 0);
3084 arg
.X_op
= O_symbol
;
3085 arg
.X_add_number
= 0;
3086 emit_byte (& arg
, BFD_RELOC_Z80_DISP8
);
3092 emit_reti (char prefix
, char opcode
, const char * args
)
3094 if (ins_ok
& INS_GBZ80
)
3095 return emit_insn (0x00, 0xD9, args
);
3097 return emit_insn (prefix
, opcode
, args
);
3101 emit_tst (char prefix
, char opcode
, const char *args
)
3108 p
= parse_exp (args
, & arg_s
);
3109 if (*p
== ',' && arg_s
.X_md
== 0 && arg_s
.X_op
== O_register
&& arg_s
.X_add_number
== REG_A
)
3111 if (!(ins_ok
& INS_EZ80
))
3114 p
= parse_exp (p
, & arg_s
);
3117 rnum
= arg_s
.X_add_number
;
3124 rnum
= arg_s
.X_add_number
;
3125 if (arg_s
.X_md
!= 0)
3134 *q
= opcode
| (rnum
<< 3);
3140 if (ins_ok
& INS_Z80N
)
3150 emit_byte (& arg_s
, BFD_RELOC_8
);
3156 emit_insn_n (char prefix
, char opcode
, const char *args
)
3162 p
= parse_exp (args
, & arg
);
3163 if (arg
.X_md
|| arg
.X_op
== O_register
|| arg
.X_op
== O_md1
)
3169 emit_byte (& arg
, BFD_RELOC_8
);
3175 emit_data (int size ATTRIBUTE_UNUSED
)
3182 if (is_it_end_of_statement ())
3184 demand_empty_rest_of_line ();
3187 p
= skip_space (input_line_pointer
);
3191 if (*p
== '\"' || *p
== '\'')
3193 for (quote
= *p
, q
= ++p
, cnt
= 0; *p
&& quote
!= *p
; ++p
, ++cnt
)
3195 u
= frag_more (cnt
);
3198 as_warn (_("unterminated string"));
3200 p
= skip_space (p
+1);
3204 p
= parse_exp (p
, &exp
);
3205 if (exp
.X_op
== O_md1
|| exp
.X_op
== O_register
)
3211 as_warn (_("parentheses ignored"));
3212 emit_byte (&exp
, BFD_RELOC_8
);
3216 while (*p
++ == ',') ;
3217 input_line_pointer
= (char *)(p
-1);
3226 if (is_it_end_of_statement ())
3228 demand_empty_rest_of_line ();
3231 p
= skip_space (input_line_pointer
);
3235 p
= parse_exp (p
, &exp
);
3236 if (exp
.X_op
== O_md1
|| exp
.X_op
== O_register
)
3242 as_warn (_("parentheses ignored"));
3243 emit_data_val (&exp
, size
);
3245 } while (*p
++ == ',') ;
3246 input_line_pointer
= (char *)(p
-1);
3249 /* next functions were commented out because it is difficult to mix
3250 both ADL and Z80 mode instructions within one COFF file:
3251 objdump cannot recognize point of mode switching.
3254 set_cpu_mode (int mode
)
3256 if (ins_ok
& INS_EZ80
)
3259 error (_("CPU mode is unsupported by target"));
3263 assume (int arg ATTRIBUTE_UNUSED
)
3269 input_line_pointer
= (char*)skip_space (input_line_pointer
);
3270 c
= get_symbol_name (& name
);
3271 if (strncasecmp (name
, "ADL", 4) != 0)
3277 restore_line_pointer (c
);
3278 input_line_pointer
= (char*)skip_space (input_line_pointer
);
3279 if (*input_line_pointer
++ != '=')
3281 error (_("assignment expected"));
3284 input_line_pointer
= (char*)skip_space (input_line_pointer
);
3285 n
= get_single_number ();
3291 emit_mulub (char prefix ATTRIBUTE_UNUSED
, char opcode
, const char * args
)
3295 p
= skip_space (args
);
3296 if (TOLOWER (*p
++) != 'a' || *p
++ != ',')
3302 reg
= TOLOWER (*p
++);
3309 check_mach (INS_R800
);
3310 if (!*skip_space (p
))
3314 *q
= opcode
+ ((reg
- 'b') << 3);
3326 emit_muluw (char prefix ATTRIBUTE_UNUSED
, char opcode
, const char * args
)
3330 p
= skip_space (args
);
3331 if (TOLOWER (*p
++) != 'h' || TOLOWER (*p
++) != 'l' || *p
++ != ',')
3338 p
= parse_exp (p
, & reg
);
3340 if ((!reg
.X_md
) && reg
.X_op
== O_register
)
3341 switch (reg
.X_add_number
)
3345 check_mach (INS_R800
);
3348 *q
= opcode
+ ((reg
.X_add_number
& 3) << 4);
3358 assemble_suffix (const char **suffix
)
3361 const char sf
[8][4] =
3381 for (i
= 0; (i
< 3) && (ISALPHA (*p
)); i
++)
3382 sbuf
[i
] = TOLOWER (*p
++);
3383 if (*p
&& !ISSPACE (*p
))
3388 t
= bsearch (sbuf
, sf
, ARRAY_SIZE (sf
), sizeof (sf
[0]), (int(*)(const void*, const void*)) strcmp
);
3395 i
= cpu_mode
? 0x5B : 0x52;
3398 i
= cpu_mode
? 0x49 : 0x40;
3401 i
= cpu_mode
? 0x5B : 0x49;
3410 i
= cpu_mode
? 0x52 : 0x40;
3419 *frag_more (1) = (char)i
;
3422 case 0x40: inst_mode
= INST_MODE_FORCED
| INST_MODE_S
| INST_MODE_IS
; break;
3423 case 0x49: inst_mode
= INST_MODE_FORCED
| INST_MODE_L
| INST_MODE_IS
; break;
3424 case 0x52: inst_mode
= INST_MODE_FORCED
| INST_MODE_S
| INST_MODE_IL
; break;
3425 case 0x5B: inst_mode
= INST_MODE_FORCED
| INST_MODE_L
| INST_MODE_IL
; break;
3433 #if defined(OBJ_ELF)
3434 return obj_elf_section (arg
);
3435 #elif defined(OBJ_COFF)
3436 return obj_coff_section (arg
);
3438 #error Unknown object format
3448 as_fatal (_("Invalid directive"));
3451 ins_ok
&= INS_MARCH_MASK
;
3453 if (old_ins
!= ins_ok
)
3458 ignore (int arg ATTRIBUTE_UNUSED
)
3460 ignore_rest_of_line ();
3468 as_fatal (_("Invalid directive"));
3469 for (p
= input_line_pointer
; *p
&& *p
!= '(' && *p
!= '\n'; p
++)
3476 ignore_rest_of_line ();
3482 /* Handle the .bss pseudo-op. */
3485 s_bss (int ignore ATTRIBUTE_UNUSED
)
3487 subseg_set (bss_section
, 0);
3488 demand_empty_rest_of_line ();
3491 /* Port specific pseudo ops. */
3492 const pseudo_typeS md_pseudo_table
[] =
3494 { ".area", area
, 0},
3495 { ".assume", assume
, 0},
3496 { ".ez80", set_inss
, INS_EZ80
},
3497 { ".gbz80", set_inss
, INS_GBZ80
},
3498 { ".module", ignore
, 0},
3499 { ".optsdcc", ignore
, 0},
3500 { ".r800", set_inss
, INS_R800
},
3501 { ".set", s_set
, 0},
3502 { ".z180", set_inss
, INS_Z180
},
3503 { ".hd64", set_inss
, INS_Z180
},
3504 { ".z80", set_inss
, INS_Z80
},
3505 { ".z80n", set_inss
, INS_Z80N
},
3507 { "db" , emit_data
, 1},
3508 { "d24", z80_cons
, 3},
3509 { "d32", z80_cons
, 4},
3510 { "def24", z80_cons
, 3},
3511 { "def32", z80_cons
, 4},
3512 { "defb", emit_data
, 1},
3513 { "defm", emit_data
, 1},
3514 { "defs", s_space
, 1}, /* Synonym for ds on some assemblers. */
3515 { "defw", z80_cons
, 2},
3516 { "ds", s_space
, 1}, /* Fill with bytes rather than words. */
3517 { "dw", z80_cons
, 2},
3518 { "psect", psect
, 0}, /* TODO: Translate attributes. */
3519 { "set", 0, 0}, /* Real instruction on z80. */
3520 { "xdef", s_globl
, 0}, /* Synonym for .GLOBAL */
3521 { "xref", s_ignore
, 0}, /* Synonym for .EXTERN */
3525 static table_t instab
[] =
3527 { "adc", 0x88, 0x4A, emit_adc
, INS_ALL
},
3528 { "add", 0x80, 0x09, emit_add
, INS_ALL
},
3529 { "and", 0x00, 0xA0, emit_s
, INS_ALL
},
3530 { "bit", 0xCB, 0x40, emit_bit
, INS_ALL
},
3531 { "brlc", 0xED, 0x2C, emit_bshft
,INS_Z80N
},
3532 { "bsla", 0xED, 0x28, emit_bshft
,INS_Z80N
},
3533 { "bsra", 0xED, 0x29, emit_bshft
,INS_Z80N
},
3534 { "bsrf", 0xED, 0x2B, emit_bshft
,INS_Z80N
},
3535 { "bsrl", 0xED, 0x2A, emit_bshft
,INS_Z80N
},
3536 { "call", 0xCD, 0xC4, emit_jpcc
, INS_ALL
},
3537 { "ccf", 0x00, 0x3F, emit_insn
, INS_ALL
},
3538 { "cp", 0x00, 0xB8, emit_s
, INS_ALL
},
3539 { "cpd", 0xED, 0xA9, emit_insn
, INS_NOT_GBZ80
},
3540 { "cpdr", 0xED, 0xB9, emit_insn
, INS_NOT_GBZ80
},
3541 { "cpi", 0xED, 0xA1, emit_insn
, INS_NOT_GBZ80
},
3542 { "cpir", 0xED, 0xB1, emit_insn
, INS_NOT_GBZ80
},
3543 { "cpl", 0x00, 0x2F, emit_insn
, INS_ALL
},
3544 { "daa", 0x00, 0x27, emit_insn
, INS_ALL
},
3545 { "dec", 0x0B, 0x05, emit_incdec
,INS_ALL
},
3546 { "di", 0x00, 0xF3, emit_insn
, INS_ALL
},
3547 { "djnz", 0x00, 0x10, emit_jr
, INS_NOT_GBZ80
},
3548 { "ei", 0x00, 0xFB, emit_insn
, INS_ALL
},
3549 { "ex", 0x00, 0x00, emit_ex
, INS_NOT_GBZ80
},
3550 { "exx", 0x00, 0xD9, emit_insn
, INS_NOT_GBZ80
},
3551 { "halt", 0x00, 0x76, emit_insn
, INS_ALL
},
3552 { "im", 0xED, 0x46, emit_im
, INS_NOT_GBZ80
},
3553 { "in", 0x00, 0x00, emit_in
, INS_NOT_GBZ80
},
3554 { "in0", 0xED, 0x00, emit_in0
, INS_Z180
|INS_EZ80
},
3555 { "inc", 0x03, 0x04, emit_incdec
,INS_ALL
},
3556 { "ind", 0xED, 0xAA, emit_insn
, INS_NOT_GBZ80
},
3557 { "ind2", 0xED, 0x8C, emit_insn
, INS_EZ80
},
3558 { "ind2r",0xED, 0x9C, emit_insn
, INS_EZ80
},
3559 { "indm", 0xED, 0x8A, emit_insn
, INS_EZ80
},
3560 { "indmr",0xED, 0x9A, emit_insn
, INS_EZ80
},
3561 { "indr", 0xED, 0xBA, emit_insn
, INS_NOT_GBZ80
},
3562 { "indrx",0xED, 0xCA, emit_insn
, INS_EZ80
},
3563 { "ini", 0xED, 0xA2, emit_insn
, INS_NOT_GBZ80
},
3564 { "ini2", 0xED, 0x84, emit_insn
, INS_EZ80
},
3565 { "ini2r",0xED, 0x94, emit_insn
, INS_EZ80
},
3566 { "inim", 0xED, 0x82, emit_insn
, INS_EZ80
},
3567 { "inimr",0xED, 0x92, emit_insn
, INS_EZ80
},
3568 { "inir", 0xED, 0xB2, emit_insn
, INS_NOT_GBZ80
},
3569 { "inirx",0xED, 0xC2, emit_insn
, INS_EZ80
},
3570 { "jp", 0xC3, 0xC2, emit_jpcc
, INS_ALL
},
3571 { "jr", 0x18, 0x20, emit_jrcc
, INS_ALL
},
3572 { "ld", 0x00, 0x00, emit_ld
, INS_ALL
},
3573 { "ldd", 0xED, 0xA8, emit_lddldi
,INS_ALL
}, /* GBZ80 has special meaning */
3574 { "lddr", 0xED, 0xB8, emit_insn
, INS_NOT_GBZ80
},
3575 { "lddrx",0xED, 0xBC, emit_insn
, INS_Z80N
},
3576 { "lddx", 0xED, 0xAC, emit_insn
, INS_Z80N
},
3577 { "ldh", 0xE0, 0x00, emit_ldh
, INS_GBZ80
},
3578 { "ldhl", 0x00, 0xF8, emit_ldhl
, INS_GBZ80
},
3579 { "ldi", 0xED, 0xA0, emit_lddldi
,INS_ALL
}, /* GBZ80 has special meaning */
3580 { "ldir", 0xED, 0xB0, emit_insn
, INS_NOT_GBZ80
},
3581 { "ldirx",0xED, 0xB4, emit_insn
, INS_Z80N
},
3582 { "ldix", 0xED, 0xA4, emit_insn
, INS_Z80N
},
3583 { "ldpirx",0xED,0xB7, emit_insn
, INS_Z80N
},
3584 { "ldws", 0xED, 0xA5, emit_insn
, INS_Z80N
},
3585 { "lea", 0xED, 0x02, emit_lea
, INS_EZ80
},
3586 { "mirror",0xED,0x24, emit_insn
, INS_Z80N
},
3587 { "mlt", 0xED, 0x4C, emit_mlt
, INS_Z180
|INS_EZ80
|INS_Z80N
},
3588 { "mul", 0xED, 0x30, emit_mul
, INS_Z80N
},
3589 { "mulub",0xED, 0xC5, emit_mulub
,INS_R800
},
3590 { "muluw",0xED, 0xC3, emit_muluw
,INS_R800
},
3591 { "neg", 0xED, 0x44, emit_insn
, INS_NOT_GBZ80
},
3592 { "nextreg",0xED,0x91,emit_nextreg
,INS_Z80N
},
3593 { "nop", 0x00, 0x00, emit_insn
, INS_ALL
},
3594 { "or", 0x00, 0xB0, emit_s
, INS_ALL
},
3595 { "otd2r",0xED, 0xBC, emit_insn
, INS_EZ80
},
3596 { "otdm", 0xED, 0x8B, emit_insn
, INS_Z180
|INS_EZ80
},
3597 { "otdmr",0xED, 0x9B, emit_insn
, INS_Z180
|INS_EZ80
},
3598 { "otdr", 0xED, 0xBB, emit_insn
, INS_NOT_GBZ80
},
3599 { "otdrx",0xED, 0xCB, emit_insn
, INS_EZ80
},
3600 { "oti2r",0xED, 0xB4, emit_insn
, INS_EZ80
},
3601 { "otim", 0xED, 0x83, emit_insn
, INS_Z180
|INS_EZ80
},
3602 { "otimr",0xED, 0x93, emit_insn
, INS_Z180
|INS_EZ80
},
3603 { "otir", 0xED, 0xB3, emit_insn
, INS_NOT_GBZ80
},
3604 { "otirx",0xED, 0xC3, emit_insn
, INS_EZ80
},
3605 { "out", 0x00, 0x00, emit_out
, INS_NOT_GBZ80
},
3606 { "out0", 0xED, 0x01, emit_out0
, INS_Z180
|INS_EZ80
},
3607 { "outd", 0xED, 0xAB, emit_insn
, INS_NOT_GBZ80
},
3608 { "outd2",0xED, 0xAC, emit_insn
, INS_EZ80
},
3609 { "outi", 0xED, 0xA3, emit_insn
, INS_NOT_GBZ80
},
3610 { "outi2",0xED, 0xA4, emit_insn
, INS_EZ80
},
3611 { "outinb",0xED,0x90, emit_insn
, INS_Z80N
},
3612 { "pea", 0xED, 0x65, emit_pea
, INS_EZ80
},
3613 { "pixelad",0xED,0x94,emit_insn
, INS_Z80N
},
3614 { "pixeldn",0xED,0x93,emit_insn
, INS_Z80N
},
3615 { "pop", 0x00, 0xC1, emit_pop
, INS_ALL
},
3616 { "push", 0x00, 0xC5, emit_push
, INS_ALL
},
3617 { "res", 0xCB, 0x80, emit_bit
, INS_ALL
},
3618 { "ret", 0xC9, 0xC0, emit_retcc
,INS_ALL
},
3619 { "reti", 0xED, 0x4D, emit_reti
, INS_ALL
}, /*GBZ80 has its own opcode for it*/
3620 { "retn", 0xED, 0x45, emit_insn
, INS_NOT_GBZ80
},
3621 { "rl", 0xCB, 0x10, emit_mr
, INS_ALL
},
3622 { "rla", 0x00, 0x17, emit_insn
, INS_ALL
},
3623 { "rlc", 0xCB, 0x00, emit_mr
, INS_ALL
},
3624 { "rlca", 0x00, 0x07, emit_insn
, INS_ALL
},
3625 { "rld", 0xED, 0x6F, emit_insn
, INS_NOT_GBZ80
},
3626 { "rr", 0xCB, 0x18, emit_mr
, INS_ALL
},
3627 { "rra", 0x00, 0x1F, emit_insn
, INS_ALL
},
3628 { "rrc", 0xCB, 0x08, emit_mr
, INS_ALL
},
3629 { "rrca", 0x00, 0x0F, emit_insn
, INS_ALL
},
3630 { "rrd", 0xED, 0x67, emit_insn
, INS_NOT_GBZ80
},
3631 { "rsmix",0xED, 0x7E, emit_insn
, INS_EZ80
},
3632 { "rst", 0x00, 0xC7, emit_rst
, INS_ALL
},
3633 { "sbc", 0x98, 0x42, emit_adc
, INS_ALL
},
3634 { "scf", 0x00, 0x37, emit_insn
, INS_ALL
},
3635 { "set", 0xCB, 0xC0, emit_bit
, INS_ALL
},
3636 { "setae",0xED, 0x95, emit_insn
, INS_Z80N
},
3637 { "sl1", 0xCB, 0x30, emit_mr
, INS_SLI
|INS_Z80N
},
3638 { "sla", 0xCB, 0x20, emit_mr
, INS_ALL
},
3639 { "sli", 0xCB, 0x30, emit_mr
, INS_SLI
|INS_Z80N
},
3640 { "sll", 0xCB, 0x30, emit_mr
, INS_SLI
|INS_Z80N
},
3641 { "slp", 0xED, 0x76, emit_insn
, INS_Z180
|INS_EZ80
},
3642 { "sra", 0xCB, 0x28, emit_mr
, INS_ALL
},
3643 { "srl", 0xCB, 0x38, emit_mr
, INS_ALL
},
3644 { "stmix",0xED, 0x7D, emit_insn
, INS_EZ80
},
3645 { "stop", 0x00, 0x10, emit_insn
, INS_GBZ80
},
3646 { "sub", 0x00, 0x90, emit_sub
, INS_ALL
},
3647 { "swap", 0xCB, 0x30, emit_swap
, INS_GBZ80
|INS_Z80N
},
3648 { "swapnib",0xED,0x23,emit_insn
, INS_Z80N
},
3649 { "test", 0xED, 0x27, emit_insn_n
, INS_Z80N
},
3650 { "tst", 0xED, 0x04, emit_tst
, INS_Z180
|INS_EZ80
|INS_Z80N
},
3651 { "tstio",0xED, 0x74, emit_insn_n
,INS_Z180
|INS_EZ80
},
3652 { "xor", 0x00, 0xA8, emit_s
, INS_ALL
},
3656 md_assemble (char *str
)
3664 inst_mode
= cpu_mode
? (INST_MODE_L
| INST_MODE_IL
) : (INST_MODE_S
| INST_MODE_IS
);
3665 old_ptr
= input_line_pointer
;
3666 p
= skip_space (str
);
3667 for (i
= 0; (i
< BUFLEN
) && (ISALPHA (*p
) || ISDIGIT (*p
));)
3668 buf
[i
++] = TOLOWER (*p
++);
3672 buf
[BUFLEN
-3] = buf
[BUFLEN
-2] = '.'; /* Mark opcode as abbreviated. */
3674 as_bad (_("Unknown instruction '%s'"), buf
);
3678 dwarf2_emit_insn (0);
3679 if ((*p
) && (!ISSPACE (*p
)))
3681 if (*p
!= '.' || !(ins_ok
& INS_EZ80
) || !assemble_suffix (&p
))
3683 as_bad (_("syntax error"));
3691 insp
= bsearch (&key
, instab
, ARRAY_SIZE (instab
),
3692 sizeof (instab
[0]), key_cmp
);
3693 if (!insp
|| (insp
->inss
&& !(insp
->inss
& ins_ok
)))
3696 as_bad (_("Unknown instruction `%s'"), buf
);
3700 p
= insp
->fp (insp
->prefix
, insp
->opcode
, p
);
3702 if ((!err_flag
) && *p
)
3703 as_bad (_("junk at end of line, "
3704 "first unrecognized character is `%c'"), *p
);
3708 input_line_pointer
= old_ptr
;
3712 signed_overflow (signed long value
, unsigned bitsize
)
3714 signed long max
= (signed long) ((1UL << (bitsize
- 1)) - 1);
3715 return value
< -max
- 1 || value
> max
;
3719 unsigned_overflow (unsigned long value
, unsigned bitsize
)
3721 return value
>> (bitsize
- 1) >> 1 != 0;
3725 is_overflow (long value
, unsigned bitsize
)
3728 return signed_overflow (value
, bitsize
);
3729 return unsigned_overflow ((unsigned long)value
, bitsize
);
3733 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
3736 char *p_lit
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
3738 if (fixP
->fx_addsy
== NULL
)
3740 else if (fixP
->fx_pcrel
)
3742 segT s
= S_GET_SEGMENT (fixP
->fx_addsy
);
3743 if (s
== seg
|| s
== absolute_section
)
3745 val
+= S_GET_VALUE (fixP
->fx_addsy
);
3750 switch (fixP
->fx_r_type
)
3752 case BFD_RELOC_8_PCREL
:
3753 case BFD_RELOC_Z80_DISP8
:
3758 case BFD_RELOC_Z80_16_BE
:
3759 fixP
->fx_no_overflow
= 0;
3762 fixP
->fx_no_overflow
= 1;
3766 switch (fixP
->fx_r_type
)
3768 case BFD_RELOC_8_PCREL
:
3769 case BFD_RELOC_Z80_DISP8
:
3770 if (fixP
->fx_done
&& signed_overflow (val
, 8))
3771 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3772 _("8-bit signed offset out of range (%+ld)"), val
);
3776 case BFD_RELOC_Z80_BYTE0
:
3780 case BFD_RELOC_Z80_BYTE1
:
3781 *p_lit
++ = (val
>> 8);
3784 case BFD_RELOC_Z80_BYTE2
:
3785 *p_lit
++ = (val
>> 16);
3788 case BFD_RELOC_Z80_BYTE3
:
3789 *p_lit
++ = (val
>> 24);
3793 if (fixP
->fx_done
&& is_overflow(val
, 8))
3794 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
3795 _("8-bit overflow (%+ld)"), val
);
3799 case BFD_RELOC_Z80_WORD1
:
3800 *p_lit
++ = (val
>> 16);
3801 *p_lit
++ = (val
>> 24);
3804 case BFD_RELOC_Z80_WORD0
:
3806 *p_lit
++ = (val
>> 8);
3810 if (fixP
->fx_done
&& is_overflow(val
, 16))
3811 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
3812 _("16-bit overflow (%+ld)"), val
);
3814 *p_lit
++ = (val
>> 8);
3817 case BFD_RELOC_24
: /* Def24 may produce this. */
3818 if (fixP
->fx_done
&& is_overflow(val
, 24))
3819 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
3820 _("24-bit overflow (%+ld)"), val
);
3822 *p_lit
++ = (val
>> 8);
3823 *p_lit
++ = (val
>> 16);
3826 case BFD_RELOC_32
: /* Def32 and .long may produce this. */
3827 if (fixP
->fx_done
&& is_overflow(val
, 32))
3828 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
3829 _("32-bit overflow (%+ld)"), val
);
3831 *p_lit
++ = (val
>> 8);
3832 *p_lit
++ = (val
>> 16);
3833 *p_lit
++ = (val
>> 24);
3836 case BFD_RELOC_Z80_16_BE
: /* Z80N PUSH nn instruction produce this. */
3837 *p_lit
++ = val
>> 8;
3842 printf (_("md_apply_fix: unknown reloc type 0x%x\n"), fixP
->fx_r_type
);
3847 /* GAS will call this to generate a reloc. GAS will pass the
3848 resulting reloc to `bfd_install_relocation'. This currently works
3849 poorly, as `bfd_install_relocation' often does the wrong thing, and
3850 instances of `tc_gen_reloc' have been written to work around the
3851 problems, which in turns makes it difficult to fix
3852 `bfd_install_relocation'. */
3854 /* If while processing a fixup, a reloc really
3855 needs to be created then it is done here. */
3858 tc_gen_reloc (asection
*seg ATTRIBUTE_UNUSED
, fixS
*fixp
)
3862 if (fixp
->fx_subsy
!= NULL
)
3864 as_bad_subtract (fixp
);
3868 reloc
= XNEW (arelent
);
3869 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
3870 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3871 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3872 reloc
->addend
= fixp
->fx_offset
;
3873 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
3874 if (reloc
->howto
== NULL
)
3876 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3877 _("reloc %d not supported by object file format"),
3878 (int) fixp
->fx_r_type
);
3882 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3883 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3884 reloc
->address
= fixp
->fx_offset
;
3890 z80_tc_labels_without_colon (void)
3892 return colonless_labels
;
3896 z80_tc_label_is_local (const char *name
)
3900 if (local_label_prefix
== NULL
)
3902 for (p
= local_label_prefix
, n
= name
; *p
&& *n
&& *n
== *p
; p
++, n
++)
3907 /* Parse floating point number from string and compute mantissa and
3908 exponent. Mantissa is normalized.
3910 #define EXP_MIN -0x10000
3911 #define EXP_MAX 0x10000
3913 str_to_broken_float (bool *signP
, uint64_t *mantissaP
, int *expP
)
3917 uint64_t mantissa
= 0;
3921 p
= (char*)skip_space (input_line_pointer
);
3924 if (sign
|| *p
== '+')
3926 if (strncasecmp (p
, "NaN", 3) == 0)
3930 input_line_pointer
= p
+ 3;
3933 if (strncasecmp (p
, "inf", 3) == 0)
3935 *mantissaP
= 1ull << 63;
3937 input_line_pointer
= p
+ 3;
3940 for (; ISDIGIT (*p
); ++p
)
3948 mantissa
= mantissa
* 10 + (*p
- '0');
3950 /* skip non-significant digits */
3951 for (; ISDIGIT (*p
); ++p
)
3957 if (!exponent
) /* If no precision overflow. */
3959 for (; ISDIGIT (*p
); ++p
, --exponent
)
3967 mantissa
= mantissa
* 10 + (*p
- '0');
3970 for (; ISDIGIT (*p
); ++p
)
3973 if (*p
== 'e' || *p
== 'E')
3979 if (es
|| *p
== '+')
3981 for (; ISDIGIT (*p
); ++p
)
3984 t
= t
* 10 + (*p
- '0');
3986 exponent
+= (es
) ? -t
: t
;
3988 if (ISALNUM (*p
) || *p
== '.')
3990 input_line_pointer
= p
;
3993 *mantissaP
= 1ull << 63;
3995 return 1; /* result is 0 */
3998 for (; mantissa
<= ~0ull/10; --exponent
)
4000 /* Now we have sign, mantissa, and signed decimal exponent
4001 need to recompute to binary exponent. */
4002 for (i
= 64; exponent
> 0; --exponent
)
4004 /* be sure that no integer overflow */
4005 while (mantissa
> ~0ull/10)
4012 for (; exponent
< 0; ++exponent
)
4014 while (!(mantissa
>> 63))
4022 for (; !(mantissa
>> 63); --i
)
4024 *mantissaP
= mantissa
;
4030 str_to_zeda32(char *litP
, int *sizeP
)
4038 if (!str_to_broken_float (&sign
, &mantissa
, &exponent
))
4039 return _("invalid syntax");
4040 /* I do not know why decrement is needed */
4042 /* shift by 39 bits right keeping 25 bit mantissa for rounding */
4046 /* make 24 bit mantissa */
4048 /* check for overflow */
4055 if (exponent
< -127)
4060 else if (exponent
> 127)
4063 mantissa
= sign
? 0xc00000 : 0x400000;
4065 else if (mantissa
== 0)
4068 mantissa
= 0x200000;
4071 mantissa
&= (1ull << 23) - 1;
4072 for (i
= 0; i
< 24; i
+= 8)
4073 *litP
++ = (char)(mantissa
>> i
);
4074 *litP
= (char)(0x80 + exponent
);
4079 Math48 by Anders Hejlsberg support.
4080 Mantissa is 39 bits wide, exponent 8 bit wide.
4083 bit 46-8: normalized mantissa (bits 38-0, bit39 assumed to be 1)
4084 bit 7-0: exponent+128 (0 - value is null)
4085 MIN: 2.938735877e-39
4086 MAX: 1.701411835e+38
4089 str_to_float48(char *litP
, int *sizeP
)
4097 if (!str_to_broken_float (&sign
, &mantissa
, &exponent
))
4098 return _("invalid syntax");
4099 /* shift by 23 bits right keeping 41 bit mantissa for rounding */
4103 /* make 40 bit mantissa */
4105 /* check for overflow */
4111 if (exponent
< -127)
4113 memset (litP
, 0, 6);
4117 return _("overflow");
4119 mantissa
&= (1ull << 39) - 1;
4120 *litP
++ = (char)(0x80 + exponent
);
4121 for (i
= 0; i
< 40; i
+= 8)
4122 *litP
++ = (char)(mantissa
>> i
);
4127 str_to_ieee754_h(char *litP
, int *sizeP
)
4129 return ieee_md_atof ('h', litP
, sizeP
, false);
4133 str_to_ieee754_s(char *litP
, int *sizeP
)
4135 return ieee_md_atof ('s', litP
, sizeP
, false);
4139 str_to_ieee754_d(char *litP
, int *sizeP
)
4141 return ieee_md_atof ('d', litP
, sizeP
, false);
4144 #ifdef TARGET_USE_CFIPOP
4145 /* Initialize the DWARF-2 unwind information for this procedure. */
4147 z80_tc_frame_initial_instructions (void)
4149 static int sp_regno
= -1;
4152 sp_regno
= z80_tc_regname_to_dw2regnum ("sp");
4154 cfi_add_CFA_def_cfa (sp_regno
, 0);
4158 z80_tc_regname_to_dw2regnum (const char *regname
)
4160 static const char *regs
[] =
4161 { /* same registers as for GDB */
4162 "af", "bc", "de", "hl",
4163 "sp", "pc", "ix", "iy",
4164 "af_", "bc_", "de_", "hl_",
4169 for (i
= 0; i
< ARRAY_SIZE(regs
); ++i
)
4170 if (!strcasecmp (regs
[i
], regname
))
4177 /* Implement DWARF2_ADDR_SIZE. */
4179 z80_dwarf2_addr_size (const bfd
*abfd
)
4181 switch (bfd_get_mach (abfd
))
4183 case bfd_mach_ez80_adl
: