gas/doc/c-aarch64.texi

   1 @c Copyright (C) 2009-2015 Free Software Foundation, Inc.
   2 @c Contributed by ARM Ltd.
   3 @c This is part of the GAS manual.
   4 @c For copying conditions, see the file as.texinfo.
   5 @c man end
   6
   7 @ifset GENERIC
   8 @page
   9 @node AArch64-Dependent
  10 @chapter AArch64 Dependent Features
  11 @end ifset
  12
  13 @ifclear GENERIC
  14 @node Machine Dependencies
  15 @chapter AArch64 Dependent Features
  16 @end ifclear
  17
  18 @cindex AArch64 support
  19 @menu
  20 * AArch64 Options::              Options
  21 * AArch64 Extensions::           Extensions
  22 * AArch64 Syntax::               Syntax
  23 * AArch64 Floating Point::       Floating Point
  24 * AArch64 Directives::           AArch64 Machine Directives
  25 * AArch64 Opcodes::              Opcodes
  26 * AArch64 Mapping Symbols::      Mapping Symbols
  27 @end menu
  28
  29 @node AArch64 Options
  30 @section Options
  31 @cindex AArch64 options (none)
  32 @cindex options for AArch64 (none)
  33
  34 @c man begin OPTIONS
  35 @table @gcctabopt
  36
  37 @cindex @option{-EB} command line option, AArch64
  38 @item -EB
  39 This option specifies that the output generated by the assembler should
  40 be marked as being encoded for a big-endian processor.
  41
  42 @cindex @option{-EL} command line option, AArch64
  43 @item -EL
  44 This option specifies that the output generated by the assembler should
  45 be marked as being encoded for a little-endian processor.
  46
  47 @cindex @option{-mabi=} command line option, AArch64
  48 @item -mabi=@var{abi}
  49 Specify which ABI the source code uses.  The recognized arguments
  50 are: @code{ilp32} and @code{lp64}, which decides the generated object
  51 file in ELF32 and ELF64 format respectively.  The default is @code{lp64}.
  52
  53 @cindex @option{-mcpu=} command line option, AArch64
  54 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
  55 This option specifies the target processor.  The assembler will issue an error
  56 message if an attempt is made to assemble an instruction which will not execute
  57 on the target processor.  The following processor names are recognized:
  58 @code{cortex-a35},
  59 @code{cortex-a53},
  60 @code{cortex-a57},
  61 @code{cortex-a72},
  62 @code{exynos-m1},
  63 @code{qdf24xx},
  64 @code{thunderx},
  65 @code{xgene1}
  66 and
  67 @code{xgene2}.
  68 The special name @code{all} may be used to allow the assembler to accept
  69 instructions valid for any supported processor, including all optional
  70 extensions.
  71
  72 In addition to the basic instruction set, the assembler can be told to
  73 accept, or restrict, various extension mnemonics that extend the
  74 processor.  @xref{AArch64 Extensions}.
  75
  76 If some implementations of a particular processor can have an
  77 extension, then then those extensions are automatically enabled.
  78 Consequently, you will not normally have to specify any additional
  79 extensions.
  80
  81 @cindex @option{-march=} command line option, AArch64
  82 @item -march=@var{architecture}[+@var{extension}@dots{}]
  83 This option specifies the target architecture.  The assembler will
  84 issue an error message if an attempt is made to assemble an
  85 instruction which will not execute on the target architecture.  The
  86 following architecture names are recognized: @code{armv8-a},
  87 @code{armv8.1-a} and @code{armv8.2-a}.
  88
  89 If both @option{-mcpu} and @option{-march} are specified, the
  90 assembler will use the setting for @option{-mcpu}.  If neither are
  91 specified, the assembler will default to @option{-mcpu=all}.
  92
  93 The architecture option can be extended with the same instruction set
  94 extension options as the @option{-mcpu} option.  Unlike
  95 @option{-mcpu}, extensions are not always enabled by default,
  96 @xref{AArch64 Extensions}.
  97
  98 @cindex @code{-mverbose-error} command line option, AArch64
  99 @item -mverbose-error
 100 This option enables verbose error messages for AArch64 gas.  This option
 101 is enabled by default.
 102
 103 @cindex @code{-mno-verbose-error} command line option, AArch64
 104 @item -mno-verbose-error
 105 This option disables verbose error messages in AArch64 gas.
 106
 107 @end table
 108 @c man end
 109
 110 @node AArch64 Extensions
 111 @section Architecture Extensions
 112
 113 The table below lists the permitted architecture extensions that are
 114 supported by the assembler and the conditions under which they are
 115 automatically enabled.
 116
 117 Multiple extensions may be specified, separated by a @code{+}.
 118 Extension mnemonics may also be removed from those the assembler
 119 accepts.  This is done by prepending @code{no} to the option that adds
 120 the extension.  Extensions that are removed must be listed after all
 121 extensions that have been added.
 122
 123 Enabling an extension that requires other extensions will
 124 automatically cause those extensions to be enabled.  Similarly,
 125 disabling an extension that is required by other extensions will
 126 automatically cause those extensions to be disabled.
 127
 128 @multitable @columnfractions .12 .17 .17 .54
 129 @headitem Extension @tab Minimum Architecture @tab Enabled by default
 130  @tab Description
 131 @item @code{crc} @tab ARMv8-A @tab ARMv8.1-A or later
 132  @tab Enable CRC instructions.
 133 @item @code{crypto} @tab ARMv8-A @tab No
 134  @tab Enable cryptographic extensions.  This implies @code{fp} and @code{simd}.
 135 @item @code{fp} @tab ARMv8-A @tab ARMv8-A or later
 136  @tab Enable floating-point extensions.
 137 @item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
 138  @tab Enable Advanced SIMD extensions.  This implies @code{fp}.
 139 @item @code{pan} @tab ARMv8-A @tab ARMv8-A or later
 140  @tab Enable Privileged Access Never support.
 141 @item @code{lor} @tab ARMv8-A @tab ARMv8-A or later
 142  @tab Enable Limited Ordering Regions extensions.
 143 @item @code{rdma} @tab ARMv8-A @tab ARMv8-A or later
 144  @tab Enable ARMv8.1 Advanced SIMD extensions.  This implies @code{simd}.
 145 @item @code{fp16} @tab ARMv8.2-A @tab ARMv8.2-A or later
 146  @tab Enable ARMv8.2 16-bit floating-point support.  This implies
 147  @code{fp}.
 148 @end multitable
 149
 150 @node AArch64 Syntax
 151 @section Syntax
 152 @menu
 153 * AArch64-Chars::                Special Characters
 154 * AArch64-Regs::                 Register Names
 155 * AArch64-Relocations::      Relocations
 156 @end menu
 157
 158 @node AArch64-Chars
 159 @subsection Special Characters
 160
 161 @cindex line comment character, AArch64
 162 @cindex AArch64 line comment character
 163 The presence of a @samp{//} on a line indicates the start of a comment
 164 that extends to the end of the current line.  If a @samp{#} appears as
 165 the first character of a line, the whole line is treated as a comment.
 166
 167 @cindex line separator, AArch64
 168 @cindex statement separator, AArch64
 169 @cindex AArch64 line separator
 170 The @samp{;} character can be used instead of a newline to separate
 171 statements.
 172
 173 @cindex immediate character, AArch64
 174 @cindex AArch64 immediate character
 175 The @samp{#} can be optionally used to indicate immediate operands.
 176
 177 @node AArch64-Regs
 178 @subsection Register Names
 179
 180 @cindex AArch64 register names
 181 @cindex register names, AArch64
 182 Please refer to the section @samp{4.4 Register Names} of
 183 @samp{ARMv8 Instruction Set Overview}, which is available at
 184 @uref{http://infocenter.arm.com}.
 185
 186 @node AArch64-Relocations
 187 @subsection Relocations
 188
 189 @cindex relocations, AArch64
 190 @cindex AArch64 relocations
 191 @cindex MOVN, MOVZ and MOVK group relocations, AArch64
 192 Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated
 193 by prefixing the label with @samp{#:abs_g2:} etc.
 194 For example to load the 48-bit absolute address of @var{foo} into x0:
 195
 196 @smallexample
 197         movz x0, #:abs_g2:foo           // bits 32-47, overflow check
 198         movk x0, #:abs_g1_nc:foo        // bits 16-31, no overflow check
 199         movk x0, #:abs_g0_nc:foo        // bits  0-15, no overflow check
 200 @end smallexample
 201
 202 @cindex ADRP, ADD, LDR/STR group relocations, AArch64
 203 Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
 204 instructions can be generated by prefixing the label with
 205 @samp{:pg_hi21:} and @samp{#:lo12:} respectively.
 206
 207 For example to use 33-bit (+/-4GB) pc-relative addressing to
 208 load the address of @var{foo} into x0:
 209
 210 @smallexample
 211         adrp x0, :pg_hi21:foo
 212         add  x0, x0, #:lo12:foo
 213 @end smallexample
 214
 215 Or to load the value of @var{foo} into x0:
 216
 217 @smallexample
 218         adrp x0, :pg_hi21:foo
 219         ldr  x0, [x0, #:lo12:foo]
 220 @end smallexample
 221
 222 Note that @samp{:pg_hi21:} is optional.
 223
 224 @smallexample
 225         adrp x0, foo
 226 @end smallexample
 227
 228 is equivalent to
 229
 230 @smallexample
 231         adrp x0, :pg_hi21:foo
 232 @end smallexample
 233
 234 @node AArch64 Floating Point
 235 @section Floating Point
 236
 237 @cindex floating point, AArch64 (@sc{ieee})
 238 @cindex AArch64 floating point (@sc{ieee})
 239 The AArch64 architecture uses @sc{ieee} floating-point numbers.
 240
 241 @node AArch64 Directives
 242 @section AArch64 Machine Directives
 243
 244 @cindex machine directives, AArch64
 245 @cindex AArch64 machine directives
 246 @table @code
 247
 248 @c AAAAAAAAAAAAAAAAAAAAAAAAA
 249
 250 @cindex @code{.arch} directive, AArch64
 251 @item .arch @var{name}
 252 Select the target architecture.  Valid values for @var{name} are the same as
 253 for the @option{-march} commandline option.
 254
 255 Specifying @code{.arch} clears any previously selected architecture
 256 extensions.
 257
 258 @cindex @code{.arch_extension} directive, AArch64
 259 @item .arch_extension @var{name}
 260 Add or remove an architecture extension to the target architecture.  Valid
 261 values for @var{name} are the same as those accepted as architectural
 262 extensions by the @option{-mcpu} commandline option.
 263
 264 @code{.arch_extension} may be used multiple times to add or remove extensions
 265 incrementally to the architecture being compiled for.
 266
 267 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
 268
 269 @cindex @code{.bss} directive, AArch64
 270 @item .bss
 271 This directive switches to the @code{.bss} section.
 272
 273 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
 274 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
 275 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
 276 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
 277 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
 278 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
 279 @c IIIIIIIIIIIIIIIIIIIIIIIIII
 280 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
 281 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
 282 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
 283
 284 @cindex @code{.ltorg} directive, AArch64
 285 @item .ltorg
 286 This directive causes the current contents of the literal pool to be
 287 dumped into the current section (which is assumed to be the .text
 288 section) at the current location (aligned to a word boundary).
 289 GAS maintains a separate literal pool for each section and each
 290 sub-section.  The @code{.ltorg} directive will only affect the literal
 291 pool of the current section and sub-section.  At the end of assembly
 292 all remaining, un-empty literal pools will automatically be dumped.
 293
 294 Note - older versions of GAS would dump the current literal
 295 pool any time a section change occurred.  This is no longer done, since
 296 it prevents accurate control of the placement of literal pools.
 297
 298 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
 299
 300 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
 301 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
 302
 303 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
 304
 305 @cindex @code{.pool} directive, AArch64
 306 @item .pool
 307 This is a synonym for .ltorg.
 308
 309 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
 310 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
 311
 312 @cindex @code{.req} directive, AArch64
 313 @item @var{name} .req @var{register name}
 314 This creates an alias for @var{register name} called @var{name}.  For
 315 example:
 316
 317 @smallexample
 318         foo .req w0
 319 @end smallexample
 320
 321 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
 322
 323 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
 324
 325 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
 326
 327 @cindex @code{.unreq} directive, AArch64
 328 @item .unreq @var{alias-name}
 329 This undefines a register alias which was previously defined using the
 330 @code{req} directive.  For example:
 331
 332 @smallexample
 333         foo .req w0
 334         .unreq foo
 335 @end smallexample
 336
 337 An error occurs if the name is undefined.  Note - this pseudo op can
 338 be used to delete builtin in register name aliases (eg 'w0').  This
 339 should only be done if it is really necessary.
 340
 341 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
 342
 343 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
 344 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
 345 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
 346 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
 347
 348 @cindex @code{.xword} directive, AArch64
 349 @item .xword
 350 The @code{.xword} directive produces 64 bit values.
 351
 352 @end table
 353
 354 @node AArch64 Opcodes
 355 @section Opcodes
 356
 357 @cindex AArch64 opcodes
 358 @cindex opcodes for AArch64
 359 GAS implements all the standard AArch64 opcodes.  It also
 360 implements several pseudo opcodes, including several synthetic load
 361 instructions.
 362
 363 @table @code
 364
 365 @cindex @code{LDR reg,=<expr>} pseudo op, AArch64
 366 @item LDR =
 367 @smallexample
 368   ldr <register> , =<expression>
 369 @end smallexample
 370
 371 The constant expression will be placed into the nearest literal pool (if it not
 372 already there) and a PC-relative LDR instruction will be generated.
 373
 374 @end table
 375
 376 For more information on the AArch64 instruction set and assembly language
 377 notation, see @samp{ARMv8 Instruction Set Overview} available at
 378 @uref{http://infocenter.arm.com}.
 379
 380
 381 @node AArch64 Mapping Symbols
 382 @section Mapping Symbols
 383
 384 The AArch64 ELF specification requires that special symbols be inserted
 385 into object files to mark certain features:
 386
 387 @table @code
 388
 389 @cindex @code{$x}
 390 @item $x
 391 At the start of a region of code containing AArch64 instructions.
 392
 393 @cindex @code{$d}
 394 @item $d
 395 At the start of a region of data.
 396
 397 @end table