gas/doc/c-aarch64.texi

   1 @c Copyright (C) 2009-2021 Free Software Foundation, Inc.
   2 @c Contributed by ARM Ltd.
   3 @c This is part of the GAS manual.
   4 @c For copying conditions, see the file as.texinfo.
   5 @c man end
   6
   7 @ifset GENERIC
   8 @page
   9 @node AArch64-Dependent
  10 @chapter AArch64 Dependent Features
  11 @end ifset
  12
  13 @ifclear GENERIC
  14 @node Machine Dependencies
  15 @chapter AArch64 Dependent Features
  16 @end ifclear
  17
  18 @cindex AArch64 support
  19 @menu
  20 * AArch64 Options::              Options
  21 * AArch64 Extensions::           Extensions
  22 * AArch64 Syntax::               Syntax
  23 * AArch64 Floating Point::       Floating Point
  24 * AArch64 Directives::           AArch64 Machine Directives
  25 * AArch64 Opcodes::              Opcodes
  26 * AArch64 Mapping Symbols::      Mapping Symbols
  27 @end menu
  28
  29 @node AArch64 Options
  30 @section Options
  31 @cindex AArch64 options (none)
  32 @cindex options for AArch64 (none)
  33
  34 @c man begin OPTIONS
  35 @table @gcctabopt
  36
  37 @cindex @option{-EB} command-line option, AArch64
  38 @item -EB
  39 This option specifies that the output generated by the assembler should
  40 be marked as being encoded for a big-endian processor.
  41
  42 @cindex @option{-EL} command-line option, AArch64
  43 @item -EL
  44 This option specifies that the output generated by the assembler should
  45 be marked as being encoded for a little-endian processor.
  46
  47 @cindex @option{-mabi=} command-line option, AArch64
  48 @item -mabi=@var{abi}
  49 Specify which ABI the source code uses.  The recognized arguments
  50 are: @code{ilp32} and @code{lp64}, which decides the generated object
  51 file in ELF32 and ELF64 format respectively.  The default is @code{lp64}.
  52
  53 @cindex @option{-mcpu=} command-line option, AArch64
  54 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
  55 This option specifies the target processor.  The assembler will issue an error
  56 message if an attempt is made to assemble an instruction which will not execute
  57 on the target processor.  The following processor names are recognized:
  58 @code{cortex-a34},
  59 @code{cortex-a35},
  60 @code{cortex-a53},
  61 @code{cortex-a55},
  62 @code{cortex-a57},
  63 @code{cortex-a65},
  64 @code{cortex-a65ae},
  65 @code{cortex-a72},
  66 @code{cortex-a73},
  67 @code{cortex-a75},
  68 @code{cortex-a76},
  69 @code{cortex-a76ae},
  70 @code{cortex-a77},
  71 @code{cortex-a78},
  72 @code{cortex-a78ae},
  73 @code{cortex-a78c},
  74 @code{cortex-a510},
  75 @code{cortex-a710},
  76 @code{ares},
  77 @code{exynos-m1},
  78 @code{falkor},
  79 @code{neoverse-n1},
  80 @code{neoverse-n2},
  81 @code{neoverse-e1},
  82 @code{neoverse-v1},
  83 @code{qdf24xx},
  84 @code{saphira},
  85 @code{thunderx},
  86 @code{vulcan},
  87 @code{xgene1}
  88 @code{xgene2},
  89 @code{cortex-r82},
  90 @code{cortex-x1},
  91 and
  92 @code{cortex-x2}.
  93 The special name @code{all} may be used to allow the assembler to accept
  94 instructions valid for any supported processor, including all optional
  95 extensions.
  96
  97 In addition to the basic instruction set, the assembler can be told to
  98 accept, or restrict, various extension mnemonics that extend the
  99 processor.  @xref{AArch64 Extensions}.
 100
 101 If some implementations of a particular processor can have an
 102 extension, then then those extensions are automatically enabled.
 103 Consequently, you will not normally have to specify any additional
 104 extensions.
 105
 106 @cindex @option{-march=} command-line option, AArch64
 107 @item -march=@var{architecture}[+@var{extension}@dots{}]
 108 This option specifies the target architecture.  The assembler will
 109 issue an error message if an attempt is made to assemble an
 110 instruction which will not execute on the target architecture.  The
 111 following architecture names are recognized: @code{armv8-a},
 112 @code{armv8.1-a}, @code{armv8.2-a}, @code{armv8.3-a}, @code{armv8.4-a}
 113 @code{armv8.5-a}, @code{armv8.6-a}, @code{armv8.7-a}, @code{armv8-r}, and
 114 @code{armv9-a}.
 115
 116 If both @option{-mcpu} and @option{-march} are specified, the
 117 assembler will use the setting for @option{-mcpu}.  If neither are
 118 specified, the assembler will default to @option{-mcpu=all}.
 119
 120 The architecture option can be extended with the same instruction set
 121 extension options as the @option{-mcpu} option.  Unlike
 122 @option{-mcpu}, extensions are not always enabled by default,
 123 @xref{AArch64 Extensions}.
 124
 125 @cindex @code{-mverbose-error} command-line option, AArch64
 126 @item -mverbose-error
 127 This option enables verbose error messages for AArch64 gas.  This option
 128 is enabled by default.
 129
 130 @cindex @code{-mno-verbose-error} command-line option, AArch64
 131 @item -mno-verbose-error
 132 This option disables verbose error messages in AArch64 gas.
 133
 134 @end table
 135 @c man end
 136
 137 @node AArch64 Extensions
 138 @section Architecture Extensions
 139
 140 The table below lists the permitted architecture extensions that are
 141 supported by the assembler and the conditions under which they are
 142 automatically enabled.
 143
 144 Multiple extensions may be specified, separated by a @code{+}.
 145 Extension mnemonics may also be removed from those the assembler
 146 accepts.  This is done by prepending @code{no} to the option that adds
 147 the extension.  Extensions that are removed must be listed after all
 148 extensions that have been added.
 149
 150 Enabling an extension that requires other extensions will
 151 automatically cause those extensions to be enabled.  Similarly,
 152 disabling an extension that is required by other extensions will
 153 automatically cause those extensions to be disabled.
 154
 155 @multitable @columnfractions .12 .17 .17 .54
 156 @headitem Extension @tab Minimum Architecture @tab Enabled by default
 157  @tab Description
 158 @item @code{aes} @tab ARMv8-A @tab No
 159  @tab Enable the AES cryptographic extensions. This implies @code{fp} and
 160  @code{simd}.
 161 @item @code{bf16} @tab ARMv8.2-A @tab ARMv8.6-A or later
 162  @tab Enable BFloat16 extension.
 163 @item @code{compnum} @tab ARMv8.2-A @tab ARMv8.3-A or later
 164  @tab Enable the complex number SIMD extensions.  This implies @code{fp16} and
 165  @code{simd}.
 166 @item @code{crc} @tab ARMv8-A @tab ARMv8.1-A or later
 167  @tab Enable CRC instructions.
 168 @item @code{crypto} @tab ARMv8-A @tab No
 169  @tab Enable cryptographic extensions.  This implies @code{fp}, @code{simd},
 170  @code{aes} and @code{sha2}.
 171 @item @code{dotprod} @tab ARMv8.2-A @tab ARMv8.4-A or later
 172  @tab Enable the Dot Product extension.  This implies @code{simd}.
 173 @item @code{f32mm} @tab ARMv8.2-A @tab No
 174  @tab Enable F32 Matrix Multiply extension.  This implies @code{sve}.
 175 @item @code{f64mm} @tab ARMv8.2-A @tab No
 176  @tab Enable F64 Matrix Multiply extension.  This implies @code{sve}.
 177 @item @code{flagm} @tab ARMv8-A @tab ARMv8.4-A or later
 178  @tab Enable Flag Manipulation instructions.
 179 @item @code{fp16fml} @tab ARMv8.2-A @tab ARMv8.4-A or later
 180  @tab Enable ARMv8.2 16-bit floating-point multiplication variant support. This
 181  implies @code{fp} and  @code{fp16}.
 182 @item @code{fp16} @tab ARMv8.2-A @tab ARMv8.2-A or later
 183  @tab Enable ARMv8.2 16-bit floating-point support.  This implies @code{fp}.
 184 @item @code{fp} @tab ARMv8-A @tab ARMv8-A or later
 185  @tab Enable floating-point extensions.
 186 @item @code{i8mm} @tab ARMv8.2-A @tab ARMv8.6-A or later
 187  @tab Enable Int8 Matrix Multiply extension.
 188 @item @code{lor} @tab ARMv8-A @tab ARMv8.1-A or later
 189  @tab Enable Limited Ordering Regions extensions.
 190 @item @code{ls64} @tab ARMv8.6-A @tab ARMv8.7-A or later
 191  @tab Enable 64 Byte Loads/Stores.
 192 @item @code{lse} @tab ARMv8-A @tab ARMv8.1-A or later
 193  @tab Enable Large System extensions.
 194 @item @code{memtag} @tab ARMv8.5-A @tab No
 195  @tab Enable ARMv8.5-A Memory Tagging Extensions.
 196 @item @code{pan} @tab ARMv8-A @tab ARMv8.1-A or later
 197  @tab Enable Privileged Access Never support.
 198 @item @code{pauth} @tab ARMv8-A @tab No
 199  @tab Enable Pointer Authentication.
 200 @item @code{predres} @tab ARMv8-A @tab ARMv8.5-A or later
 201  @tab Enable the Execution and Data and Prediction instructions.
 202 @item @code{profile} @tab ARMv8.2-A @tab No
 203  @tab Enable statistical profiling extensions.
 204 @item @code{ras} @tab ARMv8-A @tab ARMv8.2-A or later
 205  @tab Enable the Reliability, Availability and Serviceability extension.
 206 @item @code{rcpc} @tab ARMv8.2-A @tab ARMv8.3-A or later
 207  @tab Enable the weak release consistency extension.
 208 @item @code{rdma} @tab ARMv8-A @tab ARMv8.1-A or later
 209  @tab Enable ARMv8.1 Advanced SIMD extensions.  This implies @code{simd}.
 210 @item @code{rng} @tab ARMv8.5-A @tab No
 211  @tab Enable ARMv8.5-A random number instructions.
 212 @item @code{sb} @tab ARMv8-A @tab ARMv8.5-A or later
 213  @tab Enable the speculation barrier instruction sb.
 214 @item @code{sha2} @tab ARMv8-A @tab No
 215  @tab Enable the SHA2 cryptographic extensions. This implies @code{fp} and
 216  @code{simd}.
 217 @item @code{sha3} @tab ARMv8.2-A @tab No
 218  @tab Enable the ARMv8.2-A SHA2 and SHA3 cryptographic extensions. This implies
 219  @code{fp}, @code{simd} and @code{sha2}.
 220 @item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
 221  @tab Enable Advanced SIMD extensions.  This implies @code{fp}.
 222 @item @code{sm4} @tab ARMv8.2-A @tab No
 223  @tab Enable the ARMv8.2-A SM3 and SM4 cryptographic extensions. This implies
 224  @code{fp} and @code{simd}.
 225 @item @code{sme} @tab Armv9-A @tab No
 226  @tab Enable SME Extension.
 227 @item @code{sme-f64} @tab Armv9-A @tab No
 228  @tab Enable SME F64 Extension.
 229 @item @code{sme-i64} @tab Armv9-A @tab No
 230  @tab Enable SME I64 Extension.
 231 @item @code{ssbs} @tab ARMv8-A @tab ARMv8.5-A or later
 232  @tab Enable Speculative Store Bypassing Safe state read and write.
 233 @item @code{sve} @tab ARMv8.2-A @tab Armv9-A or later
 234  @tab Enable the Scalable Vector Extensions.  This implies @code{fp16},
 235  @code{simd} and @code{compnum}.
 236 @item @code{sve2} @tab ARMv8-A @tab Armv9-A or later
 237  @tab Enable the SVE2 Extension.  This implies @code{sve}.
 238 @item @code{sve2-aes} @tab ARMv8-A @tab No
 239  @tab Enable SVE2 AES Extension.  This also enables the .Q->.B form of the
 240  @code{pmullt} and @code{pmullb} instructions.  This implies @code{aes} and
 241  @code{sve2}.
 242 @item @code{sve2-bitperm} @tab ARMv8-A @tab No
 243  @tab Enable SVE2 BITPERM Extension.
 244 @item @code{sve2-sha3} @tab ARMv8-A @tab No
 245  @tab Enable SVE2 SHA3 Extension.  This implies @code{sha3} and @code{sve2}.
 246 @item @code{sve2-sm4} @tab ARMv8-A @tab No
 247  @tab Enable SVE2 SM4 Extension.  This implies @code{sm4} and @code{sve2}.
 248 @item @code{tme} @tab ARMv8-A @tab No
 249  @tab Enable Transactional Memory Extensions.
 250 @end multitable
 251
 252 @node AArch64 Syntax
 253 @section Syntax
 254 @menu
 255 * AArch64-Chars::                Special Characters
 256 * AArch64-Regs::                 Register Names
 257 * AArch64-Relocations::      Relocations
 258 @end menu
 259
 260 @node AArch64-Chars
 261 @subsection Special Characters
 262
 263 @cindex line comment character, AArch64
 264 @cindex AArch64 line comment character
 265 The presence of a @samp{//} on a line indicates the start of a comment
 266 that extends to the end of the current line.  If a @samp{#} appears as
 267 the first character of a line, the whole line is treated as a comment.
 268
 269 @cindex line separator, AArch64
 270 @cindex statement separator, AArch64
 271 @cindex AArch64 line separator
 272 The @samp{;} character can be used instead of a newline to separate
 273 statements.
 274
 275 @cindex immediate character, AArch64
 276 @cindex AArch64 immediate character
 277 The @samp{#} can be optionally used to indicate immediate operands.
 278
 279 @node AArch64-Regs
 280 @subsection Register Names
 281
 282 @cindex AArch64 register names
 283 @cindex register names, AArch64
 284 Please refer to the section @samp{4.4 Register Names} of
 285 @samp{ARMv8 Instruction Set Overview}, which is available at
 286 @uref{http://infocenter.arm.com}.
 287
 288 @node AArch64-Relocations
 289 @subsection Relocations
 290
 291 @cindex relocations, AArch64
 292 @cindex AArch64 relocations
 293 @cindex MOVN, MOVZ and MOVK group relocations, AArch64
 294 Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated
 295 by prefixing the label with @samp{#:abs_g2:} etc.
 296 For example to load the 48-bit absolute address of @var{foo} into x0:
 297
 298 @smallexample
 299         movz x0, #:abs_g2:foo           // bits 32-47, overflow check
 300         movk x0, #:abs_g1_nc:foo        // bits 16-31, no overflow check
 301         movk x0, #:abs_g0_nc:foo        // bits  0-15, no overflow check
 302 @end smallexample
 303
 304 @cindex ADRP, ADD, LDR/STR group relocations, AArch64
 305 Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
 306 instructions can be generated by prefixing the label with
 307 @samp{:pg_hi21:} and @samp{#:lo12:} respectively.
 308
 309 For example to use 33-bit (+/-4GB) pc-relative addressing to
 310 load the address of @var{foo} into x0:
 311
 312 @smallexample
 313         adrp x0, :pg_hi21:foo
 314         add  x0, x0, #:lo12:foo
 315 @end smallexample
 316
 317 Or to load the value of @var{foo} into x0:
 318
 319 @smallexample
 320         adrp x0, :pg_hi21:foo
 321         ldr  x0, [x0, #:lo12:foo]
 322 @end smallexample
 323
 324 Note that @samp{:pg_hi21:} is optional.
 325
 326 @smallexample
 327         adrp x0, foo
 328 @end smallexample
 329
 330 is equivalent to
 331
 332 @smallexample
 333         adrp x0, :pg_hi21:foo
 334 @end smallexample
 335
 336 @node AArch64 Floating Point
 337 @section Floating Point
 338
 339 @cindex floating point, AArch64 (@sc{ieee})
 340 @cindex AArch64 floating point (@sc{ieee})
 341 The AArch64 architecture uses @sc{ieee} floating-point numbers.
 342
 343 @node AArch64 Directives
 344 @section AArch64 Machine Directives
 345
 346 @cindex machine directives, AArch64
 347 @cindex AArch64 machine directives
 348 @table @code
 349
 350 @c AAAAAAAAAAAAAAAAAAAAAAAAA
 351
 352 @cindex @code{.arch} directive, AArch64
 353 @item .arch @var{name}
 354 Select the target architecture.  Valid values for @var{name} are the same as
 355 for the @option{-march} command-line option.
 356
 357 Specifying @code{.arch} clears any previously selected architecture
 358 extensions.
 359
 360 @cindex @code{.arch_extension} directive, AArch64
 361 @item .arch_extension @var{name}
 362 Add or remove an architecture extension to the target architecture.  Valid
 363 values for @var{name} are the same as those accepted as architectural
 364 extensions by the @option{-mcpu} command-line option.
 365
 366 @code{.arch_extension} may be used multiple times to add or remove extensions
 367 incrementally to the architecture being compiled for.
 368
 369 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
 370
 371 @cindex @code{.bss} directive, AArch64
 372 @item .bss
 373 This directive switches to the @code{.bss} section.
 374
 375 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
 376
 377 @cindex @code{.cpu} directive, AArch64
 378 @item .cpu @var{name}
 379 Set the target processor.  Valid values for @var{name} are the same as
 380 those accepted by the @option{-mcpu=} command-line option.
 381
 382 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
 383
 384 @cindex @code{.dword} directive, AArch64
 385 @item .dword @var{expressions}
 386 The @code{.dword} directive produces 64 bit values.
 387
 388 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
 389
 390 @cindex @code{.even} directive, AArch64
 391 @item .even
 392 The @code{.even} directive aligns the output on the next even byte
 393 boundary.
 394
 395 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
 396
 397 @cindex @code{.float16} directive, AArch64
 398 @item .float16 @var{value [,...,value_n]}
 399 Place the half precision floating point representation of one or more
 400 floating-point values into the current section.
 401 The format used to encode the floating point values is always the
 402 IEEE 754-2008 half precision floating point format.
 403
 404 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
 405 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
 406 @c IIIIIIIIIIIIIIIIIIIIIIIIII
 407
 408 @cindex @code{.inst} directive, AArch64
 409 @item .inst @var{expressions}
 410 Inserts the expressions into the output as if they were instructions,
 411 rather than data.
 412
 413 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
 414 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
 415 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
 416
 417 @cindex @code{.ltorg} directive, AArch64
 418 @item .ltorg
 419 This directive causes the current contents of the literal pool to be
 420 dumped into the current section (which is assumed to be the .text
 421 section) at the current location (aligned to a word boundary).
 422 GAS maintains a separate literal pool for each section and each
 423 sub-section.  The @code{.ltorg} directive will only affect the literal
 424 pool of the current section and sub-section.  At the end of assembly
 425 all remaining, un-empty literal pools will automatically be dumped.
 426
 427 Note - older versions of GAS would dump the current literal
 428 pool any time a section change occurred.  This is no longer done, since
 429 it prevents accurate control of the placement of literal pools.
 430
 431 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
 432
 433 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
 434 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
 435
 436 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
 437
 438 @cindex @code{.pool} directive, AArch64
 439 @item .pool
 440 This is a synonym for .ltorg.
 441
 442 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
 443 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
 444
 445 @cindex @code{.req} directive, AArch64
 446 @item @var{name} .req @var{register name}
 447 This creates an alias for @var{register name} called @var{name}.  For
 448 example:
 449
 450 @smallexample
 451         foo .req w0
 452 @end smallexample
 453
 454 ip0, ip1, lr and fp are automatically defined to
 455 alias to X16, X17, X30 and X29 respectively.
 456
 457 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
 458
 459 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
 460
 461 @cindex @code{.tlsdescadd} directive, AArch64
 462 @item   @code{.tlsdescadd}
 463 Emits a TLSDESC_ADD reloc on the next instruction.
 464
 465 @cindex @code{.tlsdesccall} directive, AArch64
 466 @item   @code{.tlsdesccall}
 467 Emits a TLSDESC_CALL reloc on the next instruction.
 468
 469 @cindex @code{.tlsdescldr} directive, AArch64
 470 @item   @code{.tlsdescldr}
 471 Emits a TLSDESC_LDR reloc on the next instruction.
 472
 473 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
 474
 475 @cindex @code{.unreq} directive, AArch64
 476 @item .unreq @var{alias-name}
 477 This undefines a register alias which was previously defined using the
 478 @code{req} directive.  For example:
 479
 480 @smallexample
 481         foo .req w0
 482         .unreq foo
 483 @end smallexample
 484
 485 An error occurs if the name is undefined.  Note - this pseudo op can
 486 be used to delete builtin in register name aliases (eg 'w0').  This
 487 should only be done if it is really necessary.
 488
 489 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
 490
 491 @cindex @code{.variant_pcs} directive, AArch64
 492 @item .variant_pcs @var{symbol}
 493 This directive marks @var{symbol} referencing a function that may
 494 follow a variant procedure call standard with different register
 495 usage convention from the base procedure call standard.
 496
 497 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
 498 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
 499
 500 @cindex @code{.xword} directive, AArch64
 501 @item .xword @var{expressions}
 502 The @code{.xword} directive produces 64 bit values.  This is the same
 503 as the @code{.dword} directive.
 504
 505 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
 506 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
 507
 508 @cindex @code{.cfi_b_key_frame} directive, AArch64
 509 @item   @code{.cfi_b_key_frame}
 510 The @code{.cfi_b_key_frame} directive inserts a 'B' character into the CIE
 511 corresponding to the current frame's FDE, meaning that its return address has
 512 been signed with the B-key.  If two frames are signed with differing keys then
 513 they will not share the same CIE.  This information is intended to be used by
 514 the stack unwinder in order to properly authenticate return addresses.
 515
 516 @end table
 517
 518 @node AArch64 Opcodes
 519 @section Opcodes
 520
 521 @cindex AArch64 opcodes
 522 @cindex opcodes for AArch64
 523 GAS implements all the standard AArch64 opcodes.  It also
 524 implements several pseudo opcodes, including several synthetic load
 525 instructions.
 526
 527 @table @code
 528
 529 @cindex @code{LDR reg,=<expr>} pseudo op, AArch64
 530 @item LDR =
 531 @smallexample
 532   ldr <register> , =<expression>
 533 @end smallexample
 534
 535 The constant expression will be placed into the nearest literal pool (if it not
 536 already there) and a PC-relative LDR instruction will be generated.
 537
 538 @end table
 539
 540 For more information on the AArch64 instruction set and assembly language
 541 notation, see @samp{ARMv8 Instruction Set Overview} available at
 542 @uref{http://infocenter.arm.com}.
 543
 544
 545 @node AArch64 Mapping Symbols
 546 @section Mapping Symbols
 547
 548 The AArch64 ELF specification requires that special symbols be inserted
 549 into object files to mark certain features:
 550
 551 @table @code
 552
 553 @cindex @code{$x}
 554 @item $x
 555 At the start of a region of code containing AArch64 instructions.
 556
 557 @cindex @code{$d}
 558 @item $d
 559 At the start of a region of data.
 560
 561 @end table