gas/doc/c-aarch64.texi

   1 @c Copyright (C) 2009-2015 Free Software Foundation, Inc.
   2 @c Contributed by ARM Ltd.
   3 @c This is part of the GAS manual.
   4 @c For copying conditions, see the file as.texinfo.
   5 @c man end
   6
   7 @ifset GENERIC
   8 @page
   9 @node AArch64-Dependent
  10 @chapter AArch64 Dependent Features
  11 @end ifset
  12
  13 @ifclear GENERIC
  14 @node Machine Dependencies
  15 @chapter AArch64 Dependent Features
  16 @end ifclear
  17
  18 @cindex AArch64 support
  19 @menu
  20 * AArch64 Options::              Options
  21 * AArch64 Extensions::           Extensions
  22 * AArch64 Syntax::               Syntax
  23 * AArch64 Floating Point::       Floating Point
  24 * AArch64 Directives::           AArch64 Machine Directives
  25 * AArch64 Opcodes::              Opcodes
  26 * AArch64 Mapping Symbols::      Mapping Symbols
  27 @end menu
  28
  29 @node AArch64 Options
  30 @section Options
  31 @cindex AArch64 options (none)
  32 @cindex options for AArch64 (none)
  33
  34 @c man begin OPTIONS
  35 @table @gcctabopt
  36
  37 @cindex @option{-EB} command line option, AArch64
  38 @item -EB
  39 This option specifies that the output generated by the assembler should
  40 be marked as being encoded for a big-endian processor.
  41
  42 @cindex @option{-EL} command line option, AArch64
  43 @item -EL
  44 This option specifies that the output generated by the assembler should
  45 be marked as being encoded for a little-endian processor.
  46
  47 @cindex @option{-mabi=} command line option, AArch64
  48 @item -mabi=@var{abi}
  49 Specify which ABI the source code uses.  The recognized arguments
  50 are: @code{ilp32} and @code{lp64}, which decides the generated object
  51 file in ELF32 and ELF64 format respectively.  The default is @code{lp64}.
  52
  53 @cindex @option{-mcpu=} command line option, AArch64
  54 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
  55 This option specifies the target processor.  The assembler will issue an error
  56 message if an attempt is made to assemble an instruction which will not execute
  57 on the target processor.  The following processor names are recognized:
  58 @code{cortex-a53},
  59 @code{cortex-a57},
  60 @code{cortex-a72},
  61 @code{exynos-m1},
  62 @code{thunderx},
  63 @code{xgene1}
  64 and
  65 @code{xgene2}.
  66 The special name @code{all} may be used to allow the assembler to accept
  67 instructions valid for any supported processor, including all optional
  68 extensions.
  69
  70 In addition to the basic instruction set, the assembler can be told to
  71 accept, or restrict, various extension mnemonics that extend the
  72 processor.  @xref{AArch64 Extensions}.
  73
  74 If some implementations of a particular processor can have an
  75 extension, then then those extensions are automatically enabled.
  76 Consequently, you will not normally have to specify any additional
  77 extensions.
  78
  79 @cindex @option{-march=} command line option, AArch64
  80 @item -march=@var{architecture}[+@var{extension}@dots{}]
  81 This option specifies the target architecture.  The assembler will
  82 issue an error message if an attempt is made to assemble an
  83 instruction which will not execute on the target architecture.  The
  84 only value for @var{architecture} is @code{armv8-a}.
  85
  86 If both @option{-mcpu} and @option{-march} are specified, the
  87 assembler will use the setting for @option{-mcpu}.  If neither are
  88 specified, the assembler will default to @option{-mcpu=all}.
  89
  90 The architecture option can be extended with the same instruction set
  91 extension options as the @option{-mcpu} option.  Unlike
  92 @option{-mcpu}, extensions are not always enabled by default,
  93 @xref{AArch64 Extensions}.
  94
  95 @cindex @code{-mverbose-error} command line option, AArch64
  96 @item -mverbose-error
  97 This option enables verbose error messages for AArch64 gas.  This option
  98 is enabled by default.
  99
 100 @cindex @code{-mno-verbose-error} command line option, AArch64
 101 @item -mno-verbose-error
 102 This option disables verbose error messages in AArch64 gas.
 103
 104 @end table
 105 @c man end
 106
 107 @node AArch64 Extensions
 108 @section Architecture Extensions
 109
 110 The table below lists the permitted architecture extensions that are
 111 supported by the assembler and the conditions under which they are
 112 automatically enabled.
 113
 114 Multiple extensions may be specified, separated by a @code{+}.
 115 Extension mnemonics may also be removed from those the assembler
 116 accepts.  This is done by prepending @code{no} to the option that adds
 117 the extension.  Extensions that are removed must be listed after all
 118 extensions that have been added.
 119
 120 Enabling an extension that requires other extensions will
 121 automatically cause those extensions to be enabled.  Similarly,
 122 disabling an extension that is required by other extensions will
 123 automatically cause those extensions to be disabled.
 124
 125 @multitable @columnfractions .12 .17 .17 .54
 126 @headitem Extension @tab Minimum Architecture @tab Enabled by default
 127  @tab Description
 128 @item @code{crc} @tab ARMv8-A @tab No
 129  @tab Enable CRC instructions.
 130 @item @code{crypto} @tab ARMv8-A @tab No
 131  @tab Enable cryptographic extensions.  This implies @code{fp} and @code{simd}.
 132 @item @code{fp} @tab ARMv8-A @tab ARMv8-A or later
 133  @tab Enable floating-point extensions.
 134 @item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
 135  @tab Enable Advanced SIMD extensions.  This implies @code{fp}.
 136 @end multitable
 137
 138 @node AArch64 Syntax
 139 @section Syntax
 140 @menu
 141 * AArch64-Chars::                Special Characters
 142 * AArch64-Regs::                 Register Names
 143 * AArch64-Relocations::      Relocations
 144 @end menu
 145
 146 @node AArch64-Chars
 147 @subsection Special Characters
 148
 149 @cindex line comment character, AArch64
 150 @cindex AArch64 line comment character
 151 The presence of a @samp{//} on a line indicates the start of a comment
 152 that extends to the end of the current line.  If a @samp{#} appears as
 153 the first character of a line, the whole line is treated as a comment.
 154
 155 @cindex line separator, AArch64
 156 @cindex statement separator, AArch64
 157 @cindex AArch64 line separator
 158 The @samp{;} character can be used instead of a newline to separate
 159 statements.
 160
 161 @cindex immediate character, AArch64
 162 @cindex AArch64 immediate character
 163 The @samp{#} can be optionally used to indicate immediate operands.
 164
 165 @node AArch64-Regs
 166 @subsection Register Names
 167
 168 @cindex AArch64 register names
 169 @cindex register names, AArch64
 170 Please refer to the section @samp{4.4 Register Names} of
 171 @samp{ARMv8 Instruction Set Overview}, which is available at
 172 @uref{http://infocenter.arm.com}.
 173
 174 @node AArch64-Relocations
 175 @subsection Relocations
 176
 177 @cindex relocations, AArch64
 178 @cindex AArch64 relocations
 179 @cindex MOVN, MOVZ and MOVK group relocations, AArch64
 180 Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated
 181 by prefixing the label with @samp{#:abs_g2:} etc.
 182 For example to load the 48-bit absolute address of @var{foo} into x0:
 183
 184 @smallexample
 185         movz x0, #:abs_g2:foo           // bits 32-47, overflow check
 186         movk x0, #:abs_g1_nc:foo        // bits 16-31, no overflow check
 187         movk x0, #:abs_g0_nc:foo        // bits  0-15, no overflow check
 188 @end smallexample
 189
 190 @cindex ADRP, ADD, LDR/STR group relocations, AArch64
 191 Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
 192 instructions can be generated by prefixing the label with
 193 @samp{:pg_hi21:} and @samp{#:lo12:} respectively.
 194
 195 For example to use 33-bit (+/-4GB) pc-relative addressing to
 196 load the address of @var{foo} into x0:
 197
 198 @smallexample
 199         adrp x0, :pg_hi21:foo
 200         add  x0, x0, #:lo12:foo
 201 @end smallexample
 202
 203 Or to load the value of @var{foo} into x0:
 204
 205 @smallexample
 206         adrp x0, :pg_hi21:foo
 207         ldr  x0, [x0, #:lo12:foo]
 208 @end smallexample
 209
 210 Note that @samp{:pg_hi21:} is optional.
 211
 212 @smallexample
 213         adrp x0, foo
 214 @end smallexample
 215
 216 is equivalent to
 217
 218 @smallexample
 219         adrp x0, :pg_hi21:foo
 220 @end smallexample
 221
 222 @node AArch64 Floating Point
 223 @section Floating Point
 224
 225 @cindex floating point, AArch64 (@sc{ieee})
 226 @cindex AArch64 floating point (@sc{ieee})
 227 The AArch64 architecture uses @sc{ieee} floating-point numbers.
 228
 229 @node AArch64 Directives
 230 @section AArch64 Machine Directives
 231
 232 @cindex machine directives, AArch64
 233 @cindex AArch64 machine directives
 234 @table @code
 235
 236 @c AAAAAAAAAAAAAAAAAAAAAAAAA
 237
 238 @cindex @code{.arch} directive, AArch64
 239 @item .arch @var{name}
 240 Select the target architecture.  Valid values for @var{name} are the same as
 241 for the @option{-march} commandline option.
 242
 243 Specifying @code{.arch} clears any previously selected architecture
 244 extensions.
 245
 246 @cindex @code{.arch_extension} directive, AArch64
 247 @item .arch_extension @var{name}
 248 Add or remove an architecture extension to the target architecture.  Valid
 249 values for @var{name} are the same as those accepted as architectural
 250 extensions by the @option{-mcpu} commandline option.
 251
 252 @code{.arch_extension} may be used multiple times to add or remove extensions
 253 incrementally to the architecture being compiled for.
 254
 255 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
 256
 257 @cindex @code{.bss} directive, AArch64
 258 @item .bss
 259 This directive switches to the @code{.bss} section.
 260
 261 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
 262 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
 263 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
 264 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
 265 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
 266 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
 267 @c IIIIIIIIIIIIIIIIIIIIIIIIII
 268 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
 269 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
 270 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
 271
 272 @cindex @code{.ltorg} directive, AArch64
 273 @item .ltorg
 274 This directive causes the current contents of the literal pool to be
 275 dumped into the current section (which is assumed to be the .text
 276 section) at the current location (aligned to a word boundary).
 277 GAS maintains a separate literal pool for each section and each
 278 sub-section.  The @code{.ltorg} directive will only affect the literal
 279 pool of the current section and sub-section.  At the end of assembly
 280 all remaining, un-empty literal pools will automatically be dumped.
 281
 282 Note - older versions of GAS would dump the current literal
 283 pool any time a section change occurred.  This is no longer done, since
 284 it prevents accurate control of the placement of literal pools.
 285
 286 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
 287
 288 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
 289 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
 290
 291 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
 292
 293 @cindex @code{.pool} directive, AArch64
 294 @item .pool
 295 This is a synonym for .ltorg.
 296
 297 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
 298 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
 299
 300 @cindex @code{.req} directive, AArch64
 301 @item @var{name} .req @var{register name}
 302 This creates an alias for @var{register name} called @var{name}.  For
 303 example:
 304
 305 @smallexample
 306         foo .req w0
 307 @end smallexample
 308
 309 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
 310
 311 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
 312
 313 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
 314
 315 @cindex @code{.unreq} directive, AArch64
 316 @item .unreq @var{alias-name}
 317 This undefines a register alias which was previously defined using the
 318 @code{req} directive.  For example:
 319
 320 @smallexample
 321         foo .req w0
 322         .unreq foo
 323 @end smallexample
 324
 325 An error occurs if the name is undefined.  Note - this pseudo op can
 326 be used to delete builtin in register name aliases (eg 'w0').  This
 327 should only be done if it is really necessary.
 328
 329 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
 330
 331 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
 332 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
 333 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
 334 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
 335
 336 @end table
 337
 338 @node AArch64 Opcodes
 339 @section Opcodes
 340
 341 @cindex AArch64 opcodes
 342 @cindex opcodes for AArch64
 343 GAS implements all the standard AArch64 opcodes.  It also
 344 implements several pseudo opcodes, including several synthetic load
 345 instructions.
 346
 347 @table @code
 348
 349 @cindex @code{LDR reg,=<expr>} pseudo op, AArch64
 350 @item LDR =
 351 @smallexample
 352   ldr <register> , =<expression>
 353 @end smallexample
 354
 355 The constant expression will be placed into the nearest literal pool (if it not
 356 already there) and a PC-relative LDR instruction will be generated.
 357
 358 @end table
 359
 360 For more information on the AArch64 instruction set and assembly language
 361 notation, see @samp{ARMv8 Instruction Set Overview} available at
 362 @uref{http://infocenter.arm.com}.
 363
 364
 365 @node AArch64 Mapping Symbols
 366 @section Mapping Symbols
 367
 368 The AArch64 ELF specification requires that special symbols be inserted
 369 into object files to mark certain features:
 370
 371 @table @code
 372
 373 @cindex @code{$x}
 374 @item $x
 375 At the start of a region of code containing AArch64 instructions.
 376
 377 @cindex @code{$d}
 378 @item $d
 379 At the start of a region of data.
 380
 381 @end table