gas/doc/c-aarch64.texi

   1 @c Copyright (C) 2009-2020 Free Software Foundation, Inc.
   2 @c Contributed by ARM Ltd.
   3 @c This is part of the GAS manual.
   4 @c For copying conditions, see the file as.texinfo.
   5 @c man end
   6
   7 @ifset GENERIC
   8 @page
   9 @node AArch64-Dependent
  10 @chapter AArch64 Dependent Features
  11 @end ifset
  12
  13 @ifclear GENERIC
  14 @node Machine Dependencies
  15 @chapter AArch64 Dependent Features
  16 @end ifclear
  17
  18 @cindex AArch64 support
  19 @menu
  20 * AArch64 Options::              Options
  21 * AArch64 Extensions::           Extensions
  22 * AArch64 Syntax::               Syntax
  23 * AArch64 Floating Point::       Floating Point
  24 * AArch64 Directives::           AArch64 Machine Directives
  25 * AArch64 Opcodes::              Opcodes
  26 * AArch64 Mapping Symbols::      Mapping Symbols
  27 @end menu
  28
  29 @node AArch64 Options
  30 @section Options
  31 @cindex AArch64 options (none)
  32 @cindex options for AArch64 (none)
  33
  34 @c man begin OPTIONS
  35 @table @gcctabopt
  36
  37 @cindex @option{-EB} command-line option, AArch64
  38 @item -EB
  39 This option specifies that the output generated by the assembler should
  40 be marked as being encoded for a big-endian processor.
  41
  42 @cindex @option{-EL} command-line option, AArch64
  43 @item -EL
  44 This option specifies that the output generated by the assembler should
  45 be marked as being encoded for a little-endian processor.
  46
  47 @cindex @option{-mabi=} command-line option, AArch64
  48 @item -mabi=@var{abi}
  49 Specify which ABI the source code uses.  The recognized arguments
  50 are: @code{ilp32} and @code{lp64}, which decides the generated object
  51 file in ELF32 and ELF64 format respectively.  The default is @code{lp64}.
  52
  53 @cindex @option{-mcpu=} command-line option, AArch64
  54 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
  55 This option specifies the target processor.  The assembler will issue an error
  56 message if an attempt is made to assemble an instruction which will not execute
  57 on the target processor.  The following processor names are recognized:
  58 @code{cortex-a34},
  59 @code{cortex-a35},
  60 @code{cortex-a53},
  61 @code{cortex-a55},
  62 @code{cortex-a57},
  63 @code{cortex-a65},
  64 @code{cortex-a65ae},
  65 @code{cortex-a72},
  66 @code{cortex-a73},
  67 @code{cortex-a75},
  68 @code{cortex-a76},
  69 @code{cortex-a76ae},
  70 @code{cortex-a77},
  71 @code{ares},
  72 @code{exynos-m1},
  73 @code{falkor},
  74 @code{neoverse-n1},
  75 @code{neoverse-e1},
  76 @code{neoverse-v1},
  77 @code{qdf24xx},
  78 @code{saphira},
  79 @code{thunderx},
  80 @code{vulcan},
  81 @code{xgene1}
  82 @code{xgene2},
  83 @code{cortex-r82},
  84 and
  85 @code{cortex-x1}.
  86 The special name @code{all} may be used to allow the assembler to accept
  87 instructions valid for any supported processor, including all optional
  88 extensions.
  89
  90 In addition to the basic instruction set, the assembler can be told to
  91 accept, or restrict, various extension mnemonics that extend the
  92 processor.  @xref{AArch64 Extensions}.
  93
  94 If some implementations of a particular processor can have an
  95 extension, then then those extensions are automatically enabled.
  96 Consequently, you will not normally have to specify any additional
  97 extensions.
  98
  99 @cindex @option{-march=} command-line option, AArch64
 100 @item -march=@var{architecture}[+@var{extension}@dots{}]
 101 This option specifies the target architecture.  The assembler will
 102 issue an error message if an attempt is made to assemble an
 103 instruction which will not execute on the target architecture.  The
 104 following architecture names are recognized: @code{armv8-a},
 105 @code{armv8.1-a}, @code{armv8.2-a}, @code{armv8.3-a}, @code{armv8.4-a}
 106 @code{armv8.5-a}, @code{armv8.6-a}, and @code{armv8-r}.
 107
 108 If both @option{-mcpu} and @option{-march} are specified, the
 109 assembler will use the setting for @option{-mcpu}.  If neither are
 110 specified, the assembler will default to @option{-mcpu=all}.
 111
 112 The architecture option can be extended with the same instruction set
 113 extension options as the @option{-mcpu} option.  Unlike
 114 @option{-mcpu}, extensions are not always enabled by default,
 115 @xref{AArch64 Extensions}.
 116
 117 @cindex @code{-mverbose-error} command-line option, AArch64
 118 @item -mverbose-error
 119 This option enables verbose error messages for AArch64 gas.  This option
 120 is enabled by default.
 121
 122 @cindex @code{-mno-verbose-error} command-line option, AArch64
 123 @item -mno-verbose-error
 124 This option disables verbose error messages in AArch64 gas.
 125
 126 @end table
 127 @c man end
 128
 129 @node AArch64 Extensions
 130 @section Architecture Extensions
 131
 132 The table below lists the permitted architecture extensions that are
 133 supported by the assembler and the conditions under which they are
 134 automatically enabled.
 135
 136 Multiple extensions may be specified, separated by a @code{+}.
 137 Extension mnemonics may also be removed from those the assembler
 138 accepts.  This is done by prepending @code{no} to the option that adds
 139 the extension.  Extensions that are removed must be listed after all
 140 extensions that have been added.
 141
 142 Enabling an extension that requires other extensions will
 143 automatically cause those extensions to be enabled.  Similarly,
 144 disabling an extension that is required by other extensions will
 145 automatically cause those extensions to be disabled.
 146
 147 @multitable @columnfractions .12 .17 .17 .54
 148 @headitem Extension @tab Minimum Architecture @tab Enabled by default
 149  @tab Description
 150 @item @code{i8mm} @tab ARMv8.2-A @tab ARMv8.6-A or later
 151  @tab Enable Int8 Matrix Multiply extension.
 152 @item @code{f32mm} @tab ARMv8.2-A @tab No
 153  @tab Enable F32 Matrix Multiply extension.
 154 @item @code{f64mm} @tab ARMv8.2-A @tab No
 155  @tab Enable F64 Matrix Multiply extension.
 156 @item @code{bf16} @tab ARMv8.2-A @tab ARMv8.6-A or later
 157  @tab Enable BFloat16 extension.
 158 @item @code{compnum} @tab ARMv8.2-A @tab ARMv8.3-A or later
 159  @tab Enable the complex number SIMD extensions.  This implies
 160  @code{fp16} and @code{simd}.
 161 @item @code{crc} @tab ARMv8-A @tab ARMv8.1-A or later
 162  @tab Enable CRC instructions.
 163 @item @code{crypto} @tab ARMv8-A @tab No
 164  @tab Enable cryptographic extensions.  This implies @code{fp}, @code{simd}, @code{aes} and @code{sha2}.
 165 @item @code{aes} @tab ARMv8-A @tab No
 166  @tab Enable the AES cryptographic extensions. This implies @code{fp} and @code{simd}.
 167 @item @code{sha2} @tab ARMv8-A @tab No
 168  @tab Enable the SHA2 cryptographic extensions. This implies @code{fp} and @code{simd}.
 169 @item @code{sha3} @tab ARMv8.2-A @tab No
 170  @tab Enable the ARMv8.2-A SHA2 and SHA3 cryptographic extensions. This implies @code{fp}, @code{simd} and @code{sha2}.
 171 @item @code{sm4} @tab ARMv8.2-A @tab No
 172  @tab Enable the ARMv8.2-A SM3 and SM4 cryptographic extensions. This implies @code{fp} and @code{simd}.
 173 @item @code{fp} @tab ARMv8-A @tab ARMv8-A or later
 174  @tab Enable floating-point extensions.
 175 @item @code{fp16} @tab ARMv8.2-A @tab ARMv8.2-A or later
 176  @tab Enable ARMv8.2 16-bit floating-point support.  This implies
 177  @code{fp}.
 178 @item @code{lor} @tab ARMv8-A @tab ARMv8.1-A or later
 179  @tab Enable Limited Ordering Regions extensions.
 180 @item @code{lse} @tab ARMv8-A @tab ARMv8.1-A or later
 181  @tab Enable Large System extensions.
 182 @item @code{pan} @tab ARMv8-A @tab ARMv8.1-A or later
 183  @tab Enable Privileged Access Never support.
 184 @item @code{profile} @tab ARMv8.2-A @tab No
 185  @tab Enable statistical profiling extensions.
 186 @item @code{ras} @tab ARMv8-A @tab ARMv8.2-A or later
 187  @tab Enable the Reliability, Availability and Serviceability
 188  extension.
 189 @item @code{rcpc} @tab ARMv8.2-A @tab ARMv8.3-A or later
 190  @tab Enable the weak release consistency extension.
 191 @item @code{rdma} @tab ARMv8-A @tab ARMv8.1-A or later
 192  @tab Enable ARMv8.1 Advanced SIMD extensions.  This implies @code{simd}.
 193 @item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
 194  @tab Enable Advanced SIMD extensions.  This implies @code{fp}.
 195 @item @code{sve} @tab ARMv8.2-A @tab No
 196  @tab Enable the Scalable Vector Extensions.  This implies @code{fp16},
 197  @code{simd} and @code{compnum}.
 198 @item @code{dotprod} @tab ARMv8.2-A @tab ARMv8.4-A or later
 199  @tab Enable the Dot Product extension.  This implies @code{simd}.
 200 @item @code{fp16fml} @tab ARMv8.2-A @tab ARMv8.4-A or later
 201  @tab Enable ARMv8.2 16-bit floating-point multiplication variant support.
 202  This implies @code{fp16}.
 203 @item @code{sb} @tab ARMv8-A @tab ARMv8.5-A or later
 204  @tab Enable the speculation barrier instruction sb.
 205 @item @code{predres} @tab ARMv8-A @tab ARMv8.5-A or later
 206  @tab Enable the Execution and Data and Prediction instructions.
 207 @item @code{rng} @tab ARMv8.5-A @tab No
 208  @tab Enable ARMv8.5-A random number instructions.
 209 @item @code{ssbs} @tab ARMv8-A @tab ARMv8.5-A or later
 210  @tab Enable Speculative Store Bypassing Safe state read and write.
 211 @item @code{memtag} @tab ARMv8.5-A @tab No
 212  @tab Enable ARMv8.5-A Memory Tagging Extensions.
 213 @item @code{tme} @tab ARMv8-A @tab No
 214  @tab Enable Transactional Memory Extensions.
 215 @item @code{sve2} @tab ARMv8-A @tab No
 216  @tab Enable the SVE2 Extension.
 217 @item @code{sve2-bitperm} @tab ARMv8-A @tab No
 218  @tab Enable SVE2 BITPERM Extension.
 219 @item @code{sve2-sm4} @tab ARMv8-A @tab No
 220  @tab Enable SVE2 SM4 Extension.
 221 @item @code{sve2-aes} @tab ARMv8-A @tab No
 222  @tab Enable SVE2 AES Extension.  This also enables the .Q->.B form of the
 223  @code{pmullt} and @code{pmullb} instructions.
 224 @item @code{sve2-sha3} @tab ARMv8-A @tab No
 225  @tab Enable SVE2 SHA3 Extension.
 226 @end multitable
 227
 228 @node AArch64 Syntax
 229 @section Syntax
 230 @menu
 231 * AArch64-Chars::                Special Characters
 232 * AArch64-Regs::                 Register Names
 233 * AArch64-Relocations::      Relocations
 234 @end menu
 235
 236 @node AArch64-Chars
 237 @subsection Special Characters
 238
 239 @cindex line comment character, AArch64
 240 @cindex AArch64 line comment character
 241 The presence of a @samp{//} on a line indicates the start of a comment
 242 that extends to the end of the current line.  If a @samp{#} appears as
 243 the first character of a line, the whole line is treated as a comment.
 244
 245 @cindex line separator, AArch64
 246 @cindex statement separator, AArch64
 247 @cindex AArch64 line separator
 248 The @samp{;} character can be used instead of a newline to separate
 249 statements.
 250
 251 @cindex immediate character, AArch64
 252 @cindex AArch64 immediate character
 253 The @samp{#} can be optionally used to indicate immediate operands.
 254
 255 @node AArch64-Regs
 256 @subsection Register Names
 257
 258 @cindex AArch64 register names
 259 @cindex register names, AArch64
 260 Please refer to the section @samp{4.4 Register Names} of
 261 @samp{ARMv8 Instruction Set Overview}, which is available at
 262 @uref{http://infocenter.arm.com}.
 263
 264 @node AArch64-Relocations
 265 @subsection Relocations
 266
 267 @cindex relocations, AArch64
 268 @cindex AArch64 relocations
 269 @cindex MOVN, MOVZ and MOVK group relocations, AArch64
 270 Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated
 271 by prefixing the label with @samp{#:abs_g2:} etc.
 272 For example to load the 48-bit absolute address of @var{foo} into x0:
 273
 274 @smallexample
 275         movz x0, #:abs_g2:foo           // bits 32-47, overflow check
 276         movk x0, #:abs_g1_nc:foo        // bits 16-31, no overflow check
 277         movk x0, #:abs_g0_nc:foo        // bits  0-15, no overflow check
 278 @end smallexample
 279
 280 @cindex ADRP, ADD, LDR/STR group relocations, AArch64
 281 Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
 282 instructions can be generated by prefixing the label with
 283 @samp{:pg_hi21:} and @samp{#:lo12:} respectively.
 284
 285 For example to use 33-bit (+/-4GB) pc-relative addressing to
 286 load the address of @var{foo} into x0:
 287
 288 @smallexample
 289         adrp x0, :pg_hi21:foo
 290         add  x0, x0, #:lo12:foo
 291 @end smallexample
 292
 293 Or to load the value of @var{foo} into x0:
 294
 295 @smallexample
 296         adrp x0, :pg_hi21:foo
 297         ldr  x0, [x0, #:lo12:foo]
 298 @end smallexample
 299
 300 Note that @samp{:pg_hi21:} is optional.
 301
 302 @smallexample
 303         adrp x0, foo
 304 @end smallexample
 305
 306 is equivalent to
 307
 308 @smallexample
 309         adrp x0, :pg_hi21:foo
 310 @end smallexample
 311
 312 @node AArch64 Floating Point
 313 @section Floating Point
 314
 315 @cindex floating point, AArch64 (@sc{ieee})
 316 @cindex AArch64 floating point (@sc{ieee})
 317 The AArch64 architecture uses @sc{ieee} floating-point numbers.
 318
 319 @node AArch64 Directives
 320 @section AArch64 Machine Directives
 321
 322 @cindex machine directives, AArch64
 323 @cindex AArch64 machine directives
 324 @table @code
 325
 326 @c AAAAAAAAAAAAAAAAAAAAAAAAA
 327
 328 @cindex @code{.arch} directive, AArch64
 329 @item .arch @var{name}
 330 Select the target architecture.  Valid values for @var{name} are the same as
 331 for the @option{-march} command-line option.
 332
 333 Specifying @code{.arch} clears any previously selected architecture
 334 extensions.
 335
 336 @cindex @code{.arch_extension} directive, AArch64
 337 @item .arch_extension @var{name}
 338 Add or remove an architecture extension to the target architecture.  Valid
 339 values for @var{name} are the same as those accepted as architectural
 340 extensions by the @option{-mcpu} command-line option.
 341
 342 @code{.arch_extension} may be used multiple times to add or remove extensions
 343 incrementally to the architecture being compiled for.
 344
 345 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
 346
 347 @cindex @code{.bss} directive, AArch64
 348 @item .bss
 349 This directive switches to the @code{.bss} section.
 350
 351 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
 352
 353 @cindex @code{.cpu} directive, AArch64
 354 @item .cpu @var{name}
 355 Set the target processor.  Valid values for @var{name} are the same as
 356 those accepted by the @option{-mcpu=} command-line option.
 357
 358 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
 359
 360 @cindex @code{.dword} directive, AArch64
 361 @item .dword @var{expressions}
 362 The @code{.dword} directive produces 64 bit values.
 363
 364 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
 365
 366 @cindex @code{.even} directive, AArch64
 367 @item .even
 368 The @code{.even} directive aligns the output on the next even byte
 369 boundary.
 370
 371 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
 372
 373 @cindex @code{.float16} directive, AArch64
 374 @item .float16 @var{value [,...,value_n]}
 375 Place the half precision floating point representation of one or more
 376 floating-point values into the current section.
 377 The format used to encode the floating point values is always the
 378 IEEE 754-2008 half precision floating point format.
 379
 380 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
 381 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
 382 @c IIIIIIIIIIIIIIIIIIIIIIIIII
 383
 384 @cindex @code{.inst} directive, AArch64
 385 @item .inst @var{expressions}
 386 Inserts the expressions into the output as if they were instructions,
 387 rather than data.
 388
 389 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
 390 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
 391 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
 392
 393 @cindex @code{.ltorg} directive, AArch64
 394 @item .ltorg
 395 This directive causes the current contents of the literal pool to be
 396 dumped into the current section (which is assumed to be the .text
 397 section) at the current location (aligned to a word boundary).
 398 GAS maintains a separate literal pool for each section and each
 399 sub-section.  The @code{.ltorg} directive will only affect the literal
 400 pool of the current section and sub-section.  At the end of assembly
 401 all remaining, un-empty literal pools will automatically be dumped.
 402
 403 Note - older versions of GAS would dump the current literal
 404 pool any time a section change occurred.  This is no longer done, since
 405 it prevents accurate control of the placement of literal pools.
 406
 407 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
 408
 409 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
 410 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
 411
 412 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
 413
 414 @cindex @code{.pool} directive, AArch64
 415 @item .pool
 416 This is a synonym for .ltorg.
 417
 418 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
 419 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
 420
 421 @cindex @code{.req} directive, AArch64
 422 @item @var{name} .req @var{register name}
 423 This creates an alias for @var{register name} called @var{name}.  For
 424 example:
 425
 426 @smallexample
 427         foo .req w0
 428 @end smallexample
 429
 430 ip0, ip1, lr and fp are automatically defined to
 431 alias to X16, X17, X30 and X29 respectively.
 432
 433 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
 434
 435 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
 436
 437 @cindex @code{.tlsdescadd} directive, AArch64
 438 @item   @code{.tlsdescadd}
 439 Emits a TLSDESC_ADD reloc on the next instruction.
 440
 441 @cindex @code{.tlsdesccall} directive, AArch64
 442 @item   @code{.tlsdesccall}
 443 Emits a TLSDESC_CALL reloc on the next instruction.
 444
 445 @cindex @code{.tlsdescldr} directive, AArch64
 446 @item   @code{.tlsdescldr}
 447 Emits a TLSDESC_LDR reloc on the next instruction.
 448
 449 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
 450
 451 @cindex @code{.unreq} directive, AArch64
 452 @item .unreq @var{alias-name}
 453 This undefines a register alias which was previously defined using the
 454 @code{req} directive.  For example:
 455
 456 @smallexample
 457         foo .req w0
 458         .unreq foo
 459 @end smallexample
 460
 461 An error occurs if the name is undefined.  Note - this pseudo op can
 462 be used to delete builtin in register name aliases (eg 'w0').  This
 463 should only be done if it is really necessary.
 464
 465 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
 466
 467 @cindex @code{.variant_pcs} directive, AArch64
 468 @item .variant_pcs @var{symbol}
 469 This directive marks @var{symbol} referencing a function that may
 470 follow a variant procedure call standard with different register
 471 usage convention from the base procedure call standard.
 472
 473 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
 474 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
 475
 476 @cindex @code{.xword} directive, AArch64
 477 @item .xword @var{expressions}
 478 The @code{.xword} directive produces 64 bit values.  This is the same
 479 as the @code{.dword} directive.
 480
 481 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
 482 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
 483
 484 @cindex @code{.cfi_b_key_frame} directive, AArch64
 485 @item   @code{.cfi_b_key_frame}
 486 The @code{.cfi_b_key_frame} directive inserts a 'B' character into the CIE
 487 corresponding to the current frame's FDE, meaning that its return address has
 488 been signed with the B-key.  If two frames are signed with differing keys then
 489 they will not share the same CIE.  This information is intended to be used by
 490 the stack unwinder in order to properly authenticate return addresses.
 491
 492 @end table
 493
 494 @node AArch64 Opcodes
 495 @section Opcodes
 496
 497 @cindex AArch64 opcodes
 498 @cindex opcodes for AArch64
 499 GAS implements all the standard AArch64 opcodes.  It also
 500 implements several pseudo opcodes, including several synthetic load
 501 instructions.
 502
 503 @table @code
 504
 505 @cindex @code{LDR reg,=<expr>} pseudo op, AArch64
 506 @item LDR =
 507 @smallexample
 508   ldr <register> , =<expression>
 509 @end smallexample
 510
 511 The constant expression will be placed into the nearest literal pool (if it not
 512 already there) and a PC-relative LDR instruction will be generated.
 513
 514 @end table
 515
 516 For more information on the AArch64 instruction set and assembly language
 517 notation, see @samp{ARMv8 Instruction Set Overview} available at
 518 @uref{http://infocenter.arm.com}.
 519
 520
 521 @node AArch64 Mapping Symbols
 522 @section Mapping Symbols
 523
 524 The AArch64 ELF specification requires that special symbols be inserted
 525 into object files to mark certain features:
 526
 527 @table @code
 528
 529 @cindex @code{$x}
 530 @item $x
 531 At the start of a region of code containing AArch64 instructions.
 532
 533 @cindex @code{$d}
 534 @item $d
 535 At the start of a region of data.
 536
 537 @end table