gas/doc/c-aarch64.texi

   1 @c Copyright (C) 2009-2021 Free Software Foundation, Inc.
   2 @c Contributed by ARM Ltd.
   3 @c This is part of the GAS manual.
   4 @c For copying conditions, see the file as.texinfo.
   5 @c man end
   6
   7 @ifset GENERIC
   8 @page
   9 @node AArch64-Dependent
  10 @chapter AArch64 Dependent Features
  11 @end ifset
  12
  13 @ifclear GENERIC
  14 @node Machine Dependencies
  15 @chapter AArch64 Dependent Features
  16 @end ifclear
  17
  18 @cindex AArch64 support
  19 @menu
  20 * AArch64 Options::              Options
  21 * AArch64 Extensions::           Extensions
  22 * AArch64 Syntax::               Syntax
  23 * AArch64 Floating Point::       Floating Point
  24 * AArch64 Directives::           AArch64 Machine Directives
  25 * AArch64 Opcodes::              Opcodes
  26 * AArch64 Mapping Symbols::      Mapping Symbols
  27 @end menu
  28
  29 @node AArch64 Options
  30 @section Options
  31 @cindex AArch64 options (none)
  32 @cindex options for AArch64 (none)
  33
  34 @c man begin OPTIONS
  35 @table @gcctabopt
  36
  37 @cindex @option{-EB} command-line option, AArch64
  38 @item -EB
  39 This option specifies that the output generated by the assembler should
  40 be marked as being encoded for a big-endian processor.
  41
  42 @cindex @option{-EL} command-line option, AArch64
  43 @item -EL
  44 This option specifies that the output generated by the assembler should
  45 be marked as being encoded for a little-endian processor.
  46
  47 @cindex @option{-mabi=} command-line option, AArch64
  48 @item -mabi=@var{abi}
  49 Specify which ABI the source code uses.  The recognized arguments
  50 are: @code{ilp32} and @code{lp64}, which decides the generated object
  51 file in ELF32 and ELF64 format respectively.  The default is @code{lp64}.
  52
  53 @cindex @option{-mcpu=} command-line option, AArch64
  54 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
  55 This option specifies the target processor.  The assembler will issue an error
  56 message if an attempt is made to assemble an instruction which will not execute
  57 on the target processor.  The following processor names are recognized:
  58 @code{cortex-a34},
  59 @code{cortex-a35},
  60 @code{cortex-a53},
  61 @code{cortex-a55},
  62 @code{cortex-a57},
  63 @code{cortex-a65},
  64 @code{cortex-a65ae},
  65 @code{cortex-a72},
  66 @code{cortex-a73},
  67 @code{cortex-a75},
  68 @code{cortex-a76},
  69 @code{cortex-a76ae},
  70 @code{cortex-a77},
  71 @code{cortex-a78},
  72 @code{cortex-a78ae},
  73 @code{cortex-a78c},
  74 @code{cortex-a510},
  75 @code{cortex-a710},
  76 @code{ares},
  77 @code{exynos-m1},
  78 @code{falkor},
  79 @code{neoverse-n1},
  80 @code{neoverse-n2},
  81 @code{neoverse-e1},
  82 @code{neoverse-v1},
  83 @code{qdf24xx},
  84 @code{saphira},
  85 @code{thunderx},
  86 @code{vulcan},
  87 @code{xgene1}
  88 @code{xgene2},
  89 @code{cortex-r82},
  90 @code{cortex-x1},
  91 and
  92 @code{cortex-x2}.
  93 The special name @code{all} may be used to allow the assembler to accept
  94 instructions valid for any supported processor, including all optional
  95 extensions.
  96
  97 In addition to the basic instruction set, the assembler can be told to
  98 accept, or restrict, various extension mnemonics that extend the
  99 processor.  @xref{AArch64 Extensions}.
 100
 101 If some implementations of a particular processor can have an
 102 extension, then then those extensions are automatically enabled.
 103 Consequently, you will not normally have to specify any additional
 104 extensions.
 105
 106 @cindex @option{-march=} command-line option, AArch64
 107 @item -march=@var{architecture}[+@var{extension}@dots{}]
 108 This option specifies the target architecture.  The assembler will
 109 issue an error message if an attempt is made to assemble an
 110 instruction which will not execute on the target architecture.  The
 111 following architecture names are recognized: @code{armv8-a},
 112 @code{armv8.1-a}, @code{armv8.2-a}, @code{armv8.3-a}, @code{armv8.4-a}
 113 @code{armv8.5-a}, @code{armv8.6-a}, @code{armv8.7-a}, @code{armv8-r}, and
 114 @code{armv9-a}.
 115
 116 If both @option{-mcpu} and @option{-march} are specified, the
 117 assembler will use the setting for @option{-mcpu}.  If neither are
 118 specified, the assembler will default to @option{-mcpu=all}.
 119
 120 The architecture option can be extended with the same instruction set
 121 extension options as the @option{-mcpu} option.  Unlike
 122 @option{-mcpu}, extensions are not always enabled by default,
 123 @xref{AArch64 Extensions}.
 124
 125 @cindex @code{-mverbose-error} command-line option, AArch64
 126 @item -mverbose-error
 127 This option enables verbose error messages for AArch64 gas.  This option
 128 is enabled by default.
 129
 130 @cindex @code{-mno-verbose-error} command-line option, AArch64
 131 @item -mno-verbose-error
 132 This option disables verbose error messages in AArch64 gas.
 133
 134 @end table
 135 @c man end
 136
 137 @node AArch64 Extensions
 138 @section Architecture Extensions
 139
 140 The table below lists the permitted architecture extensions that are
 141 supported by the assembler and the conditions under which they are
 142 automatically enabled.
 143
 144 Multiple extensions may be specified, separated by a @code{+}.
 145 Extension mnemonics may also be removed from those the assembler
 146 accepts.  This is done by prepending @code{no} to the option that adds
 147 the extension.  Extensions that are removed must be listed after all
 148 extensions that have been added.
 149
 150 Enabling an extension that requires other extensions will
 151 automatically cause those extensions to be enabled.  Similarly,
 152 disabling an extension that is required by other extensions will
 153 automatically cause those extensions to be disabled.
 154
 155 @multitable @columnfractions .12 .17 .17 .54
 156 @headitem Extension @tab Minimum Architecture @tab Enabled by default
 157  @tab Description
 158 @item @code{aes} @tab ARMv8-A @tab No
 159  @tab Enable the AES cryptographic extensions. This implies @code{fp} and
 160  @code{simd}.
 161 @item @code{bf16} @tab ARMv8.2-A @tab ARMv8.6-A or later
 162  @tab Enable BFloat16 extension.
 163 @item @code{compnum} @tab ARMv8.2-A @tab ARMv8.3-A or later
 164  @tab Enable the complex number SIMD extensions.  This implies @code{fp16} and
 165  @code{simd}.
 166 @item @code{crc} @tab ARMv8-A @tab ARMv8.1-A or later
 167  @tab Enable CRC instructions.
 168 @item @code{crypto} @tab ARMv8-A @tab No
 169  @tab Enable cryptographic extensions.  This implies @code{fp}, @code{simd},
 170  @code{aes} and @code{sha2}.
 171 @item @code{dotprod} @tab ARMv8.2-A @tab ARMv8.4-A or later
 172  @tab Enable the Dot Product extension.  This implies @code{simd}.
 173 @item @code{f32mm} @tab ARMv8.2-A @tab No
 174  @tab Enable F32 Matrix Multiply extension.  This implies @code{sve}.
 175 @item @code{f64mm} @tab ARMv8.2-A @tab No
 176  @tab Enable F64 Matrix Multiply extension.  This implies @code{sve}.
 177 @item @code{flagm} @tab ARMv8-A @tab ARMv8.4-A or later
 178  @tab Enable Flag Manipulation instructions.
 179 @item @code{fp16fml} @tab ARMv8.2-A @tab ARMv8.4-A or later
 180  @tab Enable ARMv8.2 16-bit floating-point multiplication variant support. This
 181  implies @code{fp} and  @code{fp16}.
 182 @item @code{fp16} @tab ARMv8.2-A @tab ARMv8.2-A or later
 183  @tab Enable ARMv8.2 16-bit floating-point support.  This implies @code{fp}.
 184 @item @code{fp} @tab ARMv8-A @tab ARMv8-A or later
 185  @tab Enable floating-point extensions.
 186 @item @code{i8mm} @tab ARMv8.2-A @tab ARMv8.6-A or later
 187  @tab Enable Int8 Matrix Multiply extension.
 188 @item @code{lor} @tab ARMv8-A @tab ARMv8.1-A or later
 189  @tab Enable Limited Ordering Regions extensions.
 190 @item @code{ls64} @tab ARMv8.6-A @tab ARMv8.7-A or later
 191  @tab Enable 64 Byte Loads/Stores.
 192 @item @code{lse} @tab ARMv8-A @tab ARMv8.1-A or later
 193  @tab Enable Large System extensions.
 194 @item @code{memtag} @tab ARMv8.5-A @tab No
 195  @tab Enable ARMv8.5-A Memory Tagging Extensions.
 196 @item @code{pan} @tab ARMv8-A @tab ARMv8.1-A or later
 197  @tab Enable Privileged Access Never support.
 198 @item @code{pauth} @tab ARMv8-A @tab No
 199  @tab Enable Pointer Authentication.
 200 @item @code{predres} @tab ARMv8-A @tab ARMv8.5-A or later
 201  @tab Enable the Execution and Data and Prediction instructions.
 202 @item @code{profile} @tab ARMv8.2-A @tab No
 203  @tab Enable statistical profiling extensions.
 204 @item @code{ras} @tab ARMv8-A @tab ARMv8.2-A or later
 205  @tab Enable the Reliability, Availability and Serviceability extension.
 206 @item @code{rcpc} @tab ARMv8.2-A @tab ARMv8.3-A or later
 207  @tab Enable the weak release consistency extension.
 208 @item @code{rdma} @tab ARMv8-A @tab ARMv8.1-A or later
 209  @tab Enable ARMv8.1 Advanced SIMD extensions.  This implies @code{simd}.
 210 @item @code{rng} @tab ARMv8.5-A @tab No
 211  @tab Enable ARMv8.5-A random number instructions.
 212 @item @code{sb} @tab ARMv8-A @tab ARMv8.5-A or later
 213  @tab Enable the speculation barrier instruction sb.
 214 @item @code{sha2} @tab ARMv8-A @tab No
 215  @tab Enable the SHA2 cryptographic extensions. This implies @code{fp} and
 216  @code{simd}.
 217 @item @code{sha3} @tab ARMv8.2-A @tab No
 218  @tab Enable the ARMv8.2-A SHA2 and SHA3 cryptographic extensions. This implies
 219  @code{fp}, @code{simd} and @code{sha2}.
 220 @item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
 221  @tab Enable Advanced SIMD extensions.  This implies @code{fp}.
 222 @item @code{sm4} @tab ARMv8.2-A @tab No
 223  @tab Enable the ARMv8.2-A SM3 and SM4 cryptographic extensions. This implies
 224  @code{fp} and @code{simd}.
 225 @item @code{ssbs} @tab ARMv8-A @tab ARMv8.5-A or later
 226  @tab Enable Speculative Store Bypassing Safe state read and write.
 227 @item @code{sve} @tab ARMv8.2-A @tab Armv9-A or later
 228  @tab Enable the Scalable Vector Extensions.  This implies @code{fp16},
 229  @code{simd} and @code{compnum}.
 230 @item @code{sve2} @tab ARMv8-A @tab Armv9-A or later
 231  @tab Enable the SVE2 Extension.  This implies @code{sve}.
 232 @item @code{sve2-aes} @tab ARMv8-A @tab No
 233  @tab Enable SVE2 AES Extension.  This also enables the .Q->.B form of the
 234  @code{pmullt} and @code{pmullb} instructions.  This implies @code{aes} and
 235  @code{sve2}.
 236 @item @code{sve2-bitperm} @tab ARMv8-A @tab No
 237  @tab Enable SVE2 BITPERM Extension.
 238 @item @code{sve2-sha3} @tab ARMv8-A @tab No
 239  @tab Enable SVE2 SHA3 Extension.  This implies @code{sha3} and @code{sve2}.
 240 @item @code{sve2-sm4} @tab ARMv8-A @tab No
 241  @tab Enable SVE2 SM4 Extension.  This implies @code{sm4} and @code{sve2}.
 242 @item @code{tme} @tab ARMv8-A @tab No
 243  @tab Enable Transactional Memory Extensions.
 244 @end multitable
 245
 246 @node AArch64 Syntax
 247 @section Syntax
 248 @menu
 249 * AArch64-Chars::                Special Characters
 250 * AArch64-Regs::                 Register Names
 251 * AArch64-Relocations::      Relocations
 252 @end menu
 253
 254 @node AArch64-Chars
 255 @subsection Special Characters
 256
 257 @cindex line comment character, AArch64
 258 @cindex AArch64 line comment character
 259 The presence of a @samp{//} on a line indicates the start of a comment
 260 that extends to the end of the current line.  If a @samp{#} appears as
 261 the first character of a line, the whole line is treated as a comment.
 262
 263 @cindex line separator, AArch64
 264 @cindex statement separator, AArch64
 265 @cindex AArch64 line separator
 266 The @samp{;} character can be used instead of a newline to separate
 267 statements.
 268
 269 @cindex immediate character, AArch64
 270 @cindex AArch64 immediate character
 271 The @samp{#} can be optionally used to indicate immediate operands.
 272
 273 @node AArch64-Regs
 274 @subsection Register Names
 275
 276 @cindex AArch64 register names
 277 @cindex register names, AArch64
 278 Please refer to the section @samp{4.4 Register Names} of
 279 @samp{ARMv8 Instruction Set Overview}, which is available at
 280 @uref{http://infocenter.arm.com}.
 281
 282 @node AArch64-Relocations
 283 @subsection Relocations
 284
 285 @cindex relocations, AArch64
 286 @cindex AArch64 relocations
 287 @cindex MOVN, MOVZ and MOVK group relocations, AArch64
 288 Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated
 289 by prefixing the label with @samp{#:abs_g2:} etc.
 290 For example to load the 48-bit absolute address of @var{foo} into x0:
 291
 292 @smallexample
 293         movz x0, #:abs_g2:foo           // bits 32-47, overflow check
 294         movk x0, #:abs_g1_nc:foo        // bits 16-31, no overflow check
 295         movk x0, #:abs_g0_nc:foo        // bits  0-15, no overflow check
 296 @end smallexample
 297
 298 @cindex ADRP, ADD, LDR/STR group relocations, AArch64
 299 Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
 300 instructions can be generated by prefixing the label with
 301 @samp{:pg_hi21:} and @samp{#:lo12:} respectively.
 302
 303 For example to use 33-bit (+/-4GB) pc-relative addressing to
 304 load the address of @var{foo} into x0:
 305
 306 @smallexample
 307         adrp x0, :pg_hi21:foo
 308         add  x0, x0, #:lo12:foo
 309 @end smallexample
 310
 311 Or to load the value of @var{foo} into x0:
 312
 313 @smallexample
 314         adrp x0, :pg_hi21:foo
 315         ldr  x0, [x0, #:lo12:foo]
 316 @end smallexample
 317
 318 Note that @samp{:pg_hi21:} is optional.
 319
 320 @smallexample
 321         adrp x0, foo
 322 @end smallexample
 323
 324 is equivalent to
 325
 326 @smallexample
 327         adrp x0, :pg_hi21:foo
 328 @end smallexample
 329
 330 @node AArch64 Floating Point
 331 @section Floating Point
 332
 333 @cindex floating point, AArch64 (@sc{ieee})
 334 @cindex AArch64 floating point (@sc{ieee})
 335 The AArch64 architecture uses @sc{ieee} floating-point numbers.
 336
 337 @node AArch64 Directives
 338 @section AArch64 Machine Directives
 339
 340 @cindex machine directives, AArch64
 341 @cindex AArch64 machine directives
 342 @table @code
 343
 344 @c AAAAAAAAAAAAAAAAAAAAAAAAA
 345
 346 @cindex @code{.arch} directive, AArch64
 347 @item .arch @var{name}
 348 Select the target architecture.  Valid values for @var{name} are the same as
 349 for the @option{-march} command-line option.
 350
 351 Specifying @code{.arch} clears any previously selected architecture
 352 extensions.
 353
 354 @cindex @code{.arch_extension} directive, AArch64
 355 @item .arch_extension @var{name}
 356 Add or remove an architecture extension to the target architecture.  Valid
 357 values for @var{name} are the same as those accepted as architectural
 358 extensions by the @option{-mcpu} command-line option.
 359
 360 @code{.arch_extension} may be used multiple times to add or remove extensions
 361 incrementally to the architecture being compiled for.
 362
 363 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
 364
 365 @cindex @code{.bss} directive, AArch64
 366 @item .bss
 367 This directive switches to the @code{.bss} section.
 368
 369 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
 370
 371 @cindex @code{.cpu} directive, AArch64
 372 @item .cpu @var{name}
 373 Set the target processor.  Valid values for @var{name} are the same as
 374 those accepted by the @option{-mcpu=} command-line option.
 375
 376 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
 377
 378 @cindex @code{.dword} directive, AArch64
 379 @item .dword @var{expressions}
 380 The @code{.dword} directive produces 64 bit values.
 381
 382 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
 383
 384 @cindex @code{.even} directive, AArch64
 385 @item .even
 386 The @code{.even} directive aligns the output on the next even byte
 387 boundary.
 388
 389 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
 390
 391 @cindex @code{.float16} directive, AArch64
 392 @item .float16 @var{value [,...,value_n]}
 393 Place the half precision floating point representation of one or more
 394 floating-point values into the current section.
 395 The format used to encode the floating point values is always the
 396 IEEE 754-2008 half precision floating point format.
 397
 398 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
 399 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
 400 @c IIIIIIIIIIIIIIIIIIIIIIIIII
 401
 402 @cindex @code{.inst} directive, AArch64
 403 @item .inst @var{expressions}
 404 Inserts the expressions into the output as if they were instructions,
 405 rather than data.
 406
 407 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
 408 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
 409 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
 410
 411 @cindex @code{.ltorg} directive, AArch64
 412 @item .ltorg
 413 This directive causes the current contents of the literal pool to be
 414 dumped into the current section (which is assumed to be the .text
 415 section) at the current location (aligned to a word boundary).
 416 GAS maintains a separate literal pool for each section and each
 417 sub-section.  The @code{.ltorg} directive will only affect the literal
 418 pool of the current section and sub-section.  At the end of assembly
 419 all remaining, un-empty literal pools will automatically be dumped.
 420
 421 Note - older versions of GAS would dump the current literal
 422 pool any time a section change occurred.  This is no longer done, since
 423 it prevents accurate control of the placement of literal pools.
 424
 425 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
 426
 427 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
 428 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
 429
 430 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
 431
 432 @cindex @code{.pool} directive, AArch64
 433 @item .pool
 434 This is a synonym for .ltorg.
 435
 436 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
 437 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
 438
 439 @cindex @code{.req} directive, AArch64
 440 @item @var{name} .req @var{register name}
 441 This creates an alias for @var{register name} called @var{name}.  For
 442 example:
 443
 444 @smallexample
 445         foo .req w0
 446 @end smallexample
 447
 448 ip0, ip1, lr and fp are automatically defined to
 449 alias to X16, X17, X30 and X29 respectively.
 450
 451 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
 452
 453 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
 454
 455 @cindex @code{.tlsdescadd} directive, AArch64
 456 @item   @code{.tlsdescadd}
 457 Emits a TLSDESC_ADD reloc on the next instruction.
 458
 459 @cindex @code{.tlsdesccall} directive, AArch64
 460 @item   @code{.tlsdesccall}
 461 Emits a TLSDESC_CALL reloc on the next instruction.
 462
 463 @cindex @code{.tlsdescldr} directive, AArch64
 464 @item   @code{.tlsdescldr}
 465 Emits a TLSDESC_LDR reloc on the next instruction.
 466
 467 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
 468
 469 @cindex @code{.unreq} directive, AArch64
 470 @item .unreq @var{alias-name}
 471 This undefines a register alias which was previously defined using the
 472 @code{req} directive.  For example:
 473
 474 @smallexample
 475         foo .req w0
 476         .unreq foo
 477 @end smallexample
 478
 479 An error occurs if the name is undefined.  Note - this pseudo op can
 480 be used to delete builtin in register name aliases (eg 'w0').  This
 481 should only be done if it is really necessary.
 482
 483 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
 484
 485 @cindex @code{.variant_pcs} directive, AArch64
 486 @item .variant_pcs @var{symbol}
 487 This directive marks @var{symbol} referencing a function that may
 488 follow a variant procedure call standard with different register
 489 usage convention from the base procedure call standard.
 490
 491 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
 492 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
 493
 494 @cindex @code{.xword} directive, AArch64
 495 @item .xword @var{expressions}
 496 The @code{.xword} directive produces 64 bit values.  This is the same
 497 as the @code{.dword} directive.
 498
 499 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
 500 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
 501
 502 @cindex @code{.cfi_b_key_frame} directive, AArch64
 503 @item   @code{.cfi_b_key_frame}
 504 The @code{.cfi_b_key_frame} directive inserts a 'B' character into the CIE
 505 corresponding to the current frame's FDE, meaning that its return address has
 506 been signed with the B-key.  If two frames are signed with differing keys then
 507 they will not share the same CIE.  This information is intended to be used by
 508 the stack unwinder in order to properly authenticate return addresses.
 509
 510 @end table
 511
 512 @node AArch64 Opcodes
 513 @section Opcodes
 514
 515 @cindex AArch64 opcodes
 516 @cindex opcodes for AArch64
 517 GAS implements all the standard AArch64 opcodes.  It also
 518 implements several pseudo opcodes, including several synthetic load
 519 instructions.
 520
 521 @table @code
 522
 523 @cindex @code{LDR reg,=<expr>} pseudo op, AArch64
 524 @item LDR =
 525 @smallexample
 526   ldr <register> , =<expression>
 527 @end smallexample
 528
 529 The constant expression will be placed into the nearest literal pool (if it not
 530 already there) and a PC-relative LDR instruction will be generated.
 531
 532 @end table
 533
 534 For more information on the AArch64 instruction set and assembly language
 535 notation, see @samp{ARMv8 Instruction Set Overview} available at
 536 @uref{http://infocenter.arm.com}.
 537
 538
 539 @node AArch64 Mapping Symbols
 540 @section Mapping Symbols
 541
 542 The AArch64 ELF specification requires that special symbols be inserted
 543 into object files to mark certain features:
 544
 545 @table @code
 546
 547 @cindex @code{$x}
 548 @item $x
 549 At the start of a region of code containing AArch64 instructions.
 550
 551 @cindex @code{$d}
 552 @item $d
 553 At the start of a region of data.
 554
 555 @end table