gas/doc/c-aarch64.texi

   1 @c Copyright (C) 2009-2015 Free Software Foundation, Inc.
   2 @c Contributed by ARM Ltd.
   3 @c This is part of the GAS manual.
   4 @c For copying conditions, see the file as.texinfo.
   5 @c man end
   6
   7 @ifset GENERIC
   8 @page
   9 @node AArch64-Dependent
  10 @chapter AArch64 Dependent Features
  11 @end ifset
  12
  13 @ifclear GENERIC
  14 @node Machine Dependencies
  15 @chapter AArch64 Dependent Features
  16 @end ifclear
  17
  18 @cindex AArch64 support
  19 @menu
  20 * AArch64 Options::              Options
  21 * AArch64 Extensions::           Extensions
  22 * AArch64 Syntax::               Syntax
  23 * AArch64 Floating Point::       Floating Point
  24 * AArch64 Directives::           AArch64 Machine Directives
  25 * AArch64 Opcodes::              Opcodes
  26 * AArch64 Mapping Symbols::      Mapping Symbols
  27 @end menu
  28
  29 @node AArch64 Options
  30 @section Options
  31 @cindex AArch64 options (none)
  32 @cindex options for AArch64 (none)
  33
  34 @c man begin OPTIONS
  35 @table @gcctabopt
  36
  37 @cindex @option{-EB} command line option, AArch64
  38 @item -EB
  39 This option specifies that the output generated by the assembler should
  40 be marked as being encoded for a big-endian processor.
  41
  42 @cindex @option{-EL} command line option, AArch64
  43 @item -EL
  44 This option specifies that the output generated by the assembler should
  45 be marked as being encoded for a little-endian processor.
  46
  47 @cindex @option{-mabi=} command line option, AArch64
  48 @item -mabi=@var{abi}
  49 Specify which ABI the source code uses.  The recognized arguments
  50 are: @code{ilp32} and @code{lp64}, which decides the generated object
  51 file in ELF32 and ELF64 format respectively.  The default is @code{lp64}.
  52
  53 @cindex @option{-mcpu=} command line option, AArch64
  54 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
  55 This option specifies the target processor.  The assembler will issue an error
  56 message if an attempt is made to assemble an instruction which will not execute
  57 on the target processor.  The following processor names are recognized:
  58 @code{cortex-a53},
  59 @code{cortex-a57},
  60 @code{cortex-a72},
  61 @code{exynos-m1},
  62 @code{qdf24xx},
  63 @code{thunderx},
  64 @code{xgene1}
  65 and
  66 @code{xgene2}.
  67 The special name @code{all} may be used to allow the assembler to accept
  68 instructions valid for any supported processor, including all optional
  69 extensions.
  70
  71 In addition to the basic instruction set, the assembler can be told to
  72 accept, or restrict, various extension mnemonics that extend the
  73 processor.  @xref{AArch64 Extensions}.
  74
  75 If some implementations of a particular processor can have an
  76 extension, then then those extensions are automatically enabled.
  77 Consequently, you will not normally have to specify any additional
  78 extensions.
  79
  80 @cindex @option{-march=} command line option, AArch64
  81 @item -march=@var{architecture}[+@var{extension}@dots{}]
  82 This option specifies the target architecture.  The assembler will
  83 issue an error message if an attempt is made to assemble an
  84 instruction which will not execute on the target architecture.  The
  85 following architecture names are recognized: @code{armv8-a} and
  86 @code{armv8.1-a}.
  87
  88 If both @option{-mcpu} and @option{-march} are specified, the
  89 assembler will use the setting for @option{-mcpu}.  If neither are
  90 specified, the assembler will default to @option{-mcpu=all}.
  91
  92 The architecture option can be extended with the same instruction set
  93 extension options as the @option{-mcpu} option.  Unlike
  94 @option{-mcpu}, extensions are not always enabled by default,
  95 @xref{AArch64 Extensions}.
  96
  97 @cindex @code{-mverbose-error} command line option, AArch64
  98 @item -mverbose-error
  99 This option enables verbose error messages for AArch64 gas.  This option
 100 is enabled by default.
 101
 102 @cindex @code{-mno-verbose-error} command line option, AArch64
 103 @item -mno-verbose-error
 104 This option disables verbose error messages in AArch64 gas.
 105
 106 @end table
 107 @c man end
 108
 109 @node AArch64 Extensions
 110 @section Architecture Extensions
 111
 112 The table below lists the permitted architecture extensions that are
 113 supported by the assembler and the conditions under which they are
 114 automatically enabled.
 115
 116 Multiple extensions may be specified, separated by a @code{+}.
 117 Extension mnemonics may also be removed from those the assembler
 118 accepts.  This is done by prepending @code{no} to the option that adds
 119 the extension.  Extensions that are removed must be listed after all
 120 extensions that have been added.
 121
 122 Enabling an extension that requires other extensions will
 123 automatically cause those extensions to be enabled.  Similarly,
 124 disabling an extension that is required by other extensions will
 125 automatically cause those extensions to be disabled.
 126
 127 @multitable @columnfractions .12 .17 .17 .54
 128 @headitem Extension @tab Minimum Architecture @tab Enabled by default
 129  @tab Description
 130 @item @code{crc} @tab ARMv8-A @tab No
 131  @tab Enable CRC instructions.
 132 @item @code{crypto} @tab ARMv8-A @tab No
 133  @tab Enable cryptographic extensions.  This implies @code{fp} and @code{simd}.
 134 @item @code{fp} @tab ARMv8-A @tab ARMv8-A or later
 135  @tab Enable floating-point extensions.
 136 @item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
 137  @tab Enable Advanced SIMD extensions.  This implies @code{fp}.
 138 @item @code{pan} @tab ARMv8-A @tab ARMv8-A or later
 139  @tab Enable Privileged Access Never support.
 140 @item @code{lor} @tab ARMv8-A @tab ARMv8-A or later
 141  @tab Enable Limited Ordering Regions extensions.
 142 @item @code{rdma} @tab ARMv8-A @tab ARMv8-A or later
 143  @tab Enable ARMv8.1 Advanced SIMD extensions.  This implies @code{simd}.
 144 @end multitable
 145
 146 @node AArch64 Syntax
 147 @section Syntax
 148 @menu
 149 * AArch64-Chars::                Special Characters
 150 * AArch64-Regs::                 Register Names
 151 * AArch64-Relocations::      Relocations
 152 @end menu
 153
 154 @node AArch64-Chars
 155 @subsection Special Characters
 156
 157 @cindex line comment character, AArch64
 158 @cindex AArch64 line comment character
 159 The presence of a @samp{//} on a line indicates the start of a comment
 160 that extends to the end of the current line.  If a @samp{#} appears as
 161 the first character of a line, the whole line is treated as a comment.
 162
 163 @cindex line separator, AArch64
 164 @cindex statement separator, AArch64
 165 @cindex AArch64 line separator
 166 The @samp{;} character can be used instead of a newline to separate
 167 statements.
 168
 169 @cindex immediate character, AArch64
 170 @cindex AArch64 immediate character
 171 The @samp{#} can be optionally used to indicate immediate operands.
 172
 173 @node AArch64-Regs
 174 @subsection Register Names
 175
 176 @cindex AArch64 register names
 177 @cindex register names, AArch64
 178 Please refer to the section @samp{4.4 Register Names} of
 179 @samp{ARMv8 Instruction Set Overview}, which is available at
 180 @uref{http://infocenter.arm.com}.
 181
 182 @node AArch64-Relocations
 183 @subsection Relocations
 184
 185 @cindex relocations, AArch64
 186 @cindex AArch64 relocations
 187 @cindex MOVN, MOVZ and MOVK group relocations, AArch64
 188 Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated
 189 by prefixing the label with @samp{#:abs_g2:} etc.
 190 For example to load the 48-bit absolute address of @var{foo} into x0:
 191
 192 @smallexample
 193         movz x0, #:abs_g2:foo           // bits 32-47, overflow check
 194         movk x0, #:abs_g1_nc:foo        // bits 16-31, no overflow check
 195         movk x0, #:abs_g0_nc:foo        // bits  0-15, no overflow check
 196 @end smallexample
 197
 198 @cindex ADRP, ADD, LDR/STR group relocations, AArch64
 199 Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
 200 instructions can be generated by prefixing the label with
 201 @samp{:pg_hi21:} and @samp{#:lo12:} respectively.
 202
 203 For example to use 33-bit (+/-4GB) pc-relative addressing to
 204 load the address of @var{foo} into x0:
 205
 206 @smallexample
 207         adrp x0, :pg_hi21:foo
 208         add  x0, x0, #:lo12:foo
 209 @end smallexample
 210
 211 Or to load the value of @var{foo} into x0:
 212
 213 @smallexample
 214         adrp x0, :pg_hi21:foo
 215         ldr  x0, [x0, #:lo12:foo]
 216 @end smallexample
 217
 218 Note that @samp{:pg_hi21:} is optional.
 219
 220 @smallexample
 221         adrp x0, foo
 222 @end smallexample
 223
 224 is equivalent to
 225
 226 @smallexample
 227         adrp x0, :pg_hi21:foo
 228 @end smallexample
 229
 230 @node AArch64 Floating Point
 231 @section Floating Point
 232
 233 @cindex floating point, AArch64 (@sc{ieee})
 234 @cindex AArch64 floating point (@sc{ieee})
 235 The AArch64 architecture uses @sc{ieee} floating-point numbers.
 236
 237 @node AArch64 Directives
 238 @section AArch64 Machine Directives
 239
 240 @cindex machine directives, AArch64
 241 @cindex AArch64 machine directives
 242 @table @code
 243
 244 @c AAAAAAAAAAAAAAAAAAAAAAAAA
 245
 246 @cindex @code{.arch} directive, AArch64
 247 @item .arch @var{name}
 248 Select the target architecture.  Valid values for @var{name} are the same as
 249 for the @option{-march} commandline option.
 250
 251 Specifying @code{.arch} clears any previously selected architecture
 252 extensions.
 253
 254 @cindex @code{.arch_extension} directive, AArch64
 255 @item .arch_extension @var{name}
 256 Add or remove an architecture extension to the target architecture.  Valid
 257 values for @var{name} are the same as those accepted as architectural
 258 extensions by the @option{-mcpu} commandline option.
 259
 260 @code{.arch_extension} may be used multiple times to add or remove extensions
 261 incrementally to the architecture being compiled for.
 262
 263 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
 264
 265 @cindex @code{.bss} directive, AArch64
 266 @item .bss
 267 This directive switches to the @code{.bss} section.
 268
 269 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
 270 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
 271 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
 272 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
 273 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
 274 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
 275 @c IIIIIIIIIIIIIIIIIIIIIIIIII
 276 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
 277 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
 278 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
 279
 280 @cindex @code{.ltorg} directive, AArch64
 281 @item .ltorg
 282 This directive causes the current contents of the literal pool to be
 283 dumped into the current section (which is assumed to be the .text
 284 section) at the current location (aligned to a word boundary).
 285 GAS maintains a separate literal pool for each section and each
 286 sub-section.  The @code{.ltorg} directive will only affect the literal
 287 pool of the current section and sub-section.  At the end of assembly
 288 all remaining, un-empty literal pools will automatically be dumped.
 289
 290 Note - older versions of GAS would dump the current literal
 291 pool any time a section change occurred.  This is no longer done, since
 292 it prevents accurate control of the placement of literal pools.
 293
 294 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
 295
 296 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
 297 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
 298
 299 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
 300
 301 @cindex @code{.pool} directive, AArch64
 302 @item .pool
 303 This is a synonym for .ltorg.
 304
 305 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
 306 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
 307
 308 @cindex @code{.req} directive, AArch64
 309 @item @var{name} .req @var{register name}
 310 This creates an alias for @var{register name} called @var{name}.  For
 311 example:
 312
 313 @smallexample
 314         foo .req w0
 315 @end smallexample
 316
 317 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
 318
 319 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
 320
 321 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
 322
 323 @cindex @code{.unreq} directive, AArch64
 324 @item .unreq @var{alias-name}
 325 This undefines a register alias which was previously defined using the
 326 @code{req} directive.  For example:
 327
 328 @smallexample
 329         foo .req w0
 330         .unreq foo
 331 @end smallexample
 332
 333 An error occurs if the name is undefined.  Note - this pseudo op can
 334 be used to delete builtin in register name aliases (eg 'w0').  This
 335 should only be done if it is really necessary.
 336
 337 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
 338
 339 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
 340 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
 341 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
 342 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
 343
 344 @cindex @code{.xword} directive, AArch64
 345 @item .xword
 346 The @code{.xword} directive produces 64 bit values.
 347
 348 @end table
 349
 350 @node AArch64 Opcodes
 351 @section Opcodes
 352
 353 @cindex AArch64 opcodes
 354 @cindex opcodes for AArch64
 355 GAS implements all the standard AArch64 opcodes.  It also
 356 implements several pseudo opcodes, including several synthetic load
 357 instructions.
 358
 359 @table @code
 360
 361 @cindex @code{LDR reg,=<expr>} pseudo op, AArch64
 362 @item LDR =
 363 @smallexample
 364   ldr <register> , =<expression>
 365 @end smallexample
 366
 367 The constant expression will be placed into the nearest literal pool (if it not
 368 already there) and a PC-relative LDR instruction will be generated.
 369
 370 @end table
 371
 372 For more information on the AArch64 instruction set and assembly language
 373 notation, see @samp{ARMv8 Instruction Set Overview} available at
 374 @uref{http://infocenter.arm.com}.
 375
 376
 377 @node AArch64 Mapping Symbols
 378 @section Mapping Symbols
 379
 380 The AArch64 ELF specification requires that special symbols be inserted
 381 into object files to mark certain features:
 382
 383 @table @code
 384
 385 @cindex @code{$x}
 386 @item $x
 387 At the start of a region of code containing AArch64 instructions.
 388
 389 @cindex @code{$d}
 390 @item $d
 391 At the start of a region of data.
 392
 393 @end table