gas/doc/c-aarch64.texi

   1 @c Copyright (C) 2009-2020 Free Software Foundation, Inc.
   2 @c Contributed by ARM Ltd.
   3 @c This is part of the GAS manual.
   4 @c For copying conditions, see the file as.texinfo.
   5 @c man end
   6
   7 @ifset GENERIC
   8 @page
   9 @node AArch64-Dependent
  10 @chapter AArch64 Dependent Features
  11 @end ifset
  12
  13 @ifclear GENERIC
  14 @node Machine Dependencies
  15 @chapter AArch64 Dependent Features
  16 @end ifclear
  17
  18 @cindex AArch64 support
  19 @menu
  20 * AArch64 Options::              Options
  21 * AArch64 Extensions::           Extensions
  22 * AArch64 Syntax::               Syntax
  23 * AArch64 Floating Point::       Floating Point
  24 * AArch64 Directives::           AArch64 Machine Directives
  25 * AArch64 Opcodes::              Opcodes
  26 * AArch64 Mapping Symbols::      Mapping Symbols
  27 @end menu
  28
  29 @node AArch64 Options
  30 @section Options
  31 @cindex AArch64 options (none)
  32 @cindex options for AArch64 (none)
  33
  34 @c man begin OPTIONS
  35 @table @gcctabopt
  36
  37 @cindex @option{-EB} command-line option, AArch64
  38 @item -EB
  39 This option specifies that the output generated by the assembler should
  40 be marked as being encoded for a big-endian processor.
  41
  42 @cindex @option{-EL} command-line option, AArch64
  43 @item -EL
  44 This option specifies that the output generated by the assembler should
  45 be marked as being encoded for a little-endian processor.
  46
  47 @cindex @option{-mabi=} command-line option, AArch64
  48 @item -mabi=@var{abi}
  49 Specify which ABI the source code uses.  The recognized arguments
  50 are: @code{ilp32} and @code{lp64}, which decides the generated object
  51 file in ELF32 and ELF64 format respectively.  The default is @code{lp64}.
  52
  53 @cindex @option{-mcpu=} command-line option, AArch64
  54 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
  55 This option specifies the target processor.  The assembler will issue an error
  56 message if an attempt is made to assemble an instruction which will not execute
  57 on the target processor.  The following processor names are recognized:
  58 @code{cortex-a34},
  59 @code{cortex-a35},
  60 @code{cortex-a53},
  61 @code{cortex-a55},
  62 @code{cortex-a57},
  63 @code{cortex-a65},
  64 @code{cortex-a65ae},
  65 @code{cortex-a72},
  66 @code{cortex-a73},
  67 @code{cortex-a75},
  68 @code{cortex-a76},
  69 @code{cortex-a76ae},
  70 @code{cortex-a77},
  71 @code{cortex-a78},
  72 @code{cortex-a78ae},
  73 @code{ares},
  74 @code{exynos-m1},
  75 @code{falkor},
  76 @code{neoverse-n1},
  77 @code{neoverse-n2},
  78 @code{neoverse-e1},
  79 @code{neoverse-v1},
  80 @code{qdf24xx},
  81 @code{saphira},
  82 @code{thunderx},
  83 @code{vulcan},
  84 @code{xgene1}
  85 @code{xgene2},
  86 @code{cortex-r82},
  87 and
  88 @code{cortex-x1}.
  89 The special name @code{all} may be used to allow the assembler to accept
  90 instructions valid for any supported processor, including all optional
  91 extensions.
  92
  93 In addition to the basic instruction set, the assembler can be told to
  94 accept, or restrict, various extension mnemonics that extend the
  95 processor.  @xref{AArch64 Extensions}.
  96
  97 If some implementations of a particular processor can have an
  98 extension, then then those extensions are automatically enabled.
  99 Consequently, you will not normally have to specify any additional
 100 extensions.
 101
 102 @cindex @option{-march=} command-line option, AArch64
 103 @item -march=@var{architecture}[+@var{extension}@dots{}]
 104 This option specifies the target architecture.  The assembler will
 105 issue an error message if an attempt is made to assemble an
 106 instruction which will not execute on the target architecture.  The
 107 following architecture names are recognized: @code{armv8-a},
 108 @code{armv8.1-a}, @code{armv8.2-a}, @code{armv8.3-a}, @code{armv8.4-a}
 109 @code{armv8.5-a}, @code{armv8.6-a}, and @code{armv8-r}.
 110
 111 If both @option{-mcpu} and @option{-march} are specified, the
 112 assembler will use the setting for @option{-mcpu}.  If neither are
 113 specified, the assembler will default to @option{-mcpu=all}.
 114
 115 The architecture option can be extended with the same instruction set
 116 extension options as the @option{-mcpu} option.  Unlike
 117 @option{-mcpu}, extensions are not always enabled by default,
 118 @xref{AArch64 Extensions}.
 119
 120 @cindex @code{-mverbose-error} command-line option, AArch64
 121 @item -mverbose-error
 122 This option enables verbose error messages for AArch64 gas.  This option
 123 is enabled by default.
 124
 125 @cindex @code{-mno-verbose-error} command-line option, AArch64
 126 @item -mno-verbose-error
 127 This option disables verbose error messages in AArch64 gas.
 128
 129 @end table
 130 @c man end
 131
 132 @node AArch64 Extensions
 133 @section Architecture Extensions
 134
 135 The table below lists the permitted architecture extensions that are
 136 supported by the assembler and the conditions under which they are
 137 automatically enabled.
 138
 139 Multiple extensions may be specified, separated by a @code{+}.
 140 Extension mnemonics may also be removed from those the assembler
 141 accepts.  This is done by prepending @code{no} to the option that adds
 142 the extension.  Extensions that are removed must be listed after all
 143 extensions that have been added.
 144
 145 Enabling an extension that requires other extensions will
 146 automatically cause those extensions to be enabled.  Similarly,
 147 disabling an extension that is required by other extensions will
 148 automatically cause those extensions to be disabled.
 149
 150 @multitable @columnfractions .12 .17 .17 .54
 151 @headitem Extension @tab Minimum Architecture @tab Enabled by default
 152  @tab Description
 153 @item @code{i8mm} @tab ARMv8.2-A @tab ARMv8.6-A or later
 154  @tab Enable Int8 Matrix Multiply extension.
 155 @item @code{f32mm} @tab ARMv8.2-A @tab No
 156  @tab Enable F32 Matrix Multiply extension.
 157 @item @code{f64mm} @tab ARMv8.2-A @tab No
 158  @tab Enable F64 Matrix Multiply extension.
 159 @item @code{bf16} @tab ARMv8.2-A @tab ARMv8.6-A or later
 160  @tab Enable BFloat16 extension.
 161 @item @code{compnum} @tab ARMv8.2-A @tab ARMv8.3-A or later
 162  @tab Enable the complex number SIMD extensions.  This implies
 163  @code{fp16} and @code{simd}.
 164 @item @code{crc} @tab ARMv8-A @tab ARMv8.1-A or later
 165  @tab Enable CRC instructions.
 166 @item @code{crypto} @tab ARMv8-A @tab No
 167  @tab Enable cryptographic extensions.  This implies @code{fp}, @code{simd}, @code{aes} and @code{sha2}.
 168 @item @code{aes} @tab ARMv8-A @tab No
 169  @tab Enable the AES cryptographic extensions. This implies @code{fp} and @code{simd}.
 170 @item @code{sha2} @tab ARMv8-A @tab No
 171  @tab Enable the SHA2 cryptographic extensions. This implies @code{fp} and @code{simd}.
 172 @item @code{sha3} @tab ARMv8.2-A @tab No
 173  @tab Enable the ARMv8.2-A SHA2 and SHA3 cryptographic extensions. This implies @code{fp}, @code{simd} and @code{sha2}.
 174 @item @code{sm4} @tab ARMv8.2-A @tab No
 175  @tab Enable the ARMv8.2-A SM3 and SM4 cryptographic extensions. This implies @code{fp} and @code{simd}.
 176 @item @code{fp} @tab ARMv8-A @tab ARMv8-A or later
 177  @tab Enable floating-point extensions.
 178 @item @code{fp16} @tab ARMv8.2-A @tab ARMv8.2-A or later
 179  @tab Enable ARMv8.2 16-bit floating-point support.  This implies
 180  @code{fp}.
 181 @item @code{lor} @tab ARMv8-A @tab ARMv8.1-A or later
 182  @tab Enable Limited Ordering Regions extensions.
 183 @item @code{lse} @tab ARMv8-A @tab ARMv8.1-A or later
 184  @tab Enable Large System extensions.
 185 @item @code{pan} @tab ARMv8-A @tab ARMv8.1-A or later
 186  @tab Enable Privileged Access Never support.
 187 @item @code{profile} @tab ARMv8.2-A @tab No
 188  @tab Enable statistical profiling extensions.
 189 @item @code{ras} @tab ARMv8-A @tab ARMv8.2-A or later
 190  @tab Enable the Reliability, Availability and Serviceability
 191  extension.
 192 @item @code{rcpc} @tab ARMv8.2-A @tab ARMv8.3-A or later
 193  @tab Enable the weak release consistency extension.
 194 @item @code{rdma} @tab ARMv8-A @tab ARMv8.1-A or later
 195  @tab Enable ARMv8.1 Advanced SIMD extensions.  This implies @code{simd}.
 196 @item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
 197  @tab Enable Advanced SIMD extensions.  This implies @code{fp}.
 198 @item @code{sve} @tab ARMv8.2-A @tab No
 199  @tab Enable the Scalable Vector Extensions.  This implies @code{fp16},
 200  @code{simd} and @code{compnum}.
 201 @item @code{dotprod} @tab ARMv8.2-A @tab ARMv8.4-A or later
 202  @tab Enable the Dot Product extension.  This implies @code{simd}.
 203 @item @code{fp16fml} @tab ARMv8.2-A @tab ARMv8.4-A or later
 204  @tab Enable ARMv8.2 16-bit floating-point multiplication variant support.
 205  This implies @code{fp16}.
 206 @item @code{sb} @tab ARMv8-A @tab ARMv8.5-A or later
 207  @tab Enable the speculation barrier instruction sb.
 208 @item @code{predres} @tab ARMv8-A @tab ARMv8.5-A or later
 209  @tab Enable the Execution and Data and Prediction instructions.
 210 @item @code{rng} @tab ARMv8.5-A @tab No
 211  @tab Enable ARMv8.5-A random number instructions.
 212 @item @code{ssbs} @tab ARMv8-A @tab ARMv8.5-A or later
 213  @tab Enable Speculative Store Bypassing Safe state read and write.
 214 @item @code{memtag} @tab ARMv8.5-A @tab No
 215  @tab Enable ARMv8.5-A Memory Tagging Extensions.
 216 @item @code{tme} @tab ARMv8-A @tab No
 217  @tab Enable Transactional Memory Extensions.
 218 @item @code{sve2} @tab ARMv8-A @tab No
 219  @tab Enable the SVE2 Extension.
 220 @item @code{sve2-bitperm} @tab ARMv8-A @tab No
 221  @tab Enable SVE2 BITPERM Extension.
 222 @item @code{sve2-sm4} @tab ARMv8-A @tab No
 223  @tab Enable SVE2 SM4 Extension.
 224 @item @code{sve2-aes} @tab ARMv8-A @tab No
 225  @tab Enable SVE2 AES Extension.  This also enables the .Q->.B form of the
 226  @code{pmullt} and @code{pmullb} instructions.
 227 @item @code{sve2-sha3} @tab ARMv8-A @tab No
 228  @tab Enable SVE2 SHA3 Extension.
 229 @end multitable
 230
 231 @node AArch64 Syntax
 232 @section Syntax
 233 @menu
 234 * AArch64-Chars::                Special Characters
 235 * AArch64-Regs::                 Register Names
 236 * AArch64-Relocations::      Relocations
 237 @end menu
 238
 239 @node AArch64-Chars
 240 @subsection Special Characters
 241
 242 @cindex line comment character, AArch64
 243 @cindex AArch64 line comment character
 244 The presence of a @samp{//} on a line indicates the start of a comment
 245 that extends to the end of the current line.  If a @samp{#} appears as
 246 the first character of a line, the whole line is treated as a comment.
 247
 248 @cindex line separator, AArch64
 249 @cindex statement separator, AArch64
 250 @cindex AArch64 line separator
 251 The @samp{;} character can be used instead of a newline to separate
 252 statements.
 253
 254 @cindex immediate character, AArch64
 255 @cindex AArch64 immediate character
 256 The @samp{#} can be optionally used to indicate immediate operands.
 257
 258 @node AArch64-Regs
 259 @subsection Register Names
 260
 261 @cindex AArch64 register names
 262 @cindex register names, AArch64
 263 Please refer to the section @samp{4.4 Register Names} of
 264 @samp{ARMv8 Instruction Set Overview}, which is available at
 265 @uref{http://infocenter.arm.com}.
 266
 267 @node AArch64-Relocations
 268 @subsection Relocations
 269
 270 @cindex relocations, AArch64
 271 @cindex AArch64 relocations
 272 @cindex MOVN, MOVZ and MOVK group relocations, AArch64
 273 Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated
 274 by prefixing the label with @samp{#:abs_g2:} etc.
 275 For example to load the 48-bit absolute address of @var{foo} into x0:
 276
 277 @smallexample
 278         movz x0, #:abs_g2:foo           // bits 32-47, overflow check
 279         movk x0, #:abs_g1_nc:foo        // bits 16-31, no overflow check
 280         movk x0, #:abs_g0_nc:foo        // bits  0-15, no overflow check
 281 @end smallexample
 282
 283 @cindex ADRP, ADD, LDR/STR group relocations, AArch64
 284 Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
 285 instructions can be generated by prefixing the label with
 286 @samp{:pg_hi21:} and @samp{#:lo12:} respectively.
 287
 288 For example to use 33-bit (+/-4GB) pc-relative addressing to
 289 load the address of @var{foo} into x0:
 290
 291 @smallexample
 292         adrp x0, :pg_hi21:foo
 293         add  x0, x0, #:lo12:foo
 294 @end smallexample
 295
 296 Or to load the value of @var{foo} into x0:
 297
 298 @smallexample
 299         adrp x0, :pg_hi21:foo
 300         ldr  x0, [x0, #:lo12:foo]
 301 @end smallexample
 302
 303 Note that @samp{:pg_hi21:} is optional.
 304
 305 @smallexample
 306         adrp x0, foo
 307 @end smallexample
 308
 309 is equivalent to
 310
 311 @smallexample
 312         adrp x0, :pg_hi21:foo
 313 @end smallexample
 314
 315 @node AArch64 Floating Point
 316 @section Floating Point
 317
 318 @cindex floating point, AArch64 (@sc{ieee})
 319 @cindex AArch64 floating point (@sc{ieee})
 320 The AArch64 architecture uses @sc{ieee} floating-point numbers.
 321
 322 @node AArch64 Directives
 323 @section AArch64 Machine Directives
 324
 325 @cindex machine directives, AArch64
 326 @cindex AArch64 machine directives
 327 @table @code
 328
 329 @c AAAAAAAAAAAAAAAAAAAAAAAAA
 330
 331 @cindex @code{.arch} directive, AArch64
 332 @item .arch @var{name}
 333 Select the target architecture.  Valid values for @var{name} are the same as
 334 for the @option{-march} command-line option.
 335
 336 Specifying @code{.arch} clears any previously selected architecture
 337 extensions.
 338
 339 @cindex @code{.arch_extension} directive, AArch64
 340 @item .arch_extension @var{name}
 341 Add or remove an architecture extension to the target architecture.  Valid
 342 values for @var{name} are the same as those accepted as architectural
 343 extensions by the @option{-mcpu} command-line option.
 344
 345 @code{.arch_extension} may be used multiple times to add or remove extensions
 346 incrementally to the architecture being compiled for.
 347
 348 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
 349
 350 @cindex @code{.bss} directive, AArch64
 351 @item .bss
 352 This directive switches to the @code{.bss} section.
 353
 354 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
 355
 356 @cindex @code{.cpu} directive, AArch64
 357 @item .cpu @var{name}
 358 Set the target processor.  Valid values for @var{name} are the same as
 359 those accepted by the @option{-mcpu=} command-line option.
 360
 361 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
 362
 363 @cindex @code{.dword} directive, AArch64
 364 @item .dword @var{expressions}
 365 The @code{.dword} directive produces 64 bit values.
 366
 367 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
 368
 369 @cindex @code{.even} directive, AArch64
 370 @item .even
 371 The @code{.even} directive aligns the output on the next even byte
 372 boundary.
 373
 374 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
 375
 376 @cindex @code{.float16} directive, AArch64
 377 @item .float16 @var{value [,...,value_n]}
 378 Place the half precision floating point representation of one or more
 379 floating-point values into the current section.
 380 The format used to encode the floating point values is always the
 381 IEEE 754-2008 half precision floating point format.
 382
 383 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
 384 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
 385 @c IIIIIIIIIIIIIIIIIIIIIIIIII
 386
 387 @cindex @code{.inst} directive, AArch64
 388 @item .inst @var{expressions}
 389 Inserts the expressions into the output as if they were instructions,
 390 rather than data.
 391
 392 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
 393 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
 394 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
 395
 396 @cindex @code{.ltorg} directive, AArch64
 397 @item .ltorg
 398 This directive causes the current contents of the literal pool to be
 399 dumped into the current section (which is assumed to be the .text
 400 section) at the current location (aligned to a word boundary).
 401 GAS maintains a separate literal pool for each section and each
 402 sub-section.  The @code{.ltorg} directive will only affect the literal
 403 pool of the current section and sub-section.  At the end of assembly
 404 all remaining, un-empty literal pools will automatically be dumped.
 405
 406 Note - older versions of GAS would dump the current literal
 407 pool any time a section change occurred.  This is no longer done, since
 408 it prevents accurate control of the placement of literal pools.
 409
 410 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
 411
 412 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
 413 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
 414
 415 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
 416
 417 @cindex @code{.pool} directive, AArch64
 418 @item .pool
 419 This is a synonym for .ltorg.
 420
 421 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
 422 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
 423
 424 @cindex @code{.req} directive, AArch64
 425 @item @var{name} .req @var{register name}
 426 This creates an alias for @var{register name} called @var{name}.  For
 427 example:
 428
 429 @smallexample
 430         foo .req w0
 431 @end smallexample
 432
 433 ip0, ip1, lr and fp are automatically defined to
 434 alias to X16, X17, X30 and X29 respectively.
 435
 436 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
 437
 438 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
 439
 440 @cindex @code{.tlsdescadd} directive, AArch64
 441 @item   @code{.tlsdescadd}
 442 Emits a TLSDESC_ADD reloc on the next instruction.
 443
 444 @cindex @code{.tlsdesccall} directive, AArch64
 445 @item   @code{.tlsdesccall}
 446 Emits a TLSDESC_CALL reloc on the next instruction.
 447
 448 @cindex @code{.tlsdescldr} directive, AArch64
 449 @item   @code{.tlsdescldr}
 450 Emits a TLSDESC_LDR reloc on the next instruction.
 451
 452 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
 453
 454 @cindex @code{.unreq} directive, AArch64
 455 @item .unreq @var{alias-name}
 456 This undefines a register alias which was previously defined using the
 457 @code{req} directive.  For example:
 458
 459 @smallexample
 460         foo .req w0
 461         .unreq foo
 462 @end smallexample
 463
 464 An error occurs if the name is undefined.  Note - this pseudo op can
 465 be used to delete builtin in register name aliases (eg 'w0').  This
 466 should only be done if it is really necessary.
 467
 468 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
 469
 470 @cindex @code{.variant_pcs} directive, AArch64
 471 @item .variant_pcs @var{symbol}
 472 This directive marks @var{symbol} referencing a function that may
 473 follow a variant procedure call standard with different register
 474 usage convention from the base procedure call standard.
 475
 476 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
 477 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
 478
 479 @cindex @code{.xword} directive, AArch64
 480 @item .xword @var{expressions}
 481 The @code{.xword} directive produces 64 bit values.  This is the same
 482 as the @code{.dword} directive.
 483
 484 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
 485 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
 486
 487 @cindex @code{.cfi_b_key_frame} directive, AArch64
 488 @item   @code{.cfi_b_key_frame}
 489 The @code{.cfi_b_key_frame} directive inserts a 'B' character into the CIE
 490 corresponding to the current frame's FDE, meaning that its return address has
 491 been signed with the B-key.  If two frames are signed with differing keys then
 492 they will not share the same CIE.  This information is intended to be used by
 493 the stack unwinder in order to properly authenticate return addresses.
 494
 495 @end table
 496
 497 @node AArch64 Opcodes
 498 @section Opcodes
 499
 500 @cindex AArch64 opcodes
 501 @cindex opcodes for AArch64
 502 GAS implements all the standard AArch64 opcodes.  It also
 503 implements several pseudo opcodes, including several synthetic load
 504 instructions.
 505
 506 @table @code
 507
 508 @cindex @code{LDR reg,=<expr>} pseudo op, AArch64
 509 @item LDR =
 510 @smallexample
 511   ldr <register> , =<expression>
 512 @end smallexample
 513
 514 The constant expression will be placed into the nearest literal pool (if it not
 515 already there) and a PC-relative LDR instruction will be generated.
 516
 517 @end table
 518
 519 For more information on the AArch64 instruction set and assembly language
 520 notation, see @samp{ARMv8 Instruction Set Overview} available at
 521 @uref{http://infocenter.arm.com}.
 522
 523
 524 @node AArch64 Mapping Symbols
 525 @section Mapping Symbols
 526
 527 The AArch64 ELF specification requires that special symbols be inserted
 528 into object files to mark certain features:
 529
 530 @table @code
 531
 532 @cindex @code{$x}
 533 @item $x
 534 At the start of a region of code containing AArch64 instructions.
 535
 536 @cindex @code{$d}
 537 @item $d
 538 At the start of a region of data.
 539
 540 @end table