gas/doc/c-aarch64.texi

   1 @c Copyright (C) 2009-2015 Free Software Foundation, Inc.
   2 @c Contributed by ARM Ltd.
   3 @c This is part of the GAS manual.
   4 @c For copying conditions, see the file as.texinfo.
   5 @c man end
   6
   7 @ifset GENERIC
   8 @page
   9 @node AArch64-Dependent
  10 @chapter AArch64 Dependent Features
  11 @end ifset
  12
  13 @ifclear GENERIC
  14 @node Machine Dependencies
  15 @chapter AArch64 Dependent Features
  16 @end ifclear
  17
  18 @cindex AArch64 support
  19 @menu
  20 * AArch64 Options::              Options
  21 * AArch64 Extensions::           Extensions
  22 * AArch64 Syntax::               Syntax
  23 * AArch64 Floating Point::       Floating Point
  24 * AArch64 Directives::           AArch64 Machine Directives
  25 * AArch64 Opcodes::              Opcodes
  26 * AArch64 Mapping Symbols::      Mapping Symbols
  27 @end menu
  28
  29 @node AArch64 Options
  30 @section Options
  31 @cindex AArch64 options (none)
  32 @cindex options for AArch64 (none)
  33
  34 @c man begin OPTIONS
  35 @table @gcctabopt
  36
  37 @cindex @option{-EB} command line option, AArch64
  38 @item -EB
  39 This option specifies that the output generated by the assembler should
  40 be marked as being encoded for a big-endian processor.
  41
  42 @cindex @option{-EL} command line option, AArch64
  43 @item -EL
  44 This option specifies that the output generated by the assembler should
  45 be marked as being encoded for a little-endian processor.
  46
  47 @cindex @option{-mabi=} command line option, AArch64
  48 @item -mabi=@var{abi}
  49 Specify which ABI the source code uses.  The recognized arguments
  50 are: @code{ilp32} and @code{lp64}, which decides the generated object
  51 file in ELF32 and ELF64 format respectively.  The default is @code{lp64}.
  52
  53 @cindex @option{-mcpu=} command line option, AArch64
  54 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
  55 This option specifies the target processor.  The assembler will issue an error
  56 message if an attempt is made to assemble an instruction which will not execute
  57 on the target processor.  The following processor names are recognized:
  58 @code{cortex-a53},
  59 @code{cortex-a57},
  60 @code{thunderx},
  61 @code{xgene1}
  62 and
  63 @code{xgene2}.
  64 The special name @code{all} may be used to allow the assembler to accept
  65 instructions valid for any supported processor, including all optional
  66 extensions.
  67
  68 In addition to the basic instruction set, the assembler can be told to
  69 accept, or restrict, various extension mnemonics that extend the
  70 processor.  @xref{AArch64 Extensions}.
  71
  72 If some implementations of a particular processor can have an
  73 extension, then then those extensions are automatically enabled.
  74 Consequently, you will not normally have to specify any additional
  75 extensions.
  76
  77 @cindex @option{-march=} command line option, AArch64
  78 @item -march=@var{architecture}[+@var{extension}@dots{}]
  79 This option specifies the target architecture.  The assembler will
  80 issue an error message if an attempt is made to assemble an
  81 instruction which will not execute on the target architecture.  The
  82 only value for @var{architecture} is @code{armv8-a}.
  83
  84 If both @option{-mcpu} and @option{-march} are specified, the
  85 assembler will use the setting for @option{-mcpu}.  If neither are
  86 specified, the assembler will default to @option{-mcpu=all}.
  87
  88 The architecture option can be extended with the same instruction set
  89 extension options as the @option{-mcpu} option.  Unlike
  90 @option{-mcpu}, extensions are not always enabled by default,
  91 @xref{AArch64 Extensions}.
  92
  93 @cindex @code{-mverbose-error} command line option, AArch64
  94 @item -mverbose-error
  95 This option enables verbose error messages for AArch64 gas.  This option
  96 is enabled by default.
  97
  98 @cindex @code{-mno-verbose-error} command line option, AArch64
  99 @item -mno-verbose-error
 100 This option disables verbose error messages in AArch64 gas.
 101
 102 @end table
 103 @c man end
 104
 105 @node AArch64 Extensions
 106 @section Architecture Extensions
 107
 108 The table below lists the permitted architecture extensions that are
 109 supported by the assembler and the conditions under which they are
 110 automatically enabled.
 111
 112 Multiple extensions may be specified, separated by a @code{+}.
 113 Extension mnemonics may also be removed from those the assembler
 114 accepts.  This is done by prepending @code{no} to the option that adds
 115 the extension.  Extensions that are removed must be listed after all
 116 extensions that have been added.
 117
 118 Enabling an extension that requires other extensions will
 119 automatically cause those extensions to be enabled.  Similarly,
 120 disabling an extension that is required by other extensions will
 121 automatically cause those extensions to be disabled.
 122
 123 @multitable @columnfractions .12 .17 .17 .54
 124 @headitem Extension @tab Minimum Architecture @tab Enabled by default
 125  @tab Description
 126 @item @code{crc} @tab ARMv8-A @tab No
 127  @tab Enable CRC instructions.
 128 @item @code{crypto} @tab ARMv8-A @tab No
 129  @tab Enable cryptographic extensions.  This implies @code{fp} and @code{simd}.
 130 @item @code{fp} @tab ARMv8-A @tab ARMv8-A or later
 131  @tab Enable floating-point extensions.
 132 @item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
 133  @tab Enable Advanced SIMD extensions.  This implies @code{fp}.
 134 @end multitable
 135
 136 @node AArch64 Syntax
 137 @section Syntax
 138 @menu
 139 * AArch64-Chars::                Special Characters
 140 * AArch64-Regs::                 Register Names
 141 * AArch64-Relocations::      Relocations
 142 @end menu
 143
 144 @node AArch64-Chars
 145 @subsection Special Characters
 146
 147 @cindex line comment character, AArch64
 148 @cindex AArch64 line comment character
 149 The presence of a @samp{//} on a line indicates the start of a comment
 150 that extends to the end of the current line.  If a @samp{#} appears as
 151 the first character of a line, the whole line is treated as a comment.
 152
 153 @cindex line separator, AArch64
 154 @cindex statement separator, AArch64
 155 @cindex AArch64 line separator
 156 The @samp{;} character can be used instead of a newline to separate
 157 statements.
 158
 159 @cindex immediate character, AArch64
 160 @cindex AArch64 immediate character
 161 The @samp{#} can be optionally used to indicate immediate operands.
 162
 163 @node AArch64-Regs
 164 @subsection Register Names
 165
 166 @cindex AArch64 register names
 167 @cindex register names, AArch64
 168 Please refer to the section @samp{4.4 Register Names} of
 169 @samp{ARMv8 Instruction Set Overview}, which is available at
 170 @uref{http://infocenter.arm.com}.
 171
 172 @node AArch64-Relocations
 173 @subsection Relocations
 174
 175 @cindex relocations, AArch64
 176 @cindex AArch64 relocations
 177 @cindex MOVN, MOVZ and MOVK group relocations, AArch64
 178 Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated
 179 by prefixing the label with @samp{#:abs_g2:} etc.
 180 For example to load the 48-bit absolute address of @var{foo} into x0:
 181
 182 @smallexample
 183         movz x0, #:abs_g2:foo           // bits 32-47, overflow check
 184         movk x0, #:abs_g1_nc:foo        // bits 16-31, no overflow check
 185         movk x0, #:abs_g0_nc:foo        // bits  0-15, no overflow check
 186 @end smallexample
 187
 188 @cindex ADRP, ADD, LDR/STR group relocations, AArch64
 189 Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
 190 instructions can be generated by prefixing the label with
 191 @samp{:pg_hi21:} and @samp{#:lo12:} respectively.
 192
 193 For example to use 33-bit (+/-4GB) pc-relative addressing to
 194 load the address of @var{foo} into x0:
 195
 196 @smallexample
 197         adrp x0, :pg_hi21:foo
 198         add  x0, x0, #:lo12:foo
 199 @end smallexample
 200
 201 Or to load the value of @var{foo} into x0:
 202
 203 @smallexample
 204         adrp x0, :pg_hi21:foo
 205         ldr  x0, [x0, #:lo12:foo]
 206 @end smallexample
 207
 208 Note that @samp{:pg_hi21:} is optional.
 209
 210 @smallexample
 211         adrp x0, foo
 212 @end smallexample
 213
 214 is equivalent to
 215
 216 @smallexample
 217         adrp x0, :pg_hi21:foo
 218 @end smallexample
 219
 220 @node AArch64 Floating Point
 221 @section Floating Point
 222
 223 @cindex floating point, AArch64 (@sc{ieee})
 224 @cindex AArch64 floating point (@sc{ieee})
 225 The AArch64 architecture uses @sc{ieee} floating-point numbers.
 226
 227 @node AArch64 Directives
 228 @section AArch64 Machine Directives
 229
 230 @cindex machine directives, AArch64
 231 @cindex AArch64 machine directives
 232 @table @code
 233
 234 @c AAAAAAAAAAAAAAAAAAAAAAAAA
 235
 236 @cindex @code{.arch} directive, AArch64
 237 @item .arch @var{name}
 238 Select the target architecture.  Valid values for @var{name} are the same as
 239 for the @option{-march} commandline option.
 240
 241 Specifying @code{.arch} clears any previously selected architecture
 242 extensions.
 243
 244 @cindex @code{.arch_extension} directive, AArch64
 245 @item .arch_extension @var{name}
 246 Add or remove an architecture extension to the target architecture.  Valid
 247 values for @var{name} are the same as those accepted as architectural
 248 extensions by the @option{-mcpu} commandline option.
 249
 250 @code{.arch_extension} may be used multiple times to add or remove extensions
 251 incrementally to the architecture being compiled for.
 252
 253 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
 254
 255 @cindex @code{.bss} directive, AArch64
 256 @item .bss
 257 This directive switches to the @code{.bss} section.
 258
 259 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
 260 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
 261 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
 262 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
 263 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
 264 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
 265 @c IIIIIIIIIIIIIIIIIIIIIIIIII
 266 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
 267 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
 268 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
 269
 270 @cindex @code{.ltorg} directive, AArch64
 271 @item .ltorg
 272 This directive causes the current contents of the literal pool to be
 273 dumped into the current section (which is assumed to be the .text
 274 section) at the current location (aligned to a word boundary).
 275 GAS maintains a separate literal pool for each section and each
 276 sub-section.  The @code{.ltorg} directive will only affect the literal
 277 pool of the current section and sub-section.  At the end of assembly
 278 all remaining, un-empty literal pools will automatically be dumped.
 279
 280 Note - older versions of GAS would dump the current literal
 281 pool any time a section change occurred.  This is no longer done, since
 282 it prevents accurate control of the placement of literal pools.
 283
 284 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
 285
 286 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
 287 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
 288
 289 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
 290
 291 @cindex @code{.pool} directive, AArch64
 292 @item .pool
 293 This is a synonym for .ltorg.
 294
 295 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
 296 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
 297
 298 @cindex @code{.req} directive, AArch64
 299 @item @var{name} .req @var{register name}
 300 This creates an alias for @var{register name} called @var{name}.  For
 301 example:
 302
 303 @smallexample
 304         foo .req w0
 305 @end smallexample
 306
 307 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
 308
 309 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
 310
 311 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
 312
 313 @cindex @code{.unreq} directive, AArch64
 314 @item .unreq @var{alias-name}
 315 This undefines a register alias which was previously defined using the
 316 @code{req} directive.  For example:
 317
 318 @smallexample
 319         foo .req w0
 320         .unreq foo
 321 @end smallexample
 322
 323 An error occurs if the name is undefined.  Note - this pseudo op can
 324 be used to delete builtin in register name aliases (eg 'w0').  This
 325 should only be done if it is really necessary.
 326
 327 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
 328
 329 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
 330 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
 331 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
 332 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
 333
 334 @end table
 335
 336 @node AArch64 Opcodes
 337 @section Opcodes
 338
 339 @cindex AArch64 opcodes
 340 @cindex opcodes for AArch64
 341 GAS implements all the standard AArch64 opcodes.  It also
 342 implements several pseudo opcodes, including several synthetic load
 343 instructions.
 344
 345 @table @code
 346
 347 @cindex @code{LDR reg,=<expr>} pseudo op, AArch64
 348 @item LDR =
 349 @smallexample
 350   ldr <register> , =<expression>
 351 @end smallexample
 352
 353 The constant expression will be placed into the nearest literal pool (if it not
 354 already there) and a PC-relative LDR instruction will be generated.
 355
 356 @end table
 357
 358 For more information on the AArch64 instruction set and assembly language
 359 notation, see @samp{ARMv8 Instruction Set Overview} available at
 360 @uref{http://infocenter.arm.com}.
 361
 362
 363 @node AArch64 Mapping Symbols
 364 @section Mapping Symbols
 365
 366 The AArch64 ELF specification requires that special symbols be inserted
 367 into object files to mark certain features:
 368
 369 @table @code
 370
 371 @cindex @code{$x}
 372 @item $x
 373 At the start of a region of code containing AArch64 instructions.
 374
 375 @cindex @code{$d}
 376 @item $d
 377 At the start of a region of data.
 378
 379 @end table