gas/doc/c-aarch64.texi

   1 @c Copyright (C) 2009-2021 Free Software Foundation, Inc.
   2 @c Contributed by ARM Ltd.
   3 @c This is part of the GAS manual.
   4 @c For copying conditions, see the file as.texinfo.
   5 @c man end
   6
   7 @ifset GENERIC
   8 @page
   9 @node AArch64-Dependent
  10 @chapter AArch64 Dependent Features
  11 @end ifset
  12
  13 @ifclear GENERIC
  14 @node Machine Dependencies
  15 @chapter AArch64 Dependent Features
  16 @end ifclear
  17
  18 @cindex AArch64 support
  19 @menu
  20 * AArch64 Options::              Options
  21 * AArch64 Extensions::           Extensions
  22 * AArch64 Syntax::               Syntax
  23 * AArch64 Floating Point::       Floating Point
  24 * AArch64 Directives::           AArch64 Machine Directives
  25 * AArch64 Opcodes::              Opcodes
  26 * AArch64 Mapping Symbols::      Mapping Symbols
  27 @end menu
  28
  29 @node AArch64 Options
  30 @section Options
  31 @cindex AArch64 options (none)
  32 @cindex options for AArch64 (none)
  33
  34 @c man begin OPTIONS
  35 @table @gcctabopt
  36
  37 @cindex @option{-EB} command-line option, AArch64
  38 @item -EB
  39 This option specifies that the output generated by the assembler should
  40 be marked as being encoded for a big-endian processor.
  41
  42 @cindex @option{-EL} command-line option, AArch64
  43 @item -EL
  44 This option specifies that the output generated by the assembler should
  45 be marked as being encoded for a little-endian processor.
  46
  47 @cindex @option{-mabi=} command-line option, AArch64
  48 @item -mabi=@var{abi}
  49 Specify which ABI the source code uses.  The recognized arguments
  50 are: @code{ilp32} and @code{lp64}, which decides the generated object
  51 file in ELF32 and ELF64 format respectively.  The default is @code{lp64}.
  52
  53 @cindex @option{-mcpu=} command-line option, AArch64
  54 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
  55 This option specifies the target processor.  The assembler will issue an error
  56 message if an attempt is made to assemble an instruction which will not execute
  57 on the target processor.  The following processor names are recognized:
  58 @code{cortex-a34},
  59 @code{cortex-a35},
  60 @code{cortex-a53},
  61 @code{cortex-a55},
  62 @code{cortex-a57},
  63 @code{cortex-a65},
  64 @code{cortex-a65ae},
  65 @code{cortex-a72},
  66 @code{cortex-a73},
  67 @code{cortex-a75},
  68 @code{cortex-a76},
  69 @code{cortex-a76ae},
  70 @code{cortex-a77},
  71 @code{cortex-a78},
  72 @code{cortex-a78ae},
  73 @code{cortex-a78c},
  74 @code{cortex-a510},
  75 @code{ares},
  76 @code{exynos-m1},
  77 @code{falkor},
  78 @code{neoverse-n1},
  79 @code{neoverse-n2},
  80 @code{neoverse-e1},
  81 @code{neoverse-v1},
  82 @code{qdf24xx},
  83 @code{saphira},
  84 @code{thunderx},
  85 @code{vulcan},
  86 @code{xgene1}
  87 @code{xgene2},
  88 @code{cortex-r82},
  89 and
  90 @code{cortex-x1}.
  91 The special name @code{all} may be used to allow the assembler to accept
  92 instructions valid for any supported processor, including all optional
  93 extensions.
  94
  95 In addition to the basic instruction set, the assembler can be told to
  96 accept, or restrict, various extension mnemonics that extend the
  97 processor.  @xref{AArch64 Extensions}.
  98
  99 If some implementations of a particular processor can have an
 100 extension, then then those extensions are automatically enabled.
 101 Consequently, you will not normally have to specify any additional
 102 extensions.
 103
 104 @cindex @option{-march=} command-line option, AArch64
 105 @item -march=@var{architecture}[+@var{extension}@dots{}]
 106 This option specifies the target architecture.  The assembler will
 107 issue an error message if an attempt is made to assemble an
 108 instruction which will not execute on the target architecture.  The
 109 following architecture names are recognized: @code{armv8-a},
 110 @code{armv8.1-a}, @code{armv8.2-a}, @code{armv8.3-a}, @code{armv8.4-a}
 111 @code{armv8.5-a}, @code{armv8.6-a}, @code{armv8.7-a}, @code{armv8-r}, and
 112 @code{armv9-a}.
 113
 114 If both @option{-mcpu} and @option{-march} are specified, the
 115 assembler will use the setting for @option{-mcpu}.  If neither are
 116 specified, the assembler will default to @option{-mcpu=all}.
 117
 118 The architecture option can be extended with the same instruction set
 119 extension options as the @option{-mcpu} option.  Unlike
 120 @option{-mcpu}, extensions are not always enabled by default,
 121 @xref{AArch64 Extensions}.
 122
 123 @cindex @code{-mverbose-error} command-line option, AArch64
 124 @item -mverbose-error
 125 This option enables verbose error messages for AArch64 gas.  This option
 126 is enabled by default.
 127
 128 @cindex @code{-mno-verbose-error} command-line option, AArch64
 129 @item -mno-verbose-error
 130 This option disables verbose error messages in AArch64 gas.
 131
 132 @end table
 133 @c man end
 134
 135 @node AArch64 Extensions
 136 @section Architecture Extensions
 137
 138 The table below lists the permitted architecture extensions that are
 139 supported by the assembler and the conditions under which they are
 140 automatically enabled.
 141
 142 Multiple extensions may be specified, separated by a @code{+}.
 143 Extension mnemonics may also be removed from those the assembler
 144 accepts.  This is done by prepending @code{no} to the option that adds
 145 the extension.  Extensions that are removed must be listed after all
 146 extensions that have been added.
 147
 148 Enabling an extension that requires other extensions will
 149 automatically cause those extensions to be enabled.  Similarly,
 150 disabling an extension that is required by other extensions will
 151 automatically cause those extensions to be disabled.
 152
 153 @multitable @columnfractions .12 .17 .17 .54
 154 @headitem Extension @tab Minimum Architecture @tab Enabled by default
 155  @tab Description
 156 @item @code{aes} @tab ARMv8-A @tab No
 157  @tab Enable the AES cryptographic extensions. This implies @code{fp} and
 158  @code{simd}.
 159 @item @code{bf16} @tab ARMv8.2-A @tab ARMv8.6-A or later
 160  @tab Enable BFloat16 extension.
 161 @item @code{compnum} @tab ARMv8.2-A @tab ARMv8.3-A or later
 162  @tab Enable the complex number SIMD extensions.  This implies @code{fp16} and
 163  @code{simd}.
 164 @item @code{crc} @tab ARMv8-A @tab ARMv8.1-A or later
 165  @tab Enable CRC instructions.
 166 @item @code{crypto} @tab ARMv8-A @tab No
 167  @tab Enable cryptographic extensions.  This implies @code{fp}, @code{simd},
 168  @code{aes} and @code{sha2}.
 169 @item @code{dotprod} @tab ARMv8.2-A @tab ARMv8.4-A or later
 170  @tab Enable the Dot Product extension.  This implies @code{simd}.
 171 @item @code{f32mm} @tab ARMv8.2-A @tab No
 172  @tab Enable F32 Matrix Multiply extension.  This implies @code{sve}.
 173 @item @code{f64mm} @tab ARMv8.2-A @tab No
 174  @tab Enable F64 Matrix Multiply extension.  This implies @code{sve}.
 175 @item @code{flagm} @tab ARMv8-A @tab ARMv8.4-A or later
 176  @tab Enable Flag Manipulation instructions.
 177 @item @code{fp16fml} @tab ARMv8.2-A @tab ARMv8.4-A or later
 178  @tab Enable ARMv8.2 16-bit floating-point multiplication variant support. This
 179  implies @code{fp} and  @code{fp16}.
 180 @item @code{fp16} @tab ARMv8.2-A @tab ARMv8.2-A or later
 181  @tab Enable ARMv8.2 16-bit floating-point support.  This implies @code{fp}.
 182 @item @code{fp} @tab ARMv8-A @tab ARMv8-A or later
 183  @tab Enable floating-point extensions.
 184 @item @code{i8mm} @tab ARMv8.2-A @tab ARMv8.6-A or later
 185  @tab Enable Int8 Matrix Multiply extension.
 186 @item @code{lor} @tab ARMv8-A @tab ARMv8.1-A or later
 187  @tab Enable Limited Ordering Regions extensions.
 188 @item @code{ls64} @tab ARMv8.6-A @tab ARMv8.7-A or later
 189  @tab Enable 64 Byte Loads/Stores.
 190 @item @code{lse} @tab ARMv8-A @tab ARMv8.1-A or later
 191  @tab Enable Large System extensions.
 192 @item @code{memtag} @tab ARMv8.5-A @tab No
 193  @tab Enable ARMv8.5-A Memory Tagging Extensions.
 194 @item @code{pan} @tab ARMv8-A @tab ARMv8.1-A or later
 195  @tab Enable Privileged Access Never support.
 196 @item @code{pauth} @tab ARMv8-A @tab No
 197  @tab Enable Pointer Authentication.
 198 @item @code{predres} @tab ARMv8-A @tab ARMv8.5-A or later
 199  @tab Enable the Execution and Data and Prediction instructions.
 200 @item @code{profile} @tab ARMv8.2-A @tab No
 201  @tab Enable statistical profiling extensions.
 202 @item @code{ras} @tab ARMv8-A @tab ARMv8.2-A or later
 203  @tab Enable the Reliability, Availability and Serviceability extension.
 204 @item @code{rcpc} @tab ARMv8.2-A @tab ARMv8.3-A or later
 205  @tab Enable the weak release consistency extension.
 206 @item @code{rdma} @tab ARMv8-A @tab ARMv8.1-A or later
 207  @tab Enable ARMv8.1 Advanced SIMD extensions.  This implies @code{simd}.
 208 @item @code{rng} @tab ARMv8.5-A @tab No
 209  @tab Enable ARMv8.5-A random number instructions.
 210 @item @code{sb} @tab ARMv8-A @tab ARMv8.5-A or later
 211  @tab Enable the speculation barrier instruction sb.
 212 @item @code{sha2} @tab ARMv8-A @tab No
 213  @tab Enable the SHA2 cryptographic extensions. This implies @code{fp} and
 214  @code{simd}.
 215 @item @code{sha3} @tab ARMv8.2-A @tab No
 216  @tab Enable the ARMv8.2-A SHA2 and SHA3 cryptographic extensions. This implies
 217  @code{fp}, @code{simd} and @code{sha2}.
 218 @item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
 219  @tab Enable Advanced SIMD extensions.  This implies @code{fp}.
 220 @item @code{sm4} @tab ARMv8.2-A @tab No
 221  @tab Enable the ARMv8.2-A SM3 and SM4 cryptographic extensions. This implies
 222  @code{fp} and @code{simd}.
 223 @item @code{ssbs} @tab ARMv8-A @tab ARMv8.5-A or later
 224  @tab Enable Speculative Store Bypassing Safe state read and write.
 225 @item @code{sve} @tab ARMv8.2-A @tab Armv9-A or later
 226  @tab Enable the Scalable Vector Extensions.  This implies @code{fp16},
 227  @code{simd} and @code{compnum}.
 228 @item @code{sve2} @tab ARMv8-A @tab Armv9-A or later
 229  @tab Enable the SVE2 Extension.  This implies @code{sve}.
 230 @item @code{sve2-aes} @tab ARMv8-A @tab No
 231  @tab Enable SVE2 AES Extension.  This also enables the .Q->.B form of the
 232  @code{pmullt} and @code{pmullb} instructions.  This implies @code{aes} and
 233  @code{sve2}.
 234 @item @code{sve2-bitperm} @tab ARMv8-A @tab No
 235  @tab Enable SVE2 BITPERM Extension.
 236 @item @code{sve2-sha3} @tab ARMv8-A @tab No
 237  @tab Enable SVE2 SHA3 Extension.  This implies @code{sha3} and @code{sve2}.
 238 @item @code{sve2-sm4} @tab ARMv8-A @tab No
 239  @tab Enable SVE2 SM4 Extension.  This implies @code{sm4} and @code{sve2}.
 240 @item @code{tme} @tab ARMv8-A @tab No
 241  @tab Enable Transactional Memory Extensions.
 242 @end multitable
 243
 244 @node AArch64 Syntax
 245 @section Syntax
 246 @menu
 247 * AArch64-Chars::                Special Characters
 248 * AArch64-Regs::                 Register Names
 249 * AArch64-Relocations::      Relocations
 250 @end menu
 251
 252 @node AArch64-Chars
 253 @subsection Special Characters
 254
 255 @cindex line comment character, AArch64
 256 @cindex AArch64 line comment character
 257 The presence of a @samp{//} on a line indicates the start of a comment
 258 that extends to the end of the current line.  If a @samp{#} appears as
 259 the first character of a line, the whole line is treated as a comment.
 260
 261 @cindex line separator, AArch64
 262 @cindex statement separator, AArch64
 263 @cindex AArch64 line separator
 264 The @samp{;} character can be used instead of a newline to separate
 265 statements.
 266
 267 @cindex immediate character, AArch64
 268 @cindex AArch64 immediate character
 269 The @samp{#} can be optionally used to indicate immediate operands.
 270
 271 @node AArch64-Regs
 272 @subsection Register Names
 273
 274 @cindex AArch64 register names
 275 @cindex register names, AArch64
 276 Please refer to the section @samp{4.4 Register Names} of
 277 @samp{ARMv8 Instruction Set Overview}, which is available at
 278 @uref{http://infocenter.arm.com}.
 279
 280 @node AArch64-Relocations
 281 @subsection Relocations
 282
 283 @cindex relocations, AArch64
 284 @cindex AArch64 relocations
 285 @cindex MOVN, MOVZ and MOVK group relocations, AArch64
 286 Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated
 287 by prefixing the label with @samp{#:abs_g2:} etc.
 288 For example to load the 48-bit absolute address of @var{foo} into x0:
 289
 290 @smallexample
 291         movz x0, #:abs_g2:foo           // bits 32-47, overflow check
 292         movk x0, #:abs_g1_nc:foo        // bits 16-31, no overflow check
 293         movk x0, #:abs_g0_nc:foo        // bits  0-15, no overflow check
 294 @end smallexample
 295
 296 @cindex ADRP, ADD, LDR/STR group relocations, AArch64
 297 Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
 298 instructions can be generated by prefixing the label with
 299 @samp{:pg_hi21:} and @samp{#:lo12:} respectively.
 300
 301 For example to use 33-bit (+/-4GB) pc-relative addressing to
 302 load the address of @var{foo} into x0:
 303
 304 @smallexample
 305         adrp x0, :pg_hi21:foo
 306         add  x0, x0, #:lo12:foo
 307 @end smallexample
 308
 309 Or to load the value of @var{foo} into x0:
 310
 311 @smallexample
 312         adrp x0, :pg_hi21:foo
 313         ldr  x0, [x0, #:lo12:foo]
 314 @end smallexample
 315
 316 Note that @samp{:pg_hi21:} is optional.
 317
 318 @smallexample
 319         adrp x0, foo
 320 @end smallexample
 321
 322 is equivalent to
 323
 324 @smallexample
 325         adrp x0, :pg_hi21:foo
 326 @end smallexample
 327
 328 @node AArch64 Floating Point
 329 @section Floating Point
 330
 331 @cindex floating point, AArch64 (@sc{ieee})
 332 @cindex AArch64 floating point (@sc{ieee})
 333 The AArch64 architecture uses @sc{ieee} floating-point numbers.
 334
 335 @node AArch64 Directives
 336 @section AArch64 Machine Directives
 337
 338 @cindex machine directives, AArch64
 339 @cindex AArch64 machine directives
 340 @table @code
 341
 342 @c AAAAAAAAAAAAAAAAAAAAAAAAA
 343
 344 @cindex @code{.arch} directive, AArch64
 345 @item .arch @var{name}
 346 Select the target architecture.  Valid values for @var{name} are the same as
 347 for the @option{-march} command-line option.
 348
 349 Specifying @code{.arch} clears any previously selected architecture
 350 extensions.
 351
 352 @cindex @code{.arch_extension} directive, AArch64
 353 @item .arch_extension @var{name}
 354 Add or remove an architecture extension to the target architecture.  Valid
 355 values for @var{name} are the same as those accepted as architectural
 356 extensions by the @option{-mcpu} command-line option.
 357
 358 @code{.arch_extension} may be used multiple times to add or remove extensions
 359 incrementally to the architecture being compiled for.
 360
 361 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
 362
 363 @cindex @code{.bss} directive, AArch64
 364 @item .bss
 365 This directive switches to the @code{.bss} section.
 366
 367 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
 368
 369 @cindex @code{.cpu} directive, AArch64
 370 @item .cpu @var{name}
 371 Set the target processor.  Valid values for @var{name} are the same as
 372 those accepted by the @option{-mcpu=} command-line option.
 373
 374 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
 375
 376 @cindex @code{.dword} directive, AArch64
 377 @item .dword @var{expressions}
 378 The @code{.dword} directive produces 64 bit values.
 379
 380 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
 381
 382 @cindex @code{.even} directive, AArch64
 383 @item .even
 384 The @code{.even} directive aligns the output on the next even byte
 385 boundary.
 386
 387 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
 388
 389 @cindex @code{.float16} directive, AArch64
 390 @item .float16 @var{value [,...,value_n]}
 391 Place the half precision floating point representation of one or more
 392 floating-point values into the current section.
 393 The format used to encode the floating point values is always the
 394 IEEE 754-2008 half precision floating point format.
 395
 396 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
 397 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
 398 @c IIIIIIIIIIIIIIIIIIIIIIIIII
 399
 400 @cindex @code{.inst} directive, AArch64
 401 @item .inst @var{expressions}
 402 Inserts the expressions into the output as if they were instructions,
 403 rather than data.
 404
 405 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
 406 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
 407 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
 408
 409 @cindex @code{.ltorg} directive, AArch64
 410 @item .ltorg
 411 This directive causes the current contents of the literal pool to be
 412 dumped into the current section (which is assumed to be the .text
 413 section) at the current location (aligned to a word boundary).
 414 GAS maintains a separate literal pool for each section and each
 415 sub-section.  The @code{.ltorg} directive will only affect the literal
 416 pool of the current section and sub-section.  At the end of assembly
 417 all remaining, un-empty literal pools will automatically be dumped.
 418
 419 Note - older versions of GAS would dump the current literal
 420 pool any time a section change occurred.  This is no longer done, since
 421 it prevents accurate control of the placement of literal pools.
 422
 423 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
 424
 425 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
 426 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
 427
 428 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
 429
 430 @cindex @code{.pool} directive, AArch64
 431 @item .pool
 432 This is a synonym for .ltorg.
 433
 434 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
 435 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
 436
 437 @cindex @code{.req} directive, AArch64
 438 @item @var{name} .req @var{register name}
 439 This creates an alias for @var{register name} called @var{name}.  For
 440 example:
 441
 442 @smallexample
 443         foo .req w0
 444 @end smallexample
 445
 446 ip0, ip1, lr and fp are automatically defined to
 447 alias to X16, X17, X30 and X29 respectively.
 448
 449 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
 450
 451 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
 452
 453 @cindex @code{.tlsdescadd} directive, AArch64
 454 @item   @code{.tlsdescadd}
 455 Emits a TLSDESC_ADD reloc on the next instruction.
 456
 457 @cindex @code{.tlsdesccall} directive, AArch64
 458 @item   @code{.tlsdesccall}
 459 Emits a TLSDESC_CALL reloc on the next instruction.
 460
 461 @cindex @code{.tlsdescldr} directive, AArch64
 462 @item   @code{.tlsdescldr}
 463 Emits a TLSDESC_LDR reloc on the next instruction.
 464
 465 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
 466
 467 @cindex @code{.unreq} directive, AArch64
 468 @item .unreq @var{alias-name}
 469 This undefines a register alias which was previously defined using the
 470 @code{req} directive.  For example:
 471
 472 @smallexample
 473         foo .req w0
 474         .unreq foo
 475 @end smallexample
 476
 477 An error occurs if the name is undefined.  Note - this pseudo op can
 478 be used to delete builtin in register name aliases (eg 'w0').  This
 479 should only be done if it is really necessary.
 480
 481 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
 482
 483 @cindex @code{.variant_pcs} directive, AArch64
 484 @item .variant_pcs @var{symbol}
 485 This directive marks @var{symbol} referencing a function that may
 486 follow a variant procedure call standard with different register
 487 usage convention from the base procedure call standard.
 488
 489 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
 490 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
 491
 492 @cindex @code{.xword} directive, AArch64
 493 @item .xword @var{expressions}
 494 The @code{.xword} directive produces 64 bit values.  This is the same
 495 as the @code{.dword} directive.
 496
 497 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
 498 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
 499
 500 @cindex @code{.cfi_b_key_frame} directive, AArch64
 501 @item   @code{.cfi_b_key_frame}
 502 The @code{.cfi_b_key_frame} directive inserts a 'B' character into the CIE
 503 corresponding to the current frame's FDE, meaning that its return address has
 504 been signed with the B-key.  If two frames are signed with differing keys then
 505 they will not share the same CIE.  This information is intended to be used by
 506 the stack unwinder in order to properly authenticate return addresses.
 507
 508 @end table
 509
 510 @node AArch64 Opcodes
 511 @section Opcodes
 512
 513 @cindex AArch64 opcodes
 514 @cindex opcodes for AArch64
 515 GAS implements all the standard AArch64 opcodes.  It also
 516 implements several pseudo opcodes, including several synthetic load
 517 instructions.
 518
 519 @table @code
 520
 521 @cindex @code{LDR reg,=<expr>} pseudo op, AArch64
 522 @item LDR =
 523 @smallexample
 524   ldr <register> , =<expression>
 525 @end smallexample
 526
 527 The constant expression will be placed into the nearest literal pool (if it not
 528 already there) and a PC-relative LDR instruction will be generated.
 529
 530 @end table
 531
 532 For more information on the AArch64 instruction set and assembly language
 533 notation, see @samp{ARMv8 Instruction Set Overview} available at
 534 @uref{http://infocenter.arm.com}.
 535
 536
 537 @node AArch64 Mapping Symbols
 538 @section Mapping Symbols
 539
 540 The AArch64 ELF specification requires that special symbols be inserted
 541 into object files to mark certain features:
 542
 543 @table @code
 544
 545 @cindex @code{$x}
 546 @item $x
 547 At the start of a region of code containing AArch64 instructions.
 548
 549 @cindex @code{$d}
 550 @item $d
 551 At the start of a region of data.
 552
 553 @end table