gas/doc/c-aarch64.texi

   1 @c Copyright (C) 2009-2020 Free Software Foundation, Inc.
   2 @c Contributed by ARM Ltd.
   3 @c This is part of the GAS manual.
   4 @c For copying conditions, see the file as.texinfo.
   5 @c man end
   6
   7 @ifset GENERIC
   8 @page
   9 @node AArch64-Dependent
  10 @chapter AArch64 Dependent Features
  11 @end ifset
  12
  13 @ifclear GENERIC
  14 @node Machine Dependencies
  15 @chapter AArch64 Dependent Features
  16 @end ifclear
  17
  18 @cindex AArch64 support
  19 @menu
  20 * AArch64 Options::              Options
  21 * AArch64 Extensions::           Extensions
  22 * AArch64 Syntax::               Syntax
  23 * AArch64 Floating Point::       Floating Point
  24 * AArch64 Directives::           AArch64 Machine Directives
  25 * AArch64 Opcodes::              Opcodes
  26 * AArch64 Mapping Symbols::      Mapping Symbols
  27 @end menu
  28
  29 @node AArch64 Options
  30 @section Options
  31 @cindex AArch64 options (none)
  32 @cindex options for AArch64 (none)
  33
  34 @c man begin OPTIONS
  35 @table @gcctabopt
  36
  37 @cindex @option{-EB} command-line option, AArch64
  38 @item -EB
  39 This option specifies that the output generated by the assembler should
  40 be marked as being encoded for a big-endian processor.
  41
  42 @cindex @option{-EL} command-line option, AArch64
  43 @item -EL
  44 This option specifies that the output generated by the assembler should
  45 be marked as being encoded for a little-endian processor.
  46
  47 @cindex @option{-mabi=} command-line option, AArch64
  48 @item -mabi=@var{abi}
  49 Specify which ABI the source code uses.  The recognized arguments
  50 are: @code{ilp32} and @code{lp64}, which decides the generated object
  51 file in ELF32 and ELF64 format respectively.  The default is @code{lp64}.
  52
  53 @cindex @option{-mcpu=} command-line option, AArch64
  54 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
  55 This option specifies the target processor.  The assembler will issue an error
  56 message if an attempt is made to assemble an instruction which will not execute
  57 on the target processor.  The following processor names are recognized:
  58 @code{cortex-a34},
  59 @code{cortex-a35},
  60 @code{cortex-a53},
  61 @code{cortex-a55},
  62 @code{cortex-a57},
  63 @code{cortex-a65},
  64 @code{cortex-a65ae},
  65 @code{cortex-a72},
  66 @code{cortex-a73},
  67 @code{cortex-a75},
  68 @code{cortex-a76},
  69 @code{cortex-a76ae},
  70 @code{cortex-a77},
  71 @code{ares},
  72 @code{exynos-m1},
  73 @code{falkor},
  74 @code{neoverse-n1},
  75 @code{neoverse-n2},
  76 @code{neoverse-e1},
  77 @code{neoverse-v1},
  78 @code{qdf24xx},
  79 @code{saphira},
  80 @code{thunderx},
  81 @code{vulcan},
  82 @code{xgene1}
  83 @code{xgene2},
  84 @code{cortex-r82},
  85 and
  86 @code{cortex-x1}.
  87 The special name @code{all} may be used to allow the assembler to accept
  88 instructions valid for any supported processor, including all optional
  89 extensions.
  90
  91 In addition to the basic instruction set, the assembler can be told to
  92 accept, or restrict, various extension mnemonics that extend the
  93 processor.  @xref{AArch64 Extensions}.
  94
  95 If some implementations of a particular processor can have an
  96 extension, then then those extensions are automatically enabled.
  97 Consequently, you will not normally have to specify any additional
  98 extensions.
  99
 100 @cindex @option{-march=} command-line option, AArch64
 101 @item -march=@var{architecture}[+@var{extension}@dots{}]
 102 This option specifies the target architecture.  The assembler will
 103 issue an error message if an attempt is made to assemble an
 104 instruction which will not execute on the target architecture.  The
 105 following architecture names are recognized: @code{armv8-a},
 106 @code{armv8.1-a}, @code{armv8.2-a}, @code{armv8.3-a}, @code{armv8.4-a}
 107 @code{armv8.5-a}, @code{armv8.6-a}, and @code{armv8-r}.
 108
 109 If both @option{-mcpu} and @option{-march} are specified, the
 110 assembler will use the setting for @option{-mcpu}.  If neither are
 111 specified, the assembler will default to @option{-mcpu=all}.
 112
 113 The architecture option can be extended with the same instruction set
 114 extension options as the @option{-mcpu} option.  Unlike
 115 @option{-mcpu}, extensions are not always enabled by default,
 116 @xref{AArch64 Extensions}.
 117
 118 @cindex @code{-mverbose-error} command-line option, AArch64
 119 @item -mverbose-error
 120 This option enables verbose error messages for AArch64 gas.  This option
 121 is enabled by default.
 122
 123 @cindex @code{-mno-verbose-error} command-line option, AArch64
 124 @item -mno-verbose-error
 125 This option disables verbose error messages in AArch64 gas.
 126
 127 @end table
 128 @c man end
 129
 130 @node AArch64 Extensions
 131 @section Architecture Extensions
 132
 133 The table below lists the permitted architecture extensions that are
 134 supported by the assembler and the conditions under which they are
 135 automatically enabled.
 136
 137 Multiple extensions may be specified, separated by a @code{+}.
 138 Extension mnemonics may also be removed from those the assembler
 139 accepts.  This is done by prepending @code{no} to the option that adds
 140 the extension.  Extensions that are removed must be listed after all
 141 extensions that have been added.
 142
 143 Enabling an extension that requires other extensions will
 144 automatically cause those extensions to be enabled.  Similarly,
 145 disabling an extension that is required by other extensions will
 146 automatically cause those extensions to be disabled.
 147
 148 @multitable @columnfractions .12 .17 .17 .54
 149 @headitem Extension @tab Minimum Architecture @tab Enabled by default
 150  @tab Description
 151 @item @code{i8mm} @tab ARMv8.2-A @tab ARMv8.6-A or later
 152  @tab Enable Int8 Matrix Multiply extension.
 153 @item @code{f32mm} @tab ARMv8.2-A @tab No
 154  @tab Enable F32 Matrix Multiply extension.
 155 @item @code{f64mm} @tab ARMv8.2-A @tab No
 156  @tab Enable F64 Matrix Multiply extension.
 157 @item @code{bf16} @tab ARMv8.2-A @tab ARMv8.6-A or later
 158  @tab Enable BFloat16 extension.
 159 @item @code{compnum} @tab ARMv8.2-A @tab ARMv8.3-A or later
 160  @tab Enable the complex number SIMD extensions.  This implies
 161  @code{fp16} and @code{simd}.
 162 @item @code{crc} @tab ARMv8-A @tab ARMv8.1-A or later
 163  @tab Enable CRC instructions.
 164 @item @code{crypto} @tab ARMv8-A @tab No
 165  @tab Enable cryptographic extensions.  This implies @code{fp}, @code{simd}, @code{aes} and @code{sha2}.
 166 @item @code{aes} @tab ARMv8-A @tab No
 167  @tab Enable the AES cryptographic extensions. This implies @code{fp} and @code{simd}.
 168 @item @code{sha2} @tab ARMv8-A @tab No
 169  @tab Enable the SHA2 cryptographic extensions. This implies @code{fp} and @code{simd}.
 170 @item @code{sha3} @tab ARMv8.2-A @tab No
 171  @tab Enable the ARMv8.2-A SHA2 and SHA3 cryptographic extensions. This implies @code{fp}, @code{simd} and @code{sha2}.
 172 @item @code{sm4} @tab ARMv8.2-A @tab No
 173  @tab Enable the ARMv8.2-A SM3 and SM4 cryptographic extensions. This implies @code{fp} and @code{simd}.
 174 @item @code{fp} @tab ARMv8-A @tab ARMv8-A or later
 175  @tab Enable floating-point extensions.
 176 @item @code{fp16} @tab ARMv8.2-A @tab ARMv8.2-A or later
 177  @tab Enable ARMv8.2 16-bit floating-point support.  This implies
 178  @code{fp}.
 179 @item @code{lor} @tab ARMv8-A @tab ARMv8.1-A or later
 180  @tab Enable Limited Ordering Regions extensions.
 181 @item @code{lse} @tab ARMv8-A @tab ARMv8.1-A or later
 182  @tab Enable Large System extensions.
 183 @item @code{pan} @tab ARMv8-A @tab ARMv8.1-A or later
 184  @tab Enable Privileged Access Never support.
 185 @item @code{profile} @tab ARMv8.2-A @tab No
 186  @tab Enable statistical profiling extensions.
 187 @item @code{ras} @tab ARMv8-A @tab ARMv8.2-A or later
 188  @tab Enable the Reliability, Availability and Serviceability
 189  extension.
 190 @item @code{rcpc} @tab ARMv8.2-A @tab ARMv8.3-A or later
 191  @tab Enable the weak release consistency extension.
 192 @item @code{rdma} @tab ARMv8-A @tab ARMv8.1-A or later
 193  @tab Enable ARMv8.1 Advanced SIMD extensions.  This implies @code{simd}.
 194 @item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
 195  @tab Enable Advanced SIMD extensions.  This implies @code{fp}.
 196 @item @code{sve} @tab ARMv8.2-A @tab No
 197  @tab Enable the Scalable Vector Extensions.  This implies @code{fp16},
 198  @code{simd} and @code{compnum}.
 199 @item @code{dotprod} @tab ARMv8.2-A @tab ARMv8.4-A or later
 200  @tab Enable the Dot Product extension.  This implies @code{simd}.
 201 @item @code{fp16fml} @tab ARMv8.2-A @tab ARMv8.4-A or later
 202  @tab Enable ARMv8.2 16-bit floating-point multiplication variant support.
 203  This implies @code{fp16}.
 204 @item @code{sb} @tab ARMv8-A @tab ARMv8.5-A or later
 205  @tab Enable the speculation barrier instruction sb.
 206 @item @code{predres} @tab ARMv8-A @tab ARMv8.5-A or later
 207  @tab Enable the Execution and Data and Prediction instructions.
 208 @item @code{rng} @tab ARMv8.5-A @tab No
 209  @tab Enable ARMv8.5-A random number instructions.
 210 @item @code{ssbs} @tab ARMv8-A @tab ARMv8.5-A or later
 211  @tab Enable Speculative Store Bypassing Safe state read and write.
 212 @item @code{memtag} @tab ARMv8.5-A @tab No
 213  @tab Enable ARMv8.5-A Memory Tagging Extensions.
 214 @item @code{tme} @tab ARMv8-A @tab No
 215  @tab Enable Transactional Memory Extensions.
 216 @item @code{sve2} @tab ARMv8-A @tab No
 217  @tab Enable the SVE2 Extension.
 218 @item @code{sve2-bitperm} @tab ARMv8-A @tab No
 219  @tab Enable SVE2 BITPERM Extension.
 220 @item @code{sve2-sm4} @tab ARMv8-A @tab No
 221  @tab Enable SVE2 SM4 Extension.
 222 @item @code{sve2-aes} @tab ARMv8-A @tab No
 223  @tab Enable SVE2 AES Extension.  This also enables the .Q->.B form of the
 224  @code{pmullt} and @code{pmullb} instructions.
 225 @item @code{sve2-sha3} @tab ARMv8-A @tab No
 226  @tab Enable SVE2 SHA3 Extension.
 227 @end multitable
 228
 229 @node AArch64 Syntax
 230 @section Syntax
 231 @menu
 232 * AArch64-Chars::                Special Characters
 233 * AArch64-Regs::                 Register Names
 234 * AArch64-Relocations::      Relocations
 235 @end menu
 236
 237 @node AArch64-Chars
 238 @subsection Special Characters
 239
 240 @cindex line comment character, AArch64
 241 @cindex AArch64 line comment character
 242 The presence of a @samp{//} on a line indicates the start of a comment
 243 that extends to the end of the current line.  If a @samp{#} appears as
 244 the first character of a line, the whole line is treated as a comment.
 245
 246 @cindex line separator, AArch64
 247 @cindex statement separator, AArch64
 248 @cindex AArch64 line separator
 249 The @samp{;} character can be used instead of a newline to separate
 250 statements.
 251
 252 @cindex immediate character, AArch64
 253 @cindex AArch64 immediate character
 254 The @samp{#} can be optionally used to indicate immediate operands.
 255
 256 @node AArch64-Regs
 257 @subsection Register Names
 258
 259 @cindex AArch64 register names
 260 @cindex register names, AArch64
 261 Please refer to the section @samp{4.4 Register Names} of
 262 @samp{ARMv8 Instruction Set Overview}, which is available at
 263 @uref{http://infocenter.arm.com}.
 264
 265 @node AArch64-Relocations
 266 @subsection Relocations
 267
 268 @cindex relocations, AArch64
 269 @cindex AArch64 relocations
 270 @cindex MOVN, MOVZ and MOVK group relocations, AArch64
 271 Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated
 272 by prefixing the label with @samp{#:abs_g2:} etc.
 273 For example to load the 48-bit absolute address of @var{foo} into x0:
 274
 275 @smallexample
 276         movz x0, #:abs_g2:foo           // bits 32-47, overflow check
 277         movk x0, #:abs_g1_nc:foo        // bits 16-31, no overflow check
 278         movk x0, #:abs_g0_nc:foo        // bits  0-15, no overflow check
 279 @end smallexample
 280
 281 @cindex ADRP, ADD, LDR/STR group relocations, AArch64
 282 Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
 283 instructions can be generated by prefixing the label with
 284 @samp{:pg_hi21:} and @samp{#:lo12:} respectively.
 285
 286 For example to use 33-bit (+/-4GB) pc-relative addressing to
 287 load the address of @var{foo} into x0:
 288
 289 @smallexample
 290         adrp x0, :pg_hi21:foo
 291         add  x0, x0, #:lo12:foo
 292 @end smallexample
 293
 294 Or to load the value of @var{foo} into x0:
 295
 296 @smallexample
 297         adrp x0, :pg_hi21:foo
 298         ldr  x0, [x0, #:lo12:foo]
 299 @end smallexample
 300
 301 Note that @samp{:pg_hi21:} is optional.
 302
 303 @smallexample
 304         adrp x0, foo
 305 @end smallexample
 306
 307 is equivalent to
 308
 309 @smallexample
 310         adrp x0, :pg_hi21:foo
 311 @end smallexample
 312
 313 @node AArch64 Floating Point
 314 @section Floating Point
 315
 316 @cindex floating point, AArch64 (@sc{ieee})
 317 @cindex AArch64 floating point (@sc{ieee})
 318 The AArch64 architecture uses @sc{ieee} floating-point numbers.
 319
 320 @node AArch64 Directives
 321 @section AArch64 Machine Directives
 322
 323 @cindex machine directives, AArch64
 324 @cindex AArch64 machine directives
 325 @table @code
 326
 327 @c AAAAAAAAAAAAAAAAAAAAAAAAA
 328
 329 @cindex @code{.arch} directive, AArch64
 330 @item .arch @var{name}
 331 Select the target architecture.  Valid values for @var{name} are the same as
 332 for the @option{-march} command-line option.
 333
 334 Specifying @code{.arch} clears any previously selected architecture
 335 extensions.
 336
 337 @cindex @code{.arch_extension} directive, AArch64
 338 @item .arch_extension @var{name}
 339 Add or remove an architecture extension to the target architecture.  Valid
 340 values for @var{name} are the same as those accepted as architectural
 341 extensions by the @option{-mcpu} command-line option.
 342
 343 @code{.arch_extension} may be used multiple times to add or remove extensions
 344 incrementally to the architecture being compiled for.
 345
 346 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
 347
 348 @cindex @code{.bss} directive, AArch64
 349 @item .bss
 350 This directive switches to the @code{.bss} section.
 351
 352 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
 353
 354 @cindex @code{.cpu} directive, AArch64
 355 @item .cpu @var{name}
 356 Set the target processor.  Valid values for @var{name} are the same as
 357 those accepted by the @option{-mcpu=} command-line option.
 358
 359 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
 360
 361 @cindex @code{.dword} directive, AArch64
 362 @item .dword @var{expressions}
 363 The @code{.dword} directive produces 64 bit values.
 364
 365 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
 366
 367 @cindex @code{.even} directive, AArch64
 368 @item .even
 369 The @code{.even} directive aligns the output on the next even byte
 370 boundary.
 371
 372 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
 373
 374 @cindex @code{.float16} directive, AArch64
 375 @item .float16 @var{value [,...,value_n]}
 376 Place the half precision floating point representation of one or more
 377 floating-point values into the current section.
 378 The format used to encode the floating point values is always the
 379 IEEE 754-2008 half precision floating point format.
 380
 381 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
 382 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
 383 @c IIIIIIIIIIIIIIIIIIIIIIIIII
 384
 385 @cindex @code{.inst} directive, AArch64
 386 @item .inst @var{expressions}
 387 Inserts the expressions into the output as if they were instructions,
 388 rather than data.
 389
 390 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
 391 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
 392 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
 393
 394 @cindex @code{.ltorg} directive, AArch64
 395 @item .ltorg
 396 This directive causes the current contents of the literal pool to be
 397 dumped into the current section (which is assumed to be the .text
 398 section) at the current location (aligned to a word boundary).
 399 GAS maintains a separate literal pool for each section and each
 400 sub-section.  The @code{.ltorg} directive will only affect the literal
 401 pool of the current section and sub-section.  At the end of assembly
 402 all remaining, un-empty literal pools will automatically be dumped.
 403
 404 Note - older versions of GAS would dump the current literal
 405 pool any time a section change occurred.  This is no longer done, since
 406 it prevents accurate control of the placement of literal pools.
 407
 408 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
 409
 410 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
 411 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
 412
 413 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
 414
 415 @cindex @code{.pool} directive, AArch64
 416 @item .pool
 417 This is a synonym for .ltorg.
 418
 419 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
 420 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
 421
 422 @cindex @code{.req} directive, AArch64
 423 @item @var{name} .req @var{register name}
 424 This creates an alias for @var{register name} called @var{name}.  For
 425 example:
 426
 427 @smallexample
 428         foo .req w0
 429 @end smallexample
 430
 431 ip0, ip1, lr and fp are automatically defined to
 432 alias to X16, X17, X30 and X29 respectively.
 433
 434 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
 435
 436 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
 437
 438 @cindex @code{.tlsdescadd} directive, AArch64
 439 @item   @code{.tlsdescadd}
 440 Emits a TLSDESC_ADD reloc on the next instruction.
 441
 442 @cindex @code{.tlsdesccall} directive, AArch64
 443 @item   @code{.tlsdesccall}
 444 Emits a TLSDESC_CALL reloc on the next instruction.
 445
 446 @cindex @code{.tlsdescldr} directive, AArch64
 447 @item   @code{.tlsdescldr}
 448 Emits a TLSDESC_LDR reloc on the next instruction.
 449
 450 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
 451
 452 @cindex @code{.unreq} directive, AArch64
 453 @item .unreq @var{alias-name}
 454 This undefines a register alias which was previously defined using the
 455 @code{req} directive.  For example:
 456
 457 @smallexample
 458         foo .req w0
 459         .unreq foo
 460 @end smallexample
 461
 462 An error occurs if the name is undefined.  Note - this pseudo op can
 463 be used to delete builtin in register name aliases (eg 'w0').  This
 464 should only be done if it is really necessary.
 465
 466 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
 467
 468 @cindex @code{.variant_pcs} directive, AArch64
 469 @item .variant_pcs @var{symbol}
 470 This directive marks @var{symbol} referencing a function that may
 471 follow a variant procedure call standard with different register
 472 usage convention from the base procedure call standard.
 473
 474 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
 475 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
 476
 477 @cindex @code{.xword} directive, AArch64
 478 @item .xword @var{expressions}
 479 The @code{.xword} directive produces 64 bit values.  This is the same
 480 as the @code{.dword} directive.
 481
 482 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
 483 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
 484
 485 @cindex @code{.cfi_b_key_frame} directive, AArch64
 486 @item   @code{.cfi_b_key_frame}
 487 The @code{.cfi_b_key_frame} directive inserts a 'B' character into the CIE
 488 corresponding to the current frame's FDE, meaning that its return address has
 489 been signed with the B-key.  If two frames are signed with differing keys then
 490 they will not share the same CIE.  This information is intended to be used by
 491 the stack unwinder in order to properly authenticate return addresses.
 492
 493 @end table
 494
 495 @node AArch64 Opcodes
 496 @section Opcodes
 497
 498 @cindex AArch64 opcodes
 499 @cindex opcodes for AArch64
 500 GAS implements all the standard AArch64 opcodes.  It also
 501 implements several pseudo opcodes, including several synthetic load
 502 instructions.
 503
 504 @table @code
 505
 506 @cindex @code{LDR reg,=<expr>} pseudo op, AArch64
 507 @item LDR =
 508 @smallexample
 509   ldr <register> , =<expression>
 510 @end smallexample
 511
 512 The constant expression will be placed into the nearest literal pool (if it not
 513 already there) and a PC-relative LDR instruction will be generated.
 514
 515 @end table
 516
 517 For more information on the AArch64 instruction set and assembly language
 518 notation, see @samp{ARMv8 Instruction Set Overview} available at
 519 @uref{http://infocenter.arm.com}.
 520
 521
 522 @node AArch64 Mapping Symbols
 523 @section Mapping Symbols
 524
 525 The AArch64 ELF specification requires that special symbols be inserted
 526 into object files to mark certain features:
 527
 528 @table @code
 529
 530 @cindex @code{$x}
 531 @item $x
 532 At the start of a region of code containing AArch64 instructions.
 533
 534 @cindex @code{$d}
 535 @item $d
 536 At the start of a region of data.
 537
 538 @end table