gas/doc/c-aarch64.texi

   1 @c Copyright (C) 2009-2020 Free Software Foundation, Inc.
   2 @c Contributed by ARM Ltd.
   3 @c This is part of the GAS manual.
   4 @c For copying conditions, see the file as.texinfo.
   5 @c man end
   6
   7 @ifset GENERIC
   8 @page
   9 @node AArch64-Dependent
  10 @chapter AArch64 Dependent Features
  11 @end ifset
  12
  13 @ifclear GENERIC
  14 @node Machine Dependencies
  15 @chapter AArch64 Dependent Features
  16 @end ifclear
  17
  18 @cindex AArch64 support
  19 @menu
  20 * AArch64 Options::              Options
  21 * AArch64 Extensions::           Extensions
  22 * AArch64 Syntax::               Syntax
  23 * AArch64 Floating Point::       Floating Point
  24 * AArch64 Directives::           AArch64 Machine Directives
  25 * AArch64 Opcodes::              Opcodes
  26 * AArch64 Mapping Symbols::      Mapping Symbols
  27 @end menu
  28
  29 @node AArch64 Options
  30 @section Options
  31 @cindex AArch64 options (none)
  32 @cindex options for AArch64 (none)
  33
  34 @c man begin OPTIONS
  35 @table @gcctabopt
  36
  37 @cindex @option{-EB} command-line option, AArch64
  38 @item -EB
  39 This option specifies that the output generated by the assembler should
  40 be marked as being encoded for a big-endian processor.
  41
  42 @cindex @option{-EL} command-line option, AArch64
  43 @item -EL
  44 This option specifies that the output generated by the assembler should
  45 be marked as being encoded for a little-endian processor.
  46
  47 @cindex @option{-mabi=} command-line option, AArch64
  48 @item -mabi=@var{abi}
  49 Specify which ABI the source code uses.  The recognized arguments
  50 are: @code{ilp32} and @code{lp64}, which decides the generated object
  51 file in ELF32 and ELF64 format respectively.  The default is @code{lp64}.
  52
  53 @cindex @option{-mcpu=} command-line option, AArch64
  54 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
  55 This option specifies the target processor.  The assembler will issue an error
  56 message if an attempt is made to assemble an instruction which will not execute
  57 on the target processor.  The following processor names are recognized:
  58 @code{cortex-a34},
  59 @code{cortex-a35},
  60 @code{cortex-a53},
  61 @code{cortex-a55},
  62 @code{cortex-a57},
  63 @code{cortex-a65},
  64 @code{cortex-a65ae},
  65 @code{cortex-a72},
  66 @code{cortex-a73},
  67 @code{cortex-a75},
  68 @code{cortex-a76},
  69 @code{cortex-a76ae},
  70 @code{cortex-a77},
  71 @code{ares},
  72 @code{exynos-m1},
  73 @code{falkor},
  74 @code{neoverse-n1},
  75 @code{neoverse-e1},
  76 @code{neoverse-v1},
  77 @code{qdf24xx},
  78 @code{saphira},
  79 @code{thunderx},
  80 @code{vulcan},
  81 @code{xgene1}
  82 @code{xgene2},
  83 and
  84 @code{cortex-r82}.
  85 The special name @code{all} may be used to allow the assembler to accept
  86 instructions valid for any supported processor, including all optional
  87 extensions.
  88
  89 In addition to the basic instruction set, the assembler can be told to
  90 accept, or restrict, various extension mnemonics that extend the
  91 processor.  @xref{AArch64 Extensions}.
  92
  93 If some implementations of a particular processor can have an
  94 extension, then then those extensions are automatically enabled.
  95 Consequently, you will not normally have to specify any additional
  96 extensions.
  97
  98 @cindex @option{-march=} command-line option, AArch64
  99 @item -march=@var{architecture}[+@var{extension}@dots{}]
 100 This option specifies the target architecture.  The assembler will
 101 issue an error message if an attempt is made to assemble an
 102 instruction which will not execute on the target architecture.  The
 103 following architecture names are recognized: @code{armv8-a},
 104 @code{armv8.1-a}, @code{armv8.2-a}, @code{armv8.3-a}, @code{armv8.4-a}
 105 @code{armv8.5-a}, @code{armv8.6-a}, and @code{armv8-r}.
 106
 107 If both @option{-mcpu} and @option{-march} are specified, the
 108 assembler will use the setting for @option{-mcpu}.  If neither are
 109 specified, the assembler will default to @option{-mcpu=all}.
 110
 111 The architecture option can be extended with the same instruction set
 112 extension options as the @option{-mcpu} option.  Unlike
 113 @option{-mcpu}, extensions are not always enabled by default,
 114 @xref{AArch64 Extensions}.
 115
 116 @cindex @code{-mverbose-error} command-line option, AArch64
 117 @item -mverbose-error
 118 This option enables verbose error messages for AArch64 gas.  This option
 119 is enabled by default.
 120
 121 @cindex @code{-mno-verbose-error} command-line option, AArch64
 122 @item -mno-verbose-error
 123 This option disables verbose error messages in AArch64 gas.
 124
 125 @end table
 126 @c man end
 127
 128 @node AArch64 Extensions
 129 @section Architecture Extensions
 130
 131 The table below lists the permitted architecture extensions that are
 132 supported by the assembler and the conditions under which they are
 133 automatically enabled.
 134
 135 Multiple extensions may be specified, separated by a @code{+}.
 136 Extension mnemonics may also be removed from those the assembler
 137 accepts.  This is done by prepending @code{no} to the option that adds
 138 the extension.  Extensions that are removed must be listed after all
 139 extensions that have been added.
 140
 141 Enabling an extension that requires other extensions will
 142 automatically cause those extensions to be enabled.  Similarly,
 143 disabling an extension that is required by other extensions will
 144 automatically cause those extensions to be disabled.
 145
 146 @multitable @columnfractions .12 .17 .17 .54
 147 @headitem Extension @tab Minimum Architecture @tab Enabled by default
 148  @tab Description
 149 @item @code{i8mm} @tab ARMv8.2-A @tab ARMv8.6-A or later
 150  @tab Enable Int8 Matrix Multiply extension.
 151 @item @code{f32mm} @tab ARMv8.2-A @tab No
 152  @tab Enable F32 Matrix Multiply extension.
 153 @item @code{f64mm} @tab ARMv8.2-A @tab No
 154  @tab Enable F64 Matrix Multiply extension.
 155 @item @code{bf16} @tab ARMv8.2-A @tab ARMv8.6-A or later
 156  @tab Enable BFloat16 extension.
 157 @item @code{compnum} @tab ARMv8.2-A @tab ARMv8.3-A or later
 158  @tab Enable the complex number SIMD extensions.  This implies
 159  @code{fp16} and @code{simd}.
 160 @item @code{crc} @tab ARMv8-A @tab ARMv8.1-A or later
 161  @tab Enable CRC instructions.
 162 @item @code{crypto} @tab ARMv8-A @tab No
 163  @tab Enable cryptographic extensions.  This implies @code{fp}, @code{simd}, @code{aes} and @code{sha2}.
 164 @item @code{aes} @tab ARMv8-A @tab No
 165  @tab Enable the AES cryptographic extensions. This implies @code{fp} and @code{simd}.
 166 @item @code{sha2} @tab ARMv8-A @tab No
 167  @tab Enable the SHA2 cryptographic extensions. This implies @code{fp} and @code{simd}.
 168 @item @code{sha3} @tab ARMv8.2-A @tab No
 169  @tab Enable the ARMv8.2-A SHA2 and SHA3 cryptographic extensions. This implies @code{fp}, @code{simd} and @code{sha2}.
 170 @item @code{sm4} @tab ARMv8.2-A @tab No
 171  @tab Enable the ARMv8.2-A SM3 and SM4 cryptographic extensions. This implies @code{fp} and @code{simd}.
 172 @item @code{fp} @tab ARMv8-A @tab ARMv8-A or later
 173  @tab Enable floating-point extensions.
 174 @item @code{fp16} @tab ARMv8.2-A @tab ARMv8.2-A or later
 175  @tab Enable ARMv8.2 16-bit floating-point support.  This implies
 176  @code{fp}.
 177 @item @code{lor} @tab ARMv8-A @tab ARMv8.1-A or later
 178  @tab Enable Limited Ordering Regions extensions.
 179 @item @code{lse} @tab ARMv8-A @tab ARMv8.1-A or later
 180  @tab Enable Large System extensions.
 181 @item @code{pan} @tab ARMv8-A @tab ARMv8.1-A or later
 182  @tab Enable Privileged Access Never support.
 183 @item @code{profile} @tab ARMv8.2-A @tab No
 184  @tab Enable statistical profiling extensions.
 185 @item @code{ras} @tab ARMv8-A @tab ARMv8.2-A or later
 186  @tab Enable the Reliability, Availability and Serviceability
 187  extension.
 188 @item @code{rcpc} @tab ARMv8.2-A @tab ARMv8.3-A or later
 189  @tab Enable the weak release consistency extension.
 190 @item @code{rdma} @tab ARMv8-A @tab ARMv8.1-A or later
 191  @tab Enable ARMv8.1 Advanced SIMD extensions.  This implies @code{simd}.
 192 @item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
 193  @tab Enable Advanced SIMD extensions.  This implies @code{fp}.
 194 @item @code{sve} @tab ARMv8.2-A @tab No
 195  @tab Enable the Scalable Vector Extensions.  This implies @code{fp16},
 196  @code{simd} and @code{compnum}.
 197 @item @code{dotprod} @tab ARMv8.2-A @tab ARMv8.4-A or later
 198  @tab Enable the Dot Product extension.  This implies @code{simd}.
 199 @item @code{fp16fml} @tab ARMv8.2-A @tab ARMv8.4-A or later
 200  @tab Enable ARMv8.2 16-bit floating-point multiplication variant support.
 201  This implies @code{fp16}.
 202 @item @code{sb} @tab ARMv8-A @tab ARMv8.5-A or later
 203  @tab Enable the speculation barrier instruction sb.
 204 @item @code{predres} @tab ARMv8-A @tab ARMv8.5-A or later
 205  @tab Enable the Execution and Data and Prediction instructions.
 206 @item @code{rng} @tab ARMv8.5-A @tab No
 207  @tab Enable ARMv8.5-A random number instructions.
 208 @item @code{ssbs} @tab ARMv8-A @tab ARMv8.5-A or later
 209  @tab Enable Speculative Store Bypassing Safe state read and write.
 210 @item @code{memtag} @tab ARMv8.5-A @tab No
 211  @tab Enable ARMv8.5-A Memory Tagging Extensions.
 212 @item @code{tme} @tab ARMv8-A @tab No
 213  @tab Enable Transactional Memory Extensions.
 214 @item @code{sve2} @tab ARMv8-A @tab No
 215  @tab Enable the SVE2 Extension.
 216 @item @code{sve2-bitperm} @tab ARMv8-A @tab No
 217  @tab Enable SVE2 BITPERM Extension.
 218 @item @code{sve2-sm4} @tab ARMv8-A @tab No
 219  @tab Enable SVE2 SM4 Extension.
 220 @item @code{sve2-aes} @tab ARMv8-A @tab No
 221  @tab Enable SVE2 AES Extension.  This also enables the .Q->.B form of the
 222  @code{pmullt} and @code{pmullb} instructions.
 223 @item @code{sve2-sha3} @tab ARMv8-A @tab No
 224  @tab Enable SVE2 SHA3 Extension.
 225 @end multitable
 226
 227 @node AArch64 Syntax
 228 @section Syntax
 229 @menu
 230 * AArch64-Chars::                Special Characters
 231 * AArch64-Regs::                 Register Names
 232 * AArch64-Relocations::      Relocations
 233 @end menu
 234
 235 @node AArch64-Chars
 236 @subsection Special Characters
 237
 238 @cindex line comment character, AArch64
 239 @cindex AArch64 line comment character
 240 The presence of a @samp{//} on a line indicates the start of a comment
 241 that extends to the end of the current line.  If a @samp{#} appears as
 242 the first character of a line, the whole line is treated as a comment.
 243
 244 @cindex line separator, AArch64
 245 @cindex statement separator, AArch64
 246 @cindex AArch64 line separator
 247 The @samp{;} character can be used instead of a newline to separate
 248 statements.
 249
 250 @cindex immediate character, AArch64
 251 @cindex AArch64 immediate character
 252 The @samp{#} can be optionally used to indicate immediate operands.
 253
 254 @node AArch64-Regs
 255 @subsection Register Names
 256
 257 @cindex AArch64 register names
 258 @cindex register names, AArch64
 259 Please refer to the section @samp{4.4 Register Names} of
 260 @samp{ARMv8 Instruction Set Overview}, which is available at
 261 @uref{http://infocenter.arm.com}.
 262
 263 @node AArch64-Relocations
 264 @subsection Relocations
 265
 266 @cindex relocations, AArch64
 267 @cindex AArch64 relocations
 268 @cindex MOVN, MOVZ and MOVK group relocations, AArch64
 269 Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated
 270 by prefixing the label with @samp{#:abs_g2:} etc.
 271 For example to load the 48-bit absolute address of @var{foo} into x0:
 272
 273 @smallexample
 274         movz x0, #:abs_g2:foo           // bits 32-47, overflow check
 275         movk x0, #:abs_g1_nc:foo        // bits 16-31, no overflow check
 276         movk x0, #:abs_g0_nc:foo        // bits  0-15, no overflow check
 277 @end smallexample
 278
 279 @cindex ADRP, ADD, LDR/STR group relocations, AArch64
 280 Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
 281 instructions can be generated by prefixing the label with
 282 @samp{:pg_hi21:} and @samp{#:lo12:} respectively.
 283
 284 For example to use 33-bit (+/-4GB) pc-relative addressing to
 285 load the address of @var{foo} into x0:
 286
 287 @smallexample
 288         adrp x0, :pg_hi21:foo
 289         add  x0, x0, #:lo12:foo
 290 @end smallexample
 291
 292 Or to load the value of @var{foo} into x0:
 293
 294 @smallexample
 295         adrp x0, :pg_hi21:foo
 296         ldr  x0, [x0, #:lo12:foo]
 297 @end smallexample
 298
 299 Note that @samp{:pg_hi21:} is optional.
 300
 301 @smallexample
 302         adrp x0, foo
 303 @end smallexample
 304
 305 is equivalent to
 306
 307 @smallexample
 308         adrp x0, :pg_hi21:foo
 309 @end smallexample
 310
 311 @node AArch64 Floating Point
 312 @section Floating Point
 313
 314 @cindex floating point, AArch64 (@sc{ieee})
 315 @cindex AArch64 floating point (@sc{ieee})
 316 The AArch64 architecture uses @sc{ieee} floating-point numbers.
 317
 318 @node AArch64 Directives
 319 @section AArch64 Machine Directives
 320
 321 @cindex machine directives, AArch64
 322 @cindex AArch64 machine directives
 323 @table @code
 324
 325 @c AAAAAAAAAAAAAAAAAAAAAAAAA
 326
 327 @cindex @code{.arch} directive, AArch64
 328 @item .arch @var{name}
 329 Select the target architecture.  Valid values for @var{name} are the same as
 330 for the @option{-march} command-line option.
 331
 332 Specifying @code{.arch} clears any previously selected architecture
 333 extensions.
 334
 335 @cindex @code{.arch_extension} directive, AArch64
 336 @item .arch_extension @var{name}
 337 Add or remove an architecture extension to the target architecture.  Valid
 338 values for @var{name} are the same as those accepted as architectural
 339 extensions by the @option{-mcpu} command-line option.
 340
 341 @code{.arch_extension} may be used multiple times to add or remove extensions
 342 incrementally to the architecture being compiled for.
 343
 344 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
 345
 346 @cindex @code{.bss} directive, AArch64
 347 @item .bss
 348 This directive switches to the @code{.bss} section.
 349
 350 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
 351
 352 @cindex @code{.cpu} directive, AArch64
 353 @item .cpu @var{name}
 354 Set the target processor.  Valid values for @var{name} are the same as
 355 those accepted by the @option{-mcpu=} command-line option.
 356
 357 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
 358
 359 @cindex @code{.dword} directive, AArch64
 360 @item .dword @var{expressions}
 361 The @code{.dword} directive produces 64 bit values.
 362
 363 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
 364
 365 @cindex @code{.even} directive, AArch64
 366 @item .even
 367 The @code{.even} directive aligns the output on the next even byte
 368 boundary.
 369
 370 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
 371
 372 @cindex @code{.float16} directive, AArch64
 373 @item .float16 @var{value [,...,value_n]}
 374 Place the half precision floating point representation of one or more
 375 floating-point values into the current section.
 376 The format used to encode the floating point values is always the
 377 IEEE 754-2008 half precision floating point format.
 378
 379 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
 380 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
 381 @c IIIIIIIIIIIIIIIIIIIIIIIIII
 382
 383 @cindex @code{.inst} directive, AArch64
 384 @item .inst @var{expressions}
 385 Inserts the expressions into the output as if they were instructions,
 386 rather than data.
 387
 388 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
 389 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
 390 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
 391
 392 @cindex @code{.ltorg} directive, AArch64
 393 @item .ltorg
 394 This directive causes the current contents of the literal pool to be
 395 dumped into the current section (which is assumed to be the .text
 396 section) at the current location (aligned to a word boundary).
 397 GAS maintains a separate literal pool for each section and each
 398 sub-section.  The @code{.ltorg} directive will only affect the literal
 399 pool of the current section and sub-section.  At the end of assembly
 400 all remaining, un-empty literal pools will automatically be dumped.
 401
 402 Note - older versions of GAS would dump the current literal
 403 pool any time a section change occurred.  This is no longer done, since
 404 it prevents accurate control of the placement of literal pools.
 405
 406 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
 407
 408 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
 409 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
 410
 411 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
 412
 413 @cindex @code{.pool} directive, AArch64
 414 @item .pool
 415 This is a synonym for .ltorg.
 416
 417 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
 418 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
 419
 420 @cindex @code{.req} directive, AArch64
 421 @item @var{name} .req @var{register name}
 422 This creates an alias for @var{register name} called @var{name}.  For
 423 example:
 424
 425 @smallexample
 426         foo .req w0
 427 @end smallexample
 428
 429 ip0, ip1, lr and fp are automatically defined to
 430 alias to X16, X17, X30 and X29 respectively.
 431
 432 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
 433
 434 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
 435
 436 @cindex @code{.tlsdescadd} directive, AArch64
 437 @item   @code{.tlsdescadd}
 438 Emits a TLSDESC_ADD reloc on the next instruction.
 439
 440 @cindex @code{.tlsdesccall} directive, AArch64
 441 @item   @code{.tlsdesccall}
 442 Emits a TLSDESC_CALL reloc on the next instruction.
 443
 444 @cindex @code{.tlsdescldr} directive, AArch64
 445 @item   @code{.tlsdescldr}
 446 Emits a TLSDESC_LDR reloc on the next instruction.
 447
 448 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
 449
 450 @cindex @code{.unreq} directive, AArch64
 451 @item .unreq @var{alias-name}
 452 This undefines a register alias which was previously defined using the
 453 @code{req} directive.  For example:
 454
 455 @smallexample
 456         foo .req w0
 457         .unreq foo
 458 @end smallexample
 459
 460 An error occurs if the name is undefined.  Note - this pseudo op can
 461 be used to delete builtin in register name aliases (eg 'w0').  This
 462 should only be done if it is really necessary.
 463
 464 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
 465
 466 @cindex @code{.variant_pcs} directive, AArch64
 467 @item .variant_pcs @var{symbol}
 468 This directive marks @var{symbol} referencing a function that may
 469 follow a variant procedure call standard with different register
 470 usage convention from the base procedure call standard.
 471
 472 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
 473 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
 474
 475 @cindex @code{.xword} directive, AArch64
 476 @item .xword @var{expressions}
 477 The @code{.xword} directive produces 64 bit values.  This is the same
 478 as the @code{.dword} directive.
 479
 480 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
 481 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
 482
 483 @cindex @code{.cfi_b_key_frame} directive, AArch64
 484 @item   @code{.cfi_b_key_frame}
 485 The @code{.cfi_b_key_frame} directive inserts a 'B' character into the CIE
 486 corresponding to the current frame's FDE, meaning that its return address has
 487 been signed with the B-key.  If two frames are signed with differing keys then
 488 they will not share the same CIE.  This information is intended to be used by
 489 the stack unwinder in order to properly authenticate return addresses.
 490
 491 @end table
 492
 493 @node AArch64 Opcodes
 494 @section Opcodes
 495
 496 @cindex AArch64 opcodes
 497 @cindex opcodes for AArch64
 498 GAS implements all the standard AArch64 opcodes.  It also
 499 implements several pseudo opcodes, including several synthetic load
 500 instructions.
 501
 502 @table @code
 503
 504 @cindex @code{LDR reg,=<expr>} pseudo op, AArch64
 505 @item LDR =
 506 @smallexample
 507   ldr <register> , =<expression>
 508 @end smallexample
 509
 510 The constant expression will be placed into the nearest literal pool (if it not
 511 already there) and a PC-relative LDR instruction will be generated.
 512
 513 @end table
 514
 515 For more information on the AArch64 instruction set and assembly language
 516 notation, see @samp{ARMv8 Instruction Set Overview} available at
 517 @uref{http://infocenter.arm.com}.
 518
 519
 520 @node AArch64 Mapping Symbols
 521 @section Mapping Symbols
 522
 523 The AArch64 ELF specification requires that special symbols be inserted
 524 into object files to mark certain features:
 525
 526 @table @code
 527
 528 @cindex @code{$x}
 529 @item $x
 530 At the start of a region of code containing AArch64 instructions.
 531
 532 @cindex @code{$d}
 533 @item $d
 534 At the start of a region of data.
 535
 536 @end table