gas/doc/c-aarch64.texi

   1 @c Copyright (C) 2009-2021 Free Software Foundation, Inc.
   2 @c Contributed by ARM Ltd.
   3 @c This is part of the GAS manual.
   4 @c For copying conditions, see the file as.texinfo.
   5 @c man end
   6
   7 @ifset GENERIC
   8 @page
   9 @node AArch64-Dependent
  10 @chapter AArch64 Dependent Features
  11 @end ifset
  12
  13 @ifclear GENERIC
  14 @node Machine Dependencies
  15 @chapter AArch64 Dependent Features
  16 @end ifclear
  17
  18 @cindex AArch64 support
  19 @menu
  20 * AArch64 Options::              Options
  21 * AArch64 Extensions::           Extensions
  22 * AArch64 Syntax::               Syntax
  23 * AArch64 Floating Point::       Floating Point
  24 * AArch64 Directives::           AArch64 Machine Directives
  25 * AArch64 Opcodes::              Opcodes
  26 * AArch64 Mapping Symbols::      Mapping Symbols
  27 @end menu
  28
  29 @node AArch64 Options
  30 @section Options
  31 @cindex AArch64 options (none)
  32 @cindex options for AArch64 (none)
  33
  34 @c man begin OPTIONS
  35 @table @gcctabopt
  36
  37 @cindex @option{-EB} command-line option, AArch64
  38 @item -EB
  39 This option specifies that the output generated by the assembler should
  40 be marked as being encoded for a big-endian processor.
  41
  42 @cindex @option{-EL} command-line option, AArch64
  43 @item -EL
  44 This option specifies that the output generated by the assembler should
  45 be marked as being encoded for a little-endian processor.
  46
  47 @cindex @option{-mabi=} command-line option, AArch64
  48 @item -mabi=@var{abi}
  49 Specify which ABI the source code uses.  The recognized arguments
  50 are: @code{ilp32} and @code{lp64}, which decides the generated object
  51 file in ELF32 and ELF64 format respectively.  The default is @code{lp64}.
  52
  53 @cindex @option{-mcpu=} command-line option, AArch64
  54 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
  55 This option specifies the target processor.  The assembler will issue an error
  56 message if an attempt is made to assemble an instruction which will not execute
  57 on the target processor.  The following processor names are recognized:
  58 @code{cortex-a34},
  59 @code{cortex-a35},
  60 @code{cortex-a53},
  61 @code{cortex-a55},
  62 @code{cortex-a57},
  63 @code{cortex-a65},
  64 @code{cortex-a65ae},
  65 @code{cortex-a72},
  66 @code{cortex-a73},
  67 @code{cortex-a75},
  68 @code{cortex-a76},
  69 @code{cortex-a76ae},
  70 @code{cortex-a77},
  71 @code{cortex-a78},
  72 @code{cortex-a78ae},
  73 @code{cortex-a78c},
  74 @code{ares},
  75 @code{exynos-m1},
  76 @code{falkor},
  77 @code{neoverse-n1},
  78 @code{neoverse-n2},
  79 @code{neoverse-e1},
  80 @code{neoverse-v1},
  81 @code{qdf24xx},
  82 @code{saphira},
  83 @code{thunderx},
  84 @code{vulcan},
  85 @code{xgene1}
  86 @code{xgene2},
  87 @code{cortex-r82},
  88 and
  89 @code{cortex-x1}.
  90 The special name @code{all} may be used to allow the assembler to accept
  91 instructions valid for any supported processor, including all optional
  92 extensions.
  93
  94 In addition to the basic instruction set, the assembler can be told to
  95 accept, or restrict, various extension mnemonics that extend the
  96 processor.  @xref{AArch64 Extensions}.
  97
  98 If some implementations of a particular processor can have an
  99 extension, then then those extensions are automatically enabled.
 100 Consequently, you will not normally have to specify any additional
 101 extensions.
 102
 103 @cindex @option{-march=} command-line option, AArch64
 104 @item -march=@var{architecture}[+@var{extension}@dots{}]
 105 This option specifies the target architecture.  The assembler will
 106 issue an error message if an attempt is made to assemble an
 107 instruction which will not execute on the target architecture.  The
 108 following architecture names are recognized: @code{armv8-a},
 109 @code{armv8.1-a}, @code{armv8.2-a}, @code{armv8.3-a}, @code{armv8.4-a}
 110 @code{armv8.5-a}, @code{armv8.6-a}, @code{armv8.7-a}, @code{armv8-r}, and
 111 @code{armv9-a}.
 112
 113 If both @option{-mcpu} and @option{-march} are specified, the
 114 assembler will use the setting for @option{-mcpu}.  If neither are
 115 specified, the assembler will default to @option{-mcpu=all}.
 116
 117 The architecture option can be extended with the same instruction set
 118 extension options as the @option{-mcpu} option.  Unlike
 119 @option{-mcpu}, extensions are not always enabled by default,
 120 @xref{AArch64 Extensions}.
 121
 122 @cindex @code{-mverbose-error} command-line option, AArch64
 123 @item -mverbose-error
 124 This option enables verbose error messages for AArch64 gas.  This option
 125 is enabled by default.
 126
 127 @cindex @code{-mno-verbose-error} command-line option, AArch64
 128 @item -mno-verbose-error
 129 This option disables verbose error messages in AArch64 gas.
 130
 131 @end table
 132 @c man end
 133
 134 @node AArch64 Extensions
 135 @section Architecture Extensions
 136
 137 The table below lists the permitted architecture extensions that are
 138 supported by the assembler and the conditions under which they are
 139 automatically enabled.
 140
 141 Multiple extensions may be specified, separated by a @code{+}.
 142 Extension mnemonics may also be removed from those the assembler
 143 accepts.  This is done by prepending @code{no} to the option that adds
 144 the extension.  Extensions that are removed must be listed after all
 145 extensions that have been added.
 146
 147 Enabling an extension that requires other extensions will
 148 automatically cause those extensions to be enabled.  Similarly,
 149 disabling an extension that is required by other extensions will
 150 automatically cause those extensions to be disabled.
 151
 152 @multitable @columnfractions .12 .17 .17 .54
 153 @headitem Extension @tab Minimum Architecture @tab Enabled by default
 154  @tab Description
 155 @item @code{i8mm} @tab ARMv8.2-A @tab ARMv8.6-A or later
 156  @tab Enable Int8 Matrix Multiply extension.
 157 @item @code{f32mm} @tab ARMv8.2-A @tab No
 158  @tab Enable F32 Matrix Multiply extension.
 159 @item @code{f64mm} @tab ARMv8.2-A @tab No
 160  @tab Enable F64 Matrix Multiply extension.
 161 @item @code{bf16} @tab ARMv8.2-A @tab ARMv8.6-A or later
 162  @tab Enable BFloat16 extension.
 163 @item @code{compnum} @tab ARMv8.2-A @tab ARMv8.3-A or later
 164  @tab Enable the complex number SIMD extensions.  This implies
 165  @code{fp16} and @code{simd}.
 166 @item @code{crc} @tab ARMv8-A @tab ARMv8.1-A or later
 167  @tab Enable CRC instructions.
 168 @item @code{crypto} @tab ARMv8-A @tab No
 169  @tab Enable cryptographic extensions.  This implies @code{fp}, @code{simd}, @code{aes} and @code{sha2}.
 170 @item @code{aes} @tab ARMv8-A @tab No
 171  @tab Enable the AES cryptographic extensions. This implies @code{fp} and @code{simd}.
 172 @item @code{sha2} @tab ARMv8-A @tab No
 173  @tab Enable the SHA2 cryptographic extensions. This implies @code{fp} and @code{simd}.
 174 @item @code{sha3} @tab ARMv8.2-A @tab No
 175  @tab Enable the ARMv8.2-A SHA2 and SHA3 cryptographic extensions. This implies @code{fp}, @code{simd} and @code{sha2}.
 176 @item @code{sm4} @tab ARMv8.2-A @tab No
 177  @tab Enable the ARMv8.2-A SM3 and SM4 cryptographic extensions. This implies @code{fp} and @code{simd}.
 178 @item @code{fp} @tab ARMv8-A @tab ARMv8-A or later
 179  @tab Enable floating-point extensions.
 180 @item @code{fp16} @tab ARMv8.2-A @tab ARMv8.2-A or later
 181  @tab Enable ARMv8.2 16-bit floating-point support.  This implies
 182  @code{fp}.
 183 @item @code{lor} @tab ARMv8-A @tab ARMv8.1-A or later
 184  @tab Enable Limited Ordering Regions extensions.
 185 @item @code{lse} @tab ARMv8-A @tab ARMv8.1-A or later
 186  @tab Enable Large System extensions.
 187 @item @code{pan} @tab ARMv8-A @tab ARMv8.1-A or later
 188  @tab Enable Privileged Access Never support.
 189 @item @code{profile} @tab ARMv8.2-A @tab No
 190  @tab Enable statistical profiling extensions.
 191 @item @code{ras} @tab ARMv8-A @tab ARMv8.2-A or later
 192  @tab Enable the Reliability, Availability and Serviceability
 193  extension.
 194 @item @code{rcpc} @tab ARMv8.2-A @tab ARMv8.3-A or later
 195  @tab Enable the weak release consistency extension.
 196 @item @code{rdma} @tab ARMv8-A @tab ARMv8.1-A or later
 197  @tab Enable ARMv8.1 Advanced SIMD extensions.  This implies @code{simd}.
 198 @item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
 199  @tab Enable Advanced SIMD extensions.  This implies @code{fp}.
 200 @item @code{sve} @tab ARMv8.2-A @tab Armv9-A or later
 201  @tab Enable the Scalable Vector Extensions.  This implies @code{fp16},
 202  @code{simd} and @code{compnum}.
 203 @item @code{dotprod} @tab ARMv8.2-A @tab ARMv8.4-A or later
 204  @tab Enable the Dot Product extension.  This implies @code{simd}.
 205 @item @code{fp16fml} @tab ARMv8.2-A @tab ARMv8.4-A or later
 206  @tab Enable ARMv8.2 16-bit floating-point multiplication variant support.
 207  This implies @code{fp16}.
 208 @item @code{sb} @tab ARMv8-A @tab ARMv8.5-A or later
 209  @tab Enable the speculation barrier instruction sb.
 210 @item @code{predres} @tab ARMv8-A @tab ARMv8.5-A or later
 211  @tab Enable the Execution and Data and Prediction instructions.
 212 @item @code{rng} @tab ARMv8.5-A @tab No
 213  @tab Enable ARMv8.5-A random number instructions.
 214 @item @code{ssbs} @tab ARMv8-A @tab ARMv8.5-A or later
 215  @tab Enable Speculative Store Bypassing Safe state read and write.
 216 @item @code{memtag} @tab ARMv8.5-A @tab No
 217  @tab Enable ARMv8.5-A Memory Tagging Extensions.
 218 @item @code{tme} @tab ARMv8-A @tab No
 219  @tab Enable Transactional Memory Extensions.
 220 @item @code{sve2} @tab ARMv8-A @tab Armv9-A or later
 221  @tab Enable the SVE2 Extension.
 222 @item @code{sve2-bitperm} @tab ARMv8-A @tab No
 223  @tab Enable SVE2 BITPERM Extension.
 224 @item @code{sve2-sm4} @tab ARMv8-A @tab No
 225  @tab Enable SVE2 SM4 Extension.
 226 @item @code{sve2-aes} @tab ARMv8-A @tab No
 227  @tab Enable SVE2 AES Extension.  This also enables the .Q->.B form of the
 228  @code{pmullt} and @code{pmullb} instructions.
 229 @item @code{sve2-sha3} @tab ARMv8-A @tab No
 230  @tab Enable SVE2 SHA3 Extension.
 231 @item @code{flagm} @tab ARMv8-A @tab ARMv8.4-A or later
 232  @tab Enable Flag Manipulation instructions.
 233 @item @code{ls64} @tab ARMv8.6-A @tab ARMv8.7-A or later
 234  @tab Enable 64 Byte Loads/Stores.
 235 @item @code{pauth} @tab ARMv8-A @tab No
 236  @tab Enable Pointer Authentication.
 237 @end multitable
 238
 239 @node AArch64 Syntax
 240 @section Syntax
 241 @menu
 242 * AArch64-Chars::                Special Characters
 243 * AArch64-Regs::                 Register Names
 244 * AArch64-Relocations::      Relocations
 245 @end menu
 246
 247 @node AArch64-Chars
 248 @subsection Special Characters
 249
 250 @cindex line comment character, AArch64
 251 @cindex AArch64 line comment character
 252 The presence of a @samp{//} on a line indicates the start of a comment
 253 that extends to the end of the current line.  If a @samp{#} appears as
 254 the first character of a line, the whole line is treated as a comment.
 255
 256 @cindex line separator, AArch64
 257 @cindex statement separator, AArch64
 258 @cindex AArch64 line separator
 259 The @samp{;} character can be used instead of a newline to separate
 260 statements.
 261
 262 @cindex immediate character, AArch64
 263 @cindex AArch64 immediate character
 264 The @samp{#} can be optionally used to indicate immediate operands.
 265
 266 @node AArch64-Regs
 267 @subsection Register Names
 268
 269 @cindex AArch64 register names
 270 @cindex register names, AArch64
 271 Please refer to the section @samp{4.4 Register Names} of
 272 @samp{ARMv8 Instruction Set Overview}, which is available at
 273 @uref{http://infocenter.arm.com}.
 274
 275 @node AArch64-Relocations
 276 @subsection Relocations
 277
 278 @cindex relocations, AArch64
 279 @cindex AArch64 relocations
 280 @cindex MOVN, MOVZ and MOVK group relocations, AArch64
 281 Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated
 282 by prefixing the label with @samp{#:abs_g2:} etc.
 283 For example to load the 48-bit absolute address of @var{foo} into x0:
 284
 285 @smallexample
 286         movz x0, #:abs_g2:foo           // bits 32-47, overflow check
 287         movk x0, #:abs_g1_nc:foo        // bits 16-31, no overflow check
 288         movk x0, #:abs_g0_nc:foo        // bits  0-15, no overflow check
 289 @end smallexample
 290
 291 @cindex ADRP, ADD, LDR/STR group relocations, AArch64
 292 Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
 293 instructions can be generated by prefixing the label with
 294 @samp{:pg_hi21:} and @samp{#:lo12:} respectively.
 295
 296 For example to use 33-bit (+/-4GB) pc-relative addressing to
 297 load the address of @var{foo} into x0:
 298
 299 @smallexample
 300         adrp x0, :pg_hi21:foo
 301         add  x0, x0, #:lo12:foo
 302 @end smallexample
 303
 304 Or to load the value of @var{foo} into x0:
 305
 306 @smallexample
 307         adrp x0, :pg_hi21:foo
 308         ldr  x0, [x0, #:lo12:foo]
 309 @end smallexample
 310
 311 Note that @samp{:pg_hi21:} is optional.
 312
 313 @smallexample
 314         adrp x0, foo
 315 @end smallexample
 316
 317 is equivalent to
 318
 319 @smallexample
 320         adrp x0, :pg_hi21:foo
 321 @end smallexample
 322
 323 @node AArch64 Floating Point
 324 @section Floating Point
 325
 326 @cindex floating point, AArch64 (@sc{ieee})
 327 @cindex AArch64 floating point (@sc{ieee})
 328 The AArch64 architecture uses @sc{ieee} floating-point numbers.
 329
 330 @node AArch64 Directives
 331 @section AArch64 Machine Directives
 332
 333 @cindex machine directives, AArch64
 334 @cindex AArch64 machine directives
 335 @table @code
 336
 337 @c AAAAAAAAAAAAAAAAAAAAAAAAA
 338
 339 @cindex @code{.arch} directive, AArch64
 340 @item .arch @var{name}
 341 Select the target architecture.  Valid values for @var{name} are the same as
 342 for the @option{-march} command-line option.
 343
 344 Specifying @code{.arch} clears any previously selected architecture
 345 extensions.
 346
 347 @cindex @code{.arch_extension} directive, AArch64
 348 @item .arch_extension @var{name}
 349 Add or remove an architecture extension to the target architecture.  Valid
 350 values for @var{name} are the same as those accepted as architectural
 351 extensions by the @option{-mcpu} command-line option.
 352
 353 @code{.arch_extension} may be used multiple times to add or remove extensions
 354 incrementally to the architecture being compiled for.
 355
 356 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
 357
 358 @cindex @code{.bss} directive, AArch64
 359 @item .bss
 360 This directive switches to the @code{.bss} section.
 361
 362 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
 363
 364 @cindex @code{.cpu} directive, AArch64
 365 @item .cpu @var{name}
 366 Set the target processor.  Valid values for @var{name} are the same as
 367 those accepted by the @option{-mcpu=} command-line option.
 368
 369 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
 370
 371 @cindex @code{.dword} directive, AArch64
 372 @item .dword @var{expressions}
 373 The @code{.dword} directive produces 64 bit values.
 374
 375 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
 376
 377 @cindex @code{.even} directive, AArch64
 378 @item .even
 379 The @code{.even} directive aligns the output on the next even byte
 380 boundary.
 381
 382 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
 383
 384 @cindex @code{.float16} directive, AArch64
 385 @item .float16 @var{value [,...,value_n]}
 386 Place the half precision floating point representation of one or more
 387 floating-point values into the current section.
 388 The format used to encode the floating point values is always the
 389 IEEE 754-2008 half precision floating point format.
 390
 391 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
 392 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
 393 @c IIIIIIIIIIIIIIIIIIIIIIIIII
 394
 395 @cindex @code{.inst} directive, AArch64
 396 @item .inst @var{expressions}
 397 Inserts the expressions into the output as if they were instructions,
 398 rather than data.
 399
 400 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
 401 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
 402 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
 403
 404 @cindex @code{.ltorg} directive, AArch64
 405 @item .ltorg
 406 This directive causes the current contents of the literal pool to be
 407 dumped into the current section (which is assumed to be the .text
 408 section) at the current location (aligned to a word boundary).
 409 GAS maintains a separate literal pool for each section and each
 410 sub-section.  The @code{.ltorg} directive will only affect the literal
 411 pool of the current section and sub-section.  At the end of assembly
 412 all remaining, un-empty literal pools will automatically be dumped.
 413
 414 Note - older versions of GAS would dump the current literal
 415 pool any time a section change occurred.  This is no longer done, since
 416 it prevents accurate control of the placement of literal pools.
 417
 418 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
 419
 420 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
 421 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
 422
 423 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
 424
 425 @cindex @code{.pool} directive, AArch64
 426 @item .pool
 427 This is a synonym for .ltorg.
 428
 429 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
 430 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
 431
 432 @cindex @code{.req} directive, AArch64
 433 @item @var{name} .req @var{register name}
 434 This creates an alias for @var{register name} called @var{name}.  For
 435 example:
 436
 437 @smallexample
 438         foo .req w0
 439 @end smallexample
 440
 441 ip0, ip1, lr and fp are automatically defined to
 442 alias to X16, X17, X30 and X29 respectively.
 443
 444 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
 445
 446 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
 447
 448 @cindex @code{.tlsdescadd} directive, AArch64
 449 @item   @code{.tlsdescadd}
 450 Emits a TLSDESC_ADD reloc on the next instruction.
 451
 452 @cindex @code{.tlsdesccall} directive, AArch64
 453 @item   @code{.tlsdesccall}
 454 Emits a TLSDESC_CALL reloc on the next instruction.
 455
 456 @cindex @code{.tlsdescldr} directive, AArch64
 457 @item   @code{.tlsdescldr}
 458 Emits a TLSDESC_LDR reloc on the next instruction.
 459
 460 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
 461
 462 @cindex @code{.unreq} directive, AArch64
 463 @item .unreq @var{alias-name}
 464 This undefines a register alias which was previously defined using the
 465 @code{req} directive.  For example:
 466
 467 @smallexample
 468         foo .req w0
 469         .unreq foo
 470 @end smallexample
 471
 472 An error occurs if the name is undefined.  Note - this pseudo op can
 473 be used to delete builtin in register name aliases (eg 'w0').  This
 474 should only be done if it is really necessary.
 475
 476 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
 477
 478 @cindex @code{.variant_pcs} directive, AArch64
 479 @item .variant_pcs @var{symbol}
 480 This directive marks @var{symbol} referencing a function that may
 481 follow a variant procedure call standard with different register
 482 usage convention from the base procedure call standard.
 483
 484 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
 485 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
 486
 487 @cindex @code{.xword} directive, AArch64
 488 @item .xword @var{expressions}
 489 The @code{.xword} directive produces 64 bit values.  This is the same
 490 as the @code{.dword} directive.
 491
 492 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
 493 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
 494
 495 @cindex @code{.cfi_b_key_frame} directive, AArch64
 496 @item   @code{.cfi_b_key_frame}
 497 The @code{.cfi_b_key_frame} directive inserts a 'B' character into the CIE
 498 corresponding to the current frame's FDE, meaning that its return address has
 499 been signed with the B-key.  If two frames are signed with differing keys then
 500 they will not share the same CIE.  This information is intended to be used by
 501 the stack unwinder in order to properly authenticate return addresses.
 502
 503 @end table
 504
 505 @node AArch64 Opcodes
 506 @section Opcodes
 507
 508 @cindex AArch64 opcodes
 509 @cindex opcodes for AArch64
 510 GAS implements all the standard AArch64 opcodes.  It also
 511 implements several pseudo opcodes, including several synthetic load
 512 instructions.
 513
 514 @table @code
 515
 516 @cindex @code{LDR reg,=<expr>} pseudo op, AArch64
 517 @item LDR =
 518 @smallexample
 519   ldr <register> , =<expression>
 520 @end smallexample
 521
 522 The constant expression will be placed into the nearest literal pool (if it not
 523 already there) and a PC-relative LDR instruction will be generated.
 524
 525 @end table
 526
 527 For more information on the AArch64 instruction set and assembly language
 528 notation, see @samp{ARMv8 Instruction Set Overview} available at
 529 @uref{http://infocenter.arm.com}.
 530
 531
 532 @node AArch64 Mapping Symbols
 533 @section Mapping Symbols
 534
 535 The AArch64 ELF specification requires that special symbols be inserted
 536 into object files to mark certain features:
 537
 538 @table @code
 539
 540 @cindex @code{$x}
 541 @item $x
 542 At the start of a region of code containing AArch64 instructions.
 543
 544 @cindex @code{$d}
 545 @item $d
 546 At the start of a region of data.
 547
 548 @end table