gas/doc/c-aarch64.texi

   1 @c Copyright (C) 2009-2020 Free Software Foundation, Inc.
   2 @c Contributed by ARM Ltd.
   3 @c This is part of the GAS manual.
   4 @c For copying conditions, see the file as.texinfo.
   5 @c man end
   6
   7 @ifset GENERIC
   8 @page
   9 @node AArch64-Dependent
  10 @chapter AArch64 Dependent Features
  11 @end ifset
  12
  13 @ifclear GENERIC
  14 @node Machine Dependencies
  15 @chapter AArch64 Dependent Features
  16 @end ifclear
  17
  18 @cindex AArch64 support
  19 @menu
  20 * AArch64 Options::              Options
  21 * AArch64 Extensions::           Extensions
  22 * AArch64 Syntax::               Syntax
  23 * AArch64 Floating Point::       Floating Point
  24 * AArch64 Directives::           AArch64 Machine Directives
  25 * AArch64 Opcodes::              Opcodes
  26 * AArch64 Mapping Symbols::      Mapping Symbols
  27 @end menu
  28
  29 @node AArch64 Options
  30 @section Options
  31 @cindex AArch64 options (none)
  32 @cindex options for AArch64 (none)
  33
  34 @c man begin OPTIONS
  35 @table @gcctabopt
  36
  37 @cindex @option{-EB} command-line option, AArch64
  38 @item -EB
  39 This option specifies that the output generated by the assembler should
  40 be marked as being encoded for a big-endian processor.
  41
  42 @cindex @option{-EL} command-line option, AArch64
  43 @item -EL
  44 This option specifies that the output generated by the assembler should
  45 be marked as being encoded for a little-endian processor.
  46
  47 @cindex @option{-mabi=} command-line option, AArch64
  48 @item -mabi=@var{abi}
  49 Specify which ABI the source code uses.  The recognized arguments
  50 are: @code{ilp32} and @code{lp64}, which decides the generated object
  51 file in ELF32 and ELF64 format respectively.  The default is @code{lp64}.
  52
  53 @cindex @option{-mcpu=} command-line option, AArch64
  54 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
  55 This option specifies the target processor.  The assembler will issue an error
  56 message if an attempt is made to assemble an instruction which will not execute
  57 on the target processor.  The following processor names are recognized:
  58 @code{cortex-a34},
  59 @code{cortex-a35},
  60 @code{cortex-a53},
  61 @code{cortex-a55},
  62 @code{cortex-a57},
  63 @code{cortex-a65},
  64 @code{cortex-a65ae},
  65 @code{cortex-a72},
  66 @code{cortex-a73},
  67 @code{cortex-a75},
  68 @code{cortex-a76},
  69 @code{cortex-a76ae},
  70 @code{cortex-a77},
  71 @code{cortex-a78},
  72 @code{cortex-a78ae},
  73 @code{ares},
  74 @code{exynos-m1},
  75 @code{falkor},
  76 @code{neoverse-n1},
  77 @code{neoverse-n2},
  78 @code{neoverse-e1},
  79 @code{neoverse-v1},
  80 @code{qdf24xx},
  81 @code{saphira},
  82 @code{thunderx},
  83 @code{vulcan},
  84 @code{xgene1}
  85 @code{xgene2},
  86 @code{cortex-r82},
  87 and
  88 @code{cortex-x1}.
  89 The special name @code{all} may be used to allow the assembler to accept
  90 instructions valid for any supported processor, including all optional
  91 extensions.
  92
  93 In addition to the basic instruction set, the assembler can be told to
  94 accept, or restrict, various extension mnemonics that extend the
  95 processor.  @xref{AArch64 Extensions}.
  96
  97 If some implementations of a particular processor can have an
  98 extension, then then those extensions are automatically enabled.
  99 Consequently, you will not normally have to specify any additional
 100 extensions.
 101
 102 @cindex @option{-march=} command-line option, AArch64
 103 @item -march=@var{architecture}[+@var{extension}@dots{}]
 104 This option specifies the target architecture.  The assembler will
 105 issue an error message if an attempt is made to assemble an
 106 instruction which will not execute on the target architecture.  The
 107 following architecture names are recognized: @code{armv8-a},
 108 @code{armv8.1-a}, @code{armv8.2-a}, @code{armv8.3-a}, @code{armv8.4-a}
 109 @code{armv8.5-a}, @code{armv8.6-a}, @code{armv8.7-a}, and @code{armv8-r}.
 110
 111 If both @option{-mcpu} and @option{-march} are specified, the
 112 assembler will use the setting for @option{-mcpu}.  If neither are
 113 specified, the assembler will default to @option{-mcpu=all}.
 114
 115 The architecture option can be extended with the same instruction set
 116 extension options as the @option{-mcpu} option.  Unlike
 117 @option{-mcpu}, extensions are not always enabled by default,
 118 @xref{AArch64 Extensions}.
 119
 120 @cindex @code{-mverbose-error} command-line option, AArch64
 121 @item -mverbose-error
 122 This option enables verbose error messages for AArch64 gas.  This option
 123 is enabled by default.
 124
 125 @cindex @code{-mno-verbose-error} command-line option, AArch64
 126 @item -mno-verbose-error
 127 This option disables verbose error messages in AArch64 gas.
 128
 129 @end table
 130 @c man end
 131
 132 @node AArch64 Extensions
 133 @section Architecture Extensions
 134
 135 The table below lists the permitted architecture extensions that are
 136 supported by the assembler and the conditions under which they are
 137 automatically enabled.
 138
 139 Multiple extensions may be specified, separated by a @code{+}.
 140 Extension mnemonics may also be removed from those the assembler
 141 accepts.  This is done by prepending @code{no} to the option that adds
 142 the extension.  Extensions that are removed must be listed after all
 143 extensions that have been added.
 144
 145 Enabling an extension that requires other extensions will
 146 automatically cause those extensions to be enabled.  Similarly,
 147 disabling an extension that is required by other extensions will
 148 automatically cause those extensions to be disabled.
 149
 150 @multitable @columnfractions .12 .17 .17 .54
 151 @headitem Extension @tab Minimum Architecture @tab Enabled by default
 152  @tab Description
 153 @item @code{i8mm} @tab ARMv8.2-A @tab ARMv8.6-A or later
 154  @tab Enable Int8 Matrix Multiply extension.
 155 @item @code{f32mm} @tab ARMv8.2-A @tab No
 156  @tab Enable F32 Matrix Multiply extension.
 157 @item @code{f64mm} @tab ARMv8.2-A @tab No
 158  @tab Enable F64 Matrix Multiply extension.
 159 @item @code{bf16} @tab ARMv8.2-A @tab ARMv8.6-A or later
 160  @tab Enable BFloat16 extension.
 161 @item @code{compnum} @tab ARMv8.2-A @tab ARMv8.3-A or later
 162  @tab Enable the complex number SIMD extensions.  This implies
 163  @code{fp16} and @code{simd}.
 164 @item @code{crc} @tab ARMv8-A @tab ARMv8.1-A or later
 165  @tab Enable CRC instructions.
 166 @item @code{crypto} @tab ARMv8-A @tab No
 167  @tab Enable cryptographic extensions.  This implies @code{fp}, @code{simd}, @code{aes} and @code{sha2}.
 168 @item @code{aes} @tab ARMv8-A @tab No
 169  @tab Enable the AES cryptographic extensions. This implies @code{fp} and @code{simd}.
 170 @item @code{sha2} @tab ARMv8-A @tab No
 171  @tab Enable the SHA2 cryptographic extensions. This implies @code{fp} and @code{simd}.
 172 @item @code{sha3} @tab ARMv8.2-A @tab No
 173  @tab Enable the ARMv8.2-A SHA2 and SHA3 cryptographic extensions. This implies @code{fp}, @code{simd} and @code{sha2}.
 174 @item @code{sm4} @tab ARMv8.2-A @tab No
 175  @tab Enable the ARMv8.2-A SM3 and SM4 cryptographic extensions. This implies @code{fp} and @code{simd}.
 176 @item @code{fp} @tab ARMv8-A @tab ARMv8-A or later
 177  @tab Enable floating-point extensions.
 178 @item @code{fp16} @tab ARMv8.2-A @tab ARMv8.2-A or later
 179  @tab Enable ARMv8.2 16-bit floating-point support.  This implies
 180  @code{fp}.
 181 @item @code{lor} @tab ARMv8-A @tab ARMv8.1-A or later
 182  @tab Enable Limited Ordering Regions extensions.
 183 @item @code{lse} @tab ARMv8-A @tab ARMv8.1-A or later
 184  @tab Enable Large System extensions.
 185 @item @code{pan} @tab ARMv8-A @tab ARMv8.1-A or later
 186  @tab Enable Privileged Access Never support.
 187 @item @code{profile} @tab ARMv8.2-A @tab No
 188  @tab Enable statistical profiling extensions.
 189 @item @code{ras} @tab ARMv8-A @tab ARMv8.2-A or later
 190  @tab Enable the Reliability, Availability and Serviceability
 191  extension.
 192 @item @code{rcpc} @tab ARMv8.2-A @tab ARMv8.3-A or later
 193  @tab Enable the weak release consistency extension.
 194 @item @code{rdma} @tab ARMv8-A @tab ARMv8.1-A or later
 195  @tab Enable ARMv8.1 Advanced SIMD extensions.  This implies @code{simd}.
 196 @item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
 197  @tab Enable Advanced SIMD extensions.  This implies @code{fp}.
 198 @item @code{sve} @tab ARMv8.2-A @tab No
 199  @tab Enable the Scalable Vector Extensions.  This implies @code{fp16},
 200  @code{simd} and @code{compnum}.
 201 @item @code{dotprod} @tab ARMv8.2-A @tab ARMv8.4-A or later
 202  @tab Enable the Dot Product extension.  This implies @code{simd}.
 203 @item @code{fp16fml} @tab ARMv8.2-A @tab ARMv8.4-A or later
 204  @tab Enable ARMv8.2 16-bit floating-point multiplication variant support.
 205  This implies @code{fp16}.
 206 @item @code{sb} @tab ARMv8-A @tab ARMv8.5-A or later
 207  @tab Enable the speculation barrier instruction sb.
 208 @item @code{predres} @tab ARMv8-A @tab ARMv8.5-A or later
 209  @tab Enable the Execution and Data and Prediction instructions.
 210 @item @code{rng} @tab ARMv8.5-A @tab No
 211  @tab Enable ARMv8.5-A random number instructions.
 212 @item @code{ssbs} @tab ARMv8-A @tab ARMv8.5-A or later
 213  @tab Enable Speculative Store Bypassing Safe state read and write.
 214 @item @code{memtag} @tab ARMv8.5-A @tab No
 215  @tab Enable ARMv8.5-A Memory Tagging Extensions.
 216 @item @code{tme} @tab ARMv8-A @tab No
 217  @tab Enable Transactional Memory Extensions.
 218 @item @code{sve2} @tab ARMv8-A @tab No
 219  @tab Enable the SVE2 Extension.
 220 @item @code{sve2-bitperm} @tab ARMv8-A @tab No
 221  @tab Enable SVE2 BITPERM Extension.
 222 @item @code{sve2-sm4} @tab ARMv8-A @tab No
 223  @tab Enable SVE2 SM4 Extension.
 224 @item @code{sve2-aes} @tab ARMv8-A @tab No
 225  @tab Enable SVE2 AES Extension.  This also enables the .Q->.B form of the
 226  @code{pmullt} and @code{pmullb} instructions.
 227 @item @code{sve2-sha3} @tab ARMv8-A @tab No
 228  @tab Enable SVE2 SHA3 Extension.
 229 @item @code{flagm} @tab ARMv8-A @tab ARMv8.4-A or later
 230  @tab Enable Flag Manipulation instructions.
 231 @item @code{csre} @tab ARMv8-A @tab No
 232  @tab Enable Call Stack Recorder Extension.
 233 @item @code{ls64} @tab ARMv8-6 @tab ARMv8.7-A or later
 234  @tab Enable 64 Byte Loads/Stores.
 235 @end multitable
 236
 237 @node AArch64 Syntax
 238 @section Syntax
 239 @menu
 240 * AArch64-Chars::                Special Characters
 241 * AArch64-Regs::                 Register Names
 242 * AArch64-Relocations::      Relocations
 243 @end menu
 244
 245 @node AArch64-Chars
 246 @subsection Special Characters
 247
 248 @cindex line comment character, AArch64
 249 @cindex AArch64 line comment character
 250 The presence of a @samp{//} on a line indicates the start of a comment
 251 that extends to the end of the current line.  If a @samp{#} appears as
 252 the first character of a line, the whole line is treated as a comment.
 253
 254 @cindex line separator, AArch64
 255 @cindex statement separator, AArch64
 256 @cindex AArch64 line separator
 257 The @samp{;} character can be used instead of a newline to separate
 258 statements.
 259
 260 @cindex immediate character, AArch64
 261 @cindex AArch64 immediate character
 262 The @samp{#} can be optionally used to indicate immediate operands.
 263
 264 @node AArch64-Regs
 265 @subsection Register Names
 266
 267 @cindex AArch64 register names
 268 @cindex register names, AArch64
 269 Please refer to the section @samp{4.4 Register Names} of
 270 @samp{ARMv8 Instruction Set Overview}, which is available at
 271 @uref{http://infocenter.arm.com}.
 272
 273 @node AArch64-Relocations
 274 @subsection Relocations
 275
 276 @cindex relocations, AArch64
 277 @cindex AArch64 relocations
 278 @cindex MOVN, MOVZ and MOVK group relocations, AArch64
 279 Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated
 280 by prefixing the label with @samp{#:abs_g2:} etc.
 281 For example to load the 48-bit absolute address of @var{foo} into x0:
 282
 283 @smallexample
 284         movz x0, #:abs_g2:foo           // bits 32-47, overflow check
 285         movk x0, #:abs_g1_nc:foo        // bits 16-31, no overflow check
 286         movk x0, #:abs_g0_nc:foo        // bits  0-15, no overflow check
 287 @end smallexample
 288
 289 @cindex ADRP, ADD, LDR/STR group relocations, AArch64
 290 Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
 291 instructions can be generated by prefixing the label with
 292 @samp{:pg_hi21:} and @samp{#:lo12:} respectively.
 293
 294 For example to use 33-bit (+/-4GB) pc-relative addressing to
 295 load the address of @var{foo} into x0:
 296
 297 @smallexample
 298         adrp x0, :pg_hi21:foo
 299         add  x0, x0, #:lo12:foo
 300 @end smallexample
 301
 302 Or to load the value of @var{foo} into x0:
 303
 304 @smallexample
 305         adrp x0, :pg_hi21:foo
 306         ldr  x0, [x0, #:lo12:foo]
 307 @end smallexample
 308
 309 Note that @samp{:pg_hi21:} is optional.
 310
 311 @smallexample
 312         adrp x0, foo
 313 @end smallexample
 314
 315 is equivalent to
 316
 317 @smallexample
 318         adrp x0, :pg_hi21:foo
 319 @end smallexample
 320
 321 @node AArch64 Floating Point
 322 @section Floating Point
 323
 324 @cindex floating point, AArch64 (@sc{ieee})
 325 @cindex AArch64 floating point (@sc{ieee})
 326 The AArch64 architecture uses @sc{ieee} floating-point numbers.
 327
 328 @node AArch64 Directives
 329 @section AArch64 Machine Directives
 330
 331 @cindex machine directives, AArch64
 332 @cindex AArch64 machine directives
 333 @table @code
 334
 335 @c AAAAAAAAAAAAAAAAAAAAAAAAA
 336
 337 @cindex @code{.arch} directive, AArch64
 338 @item .arch @var{name}
 339 Select the target architecture.  Valid values for @var{name} are the same as
 340 for the @option{-march} command-line option.
 341
 342 Specifying @code{.arch} clears any previously selected architecture
 343 extensions.
 344
 345 @cindex @code{.arch_extension} directive, AArch64
 346 @item .arch_extension @var{name}
 347 Add or remove an architecture extension to the target architecture.  Valid
 348 values for @var{name} are the same as those accepted as architectural
 349 extensions by the @option{-mcpu} command-line option.
 350
 351 @code{.arch_extension} may be used multiple times to add or remove extensions
 352 incrementally to the architecture being compiled for.
 353
 354 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
 355
 356 @cindex @code{.bss} directive, AArch64
 357 @item .bss
 358 This directive switches to the @code{.bss} section.
 359
 360 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
 361
 362 @cindex @code{.cpu} directive, AArch64
 363 @item .cpu @var{name}
 364 Set the target processor.  Valid values for @var{name} are the same as
 365 those accepted by the @option{-mcpu=} command-line option.
 366
 367 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
 368
 369 @cindex @code{.dword} directive, AArch64
 370 @item .dword @var{expressions}
 371 The @code{.dword} directive produces 64 bit values.
 372
 373 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
 374
 375 @cindex @code{.even} directive, AArch64
 376 @item .even
 377 The @code{.even} directive aligns the output on the next even byte
 378 boundary.
 379
 380 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
 381
 382 @cindex @code{.float16} directive, AArch64
 383 @item .float16 @var{value [,...,value_n]}
 384 Place the half precision floating point representation of one or more
 385 floating-point values into the current section.
 386 The format used to encode the floating point values is always the
 387 IEEE 754-2008 half precision floating point format.
 388
 389 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
 390 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
 391 @c IIIIIIIIIIIIIIIIIIIIIIIIII
 392
 393 @cindex @code{.inst} directive, AArch64
 394 @item .inst @var{expressions}
 395 Inserts the expressions into the output as if they were instructions,
 396 rather than data.
 397
 398 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
 399 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
 400 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
 401
 402 @cindex @code{.ltorg} directive, AArch64
 403 @item .ltorg
 404 This directive causes the current contents of the literal pool to be
 405 dumped into the current section (which is assumed to be the .text
 406 section) at the current location (aligned to a word boundary).
 407 GAS maintains a separate literal pool for each section and each
 408 sub-section.  The @code{.ltorg} directive will only affect the literal
 409 pool of the current section and sub-section.  At the end of assembly
 410 all remaining, un-empty literal pools will automatically be dumped.
 411
 412 Note - older versions of GAS would dump the current literal
 413 pool any time a section change occurred.  This is no longer done, since
 414 it prevents accurate control of the placement of literal pools.
 415
 416 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
 417
 418 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
 419 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
 420
 421 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
 422
 423 @cindex @code{.pool} directive, AArch64
 424 @item .pool
 425 This is a synonym for .ltorg.
 426
 427 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
 428 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
 429
 430 @cindex @code{.req} directive, AArch64
 431 @item @var{name} .req @var{register name}
 432 This creates an alias for @var{register name} called @var{name}.  For
 433 example:
 434
 435 @smallexample
 436         foo .req w0
 437 @end smallexample
 438
 439 ip0, ip1, lr and fp are automatically defined to
 440 alias to X16, X17, X30 and X29 respectively.
 441
 442 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
 443
 444 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
 445
 446 @cindex @code{.tlsdescadd} directive, AArch64
 447 @item   @code{.tlsdescadd}
 448 Emits a TLSDESC_ADD reloc on the next instruction.
 449
 450 @cindex @code{.tlsdesccall} directive, AArch64
 451 @item   @code{.tlsdesccall}
 452 Emits a TLSDESC_CALL reloc on the next instruction.
 453
 454 @cindex @code{.tlsdescldr} directive, AArch64
 455 @item   @code{.tlsdescldr}
 456 Emits a TLSDESC_LDR reloc on the next instruction.
 457
 458 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
 459
 460 @cindex @code{.unreq} directive, AArch64
 461 @item .unreq @var{alias-name}
 462 This undefines a register alias which was previously defined using the
 463 @code{req} directive.  For example:
 464
 465 @smallexample
 466         foo .req w0
 467         .unreq foo
 468 @end smallexample
 469
 470 An error occurs if the name is undefined.  Note - this pseudo op can
 471 be used to delete builtin in register name aliases (eg 'w0').  This
 472 should only be done if it is really necessary.
 473
 474 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
 475
 476 @cindex @code{.variant_pcs} directive, AArch64
 477 @item .variant_pcs @var{symbol}
 478 This directive marks @var{symbol} referencing a function that may
 479 follow a variant procedure call standard with different register
 480 usage convention from the base procedure call standard.
 481
 482 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
 483 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
 484
 485 @cindex @code{.xword} directive, AArch64
 486 @item .xword @var{expressions}
 487 The @code{.xword} directive produces 64 bit values.  This is the same
 488 as the @code{.dword} directive.
 489
 490 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
 491 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
 492
 493 @cindex @code{.cfi_b_key_frame} directive, AArch64
 494 @item   @code{.cfi_b_key_frame}
 495 The @code{.cfi_b_key_frame} directive inserts a 'B' character into the CIE
 496 corresponding to the current frame's FDE, meaning that its return address has
 497 been signed with the B-key.  If two frames are signed with differing keys then
 498 they will not share the same CIE.  This information is intended to be used by
 499 the stack unwinder in order to properly authenticate return addresses.
 500
 501 @end table
 502
 503 @node AArch64 Opcodes
 504 @section Opcodes
 505
 506 @cindex AArch64 opcodes
 507 @cindex opcodes for AArch64
 508 GAS implements all the standard AArch64 opcodes.  It also
 509 implements several pseudo opcodes, including several synthetic load
 510 instructions.
 511
 512 @table @code
 513
 514 @cindex @code{LDR reg,=<expr>} pseudo op, AArch64
 515 @item LDR =
 516 @smallexample
 517   ldr <register> , =<expression>
 518 @end smallexample
 519
 520 The constant expression will be placed into the nearest literal pool (if it not
 521 already there) and a PC-relative LDR instruction will be generated.
 522
 523 @end table
 524
 525 For more information on the AArch64 instruction set and assembly language
 526 notation, see @samp{ARMv8 Instruction Set Overview} available at
 527 @uref{http://infocenter.arm.com}.
 528
 529
 530 @node AArch64 Mapping Symbols
 531 @section Mapping Symbols
 532
 533 The AArch64 ELF specification requires that special symbols be inserted
 534 into object files to mark certain features:
 535
 536 @table @code
 537
 538 @cindex @code{$x}
 539 @item $x
 540 At the start of a region of code containing AArch64 instructions.
 541
 542 @cindex @code{$d}
 543 @item $d
 544 At the start of a region of data.
 545
 546 @end table