1 @c Copyright (C) 1996-2021 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
8 @chapter ARM Dependent Features
12 @node Machine Dependencies
13 @chapter ARM Dependent Features
19 * ARM Options:: Options
21 * ARM Floating Point:: Floating Point
22 * ARM Directives:: ARM Machine Directives
23 * ARM Opcodes:: Opcodes
24 * ARM Mapping Symbols:: Mapping Symbols
25 * ARM Unwinding Tutorial:: Unwinding
30 @cindex ARM options (none)
31 @cindex options for ARM (none)
35 @cindex @code{-mcpu=} command-line option, ARM
36 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
37 This option specifies the target processor. The assembler will issue an
38 error message if an attempt is made to assemble an instruction which
39 will not execute on the target processor. The following processor names are
84 @code{fa526} (Faraday FA526 processor),
85 @code{fa626} (Faraday FA626 processor),
104 @code{fa606te} (Faraday FA606TE processor),
105 @code{fa616te} (Faraday FA616TE processor),
106 @code{fa626te} (Faraday FA626TE processor),
107 @code{fmp626} (Faraday FMP626 processor),
108 @code{fa726te} (Faraday FA726TE processor),
145 @code{cortex-r52plus},
154 @code{cortex-m0plus},
158 @code{marvell-whitney},
164 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
165 @code{i80200} (Intel XScale processor)
166 @code{iwmmxt} (Intel XScale processor with Wireless MMX technology coprocessor)
169 The special name @code{all} may be used to allow the
170 assembler to accept instructions valid for any ARM processor.
172 In addition to the basic instruction set, the assembler can be told to
173 accept various extension mnemonics that extend the processor using the
174 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
175 is equivalent to specifying @code{-mcpu=ep9312}.
177 Multiple extensions may be specified, separated by a @code{+}. The
178 extensions should be specified in ascending alphabetical order.
180 Some extensions may be restricted to particular architectures; this is
181 documented in the list of extensions below.
183 Extension mnemonics may also be removed from those the assembler accepts.
184 This is done be prepending @code{no} to the option that adds the extension.
185 Extensions that are removed should be listed after all extensions which have
186 been added, again in ascending alphabetical order. For example,
187 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
190 The following extensions are currently supported:
191 @code{bf16} (BFloat16 extensions for v8.6-A architecture),
192 @code{i8mm} (Int8 Matrix Multiply extensions for v8.6-A architecture),
194 @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
195 @code{dotprod} (Dot Product Extensions for v8.2-A architecture, implies @code{fp+simd}),
196 @code{fp} (Floating Point Extensions for v8-A architecture),
197 @code{fp16} (FP16 Extensions for v8.2-A architecture, implies @code{fp}),
198 @code{fp16fml} (FP16 Floating Point Multiplication Variant Extensions for v8.2-A architecture, implies @code{fp16}),
199 @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
204 @code{mp} (Multiprocessing Extensions for v7-A and v7-R
206 @code{os} (Operating System for v6M architecture),
207 @code{predres} (Execution and Data Prediction Restriction Instruction for
208 v8-A architectures, added by default from v8.5-A),
209 @code{sb} (Speculation Barrier Instruction for v8-A architectures, added by
210 default from v8.5-A),
211 @code{sec} (Security Extensions for v6K and v7-A architectures),
212 @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
213 @code{virt} (Virtualization Extensions for v7-A architecture, implies
215 @code{pan} (Privileged Access Never Extensions for v8-A architecture),
216 @code{ras} (Reliability, Availability and Serviceability extensions
217 for v8-A architecture),
218 @code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
223 @cindex @code{-march=} command-line option, ARM
224 @item -march=@var{architecture}[+@var{extension}@dots{}]
225 This option specifies the target architecture. The assembler will issue
226 an error message if an attempt is made to assemble an instruction which
227 will not execute on the target architecture. The following architecture
228 names are recognized:
266 @code{armv8.1-m.main},
273 If both @code{-mcpu} and
274 @code{-march} are specified, the assembler will use
275 the setting for @code{-mcpu}.
277 The architecture option can be extended with a set extension options. These
278 extensions are context sensitive, i.e. the same extension may mean different
279 things when used with different architectures. When used together with a
280 @code{-mfpu} option, the union of both feature enablement is taken.
281 See their availability and meaning below:
283 For @code{armv5te}, @code{armv5texp}, @code{armv5tej}, @code{armv6}, @code{armv6j}, @code{armv6k}, @code{armv6z}, @code{armv6kz}, @code{armv6zk}, @code{armv6t2}, @code{armv6kt2} and @code{armv6zt2}:
285 @code{+fp}: Enables VFPv2 instructions.
286 @code{+nofp}: Disables all FPU instrunctions.
290 @code{+fp}: Enables VFPv3 instructions with 16 double-word registers.
291 @code{+nofp}: Disables all FPU instructions.
295 @code{+fp}: Enables VFPv3 instructions with 16 double-word registers.
296 @code{+vfpv3-d16}: Alias for @code{+fp}.
297 @code{+vfpv3}: Enables VFPv3 instructions with 32 double-word registers.
298 @code{+vfpv3-d16-fp16}: Enables VFPv3 with half precision floating-point
299 conversion instructions and 16 double-word registers.
300 @code{+vfpv3-fp16}: Enables VFPv3 with half precision floating-point conversion
301 instructions and 32 double-word registers.
302 @code{+vfpv4-d16}: Enables VFPv4 instructions with 16 double-word registers.
303 @code{+vfpv4}: Enables VFPv4 instructions with 32 double-word registers.
304 @code{+simd}: Enables VFPv3 and NEONv1 instructions with 32 double-word
306 @code{+neon}: Alias for @code{+simd}.
307 @code{+neon-vfpv3}: Alias for @code{+simd}.
308 @code{+neon-fp16}: Enables VFPv3, half precision floating-point conversion and
309 NEONv1 instructions with 32 double-word registers.
310 @code{+neon-vfpv4}: Enables VFPv4 and NEONv1 with Fused-MAC instructions and 32
311 double-word registers.
312 @code{+mp}: Enables Multiprocessing Extensions.
313 @code{+sec}: Enables Security Extensions.
314 @code{+nofp}: Disables all FPU and NEON instructions.
315 @code{+nosimd}: Disables all NEON instructions.
319 @code{+fp}: Enables VFPv4 instructions with 16 double-word registers.
320 @code{+vfpv4-d16}: Alias for @code{+fp}.
321 @code{+vfpv3-d16}: Enables VFPv3 instructions with 16 double-word registers.
322 @code{+vfpv3}: Enables VFPv3 instructions with 32 double-word registers.
323 @code{+vfpv3-d16-fp16}: Enables VFPv3 with half precision floating-point
324 conversion instructions and 16 double-word registers.
325 @code{+vfpv3-fp16}: Enables VFPv3 with half precision floating-point conversion
326 instructions and 32 double-word registers.
327 @code{+vfpv4}: Enables VFPv4 instructions with 32 double-word registers.
328 @code{+simd}: Enables VFPv4 and NEONv1 with Fused-MAC instructions and 32
329 double-word registers.
330 @code{+neon-vfpv4}: Alias for @code{+simd}.
331 @code{+neon}: Enables VFPv3 and NEONv1 instructions with 32 double-word
333 @code{+neon-vfpv3}: Alias for @code{+neon}.
334 @code{+neon-fp16}: Enables VFPv3, half precision floating-point conversion and
335 NEONv1 instructions with 32 double-word registers.
336 double-word registers.
337 @code{+nofp}: Disables all FPU and NEON instructions.
338 @code{+nosimd}: Disables all NEON instructions.
342 @code{+fp.sp}: Enables single-precision only VFPv3 instructions with 16
343 double-word registers.
344 @code{+vfpv3xd}: Alias for @code{+fp.sp}.
345 @code{+fp}: Enables VFPv3 instructions with 16 double-word registers.
346 @code{+vfpv3-d16}: Alias for @code{+fp}.
347 @code{+vfpv3xd-fp16}: Enables single-precision only VFPv3 and half
348 floating-point conversion instructions with 16 double-word registers.
349 @code{+vfpv3-d16-fp16}: Enables VFPv3 and half precision floating-point
350 conversion instructions with 16 double-word registers.
351 @code{+idiv}: Enables integer division instructions in ARM mode.
352 @code{+nofp}: Disables all FPU instructions.
356 @code{+fp}: Enables single-precision only VFPv4 instructions with 16
357 double-word registers.
358 @code{+vfpvf4-sp-d16}: Alias for @code{+fp}.
359 @code{+fpv5}: Enables single-precision only VFPv5 instructions with 16
360 double-word registers.
361 @code{+fp.dp}: Enables VFPv5 instructions with 16 double-word registers.
362 @code{+fpv5-d16"}: Alias for @code{+fp.dp}.
363 @code{+nofp}: Disables all FPU instructions.
365 For @code{armv8-m.main}:
367 @code{+dsp}: Enables DSP Extension.
368 @code{+fp}: Enables single-precision only VFPv5 instructions with 16
369 double-word registers.
370 @code{+fp.dp}: Enables VFPv5 instructions with 16 double-word registers.
371 @code{+cdecp0} (CDE extensions for v8-m architecture with coprocessor 0),
372 @code{+cdecp1} (CDE extensions for v8-m architecture with coprocessor 1),
373 @code{+cdecp2} (CDE extensions for v8-m architecture with coprocessor 2),
374 @code{+cdecp3} (CDE extensions for v8-m architecture with coprocessor 3),
375 @code{+cdecp4} (CDE extensions for v8-m architecture with coprocessor 4),
376 @code{+cdecp5} (CDE extensions for v8-m architecture with coprocessor 5),
377 @code{+cdecp6} (CDE extensions for v8-m architecture with coprocessor 6),
378 @code{+cdecp7} (CDE extensions for v8-m architecture with coprocessor 7),
379 @code{+nofp}: Disables all FPU instructions.
380 @code{+nodsp}: Disables DSP Extension.
382 For @code{armv8.1-m.main}:
384 @code{+dsp}: Enables DSP Extension.
385 @code{+fp}: Enables single and half precision scalar Floating Point Extensions
386 for Armv8.1-M Mainline with 16 double-word registers.
387 @code{+fp.dp}: Enables double precision scalar Floating Point Extensions for
388 Armv8.1-M Mainline, implies @code{+fp}.
389 @code{+mve}: Enables integer only M-profile Vector Extension for
390 Armv8.1-M Mainline, implies @code{+dsp}.
391 @code{+mve.fp}: Enables Floating Point M-profile Vector Extension for
392 Armv8.1-M Mainline, implies @code{+mve} and @code{+fp}.
393 @code{+nofp}: Disables all FPU instructions.
394 @code{+nodsp}: Disables DSP Extension.
395 @code{+nomve}: Disables all M-profile Vector Extensions.
399 @code{+crc}: Enables CRC32 Extension.
400 @code{+simd}: Enables VFP and NEON for Armv8-A.
401 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
403 @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
404 @code{+predres}: Enables Execution and Data Prediction Restriction Instruction
406 @code{+nofp}: Disables all FPU, NEON and Cryptography Extensions.
407 @code{+nocrypto}: Disables Cryptography Extensions.
409 For @code{armv8.1-a}:
411 @code{+simd}: Enables VFP and NEON for Armv8.1-A.
412 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
414 @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
415 @code{+predres}: Enables Execution and Data Prediction Restriction Instruction
417 @code{+nofp}: Disables all FPU, NEON and Cryptography Extensions.
418 @code{+nocrypto}: Disables Cryptography Extensions.
420 For @code{armv8.2-a} and @code{armv8.3-a}:
422 @code{+simd}: Enables VFP and NEON for Armv8.1-A.
423 @code{+fp16}: Enables FP16 Extension for Armv8.2-A, implies @code{+simd}.
424 @code{+fp16fml}: Enables FP16 Floating Point Multiplication Variant Extensions
425 for Armv8.2-A, implies @code{+fp16}.
426 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
428 @code{+dotprod}: Enables Dot Product Extensions for Armv8.2-A, implies
430 @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
431 @code{+predres}: Enables Execution and Data Prediction Restriction Instruction
433 @code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions.
434 @code{+nocrypto}: Disables Cryptography Extensions.
436 For @code{armv8.4-a}:
438 @code{+simd}: Enables VFP and NEON for Armv8.1-A and Dot Product Extensions for
440 @code{+fp16}: Enables FP16 Floating Point and Floating Point Multiplication
441 Variant Extensions for Armv8.2-A, implies @code{+simd}.
442 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
444 @code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
445 @code{+predres}: Enables Execution and Data Prediction Restriction Instruction
447 @code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions.
448 @code{+nocryptp}: Disables Cryptography Extensions.
450 For @code{armv8.5-a}:
452 @code{+simd}: Enables VFP and NEON for Armv8.1-A and Dot Product Extensions for
454 @code{+fp16}: Enables FP16 Floating Point and Floating Point Multiplication
455 Variant Extensions for Armv8.2-A, implies @code{+simd}.
456 @code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
458 @code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions.
459 @code{+nocryptp}: Disables Cryptography Extensions.
462 @cindex @code{-mfpu=} command-line option, ARM
463 @item -mfpu=@var{floating-point-format}
465 This option specifies the floating point format to assemble for. The
466 assembler will issue an error message if an attempt is made to assemble
467 an instruction which will not execute on the target floating point unit.
468 The following format options are recognized:
488 @code{vfpv3-d16-fp16},
505 @code{neon-fp-armv8},
506 @code{crypto-neon-fp-armv8},
507 @code{neon-fp-armv8.1}
509 @code{crypto-neon-fp-armv8.1}.
511 In addition to determining which instructions are assembled, this option
512 also affects the way in which the @code{.double} assembler directive behaves
513 when assembling little-endian code.
515 The default is dependent on the processor selected. For Architecture 5 or
516 later, the default is to assemble for VFP instructions; for earlier
517 architectures the default is to assemble for FPA instructions.
519 @cindex @code{-mfp16-format=} command-line option
520 @item -mfp16-format=@var{format}
521 This option specifies the half-precision floating point format to use
522 when assembling floating point numbers emitted by the @code{.float16}
524 The following format options are recognized:
527 If @code{ieee} is specified then the IEEE 754-2008 half-precision floating
528 point format is used, if @code{alternative} is specified then the Arm
529 alternative half-precision format is used. If this option is set on the
530 command line then the format is fixed and cannot be changed with
531 the @code{float16_format} directive. If this value is not set then
532 the IEEE 754-2008 format is used until the format is explicitly set with
533 the @code{float16_format} directive.
535 @cindex @code{-mthumb} command-line option, ARM
537 This option specifies that the assembler should start assembling Thumb
538 instructions; that is, it should behave as though the file starts with a
539 @code{.code 16} directive.
541 @cindex @code{-mthumb-interwork} command-line option, ARM
542 @item -mthumb-interwork
543 This option specifies that the output generated by the assembler should
544 be marked as supporting interworking. It also affects the behaviour
545 of the @code{ADR} and @code{ADRL} pseudo opcodes.
547 @cindex @code{-mimplicit-it} command-line option, ARM
548 @item -mimplicit-it=never
549 @itemx -mimplicit-it=always
550 @itemx -mimplicit-it=arm
551 @itemx -mimplicit-it=thumb
552 The @code{-mimplicit-it} option controls the behavior of the assembler when
553 conditional instructions are not enclosed in IT blocks.
554 There are four possible behaviors.
555 If @code{never} is specified, such constructs cause a warning in ARM
556 code and an error in Thumb-2 code.
557 If @code{always} is specified, such constructs are accepted in both
558 ARM and Thumb-2 code, where the IT instruction is added implicitly.
559 If @code{arm} is specified, such constructs are accepted in ARM code
560 and cause an error in Thumb-2 code.
561 If @code{thumb} is specified, such constructs cause a warning in ARM
562 code and are accepted in Thumb-2 code. If you omit this option, the
563 behavior is equivalent to @code{-mimplicit-it=arm}.
565 @cindex @code{-mapcs-26} command-line option, ARM
566 @cindex @code{-mapcs-32} command-line option, ARM
569 These options specify that the output generated by the assembler should
570 be marked as supporting the indicated version of the Arm Procedure.
573 @cindex @code{-matpcs} command-line option, ARM
575 This option specifies that the output generated by the assembler should
576 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
577 enabled this option will cause the assembler to create an empty
578 debugging section in the object file called .arm.atpcs. Debuggers can
579 use this to determine the ABI being used by.
581 @cindex @code{-mapcs-float} command-line option, ARM
583 This indicates the floating point variant of the APCS should be
584 used. In this variant floating point arguments are passed in FP
585 registers rather than integer registers.
587 @cindex @code{-mapcs-reentrant} command-line option, ARM
588 @item -mapcs-reentrant
589 This indicates that the reentrant variant of the APCS should be used.
590 This variant supports position independent code.
592 @cindex @code{-mfloat-abi=} command-line option, ARM
593 @item -mfloat-abi=@var{abi}
594 This option specifies that the output generated by the assembler should be
595 marked as using specified floating point ABI.
596 The following values are recognized:
602 @cindex @code{-eabi=} command-line option, ARM
603 @item -meabi=@var{ver}
604 This option specifies which EABI version the produced object files should
606 The following values are recognized:
612 @cindex @code{-EB} command-line option, ARM
614 This option specifies that the output generated by the assembler should
615 be marked as being encoded for a big-endian processor.
617 Note: If a program is being built for a system with big-endian data
618 and little-endian instructions then it should be assembled with the
619 @option{-EB} option, (all of it, code and data) and then linked with
620 the @option{--be8} option. This will reverse the endianness of the
621 instructions back to little-endian, but leave the data as big-endian.
623 @cindex @code{-EL} command-line option, ARM
625 This option specifies that the output generated by the assembler should
626 be marked as being encoded for a little-endian processor.
628 @cindex @code{-k} command-line option, ARM
629 @cindex PIC code generation for ARM
631 This option specifies that the output of the assembler should be marked
632 as position-independent code (PIC).
634 @cindex @code{--fix-v4bx} command-line option, ARM
636 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
637 the linker option of the same name.
639 @cindex @code{-mwarn-deprecated} command-line option, ARM
640 @item -mwarn-deprecated
641 @itemx -mno-warn-deprecated
642 Enable or disable warnings about using deprecated options or
643 features. The default is to warn.
645 @cindex @code{-mccs} command-line option, ARM
647 Turns on CodeComposer Studio assembly syntax compatibility mode.
649 @cindex @code{-mwarn-syms} command-line option, ARM
651 @itemx -mno-warn-syms
652 Enable or disable warnings about symbols that match the names of ARM
653 instructions. The default is to warn.
661 * ARM-Instruction-Set:: Instruction Set
662 * ARM-Chars:: Special Characters
663 * ARM-Regs:: Register Names
664 * ARM-Relocations:: Relocations
665 * ARM-Neon-Alignment:: NEON Alignment Specifiers
668 @node ARM-Instruction-Set
669 @subsection Instruction Set Syntax
670 Two slightly different syntaxes are support for ARM and THUMB
671 instructions. The default, @code{divided}, uses the old style where
672 ARM and THUMB instructions had their own, separate syntaxes. The new,
673 @code{unified} syntax, which can be selected via the @code{.syntax}
674 directive, and has the following main features:
678 Immediate operands do not require a @code{#} prefix.
681 The @code{IT} instruction may appear, and if it does it is validated
682 against subsequent conditional affixes. In ARM mode it does not
683 generate machine code, in THUMB mode it does.
686 For ARM instructions the conditional affixes always appear at the end
687 of the instruction. For THUMB instructions conditional affixes can be
688 used, but only inside the scope of an @code{IT} instruction.
691 All of the instructions new to the V6T2 architecture (and later) are
692 available. (Only a few such instructions can be written in the
693 @code{divided} syntax).
696 The @code{.N} and @code{.W} suffixes are recognized and honored.
699 All instructions set the flags if and only if they have an @code{s}
704 @subsection Special Characters
706 @cindex line comment character, ARM
707 @cindex ARM line comment character
708 The presence of a @samp{@@} anywhere on a line indicates the start of
709 a comment that extends to the end of that line.
711 If a @samp{#} appears as the first character of a line then the whole
712 line is treated as a comment, but in this case the line could also be
713 a logical line number directive (@pxref{Comments}) or a preprocessor
714 control command (@pxref{Preprocessing}).
716 @cindex line separator, ARM
717 @cindex statement separator, ARM
718 @cindex ARM line separator
719 The @samp{;} character can be used instead of a newline to separate
722 @cindex immediate character, ARM
723 @cindex ARM immediate character
724 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
726 @cindex identifiers, ARM
727 @cindex ARM identifiers
728 *TODO* Explain about /data modifier on symbols.
731 @subsection Register Names
733 @cindex ARM register names
734 @cindex register names, ARM
735 *TODO* Explain about ARM register naming, and the predefined names.
737 @node ARM-Relocations
738 @subsection ARM relocation generation
740 @cindex data relocations, ARM
741 @cindex ARM data relocations
742 Specific data relocations can be generated by putting the relocation name
743 in parentheses after the symbol name. For example:
749 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
751 The following relocations are supported:
767 For compatibility with older toolchains the assembler also accepts
768 @code{(PLT)} after branch targets. On legacy targets this will
769 generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI
770 targets it will encode either the @samp{R_ARM_CALL} or
771 @samp{R_ARM_JUMP24} relocation, as appropriate.
773 @cindex MOVW and MOVT relocations, ARM
774 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
775 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
776 respectively. For example to load the 32-bit address of foo into r0:
779 MOVW r0, #:lower16:foo
780 MOVT r0, #:upper16:foo
783 Relocations @samp{R_ARM_THM_ALU_ABS_G0_NC}, @samp{R_ARM_THM_ALU_ABS_G1_NC},
784 @samp{R_ARM_THM_ALU_ABS_G2_NC} and @samp{R_ARM_THM_ALU_ABS_G3_NC} can be
785 generated by prefixing the value with @samp{#:lower0_7:#},
786 @samp{#:lower8_15:#}, @samp{#:upper0_7:#} and @samp{#:upper8_15:#}
787 respectively. For example to load the 32-bit address of foo into r0:
790 MOVS r0, #:upper8_15:#foo
792 ADDS r0, #:upper0_7:#foo
794 ADDS r0, #:lower8_15:#foo
796 ADDS r0, #:lower0_7:#foo
799 @node ARM-Neon-Alignment
800 @subsection NEON Alignment Specifiers
802 @cindex alignment for NEON instructions
803 Some NEON load/store instructions allow an optional address
805 The ARM documentation specifies that this is indicated by
806 @samp{@@ @var{align}}. However GAS already interprets
807 the @samp{@@} character as a "line comment" start,
808 so @samp{: @var{align}} is used instead. For example:
811 vld1.8 @{q0@}, [r0, :128]
814 @node ARM Floating Point
815 @section Floating Point
817 @cindex floating point, ARM (@sc{ieee})
818 @cindex ARM floating point (@sc{ieee})
819 The ARM family uses @sc{ieee} floating-point numbers.
822 @section ARM Machine Directives
824 @cindex machine directives, ARM
825 @cindex ARM machine directives
828 @c AAAAAAAAAAAAAAAAAAAAAAAAA
831 @cindex @code{.2byte} directive, ARM
832 @cindex @code{.4byte} directive, ARM
833 @cindex @code{.8byte} directive, ARM
834 @item .2byte @var{expression} [, @var{expression}]*
835 @itemx .4byte @var{expression} [, @var{expression}]*
836 @itemx .8byte @var{expression} [, @var{expression}]*
837 These directives write 2, 4 or 8 byte values to the output section.
840 @cindex @code{.align} directive, ARM
841 @item .align @var{expression} [, @var{expression}]
842 This is the generic @var{.align} directive. For the ARM however if the
843 first argument is zero (ie no alignment is needed) the assembler will
844 behave as if the argument had been 2 (ie pad to the next four byte
845 boundary). This is for compatibility with ARM's own assembler.
847 @cindex @code{.arch} directive, ARM
848 @item .arch @var{name}
849 Select the target architecture. Valid values for @var{name} are the same as
850 for the @option{-march} command-line option without the instruction set
853 Specifying @code{.arch} clears any previously selected architecture
856 @cindex @code{.arch_extension} directive, ARM
857 @item .arch_extension @var{name}
858 Add or remove an architecture extension to the target architecture. Valid
859 values for @var{name} are the same as those accepted as architectural
860 extensions by the @option{-mcpu} and @option{-march} command-line options.
862 @code{.arch_extension} may be used multiple times to add or remove extensions
863 incrementally to the architecture being compiled for.
865 @cindex @code{.arm} directive, ARM
867 This performs the same action as @var{.code 32}.
869 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
871 @cindex @code{.bss} directive, ARM
873 This directive switches to the @code{.bss} section.
875 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
877 @cindex @code{.cantunwind} directive, ARM
879 Prevents unwinding through the current function. No personality routine
880 or exception table data is required or permitted.
882 @cindex @code{.code} directive, ARM
883 @item .code @code{[16|32]}
884 This directive selects the instruction set being generated. The value 16
885 selects Thumb, with the value 32 selecting ARM.
887 @cindex @code{.cpu} directive, ARM
888 @item .cpu @var{name}
889 Select the target processor. Valid values for @var{name} are the same as
890 for the @option{-mcpu} command-line option without the instruction set
893 Specifying @code{.cpu} clears any previously selected architecture
896 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
898 @cindex @code{.dn} and @code{.qn} directives, ARM
899 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
900 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
902 The @code{dn} and @code{qn} directives are used to create typed
903 and/or indexed register aliases for use in Advanced SIMD Extension
904 (Neon) instructions. The former should be used to create aliases
905 of double-precision registers, and the latter to create aliases of
906 quad-precision registers.
908 If these directives are used to create typed aliases, those aliases can
909 be used in Neon instructions instead of writing types after the mnemonic
910 or after each operand. For example:
919 This is equivalent to writing the following:
925 Aliases created using @code{dn} or @code{qn} can be destroyed using
928 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
930 @cindex @code{.eabi_attribute} directive, ARM
931 @item .eabi_attribute @var{tag}, @var{value}
932 Set the EABI object attribute @var{tag} to @var{value}.
934 The @var{tag} is either an attribute number, or one of the following:
935 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
936 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
937 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
938 @code{Tag_Advanced_SIMD_arch}, @code{Tag_MVE_arch}, @code{Tag_PCS_config},
939 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
940 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
941 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
942 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
943 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
944 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
945 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
946 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
947 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
948 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
949 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
950 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
951 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
952 @code{Tag_conformance}, @code{Tag_T2EE_use},
953 @code{Tag_Virtualization_use}
955 The @var{value} is either a @code{number}, @code{"string"}, or
956 @code{number, "string"} depending on the tag.
958 Note - the following legacy values are also accepted by @var{tag}:
959 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
960 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
962 @cindex @code{.even} directive, ARM
964 This directive aligns to an even-numbered address.
966 @cindex @code{.extend} directive, ARM
967 @cindex @code{.ldouble} directive, ARM
968 @item .extend @var{expression} [, @var{expression}]*
969 @itemx .ldouble @var{expression} [, @var{expression}]*
970 These directives write 12byte long double floating-point values to the
971 output section. These are not compatible with current ARM processors
974 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
976 @cindex @code{.float16} directive, ARM
977 @item .float16 @var{value [,...,value_n]}
978 Place the half precision floating point representation of one or more
979 floating-point values into the current section. The exact format of the
980 encoding is specified by @code{.float16_format}. If the format has not
981 been explicitly set yet (either via the @code{.float16_format} directive or
982 the command line option) then the IEEE 754-2008 format is used.
984 @cindex @code{.float16_format} directive, ARM
985 @item .float16_format @var{format}
986 Set the format to use when encoding float16 values emitted by
987 the @code{.float16} directive.
988 Once the format has been set it cannot be changed.
989 @code{format} should be one of the following: @code{ieee} (encode in
990 the IEEE 754-2008 half precision format) or @code{alternative} (encode in
991 the Arm alternative half precision format).
994 @cindex @code{.fnend} directive, ARM
996 Marks the end of a function with an unwind table entry. The unwind index
997 table entry is created when this directive is processed.
999 If no personality routine has been specified then standard personality
1000 routine 0 or 1 will be used, depending on the number of unwind opcodes
1003 @anchor{arm_fnstart}
1004 @cindex @code{.fnstart} directive, ARM
1006 Marks the start of a function with an unwind table entry.
1008 @cindex @code{.force_thumb} directive, ARM
1010 This directive forces the selection of Thumb instructions, even if the
1011 target processor does not support those instructions
1013 @cindex @code{.fpu} directive, ARM
1014 @item .fpu @var{name}
1015 Select the floating-point unit to assemble for. Valid values for @var{name}
1016 are the same as for the @option{-mfpu} command-line option.
1018 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
1019 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
1021 @cindex @code{.handlerdata} directive, ARM
1023 Marks the end of the current function, and the start of the exception table
1024 entry for that function. Anything between this directive and the
1025 @code{.fnend} directive will be added to the exception table entry.
1027 Must be preceded by a @code{.personality} or @code{.personalityindex}
1030 @c IIIIIIIIIIIIIIIIIIIIIIIIII
1032 @cindex @code{.inst} directive, ARM
1033 @item .inst @var{opcode} [ , @dots{} ]
1034 @itemx .inst.n @var{opcode} [ , @dots{} ]
1035 @itemx .inst.w @var{opcode} [ , @dots{} ]
1036 Generates the instruction corresponding to the numerical value @var{opcode}.
1037 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
1038 specified explicitly, overriding the normal encoding rules.
1040 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
1041 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
1042 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
1044 @item .ldouble @var{expression} [, @var{expression}]*
1047 @cindex @code{.ltorg} directive, ARM
1049 This directive causes the current contents of the literal pool to be
1050 dumped into the current section (which is assumed to be the .text
1051 section) at the current location (aligned to a word boundary).
1052 @code{GAS} maintains a separate literal pool for each section and each
1053 sub-section. The @code{.ltorg} directive will only affect the literal
1054 pool of the current section and sub-section. At the end of assembly
1055 all remaining, un-empty literal pools will automatically be dumped.
1057 Note - older versions of @code{GAS} would dump the current literal
1058 pool any time a section change occurred. This is no longer done, since
1059 it prevents accurate control of the placement of literal pools.
1061 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
1063 @cindex @code{.movsp} directive, ARM
1064 @item .movsp @var{reg} [, #@var{offset}]
1065 Tell the unwinder that @var{reg} contains an offset from the current
1066 stack pointer. If @var{offset} is not specified then it is assumed to be
1069 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
1070 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
1072 @cindex @code{.object_arch} directive, ARM
1073 @item .object_arch @var{name}
1074 Override the architecture recorded in the EABI object attribute section.
1075 Valid values for @var{name} are the same as for the @code{.arch} directive.
1076 Typically this is useful when code uses runtime detection of CPU features.
1078 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
1080 @cindex @code{.packed} directive, ARM
1081 @item .packed @var{expression} [, @var{expression}]*
1082 This directive writes 12-byte packed floating-point values to the
1083 output section. These are not compatible with current ARM processors
1087 @cindex @code{.pad} directive, ARM
1088 @item .pad #@var{count}
1089 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
1090 A positive value indicates the function prologue allocated stack space by
1091 decrementing the stack pointer.
1093 @cindex @code{.personality} directive, ARM
1094 @item .personality @var{name}
1095 Sets the personality routine for the current function to @var{name}.
1097 @cindex @code{.personalityindex} directive, ARM
1098 @item .personalityindex @var{index}
1099 Sets the personality routine for the current function to the EABI standard
1100 routine number @var{index}
1102 @cindex @code{.pool} directive, ARM
1104 This is a synonym for .ltorg.
1106 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
1107 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
1109 @cindex @code{.req} directive, ARM
1110 @item @var{name} .req @var{register name}
1111 This creates an alias for @var{register name} called @var{name}. For
1118 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
1121 @cindex @code{.save} directive, ARM
1122 @item .save @var{reglist}
1123 Generate unwinder annotations to restore the registers in @var{reglist}.
1124 The format of @var{reglist} is the same as the corresponding store-multiple
1128 @exdent @emph{core registers}
1129 .save @{r4, r5, r6, lr@}
1130 stmfd sp!, @{r4, r5, r6, lr@}
1131 @exdent @emph{FPA registers}
1134 @exdent @emph{VFP registers}
1135 .save @{d8, d9, d10@}
1136 fstmdx sp!, @{d8, d9, d10@}
1137 @exdent @emph{iWMMXt registers}
1138 .save @{wr10, wr11@}
1139 wstrd wr11, [sp, #-8]!
1140 wstrd wr10, [sp, #-8]!
1143 wstrd wr11, [sp, #-8]!
1145 wstrd wr10, [sp, #-8]!
1149 @cindex @code{.setfp} directive, ARM
1150 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
1151 Make all unwinder annotations relative to a frame pointer. Without this
1152 the unwinder will use offsets from the stack pointer.
1154 The syntax of this directive is the same as the @code{add} or @code{mov}
1155 instruction used to set the frame pointer. @var{spreg} must be either
1156 @code{sp} or mentioned in a previous @code{.movsp} directive.
1166 @cindex @code{.secrel32} directive, ARM
1167 @item .secrel32 @var{expression} [, @var{expression}]*
1168 This directive emits relocations that evaluate to the section-relative
1169 offset of each expression's symbol. This directive is only supported
1172 @cindex @code{.syntax} directive, ARM
1173 @item .syntax [@code{unified} | @code{divided}]
1174 This directive sets the Instruction Set Syntax as described in the
1175 @ref{ARM-Instruction-Set} section.
1177 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
1179 @cindex @code{.thumb} directive, ARM
1181 This performs the same action as @var{.code 16}.
1183 @cindex @code{.thumb_func} directive, ARM
1185 This directive specifies that the following symbol is the name of a
1186 Thumb encoded function. This information is necessary in order to allow
1187 the assembler and linker to generate correct code for interworking
1188 between Arm and Thumb instructions and should be used even if
1189 interworking is not going to be performed. The presence of this
1190 directive also implies @code{.thumb}
1192 This directive is not necessary when generating EABI objects. On these
1193 targets the encoding is implicit when generating Thumb code.
1195 @cindex @code{.thumb_set} directive, ARM
1197 This performs the equivalent of a @code{.set} directive in that it
1198 creates a symbol which is an alias for another symbol (possibly not yet
1199 defined). This directive also has the added property in that it marks
1200 the aliased symbol as being a thumb function entry point, in the same
1201 way that the @code{.thumb_func} directive does.
1203 @cindex @code{.tlsdescseq} directive, ARM
1204 @item .tlsdescseq @var{tls-variable}
1205 This directive is used to annotate parts of an inlined TLS descriptor
1206 trampoline. Normally the trampoline is provided by the linker, and
1207 this directive is not needed.
1209 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
1211 @cindex @code{.unreq} directive, ARM
1212 @item .unreq @var{alias-name}
1213 This undefines a register alias which was previously defined using the
1214 @code{req}, @code{dn} or @code{qn} directives. For example:
1221 An error occurs if the name is undefined. Note - this pseudo op can
1222 be used to delete builtin in register name aliases (eg 'r0'). This
1223 should only be done if it is really necessary.
1225 @cindex @code{.unwind_raw} directive, ARM
1226 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
1227 Insert one of more arbitrary unwind opcode bytes, which are known to adjust
1228 the stack pointer by @var{offset} bytes.
1230 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
1233 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
1235 @cindex @code{.vsave} directive, ARM
1236 @item .vsave @var{vfp-reglist}
1237 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
1238 using FLDMD. Also works for VFPv3 registers
1239 that are to be restored using VLDM.
1240 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
1244 @exdent @emph{VFP registers}
1245 .vsave @{d8, d9, d10@}
1246 fstmdd sp!, @{d8, d9, d10@}
1247 @exdent @emph{VFPv3 registers}
1248 .vsave @{d15, d16, d17@}
1249 vstm sp!, @{d15, d16, d17@}
1252 Since FLDMX and FSTMX are now deprecated, this directive should be
1253 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
1255 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
1256 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
1257 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
1258 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
1266 @cindex opcodes for ARM
1267 @code{@value{AS}} implements all the standard ARM opcodes. It also
1268 implements several pseudo opcodes, including several synthetic load
1273 @cindex @code{NOP} pseudo op, ARM
1279 This pseudo op will always evaluate to a legal ARM instruction that does
1280 nothing. Currently it will evaluate to MOV r0, r0.
1282 @cindex @code{LDR reg,=<label>} pseudo op, ARM
1285 ldr <register> , = <expression>
1288 If expression evaluates to a numeric constant then a MOV or MVN
1289 instruction will be used in place of the LDR instruction, if the
1290 constant can be generated by either of these instructions. Otherwise
1291 the constant will be placed into the nearest literal pool (if it not
1292 already there) and a PC relative LDR instruction will be generated.
1294 @cindex @code{ADR reg,<label>} pseudo op, ARM
1297 adr <register> <label>
1300 This instruction will load the address of @var{label} into the indicated
1301 register. The instruction will evaluate to a PC relative ADD or SUB
1302 instruction depending upon where the label is located. If the label is
1303 out of range, or if it is not defined in the same file (and section) as
1304 the ADR instruction, then an error will be generated. This instruction
1305 will not make use of the literal pool.
1307 If @var{label} is a thumb function symbol, and thumb interworking has
1308 been enabled via the @option{-mthumb-interwork} option then the bottom
1309 bit of the value stored into @var{register} will be set. This allows
1310 the following sequence to work as expected:
1313 adr r0, thumb_function
1317 @cindex @code{ADRL reg,<label>} pseudo op, ARM
1320 adrl <register> <label>
1323 This instruction will load the address of @var{label} into the indicated
1324 register. The instruction will evaluate to one or two PC relative ADD
1325 or SUB instructions depending upon where the label is located. If a
1326 second instruction is not needed a NOP instruction will be generated in
1327 its place, so that this instruction is always 8 bytes long.
1329 If the label is out of range, or if it is not defined in the same file
1330 (and section) as the ADRL instruction, then an error will be generated.
1331 This instruction will not make use of the literal pool.
1333 If @var{label} is a thumb function symbol, and thumb interworking has
1334 been enabled via the @option{-mthumb-interwork} option then the bottom
1335 bit of the value stored into @var{register} will be set.
1339 For information on the ARM or Thumb instruction sets, see @cite{ARM
1340 Software Development Toolkit Reference Manual}, Advanced RISC Machines
1343 @node ARM Mapping Symbols
1344 @section Mapping Symbols
1346 The ARM ELF specification requires that special symbols be inserted
1347 into object files to mark certain features:
1353 At the start of a region of code containing ARM instructions.
1357 At the start of a region of code containing THUMB instructions.
1361 At the start of a region of data.
1365 The assembler will automatically insert these symbols for you - there
1366 is no need to code them yourself. Support for tagging symbols ($b,
1367 $f, $p and $m) which is also mentioned in the current ARM ELF
1368 specification is not implemented. This is because they have been
1369 dropped from the new EABI and so tools cannot rely upon their
1372 @node ARM Unwinding Tutorial
1375 The ABI for the ARM Architecture specifies a standard format for
1376 exception unwind information. This information is used when an
1377 exception is thrown to determine where control should be transferred.
1378 In particular, the unwind information is used to determine which
1379 function called the function that threw the exception, and which
1380 function called that one, and so forth. This information is also used
1381 to restore the values of callee-saved registers in the function
1382 catching the exception.
1384 If you are writing functions in assembly code, and those functions
1385 call other functions that throw exceptions, you must use assembly
1386 pseudo ops to ensure that appropriate exception unwind information is
1387 generated. Otherwise, if one of the functions called by your assembly
1388 code throws an exception, the run-time library will be unable to
1389 unwind the stack through your assembly code and your program will not
1392 To illustrate the use of these pseudo ops, we will examine the code
1393 that G++ generates for the following C++ input:
1396 void callee (int *);
1407 This example does not show how to throw or catch an exception from
1408 assembly code. That is a much more complex operation and should
1409 always be done in a high-level language, such as C++, that directly
1410 supports exceptions.
1412 The code generated by one particular version of G++ when compiling the
1419 @ Function supports interworking.
1420 @ args = 0, pretend = 0, frame = 8
1421 @ frame_needed = 1, uses_anonymous_args = 0
1443 Of course, the sequence of instructions varies based on the options
1444 you pass to GCC and on the version of GCC in use. The exact
1445 instructions are not important since we are focusing on the pseudo ops
1446 that are used to generate unwind information.
1448 An important assumption made by the unwinder is that the stack frame
1449 does not change during the body of the function. In particular, since
1450 we assume that the assembly code does not itself throw an exception,
1451 the only point where an exception can be thrown is from a call, such
1452 as the @code{bl} instruction above. At each call site, the same saved
1453 registers (including @code{lr}, which indicates the return address)
1454 must be located in the same locations relative to the frame pointer.
1456 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1457 op appears immediately before the first instruction of the function
1458 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1459 op appears immediately after the last instruction of the function.
1460 These pseudo ops specify the range of the function.
1462 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1463 @code{.pad}) matters; their exact locations are irrelevant. In the
1464 example above, the compiler emits the pseudo ops with particular
1465 instructions. That makes it easier to understand the code, but it is
1466 not required for correctness. It would work just as well to emit all
1467 of the pseudo ops other than @code{.fnend} in the same order, but
1468 immediately after @code{.fnstart}.
1470 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1471 indicates registers that have been saved to the stack so that they can
1472 be restored before the function returns. The argument to the
1473 @code{.save} pseudo op is a list of registers to save. If a register
1474 is ``callee-saved'' (as specified by the ABI) and is modified by the
1475 function you are writing, then your code must save the value before it
1476 is modified and restore the original value before the function
1477 returns. If an exception is thrown, the run-time library restores the
1478 values of these registers from their locations on the stack before
1479 returning control to the exception handler. (Of course, if an
1480 exception is not thrown, the function that contains the @code{.save}
1481 pseudo op restores these registers in the function epilogue, as is
1482 done with the @code{ldmfd} instruction above.)
1484 You do not have to save callee-saved registers at the very beginning
1485 of the function and you do not need to use the @code{.save} pseudo op
1486 immediately following the point at which the registers are saved.
1487 However, if you modify a callee-saved register, you must save it on
1488 the stack before modifying it and before calling any functions which
1489 might throw an exception. And, you must use the @code{.save} pseudo
1490 op to indicate that you have done so.
1492 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1493 modification of the stack pointer that does not save any registers.
1494 The argument is the number of bytes (in decimal) that are subtracted
1495 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1496 subtracting from the stack pointer increases the size of the stack.)
1498 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1499 indicates the register that contains the frame pointer. The first
1500 argument is the register that is set, which is typically @code{fp}.
1501 The second argument indicates the register from which the frame
1502 pointer takes its value. The third argument, if present, is the value
1503 (in decimal) added to the register specified by the second argument to
1504 compute the value of the frame pointer. You should not modify the
1505 frame pointer in the body of the function.
1507 If you do not use a frame pointer, then you should not use the
1508 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1509 should avoid modifying the stack pointer outside of the function
1510 prologue. Otherwise, the run-time library will be unable to find
1511 saved registers when it is unwinding the stack.
1513 The pseudo ops described above are sufficient for writing assembly
1514 code that calls functions which may throw exceptions. If you need to
1515 know more about the object-file format used to represent unwind
1516 information, you may consult the @cite{Exception Handling ABI for the
1517 ARM Architecture} available from @uref{http://infocenter.arm.com}.
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