1 @c Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
2 @c 2008, 2009 Free Software Foundation, Inc.
3 @c This is part of the GAS manual.
4 @c For copying conditions, see the file as.texinfo.
9 @chapter ARM Dependent Features
13 @node Machine Dependencies
14 @chapter ARM Dependent Features
20 * ARM Options:: Options
22 * ARM Floating Point:: Floating Point
23 * ARM Directives:: ARM Machine Directives
24 * ARM Opcodes:: Opcodes
25 * ARM Mapping Symbols:: Mapping Symbols
26 * ARM Unwinding Tutorial:: Unwinding
31 @cindex ARM options (none)
32 @cindex options for ARM (none)
36 @cindex @code{-mcpu=} command line option, ARM
37 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
38 This option specifies the target processor. The assembler will issue an
39 error message if an attempt is made to assemble an instruction which
40 will not execute on the target processor. The following processor names are
85 @code{fa526} (Faraday FA526 processor),
86 @code{fa626} (Faraday FA626 processor),
105 @code{fa626te} (Faraday FA626TE processor),
106 @code{fa726te} (Faraday FA726TE processor),
121 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
122 @code{i80200} (Intel XScale processor)
123 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
126 The special name @code{all} may be used to allow the
127 assembler to accept instructions valid for any ARM processor.
129 In addition to the basic instruction set, the assembler can be told to
130 accept various extension mnemonics that extend the processor using the
131 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
132 is equivalent to specifying @code{-mcpu=ep9312}. The following extensions
133 are currently supported:
139 @cindex @code{-march=} command line option, ARM
140 @item -march=@var{architecture}[+@var{extension}@dots{}]
141 This option specifies the target architecture. The assembler will issue
142 an error message if an attempt is made to assemble an instruction which
143 will not execute on the target architecture. The following architecture
144 names are recognized:
172 If both @code{-mcpu} and
173 @code{-march} are specified, the assembler will use
174 the setting for @code{-mcpu}.
176 The architecture option can be extended with the same instruction set
177 extension options as the @code{-mcpu} option.
179 @cindex @code{-mfpu=} command line option, ARM
180 @item -mfpu=@var{floating-point-format}
182 This option specifies the floating point format to assemble for. The
183 assembler will issue an error message if an attempt is made to assemble
184 an instruction which will not execute on the target floating point unit.
185 The following format options are recognized:
211 In addition to determining which instructions are assembled, this option
212 also affects the way in which the @code{.double} assembler directive behaves
213 when assembling little-endian code.
215 The default is dependent on the processor selected. For Architecture 5 or
216 later, the default is to assembler for VFP instructions; for earlier
217 architectures the default is to assemble for FPA instructions.
219 @cindex @code{-mthumb} command line option, ARM
221 This option specifies that the assembler should start assembling Thumb
222 instructions; that is, it should behave as though the file starts with a
223 @code{.code 16} directive.
225 @cindex @code{-mthumb-interwork} command line option, ARM
226 @item -mthumb-interwork
227 This option specifies that the output generated by the assembler should
228 be marked as supporting interworking.
230 @cindex @code{-mimplicit-it} command line option, ARM
231 @item -mimplicit-it=never
232 @itemx -mimplicit-it=always
233 @itemx -mimplicit-it=arm
234 @itemx -mimplicit-it=thumb
235 The @code{-mimplicit-it} option controls the behavior of the assembler when
236 conditional instructions are not enclosed in IT blocks.
237 There are four possible behaviors.
238 If @code{never} is specified, such constructs cause a warning in ARM
239 code and an error in Thumb-2 code.
240 If @code{always} is specified, such constructs are accepted in both
241 ARM and Thumb-2 code, where the IT instruction is added implicitly.
242 If @code{arm} is specified, such constructs are accepted in ARM code
243 and cause an error in Thumb-2 code.
244 If @code{thumb} is specified, such constructs cause a warning in ARM
245 code and are accepted in Thumb-2 code. If you omit this option, the
246 behavior is equivalent to @code{-mimplicit-it=arm}.
248 @cindex @code{-mapcs} command line option, ARM
249 @item -mapcs @code{[26|32]}
250 This option specifies that the output generated by the assembler should
251 be marked as supporting the indicated version of the Arm Procedure.
254 @cindex @code{-matpcs} command line option, ARM
256 This option specifies that the output generated by the assembler should
257 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
258 enabled this option will cause the assembler to create an empty
259 debugging section in the object file called .arm.atpcs. Debuggers can
260 use this to determine the ABI being used by.
262 @cindex @code{-mapcs-float} command line option, ARM
264 This indicates the floating point variant of the APCS should be
265 used. In this variant floating point arguments are passed in FP
266 registers rather than integer registers.
268 @cindex @code{-mapcs-reentrant} command line option, ARM
269 @item -mapcs-reentrant
270 This indicates that the reentrant variant of the APCS should be used.
271 This variant supports position independent code.
273 @cindex @code{-mfloat-abi=} command line option, ARM
274 @item -mfloat-abi=@var{abi}
275 This option specifies that the output generated by the assembler should be
276 marked as using specified floating point ABI.
277 The following values are recognized:
283 @cindex @code{-eabi=} command line option, ARM
284 @item -meabi=@var{ver}
285 This option specifies which EABI version the produced object files should
287 The following values are recognized:
293 @cindex @code{-EB} command line option, ARM
295 This option specifies that the output generated by the assembler should
296 be marked as being encoded for a big-endian processor.
298 @cindex @code{-EL} command line option, ARM
300 This option specifies that the output generated by the assembler should
301 be marked as being encoded for a little-endian processor.
303 @cindex @code{-k} command line option, ARM
304 @cindex PIC code generation for ARM
306 This option specifies that the output of the assembler should be marked
307 as position-independent code (PIC).
309 @cindex @code{--fix-v4bx} command line option, ARM
311 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
312 the linker option of the same name.
314 @cindex @code{-mwarn-deprecated} command line option, ARM
315 @item -mwarn-deprecated
316 @itemx -mno-warn-deprecated
317 Enable or disable warnings about using deprecated options or
318 features. The default is to warn.
326 * ARM-Chars:: Special Characters
327 * ARM-Regs:: Register Names
328 * ARM-Relocations:: Relocations
332 @subsection Special Characters
334 @cindex line comment character, ARM
335 @cindex ARM line comment character
336 The presence of a @samp{@@} on a line indicates the start of a comment
337 that extends to the end of the current line. If a @samp{#} appears as
338 the first character of a line, the whole line is treated as a comment.
340 @cindex line separator, ARM
341 @cindex statement separator, ARM
342 @cindex ARM line separator
343 The @samp{;} character can be used instead of a newline to separate
346 @cindex immediate character, ARM
347 @cindex ARM immediate character
348 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
350 @cindex identifiers, ARM
351 @cindex ARM identifiers
352 *TODO* Explain about /data modifier on symbols.
355 @subsection Register Names
357 @cindex ARM register names
358 @cindex register names, ARM
359 *TODO* Explain about ARM register naming, and the predefined names.
361 @node ARM Floating Point
362 @section Floating Point
364 @cindex floating point, ARM (@sc{ieee})
365 @cindex ARM floating point (@sc{ieee})
366 The ARM family uses @sc{ieee} floating-point numbers.
368 @node ARM-Relocations
369 @subsection ARM relocation generation
371 @cindex data relocations, ARM
372 @cindex ARM data relocations
373 Specific data relocations can be generated by putting the relocation name
374 in parentheses after the symbol name. For example:
380 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
382 The following relocations are supported:
395 For compatibility with older toolchains the assembler also accepts
396 @code{(PLT)} after branch targets. This will generate the deprecated
397 @samp{R_ARM_PLT32} relocation.
399 @cindex MOVW and MOVT relocations, ARM
400 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
401 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
402 respectively. For example to load the 32-bit address of foo into r0:
405 MOVW r0, #:lower16:foo
406 MOVT r0, #:upper16:foo
410 @section ARM Machine Directives
412 @cindex machine directives, ARM
413 @cindex ARM machine directives
416 @c AAAAAAAAAAAAAAAAAAAAAAAAA
418 @cindex @code{.2byte} directive, ARM
419 @cindex @code{.4byte} directive, ARM
420 @cindex @code{.8byte} directive, ARM
421 @item .2byte @var{expression} [, @var{expression}]*
422 @itemx .4byte @var{expression} [, @var{expression}]*
423 @itemx .8byte @var{expression} [, @var{expression}]*
424 These directives write 2, 4 or 8 byte values to the output section.
426 @cindex @code{.align} directive, ARM
427 @item .align @var{expression} [, @var{expression}]
428 This is the generic @var{.align} directive. For the ARM however if the
429 first argument is zero (ie no alignment is needed) the assembler will
430 behave as if the argument had been 2 (ie pad to the next four byte
431 boundary). This is for compatibility with ARM's own assembler.
433 @cindex @code{.arch} directive, ARM
434 @item .arch @var{name}
435 Select the target architecture. Valid values for @var{name} are the same as
436 for the @option{-march} commandline option.
438 @cindex @code{.arm} directive, ARM
440 This performs the same action as @var{.code 32}.
443 @cindex @code{.pad} directive, ARM
444 @item .pad #@var{count}
445 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
446 A positive value indicates the function prologue allocated stack space by
447 decrementing the stack pointer.
449 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
451 @cindex @code{.bss} directive, ARM
453 This directive switches to the @code{.bss} section.
455 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
457 @cindex @code{.cantunwind} directive, ARM
459 Prevents unwinding through the current function. No personality routine
460 or exception table data is required or permitted.
462 @cindex @code{.code} directive, ARM
463 @item .code @code{[16|32]}
464 This directive selects the instruction set being generated. The value 16
465 selects Thumb, with the value 32 selecting ARM.
467 @cindex @code{.cpu} directive, ARM
468 @item .cpu @var{name}
469 Select the target processor. Valid values for @var{name} are the same as
470 for the @option{-mcpu} commandline option.
472 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
474 @cindex @code{.dn} and @code{.qn} directives, ARM
475 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
476 @item @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
478 The @code{dn} and @code{qn} directives are used to create typed
479 and/or indexed register aliases for use in Advanced SIMD Extension
480 (Neon) instructions. The former should be used to create aliases
481 of double-precision registers, and the latter to create aliases of
482 quad-precision registers.
484 If these directives are used to create typed aliases, those aliases can
485 be used in Neon instructions instead of writing types after the mnemonic
486 or after each operand. For example:
495 This is equivalent to writing the following:
501 Aliases created using @code{dn} or @code{qn} can be destroyed using
504 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
506 @cindex @code{.eabi_attribute} directive, ARM
507 @item .eabi_attribute @var{tag}, @var{value}
508 Set the EABI object attribute @var{tag} to @var{value}.
510 The @var{tag} is either an attribute number, or one of the following:
511 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
512 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
513 @code{Tag_THUMB_ISA_use}, @code{Tag_VFP_arch}, @code{Tag_WMMX_arch},
514 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
515 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
516 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
517 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
518 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
519 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
520 @code{Tag_ABI_align8_needed}, @code{Tag_ABI_align8_preserved},
521 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
522 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
523 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
524 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
525 @code{Tag_VFP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
526 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
527 @code{Tag_conformance}, @code{Tag_T2EE_use},
528 @code{Tag_Virtualization_use}, @code{Tag_MPextension_use}
530 The @var{value} is either a @code{number}, @code{"string"}, or
531 @code{number, "string"} depending on the tag.
533 @cindex @code{.even} directive, ARM
535 This directive aligns to an even-numbered address.
537 @cindex @code{.extend} directive, ARM
538 @cindex @code{.ldouble} directive, ARM
539 @item .extend @var{expression} [, @var{expression}]*
540 @itemx .ldouble @var{expression} [, @var{expression}]*
541 These directives write 12byte long double floating-point values to the
542 output section. These are not compatible with current ARM processors
545 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
548 @cindex @code{.fnend} directive, ARM
550 Marks the end of a function with an unwind table entry. The unwind index
551 table entry is created when this directive is processed.
553 If no personality routine has been specified then standard personality
554 routine 0 or 1 will be used, depending on the number of unwind opcodes
558 @cindex @code{.fnstart} directive, ARM
560 Marks the start of a function with an unwind table entry.
562 @cindex @code{.force_thumb} directive, ARM
564 This directive forces the selection of Thumb instructions, even if the
565 target processor does not support those instructions
567 @cindex @code{.fpu} directive, ARM
568 @item .fpu @var{name}
569 Select the floating-point unit to assemble for. Valid values for @var{name}
570 are the same as for the @option{-mfpu} commandline option.
572 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
573 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
575 @cindex @code{.handlerdata} directive, ARM
577 Marks the end of the current function, and the start of the exception table
578 entry for that function. Anything between this directive and the
579 @code{.fnend} directive will be added to the exception table entry.
581 Must be preceded by a @code{.personality} or @code{.personalityindex}
584 @c IIIIIIIIIIIIIIIIIIIIIIIIII
586 @cindex @code{.inst} directive, ARM
587 @item .inst @var{opcode} [ , @dots{} ]
588 @item .inst.n @var{opcode} [ , @dots{} ]
589 @item .inst.w @var{opcode} [ , @dots{} ]
590 Generates the instruction corresponding to the numerical value @var{opcode}.
591 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
592 specified explicitly, overriding the normal encoding rules.
594 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
595 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
596 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
598 @item .ldouble @var{expression} [, @var{expression}]*
601 @cindex @code{.ltorg} directive, ARM
603 This directive causes the current contents of the literal pool to be
604 dumped into the current section (which is assumed to be the .text
605 section) at the current location (aligned to a word boundary).
606 @code{GAS} maintains a separate literal pool for each section and each
607 sub-section. The @code{.ltorg} directive will only affect the literal
608 pool of the current section and sub-section. At the end of assembly
609 all remaining, un-empty literal pools will automatically be dumped.
611 Note - older versions of @code{GAS} would dump the current literal
612 pool any time a section change occurred. This is no longer done, since
613 it prevents accurate control of the placement of literal pools.
615 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
617 @cindex @code{.movsp} directive, ARM
618 @item .movsp @var{reg} [, #@var{offset}]
619 Tell the unwinder that @var{reg} contains an offset from the current
620 stack pointer. If @var{offset} is not specified then it is assumed to be
623 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
624 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
626 @cindex @code{.object_arch} directive, ARM
627 @item .object_arch @var{name}
628 Override the architecture recorded in the EABI object attribute section.
629 Valid values for @var{name} are the same as for the @code{.arch} directive.
630 Typically this is useful when code uses runtime detection of CPU features.
632 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
634 @cindex @code{.packed} directive, ARM
635 @item .packed @var{expression} [, @var{expression}]*
636 This directive writes 12-byte packed floating-point values to the
637 output section. These are not compatible with current ARM processors
640 @cindex @code{.pad} directive, ARM
641 @item .pad #@var{count}
642 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
643 A positive value indicates the function prologue allocated stack space by
644 decrementing the stack pointer.
646 @cindex @code{.personality} directive, ARM
647 @item .personality @var{name}
648 Sets the personality routine for the current function to @var{name}.
650 @cindex @code{.personalityindex} directive, ARM
651 @item .personalityindex @var{index}
652 Sets the personality routine for the current function to the EABI standard
653 routine number @var{index}
655 @cindex @code{.pool} directive, ARM
657 This is a synonym for .ltorg.
659 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
660 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
662 @cindex @code{.req} directive, ARM
663 @item @var{name} .req @var{register name}
664 This creates an alias for @var{register name} called @var{name}. For
671 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
674 @cindex @code{.save} directive, ARM
675 @item .save @var{reglist}
676 Generate unwinder annotations to restore the registers in @var{reglist}.
677 The format of @var{reglist} is the same as the corresponding store-multiple
681 @exdent @emph{core registers}
682 .save @{r4, r5, r6, lr@}
683 stmfd sp!, @{r4, r5, r6, lr@}
684 @exdent @emph{FPA registers}
687 @exdent @emph{VFP registers}
688 .save @{d8, d9, d10@}
689 fstmdx sp!, @{d8, d9, d10@}
690 @exdent @emph{iWMMXt registers}
692 wstrd wr11, [sp, #-8]!
693 wstrd wr10, [sp, #-8]!
696 wstrd wr11, [sp, #-8]!
698 wstrd wr10, [sp, #-8]!
702 @cindex @code{.setfp} directive, ARM
703 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
704 Make all unwinder annotations relative to a frame pointer. Without this
705 the unwinder will use offsets from the stack pointer.
707 The syntax of this directive is the same as the @code{sub} or @code{mov}
708 instruction used to set the frame pointer. @var{spreg} must be either
709 @code{sp} or mentioned in a previous @code{.movsp} directive.
719 @cindex @code{.secrel32} directive, ARM
720 @item .secrel32 @var{expression} [, @var{expression}]*
721 This directive emits relocations that evaluate to the section-relative
722 offset of each expression's symbol. This directive is only supported
725 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
727 @cindex @code{.thumb} directive, ARM
729 This performs the same action as @var{.code 16}.
731 @cindex @code{.thumb_func} directive, ARM
733 This directive specifies that the following symbol is the name of a
734 Thumb encoded function. This information is necessary in order to allow
735 the assembler and linker to generate correct code for interworking
736 between Arm and Thumb instructions and should be used even if
737 interworking is not going to be performed. The presence of this
738 directive also implies @code{.thumb}
740 This directive is not neccessary when generating EABI objects. On these
741 targets the encoding is implicit when generating Thumb code.
743 @cindex @code{.thumb_set} directive, ARM
745 This performs the equivalent of a @code{.set} directive in that it
746 creates a symbol which is an alias for another symbol (possibly not yet
747 defined). This directive also has the added property in that it marks
748 the aliased symbol as being a thumb function entry point, in the same
749 way that the @code{.thumb_func} directive does.
751 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
753 @cindex @code{.unreq} directive, ARM
754 @item .unreq @var{alias-name}
755 This undefines a register alias which was previously defined using the
756 @code{req}, @code{dn} or @code{qn} directives. For example:
763 An error occurs if the name is undefined. Note - this pseudo op can
764 be used to delete builtin in register name aliases (eg 'r0'). This
765 should only be done if it is really necessary.
767 @cindex @code{.unwind_raw} directive, ARM
768 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
769 Insert one of more arbitary unwind opcode bytes, which are known to adjust
770 the stack pointer by @var{offset} bytes.
772 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
775 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
777 @cindex @code{.vsave} directive, ARM
778 @item .vsave @var{vfp-reglist}
779 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
780 using FLDMD. Also works for VFPv3 registers
781 that are to be restored using VLDM.
782 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
786 @exdent @emph{VFP registers}
787 .vsave @{d8, d9, d10@}
788 fstmdd sp!, @{d8, d9, d10@}
789 @exdent @emph{VFPv3 registers}
790 .vsave @{d15, d16, d17@}
791 vstm sp!, @{d15, d16, d17@}
794 Since FLDMX and FSTMX are now deprecated, this directive should be
795 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
797 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
798 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
799 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
800 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
808 @cindex opcodes for ARM
809 @code{@value{AS}} implements all the standard ARM opcodes. It also
810 implements several pseudo opcodes, including several synthetic load
815 @cindex @code{NOP} pseudo op, ARM
821 This pseudo op will always evaluate to a legal ARM instruction that does
822 nothing. Currently it will evaluate to MOV r0, r0.
824 @cindex @code{LDR reg,=<label>} pseudo op, ARM
827 ldr <register> , = <expression>
830 If expression evaluates to a numeric constant then a MOV or MVN
831 instruction will be used in place of the LDR instruction, if the
832 constant can be generated by either of these instructions. Otherwise
833 the constant will be placed into the nearest literal pool (if it not
834 already there) and a PC relative LDR instruction will be generated.
836 @cindex @code{ADR reg,<label>} pseudo op, ARM
839 adr <register> <label>
842 This instruction will load the address of @var{label} into the indicated
843 register. The instruction will evaluate to a PC relative ADD or SUB
844 instruction depending upon where the label is located. If the label is
845 out of range, or if it is not defined in the same file (and section) as
846 the ADR instruction, then an error will be generated. This instruction
847 will not make use of the literal pool.
849 @cindex @code{ADRL reg,<label>} pseudo op, ARM
852 adrl <register> <label>
855 This instruction will load the address of @var{label} into the indicated
856 register. The instruction will evaluate to one or two PC relative ADD
857 or SUB instructions depending upon where the label is located. If a
858 second instruction is not needed a NOP instruction will be generated in
859 its place, so that this instruction is always 8 bytes long.
861 If the label is out of range, or if it is not defined in the same file
862 (and section) as the ADRL instruction, then an error will be generated.
863 This instruction will not make use of the literal pool.
867 For information on the ARM or Thumb instruction sets, see @cite{ARM
868 Software Development Toolkit Reference Manual}, Advanced RISC Machines
871 @node ARM Mapping Symbols
872 @section Mapping Symbols
874 The ARM ELF specification requires that special symbols be inserted
875 into object files to mark certain features:
881 At the start of a region of code containing ARM instructions.
885 At the start of a region of code containing THUMB instructions.
889 At the start of a region of data.
893 The assembler will automatically insert these symbols for you - there
894 is no need to code them yourself. Support for tagging symbols ($b,
895 $f, $p and $m) which is also mentioned in the current ARM ELF
896 specification is not implemented. This is because they have been
897 dropped from the new EABI and so tools cannot rely upon their
900 @node ARM Unwinding Tutorial
903 The ABI for the ARM Architecture specifies a standard format for
904 exception unwind information. This information is used when an
905 exception is thrown to determine where control should be transferred.
906 In particular, the unwind information is used to determine which
907 function called the function that threw the exception, and which
908 function called that one, and so forth. This information is also used
909 to restore the values of callee-saved registers in the function
910 catching the exception.
912 If you are writing functions in assembly code, and those functions
913 call other functions that throw exceptions, you must use assembly
914 pseudo ops to ensure that appropriate exception unwind information is
915 generated. Otherwise, if one of the functions called by your assembly
916 code throws an exception, the run-time library will be unable to
917 unwind the stack through your assembly code and your program will not
920 To illustrate the use of these pseudo ops, we will examine the code
921 that G++ generates for the following C++ input:
935 This example does not show how to throw or catch an exception from
936 assembly code. That is a much more complex operation and should
937 always be done in a high-level language, such as C++, that directly
940 The code generated by one particular version of G++ when compiling the
947 @ Function supports interworking.
948 @ args = 0, pretend = 0, frame = 8
949 @ frame_needed = 1, uses_anonymous_args = 0
971 Of course, the sequence of instructions varies based on the options
972 you pass to GCC and on the version of GCC in use. The exact
973 instructions are not important since we are focusing on the pseudo ops
974 that are used to generate unwind information.
976 An important assumption made by the unwinder is that the stack frame
977 does not change during the body of the function. In particular, since
978 we assume that the assembly code does not itself throw an exception,
979 the only point where an exception can be thrown is from a call, such
980 as the @code{bl} instruction above. At each call site, the same saved
981 registers (including @code{lr}, which indicates the return address)
982 must be located in the same locations relative to the frame pointer.
984 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
985 op appears immediately before the first instruction of the function
986 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
987 op appears immediately after the last instruction of the function.
988 These pseudo ops specify the range of the function.
990 Only the order of the other pseudos ops (e.g., @code{.setfp} or
991 @code{.pad}) matters; their exact locations are irrelevant. In the
992 example above, the compiler emits the pseudo ops with particular
993 instructions. That makes it easier to understand the code, but it is
994 not required for correctness. It would work just as well to emit all
995 of the pseudo ops other than @code{.fnend} in the same order, but
996 immediately after @code{.fnstart}.
998 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
999 indicates registers that have been saved to the stack so that they can
1000 be restored before the function returns. The argument to the
1001 @code{.save} pseudo op is a list of registers to save. If a register
1002 is ``callee-saved'' (as specified by the ABI) and is modified by the
1003 function you are writing, then your code must save the value before it
1004 is modified and restore the original value before the function
1005 returns. If an exception is thrown, the run-time library restores the
1006 values of these registers from their locations on the stack before
1007 returning control to the exception handler. (Of course, if an
1008 exception is not thrown, the function that contains the @code{.save}
1009 pseudo op restores these registers in the function epilogue, as is
1010 done with the @code{ldmfd} instruction above.)
1012 You do not have to save callee-saved registers at the very beginning
1013 of the function and you do not need to use the @code{.save} pseudo op
1014 immediately following the point at which the registers are saved.
1015 However, if you modify a callee-saved register, you must save it on
1016 the stack before modifying it and before calling any functions which
1017 might throw an exception. And, you must use the @code{.save} pseudo
1018 op to indicate that you have done so.
1020 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1021 modification of the stack pointer that does not save any registers.
1022 The argument is the number of bytes (in decimal) that are subtracted
1023 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1024 subtracting from the stack pointer increases the size of the stack.)
1026 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1027 indicates the register that contains the frame pointer. The first
1028 argument is the register that is set, which is typically @code{fp}.
1029 The second argument indicates the register from which the frame
1030 pointer takes its value. The third argument, if present, is the value
1031 (in decimal) added to the register specified by the second argument to
1032 compute the value of the frame pointer. You should not modify the
1033 frame pointer in the body of the function.
1035 If you do not use a frame pointer, then you should not use the
1036 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1037 should avoid modifying the stack pointer outside of the function
1038 prologue. Otherwise, the run-time library will be unable to find
1039 saved registers when it is unwinding the stack.
1041 The pseudo ops described above are sufficient for writing assembly
1042 code that calls functions which may throw exceptions. If you need to
1043 know more about the object-file format used to represent unwind
1044 information, you may consult the @cite{Exception Handling ABI for the
1045 ARM Architecture} available from @uref{http://infocenter.arm.com}.