1 @c Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
2 @c 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
3 @c This is part of the GAS manual.
4 @c For copying conditions, see the file as.texinfo.
9 @chapter ARM Dependent Features
13 @node Machine Dependencies
14 @chapter ARM Dependent Features
20 * ARM Options:: Options
22 * ARM Floating Point:: Floating Point
23 * ARM Directives:: ARM Machine Directives
24 * ARM Opcodes:: Opcodes
25 * ARM Mapping Symbols:: Mapping Symbols
26 * ARM Unwinding Tutorial:: Unwinding
31 @cindex ARM options (none)
32 @cindex options for ARM (none)
36 @cindex @code{-mcpu=} command line option, ARM
37 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
38 This option specifies the target processor. The assembler will issue an
39 error message if an attempt is made to assemble an instruction which
40 will not execute on the target processor. The following processor names are
85 @code{fa526} (Faraday FA526 processor),
86 @code{fa626} (Faraday FA626 processor),
105 @code{fa626te} (Faraday FA626TE processor),
106 @code{fa726te} (Faraday FA726TE processor),
123 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
124 @code{i80200} (Intel XScale processor)
125 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
128 The special name @code{all} may be used to allow the
129 assembler to accept instructions valid for any ARM processor.
131 In addition to the basic instruction set, the assembler can be told to
132 accept various extension mnemonics that extend the processor using the
133 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
134 is equivalent to specifying @code{-mcpu=ep9312}. The following extensions
135 are currently supported:
141 @cindex @code{-march=} command line option, ARM
142 @item -march=@var{architecture}[+@var{extension}@dots{}]
143 This option specifies the target architecture. The assembler will issue
144 an error message if an attempt is made to assemble an instruction which
145 will not execute on the target architecture. The following architecture
146 names are recognized:
175 If both @code{-mcpu} and
176 @code{-march} are specified, the assembler will use
177 the setting for @code{-mcpu}.
179 The architecture option can be extended with the same instruction set
180 extension options as the @code{-mcpu} option.
182 @cindex @code{-mfpu=} command line option, ARM
183 @item -mfpu=@var{floating-point-format}
185 This option specifies the floating point format to assemble for. The
186 assembler will issue an error message if an attempt is made to assemble
187 an instruction which will not execute on the target floating point unit.
188 The following format options are recognized:
208 @code{vfpv3-d16-fp16},
222 In addition to determining which instructions are assembled, this option
223 also affects the way in which the @code{.double} assembler directive behaves
224 when assembling little-endian code.
226 The default is dependent on the processor selected. For Architecture 5 or
227 later, the default is to assembler for VFP instructions; for earlier
228 architectures the default is to assemble for FPA instructions.
230 @cindex @code{-mthumb} command line option, ARM
232 This option specifies that the assembler should start assembling Thumb
233 instructions; that is, it should behave as though the file starts with a
234 @code{.code 16} directive.
236 @cindex @code{-mthumb-interwork} command line option, ARM
237 @item -mthumb-interwork
238 This option specifies that the output generated by the assembler should
239 be marked as supporting interworking.
241 @cindex @code{-mimplicit-it} command line option, ARM
242 @item -mimplicit-it=never
243 @itemx -mimplicit-it=always
244 @itemx -mimplicit-it=arm
245 @itemx -mimplicit-it=thumb
246 The @code{-mimplicit-it} option controls the behavior of the assembler when
247 conditional instructions are not enclosed in IT blocks.
248 There are four possible behaviors.
249 If @code{never} is specified, such constructs cause a warning in ARM
250 code and an error in Thumb-2 code.
251 If @code{always} is specified, such constructs are accepted in both
252 ARM and Thumb-2 code, where the IT instruction is added implicitly.
253 If @code{arm} is specified, such constructs are accepted in ARM code
254 and cause an error in Thumb-2 code.
255 If @code{thumb} is specified, such constructs cause a warning in ARM
256 code and are accepted in Thumb-2 code. If you omit this option, the
257 behavior is equivalent to @code{-mimplicit-it=arm}.
259 @cindex @code{-mapcs-26} command line option, ARM
260 @cindex @code{-mapcs-32} command line option, ARM
263 These options specify that the output generated by the assembler should
264 be marked as supporting the indicated version of the Arm Procedure.
267 @cindex @code{-matpcs} command line option, ARM
269 This option specifies that the output generated by the assembler should
270 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
271 enabled this option will cause the assembler to create an empty
272 debugging section in the object file called .arm.atpcs. Debuggers can
273 use this to determine the ABI being used by.
275 @cindex @code{-mapcs-float} command line option, ARM
277 This indicates the floating point variant of the APCS should be
278 used. In this variant floating point arguments are passed in FP
279 registers rather than integer registers.
281 @cindex @code{-mapcs-reentrant} command line option, ARM
282 @item -mapcs-reentrant
283 This indicates that the reentrant variant of the APCS should be used.
284 This variant supports position independent code.
286 @cindex @code{-mfloat-abi=} command line option, ARM
287 @item -mfloat-abi=@var{abi}
288 This option specifies that the output generated by the assembler should be
289 marked as using specified floating point ABI.
290 The following values are recognized:
296 @cindex @code{-eabi=} command line option, ARM
297 @item -meabi=@var{ver}
298 This option specifies which EABI version the produced object files should
300 The following values are recognized:
306 @cindex @code{-EB} command line option, ARM
308 This option specifies that the output generated by the assembler should
309 be marked as being encoded for a big-endian processor.
311 @cindex @code{-EL} command line option, ARM
313 This option specifies that the output generated by the assembler should
314 be marked as being encoded for a little-endian processor.
316 @cindex @code{-k} command line option, ARM
317 @cindex PIC code generation for ARM
319 This option specifies that the output of the assembler should be marked
320 as position-independent code (PIC).
322 @cindex @code{--fix-v4bx} command line option, ARM
324 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
325 the linker option of the same name.
327 @cindex @code{-mwarn-deprecated} command line option, ARM
328 @item -mwarn-deprecated
329 @itemx -mno-warn-deprecated
330 Enable or disable warnings about using deprecated options or
331 features. The default is to warn.
339 * ARM-Instruction-Set:: Instruction Set
340 * ARM-Chars:: Special Characters
341 * ARM-Regs:: Register Names
342 * ARM-Relocations:: Relocations
343 * ARM-Neon-Alignment:: NEON Alignment Specifiers
346 @node ARM-Instruction-Set
347 @subsection Instruction Set Syntax
348 Two slightly different syntaxes are support for ARM and THUMB
349 instructions. The default, @code{divided}, uses the old style where
350 ARM and THUMB instructions had their own, separate syntaxes. The new,
351 @code{unified} syntax, which can be selected via the @code{.syntax}
352 directive, and has the following main features:
356 Immediate operands do not require a @code{#} prefix.
359 The @code{IT} instruction may appear, and if it does it is validated
360 against subsequent conditional affixes. In ARM mode it does not
361 generate machine code, in THUMB mode it does.
364 For ARM instructions the conditional affixes always appear at the end
365 of the instruction. For THUMB instructions conditional affixes can be
366 used, but only inside the scope of an @code{IT} instruction.
369 All of the instructions new to the V6T2 architecture (and later) are
370 available. (Only a few such instructions can be written in the
371 @code{divided} syntax).
374 The @code{.N} and @code{.W} suffixes are recognized and honored.
377 All instructions set the flags if and only if they have an @code{s}
382 @subsection Special Characters
384 @cindex line comment character, ARM
385 @cindex ARM line comment character
386 The presence of a @samp{@@} on a line indicates the start of a comment
387 that extends to the end of the current line. If a @samp{#} appears as
388 the first character of a line, the whole line is treated as a comment.
390 @cindex line separator, ARM
391 @cindex statement separator, ARM
392 @cindex ARM line separator
393 The @samp{;} character can be used instead of a newline to separate
396 @cindex immediate character, ARM
397 @cindex ARM immediate character
398 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
400 @cindex identifiers, ARM
401 @cindex ARM identifiers
402 *TODO* Explain about /data modifier on symbols.
405 @subsection Register Names
407 @cindex ARM register names
408 @cindex register names, ARM
409 *TODO* Explain about ARM register naming, and the predefined names.
411 @node ARM-Neon-Alignment
412 @subsection NEON Alignment Specifiers
414 @cindex alignment for NEON instructions
415 Some NEON load/store instructions allow an optional address
417 The ARM documentation specifies that this is indicated by
418 @samp{@@ @var{align}}. However GAS already interprets
419 the @samp{@@} character as a "line comment" start,
420 so @samp{: @var{align}} is used instead. For example:
423 vld1.8 @{q0@}, [r0, :128]
426 @node ARM Floating Point
427 @section Floating Point
429 @cindex floating point, ARM (@sc{ieee})
430 @cindex ARM floating point (@sc{ieee})
431 The ARM family uses @sc{ieee} floating-point numbers.
433 @node ARM-Relocations
434 @subsection ARM relocation generation
436 @cindex data relocations, ARM
437 @cindex ARM data relocations
438 Specific data relocations can be generated by putting the relocation name
439 in parentheses after the symbol name. For example:
445 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
447 The following relocations are supported:
461 For compatibility with older toolchains the assembler also accepts
462 @code{(PLT)} after branch targets. This will generate the deprecated
463 @samp{R_ARM_PLT32} relocation.
465 @cindex MOVW and MOVT relocations, ARM
466 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
467 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
468 respectively. For example to load the 32-bit address of foo into r0:
471 MOVW r0, #:lower16:foo
472 MOVT r0, #:upper16:foo
476 @section ARM Machine Directives
478 @cindex machine directives, ARM
479 @cindex ARM machine directives
482 @c AAAAAAAAAAAAAAAAAAAAAAAAA
484 @cindex @code{.2byte} directive, ARM
485 @cindex @code{.4byte} directive, ARM
486 @cindex @code{.8byte} directive, ARM
487 @item .2byte @var{expression} [, @var{expression}]*
488 @itemx .4byte @var{expression} [, @var{expression}]*
489 @itemx .8byte @var{expression} [, @var{expression}]*
490 These directives write 2, 4 or 8 byte values to the output section.
492 @cindex @code{.align} directive, ARM
493 @item .align @var{expression} [, @var{expression}]
494 This is the generic @var{.align} directive. For the ARM however if the
495 first argument is zero (ie no alignment is needed) the assembler will
496 behave as if the argument had been 2 (ie pad to the next four byte
497 boundary). This is for compatibility with ARM's own assembler.
499 @cindex @code{.arch} directive, ARM
500 @item .arch @var{name}
501 Select the target architecture. Valid values for @var{name} are the same as
502 for the @option{-march} commandline option.
504 @cindex @code{.arm} directive, ARM
506 This performs the same action as @var{.code 32}.
509 @cindex @code{.pad} directive, ARM
510 @item .pad #@var{count}
511 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
512 A positive value indicates the function prologue allocated stack space by
513 decrementing the stack pointer.
515 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
517 @cindex @code{.bss} directive, ARM
519 This directive switches to the @code{.bss} section.
521 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
523 @cindex @code{.cantunwind} directive, ARM
525 Prevents unwinding through the current function. No personality routine
526 or exception table data is required or permitted.
528 @cindex @code{.code} directive, ARM
529 @item .code @code{[16|32]}
530 This directive selects the instruction set being generated. The value 16
531 selects Thumb, with the value 32 selecting ARM.
533 @cindex @code{.cpu} directive, ARM
534 @item .cpu @var{name}
535 Select the target processor. Valid values for @var{name} are the same as
536 for the @option{-mcpu} commandline option.
538 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
540 @cindex @code{.dn} and @code{.qn} directives, ARM
541 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
542 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
544 The @code{dn} and @code{qn} directives are used to create typed
545 and/or indexed register aliases for use in Advanced SIMD Extension
546 (Neon) instructions. The former should be used to create aliases
547 of double-precision registers, and the latter to create aliases of
548 quad-precision registers.
550 If these directives are used to create typed aliases, those aliases can
551 be used in Neon instructions instead of writing types after the mnemonic
552 or after each operand. For example:
561 This is equivalent to writing the following:
567 Aliases created using @code{dn} or @code{qn} can be destroyed using
570 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
572 @cindex @code{.eabi_attribute} directive, ARM
573 @item .eabi_attribute @var{tag}, @var{value}
574 Set the EABI object attribute @var{tag} to @var{value}.
576 The @var{tag} is either an attribute number, or one of the following:
577 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
578 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
579 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
580 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
581 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
582 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
583 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
584 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
585 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
586 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
587 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
588 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
589 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
590 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
591 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
592 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
593 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
594 @code{Tag_conformance}, @code{Tag_T2EE_use},
595 @code{Tag_Virtualization_use}
597 The @var{value} is either a @code{number}, @code{"string"}, or
598 @code{number, "string"} depending on the tag.
600 Note - the following legacy values are also accepted by @var{tag}:
601 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
602 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
604 @cindex @code{.even} directive, ARM
606 This directive aligns to an even-numbered address.
608 @cindex @code{.extend} directive, ARM
609 @cindex @code{.ldouble} directive, ARM
610 @item .extend @var{expression} [, @var{expression}]*
611 @itemx .ldouble @var{expression} [, @var{expression}]*
612 These directives write 12byte long double floating-point values to the
613 output section. These are not compatible with current ARM processors
616 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
619 @cindex @code{.fnend} directive, ARM
621 Marks the end of a function with an unwind table entry. The unwind index
622 table entry is created when this directive is processed.
624 If no personality routine has been specified then standard personality
625 routine 0 or 1 will be used, depending on the number of unwind opcodes
629 @cindex @code{.fnstart} directive, ARM
631 Marks the start of a function with an unwind table entry.
633 @cindex @code{.force_thumb} directive, ARM
635 This directive forces the selection of Thumb instructions, even if the
636 target processor does not support those instructions
638 @cindex @code{.fpu} directive, ARM
639 @item .fpu @var{name}
640 Select the floating-point unit to assemble for. Valid values for @var{name}
641 are the same as for the @option{-mfpu} commandline option.
643 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
644 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
646 @cindex @code{.handlerdata} directive, ARM
648 Marks the end of the current function, and the start of the exception table
649 entry for that function. Anything between this directive and the
650 @code{.fnend} directive will be added to the exception table entry.
652 Must be preceded by a @code{.personality} or @code{.personalityindex}
655 @c IIIIIIIIIIIIIIIIIIIIIIIIII
657 @cindex @code{.inst} directive, ARM
658 @item .inst @var{opcode} [ , @dots{} ]
659 @itemx .inst.n @var{opcode} [ , @dots{} ]
660 @itemx .inst.w @var{opcode} [ , @dots{} ]
661 Generates the instruction corresponding to the numerical value @var{opcode}.
662 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
663 specified explicitly, overriding the normal encoding rules.
665 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
666 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
667 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
669 @item .ldouble @var{expression} [, @var{expression}]*
672 @cindex @code{.ltorg} directive, ARM
674 This directive causes the current contents of the literal pool to be
675 dumped into the current section (which is assumed to be the .text
676 section) at the current location (aligned to a word boundary).
677 @code{GAS} maintains a separate literal pool for each section and each
678 sub-section. The @code{.ltorg} directive will only affect the literal
679 pool of the current section and sub-section. At the end of assembly
680 all remaining, un-empty literal pools will automatically be dumped.
682 Note - older versions of @code{GAS} would dump the current literal
683 pool any time a section change occurred. This is no longer done, since
684 it prevents accurate control of the placement of literal pools.
686 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
688 @cindex @code{.movsp} directive, ARM
689 @item .movsp @var{reg} [, #@var{offset}]
690 Tell the unwinder that @var{reg} contains an offset from the current
691 stack pointer. If @var{offset} is not specified then it is assumed to be
694 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
695 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
697 @cindex @code{.object_arch} directive, ARM
698 @item .object_arch @var{name}
699 Override the architecture recorded in the EABI object attribute section.
700 Valid values for @var{name} are the same as for the @code{.arch} directive.
701 Typically this is useful when code uses runtime detection of CPU features.
703 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
705 @cindex @code{.packed} directive, ARM
706 @item .packed @var{expression} [, @var{expression}]*
707 This directive writes 12-byte packed floating-point values to the
708 output section. These are not compatible with current ARM processors
711 @cindex @code{.pad} directive, ARM
712 @item .pad #@var{count}
713 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
714 A positive value indicates the function prologue allocated stack space by
715 decrementing the stack pointer.
717 @cindex @code{.personality} directive, ARM
718 @item .personality @var{name}
719 Sets the personality routine for the current function to @var{name}.
721 @cindex @code{.personalityindex} directive, ARM
722 @item .personalityindex @var{index}
723 Sets the personality routine for the current function to the EABI standard
724 routine number @var{index}
726 @cindex @code{.pool} directive, ARM
728 This is a synonym for .ltorg.
730 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
731 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
733 @cindex @code{.req} directive, ARM
734 @item @var{name} .req @var{register name}
735 This creates an alias for @var{register name} called @var{name}. For
742 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
745 @cindex @code{.save} directive, ARM
746 @item .save @var{reglist}
747 Generate unwinder annotations to restore the registers in @var{reglist}.
748 The format of @var{reglist} is the same as the corresponding store-multiple
752 @exdent @emph{core registers}
753 .save @{r4, r5, r6, lr@}
754 stmfd sp!, @{r4, r5, r6, lr@}
755 @exdent @emph{FPA registers}
758 @exdent @emph{VFP registers}
759 .save @{d8, d9, d10@}
760 fstmdx sp!, @{d8, d9, d10@}
761 @exdent @emph{iWMMXt registers}
763 wstrd wr11, [sp, #-8]!
764 wstrd wr10, [sp, #-8]!
767 wstrd wr11, [sp, #-8]!
769 wstrd wr10, [sp, #-8]!
773 @cindex @code{.setfp} directive, ARM
774 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
775 Make all unwinder annotations relative to a frame pointer. Without this
776 the unwinder will use offsets from the stack pointer.
778 The syntax of this directive is the same as the @code{add} or @code{mov}
779 instruction used to set the frame pointer. @var{spreg} must be either
780 @code{sp} or mentioned in a previous @code{.movsp} directive.
790 @cindex @code{.secrel32} directive, ARM
791 @item .secrel32 @var{expression} [, @var{expression}]*
792 This directive emits relocations that evaluate to the section-relative
793 offset of each expression's symbol. This directive is only supported
796 @cindex @code{.syntax} directive, ARM
797 @item .syntax [@code{unified} | @code{divided}]
798 This directive sets the Instruction Set Syntax as described in the
799 @ref{ARM-Instruction-Set} section.
801 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
803 @cindex @code{.thumb} directive, ARM
805 This performs the same action as @var{.code 16}.
807 @cindex @code{.thumb_func} directive, ARM
809 This directive specifies that the following symbol is the name of a
810 Thumb encoded function. This information is necessary in order to allow
811 the assembler and linker to generate correct code for interworking
812 between Arm and Thumb instructions and should be used even if
813 interworking is not going to be performed. The presence of this
814 directive also implies @code{.thumb}
816 This directive is not neccessary when generating EABI objects. On these
817 targets the encoding is implicit when generating Thumb code.
819 @cindex @code{.thumb_set} directive, ARM
821 This performs the equivalent of a @code{.set} directive in that it
822 creates a symbol which is an alias for another symbol (possibly not yet
823 defined). This directive also has the added property in that it marks
824 the aliased symbol as being a thumb function entry point, in the same
825 way that the @code{.thumb_func} directive does.
827 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
829 @cindex @code{.unreq} directive, ARM
830 @item .unreq @var{alias-name}
831 This undefines a register alias which was previously defined using the
832 @code{req}, @code{dn} or @code{qn} directives. For example:
839 An error occurs if the name is undefined. Note - this pseudo op can
840 be used to delete builtin in register name aliases (eg 'r0'). This
841 should only be done if it is really necessary.
843 @cindex @code{.unwind_raw} directive, ARM
844 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
845 Insert one of more arbitary unwind opcode bytes, which are known to adjust
846 the stack pointer by @var{offset} bytes.
848 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
851 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
853 @cindex @code{.vsave} directive, ARM
854 @item .vsave @var{vfp-reglist}
855 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
856 using FLDMD. Also works for VFPv3 registers
857 that are to be restored using VLDM.
858 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
862 @exdent @emph{VFP registers}
863 .vsave @{d8, d9, d10@}
864 fstmdd sp!, @{d8, d9, d10@}
865 @exdent @emph{VFPv3 registers}
866 .vsave @{d15, d16, d17@}
867 vstm sp!, @{d15, d16, d17@}
870 Since FLDMX and FSTMX are now deprecated, this directive should be
871 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
873 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
874 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
875 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
876 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
884 @cindex opcodes for ARM
885 @code{@value{AS}} implements all the standard ARM opcodes. It also
886 implements several pseudo opcodes, including several synthetic load
891 @cindex @code{NOP} pseudo op, ARM
897 This pseudo op will always evaluate to a legal ARM instruction that does
898 nothing. Currently it will evaluate to MOV r0, r0.
900 @cindex @code{LDR reg,=<label>} pseudo op, ARM
903 ldr <register> , = <expression>
906 If expression evaluates to a numeric constant then a MOV or MVN
907 instruction will be used in place of the LDR instruction, if the
908 constant can be generated by either of these instructions. Otherwise
909 the constant will be placed into the nearest literal pool (if it not
910 already there) and a PC relative LDR instruction will be generated.
912 @cindex @code{ADR reg,<label>} pseudo op, ARM
915 adr <register> <label>
918 This instruction will load the address of @var{label} into the indicated
919 register. The instruction will evaluate to a PC relative ADD or SUB
920 instruction depending upon where the label is located. If the label is
921 out of range, or if it is not defined in the same file (and section) as
922 the ADR instruction, then an error will be generated. This instruction
923 will not make use of the literal pool.
925 @cindex @code{ADRL reg,<label>} pseudo op, ARM
928 adrl <register> <label>
931 This instruction will load the address of @var{label} into the indicated
932 register. The instruction will evaluate to one or two PC relative ADD
933 or SUB instructions depending upon where the label is located. If a
934 second instruction is not needed a NOP instruction will be generated in
935 its place, so that this instruction is always 8 bytes long.
937 If the label is out of range, or if it is not defined in the same file
938 (and section) as the ADRL instruction, then an error will be generated.
939 This instruction will not make use of the literal pool.
943 For information on the ARM or Thumb instruction sets, see @cite{ARM
944 Software Development Toolkit Reference Manual}, Advanced RISC Machines
947 @node ARM Mapping Symbols
948 @section Mapping Symbols
950 The ARM ELF specification requires that special symbols be inserted
951 into object files to mark certain features:
957 At the start of a region of code containing ARM instructions.
961 At the start of a region of code containing THUMB instructions.
965 At the start of a region of data.
969 The assembler will automatically insert these symbols for you - there
970 is no need to code them yourself. Support for tagging symbols ($b,
971 $f, $p and $m) which is also mentioned in the current ARM ELF
972 specification is not implemented. This is because they have been
973 dropped from the new EABI and so tools cannot rely upon their
976 @node ARM Unwinding Tutorial
979 The ABI for the ARM Architecture specifies a standard format for
980 exception unwind information. This information is used when an
981 exception is thrown to determine where control should be transferred.
982 In particular, the unwind information is used to determine which
983 function called the function that threw the exception, and which
984 function called that one, and so forth. This information is also used
985 to restore the values of callee-saved registers in the function
986 catching the exception.
988 If you are writing functions in assembly code, and those functions
989 call other functions that throw exceptions, you must use assembly
990 pseudo ops to ensure that appropriate exception unwind information is
991 generated. Otherwise, if one of the functions called by your assembly
992 code throws an exception, the run-time library will be unable to
993 unwind the stack through your assembly code and your program will not
996 To illustrate the use of these pseudo ops, we will examine the code
997 that G++ generates for the following C++ input:
1000 void callee (int *);
1011 This example does not show how to throw or catch an exception from
1012 assembly code. That is a much more complex operation and should
1013 always be done in a high-level language, such as C++, that directly
1014 supports exceptions.
1016 The code generated by one particular version of G++ when compiling the
1023 @ Function supports interworking.
1024 @ args = 0, pretend = 0, frame = 8
1025 @ frame_needed = 1, uses_anonymous_args = 0
1047 Of course, the sequence of instructions varies based on the options
1048 you pass to GCC and on the version of GCC in use. The exact
1049 instructions are not important since we are focusing on the pseudo ops
1050 that are used to generate unwind information.
1052 An important assumption made by the unwinder is that the stack frame
1053 does not change during the body of the function. In particular, since
1054 we assume that the assembly code does not itself throw an exception,
1055 the only point where an exception can be thrown is from a call, such
1056 as the @code{bl} instruction above. At each call site, the same saved
1057 registers (including @code{lr}, which indicates the return address)
1058 must be located in the same locations relative to the frame pointer.
1060 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1061 op appears immediately before the first instruction of the function
1062 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1063 op appears immediately after the last instruction of the function.
1064 These pseudo ops specify the range of the function.
1066 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1067 @code{.pad}) matters; their exact locations are irrelevant. In the
1068 example above, the compiler emits the pseudo ops with particular
1069 instructions. That makes it easier to understand the code, but it is
1070 not required for correctness. It would work just as well to emit all
1071 of the pseudo ops other than @code{.fnend} in the same order, but
1072 immediately after @code{.fnstart}.
1074 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1075 indicates registers that have been saved to the stack so that they can
1076 be restored before the function returns. The argument to the
1077 @code{.save} pseudo op is a list of registers to save. If a register
1078 is ``callee-saved'' (as specified by the ABI) and is modified by the
1079 function you are writing, then your code must save the value before it
1080 is modified and restore the original value before the function
1081 returns. If an exception is thrown, the run-time library restores the
1082 values of these registers from their locations on the stack before
1083 returning control to the exception handler. (Of course, if an
1084 exception is not thrown, the function that contains the @code{.save}
1085 pseudo op restores these registers in the function epilogue, as is
1086 done with the @code{ldmfd} instruction above.)
1088 You do not have to save callee-saved registers at the very beginning
1089 of the function and you do not need to use the @code{.save} pseudo op
1090 immediately following the point at which the registers are saved.
1091 However, if you modify a callee-saved register, you must save it on
1092 the stack before modifying it and before calling any functions which
1093 might throw an exception. And, you must use the @code{.save} pseudo
1094 op to indicate that you have done so.
1096 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1097 modification of the stack pointer that does not save any registers.
1098 The argument is the number of bytes (in decimal) that are subtracted
1099 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1100 subtracting from the stack pointer increases the size of the stack.)
1102 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1103 indicates the register that contains the frame pointer. The first
1104 argument is the register that is set, which is typically @code{fp}.
1105 The second argument indicates the register from which the frame
1106 pointer takes its value. The third argument, if present, is the value
1107 (in decimal) added to the register specified by the second argument to
1108 compute the value of the frame pointer. You should not modify the
1109 frame pointer in the body of the function.
1111 If you do not use a frame pointer, then you should not use the
1112 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1113 should avoid modifying the stack pointer outside of the function
1114 prologue. Otherwise, the run-time library will be unable to find
1115 saved registers when it is unwinding the stack.
1117 The pseudo ops described above are sufficient for writing assembly
1118 code that calls functions which may throw exceptions. If you need to
1119 know more about the object-file format used to represent unwind
1120 information, you may consult the @cite{Exception Handling ABI for the
1121 ARM Architecture} available from @uref{http://infocenter.arm.com}.