gas/doc/c-arm.texi

   1 @c Copyright (C) 1996, 1998, 1999 Free Software Foundation, Inc.
   2 @c This is part of the GAS manual.
   3 @c For copying conditions, see the file as.texinfo.
   4
   5 @ifset GENERIC
   6 @page
   7 @node ARM-Dependent
   8 @chapter ARM Dependent Features
   9 @end ifset
  10
  11 @ifclear GENERIC
  12 @node Machine Dependencies
  13 @chapter ARM Dependent Features
  14 @end ifclear
  15
  16 @cindex ARM support
  17 @cindex Thumb support
  18 @menu
  19 * ARM Options::              Options
  20 * ARM Syntax::               Syntax
  21 * ARM Floating Point::       Floating Point
  22 * ARM Directives::           ARM Machine Directives
  23 * ARM Opcodes::              Opcodes
  24 @end menu
  25
  26 @node ARM Options
  27 @section Options
  28 @cindex ARM options (none)
  29 @cindex options for ARM (none)
  30 @table @code
  31 @cindex @code{-marm} command line option, ARM
  32 @item -marm [@var{2}|@var{250}|@var{3}|@var{6}|@var{60}|@var{600}|@var{610}|@var{620}|@var{7}|@var{7m}|@var{7d}|@var{7dm}|@var{7di}|@var{7dmi}|@var{70}|@var{700}|@var{700i}|@var{710}|@var{710c}|@var{7100}|@var{7500}|@var{7500fe}|@var{7tdmi}|@var{8}|@var{810}|@var{9}|@var{9tdmi}|@var{920}|@var{strongarm}|@var{strongarm110}|@var{strongarm1100}]
  33 This option specifies the target processor.  The assembler will issue an
  34 error message if an attempt is made to assemble an instruction which
  35 will not execute on the target processor.
  36 @cindex @code{-marmv} command line option, ARM
  37 @item -marmv [@var{2}|@var{2a}|@var{3}|@var{3m}|@var{4}|@var{4t}|@var{5}|@var{5t}]
  38 This option specifies the target architecture.  The assembler will issue
  39 an error message if an attempt is made to assemble an instruction which
  40 will not execute on the target architecture.
  41 @cindex @code{-mthumb} command line option, ARM
  42 @item -mthumb
  43 This option specifies that only Thumb instructions should be assembled.
  44 @cindex @code{-mall} command line option, ARM
  45 @item -mall
  46 This option specifies that any Arm or Thumb instruction should be assembled.
  47 @cindex @code{-mfpa} command line option, ARM
  48 @item -mfpa [@var{10}|@var{11}]
  49 This option specifies the floating point architecture in use on the
  50 target processor.
  51 @cindex @code{-mfpe-old} command line option, ARM
  52 @item -mfpe-old
  53 Do not allow the assemble of floating point multiple instructions.
  54 @cindex @code{-mno-fpu} command line option, ARM
  55 @item -mno-fpu
  56 Do not allow the assembly of any floating point instructions.
  57 @cindex @code{-mthumb-interwork} command line option, ARM
  58 @item -mthumb-interwork
  59 This option specifies that the output generated by the assembler should
  60 be marked as supporting interworking.
  61 @cindex @code{-mapcs} command line option, ARM
  62 @item -mapcs [@var{26}|@var{32}]
  63 This option specifies that the output generated by the assembler should
  64 be marked as supporting the indicated version of the Arm Procedure.
  65 Calling Standard.
  66 @item -mapcs-float
  67 This indicates the the floating point variant of the APCS should be
  68 used.  In this variant floating point arguments are passed in FP
  69 registers rather than integer registers.
  70 @item -mapcs-reentrant
  71 This indicates that the reentrant variant of the APCS should be used.
  72 This variant supports position independent code.
  73 @cindex @code{-EB} command line option, ARM
  74 @item -EB
  75 This option specifies that the output generated by the assembler should
  76 be marked as being encoded for a big-endian processor.
  77 @cindex @code{-EL} command line option, ARM
  78 @item -EL
  79 This option specifies that the output generated by the assembler should
  80 be marked as being encoded for a little-endian processor.
  81 @cindex @code{-k} command line option, ARM
  82 @cindex PIC code generation for ARM
  83 @item -k
  84 This option enables the generation of PIC (position independent code).
  85 @item -moabi
  86 This indicates that the code should be assembled using the old ARM ELF
  87 conventions, based on a beta release release of the ARM-ELF
  88 specifications, rather than the default conventions which are based on
  89 the final release of the ARM-ELF specifications.
  90 @end table
  91
  92
  93 @node ARM Syntax
  94 @section Syntax
  95 @menu
  96 * ARM-Chars::                Special Characters
  97 * ARM-Regs::                 Register Names
  98 @end menu
  99
 100 @node ARM-Chars
 101 @subsection Special Characters
 102
 103 @cindex line comment character, ARM
 104 @cindex ARM line comment character
 105 The presence of a @samp{@@} on a line indicates the start of a comment
 106 that extends to the end of the current line.  If a @samp{#} appears as
 107 the first character of a line, the whole line is treated as a comment.
 108
 109 @cindex line separator, ARM
 110 @cindex statement separator, ARM
 111 @cindex ARM line separator
 112 On ARM systems running the GNU/Linux operating system, @samp{;} can be
 113 used instead of a newline to separate statements.
 114
 115 @cindex immediate character, ARM
 116 @cindex ARM immediate character
 117 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
 118
 119 @cindex identifiers, ARM
 120 @cindex ARM identifiers
 121 *TODO* Explain about /data modifier on symbols.
 122
 123 @node ARM-Regs
 124 @subsection Register Names
 125
 126 @cindex ARM register names
 127 @cindex register names, ARM
 128 *TODO* Explain about ARM register naming, and the predefined names.
 129
 130 @node ARM Floating Point
 131 @section Floating Point
 132
 133 @cindex floating point, ARM (@sc{ieee})
 134 @cindex ARM floating point (@sc{ieee})
 135 The ARM family uses @sc{ieee} floating-point numbers.
 136
 137
 138
 139 @node ARM Directives
 140 @section ARM Machine Directives
 141
 142 @cindex machine directives, ARM
 143 @cindex ARM machine directives
 144 @table @code
 145
 146 @cindex @code{req} directive, ARM
 147 @item @var{name} .req @var{register name}
 148 This creates an alias for @var{register name} called @var{name}.  For
 149 example:
 150
 151 @smallexample
 152         foo .req r0
 153 @end smallexample
 154
 155 @cindex @code{code} directive, ARM
 156 @item .code [@var{16}|@var{32}]
 157 This directive selects the instruction set being generated. The value 16
 158 selects Thumb, with the value 32 selecting ARM.
 159
 160 @cindex @code{thumb} directive, ARM
 161 @item .thumb
 162 This performs the same action as @var{.code 16}.
 163
 164 @cindex @code{arm} directive, ARM
 165 @item .arm
 166 This performs the same action as @var{.code 32}.
 167
 168 @cindex @code{force_thumb} directive, ARM
 169 @item .force_thumb
 170 This directive forces the selection of Thumb instructions, even if the
 171 target processor does not support those instructions
 172
 173 @cindex @code{thumb_func} directive, ARM
 174 @item .thumb_func
 175 This directive specifies that the following symbol is the name of a
 176 Thumb encoded function.  This information is necessary in order to allow
 177 the assembler and linker to generate correct code for interworking
 178 between Arm and Thumb instructions and should be used even if
 179 interworking is not going to be performed.
 180
 181 @cindex @code{thumb_set} directive, ARM
 182 @item .thumb_set
 183 This performs the equivalent of a @code{.set} directive in that it
 184 creates a symbol which is an alias for another symbol (possibly not yet
 185 defined).  This directive also has the added property in that it marks
 186 the aliased symbol as being a thumb function entry point, in the same
 187 way that the @code{.thumb_func} directive does.
 188
 189 @cindex @code{.ltorg} directive, ARM
 190 @item .ltorg
 191 This directive causes the current contents of the literal pool to be
 192 dumped into the current section (which is assumed to be the .text
 193 section) at the current location (aligned to a word boundary).
 194
 195 @cindex @code{.pool} directive, ARM
 196 @item .pool
 197 This is a synonym for .ltorg.
 198
 199 @end table
 200
 201 @node ARM Opcodes
 202 @section Opcodes
 203
 204 @cindex ARM opcodes
 205 @cindex opcodes for ARM
 206 @code{@value{AS}} implements all the standard ARM opcodes.  It also
 207 implements several pseudo opcodes, including several synthetic load
 208 instructions.
 209
 210 @table @code
 211
 212 @cindex @code{NOP} pseudo op, ARM
 213 @item NOP
 214 @smallexample
 215   nop
 216 @end smallexample
 217
 218 This pseudo op will always evaluate to a legal ARM instruction that does
 219 nothing.  Currently it will evaluate to MOV r0, r0.
 220
 221 @cindex @code{LDR reg,=<label>} pseudo op, ARM
 222 @item LDR
 223 @smallexample
 224   ldr <register> , = <expression>
 225 @end smallexample
 226
 227 If expression evaluates to a numeric constant then a MOV or MVN
 228 instruction will be used in place of the LDR instruction, if the
 229 constant can be generated by either of these instructions.  Otherwise
 230 the constant will be placed into the nearest literal pool (if it not
 231 already there) and a PC relative LDR instruction will be generated.
 232
 233 @cindex @code{ADR reg,<label>} pseudo op, ARM
 234 @item ADR
 235 @smallexample
 236   adr <register> <label>
 237 @end smallexample
 238
 239 This instruction will load the address of @var{label} into the indicated
 240 register.  The instruction will evaluate to a PC relative ADD or SUB
 241 instruction depending upon where the label is located.  If the label is
 242 out of range, or if it is not defined in the same file (and section) as
 243 the ADR instruction, then an error will be generated.  This instruction
 244 will not make use of the literal pool.
 245
 246 @cindex @code{ADRL reg,<label>} pseudo op, ARM
 247 @item ADRL
 248 @smallexample
 249   adrl <register> <label>
 250 @end smallexample
 251
 252 This instruction will load the address of @var{label} into the indicated
 253 register.  The instruction will evaluate to one or two a PC relative ADD
 254 or SUB instructions depending upon where the label is located.  If a
 255 second instruction is not needed a NOP instruction will be generated in
 256 its place, so that this instruction is always 8 bytes long.
 257
 258 If the label is out of range, or if it is not defined in the same file
 259 (and section) as the ADRL instruction, then an error will be generated.
 260 This instruction will not make use of the literal pool.
 261
 262 @end table
 263
 264 For information on the ARM or Thumb instruction sets, see @cite{ARM
 265 Software Development Toolkit Reference Manual}, Advanced RISC Machines
 266 Ltd.
 267