1 @c Copyright (C) 2019-2023 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
8 @chapter BPF Dependent Features
12 @node Machine Dependencies
13 @chapter BPF Dependent Features
18 * BPF Options:: BPF specific command-line options.
19 * BPF Special Characters:: Comments and statements.
20 * BPF Registers:: Register names.
21 * BPF Directives:: Machine directives.
22 * BPF Instructions:: Machine instructions.
27 @cindex BPF options (none)
28 @cindex options for BPF (none)
33 @cindex @option{-EB} command-line option, BPF
35 This option specifies that the assembler should emit big-endian eBPF.
37 @cindex @option{-EL} command-line option, BPF
39 This option specifies that the assembler should emit little-endian
42 @cindex @option{-mdialect} command-line options, BPF
43 @item -mdialect=@var{dialect}
44 This option specifies the assembly language dialect to recognize while
45 assembling. The assembler supports @option{normal} and
48 @cindex @option{-misa-spec} command-line options, BPF
49 @item -misa-spec=@var{spec}
50 This option specifies the version of the BPF instruction set to use
51 when assembling. The BPF ISA versions supported are @option{v1} @option{v2}, @option{v3} and @option{v4}.
53 The value @option{xbpf} can be specified to recognize extra
54 instructions that are used by GCC for testing purposes. But beware
55 this is not valid BPF.
57 @cindex @option{-mno-relax} command-line options, BPF
59 This option tells the assembler to not relax instructions.
62 Note that if no endianness option is specified in the command line,
63 the host endianness is used.
66 @node BPF Special Characters
67 @section BPF Special Characters
69 @cindex line comment character, BPF
70 @cindex BPF line comment character
71 The presence of a @samp{;} or a @samp{#} on a line indicates the start
72 of a comment that extends to the end of the current line.
74 @cindex statement separator, BPF
75 Statements and assembly directives are separated by newlines.
78 @section BPF Registers
80 @cindex BPF register names
81 @cindex register names, BPF
82 The eBPF processor provides ten general-purpose 64-bit registers,
83 which are read-write, and a read-only frame pointer register:
90 General-purpose registers.
93 Read-only frame pointer register.
96 All BPF registers are 64-bit long. However, in the Pseudo-C syntax
97 registers can be referred using different names, which actually
98 reflect the kind of instruction they appear on:
105 General-purpose register in an instruction that operates on its value
106 as if it was a 64-bit value.
108 General-purpose register in an instruction that operates on its value
109 as if it was a 32-bit value.
111 Read-only frame pointer register.
115 Note that in the Pseudo-C syntax register names are not preceded by
119 @section BPF Directives
121 @cindex machine directives, BPF
123 The BPF version of @code{@value{AS}} supports the following additional
127 @cindex @code{half} directive, BPF
129 The @code{.half} directive produces a 16 bit value.
131 @cindex @code{word} directive, BPF
133 The @code{.word} directive produces a 32 bit value.
135 @cindex @code{dword} directive, BPF
137 The @code{.dword} directive produces a 64 bit value.
140 @node BPF Instructions
141 @section BPF Instructions
144 @cindex opcodes for BPF
145 In the instruction descriptions below the following field descriptors
150 Destination general-purpose register whose role is to be the
151 destination of an operation.
153 Source general-purpose register whose role is to be the source of an
156 16-bit signed PC-relative offset, measured in number of 64-bit words,
159 32-bit signed PC-relative offset, measured in number of 64-bit words,
162 Signed 16-bit immediate representing an offset in bytes.
164 Signed 16-bit immediate representing a displacement to a target,
165 measured in number of 64-bit words @emph{minus one}.
167 Signed 32-bit immediate representing a displacement to a target,
168 measured in number of 64-bit words @emph{minus one}.
170 Signed 32-bit immediate.
172 Signed 64-bit immediate.
176 Note that the assembler allows to express the value for an immediate
177 using any numerical literal whose two's complement encoding fits in
178 the immediate field. For example, @code{-2}, @code{0xfffffffe} and
179 @code{4294967294} all denote the same encoded 32-bit immediate, whose
180 value may be then interpreted by different instructions as either as a
181 negative or a positive number.
183 @subsection Arithmetic instructions
185 The destination register in these instructions act like an
188 Note that in pseudoc syntax these instructions should use @code{r}
196 64-bit arithmetic addition.
202 64-bit arithmetic subtraction.
208 64-bit arithmetic multiplication.
214 64-bit arithmetic integer division.
220 64-bit integer remainder.
226 64-bit bit-wise ``and'' operation.
232 64-bit bit-wise ``or'' operation.
238 64-bit bit-wise exclusive-or operation.
244 64-bit left shift, by @code{rs} or @code{imm32} bits.
250 64-bit right logical shift, by @code{rs} or @code{imm32} bits.
253 @itemx arsh rd, imm32
256 64-bit right arithmetic shift, by @code{rs} or @code{imm32} bits.
260 64-bit arithmetic negation.
266 Move the 64-bit value of @code{rs} in @code{rd}, or load @code{imm32}
271 Move the sign-extended 8-bit value in @code{rs} to @code{rd}.
273 @item movs rd, rs, 16
275 Move the sign-extended 16-bit value in @code{rs} to @code{rd}.
277 @item movs rd, rs, 32
279 Move the sign-extended 32-bit value in @code{rs} to @code{rd}.
282 @subsection 32-bit arithmetic instructions
284 The destination register in these instructions act as an accumulator.
286 Note that in pseudoc syntax these instructions should use @code{w}
287 registers. It is not allowed to mix @code{w} and @code{r} registers
288 in the same instruction.
292 @itemx add32 rd, imm32
295 32-bit arithmetic addition.
298 @itemx sub32 rd, imm32
301 32-bit arithmetic subtraction.
304 @itemx mul32 rd, imm32
307 32-bit arithmetic multiplication.
310 @itemx div32 rd, imm32
313 32-bit arithmetic integer division.
316 @itemx mod32 rd, imm32
319 32-bit integer remainder.
322 @itemx and32 rd, imm32
325 32-bit bit-wise ``and'' operation.
328 @itemx or32 rd, imm32
331 32-bit bit-wise ``or'' operation.
334 @itemx xor32 rd, imm32
337 32-bit bit-wise exclusive-or operation.
340 @itemx lsh32 rd, imm32
343 32-bit left shift, by @code{rs} or @code{imm32} bits.
346 @itemx rsh32 rd, imm32
349 32-bit right logical shift, by @code{rs} or @code{imm32} bits.
352 @itemx arsh32 rd, imm32
355 32-bit right arithmetic shift, by @code{rs} or @code{imm32} bits.
359 32-bit arithmetic negation.
362 @itemx mov32 rd, imm32
365 Move the 32-bit value of @code{rs} in @code{rd}, or load @code{imm32}
368 @item mov32s rd, rs, 8
370 Move the sign-extended 8-bit value in @code{rs} to @code{rd}.
372 @item mov32s rd, rs, 16
374 Move the sign-extended 16-bit value in @code{rs} to @code{rd}.
376 @item mov32s rd, rs, 32
378 Move the sign-extended 32-bit value in @code{rs} to @code{rd}.
381 @subsection Endianness conversion instructions
390 Convert the 16-bit, 32-bit or 64-bit value in @code{rd} to
391 little-endian and store it back in @code{rd}.
398 Convert the 16-bit, 32-bit or 64-bit value in @code{rd} to big-endian
399 and store it back in @code{rd}.
402 @subsection Byte swap instructions
406 @itemx rd = bswap16 rd
407 Swap the least-significant 16-bit word in @code{rd} with the
408 most-significant 16-bit word.
411 @itemx rd = bswap32 rd
412 Swap the least-significant 32-bit word in @code{rd} with the
413 most-significant 32-bit word.
416 @itemx rd = bswap64 rd
417 Swap the least-significant 64-bit word in @code{rd} with the
418 most-significant 64-bit word.
422 @subsection 64-bit load and pseudo maps
427 Load the given signed 64-bit immediate to the destination register
431 @subsection Load instructions for socket filters
433 The following instructions are intended to be used in socket filters,
434 and are therefore not general-purpose: they make assumptions on the
435 contents of several registers. See the file
436 @file{Documentation/networking/filter.txt} in the Linux kernel source
437 tree for more information.
443 @itemx r0 = *(u64 *) skb[imm32]
444 Absolute 64-bit load.
447 @itemx r0 = *(u32 *) skb[imm32]
448 Absolute 32-bit load.
451 @itemx r0 = *(u16 *) skb[imm32]
452 Absolute 16-bit load.
455 @itemx r0 = *(u8 *) skb[imm32]
462 @item ldinddw rs, imm32
463 @itemx r0 = *(u64 *) skb[rs + imm32]
464 Indirect 64-bit load.
466 @item ldindw rs, imm32
467 @itemx r0 = *(u32 *) skb[rs + imm32]
468 Indirect 32-bit load.
470 @item ldindh rs, imm32
471 @itemx r0 = *(u16 *) skb[rs + imm32]
472 Indirect 16-bit load.
474 @item ldindb %s, imm32
475 @itemx r0 = *(u8 *) skb[rs + imm32]
479 @subsection Generic load/store instructions
481 General-purpose load and store instructions are provided for several
484 Load to register instructions:
487 @item ldxdw rd, [rs + offset16]
488 @itemx rd = *(u64 *) (rs + offset16)
491 @item ldxw rd, [rs + offset16]
492 @itemx rd = *(u32 *) (rs + offset16)
495 @item ldxh rd, [rs + offset16]
496 @itemx rd = *(u16 *) (rs + offset16)
499 @item ldxb rd, [rs + offset16]
500 @itemx rd = *(u8 *) (rs + offset16)
504 Signed load to register instructions:
507 @item ldxsdw rd, [rs + offset16]
508 @itemx rd = *(s64 *) (rs + offset16)
509 Generic 64-bit signed load.
511 @item ldxsw rd, [rs + offset16]
512 @itemx rd = *(s32 *) (rs + offset16)
513 Generic 32-bit signed load.
515 @item ldxsh rd, [rs + offset16]
516 @itemx rd = *(s16 *) (rs + offset16)
517 Generic 16-bit signed load.
519 @item ldxsb rd, [rs + offset16]
520 @itemx rd = *(s8 *) (rs + offset16)
521 Generic 8-bit signed load.
524 Store from register instructions:
527 @item stxdw [rd + offset16], %s
528 @itemx *(u64 *) (rd + offset16)
529 Generic 64-bit store.
531 @item stxw [rd + offset16], %s
532 @itemx *(u32 *) (rd + offset16)
533 Generic 32-bit store.
535 @item stxh [rd + offset16], %s
536 @itemx *(u16 *) (rd + offset16)
537 Generic 16-bit store.
539 @item stxb [rd + offset16], %s
540 @itemx *(u8 *) (rd + offset16)
544 Store from immediates instructions:
547 @item stdw [rd + offset16], imm32
548 @itemx *(u64 *) (rd + offset16) = imm32
549 Store immediate as 64-bit.
551 @item stw [rd + offset16], imm32
552 @itemx *(u32 *) (rd + offset16) = imm32
553 Store immediate as 32-bit.
555 @item sth [rd + offset16], imm32
556 @itemx *(u16 *) (rd + offset16) = imm32
557 Store immediate as 16-bit.
559 @item stb [rd + offset16], imm32
560 @itemx *(u8 *) (rd + offset16) = imm32
561 Store immediate as 8-bit.
564 @subsection Jump instructions
566 eBPF provides the following compare-and-jump instructions, which
567 compare the values of the two given registers, or the values of a
568 register and an immediate, and perform a branch in case the comparison
578 Jump-always, long range.
580 @item jeq rd, rs, disp16
581 @itemx jeq rd, imm32, disp16
582 @itemx if rd == rs goto disp16
583 @itemx if rd == imm32 goto disp16
584 Jump if equal, unsigned.
586 @item jgt rd, rs, disp16
587 @itemx jgt rd, imm32, disp16
588 @itemx if rd > rs goto disp16
589 @itemx if rd > imm32 goto disp16
590 Jump if greater, unsigned.
592 @item jge rd, rs, disp16
593 @itemx jge rd, imm32, disp16
594 @itemx if rd >= rs goto disp16
595 @itemx if rd >= imm32 goto disp16
596 Jump if greater or equal.
598 @item jlt rd, rs, disp16
599 @itemx jlt rd, imm32, disp16
600 @itemx if rd < rs goto disp16
601 @itemx if rd < imm32 goto disp16
604 @item jle rd , rs, disp16
605 @itemx jle rd, imm32, disp16
606 @itemx if rd <= rs goto disp16
607 @itemx if rd <= imm32 goto disp16
608 Jump if lesser or equal.
610 @item jset rd, rs, disp16
611 @itemx jset rd, imm32, disp16
612 @itemx if rd & rs goto disp16
613 @itemx if rd & imm32 goto disp16
614 Jump if signed equal.
616 @item jne rd, rs, disp16
617 @itemx jne rd, imm32, disp16
618 @itemx if rd != rs goto disp16
619 @itemx if rd != imm32 goto disp16
622 @item jsgt rd, rs, disp16
623 @itemx jsgt rd, imm32, disp16
624 @itemx if rd s> rs goto disp16
625 @itemx if rd s> imm32 goto disp16
626 Jump if signed greater.
628 @item jsge rd, rs, disp16
629 @itemx jsge rd, imm32, disp16
630 @itemx if rd s>= rd goto disp16
631 @itemx if rd s>= imm32 goto disp16
632 Jump if signed greater or equal.
634 @item jslt rd, rs, disp16
635 @itemx jslt rd, imm32, disp16
636 @itemx if rd s< rs goto disp16
637 @itemx if rd s< imm32 goto disp16
638 Jump if signed lesser.
640 @item jsle rd, rs, disp16
641 @itemx jsle rd, imm32, disp16
642 @itemx if rd s<= rs goto disp16
643 @itemx if rd s<= imm32 goto disp16
644 Jump if signed lesser or equal.
647 A call instruction is provided in order to perform calls to other eBPF
648 functions, or to external kernel helpers:
653 Jump and link to the offset @emph{disp32}, or to the kernel helper
654 function identified by @emph{imm32}.
661 Terminate the eBPF program.
664 @subsection 32-bit jump instructions
666 eBPF provides the following compare-and-jump instructions, which
667 compare the 32-bit values of the two given registers, or the values of
668 a register and an immediate, and perform a branch in case the
669 comparison holds true.
671 These instructions are only available in BPF v3 or later.
674 @item jeq32 rd, rs, disp16
675 @itemx jeq32 rd, imm32, disp16
676 @itemx if rd == rs goto disp16
677 @itemx if rd == imm32 goto disp16
678 Jump if equal, unsigned.
680 @item jgt32 rd, rs, disp16
681 @itemx jgt32 rd, imm32, disp16
682 @itemx if rd > rs goto disp16
683 @itemx if rd > imm32 goto disp16
684 Jump if greater, unsigned.
686 @item jge32 rd, rs, disp16
687 @itemx jge32 rd, imm32, disp16
688 @itemx if rd >= rs goto disp16
689 @itemx if rd >= imm32 goto disp16
690 Jump if greater or equal.
692 @item jlt32 rd, rs, disp16
693 @itemx jlt32 rd, imm32, disp16
694 @itemx if rd < rs goto disp16
695 @itemx if rd < imm32 goto disp16
698 @item jle32 rd , rs, disp16
699 @itemx jle32 rd, imm32, disp16
700 @itemx if rd <= rs goto disp16
701 @itemx if rd <= imm32 goto disp16
702 Jump if lesser or equal.
704 @item jset32 rd, rs, disp16
705 @itemx jset32 rd, imm32, disp16
706 @itemx if rd & rs goto disp16
707 @itemx if rd & imm32 goto disp16
708 Jump if signed equal.
710 @item jne32 rd, rs, disp16
711 @itemx jne32 rd, imm32, disp16
712 @itemx if rd != rs goto disp16
713 @itemx if rd != imm32 goto disp16
716 @item jsgt32 rd, rs, disp16
717 @itemx jsgt32 rd, imm32, disp16
718 @itemx if rd s> rs goto disp16
719 @itemx if rd s> imm32 goto disp16
720 Jump if signed greater.
722 @item jsge32 rd, rs, disp16
723 @itemx jsge32 rd, imm32, disp16
724 @itemx if rd s>= rd goto disp16
725 @itemx if rd s>= imm32 goto disp16
726 Jump if signed greater or equal.
728 @item jslt32 rd, rs, disp16
729 @itemx jslt32 rd, imm32, disp16
730 @itemx if rd s< rs goto disp16
731 @itemx if rd s< imm32 goto disp16
732 Jump if signed lesser.
734 @item jsle32 rd, rs, disp16
735 @itemx jsle32 rd, imm32, disp16
736 @itemx if rd s<= rs goto disp16
737 @itemx if rd s<= imm32 goto disp16
738 Jump if signed lesser or equal.
741 @subsection Atomic instructions
743 Atomic exchange instructions are provided in two flavors: one for
744 compare-and-swap, one for unconditional exchange.
747 @item acmp [rd + offset16], rs
748 @itemx r0 = cmpxchg_64 (rd + offset16, r0, rs)
749 Atomic compare-and-swap. Compares value in @code{r0} to value
750 addressed by @code{rd + offset16}. On match, the value addressed by
751 @code{rd + offset16} is replaced with the value in @code{rs}.
752 Regardless, the value that was at @code{rd + offset16} is
753 zero-extended and loaded into @code{r0}.
755 @item axchg [rd + offset16], rs
756 @itemx rs = xchg_64 (rd + offset16, rs)
757 Atomic exchange. Atomically exchanges the value in @code{rs} with
758 the value addressed by @code{rd + offset16}.
762 The following instructions provide atomic arithmetic operations.
765 @item aadd [rd + offset16], rs
766 @itemx lock *(u64 *)(rd + offset16) = rs
767 Atomic add instruction.
769 @item aor [rd + offset16], rs
770 @itemx lock *(u64 *) (rd + offset16) |= rs
771 Atomic or instruction.
773 @item aand [rd + offset16], rs
774 @itemx lock *(u64 *) (rd + offset16) &= rs
775 Atomic and instruction.
777 @item axor [rd + offset16], rs
778 @itemx lock *(u64 *) (rd + offset16) ^= rs
779 Atomic xor instruction.
783 The following variants perform fetching before the atomic operation.
786 @item afadd [rd + offset16], rs
787 @itemx rs = atomic_fetch_add ((u64 *)(rd + offset16), rs)
788 Atomic fetch-and-add instruction.
790 @item afor [rd + offset16], rs
791 @itemx rs = atomic_fetch_or ((u64 *)(rd + offset16), rs)
792 Atomic fetch-and-or instruction.
794 @item afand [rd + offset16], rs
795 @itemx rs = atomic_fetch_and ((u64 *)(rd + offset16), rs)
796 Atomic fetch-and-and instruction.
798 @item afxor [rd + offset16], rs
799 @itemx rs = atomic_fetch_xor ((u64 *)(rd + offset16), rs)
800 Atomic fetch-and-or instruction.
803 The above instructions were introduced in the V3 of the BPF
804 instruction set. The following instruction is supported for backwards
808 @item xadddw [rd + offset16], rs
809 Alias to @code{aadd}.
812 @subsection 32-bit atomic instructions
814 32-bit atomic exchange instructions are provided in two flavors: one
815 for compare-and-swap, one for unconditional exchange.
818 @item acmp32 [rd + offset16], rs
819 @itemx w0 = cmpxchg32_32 (rd + offset16, w0, ws)
820 Atomic compare-and-swap. Compares value in @code{w0} to value
821 addressed by @code{rd + offset16}. On match, the value addressed by
822 @code{rd + offset16} is replaced with the value in @code{ws}.
823 Regardless, the value that was at @code{rd + offset16} is
824 zero-extended and loaded into @code{w0}.
826 @item axchg [rd + offset16], rs
827 @itemx ws = xchg32_32 (rd + offset16, ws)
828 Atomic exchange. Atomically exchanges the value in @code{ws} with
829 the value addressed by @code{rd + offset16}.
833 The following instructions provide 32-bit atomic arithmetic operations.
836 @item aadd32 [rd + offset16], rs
837 @itemx lock *(u32 *)(rd + offset16) = rs
838 Atomic add instruction.
840 @item aor32 [rd + offset16], rs
841 @itemx lock *(u32 *) (rd + offset16) |= rs
842 Atomic or instruction.
844 @item aand32 [rd + offset16], rs
845 @itemx lock *(u32 *) (rd + offset16) &= rs
846 Atomic and instruction.
848 @item axor32 [rd + offset16], rs
849 @itemx lock *(u32 *) (rd + offset16) ^= rs
850 Atomic xor instruction
854 The following variants perform fetching before the atomic operation.
857 @item afadd32 [dr + offset16], rs
858 @itemx ws = atomic_fetch_add ((u32 *)(rd + offset16), ws)
859 Atomic fetch-and-add instruction.
861 @item afor32 [dr + offset16], rs
862 @itemx ws = atomic_fetch_or ((u32 *)(rd + offset16), ws)
863 Atomic fetch-and-or instruction.
865 @item afand32 [dr + offset16], rs
866 @itemx ws = atomic_fetch_and ((u32 *)(rd + offset16), ws)
867 Atomic fetch-and-and instruction.
869 @item afxor32 [dr + offset16], rs
870 @itemx ws = atomic_fetch_xor ((u32 *)(rd + offset16), ws)
871 Atomic fetch-and-or instruction
874 The above instructions were introduced in the V3 of the BPF
875 instruction set. The following instruction is supported for backwards
879 @item xaddw [rd + offset16], rs
880 Alias to @code{aadd32}.