1 @c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1998, 1999, 2000,
2 @c 2001, 2003, 2004, 2005, 2006, 2007, 2008, 2009
3 @c Free Software Foundation, Inc.
4 @c This is part of the GAS manual.
5 @c For copying conditions, see the file as.texinfo.
9 @chapter 80386 Dependent Features
12 @node Machine Dependencies
13 @chapter 80386 Dependent Features
17 @cindex i80386 support
18 @cindex x86-64 support
20 The i386 version @code{@value{AS}} supports both the original Intel 386
21 architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture
22 extending the Intel architecture to 64-bits.
25 * i386-Options:: Options
26 * i386-Directives:: X86 specific directives
27 * i386-Syntax:: AT&T Syntax versus Intel Syntax
28 * i386-Mnemonics:: Instruction Naming
29 * i386-Regs:: Register Naming
30 * i386-Prefixes:: Instruction Prefixes
31 * i386-Memory:: Memory References
32 * i386-Jumps:: Handling of Jump Instructions
33 * i386-Float:: Floating Point
34 * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
35 * i386-LWP:: AMD's Lightweight Profiling Instructions
36 * i386-16bit:: Writing 16-bit Code
37 * i386-Arch:: Specifying an x86 CPU architecture
38 * i386-Bugs:: AT&T Syntax bugs
45 @cindex options for i386
46 @cindex options for x86-64
48 @cindex x86-64 options
50 The i386 version of @code{@value{AS}} has a few machine
54 @cindex @samp{--32} option, i386
55 @cindex @samp{--32} option, x86-64
56 @cindex @samp{--64} option, i386
57 @cindex @samp{--64} option, x86-64
59 Select the word size, either 32 bits or 64 bits. Selecting 32-bit
60 implies Intel i386 architecture, while 64-bit implies AMD x86-64
63 These options are only available with the ELF object file format, and
64 require that the necessary BFD support has been included (on a 32-bit
65 platform you have to add --enable-64-bit-bfd to configure enable 64-bit
66 usage and use x86-64 as target platform).
69 By default, x86 GAS replaces multiple nop instructions used for
70 alignment within code sections with multi-byte nop instructions such
71 as leal 0(%esi,1),%esi. This switch disables the optimization.
73 @cindex @samp{--divide} option, i386
75 On SVR4-derived platforms, the character @samp{/} is treated as a comment
76 character, which means that it cannot be used in expressions. The
77 @samp{--divide} option turns @samp{/} into a normal character. This does
78 not disable @samp{/} at the beginning of a line starting a comment, or
79 affect using @samp{#} for starting a comment.
81 @cindex @samp{-march=} option, i386
82 @cindex @samp{-march=} option, x86-64
83 @item -march=@var{CPU}[+@var{EXTENSION}@dots{}]
84 This option specifies the target processor. The assembler will
85 issue an error message if an attempt is made to assemble an instruction
86 which will not execute on the target processor. The following
87 processor names are recognized:
116 In addition to the basic instruction set, the assembler can be told to
117 accept various extension mnemonics. For example,
118 @code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and
119 @var{vmx}. The following extensions are currently supported:
157 Note that rather than extending a basic instruction set, the extension
158 mnemonics starting with @code{no} revoke the respective functionality.
160 When the @code{.arch} directive is used with @option{-march}, the
161 @code{.arch} directive will take precedent.
163 @cindex @samp{-mtune=} option, i386
164 @cindex @samp{-mtune=} option, x86-64
165 @item -mtune=@var{CPU}
166 This option specifies a processor to optimize for. When used in
167 conjunction with the @option{-march} option, only instructions
168 of the processor specified by the @option{-march} option will be
171 Valid @var{CPU} values are identical to the processor list of
172 @option{-march=@var{CPU}}.
174 @cindex @samp{-msse2avx} option, i386
175 @cindex @samp{-msse2avx} option, x86-64
177 This option specifies that the assembler should encode SSE instructions
180 @cindex @samp{-msse-check=} option, i386
181 @cindex @samp{-msse-check=} option, x86-64
182 @item -msse-check=@var{none}
183 @item -msse-check=@var{warning}
184 @item -msse-check=@var{error}
185 These options control if the assembler should check SSE intructions.
186 @option{-msse-check=@var{none}} will make the assembler not to check SSE
187 instructions, which is the default. @option{-msse-check=@var{warning}}
188 will make the assembler issue a warning for any SSE intruction.
189 @option{-msse-check=@var{error}} will make the assembler issue an error
190 for any SSE intruction.
192 @cindex @samp{-mmnemonic=} option, i386
193 @cindex @samp{-mmnemonic=} option, x86-64
194 @item -mmnemonic=@var{att}
195 @item -mmnemonic=@var{intel}
196 This option specifies instruction mnemonic for matching instructions.
197 The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will
200 @cindex @samp{-msyntax=} option, i386
201 @cindex @samp{-msyntax=} option, x86-64
202 @item -msyntax=@var{att}
203 @item -msyntax=@var{intel}
204 This option specifies instruction syntax when processing instructions.
205 The @code{.att_syntax} and @code{.intel_syntax} directives will
208 @cindex @samp{-mnaked-reg} option, i386
209 @cindex @samp{-mnaked-reg} option, x86-64
211 This opetion specifies that registers don't require a @samp{%} prefix.
212 The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent.
216 @node i386-Directives
217 @section x86 specific Directives
219 @cindex machine directives, x86
220 @cindex x86 machine directives
223 @cindex @code{lcomm} directive, COFF
224 @item .lcomm @var{symbol} , @var{length}[, @var{alignment}]
225 Reserve @var{length} (an absolute expression) bytes for a local common
226 denoted by @var{symbol}. The section and value of @var{symbol} are
227 those of the new local common. The addresses are allocated in the bss
228 section, so that at run-time the bytes start off zeroed. Since
229 @var{symbol} is not declared global, it is normally not visible to
230 @code{@value{LD}}. The optional third parameter, @var{alignment},
231 specifies the desired alignment of the symbol in the bss section.
233 This directive is only available for COFF based x86 targets.
235 @c FIXME: Document other x86 specific directives ? Eg: .code16gcc,
241 @section AT&T Syntax versus Intel Syntax
243 @cindex i386 intel_syntax pseudo op
244 @cindex intel_syntax pseudo op, i386
245 @cindex i386 att_syntax pseudo op
246 @cindex att_syntax pseudo op, i386
247 @cindex i386 syntax compatibility
248 @cindex syntax compatibility, i386
249 @cindex x86-64 intel_syntax pseudo op
250 @cindex intel_syntax pseudo op, x86-64
251 @cindex x86-64 att_syntax pseudo op
252 @cindex att_syntax pseudo op, x86-64
253 @cindex x86-64 syntax compatibility
254 @cindex syntax compatibility, x86-64
256 @code{@value{AS}} now supports assembly using Intel assembler syntax.
257 @code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches
258 back to the usual AT&T mode for compatibility with the output of
259 @code{@value{GCC}}. Either of these directives may have an optional
260 argument, @code{prefix}, or @code{noprefix} specifying whether registers
261 require a @samp{%} prefix. AT&T System V/386 assembler syntax is quite
262 different from Intel syntax. We mention these differences because
263 almost all 80386 documents use Intel syntax. Notable differences
264 between the two syntaxes are:
266 @cindex immediate operands, i386
267 @cindex i386 immediate operands
268 @cindex register operands, i386
269 @cindex i386 register operands
270 @cindex jump/call operands, i386
271 @cindex i386 jump/call operands
272 @cindex operand delimiters, i386
274 @cindex immediate operands, x86-64
275 @cindex x86-64 immediate operands
276 @cindex register operands, x86-64
277 @cindex x86-64 register operands
278 @cindex jump/call operands, x86-64
279 @cindex x86-64 jump/call operands
280 @cindex operand delimiters, x86-64
283 AT&T immediate operands are preceded by @samp{$}; Intel immediate
284 operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}).
285 AT&T register operands are preceded by @samp{%}; Intel register operands
286 are undelimited. AT&T absolute (as opposed to PC relative) jump/call
287 operands are prefixed by @samp{*}; they are undelimited in Intel syntax.
289 @cindex i386 source, destination operands
290 @cindex source, destination operands; i386
291 @cindex x86-64 source, destination operands
292 @cindex source, destination operands; x86-64
294 AT&T and Intel syntax use the opposite order for source and destination
295 operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The
296 @samp{source, dest} convention is maintained for compatibility with
297 previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and
298 instructions with 2 immediate operands, such as the @samp{enter}
299 instruction, do @emph{not} have reversed order. @ref{i386-Bugs}.
301 @cindex mnemonic suffixes, i386
302 @cindex sizes operands, i386
303 @cindex i386 size suffixes
304 @cindex mnemonic suffixes, x86-64
305 @cindex sizes operands, x86-64
306 @cindex x86-64 size suffixes
308 In AT&T syntax the size of memory operands is determined from the last
309 character of the instruction mnemonic. Mnemonic suffixes of @samp{b},
310 @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long
311 (32-bit) and quadruple word (64-bit) memory references. Intel syntax accomplishes
312 this by prefixing memory operands (@emph{not} the instruction mnemonics) with
313 @samp{byte ptr}, @samp{word ptr}, @samp{dword ptr} and @samp{qword ptr}. Thus,
314 Intel @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
317 In 64-bit code, @samp{movabs} can be used to encode the @samp{mov}
318 instruction with the 64-bit displacement or immediate operand.
320 @cindex return instructions, i386
321 @cindex i386 jump, call, return
322 @cindex return instructions, x86-64
323 @cindex x86-64 jump, call, return
325 Immediate form long jumps and calls are
326 @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
328 @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return
330 is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
331 @samp{ret far @var{stack-adjust}}.
333 @cindex sections, i386
334 @cindex i386 sections
335 @cindex sections, x86-64
336 @cindex x86-64 sections
338 The AT&T assembler does not provide support for multiple section
339 programs. Unix style systems expect all programs to be single sections.
343 @section Instruction Naming
345 @cindex i386 instruction naming
346 @cindex instruction naming, i386
347 @cindex x86-64 instruction naming
348 @cindex instruction naming, x86-64
350 Instruction mnemonics are suffixed with one character modifiers which
351 specify the size of operands. The letters @samp{b}, @samp{w}, @samp{l}
352 and @samp{q} specify byte, word, long and quadruple word operands. If
353 no suffix is specified by an instruction then @code{@value{AS}} tries to
354 fill in the missing suffix based on the destination register operand
355 (the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent
356 to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to
357 @samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix
358 assembler which assumes that a missing mnemonic suffix implies long
359 operand size. (This incompatibility does not affect compiler output
360 since compilers always explicitly specify the mnemonic suffix.)
362 Almost all instructions have the same names in AT&T and Intel format.
363 There are a few exceptions. The sign extend and zero extend
364 instructions need two sizes to specify them. They need a size to
365 sign/zero extend @emph{from} and a size to zero extend @emph{to}. This
366 is accomplished by using two instruction mnemonic suffixes in AT&T
367 syntax. Base names for sign extend and zero extend are
368 @samp{movs@dots{}} and @samp{movz@dots{}} in AT&T syntax (@samp{movsx}
369 and @samp{movzx} in Intel syntax). The instruction mnemonic suffixes
370 are tacked on to this base name, the @emph{from} suffix before the
371 @emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for
372 ``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes,
373 thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word),
374 @samp{wl} (from word to long), @samp{bq} (from byte to quadruple word),
375 @samp{wq} (from word to quadruple word), and @samp{lq} (from long to
378 @cindex encoding options, i386
379 @cindex encoding options, x86-64
381 Different encoding options can be specified via optional mnemonic
382 suffix. @samp{.s} suffix swaps 2 register operands in encoding when
383 moving from one register to another.
385 @cindex conversion instructions, i386
386 @cindex i386 conversion instructions
387 @cindex conversion instructions, x86-64
388 @cindex x86-64 conversion instructions
389 The Intel-syntax conversion instructions
393 @samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax},
396 @samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax},
399 @samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax},
402 @samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax},
405 @samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax}
409 @samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in
410 @samp{%rdx:%rax} (x86-64 only),
414 are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and
415 @samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these
418 @cindex jump instructions, i386
419 @cindex call instructions, i386
420 @cindex jump instructions, x86-64
421 @cindex call instructions, x86-64
422 Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
423 AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
426 @section AT&T Mnemonic versus Intel Mnemonic
428 @cindex i386 mnemonic compatibility
429 @cindex mnemonic compatibility, i386
431 @code{@value{AS}} supports assembly using Intel mnemonic.
432 @code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and
433 @code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T
434 syntax for compatibility with the output of @code{@value{GCC}}.
435 Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp},
436 @samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp},
437 @samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386
438 assembler with different mnemonics from those in Intel IA32 specification.
439 @code{@value{GCC}} generates those instructions with AT&T mnemonic.
442 @section Register Naming
444 @cindex i386 registers
445 @cindex registers, i386
446 @cindex x86-64 registers
447 @cindex registers, x86-64
448 Register operands are always prefixed with @samp{%}. The 80386 registers
453 the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx},
454 @samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the
455 frame pointer), and @samp{%esp} (the stack pointer).
458 the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx},
459 @samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}.
462 the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh},
463 @samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These
464 are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx},
465 @samp{%cx}, and @samp{%dx})
468 the 6 section registers @samp{%cs} (code section), @samp{%ds}
469 (data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs},
473 the 3 processor control registers @samp{%cr0}, @samp{%cr2}, and
477 the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2},
478 @samp{%db3}, @samp{%db6}, and @samp{%db7}.
481 the 2 test registers @samp{%tr6} and @samp{%tr7}.
484 the 8 floating point register stack @samp{%st} or equivalently
485 @samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)},
486 @samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}.
487 These registers are overloaded by 8 MMX registers @samp{%mm0},
488 @samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5},
489 @samp{%mm6} and @samp{%mm7}.
492 the 8 SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2},
493 @samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}.
496 The AMD x86-64 architecture extends the register set by:
500 enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the
501 accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi},
502 @samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack
506 the 8 extended registers @samp{%r8}--@samp{%r15}.
509 the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}
512 the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}
515 the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}
518 the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}.
521 the 8 debug registers: @samp{%db8}--@samp{%db15}.
524 the 8 SSE registers: @samp{%xmm8}--@samp{%xmm15}.
528 @section Instruction Prefixes
530 @cindex i386 instruction prefixes
531 @cindex instruction prefixes, i386
532 @cindex prefixes, i386
533 Instruction prefixes are used to modify the following instruction. They
534 are used to repeat string instructions, to provide section overrides, to
535 perform bus lock operations, and to change operand and address sizes.
536 (Most instructions that normally operate on 32-bit operands will use
537 16-bit operands if the instruction has an ``operand size'' prefix.)
538 Instruction prefixes are best written on the same line as the instruction
539 they act upon. For example, the @samp{scas} (scan string) instruction is
543 repne scas %es:(%edi),%al
546 You may also place prefixes on the lines immediately preceding the
547 instruction, but this circumvents checks that @code{@value{AS}} does
548 with prefixes, and will not work with all prefixes.
550 Here is a list of instruction prefixes:
552 @cindex section override prefixes, i386
555 Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es},
556 @samp{fs}, @samp{gs}. These are automatically added by specifying
557 using the @var{section}:@var{memory-operand} form for memory references.
559 @cindex size prefixes, i386
561 Operand/Address size prefixes @samp{data16} and @samp{addr16}
562 change 32-bit operands/addresses into 16-bit operands/addresses,
563 while @samp{data32} and @samp{addr32} change 16-bit ones (in a
564 @code{.code16} section) into 32-bit operands/addresses. These prefixes
565 @emph{must} appear on the same line of code as the instruction they
566 modify. For example, in a 16-bit @code{.code16} section, you might
573 @cindex bus lock prefixes, i386
574 @cindex inhibiting interrupts, i386
576 The bus lock prefix @samp{lock} inhibits interrupts during execution of
577 the instruction it precedes. (This is only valid with certain
578 instructions; see a 80386 manual for details).
580 @cindex coprocessor wait, i386
582 The wait for coprocessor prefix @samp{wait} waits for the coprocessor to
583 complete the current instruction. This should never be needed for the
584 80386/80387 combination.
586 @cindex repeat prefixes, i386
588 The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added
589 to string instructions to make them repeat @samp{%ecx} times (@samp{%cx}
590 times if the current address size is 16-bits).
591 @cindex REX prefixes, i386
593 The @samp{rex} family of prefixes is used by x86-64 to encode
594 extensions to i386 instruction set. The @samp{rex} prefix has four
595 bits --- an operand size overwrite (@code{64}) used to change operand size
596 from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the
599 You may write the @samp{rex} prefixes directly. The @samp{rex64xyz}
600 instruction emits @samp{rex} prefix with all the bits set. By omitting
601 the @code{64}, @code{x}, @code{y} or @code{z} you may write other
602 prefixes as well. Normally, there is no need to write the prefixes
603 explicitly, since gas will automatically generate them based on the
604 instruction operands.
608 @section Memory References
610 @cindex i386 memory references
611 @cindex memory references, i386
612 @cindex x86-64 memory references
613 @cindex memory references, x86-64
614 An Intel syntax indirect memory reference of the form
617 @var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}]
621 is translated into the AT&T syntax
624 @var{section}:@var{disp}(@var{base}, @var{index}, @var{scale})
628 where @var{base} and @var{index} are the optional 32-bit base and
629 index registers, @var{disp} is the optional displacement, and
630 @var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index}
631 to calculate the address of the operand. If no @var{scale} is
632 specified, @var{scale} is taken to be 1. @var{section} specifies the
633 optional section register for the memory operand, and may override the
634 default section register (see a 80386 manual for section register
635 defaults). Note that section overrides in AT&T syntax @emph{must}
636 be preceded by a @samp{%}. If you specify a section override which
637 coincides with the default section register, @code{@value{AS}} does @emph{not}
638 output any section register override prefixes to assemble the given
639 instruction. Thus, section overrides can be specified to emphasize which
640 section register is used for a given memory operand.
642 Here are some examples of Intel and AT&T style memory references:
645 @item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]}
646 @var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is
647 missing, and the default section is used (@samp{%ss} for addressing with
648 @samp{%ebp} as the base register). @var{index}, @var{scale} are both missing.
650 @item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]}
651 @var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is
652 @samp{foo}. All other fields are missing. The section register here
653 defaults to @samp{%ds}.
655 @item AT&T: @samp{foo(,1)}; Intel @samp{[foo]}
656 This uses the value pointed to by @samp{foo} as a memory operand.
657 Note that @var{base} and @var{index} are both missing, but there is only
658 @emph{one} @samp{,}. This is a syntactic exception.
660 @item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo}
661 This selects the contents of the variable @samp{foo} with section
662 register @var{section} being @samp{%gs}.
665 Absolute (as opposed to PC relative) call and jump operands must be
666 prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}}
667 always chooses PC relative addressing for jump/call labels.
669 Any instruction that has a memory operand, but no register operand,
670 @emph{must} specify its size (byte, word, long, or quadruple) with an
671 instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q},
674 The x86-64 architecture adds an RIP (instruction pointer relative)
675 addressing. This addressing mode is specified by using @samp{rip} as a
676 base register. Only constant offsets are valid. For example:
679 @item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]}
680 Points to the address 1234 bytes past the end of the current
683 @item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]}
684 Points to the @code{symbol} in RIP relative way, this is shorter than
685 the default absolute addressing.
688 Other addressing modes remain unchanged in x86-64 architecture, except
689 registers used are 64-bit instead of 32-bit.
692 @section Handling of Jump Instructions
694 @cindex jump optimization, i386
695 @cindex i386 jump optimization
696 @cindex jump optimization, x86-64
697 @cindex x86-64 jump optimization
698 Jump instructions are always optimized to use the smallest possible
699 displacements. This is accomplished by using byte (8-bit) displacement
700 jumps whenever the target is sufficiently close. If a byte displacement
701 is insufficient a long displacement is used. We do not support
702 word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
703 instruction with the @samp{data16} instruction prefix), since the 80386
704 insists upon masking @samp{%eip} to 16 bits after the word displacement
705 is added. (See also @pxref{i386-Arch})
707 Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz},
708 @samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte
709 displacements, so that if you use these instructions (@code{@value{GCC}} does
710 not use them) you may get an error message (and incorrect code). The AT&T
711 80386 assembler tries to get around this problem by expanding @samp{jcxz foo}
722 @section Floating Point
724 @cindex i386 floating point
725 @cindex floating point, i386
726 @cindex x86-64 floating point
727 @cindex floating point, x86-64
728 All 80387 floating point types except packed BCD are supported.
729 (BCD support may be added without much difficulty). These data
730 types are 16-, 32-, and 64- bit integers, and single (32-bit),
731 double (64-bit), and extended (80-bit) precision floating point.
732 Each supported type has an instruction mnemonic suffix and a constructor
733 associated with it. Instruction mnemonic suffixes specify the operand's
734 data type. Constructors build these data types into memory.
736 @cindex @code{float} directive, i386
737 @cindex @code{single} directive, i386
738 @cindex @code{double} directive, i386
739 @cindex @code{tfloat} directive, i386
740 @cindex @code{float} directive, x86-64
741 @cindex @code{single} directive, x86-64
742 @cindex @code{double} directive, x86-64
743 @cindex @code{tfloat} directive, x86-64
746 Floating point constructors are @samp{.float} or @samp{.single},
747 @samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats.
748 These correspond to instruction mnemonic suffixes @samp{s}, @samp{l},
749 and @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387
750 only supports this format via the @samp{fldt} (load 80-bit real to stack
751 top) and @samp{fstpt} (store 80-bit real and pop stack) instructions.
753 @cindex @code{word} directive, i386
754 @cindex @code{long} directive, i386
755 @cindex @code{int} directive, i386
756 @cindex @code{quad} directive, i386
757 @cindex @code{word} directive, x86-64
758 @cindex @code{long} directive, x86-64
759 @cindex @code{int} directive, x86-64
760 @cindex @code{quad} directive, x86-64
762 Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and
763 @samp{.quad} for the 16-, 32-, and 64-bit integer formats. The
764 corresponding instruction mnemonic suffixes are @samp{s} (single),
765 @samp{l} (long), and @samp{q} (quad). As with the 80-bit real format,
766 the 64-bit @samp{q} format is only present in the @samp{fildq} (load
767 quad integer to stack top) and @samp{fistpq} (store quad integer and pop
771 Register to register operations should not use instruction mnemonic suffixes.
772 @samp{fstl %st, %st(1)} will give a warning, and be assembled as if you
773 wrote @samp{fst %st, %st(1)}, since all register to register operations
774 use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem},
775 which converts @samp{%st} from 80-bit to 64-bit floating point format,
776 then stores the result in the 4 byte location @samp{mem})
779 @section Intel's MMX and AMD's 3DNow! SIMD Operations
785 @cindex 3DNow!, x86-64
788 @code{@value{AS}} supports Intel's MMX instruction set (SIMD
789 instructions for integer data), available on Intel's Pentium MMX
790 processors and Pentium II processors, AMD's K6 and K6-2 processors,
791 Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@:
792 instruction set (SIMD instructions for 32-bit floating point data)
793 available on AMD's K6-2 processor and possibly others in the future.
795 Currently, @code{@value{AS}} does not support Intel's floating point
798 The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0},
799 @samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four
800 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
801 floating point values. The MMX registers cannot be used at the same time
802 as the floating point stack.
804 See Intel and AMD documentation, keeping in mind that the operand order in
805 instructions is reversed from the Intel syntax.
808 @section AMD's Lightweight Profiling Instructions
813 @code{@value{AS}} supports AMD's Lightweight Profiling (LWP)
814 instruction set, available on AMD's Family 15h (Orochi) processors.
816 LWP enables applications to collect and manage performance data, and
817 react to performance events. The collection of performance data
818 requires no context switches. LWP runs in the context of a thread and
819 so several counters can be used independently across multiple threads.
820 LWP can be used in both 64-bit and legacy 32-bit modes.
822 For detailed information on the LWP instruction set, see the
823 @cite{AMD Lightweight Profiling Specification} available at
824 @uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}.
827 @section Writing 16-bit Code
829 @cindex i386 16-bit code
830 @cindex 16-bit code, i386
831 @cindex real-mode code, i386
832 @cindex @code{code16gcc} directive, i386
833 @cindex @code{code16} directive, i386
834 @cindex @code{code32} directive, i386
835 @cindex @code{code64} directive, i386
836 @cindex @code{code64} directive, x86-64
837 While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code
838 or 64-bit x86-64 code depending on the default configuration,
839 it also supports writing code to run in real mode or in 16-bit protected
840 mode code segments. To do this, put a @samp{.code16} or
841 @samp{.code16gcc} directive before the assembly language instructions to
842 be run in 16-bit mode. You can switch @code{@value{AS}} to writing
843 32-bit code with the @samp{.code32} directive or 64-bit code with the
844 @samp{.code64} directive.
846 @samp{.code16gcc} provides experimental support for generating 16-bit
847 code from gcc, and differs from @samp{.code16} in that @samp{call},
848 @samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop},
849 @samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions
850 default to 32-bit size. This is so that the stack pointer is
851 manipulated in the same way over function calls, allowing access to
852 function parameters at the same stack offsets as in 32-bit mode.
853 @samp{.code16gcc} also automatically adds address size prefixes where
854 necessary to use the 32-bit addressing modes that gcc generates.
856 The code which @code{@value{AS}} generates in 16-bit mode will not
857 necessarily run on a 16-bit pre-80386 processor. To write code that
858 runs on such a processor, you must refrain from using @emph{any} 32-bit
859 constructs which require @code{@value{AS}} to output address or operand
862 Note that writing 16-bit code instructions by explicitly specifying a
863 prefix or an instruction mnemonic suffix within a 32-bit code section
864 generates different machine instructions than those generated for a
865 16-bit code segment. In a 32-bit code section, the following code
866 generates the machine opcode bytes @samp{66 6a 04}, which pushes the
867 value @samp{4} onto the stack, decrementing @samp{%esp} by 2.
873 The same code in a 16-bit code section would generate the machine
874 opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which
875 is correct since the processor default operand size is assumed to be 16
876 bits in a 16-bit code section.
879 @section AT&T Syntax bugs
881 The UnixWare assembler, and probably other AT&T derived ix86 Unix
882 assemblers, generate floating point instructions with reversed source
883 and destination registers in certain cases. Unfortunately, gcc and
884 possibly many other programs use this reversed syntax, so we're stuck
893 results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather
894 than the expected @samp{%st(3) - %st}. This happens with all the
895 non-commutative arithmetic floating point operations with two register
896 operands where the source register is @samp{%st} and the destination
897 register is @samp{%st(i)}.
900 @section Specifying CPU Architecture
902 @cindex arch directive, i386
903 @cindex i386 arch directive
904 @cindex arch directive, x86-64
905 @cindex x86-64 arch directive
907 @code{@value{AS}} may be told to assemble for a particular CPU
908 (sub-)architecture with the @code{.arch @var{cpu_type}} directive. This
909 directive enables a warning when gas detects an instruction that is not
910 supported on the CPU specified. The choices for @var{cpu_type} are:
912 @multitable @columnfractions .20 .20 .20 .20
913 @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
914 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
915 @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
916 @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
917 @item @samp{corei7} @tab @samp{l1om}
918 @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
919 @item @samp{amdfam10} @tab @samp{amdfam15}
920 @item @samp{generic32} @tab @samp{generic64}
921 @item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
922 @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
923 @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.xsave}
924 @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.movbe}
925 @item @samp{.ept} @tab @samp{.clflush}
926 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
927 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
928 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop}
929 @item @samp{.padlock}
932 Apart from the warning, there are only two other effects on
933 @code{@value{AS}} operation; Firstly, if you specify a CPU other than
934 @samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax}
935 will automatically use a two byte opcode sequence. The larger three
936 byte opcode sequence is used on the 486 (and when no architecture is
937 specified) because it executes faster on the 486. Note that you can
938 explicitly request the two byte opcode by writing @samp{sarl %eax}.
939 Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286},
940 @emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset
941 conditional jumps will be promoted when necessary to a two instruction
942 sequence consisting of a conditional jump of the opposite sense around
943 an unconditional jump to the target.
945 Following the CPU architecture (but not a sub-architecture, which are those
946 starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to
947 control automatic promotion of conditional jumps. @samp{jumps} is the
948 default, and enables jump promotion; All external jumps will be of the long
949 variety, and file-local jumps will be promoted as necessary.
950 (@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as
951 byte offset jumps, and warns about file-local conditional jumps that
952 @code{@value{AS}} promotes.
953 Unconditional jumps are treated as for @samp{jumps}.
964 @cindex i386 @code{mul}, @code{imul} instructions
965 @cindex @code{mul} instruction, i386
966 @cindex @code{imul} instruction, i386
967 @cindex @code{mul} instruction, x86-64
968 @cindex @code{imul} instruction, x86-64
969 There is some trickery concerning the @samp{mul} and @samp{imul}
970 instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding
971 multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5
972 for @samp{imul}) can be output only in the one operand form. Thus,
973 @samp{imul %ebx, %eax} does @emph{not} select the expanding multiply;
974 the expanding multiply would clobber the @samp{%edx} register, and this
975 would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the
976 64-bit product in @samp{%edx:%eax}.
978 We have added a two operand form of @samp{imul} when the first operand
979 is an immediate mode expression and the second operand is a register.
980 This is just a shorthand, so that, multiplying @samp{%eax} by 69, for
981 example, can be done with @samp{imul $69, %eax} rather than @samp{imul