1 @c Copyright (C) 1991-2020 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
9 @chapter 80386 Dependent Features
12 @node Machine Dependencies
13 @chapter 80386 Dependent Features
17 @cindex i80386 support
18 @cindex x86-64 support
20 The i386 version @code{@value{AS}} supports both the original Intel 386
21 architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture
22 extending the Intel architecture to 64-bits.
25 * i386-Options:: Options
26 * i386-Directives:: X86 specific directives
27 * i386-Syntax:: Syntactical considerations
28 * i386-Mnemonics:: Instruction Naming
29 * i386-Regs:: Register Naming
30 * i386-Prefixes:: Instruction Prefixes
31 * i386-Memory:: Memory References
32 * i386-Jumps:: Handling of Jump Instructions
33 * i386-Float:: Floating Point
34 * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
35 * i386-LWP:: AMD's Lightweight Profiling Instructions
36 * i386-BMI:: Bit Manipulation Instruction
37 * i386-TBM:: AMD's Trailing Bit Manipulation Instructions
38 * i386-16bit:: Writing 16-bit Code
39 * i386-Arch:: Specifying an x86 CPU architecture
40 * i386-ISA:: AMD64 ISA vs. Intel64 ISA
41 * i386-Bugs:: AT&T Syntax bugs
48 @cindex options for i386
49 @cindex options for x86-64
51 @cindex x86-64 options
53 The i386 version of @code{@value{AS}} has a few machine
58 @cindex @samp{--32} option, i386
59 @cindex @samp{--32} option, x86-64
60 @cindex @samp{--x32} option, i386
61 @cindex @samp{--x32} option, x86-64
62 @cindex @samp{--64} option, i386
63 @cindex @samp{--64} option, x86-64
64 @item --32 | --x32 | --64
65 Select the word size, either 32 bits or 64 bits. @samp{--32}
66 implies Intel i386 architecture, while @samp{--x32} and @samp{--64}
67 imply AMD x86-64 architecture with 32-bit or 64-bit word-size
70 These options are only available with the ELF object file format, and
71 require that the necessary BFD support has been included (on a 32-bit
72 platform you have to add --enable-64-bit-bfd to configure enable 64-bit
73 usage and use x86-64 as target platform).
76 By default, x86 GAS replaces multiple nop instructions used for
77 alignment within code sections with multi-byte nop instructions such
78 as leal 0(%esi,1),%esi. This switch disables the optimization if a single
79 byte nop (0x90) is explicitly specified as the fill byte for alignment.
81 @cindex @samp{--divide} option, i386
83 On SVR4-derived platforms, the character @samp{/} is treated as a comment
84 character, which means that it cannot be used in expressions. The
85 @samp{--divide} option turns @samp{/} into a normal character. This does
86 not disable @samp{/} at the beginning of a line starting a comment, or
87 affect using @samp{#} for starting a comment.
89 @cindex @samp{-march=} option, i386
90 @cindex @samp{-march=} option, x86-64
91 @item -march=@var{CPU}[+@var{EXTENSION}@dots{}]
92 This option specifies the target processor. The assembler will
93 issue an error message if an attempt is made to assemble an instruction
94 which will not execute on the target processor. The following
95 processor names are recognized:
133 In addition to the basic instruction set, the assembler can be told to
134 accept various extension mnemonics. For example,
135 @code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and
136 @var{vmx}. The following extensions are currently supported:
205 @code{avx512_4fmaps},
206 @code{avx512_4vnniw},
207 @code{avx512_vpopcntdq},
210 @code{avx512_bitalg},
211 @code{avx512_vp2intersect},
223 @code{noavx512_4fmaps},
224 @code{noavx512_4vnniw},
225 @code{noavx512_vpopcntdq},
226 @code{noavx512_vbmi2},
227 @code{noavx512_vnni},
228 @code{noavx512_bitalg},
229 @code{noavx512_vp2intersect},
231 @code{noavx512_bf16},
286 Note that rather than extending a basic instruction set, the extension
287 mnemonics starting with @code{no} revoke the respective functionality.
289 When the @code{.arch} directive is used with @option{-march}, the
290 @code{.arch} directive will take precedent.
292 @cindex @samp{-mtune=} option, i386
293 @cindex @samp{-mtune=} option, x86-64
294 @item -mtune=@var{CPU}
295 This option specifies a processor to optimize for. When used in
296 conjunction with the @option{-march} option, only instructions
297 of the processor specified by the @option{-march} option will be
300 Valid @var{CPU} values are identical to the processor list of
301 @option{-march=@var{CPU}}.
303 @cindex @samp{-msse2avx} option, i386
304 @cindex @samp{-msse2avx} option, x86-64
306 This option specifies that the assembler should encode SSE instructions
309 @cindex @samp{-msse-check=} option, i386
310 @cindex @samp{-msse-check=} option, x86-64
311 @item -msse-check=@var{none}
312 @itemx -msse-check=@var{warning}
313 @itemx -msse-check=@var{error}
314 These options control if the assembler should check SSE instructions.
315 @option{-msse-check=@var{none}} will make the assembler not to check SSE
316 instructions, which is the default. @option{-msse-check=@var{warning}}
317 will make the assembler issue a warning for any SSE instruction.
318 @option{-msse-check=@var{error}} will make the assembler issue an error
319 for any SSE instruction.
321 @cindex @samp{-mavxscalar=} option, i386
322 @cindex @samp{-mavxscalar=} option, x86-64
323 @item -mavxscalar=@var{128}
324 @itemx -mavxscalar=@var{256}
325 These options control how the assembler should encode scalar AVX
326 instructions. @option{-mavxscalar=@var{128}} will encode scalar
327 AVX instructions with 128bit vector length, which is the default.
328 @option{-mavxscalar=@var{256}} will encode scalar AVX instructions
329 with 256bit vector length.
331 WARNING: Don't use this for production code - due to CPU errata the
332 resulting code may not work on certain models.
334 @cindex @samp{-mvexwig=} option, i386
335 @cindex @samp{-mvexwig=} option, x86-64
336 @item -mvexwig=@var{0}
337 @itemx -mvexwig=@var{1}
338 These options control how the assembler should encode VEX.W-ignored (WIG)
339 VEX instructions. @option{-mvexwig=@var{0}} will encode WIG VEX
340 instructions with vex.w = 0, which is the default.
341 @option{-mvexwig=@var{1}} will encode WIG EVEX instructions with
344 WARNING: Don't use this for production code - due to CPU errata the
345 resulting code may not work on certain models.
347 @cindex @samp{-mevexlig=} option, i386
348 @cindex @samp{-mevexlig=} option, x86-64
349 @item -mevexlig=@var{128}
350 @itemx -mevexlig=@var{256}
351 @itemx -mevexlig=@var{512}
352 These options control how the assembler should encode length-ignored
353 (LIG) EVEX instructions. @option{-mevexlig=@var{128}} will encode LIG
354 EVEX instructions with 128bit vector length, which is the default.
355 @option{-mevexlig=@var{256}} and @option{-mevexlig=@var{512}} will
356 encode LIG EVEX instructions with 256bit and 512bit vector length,
359 @cindex @samp{-mevexwig=} option, i386
360 @cindex @samp{-mevexwig=} option, x86-64
361 @item -mevexwig=@var{0}
362 @itemx -mevexwig=@var{1}
363 These options control how the assembler should encode w-ignored (WIG)
364 EVEX instructions. @option{-mevexwig=@var{0}} will encode WIG
365 EVEX instructions with evex.w = 0, which is the default.
366 @option{-mevexwig=@var{1}} will encode WIG EVEX instructions with
369 @cindex @samp{-mmnemonic=} option, i386
370 @cindex @samp{-mmnemonic=} option, x86-64
371 @item -mmnemonic=@var{att}
372 @itemx -mmnemonic=@var{intel}
373 This option specifies instruction mnemonic for matching instructions.
374 The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will
377 @cindex @samp{-msyntax=} option, i386
378 @cindex @samp{-msyntax=} option, x86-64
379 @item -msyntax=@var{att}
380 @itemx -msyntax=@var{intel}
381 This option specifies instruction syntax when processing instructions.
382 The @code{.att_syntax} and @code{.intel_syntax} directives will
385 @cindex @samp{-mnaked-reg} option, i386
386 @cindex @samp{-mnaked-reg} option, x86-64
388 This option specifies that registers don't require a @samp{%} prefix.
389 The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent.
391 @cindex @samp{-madd-bnd-prefix} option, i386
392 @cindex @samp{-madd-bnd-prefix} option, x86-64
393 @item -madd-bnd-prefix
394 This option forces the assembler to add BND prefix to all branches, even
395 if such prefix was not explicitly specified in the source code.
397 @cindex @samp{-mshared} option, i386
398 @cindex @samp{-mshared} option, x86-64
400 On ELF target, the assembler normally optimizes out non-PLT relocations
401 against defined non-weak global branch targets with default visibility.
402 The @samp{-mshared} option tells the assembler to generate code which
403 may go into a shared library where all non-weak global branch targets
404 with default visibility can be preempted. The resulting code is
405 slightly bigger. This option only affects the handling of branch
408 @cindex @samp{-mbig-obj} option, i386
409 @cindex @samp{-mbig-obj} option, x86-64
411 On PE/COFF target this option forces the use of big object file
412 format, which allows more than 32768 sections.
414 @cindex @samp{-momit-lock-prefix=} option, i386
415 @cindex @samp{-momit-lock-prefix=} option, x86-64
416 @item -momit-lock-prefix=@var{no}
417 @itemx -momit-lock-prefix=@var{yes}
418 These options control how the assembler should encode lock prefix.
419 This option is intended as a workaround for processors, that fail on
420 lock prefix. This option can only be safely used with single-core,
421 single-thread computers
422 @option{-momit-lock-prefix=@var{yes}} will omit all lock prefixes.
423 @option{-momit-lock-prefix=@var{no}} will encode lock prefix as usual,
424 which is the default.
426 @cindex @samp{-mfence-as-lock-add=} option, i386
427 @cindex @samp{-mfence-as-lock-add=} option, x86-64
428 @item -mfence-as-lock-add=@var{no}
429 @itemx -mfence-as-lock-add=@var{yes}
430 These options control how the assembler should encode lfence, mfence and
432 @option{-mfence-as-lock-add=@var{yes}} will encode lfence, mfence and
433 sfence as @samp{lock addl $0x0, (%rsp)} in 64-bit mode and
434 @samp{lock addl $0x0, (%esp)} in 32-bit mode.
435 @option{-mfence-as-lock-add=@var{no}} will encode lfence, mfence and
436 sfence as usual, which is the default.
438 @cindex @samp{-mrelax-relocations=} option, i386
439 @cindex @samp{-mrelax-relocations=} option, x86-64
440 @item -mrelax-relocations=@var{no}
441 @itemx -mrelax-relocations=@var{yes}
442 These options control whether the assembler should generate relax
443 relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX and
444 R_X86_64_REX_GOTPCRELX, in 64-bit mode.
445 @option{-mrelax-relocations=@var{yes}} will generate relax relocations.
446 @option{-mrelax-relocations=@var{no}} will not generate relax
447 relocations. The default can be controlled by a configure option
448 @option{--enable-x86-relax-relocations}.
450 @cindex @samp{-malign-branch-boundary=} option, i386
451 @cindex @samp{-malign-branch-boundary=} option, x86-64
452 @item -malign-branch-boundary=@var{NUM}
453 This option controls how the assembler should align branches with segment
454 prefixes or NOP. @var{NUM} must be a power of 2. It should be 0 or
455 no less than 16. Branches will be aligned within @var{NUM} byte
456 boundary. @option{-malign-branch-boundary=0}, which is the default,
457 doesn't align branches.
459 @cindex @samp{-malign-branch=} option, i386
460 @cindex @samp{-malign-branch=} option, x86-64
461 @item -malign-branch=@var{TYPE}[+@var{TYPE}...]
462 This option specifies types of branches to align. @var{TYPE} is
463 combination of @samp{jcc}, which aligns conditional jumps,
464 @samp{fused}, which aligns fused conditional jumps, @samp{jmp},
465 which aligns unconditional jumps, @samp{call} which aligns calls,
466 @samp{ret}, which aligns rets, @samp{indirect}, which aligns indirect
467 jumps and calls. The default is @option{-malign-branch=jcc+fused+jmp}.
469 @cindex @samp{-malign-branch-prefix-size=} option, i386
470 @cindex @samp{-malign-branch-prefix-size=} option, x86-64
471 @item -malign-branch-prefix-size=@var{NUM}
472 This option specifies the maximum number of prefixes on an instruction
473 to align branches. @var{NUM} should be between 0 and 5. The default
476 @cindex @samp{-mbranches-within-32B-boundaries} option, i386
477 @cindex @samp{-mbranches-within-32B-boundaries} option, x86-64
478 @item -mbranches-within-32B-boundaries
479 This option aligns conditional jumps, fused conditional jumps and
480 unconditional jumps within 32 byte boundary with up to 5 segment prefixes
481 on an instruction. It is equivalent to
482 @option{-malign-branch-boundary=32}
483 @option{-malign-branch=jcc+fused+jmp}
484 @option{-malign-branch-prefix-size=5}.
485 The default doesn't align branches.
487 @cindex @samp{-mlfence-after-load=} option, i386
488 @cindex @samp{-mlfence-after-load=} option, x86-64
489 @item -mlfence-after-load=@var{no}
490 @itemx -mlfence-after-load=@var{yes}
491 These options control whether the assembler should generate lfence
492 after load instructions. @option{-mlfence-after-load=@var{yes}} will
493 generate lfence. @option{-mlfence-after-load=@var{no}} will not generate
494 lfence, which is the default.
496 @cindex @samp{-mlfence-before-indirect-branch=} option, i386
497 @cindex @samp{-mlfence-before-indirect-branch=} option, x86-64
498 @item -mlfence-before-indirect-branch=@var{none}
499 @item -mlfence-before-indirect-branch=@var{all}
500 @item -mlfence-before-indirect-branch=@var{register}
501 @itemx -mlfence-before-indirect-branch=@var{memory}
502 These options control whether the assembler should generate lfence
503 before indirect near branch instructions.
504 @option{-mlfence-before-indirect-branch=@var{all}} will generate lfence
505 before indirect near branch via register and issue a warning before
506 indirect near branch via memory.
507 It also implicitly sets @option{-mlfence-before-ret=@var{shl}} when
508 there's no explict @option{-mlfence-before-ret=}.
509 @option{-mlfence-before-indirect-branch=@var{register}} will generate
510 lfence before indirect near branch via register.
511 @option{-mlfence-before-indirect-branch=@var{memory}} will issue a
512 warning before indirect near branch via memory.
513 @option{-mlfence-before-indirect-branch=@var{none}} will not generate
514 lfence nor issue warning, which is the default. Note that lfence won't
515 be generated before indirect near branch via register with
516 @option{-mlfence-after-load=@var{yes}} since lfence will be generated
517 after loading branch target register.
519 @cindex @samp{-mlfence-before-ret=} option, i386
520 @cindex @samp{-mlfence-before-ret=} option, x86-64
521 @item -mlfence-before-ret=@var{none}
522 @item -mlfence-before-ret=@var{shl}
523 @item -mlfence-before-ret=@var{or}
524 @item -mlfence-before-ret=@var{yes}
525 @itemx -mlfence-before-ret=@var{not}
526 These options control whether the assembler should generate lfence
527 before ret. @option{-mlfence-before-ret=@var{or}} will generate
528 generate or instruction with lfence.
529 @option{-mlfence-before-ret=@var{shl/yes}} will generate shl instruction
530 with lfence. @option{-mlfence-before-ret=@var{not}} will generate not
531 instruction with lfence. @option{-mlfence-before-ret=@var{none}} will not
532 generate lfence, which is the default.
534 @cindex @samp{-mx86-used-note=} option, i386
535 @cindex @samp{-mx86-used-note=} option, x86-64
536 @item -mx86-used-note=@var{no}
537 @itemx -mx86-used-note=@var{yes}
538 These options control whether the assembler should generate
539 GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_FEATURE_2_USED
540 GNU property notes. The default can be controlled by the
541 @option{--enable-x86-used-note} configure option.
543 @cindex @samp{-mevexrcig=} option, i386
544 @cindex @samp{-mevexrcig=} option, x86-64
545 @item -mevexrcig=@var{rne}
546 @itemx -mevexrcig=@var{rd}
547 @itemx -mevexrcig=@var{ru}
548 @itemx -mevexrcig=@var{rz}
549 These options control how the assembler should encode SAE-only
550 EVEX instructions. @option{-mevexrcig=@var{rne}} will encode RC bits
551 of EVEX instruction with 00, which is the default.
552 @option{-mevexrcig=@var{rd}}, @option{-mevexrcig=@var{ru}}
553 and @option{-mevexrcig=@var{rz}} will encode SAE-only EVEX instructions
554 with 01, 10 and 11 RC bits, respectively.
556 @cindex @samp{-mamd64} option, x86-64
557 @cindex @samp{-mintel64} option, x86-64
560 This option specifies that the assembler should accept only AMD64 or
561 Intel64 ISA in 64-bit mode. The default is to accept common, Intel64
564 @cindex @samp{-O0} option, i386
565 @cindex @samp{-O0} option, x86-64
566 @cindex @samp{-O} option, i386
567 @cindex @samp{-O} option, x86-64
568 @cindex @samp{-O1} option, i386
569 @cindex @samp{-O1} option, x86-64
570 @cindex @samp{-O2} option, i386
571 @cindex @samp{-O2} option, x86-64
572 @cindex @samp{-Os} option, i386
573 @cindex @samp{-Os} option, x86-64
574 @item -O0 | -O | -O1 | -O2 | -Os
575 Optimize instruction encoding with smaller instruction size. @samp{-O}
576 and @samp{-O1} encode 64-bit register load instructions with 64-bit
577 immediate as 32-bit register load instructions with 31-bit or 32-bits
578 immediates, encode 64-bit register clearing instructions with 32-bit
579 register clearing instructions, encode 256-bit/512-bit VEX/EVEX vector
580 register clearing instructions with 128-bit VEX vector register
581 clearing instructions, encode 128-bit/256-bit EVEX vector
582 register load/store instructions with VEX vector register load/store
583 instructions, and encode 128-bit/256-bit EVEX packed integer logical
584 instructions with 128-bit/256-bit VEX packed integer logical.
586 @samp{-O2} includes @samp{-O1} optimization plus encodes
587 256-bit/512-bit EVEX vector register clearing instructions with 128-bit
588 EVEX vector register clearing instructions. In 64-bit mode VEX encoded
589 instructions with commutative source operands will also have their
590 source operands swapped if this allows using the 2-byte VEX prefix form
591 instead of the 3-byte one. Certain forms of AND as well as OR with the
592 same (register) operand specified twice will also be changed to TEST.
594 @samp{-Os} includes @samp{-O2} optimization plus encodes 16-bit, 32-bit
595 and 64-bit register tests with immediate as 8-bit register test with
596 immediate. @samp{-O0} turns off this optimization.
601 @node i386-Directives
602 @section x86 specific Directives
604 @cindex machine directives, x86
605 @cindex x86 machine directives
608 @cindex @code{lcomm} directive, COFF
609 @item .lcomm @var{symbol} , @var{length}[, @var{alignment}]
610 Reserve @var{length} (an absolute expression) bytes for a local common
611 denoted by @var{symbol}. The section and value of @var{symbol} are
612 those of the new local common. The addresses are allocated in the bss
613 section, so that at run-time the bytes start off zeroed. Since
614 @var{symbol} is not declared global, it is normally not visible to
615 @code{@value{LD}}. The optional third parameter, @var{alignment},
616 specifies the desired alignment of the symbol in the bss section.
618 This directive is only available for COFF based x86 targets.
620 @cindex @code{largecomm} directive, ELF
621 @item .largecomm @var{symbol} , @var{length}[, @var{alignment}]
622 This directive behaves in the same way as the @code{comm} directive
623 except that the data is placed into the @var{.lbss} section instead of
624 the @var{.bss} section @ref{Comm}.
626 The directive is intended to be used for data which requires a large
627 amount of space, and it is only available for ELF based x86_64
630 @cindex @code{value} directive
631 @item .value @var{expression} [, @var{expression}]
632 This directive behaves in the same way as the @code{.short} directive,
633 taking a series of comma separated expressions and storing them as
634 two-byte wide values into the current section.
636 @c FIXME: Document other x86 specific directives ? Eg: .code16gcc,
641 @section i386 Syntactical Considerations
643 * i386-Variations:: AT&T Syntax versus Intel Syntax
644 * i386-Chars:: Special Characters
647 @node i386-Variations
648 @subsection AT&T Syntax versus Intel Syntax
650 @cindex i386 intel_syntax pseudo op
651 @cindex intel_syntax pseudo op, i386
652 @cindex i386 att_syntax pseudo op
653 @cindex att_syntax pseudo op, i386
654 @cindex i386 syntax compatibility
655 @cindex syntax compatibility, i386
656 @cindex x86-64 intel_syntax pseudo op
657 @cindex intel_syntax pseudo op, x86-64
658 @cindex x86-64 att_syntax pseudo op
659 @cindex att_syntax pseudo op, x86-64
660 @cindex x86-64 syntax compatibility
661 @cindex syntax compatibility, x86-64
663 @code{@value{AS}} now supports assembly using Intel assembler syntax.
664 @code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches
665 back to the usual AT&T mode for compatibility with the output of
666 @code{@value{GCC}}. Either of these directives may have an optional
667 argument, @code{prefix}, or @code{noprefix} specifying whether registers
668 require a @samp{%} prefix. AT&T System V/386 assembler syntax is quite
669 different from Intel syntax. We mention these differences because
670 almost all 80386 documents use Intel syntax. Notable differences
671 between the two syntaxes are:
673 @cindex immediate operands, i386
674 @cindex i386 immediate operands
675 @cindex register operands, i386
676 @cindex i386 register operands
677 @cindex jump/call operands, i386
678 @cindex i386 jump/call operands
679 @cindex operand delimiters, i386
681 @cindex immediate operands, x86-64
682 @cindex x86-64 immediate operands
683 @cindex register operands, x86-64
684 @cindex x86-64 register operands
685 @cindex jump/call operands, x86-64
686 @cindex x86-64 jump/call operands
687 @cindex operand delimiters, x86-64
690 AT&T immediate operands are preceded by @samp{$}; Intel immediate
691 operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}).
692 AT&T register operands are preceded by @samp{%}; Intel register operands
693 are undelimited. AT&T absolute (as opposed to PC relative) jump/call
694 operands are prefixed by @samp{*}; they are undelimited in Intel syntax.
696 @cindex i386 source, destination operands
697 @cindex source, destination operands; i386
698 @cindex x86-64 source, destination operands
699 @cindex source, destination operands; x86-64
701 AT&T and Intel syntax use the opposite order for source and destination
702 operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The
703 @samp{source, dest} convention is maintained for compatibility with
704 previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and
705 instructions with 2 immediate operands, such as the @samp{enter}
706 instruction, do @emph{not} have reversed order. @ref{i386-Bugs}.
708 @cindex mnemonic suffixes, i386
709 @cindex sizes operands, i386
710 @cindex i386 size suffixes
711 @cindex mnemonic suffixes, x86-64
712 @cindex sizes operands, x86-64
713 @cindex x86-64 size suffixes
715 In AT&T syntax the size of memory operands is determined from the last
716 character of the instruction mnemonic. Mnemonic suffixes of @samp{b},
717 @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long
718 (32-bit) and quadruple word (64-bit) memory references. Mnemonic suffixes
719 of @samp{x}, @samp{y} and @samp{z} specify xmm (128-bit vector), ymm
720 (256-bit vector) and zmm (512-bit vector) memory references, only when there's
721 no other way to disambiguate an instruction. Intel syntax accomplishes this by
722 prefixing memory operands (@emph{not} the instruction mnemonics) with
723 @samp{byte ptr}, @samp{word ptr}, @samp{dword ptr}, @samp{qword ptr},
724 @samp{xmmword ptr}, @samp{ymmword ptr} and @samp{zmmword ptr}. Thus, Intel
725 syntax @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
726 syntax. In Intel syntax, @samp{fword ptr}, @samp{tbyte ptr} and
727 @samp{oword ptr} specify 48-bit, 80-bit and 128-bit memory references.
729 In 64-bit code, @samp{movabs} can be used to encode the @samp{mov}
730 instruction with the 64-bit displacement or immediate operand.
732 @cindex return instructions, i386
733 @cindex i386 jump, call, return
734 @cindex return instructions, x86-64
735 @cindex x86-64 jump, call, return
737 Immediate form long jumps and calls are
738 @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
740 @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return
742 is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
743 @samp{ret far @var{stack-adjust}}.
745 @cindex sections, i386
746 @cindex i386 sections
747 @cindex sections, x86-64
748 @cindex x86-64 sections
750 The AT&T assembler does not provide support for multiple section
751 programs. Unix style systems expect all programs to be single sections.
755 @subsection Special Characters
757 @cindex line comment character, i386
758 @cindex i386 line comment character
759 The presence of a @samp{#} appearing anywhere on a line indicates the
760 start of a comment that extends to the end of that line.
762 If a @samp{#} appears as the first character of a line then the whole
763 line is treated as a comment, but in this case the line can also be a
764 logical line number directive (@pxref{Comments}) or a preprocessor
765 control command (@pxref{Preprocessing}).
767 If the @option{--divide} command-line option has not been specified
768 then the @samp{/} character appearing anywhere on a line also
769 introduces a line comment.
771 @cindex line separator, i386
772 @cindex statement separator, i386
773 @cindex i386 line separator
774 The @samp{;} character can be used to separate statements on the same
778 @section i386-Mnemonics
779 @subsection Instruction Naming
781 @cindex i386 instruction naming
782 @cindex instruction naming, i386
783 @cindex x86-64 instruction naming
784 @cindex instruction naming, x86-64
786 Instruction mnemonics are suffixed with one character modifiers which
787 specify the size of operands. The letters @samp{b}, @samp{w}, @samp{l}
788 and @samp{q} specify byte, word, long and quadruple word operands. If
789 no suffix is specified by an instruction then @code{@value{AS}} tries to
790 fill in the missing suffix based on the destination register operand
791 (the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent
792 to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to
793 @samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix
794 assembler which assumes that a missing mnemonic suffix implies long
795 operand size. (This incompatibility does not affect compiler output
796 since compilers always explicitly specify the mnemonic suffix.)
798 When there is no sizing suffix and no (suitable) register operands to
799 deduce the size of memory operands, with a few exceptions and where long
800 operand size is possible in the first place, operand size will default
801 to long in 32- and 64-bit modes. Similarly it will default to short in
802 16-bit mode. Noteworthy exceptions are
806 Instructions with an implicit on-stack operand as well as branches,
807 which default to quad in 64-bit mode.
810 Sign- and zero-extending moves, which default to byte size source
814 Floating point insns with integer operands, which default to short (for
815 perhaps historical reasons).
818 CRC32 with a 64-bit destination, which defaults to a quad source
823 @cindex encoding options, i386
824 @cindex encoding options, x86-64
826 Different encoding options can be specified via pseudo prefixes:
830 @samp{@{disp8@}} -- prefer 8-bit displacement.
833 @samp{@{disp32@}} -- prefer 32-bit displacement.
836 @samp{@{disp16@}} -- prefer 16-bit displacement.
839 @samp{@{load@}} -- prefer load-form instruction.
842 @samp{@{store@}} -- prefer store-form instruction.
845 @samp{@{vex@}} -- encode with VEX prefix.
848 @samp{@{vex3@}} -- encode with 3-byte VEX prefix.
851 @samp{@{evex@}} -- encode with EVEX prefix.
854 @samp{@{rex@}} -- prefer REX prefix for integer and legacy vector
855 instructions (x86-64 only). Note that this differs from the @samp{rex}
856 prefix which generates REX prefix unconditionally.
859 @samp{@{nooptimize@}} -- disable instruction size optimization.
862 @cindex conversion instructions, i386
863 @cindex i386 conversion instructions
864 @cindex conversion instructions, x86-64
865 @cindex x86-64 conversion instructions
866 The Intel-syntax conversion instructions
870 @samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax},
873 @samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax},
876 @samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax},
879 @samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax},
882 @samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax}
886 @samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in
887 @samp{%rdx:%rax} (x86-64 only),
891 are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and
892 @samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these
895 @cindex extension instructions, i386
896 @cindex i386 extension instructions
897 @cindex extension instructions, x86-64
898 @cindex x86-64 extension instructions
899 The Intel-syntax extension instructions
903 @samp{movsx} --- sign-extend @samp{reg8/mem8} to @samp{reg16}.
906 @samp{movsx} --- sign-extend @samp{reg8/mem8} to @samp{reg32}.
909 @samp{movsx} --- sign-extend @samp{reg8/mem8} to @samp{reg64}
913 @samp{movsx} --- sign-extend @samp{reg16/mem16} to @samp{reg32}
916 @samp{movsx} --- sign-extend @samp{reg16/mem16} to @samp{reg64}
920 @samp{movsxd} --- sign-extend @samp{reg32/mem32} to @samp{reg64}
924 @samp{movzx} --- zero-extend @samp{reg8/mem8} to @samp{reg16}.
927 @samp{movzx} --- zero-extend @samp{reg8/mem8} to @samp{reg32}.
930 @samp{movzx} --- zero-extend @samp{reg8/mem8} to @samp{reg64}
934 @samp{movzx} --- zero-extend @samp{reg16/mem16} to @samp{reg32}
937 @samp{movzx} --- zero-extend @samp{reg16/mem16} to @samp{reg64}
942 are called @samp{movsbw/movsxb/movsx}, @samp{movsbl/movsxb/movsx},
943 @samp{movsbq/movsb/movsx}, @samp{movswl/movsxw}, @samp{movswq/movsxw},
944 @samp{movslq/movsxl}, @samp{movzbw/movzxb/movzx},
945 @samp{movzbl/movzxb/movzx}, @samp{movzbq/movzxb/movzx},
946 @samp{movzwl/movzxw} and @samp{movzwq/movzxw} in AT&T syntax.
948 @cindex jump instructions, i386
949 @cindex call instructions, i386
950 @cindex jump instructions, x86-64
951 @cindex call instructions, x86-64
952 Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
953 AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
956 @subsection AT&T Mnemonic versus Intel Mnemonic
958 @cindex i386 mnemonic compatibility
959 @cindex mnemonic compatibility, i386
961 @code{@value{AS}} supports assembly using Intel mnemonic.
962 @code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and
963 @code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T
964 syntax for compatibility with the output of @code{@value{GCC}}.
965 Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp},
966 @samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp},
967 @samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386
968 assembler with different mnemonics from those in Intel IA32 specification.
969 @code{@value{GCC}} generates those instructions with AT&T mnemonic.
972 @item @samp{movslq} with AT&T mnemonic only accepts 64-bit destination
973 register. @samp{movsxd} should be used to encode 16-bit or 32-bit
974 destination register with both AT&T and Intel mnemonics.
978 @section Register Naming
980 @cindex i386 registers
981 @cindex registers, i386
982 @cindex x86-64 registers
983 @cindex registers, x86-64
984 Register operands are always prefixed with @samp{%}. The 80386 registers
989 the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx},
990 @samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the
991 frame pointer), and @samp{%esp} (the stack pointer).
994 the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx},
995 @samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}.
998 the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh},
999 @samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These
1000 are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx},
1001 @samp{%cx}, and @samp{%dx})
1004 the 6 section registers @samp{%cs} (code section), @samp{%ds}
1005 (data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs},
1009 the 5 processor control registers @samp{%cr0}, @samp{%cr2},
1010 @samp{%cr3}, @samp{%cr4}, and @samp{%cr8}.
1013 the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2},
1014 @samp{%db3}, @samp{%db6}, and @samp{%db7}.
1017 the 2 test registers @samp{%tr6} and @samp{%tr7}.
1020 the 8 floating point register stack @samp{%st} or equivalently
1021 @samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)},
1022 @samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}.
1023 These registers are overloaded by 8 MMX registers @samp{%mm0},
1024 @samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5},
1025 @samp{%mm6} and @samp{%mm7}.
1028 the 8 128-bit SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2},
1029 @samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}.
1032 The AMD x86-64 architecture extends the register set by:
1036 enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the
1037 accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi},
1038 @samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack
1042 the 8 extended registers @samp{%r8}--@samp{%r15}.
1045 the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}.
1048 the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}.
1051 the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}.
1054 the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}.
1057 the 8 debug registers: @samp{%db8}--@samp{%db15}.
1060 the 8 128-bit SSE registers: @samp{%xmm8}--@samp{%xmm15}.
1063 With the AVX extensions more registers were made available:
1068 the 16 256-bit SSE @samp{%ymm0}--@samp{%ymm15} (only the first 8
1069 available in 32-bit mode). The bottom 128 bits are overlaid with the
1070 @samp{xmm0}--@samp{xmm15} registers.
1074 The AVX512 extensions added the following registers:
1079 the 32 512-bit registers @samp{%zmm0}--@samp{%zmm31} (only the first 8
1080 available in 32-bit mode). The bottom 128 bits are overlaid with the
1081 @samp{%xmm0}--@samp{%xmm31} registers and the first 256 bits are
1082 overlaid with the @samp{%ymm0}--@samp{%ymm31} registers.
1085 the 8 mask registers @samp{%k0}--@samp{%k7}.
1090 @section Instruction Prefixes
1092 @cindex i386 instruction prefixes
1093 @cindex instruction prefixes, i386
1094 @cindex prefixes, i386
1095 Instruction prefixes are used to modify the following instruction. They
1096 are used to repeat string instructions, to provide section overrides, to
1097 perform bus lock operations, and to change operand and address sizes.
1098 (Most instructions that normally operate on 32-bit operands will use
1099 16-bit operands if the instruction has an ``operand size'' prefix.)
1100 Instruction prefixes are best written on the same line as the instruction
1101 they act upon. For example, the @samp{scas} (scan string) instruction is
1105 repne scas %es:(%edi),%al
1108 You may also place prefixes on the lines immediately preceding the
1109 instruction, but this circumvents checks that @code{@value{AS}} does
1110 with prefixes, and will not work with all prefixes.
1112 Here is a list of instruction prefixes:
1114 @cindex section override prefixes, i386
1117 Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es},
1118 @samp{fs}, @samp{gs}. These are automatically added by specifying
1119 using the @var{section}:@var{memory-operand} form for memory references.
1121 @cindex size prefixes, i386
1123 Operand/Address size prefixes @samp{data16} and @samp{addr16}
1124 change 32-bit operands/addresses into 16-bit operands/addresses,
1125 while @samp{data32} and @samp{addr32} change 16-bit ones (in a
1126 @code{.code16} section) into 32-bit operands/addresses. These prefixes
1127 @emph{must} appear on the same line of code as the instruction they
1128 modify. For example, in a 16-bit @code{.code16} section, you might
1135 @cindex bus lock prefixes, i386
1136 @cindex inhibiting interrupts, i386
1138 The bus lock prefix @samp{lock} inhibits interrupts during execution of
1139 the instruction it precedes. (This is only valid with certain
1140 instructions; see a 80386 manual for details).
1142 @cindex coprocessor wait, i386
1144 The wait for coprocessor prefix @samp{wait} waits for the coprocessor to
1145 complete the current instruction. This should never be needed for the
1146 80386/80387 combination.
1148 @cindex repeat prefixes, i386
1150 The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added
1151 to string instructions to make them repeat @samp{%ecx} times (@samp{%cx}
1152 times if the current address size is 16-bits).
1153 @cindex REX prefixes, i386
1155 The @samp{rex} family of prefixes is used by x86-64 to encode
1156 extensions to i386 instruction set. The @samp{rex} prefix has four
1157 bits --- an operand size overwrite (@code{64}) used to change operand size
1158 from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the
1161 You may write the @samp{rex} prefixes directly. The @samp{rex64xyz}
1162 instruction emits @samp{rex} prefix with all the bits set. By omitting
1163 the @code{64}, @code{x}, @code{y} or @code{z} you may write other
1164 prefixes as well. Normally, there is no need to write the prefixes
1165 explicitly, since gas will automatically generate them based on the
1166 instruction operands.
1170 @section Memory References
1172 @cindex i386 memory references
1173 @cindex memory references, i386
1174 @cindex x86-64 memory references
1175 @cindex memory references, x86-64
1176 An Intel syntax indirect memory reference of the form
1179 @var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}]
1183 is translated into the AT&T syntax
1186 @var{section}:@var{disp}(@var{base}, @var{index}, @var{scale})
1190 where @var{base} and @var{index} are the optional 32-bit base and
1191 index registers, @var{disp} is the optional displacement, and
1192 @var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index}
1193 to calculate the address of the operand. If no @var{scale} is
1194 specified, @var{scale} is taken to be 1. @var{section} specifies the
1195 optional section register for the memory operand, and may override the
1196 default section register (see a 80386 manual for section register
1197 defaults). Note that section overrides in AT&T syntax @emph{must}
1198 be preceded by a @samp{%}. If you specify a section override which
1199 coincides with the default section register, @code{@value{AS}} does @emph{not}
1200 output any section register override prefixes to assemble the given
1201 instruction. Thus, section overrides can be specified to emphasize which
1202 section register is used for a given memory operand.
1204 Here are some examples of Intel and AT&T style memory references:
1207 @item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]}
1208 @var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is
1209 missing, and the default section is used (@samp{%ss} for addressing with
1210 @samp{%ebp} as the base register). @var{index}, @var{scale} are both missing.
1212 @item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]}
1213 @var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is
1214 @samp{foo}. All other fields are missing. The section register here
1215 defaults to @samp{%ds}.
1217 @item AT&T: @samp{foo(,1)}; Intel @samp{[foo]}
1218 This uses the value pointed to by @samp{foo} as a memory operand.
1219 Note that @var{base} and @var{index} are both missing, but there is only
1220 @emph{one} @samp{,}. This is a syntactic exception.
1222 @item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo}
1223 This selects the contents of the variable @samp{foo} with section
1224 register @var{section} being @samp{%gs}.
1227 Absolute (as opposed to PC relative) call and jump operands must be
1228 prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}}
1229 always chooses PC relative addressing for jump/call labels.
1231 Any instruction that has a memory operand, but no register operand,
1232 @emph{must} specify its size (byte, word, long, or quadruple) with an
1233 instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q},
1236 The x86-64 architecture adds an RIP (instruction pointer relative)
1237 addressing. This addressing mode is specified by using @samp{rip} as a
1238 base register. Only constant offsets are valid. For example:
1241 @item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]}
1242 Points to the address 1234 bytes past the end of the current
1245 @item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]}
1246 Points to the @code{symbol} in RIP relative way, this is shorter than
1247 the default absolute addressing.
1250 Other addressing modes remain unchanged in x86-64 architecture, except
1251 registers used are 64-bit instead of 32-bit.
1254 @section Handling of Jump Instructions
1256 @cindex jump optimization, i386
1257 @cindex i386 jump optimization
1258 @cindex jump optimization, x86-64
1259 @cindex x86-64 jump optimization
1260 Jump instructions are always optimized to use the smallest possible
1261 displacements. This is accomplished by using byte (8-bit) displacement
1262 jumps whenever the target is sufficiently close. If a byte displacement
1263 is insufficient a long displacement is used. We do not support
1264 word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
1265 instruction with the @samp{data16} instruction prefix), since the 80386
1266 insists upon masking @samp{%eip} to 16 bits after the word displacement
1267 is added. (See also @pxref{i386-Arch})
1269 Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz},
1270 @samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte
1271 displacements, so that if you use these instructions (@code{@value{GCC}} does
1272 not use them) you may get an error message (and incorrect code). The AT&T
1273 80386 assembler tries to get around this problem by expanding @samp{jcxz foo}
1284 @section Floating Point
1286 @cindex i386 floating point
1287 @cindex floating point, i386
1288 @cindex x86-64 floating point
1289 @cindex floating point, x86-64
1290 All 80387 floating point types except packed BCD are supported.
1291 (BCD support may be added without much difficulty). These data
1292 types are 16-, 32-, and 64- bit integers, and single (32-bit),
1293 double (64-bit), and extended (80-bit) precision floating point.
1294 Each supported type has an instruction mnemonic suffix and a constructor
1295 associated with it. Instruction mnemonic suffixes specify the operand's
1296 data type. Constructors build these data types into memory.
1298 @cindex @code{float} directive, i386
1299 @cindex @code{single} directive, i386
1300 @cindex @code{double} directive, i386
1301 @cindex @code{tfloat} directive, i386
1302 @cindex @code{float} directive, x86-64
1303 @cindex @code{single} directive, x86-64
1304 @cindex @code{double} directive, x86-64
1305 @cindex @code{tfloat} directive, x86-64
1308 Floating point constructors are @samp{.float} or @samp{.single},
1309 @samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats.
1310 These correspond to instruction mnemonic suffixes @samp{s}, @samp{l},
1311 and @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387
1312 only supports this format via the @samp{fldt} (load 80-bit real to stack
1313 top) and @samp{fstpt} (store 80-bit real and pop stack) instructions.
1315 @cindex @code{word} directive, i386
1316 @cindex @code{long} directive, i386
1317 @cindex @code{int} directive, i386
1318 @cindex @code{quad} directive, i386
1319 @cindex @code{word} directive, x86-64
1320 @cindex @code{long} directive, x86-64
1321 @cindex @code{int} directive, x86-64
1322 @cindex @code{quad} directive, x86-64
1324 Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and
1325 @samp{.quad} for the 16-, 32-, and 64-bit integer formats. The
1326 corresponding instruction mnemonic suffixes are @samp{s} (single),
1327 @samp{l} (long), and @samp{q} (quad). As with the 80-bit real format,
1328 the 64-bit @samp{q} format is only present in the @samp{fildq} (load
1329 quad integer to stack top) and @samp{fistpq} (store quad integer and pop
1330 stack) instructions.
1333 Register to register operations should not use instruction mnemonic suffixes.
1334 @samp{fstl %st, %st(1)} will give a warning, and be assembled as if you
1335 wrote @samp{fst %st, %st(1)}, since all register to register operations
1336 use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem},
1337 which converts @samp{%st} from 80-bit to 64-bit floating point format,
1338 then stores the result in the 4 byte location @samp{mem})
1341 @section Intel's MMX and AMD's 3DNow! SIMD Operations
1344 @cindex 3DNow!, i386
1347 @cindex 3DNow!, x86-64
1348 @cindex SIMD, x86-64
1350 @code{@value{AS}} supports Intel's MMX instruction set (SIMD
1351 instructions for integer data), available on Intel's Pentium MMX
1352 processors and Pentium II processors, AMD's K6 and K6-2 processors,
1353 Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@:
1354 instruction set (SIMD instructions for 32-bit floating point data)
1355 available on AMD's K6-2 processor and possibly others in the future.
1357 Currently, @code{@value{AS}} does not support Intel's floating point
1360 The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0},
1361 @samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four
1362 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
1363 floating point values. The MMX registers cannot be used at the same time
1364 as the floating point stack.
1366 See Intel and AMD documentation, keeping in mind that the operand order in
1367 instructions is reversed from the Intel syntax.
1370 @section AMD's Lightweight Profiling Instructions
1375 @code{@value{AS}} supports AMD's Lightweight Profiling (LWP)
1376 instruction set, available on AMD's Family 15h (Orochi) processors.
1378 LWP enables applications to collect and manage performance data, and
1379 react to performance events. The collection of performance data
1380 requires no context switches. LWP runs in the context of a thread and
1381 so several counters can be used independently across multiple threads.
1382 LWP can be used in both 64-bit and legacy 32-bit modes.
1384 For detailed information on the LWP instruction set, see the
1385 @cite{AMD Lightweight Profiling Specification} available at
1386 @uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}.
1389 @section Bit Manipulation Instructions
1394 @code{@value{AS}} supports the Bit Manipulation (BMI) instruction set.
1396 BMI instructions provide several instructions implementing individual
1397 bit manipulation operations such as isolation, masking, setting, or
1400 @c Need to add a specification citation here when available.
1403 @section AMD's Trailing Bit Manipulation Instructions
1408 @code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM)
1409 instruction set, available on AMD's BDVER2 processors (Trinity and
1412 TBM instructions provide instructions implementing individual bit
1413 manipulation operations such as isolating, masking, setting, resetting,
1414 complementing, and operations on trailing zeros and ones.
1416 @c Need to add a specification citation here when available.
1419 @section Writing 16-bit Code
1421 @cindex i386 16-bit code
1422 @cindex 16-bit code, i386
1423 @cindex real-mode code, i386
1424 @cindex @code{code16gcc} directive, i386
1425 @cindex @code{code16} directive, i386
1426 @cindex @code{code32} directive, i386
1427 @cindex @code{code64} directive, i386
1428 @cindex @code{code64} directive, x86-64
1429 While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code
1430 or 64-bit x86-64 code depending on the default configuration,
1431 it also supports writing code to run in real mode or in 16-bit protected
1432 mode code segments. To do this, put a @samp{.code16} or
1433 @samp{.code16gcc} directive before the assembly language instructions to
1434 be run in 16-bit mode. You can switch @code{@value{AS}} to writing
1435 32-bit code with the @samp{.code32} directive or 64-bit code with the
1436 @samp{.code64} directive.
1438 @samp{.code16gcc} provides experimental support for generating 16-bit
1439 code from gcc, and differs from @samp{.code16} in that @samp{call},
1440 @samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop},
1441 @samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions
1442 default to 32-bit size. This is so that the stack pointer is
1443 manipulated in the same way over function calls, allowing access to
1444 function parameters at the same stack offsets as in 32-bit mode.
1445 @samp{.code16gcc} also automatically adds address size prefixes where
1446 necessary to use the 32-bit addressing modes that gcc generates.
1448 The code which @code{@value{AS}} generates in 16-bit mode will not
1449 necessarily run on a 16-bit pre-80386 processor. To write code that
1450 runs on such a processor, you must refrain from using @emph{any} 32-bit
1451 constructs which require @code{@value{AS}} to output address or operand
1454 Note that writing 16-bit code instructions by explicitly specifying a
1455 prefix or an instruction mnemonic suffix within a 32-bit code section
1456 generates different machine instructions than those generated for a
1457 16-bit code segment. In a 32-bit code section, the following code
1458 generates the machine opcode bytes @samp{66 6a 04}, which pushes the
1459 value @samp{4} onto the stack, decrementing @samp{%esp} by 2.
1465 The same code in a 16-bit code section would generate the machine
1466 opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which
1467 is correct since the processor default operand size is assumed to be 16
1468 bits in a 16-bit code section.
1471 @section Specifying CPU Architecture
1473 @cindex arch directive, i386
1474 @cindex i386 arch directive
1475 @cindex arch directive, x86-64
1476 @cindex x86-64 arch directive
1478 @code{@value{AS}} may be told to assemble for a particular CPU
1479 (sub-)architecture with the @code{.arch @var{cpu_type}} directive. This
1480 directive enables a warning when gas detects an instruction that is not
1481 supported on the CPU specified. The choices for @var{cpu_type} are:
1483 @multitable @columnfractions .20 .20 .20 .20
1484 @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
1485 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
1486 @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
1487 @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
1488 @item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om} @tab @samp{iamcu}
1489 @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
1490 @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3}
1491 @item @samp{bdver4} @tab @samp{znver1} @tab @samp{znver2} @tab @samp{btver1}
1492 @item @samp{btver2} @tab @samp{generic32} @tab @samp{generic64}
1493 @item @samp{.cmov} @tab @samp{.fxsr} @tab @samp{.mmx}
1494 @item @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3} @tab @samp{.sse4a}
1495 @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
1496 @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept}
1497 @item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt}
1498 @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase}
1499 @item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2}
1500 @item @samp{.lzcnt} @tab @samp{.popcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc}
1502 @item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
1503 @item @samp{.smap} @tab @samp{.mpx} @tab @samp{.sha} @tab @samp{.prefetchwt1}
1504 @item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1}
1505 @item @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} @tab @samp{.avx512pf}
1506 @item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma}
1507 @item @samp{.avx512vbmi} @tab @samp{.avx512_4fmaps} @tab @samp{.avx512_4vnniw}
1508 @item @samp{.avx512_vpopcntdq} @tab @samp{.avx512_vbmi2} @tab @samp{.avx512_vnni}
1509 @item @samp{.avx512_bitalg} @tab @samp{.avx512_bf16} @tab @samp{.avx512_vp2intersect}
1511 @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @item @samp{.ibt}
1512 @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
1513 @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
1514 @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
1515 @item @samp{.amx_int8} @tab @samp{.amx_bf16} @tab @samp{.amx_tile}
1516 @item @samp{.kl} @tab @samp{.widekl} @tab @samp{.uintr}
1517 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
1518 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme}
1519 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
1520 @item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx} @tab @samp{.rdpru}
1521 @item @samp{.mcommit} @tab @samp{.sev_es}
1524 Apart from the warning, there are only two other effects on
1525 @code{@value{AS}} operation; Firstly, if you specify a CPU other than
1526 @samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax}
1527 will automatically use a two byte opcode sequence. The larger three
1528 byte opcode sequence is used on the 486 (and when no architecture is
1529 specified) because it executes faster on the 486. Note that you can
1530 explicitly request the two byte opcode by writing @samp{sarl %eax}.
1531 Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286},
1532 @emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset
1533 conditional jumps will be promoted when necessary to a two instruction
1534 sequence consisting of a conditional jump of the opposite sense around
1535 an unconditional jump to the target.
1537 Following the CPU architecture (but not a sub-architecture, which are those
1538 starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to
1539 control automatic promotion of conditional jumps. @samp{jumps} is the
1540 default, and enables jump promotion; All external jumps will be of the long
1541 variety, and file-local jumps will be promoted as necessary.
1542 (@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as
1543 byte offset jumps, and warns about file-local conditional jumps that
1544 @code{@value{AS}} promotes.
1545 Unconditional jumps are treated as for @samp{jumps}.
1554 @section AMD64 ISA vs. Intel64 ISA
1556 There are some discrepancies between AMD64 and Intel64 ISAs.
1559 @item For @samp{movsxd} with 16-bit destination register, AMD64
1560 supports 32-bit source operand and Intel64 supports 16-bit source
1563 @item For far branches (with explicit memory operand), both ISAs support
1564 32- and 16-bit operand size. Intel64 additionally supports 64-bit
1565 operand size, encoded as @samp{ljmpq} and @samp{lcallq} in AT&T syntax
1566 and with an explicit @samp{tbyte ptr} operand size specifier in Intel
1569 @item @samp{lfs}, @samp{lgs}, and @samp{lss} similarly allow for 16-
1570 and 32-bit operand size (32- and 48-bit memory operand) in both ISAs,
1571 while Intel64 additionally supports 64-bit operand sise (80-bit memory
1577 @section AT&T Syntax bugs
1579 The UnixWare assembler, and probably other AT&T derived ix86 Unix
1580 assemblers, generate floating point instructions with reversed source
1581 and destination registers in certain cases. Unfortunately, gcc and
1582 possibly many other programs use this reversed syntax, so we're stuck
1591 results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather
1592 than the expected @samp{%st(3) - %st}. This happens with all the
1593 non-commutative arithmetic floating point operations with two register
1594 operands where the source register is @samp{%st} and the destination
1595 register is @samp{%st(i)}.
1600 @cindex i386 @code{mul}, @code{imul} instructions
1601 @cindex @code{mul} instruction, i386
1602 @cindex @code{imul} instruction, i386
1603 @cindex @code{mul} instruction, x86-64
1604 @cindex @code{imul} instruction, x86-64
1605 There is some trickery concerning the @samp{mul} and @samp{imul}
1606 instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding
1607 multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5
1608 for @samp{imul}) can be output only in the one operand form. Thus,
1609 @samp{imul %ebx, %eax} does @emph{not} select the expanding multiply;
1610 the expanding multiply would clobber the @samp{%edx} register, and this
1611 would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the
1612 64-bit product in @samp{%edx:%eax}.
1614 We have added a two operand form of @samp{imul} when the first operand
1615 is an immediate mode expression and the second operand is a register.
1616 This is just a shorthand, so that, multiplying @samp{%eax} by 69, for
1617 example, can be done with @samp{imul $69, %eax} rather than @samp{imul