Symbols with octets value
[binutils-gdb.git] / gas / doc / c-i386.texi
1 @c Copyright (C) 1991-2019 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
4 @c man end
5
6 @ifset GENERIC
7 @page
8 @node i386-Dependent
9 @chapter 80386 Dependent Features
10 @end ifset
11 @ifclear GENERIC
12 @node Machine Dependencies
13 @chapter 80386 Dependent Features
14 @end ifclear
15
16 @cindex i386 support
17 @cindex i80386 support
18 @cindex x86-64 support
19
20 The i386 version @code{@value{AS}} supports both the original Intel 386
21 architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture
22 extending the Intel architecture to 64-bits.
23
24 @menu
25 * i386-Options:: Options
26 * i386-Directives:: X86 specific directives
27 * i386-Syntax:: Syntactical considerations
28 * i386-Mnemonics:: Instruction Naming
29 * i386-Regs:: Register Naming
30 * i386-Prefixes:: Instruction Prefixes
31 * i386-Memory:: Memory References
32 * i386-Jumps:: Handling of Jump Instructions
33 * i386-Float:: Floating Point
34 * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
35 * i386-LWP:: AMD's Lightweight Profiling Instructions
36 * i386-BMI:: Bit Manipulation Instruction
37 * i386-TBM:: AMD's Trailing Bit Manipulation Instructions
38 * i386-16bit:: Writing 16-bit Code
39 * i386-Arch:: Specifying an x86 CPU architecture
40 * i386-Bugs:: AT&T Syntax bugs
41 * i386-Notes:: Notes
42 @end menu
43
44 @node i386-Options
45 @section Options
46
47 @cindex options for i386
48 @cindex options for x86-64
49 @cindex i386 options
50 @cindex x86-64 options
51
52 The i386 version of @code{@value{AS}} has a few machine
53 dependent options:
54
55 @c man begin OPTIONS
56 @table @gcctabopt
57 @cindex @samp{--32} option, i386
58 @cindex @samp{--32} option, x86-64
59 @cindex @samp{--x32} option, i386
60 @cindex @samp{--x32} option, x86-64
61 @cindex @samp{--64} option, i386
62 @cindex @samp{--64} option, x86-64
63 @item --32 | --x32 | --64
64 Select the word size, either 32 bits or 64 bits. @samp{--32}
65 implies Intel i386 architecture, while @samp{--x32} and @samp{--64}
66 imply AMD x86-64 architecture with 32-bit or 64-bit word-size
67 respectively.
68
69 These options are only available with the ELF object file format, and
70 require that the necessary BFD support has been included (on a 32-bit
71 platform you have to add --enable-64-bit-bfd to configure enable 64-bit
72 usage and use x86-64 as target platform).
73
74 @item -n
75 By default, x86 GAS replaces multiple nop instructions used for
76 alignment within code sections with multi-byte nop instructions such
77 as leal 0(%esi,1),%esi. This switch disables the optimization if a single
78 byte nop (0x90) is explicitly specified as the fill byte for alignment.
79
80 @cindex @samp{--divide} option, i386
81 @item --divide
82 On SVR4-derived platforms, the character @samp{/} is treated as a comment
83 character, which means that it cannot be used in expressions. The
84 @samp{--divide} option turns @samp{/} into a normal character. This does
85 not disable @samp{/} at the beginning of a line starting a comment, or
86 affect using @samp{#} for starting a comment.
87
88 @cindex @samp{-march=} option, i386
89 @cindex @samp{-march=} option, x86-64
90 @item -march=@var{CPU}[+@var{EXTENSION}@dots{}]
91 This option specifies the target processor. The assembler will
92 issue an error message if an attempt is made to assemble an instruction
93 which will not execute on the target processor. The following
94 processor names are recognized:
95 @code{i8086},
96 @code{i186},
97 @code{i286},
98 @code{i386},
99 @code{i486},
100 @code{i586},
101 @code{i686},
102 @code{pentium},
103 @code{pentiumpro},
104 @code{pentiumii},
105 @code{pentiumiii},
106 @code{pentium4},
107 @code{prescott},
108 @code{nocona},
109 @code{core},
110 @code{core2},
111 @code{corei7},
112 @code{l1om},
113 @code{k1om},
114 @code{iamcu},
115 @code{k6},
116 @code{k6_2},
117 @code{athlon},
118 @code{opteron},
119 @code{k8},
120 @code{amdfam10},
121 @code{bdver1},
122 @code{bdver2},
123 @code{bdver3},
124 @code{bdver4},
125 @code{znver1},
126 @code{znver2},
127 @code{btver1},
128 @code{btver2},
129 @code{generic32} and
130 @code{generic64}.
131
132 In addition to the basic instruction set, the assembler can be told to
133 accept various extension mnemonics. For example,
134 @code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and
135 @var{vmx}. The following extensions are currently supported:
136 @code{8087},
137 @code{287},
138 @code{387},
139 @code{687},
140 @code{no87},
141 @code{no287},
142 @code{no387},
143 @code{no687},
144 @code{cmov},
145 @code{nocmov},
146 @code{fxsr},
147 @code{nofxsr},
148 @code{mmx},
149 @code{nommx},
150 @code{sse},
151 @code{sse2},
152 @code{sse3},
153 @code{ssse3},
154 @code{sse4.1},
155 @code{sse4.2},
156 @code{sse4},
157 @code{nosse},
158 @code{nosse2},
159 @code{nosse3},
160 @code{nossse3},
161 @code{nosse4.1},
162 @code{nosse4.2},
163 @code{nosse4},
164 @code{avx},
165 @code{avx2},
166 @code{noavx},
167 @code{noavx2},
168 @code{adx},
169 @code{rdseed},
170 @code{prfchw},
171 @code{smap},
172 @code{mpx},
173 @code{sha},
174 @code{rdpid},
175 @code{ptwrite},
176 @code{cet},
177 @code{gfni},
178 @code{vaes},
179 @code{vpclmulqdq},
180 @code{prefetchwt1},
181 @code{clflushopt},
182 @code{se1},
183 @code{clwb},
184 @code{movdiri},
185 @code{movdir64b},
186 @code{avx512f},
187 @code{avx512cd},
188 @code{avx512er},
189 @code{avx512pf},
190 @code{avx512vl},
191 @code{avx512bw},
192 @code{avx512dq},
193 @code{avx512ifma},
194 @code{avx512vbmi},
195 @code{avx512_4fmaps},
196 @code{avx512_4vnniw},
197 @code{avx512_vpopcntdq},
198 @code{avx512_vbmi2},
199 @code{avx512_vnni},
200 @code{avx512_bitalg},
201 @code{noavx512f},
202 @code{noavx512cd},
203 @code{noavx512er},
204 @code{noavx512pf},
205 @code{noavx512vl},
206 @code{noavx512bw},
207 @code{noavx512dq},
208 @code{noavx512ifma},
209 @code{noavx512vbmi},
210 @code{noavx512_4fmaps},
211 @code{noavx512_4vnniw},
212 @code{noavx512_vpopcntdq},
213 @code{noavx512_vbmi2},
214 @code{noavx512_vnni},
215 @code{noavx512_bitalg},
216 @code{vmx},
217 @code{vmfunc},
218 @code{smx},
219 @code{xsave},
220 @code{xsaveopt},
221 @code{xsavec},
222 @code{xsaves},
223 @code{aes},
224 @code{pclmul},
225 @code{fsgsbase},
226 @code{rdrnd},
227 @code{f16c},
228 @code{bmi2},
229 @code{fma},
230 @code{movbe},
231 @code{ept},
232 @code{lzcnt},
233 @code{hle},
234 @code{rtm},
235 @code{invpcid},
236 @code{clflush},
237 @code{mwaitx},
238 @code{clzero},
239 @code{wbnoinvd},
240 @code{pconfig},
241 @code{waitpkg},
242 @code{cldemote},
243 @code{lwp},
244 @code{fma4},
245 @code{xop},
246 @code{cx16},
247 @code{syscall},
248 @code{rdtscp},
249 @code{3dnow},
250 @code{3dnowa},
251 @code{sse4a},
252 @code{sse5},
253 @code{svme},
254 @code{abm} and
255 @code{padlock}.
256 Note that rather than extending a basic instruction set, the extension
257 mnemonics starting with @code{no} revoke the respective functionality.
258
259 When the @code{.arch} directive is used with @option{-march}, the
260 @code{.arch} directive will take precedent.
261
262 @cindex @samp{-mtune=} option, i386
263 @cindex @samp{-mtune=} option, x86-64
264 @item -mtune=@var{CPU}
265 This option specifies a processor to optimize for. When used in
266 conjunction with the @option{-march} option, only instructions
267 of the processor specified by the @option{-march} option will be
268 generated.
269
270 Valid @var{CPU} values are identical to the processor list of
271 @option{-march=@var{CPU}}.
272
273 @cindex @samp{-msse2avx} option, i386
274 @cindex @samp{-msse2avx} option, x86-64
275 @item -msse2avx
276 This option specifies that the assembler should encode SSE instructions
277 with VEX prefix.
278
279 @cindex @samp{-msse-check=} option, i386
280 @cindex @samp{-msse-check=} option, x86-64
281 @item -msse-check=@var{none}
282 @itemx -msse-check=@var{warning}
283 @itemx -msse-check=@var{error}
284 These options control if the assembler should check SSE instructions.
285 @option{-msse-check=@var{none}} will make the assembler not to check SSE
286 instructions, which is the default. @option{-msse-check=@var{warning}}
287 will make the assembler issue a warning for any SSE instruction.
288 @option{-msse-check=@var{error}} will make the assembler issue an error
289 for any SSE instruction.
290
291 @cindex @samp{-mavxscalar=} option, i386
292 @cindex @samp{-mavxscalar=} option, x86-64
293 @item -mavxscalar=@var{128}
294 @itemx -mavxscalar=@var{256}
295 These options control how the assembler should encode scalar AVX
296 instructions. @option{-mavxscalar=@var{128}} will encode scalar
297 AVX instructions with 128bit vector length, which is the default.
298 @option{-mavxscalar=@var{256}} will encode scalar AVX instructions
299 with 256bit vector length.
300
301 @cindex @samp{-mvexwig=} option, i386
302 @cindex @samp{-mvexwig=} option, x86-64
303 @item -mvexwig=@var{0}
304 @itemx -mvexwig=@var{1}
305 These options control how the assembler should encode VEX.W-ignored (WIG)
306 VEX instructions. @option{-mvexwig=@var{0}} will encode WIG VEX
307 instructions with vex.w = 0, which is the default.
308 @option{-mvexwig=@var{1}} will encode WIG EVEX instructions with
309 vex.w = 1.
310
311 @cindex @samp{-mevexlig=} option, i386
312 @cindex @samp{-mevexlig=} option, x86-64
313 @item -mevexlig=@var{128}
314 @itemx -mevexlig=@var{256}
315 @itemx -mevexlig=@var{512}
316 These options control how the assembler should encode length-ignored
317 (LIG) EVEX instructions. @option{-mevexlig=@var{128}} will encode LIG
318 EVEX instructions with 128bit vector length, which is the default.
319 @option{-mevexlig=@var{256}} and @option{-mevexlig=@var{512}} will
320 encode LIG EVEX instructions with 256bit and 512bit vector length,
321 respectively.
322
323 @cindex @samp{-mevexwig=} option, i386
324 @cindex @samp{-mevexwig=} option, x86-64
325 @item -mevexwig=@var{0}
326 @itemx -mevexwig=@var{1}
327 These options control how the assembler should encode w-ignored (WIG)
328 EVEX instructions. @option{-mevexwig=@var{0}} will encode WIG
329 EVEX instructions with evex.w = 0, which is the default.
330 @option{-mevexwig=@var{1}} will encode WIG EVEX instructions with
331 evex.w = 1.
332
333 @cindex @samp{-mmnemonic=} option, i386
334 @cindex @samp{-mmnemonic=} option, x86-64
335 @item -mmnemonic=@var{att}
336 @itemx -mmnemonic=@var{intel}
337 This option specifies instruction mnemonic for matching instructions.
338 The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will
339 take precedent.
340
341 @cindex @samp{-msyntax=} option, i386
342 @cindex @samp{-msyntax=} option, x86-64
343 @item -msyntax=@var{att}
344 @itemx -msyntax=@var{intel}
345 This option specifies instruction syntax when processing instructions.
346 The @code{.att_syntax} and @code{.intel_syntax} directives will
347 take precedent.
348
349 @cindex @samp{-mnaked-reg} option, i386
350 @cindex @samp{-mnaked-reg} option, x86-64
351 @item -mnaked-reg
352 This option specifies that registers don't require a @samp{%} prefix.
353 The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent.
354
355 @cindex @samp{-madd-bnd-prefix} option, i386
356 @cindex @samp{-madd-bnd-prefix} option, x86-64
357 @item -madd-bnd-prefix
358 This option forces the assembler to add BND prefix to all branches, even
359 if such prefix was not explicitly specified in the source code.
360
361 @cindex @samp{-mshared} option, i386
362 @cindex @samp{-mshared} option, x86-64
363 @item -mno-shared
364 On ELF target, the assembler normally optimizes out non-PLT relocations
365 against defined non-weak global branch targets with default visibility.
366 The @samp{-mshared} option tells the assembler to generate code which
367 may go into a shared library where all non-weak global branch targets
368 with default visibility can be preempted. The resulting code is
369 slightly bigger. This option only affects the handling of branch
370 instructions.
371
372 @cindex @samp{-mbig-obj} option, x86-64
373 @item -mbig-obj
374 On x86-64 PE/COFF target this option forces the use of big object file
375 format, which allows more than 32768 sections.
376
377 @cindex @samp{-momit-lock-prefix=} option, i386
378 @cindex @samp{-momit-lock-prefix=} option, x86-64
379 @item -momit-lock-prefix=@var{no}
380 @itemx -momit-lock-prefix=@var{yes}
381 These options control how the assembler should encode lock prefix.
382 This option is intended as a workaround for processors, that fail on
383 lock prefix. This option can only be safely used with single-core,
384 single-thread computers
385 @option{-momit-lock-prefix=@var{yes}} will omit all lock prefixes.
386 @option{-momit-lock-prefix=@var{no}} will encode lock prefix as usual,
387 which is the default.
388
389 @cindex @samp{-mfence-as-lock-add=} option, i386
390 @cindex @samp{-mfence-as-lock-add=} option, x86-64
391 @item -mfence-as-lock-add=@var{no}
392 @itemx -mfence-as-lock-add=@var{yes}
393 These options control how the assembler should encode lfence, mfence and
394 sfence.
395 @option{-mfence-as-lock-add=@var{yes}} will encode lfence, mfence and
396 sfence as @samp{lock addl $0x0, (%rsp)} in 64-bit mode and
397 @samp{lock addl $0x0, (%esp)} in 32-bit mode.
398 @option{-mfence-as-lock-add=@var{no}} will encode lfence, mfence and
399 sfence as usual, which is the default.
400
401 @cindex @samp{-mrelax-relocations=} option, i386
402 @cindex @samp{-mrelax-relocations=} option, x86-64
403 @item -mrelax-relocations=@var{no}
404 @itemx -mrelax-relocations=@var{yes}
405 These options control whether the assembler should generate relax
406 relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX and
407 R_X86_64_REX_GOTPCRELX, in 64-bit mode.
408 @option{-mrelax-relocations=@var{yes}} will generate relax relocations.
409 @option{-mrelax-relocations=@var{no}} will not generate relax
410 relocations. The default can be controlled by a configure option
411 @option{--enable-x86-relax-relocations}.
412
413 @cindex @samp{-mx86-used-note=} option, i386
414 @cindex @samp{-mx86-used-note=} option, x86-64
415 @item -mx86-used-note=@var{no}
416 @itemx -mx86-used-note=@var{yes}
417 These options control whether the assembler should generate
418 GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_FEATURE_2_USED
419 GNU property notes. The default can be controlled by the
420 @option{--enable-x86-used-note} configure option.
421
422 @cindex @samp{-mevexrcig=} option, i386
423 @cindex @samp{-mevexrcig=} option, x86-64
424 @item -mevexrcig=@var{rne}
425 @itemx -mevexrcig=@var{rd}
426 @itemx -mevexrcig=@var{ru}
427 @itemx -mevexrcig=@var{rz}
428 These options control how the assembler should encode SAE-only
429 EVEX instructions. @option{-mevexrcig=@var{rne}} will encode RC bits
430 of EVEX instruction with 00, which is the default.
431 @option{-mevexrcig=@var{rd}}, @option{-mevexrcig=@var{ru}}
432 and @option{-mevexrcig=@var{rz}} will encode SAE-only EVEX instructions
433 with 01, 10 and 11 RC bits, respectively.
434
435 @cindex @samp{-mamd64} option, x86-64
436 @cindex @samp{-mintel64} option, x86-64
437 @item -mamd64
438 @itemx -mintel64
439 This option specifies that the assembler should accept only AMD64 or
440 Intel64 ISA in 64-bit mode. The default is to accept both.
441
442 @cindex @samp{-O0} option, i386
443 @cindex @samp{-O0} option, x86-64
444 @cindex @samp{-O} option, i386
445 @cindex @samp{-O} option, x86-64
446 @cindex @samp{-O1} option, i386
447 @cindex @samp{-O1} option, x86-64
448 @cindex @samp{-O2} option, i386
449 @cindex @samp{-O2} option, x86-64
450 @cindex @samp{-Os} option, i386
451 @cindex @samp{-Os} option, x86-64
452 @item -O0 | -O | -O1 | -O2 | -Os
453 Optimize instruction encoding with smaller instruction size. @samp{-O}
454 and @samp{-O1} encode 64-bit register load instructions with 64-bit
455 immediate as 32-bit register load instructions with 31-bit or 32-bits
456 immediates and encode 64-bit register clearing instructions with 32-bit
457 register clearing instructions. @samp{-O2} includes @samp{-O1}
458 optimization plus encodes 256-bit and 512-bit vector register clearing
459 instructions with 128-bit vector register clearing instructions.
460 @samp{-Os} includes @samp{-O2} optimization plus encodes 16-bit, 32-bit
461 and 64-bit register tests with immediate as 8-bit register test with
462 immediate. @samp{-O0} turns off this optimization.
463
464 @end table
465 @c man end
466
467 @node i386-Directives
468 @section x86 specific Directives
469
470 @cindex machine directives, x86
471 @cindex x86 machine directives
472 @table @code
473
474 @cindex @code{lcomm} directive, COFF
475 @item .lcomm @var{symbol} , @var{length}[, @var{alignment}]
476 Reserve @var{length} (an absolute expression) bytes for a local common
477 denoted by @var{symbol}. The section and value of @var{symbol} are
478 those of the new local common. The addresses are allocated in the bss
479 section, so that at run-time the bytes start off zeroed. Since
480 @var{symbol} is not declared global, it is normally not visible to
481 @code{@value{LD}}. The optional third parameter, @var{alignment},
482 specifies the desired alignment of the symbol in the bss section.
483
484 This directive is only available for COFF based x86 targets.
485
486 @cindex @code{largecomm} directive, ELF
487 @item .largecomm @var{symbol} , @var{length}[, @var{alignment}]
488 This directive behaves in the same way as the @code{comm} directive
489 except that the data is placed into the @var{.lbss} section instead of
490 the @var{.bss} section @ref{Comm}.
491
492 The directive is intended to be used for data which requires a large
493 amount of space, and it is only available for ELF based x86_64
494 targets.
495
496 @c FIXME: Document other x86 specific directives ? Eg: .code16gcc,
497
498 @end table
499
500 @node i386-Syntax
501 @section i386 Syntactical Considerations
502 @menu
503 * i386-Variations:: AT&T Syntax versus Intel Syntax
504 * i386-Chars:: Special Characters
505 @end menu
506
507 @node i386-Variations
508 @subsection AT&T Syntax versus Intel Syntax
509
510 @cindex i386 intel_syntax pseudo op
511 @cindex intel_syntax pseudo op, i386
512 @cindex i386 att_syntax pseudo op
513 @cindex att_syntax pseudo op, i386
514 @cindex i386 syntax compatibility
515 @cindex syntax compatibility, i386
516 @cindex x86-64 intel_syntax pseudo op
517 @cindex intel_syntax pseudo op, x86-64
518 @cindex x86-64 att_syntax pseudo op
519 @cindex att_syntax pseudo op, x86-64
520 @cindex x86-64 syntax compatibility
521 @cindex syntax compatibility, x86-64
522
523 @code{@value{AS}} now supports assembly using Intel assembler syntax.
524 @code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches
525 back to the usual AT&T mode for compatibility with the output of
526 @code{@value{GCC}}. Either of these directives may have an optional
527 argument, @code{prefix}, or @code{noprefix} specifying whether registers
528 require a @samp{%} prefix. AT&T System V/386 assembler syntax is quite
529 different from Intel syntax. We mention these differences because
530 almost all 80386 documents use Intel syntax. Notable differences
531 between the two syntaxes are:
532
533 @cindex immediate operands, i386
534 @cindex i386 immediate operands
535 @cindex register operands, i386
536 @cindex i386 register operands
537 @cindex jump/call operands, i386
538 @cindex i386 jump/call operands
539 @cindex operand delimiters, i386
540
541 @cindex immediate operands, x86-64
542 @cindex x86-64 immediate operands
543 @cindex register operands, x86-64
544 @cindex x86-64 register operands
545 @cindex jump/call operands, x86-64
546 @cindex x86-64 jump/call operands
547 @cindex operand delimiters, x86-64
548 @itemize @bullet
549 @item
550 AT&T immediate operands are preceded by @samp{$}; Intel immediate
551 operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}).
552 AT&T register operands are preceded by @samp{%}; Intel register operands
553 are undelimited. AT&T absolute (as opposed to PC relative) jump/call
554 operands are prefixed by @samp{*}; they are undelimited in Intel syntax.
555
556 @cindex i386 source, destination operands
557 @cindex source, destination operands; i386
558 @cindex x86-64 source, destination operands
559 @cindex source, destination operands; x86-64
560 @item
561 AT&T and Intel syntax use the opposite order for source and destination
562 operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The
563 @samp{source, dest} convention is maintained for compatibility with
564 previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and
565 instructions with 2 immediate operands, such as the @samp{enter}
566 instruction, do @emph{not} have reversed order. @ref{i386-Bugs}.
567
568 @cindex mnemonic suffixes, i386
569 @cindex sizes operands, i386
570 @cindex i386 size suffixes
571 @cindex mnemonic suffixes, x86-64
572 @cindex sizes operands, x86-64
573 @cindex x86-64 size suffixes
574 @item
575 In AT&T syntax the size of memory operands is determined from the last
576 character of the instruction mnemonic. Mnemonic suffixes of @samp{b},
577 @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long
578 (32-bit) and quadruple word (64-bit) memory references. Intel syntax accomplishes
579 this by prefixing memory operands (@emph{not} the instruction mnemonics) with
580 @samp{byte ptr}, @samp{word ptr}, @samp{dword ptr} and @samp{qword ptr}. Thus,
581 Intel @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
582 syntax.
583
584 In 64-bit code, @samp{movabs} can be used to encode the @samp{mov}
585 instruction with the 64-bit displacement or immediate operand.
586
587 @cindex return instructions, i386
588 @cindex i386 jump, call, return
589 @cindex return instructions, x86-64
590 @cindex x86-64 jump, call, return
591 @item
592 Immediate form long jumps and calls are
593 @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
594 Intel syntax is
595 @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return
596 instruction
597 is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
598 @samp{ret far @var{stack-adjust}}.
599
600 @cindex sections, i386
601 @cindex i386 sections
602 @cindex sections, x86-64
603 @cindex x86-64 sections
604 @item
605 The AT&T assembler does not provide support for multiple section
606 programs. Unix style systems expect all programs to be single sections.
607 @end itemize
608
609 @node i386-Chars
610 @subsection Special Characters
611
612 @cindex line comment character, i386
613 @cindex i386 line comment character
614 The presence of a @samp{#} appearing anywhere on a line indicates the
615 start of a comment that extends to the end of that line.
616
617 If a @samp{#} appears as the first character of a line then the whole
618 line is treated as a comment, but in this case the line can also be a
619 logical line number directive (@pxref{Comments}) or a preprocessor
620 control command (@pxref{Preprocessing}).
621
622 If the @option{--divide} command-line option has not been specified
623 then the @samp{/} character appearing anywhere on a line also
624 introduces a line comment.
625
626 @cindex line separator, i386
627 @cindex statement separator, i386
628 @cindex i386 line separator
629 The @samp{;} character can be used to separate statements on the same
630 line.
631
632 @node i386-Mnemonics
633 @section i386-Mnemonics
634 @subsection Instruction Naming
635
636 @cindex i386 instruction naming
637 @cindex instruction naming, i386
638 @cindex x86-64 instruction naming
639 @cindex instruction naming, x86-64
640
641 Instruction mnemonics are suffixed with one character modifiers which
642 specify the size of operands. The letters @samp{b}, @samp{w}, @samp{l}
643 and @samp{q} specify byte, word, long and quadruple word operands. If
644 no suffix is specified by an instruction then @code{@value{AS}} tries to
645 fill in the missing suffix based on the destination register operand
646 (the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent
647 to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to
648 @samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix
649 assembler which assumes that a missing mnemonic suffix implies long
650 operand size. (This incompatibility does not affect compiler output
651 since compilers always explicitly specify the mnemonic suffix.)
652
653 Almost all instructions have the same names in AT&T and Intel format.
654 There are a few exceptions. The sign extend and zero extend
655 instructions need two sizes to specify them. They need a size to
656 sign/zero extend @emph{from} and a size to zero extend @emph{to}. This
657 is accomplished by using two instruction mnemonic suffixes in AT&T
658 syntax. Base names for sign extend and zero extend are
659 @samp{movs@dots{}} and @samp{movz@dots{}} in AT&T syntax (@samp{movsx}
660 and @samp{movzx} in Intel syntax). The instruction mnemonic suffixes
661 are tacked on to this base name, the @emph{from} suffix before the
662 @emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for
663 ``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes,
664 thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word),
665 @samp{wl} (from word to long), @samp{bq} (from byte to quadruple word),
666 @samp{wq} (from word to quadruple word), and @samp{lq} (from long to
667 quadruple word).
668
669 @cindex encoding options, i386
670 @cindex encoding options, x86-64
671
672 Different encoding options can be specified via pseudo prefixes:
673
674 @itemize @bullet
675 @item
676 @samp{@{disp8@}} -- prefer 8-bit displacement.
677
678 @item
679 @samp{@{disp32@}} -- prefer 32-bit displacement.
680
681 @item
682 @samp{@{load@}} -- prefer load-form instruction.
683
684 @item
685 @samp{@{store@}} -- prefer store-form instruction.
686
687 @item
688 @samp{@{vex2@}} -- prefer 2-byte VEX prefix for VEX instruction.
689
690 @item
691 @samp{@{vex3@}} -- prefer 3-byte VEX prefix for VEX instruction.
692
693 @item
694 @samp{@{evex@}} -- encode with EVEX prefix.
695
696 @item
697 @samp{@{rex@}} -- prefer REX prefix for integer and legacy vector
698 instructions (x86-64 only). Note that this differs from the @samp{rex}
699 prefix which generates REX prefix unconditionally.
700
701 @item
702 @samp{@{nooptimize@}} -- disable instruction size optimization.
703 @end itemize
704
705 @cindex conversion instructions, i386
706 @cindex i386 conversion instructions
707 @cindex conversion instructions, x86-64
708 @cindex x86-64 conversion instructions
709 The Intel-syntax conversion instructions
710
711 @itemize @bullet
712 @item
713 @samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax},
714
715 @item
716 @samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax},
717
718 @item
719 @samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax},
720
721 @item
722 @samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax},
723
724 @item
725 @samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax}
726 (x86-64 only),
727
728 @item
729 @samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in
730 @samp{%rdx:%rax} (x86-64 only),
731 @end itemize
732
733 @noindent
734 are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and
735 @samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these
736 instructions.
737
738 @cindex jump instructions, i386
739 @cindex call instructions, i386
740 @cindex jump instructions, x86-64
741 @cindex call instructions, x86-64
742 Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
743 AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
744 convention.
745
746 @subsection AT&T Mnemonic versus Intel Mnemonic
747
748 @cindex i386 mnemonic compatibility
749 @cindex mnemonic compatibility, i386
750
751 @code{@value{AS}} supports assembly using Intel mnemonic.
752 @code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and
753 @code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T
754 syntax for compatibility with the output of @code{@value{GCC}}.
755 Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp},
756 @samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp},
757 @samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386
758 assembler with different mnemonics from those in Intel IA32 specification.
759 @code{@value{GCC}} generates those instructions with AT&T mnemonic.
760
761 @node i386-Regs
762 @section Register Naming
763
764 @cindex i386 registers
765 @cindex registers, i386
766 @cindex x86-64 registers
767 @cindex registers, x86-64
768 Register operands are always prefixed with @samp{%}. The 80386 registers
769 consist of
770
771 @itemize @bullet
772 @item
773 the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx},
774 @samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the
775 frame pointer), and @samp{%esp} (the stack pointer).
776
777 @item
778 the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx},
779 @samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}.
780
781 @item
782 the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh},
783 @samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These
784 are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx},
785 @samp{%cx}, and @samp{%dx})
786
787 @item
788 the 6 section registers @samp{%cs} (code section), @samp{%ds}
789 (data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs},
790 and @samp{%gs}.
791
792 @item
793 the 5 processor control registers @samp{%cr0}, @samp{%cr2},
794 @samp{%cr3}, @samp{%cr4}, and @samp{%cr8}.
795
796 @item
797 the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2},
798 @samp{%db3}, @samp{%db6}, and @samp{%db7}.
799
800 @item
801 the 2 test registers @samp{%tr6} and @samp{%tr7}.
802
803 @item
804 the 8 floating point register stack @samp{%st} or equivalently
805 @samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)},
806 @samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}.
807 These registers are overloaded by 8 MMX registers @samp{%mm0},
808 @samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5},
809 @samp{%mm6} and @samp{%mm7}.
810
811 @item
812 the 8 128-bit SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2},
813 @samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}.
814 @end itemize
815
816 The AMD x86-64 architecture extends the register set by:
817
818 @itemize @bullet
819 @item
820 enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the
821 accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi},
822 @samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack
823 pointer)
824
825 @item
826 the 8 extended registers @samp{%r8}--@samp{%r15}.
827
828 @item
829 the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}.
830
831 @item
832 the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}.
833
834 @item
835 the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}.
836
837 @item
838 the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}.
839
840 @item
841 the 8 debug registers: @samp{%db8}--@samp{%db15}.
842
843 @item
844 the 8 128-bit SSE registers: @samp{%xmm8}--@samp{%xmm15}.
845 @end itemize
846
847 With the AVX extensions more registers were made available:
848
849 @itemize @bullet
850
851 @item
852 the 16 256-bit SSE @samp{%ymm0}--@samp{%ymm15} (only the first 8
853 available in 32-bit mode). The bottom 128 bits are overlaid with the
854 @samp{xmm0}--@samp{xmm15} registers.
855
856 @end itemize
857
858 The AVX2 extensions made in 64-bit mode more registers available:
859
860 @itemize @bullet
861
862 @item
863 the 16 128-bit registers @samp{%xmm16}--@samp{%xmm31} and the 16 256-bit
864 registers @samp{%ymm16}--@samp{%ymm31}.
865
866 @end itemize
867
868 The AVX512 extensions added the following registers:
869
870 @itemize @bullet
871
872 @item
873 the 32 512-bit registers @samp{%zmm0}--@samp{%zmm31} (only the first 8
874 available in 32-bit mode). The bottom 128 bits are overlaid with the
875 @samp{%xmm0}--@samp{%xmm31} registers and the first 256 bits are
876 overlaid with the @samp{%ymm0}--@samp{%ymm31} registers.
877
878 @item
879 the 8 mask registers @samp{%k0}--@samp{%k7}.
880
881 @end itemize
882
883 @node i386-Prefixes
884 @section Instruction Prefixes
885
886 @cindex i386 instruction prefixes
887 @cindex instruction prefixes, i386
888 @cindex prefixes, i386
889 Instruction prefixes are used to modify the following instruction. They
890 are used to repeat string instructions, to provide section overrides, to
891 perform bus lock operations, and to change operand and address sizes.
892 (Most instructions that normally operate on 32-bit operands will use
893 16-bit operands if the instruction has an ``operand size'' prefix.)
894 Instruction prefixes are best written on the same line as the instruction
895 they act upon. For example, the @samp{scas} (scan string) instruction is
896 repeated with:
897
898 @smallexample
899 repne scas %es:(%edi),%al
900 @end smallexample
901
902 You may also place prefixes on the lines immediately preceding the
903 instruction, but this circumvents checks that @code{@value{AS}} does
904 with prefixes, and will not work with all prefixes.
905
906 Here is a list of instruction prefixes:
907
908 @cindex section override prefixes, i386
909 @itemize @bullet
910 @item
911 Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es},
912 @samp{fs}, @samp{gs}. These are automatically added by specifying
913 using the @var{section}:@var{memory-operand} form for memory references.
914
915 @cindex size prefixes, i386
916 @item
917 Operand/Address size prefixes @samp{data16} and @samp{addr16}
918 change 32-bit operands/addresses into 16-bit operands/addresses,
919 while @samp{data32} and @samp{addr32} change 16-bit ones (in a
920 @code{.code16} section) into 32-bit operands/addresses. These prefixes
921 @emph{must} appear on the same line of code as the instruction they
922 modify. For example, in a 16-bit @code{.code16} section, you might
923 write:
924
925 @smallexample
926 addr32 jmpl *(%ebx)
927 @end smallexample
928
929 @cindex bus lock prefixes, i386
930 @cindex inhibiting interrupts, i386
931 @item
932 The bus lock prefix @samp{lock} inhibits interrupts during execution of
933 the instruction it precedes. (This is only valid with certain
934 instructions; see a 80386 manual for details).
935
936 @cindex coprocessor wait, i386
937 @item
938 The wait for coprocessor prefix @samp{wait} waits for the coprocessor to
939 complete the current instruction. This should never be needed for the
940 80386/80387 combination.
941
942 @cindex repeat prefixes, i386
943 @item
944 The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added
945 to string instructions to make them repeat @samp{%ecx} times (@samp{%cx}
946 times if the current address size is 16-bits).
947 @cindex REX prefixes, i386
948 @item
949 The @samp{rex} family of prefixes is used by x86-64 to encode
950 extensions to i386 instruction set. The @samp{rex} prefix has four
951 bits --- an operand size overwrite (@code{64}) used to change operand size
952 from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the
953 register set.
954
955 You may write the @samp{rex} prefixes directly. The @samp{rex64xyz}
956 instruction emits @samp{rex} prefix with all the bits set. By omitting
957 the @code{64}, @code{x}, @code{y} or @code{z} you may write other
958 prefixes as well. Normally, there is no need to write the prefixes
959 explicitly, since gas will automatically generate them based on the
960 instruction operands.
961 @end itemize
962
963 @node i386-Memory
964 @section Memory References
965
966 @cindex i386 memory references
967 @cindex memory references, i386
968 @cindex x86-64 memory references
969 @cindex memory references, x86-64
970 An Intel syntax indirect memory reference of the form
971
972 @smallexample
973 @var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}]
974 @end smallexample
975
976 @noindent
977 is translated into the AT&T syntax
978
979 @smallexample
980 @var{section}:@var{disp}(@var{base}, @var{index}, @var{scale})
981 @end smallexample
982
983 @noindent
984 where @var{base} and @var{index} are the optional 32-bit base and
985 index registers, @var{disp} is the optional displacement, and
986 @var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index}
987 to calculate the address of the operand. If no @var{scale} is
988 specified, @var{scale} is taken to be 1. @var{section} specifies the
989 optional section register for the memory operand, and may override the
990 default section register (see a 80386 manual for section register
991 defaults). Note that section overrides in AT&T syntax @emph{must}
992 be preceded by a @samp{%}. If you specify a section override which
993 coincides with the default section register, @code{@value{AS}} does @emph{not}
994 output any section register override prefixes to assemble the given
995 instruction. Thus, section overrides can be specified to emphasize which
996 section register is used for a given memory operand.
997
998 Here are some examples of Intel and AT&T style memory references:
999
1000 @table @asis
1001 @item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]}
1002 @var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is
1003 missing, and the default section is used (@samp{%ss} for addressing with
1004 @samp{%ebp} as the base register). @var{index}, @var{scale} are both missing.
1005
1006 @item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]}
1007 @var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is
1008 @samp{foo}. All other fields are missing. The section register here
1009 defaults to @samp{%ds}.
1010
1011 @item AT&T: @samp{foo(,1)}; Intel @samp{[foo]}
1012 This uses the value pointed to by @samp{foo} as a memory operand.
1013 Note that @var{base} and @var{index} are both missing, but there is only
1014 @emph{one} @samp{,}. This is a syntactic exception.
1015
1016 @item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo}
1017 This selects the contents of the variable @samp{foo} with section
1018 register @var{section} being @samp{%gs}.
1019 @end table
1020
1021 Absolute (as opposed to PC relative) call and jump operands must be
1022 prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}}
1023 always chooses PC relative addressing for jump/call labels.
1024
1025 Any instruction that has a memory operand, but no register operand,
1026 @emph{must} specify its size (byte, word, long, or quadruple) with an
1027 instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q},
1028 respectively).
1029
1030 The x86-64 architecture adds an RIP (instruction pointer relative)
1031 addressing. This addressing mode is specified by using @samp{rip} as a
1032 base register. Only constant offsets are valid. For example:
1033
1034 @table @asis
1035 @item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]}
1036 Points to the address 1234 bytes past the end of the current
1037 instruction.
1038
1039 @item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]}
1040 Points to the @code{symbol} in RIP relative way, this is shorter than
1041 the default absolute addressing.
1042 @end table
1043
1044 Other addressing modes remain unchanged in x86-64 architecture, except
1045 registers used are 64-bit instead of 32-bit.
1046
1047 @node i386-Jumps
1048 @section Handling of Jump Instructions
1049
1050 @cindex jump optimization, i386
1051 @cindex i386 jump optimization
1052 @cindex jump optimization, x86-64
1053 @cindex x86-64 jump optimization
1054 Jump instructions are always optimized to use the smallest possible
1055 displacements. This is accomplished by using byte (8-bit) displacement
1056 jumps whenever the target is sufficiently close. If a byte displacement
1057 is insufficient a long displacement is used. We do not support
1058 word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
1059 instruction with the @samp{data16} instruction prefix), since the 80386
1060 insists upon masking @samp{%eip} to 16 bits after the word displacement
1061 is added. (See also @pxref{i386-Arch})
1062
1063 Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz},
1064 @samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte
1065 displacements, so that if you use these instructions (@code{@value{GCC}} does
1066 not use them) you may get an error message (and incorrect code). The AT&T
1067 80386 assembler tries to get around this problem by expanding @samp{jcxz foo}
1068 to
1069
1070 @smallexample
1071 jcxz cx_zero
1072 jmp cx_nonzero
1073 cx_zero: jmp foo
1074 cx_nonzero:
1075 @end smallexample
1076
1077 @node i386-Float
1078 @section Floating Point
1079
1080 @cindex i386 floating point
1081 @cindex floating point, i386
1082 @cindex x86-64 floating point
1083 @cindex floating point, x86-64
1084 All 80387 floating point types except packed BCD are supported.
1085 (BCD support may be added without much difficulty). These data
1086 types are 16-, 32-, and 64- bit integers, and single (32-bit),
1087 double (64-bit), and extended (80-bit) precision floating point.
1088 Each supported type has an instruction mnemonic suffix and a constructor
1089 associated with it. Instruction mnemonic suffixes specify the operand's
1090 data type. Constructors build these data types into memory.
1091
1092 @cindex @code{float} directive, i386
1093 @cindex @code{single} directive, i386
1094 @cindex @code{double} directive, i386
1095 @cindex @code{tfloat} directive, i386
1096 @cindex @code{float} directive, x86-64
1097 @cindex @code{single} directive, x86-64
1098 @cindex @code{double} directive, x86-64
1099 @cindex @code{tfloat} directive, x86-64
1100 @itemize @bullet
1101 @item
1102 Floating point constructors are @samp{.float} or @samp{.single},
1103 @samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats.
1104 These correspond to instruction mnemonic suffixes @samp{s}, @samp{l},
1105 and @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387
1106 only supports this format via the @samp{fldt} (load 80-bit real to stack
1107 top) and @samp{fstpt} (store 80-bit real and pop stack) instructions.
1108
1109 @cindex @code{word} directive, i386
1110 @cindex @code{long} directive, i386
1111 @cindex @code{int} directive, i386
1112 @cindex @code{quad} directive, i386
1113 @cindex @code{word} directive, x86-64
1114 @cindex @code{long} directive, x86-64
1115 @cindex @code{int} directive, x86-64
1116 @cindex @code{quad} directive, x86-64
1117 @item
1118 Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and
1119 @samp{.quad} for the 16-, 32-, and 64-bit integer formats. The
1120 corresponding instruction mnemonic suffixes are @samp{s} (single),
1121 @samp{l} (long), and @samp{q} (quad). As with the 80-bit real format,
1122 the 64-bit @samp{q} format is only present in the @samp{fildq} (load
1123 quad integer to stack top) and @samp{fistpq} (store quad integer and pop
1124 stack) instructions.
1125 @end itemize
1126
1127 Register to register operations should not use instruction mnemonic suffixes.
1128 @samp{fstl %st, %st(1)} will give a warning, and be assembled as if you
1129 wrote @samp{fst %st, %st(1)}, since all register to register operations
1130 use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem},
1131 which converts @samp{%st} from 80-bit to 64-bit floating point format,
1132 then stores the result in the 4 byte location @samp{mem})
1133
1134 @node i386-SIMD
1135 @section Intel's MMX and AMD's 3DNow! SIMD Operations
1136
1137 @cindex MMX, i386
1138 @cindex 3DNow!, i386
1139 @cindex SIMD, i386
1140 @cindex MMX, x86-64
1141 @cindex 3DNow!, x86-64
1142 @cindex SIMD, x86-64
1143
1144 @code{@value{AS}} supports Intel's MMX instruction set (SIMD
1145 instructions for integer data), available on Intel's Pentium MMX
1146 processors and Pentium II processors, AMD's K6 and K6-2 processors,
1147 Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@:
1148 instruction set (SIMD instructions for 32-bit floating point data)
1149 available on AMD's K6-2 processor and possibly others in the future.
1150
1151 Currently, @code{@value{AS}} does not support Intel's floating point
1152 SIMD, Katmai (KNI).
1153
1154 The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0},
1155 @samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four
1156 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
1157 floating point values. The MMX registers cannot be used at the same time
1158 as the floating point stack.
1159
1160 See Intel and AMD documentation, keeping in mind that the operand order in
1161 instructions is reversed from the Intel syntax.
1162
1163 @node i386-LWP
1164 @section AMD's Lightweight Profiling Instructions
1165
1166 @cindex LWP, i386
1167 @cindex LWP, x86-64
1168
1169 @code{@value{AS}} supports AMD's Lightweight Profiling (LWP)
1170 instruction set, available on AMD's Family 15h (Orochi) processors.
1171
1172 LWP enables applications to collect and manage performance data, and
1173 react to performance events. The collection of performance data
1174 requires no context switches. LWP runs in the context of a thread and
1175 so several counters can be used independently across multiple threads.
1176 LWP can be used in both 64-bit and legacy 32-bit modes.
1177
1178 For detailed information on the LWP instruction set, see the
1179 @cite{AMD Lightweight Profiling Specification} available at
1180 @uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}.
1181
1182 @node i386-BMI
1183 @section Bit Manipulation Instructions
1184
1185 @cindex BMI, i386
1186 @cindex BMI, x86-64
1187
1188 @code{@value{AS}} supports the Bit Manipulation (BMI) instruction set.
1189
1190 BMI instructions provide several instructions implementing individual
1191 bit manipulation operations such as isolation, masking, setting, or
1192 resetting.
1193
1194 @c Need to add a specification citation here when available.
1195
1196 @node i386-TBM
1197 @section AMD's Trailing Bit Manipulation Instructions
1198
1199 @cindex TBM, i386
1200 @cindex TBM, x86-64
1201
1202 @code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM)
1203 instruction set, available on AMD's BDVER2 processors (Trinity and
1204 Viperfish).
1205
1206 TBM instructions provide instructions implementing individual bit
1207 manipulation operations such as isolating, masking, setting, resetting,
1208 complementing, and operations on trailing zeros and ones.
1209
1210 @c Need to add a specification citation here when available.
1211
1212 @node i386-16bit
1213 @section Writing 16-bit Code
1214
1215 @cindex i386 16-bit code
1216 @cindex 16-bit code, i386
1217 @cindex real-mode code, i386
1218 @cindex @code{code16gcc} directive, i386
1219 @cindex @code{code16} directive, i386
1220 @cindex @code{code32} directive, i386
1221 @cindex @code{code64} directive, i386
1222 @cindex @code{code64} directive, x86-64
1223 While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code
1224 or 64-bit x86-64 code depending on the default configuration,
1225 it also supports writing code to run in real mode or in 16-bit protected
1226 mode code segments. To do this, put a @samp{.code16} or
1227 @samp{.code16gcc} directive before the assembly language instructions to
1228 be run in 16-bit mode. You can switch @code{@value{AS}} to writing
1229 32-bit code with the @samp{.code32} directive or 64-bit code with the
1230 @samp{.code64} directive.
1231
1232 @samp{.code16gcc} provides experimental support for generating 16-bit
1233 code from gcc, and differs from @samp{.code16} in that @samp{call},
1234 @samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop},
1235 @samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions
1236 default to 32-bit size. This is so that the stack pointer is
1237 manipulated in the same way over function calls, allowing access to
1238 function parameters at the same stack offsets as in 32-bit mode.
1239 @samp{.code16gcc} also automatically adds address size prefixes where
1240 necessary to use the 32-bit addressing modes that gcc generates.
1241
1242 The code which @code{@value{AS}} generates in 16-bit mode will not
1243 necessarily run on a 16-bit pre-80386 processor. To write code that
1244 runs on such a processor, you must refrain from using @emph{any} 32-bit
1245 constructs which require @code{@value{AS}} to output address or operand
1246 size prefixes.
1247
1248 Note that writing 16-bit code instructions by explicitly specifying a
1249 prefix or an instruction mnemonic suffix within a 32-bit code section
1250 generates different machine instructions than those generated for a
1251 16-bit code segment. In a 32-bit code section, the following code
1252 generates the machine opcode bytes @samp{66 6a 04}, which pushes the
1253 value @samp{4} onto the stack, decrementing @samp{%esp} by 2.
1254
1255 @smallexample
1256 pushw $4
1257 @end smallexample
1258
1259 The same code in a 16-bit code section would generate the machine
1260 opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which
1261 is correct since the processor default operand size is assumed to be 16
1262 bits in a 16-bit code section.
1263
1264 @node i386-Arch
1265 @section Specifying CPU Architecture
1266
1267 @cindex arch directive, i386
1268 @cindex i386 arch directive
1269 @cindex arch directive, x86-64
1270 @cindex x86-64 arch directive
1271
1272 @code{@value{AS}} may be told to assemble for a particular CPU
1273 (sub-)architecture with the @code{.arch @var{cpu_type}} directive. This
1274 directive enables a warning when gas detects an instruction that is not
1275 supported on the CPU specified. The choices for @var{cpu_type} are:
1276
1277 @multitable @columnfractions .20 .20 .20 .20
1278 @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
1279 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
1280 @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
1281 @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
1282 @item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om} @tab @samp{iamcu}
1283 @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
1284 @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3}
1285 @item @samp{bdver4} @tab @samp{znver1} @tab @samp{znver2} @tab @samp{btver1}
1286 @item @samp{btver2} @tab @samp{generic32} @tab @samp{generic64}
1287 @item @samp{.cmov} @tab @samp{.fxsr} @tab @samp{.mmx}
1288 @item @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
1289 @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
1290 @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept}
1291 @item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt}
1292 @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase}
1293 @item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2}
1294 @item @samp{.lzcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} @tab @samp{.hle}
1295 @item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
1296 @item @samp{.smap} @tab @samp{.mpx} @tab @samp{.sha} @tab @samp{.prefetchwt1}
1297 @item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1}
1298 @item @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} @tab @samp{.avx512pf}
1299 @item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma}
1300 @item @samp{.avx512vbmi} @tab @samp{.avx512_4fmaps} @tab @samp{.avx512_4vnniw}
1301 @item @samp{.avx512_vpopcntdq} @tab @samp{.avx512_vbmi2} @tab @samp{.avx512_vnni}
1302 @item @samp{.avx512_bitalg}
1303 @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @item @samp{.ibt}
1304 @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
1305 @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
1306 @item @samp{.movdiri} @tab @samp{.movdir64b}
1307 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
1308 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
1309 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
1310 @item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx}
1311 @end multitable
1312
1313 Apart from the warning, there are only two other effects on
1314 @code{@value{AS}} operation; Firstly, if you specify a CPU other than
1315 @samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax}
1316 will automatically use a two byte opcode sequence. The larger three
1317 byte opcode sequence is used on the 486 (and when no architecture is
1318 specified) because it executes faster on the 486. Note that you can
1319 explicitly request the two byte opcode by writing @samp{sarl %eax}.
1320 Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286},
1321 @emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset
1322 conditional jumps will be promoted when necessary to a two instruction
1323 sequence consisting of a conditional jump of the opposite sense around
1324 an unconditional jump to the target.
1325
1326 Following the CPU architecture (but not a sub-architecture, which are those
1327 starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to
1328 control automatic promotion of conditional jumps. @samp{jumps} is the
1329 default, and enables jump promotion; All external jumps will be of the long
1330 variety, and file-local jumps will be promoted as necessary.
1331 (@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as
1332 byte offset jumps, and warns about file-local conditional jumps that
1333 @code{@value{AS}} promotes.
1334 Unconditional jumps are treated as for @samp{jumps}.
1335
1336 For example
1337
1338 @smallexample
1339 .arch i8086,nojumps
1340 @end smallexample
1341
1342 @node i386-Bugs
1343 @section AT&T Syntax bugs
1344
1345 The UnixWare assembler, and probably other AT&T derived ix86 Unix
1346 assemblers, generate floating point instructions with reversed source
1347 and destination registers in certain cases. Unfortunately, gcc and
1348 possibly many other programs use this reversed syntax, so we're stuck
1349 with it.
1350
1351 For example
1352
1353 @smallexample
1354 fsub %st,%st(3)
1355 @end smallexample
1356 @noindent
1357 results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather
1358 than the expected @samp{%st(3) - %st}. This happens with all the
1359 non-commutative arithmetic floating point operations with two register
1360 operands where the source register is @samp{%st} and the destination
1361 register is @samp{%st(i)}.
1362
1363 @node i386-Notes
1364 @section Notes
1365
1366 @cindex i386 @code{mul}, @code{imul} instructions
1367 @cindex @code{mul} instruction, i386
1368 @cindex @code{imul} instruction, i386
1369 @cindex @code{mul} instruction, x86-64
1370 @cindex @code{imul} instruction, x86-64
1371 There is some trickery concerning the @samp{mul} and @samp{imul}
1372 instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding
1373 multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5
1374 for @samp{imul}) can be output only in the one operand form. Thus,
1375 @samp{imul %ebx, %eax} does @emph{not} select the expanding multiply;
1376 the expanding multiply would clobber the @samp{%edx} register, and this
1377 would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the
1378 64-bit product in @samp{%edx:%eax}.
1379
1380 We have added a two operand form of @samp{imul} when the first operand
1381 is an immediate mode expression and the second operand is a register.
1382 This is just a shorthand, so that, multiplying @samp{%eax} by 69, for
1383 example, can be done with @samp{imul $69, %eax} rather than @samp{imul
1384 $69, %eax, %eax}.
1385