gas/doc/c-m68k.texi

   1 @c Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2003
   2 @c Free Software Foundation, Inc.
   3 @c This is part of the GAS manual.
   4 @c For copying conditions, see the file as.texinfo.
   5 @ifset GENERIC
   6 @page
   7 @node M68K-Dependent
   8 @chapter M680x0 Dependent Features
   9 @end ifset
  10 @ifclear GENERIC
  11 @node Machine Dependencies
  12 @chapter M680x0 Dependent Features
  13 @end ifclear
  14
  15 @cindex M680x0 support
  16 @menu
  17 * M68K-Opts::                   M680x0 Options
  18 * M68K-Syntax::                 Syntax
  19 * M68K-Moto-Syntax::            Motorola Syntax
  20 * M68K-Float::                  Floating Point
  21 * M68K-Directives::             680x0 Machine Directives
  22 * M68K-opcodes::                Opcodes
  23 @end menu
  24
  25 @node M68K-Opts
  26 @section M680x0 Options
  27
  28 @cindex options, M680x0
  29 @cindex M680x0 options
  30 The Motorola 680x0 version of @code{@value{AS}} has a few machine
  31 dependent options:
  32
  33 @table @samp
  34
  35 @cindex @samp{-l} option, M680x0
  36 @item -l
  37 You can use the @samp{-l} option to shorten the size of references to undefined
  38 symbols.  If you do not use the @samp{-l} option, references to undefined
  39 symbols are wide enough for a full @code{long} (32 bits).  (Since
  40 @code{@value{AS}} cannot know where these symbols end up, @code{@value{AS}} can
  41 only allocate space for the linker to fill in later.  Since @code{@value{AS}}
  42 does not know how far away these symbols are, it allocates as much space as it
  43 can.)  If you use this option, the references are only one word wide (16 bits).
  44 This may be useful if you want the object file to be as small as possible, and
  45 you know that the relevant symbols are always less than 17 bits away.
  46
  47 @cindex @samp{--register-prefix-optional} option, M680x0
  48 @item --register-prefix-optional
  49 For some configurations, especially those where the compiler normally
  50 does not prepend an underscore to the names of user variables, the
  51 assembler requires a @samp{%} before any use of a register name.  This
  52 is intended to let the assembler distinguish between C variables and
  53 functions named @samp{a0} through @samp{a7}, and so on.  The @samp{%} is
  54 always accepted, but is not required for certain configurations, notably
  55 @samp{sun3}.  The @samp{--register-prefix-optional} option may be used
  56 to permit omitting the @samp{%} even for configurations for which it is
  57 normally required.  If this is done, it will generally be impossible to
  58 refer to C variables and functions with the same names as register
  59 names.
  60
  61 @cindex @samp{--bitwise-or} option, M680x0
  62 @item --bitwise-or
  63 Normally the character @samp{|} is treated as a comment character, which
  64 means that it can not be used in expressions.  The @samp{--bitwise-or}
  65 option turns @samp{|} into a normal character.  In this mode, you must
  66 either use C style comments, or start comments with a @samp{#} character
  67 at the beginning of a line.
  68
  69 @cindex @samp{--base-size-default-16}
  70 @cindex @samp{--base-size-default-32}
  71 @item --base-size-default-16  --base-size-default-32
  72 If you use an addressing mode with a base register without specifying
  73 the size, @code{@value{AS}} will normally use the full 32 bit value.
  74 For example, the addressing mode @samp{%a0@@(%d0)} is equivalent to
  75 @samp{%a0@@(%d0:l)}.  You may use the @samp{--base-size-default-16}
  76 option to tell @code{@value{AS}} to default to using the 16 bit value.
  77 In this case, @samp{%a0@@(%d0)} is equivalent to @samp{%a0@@(%d0:w)}.
  78 You may use the @samp{--base-size-default-32} option to restore the
  79 default behaviour.
  80
  81 @cindex @samp{--disp-size-default-16}
  82 @cindex @samp{--disp-size-default-32}
  83 @item --disp-size-default-16  --disp-size-default-32
  84 If you use an addressing mode with a displacement, and the value of the
  85 displacement is not known, @code{@value{AS}} will normally assume that
  86 the value is 32 bits.  For example, if the symbol @samp{disp} has not
  87 been defined, @code{@value{AS}} will assemble the addressing mode
  88 @samp{%a0@@(disp,%d0)} as though @samp{disp} is a 32 bit value.  You may
  89 use the @samp{--disp-size-default-16} option to tell @code{@value{AS}}
  90 to instead assume that the displacement is 16 bits.  In this case,
  91 @code{@value{AS}} will assemble @samp{%a0@@(disp,%d0)} as though
  92 @samp{disp} is a 16 bit value.  You may use the
  93 @samp{--disp-size-default-32} option to restore the default behaviour.
  94
  95 @cindex @samp{--pcrel}
  96 @item --pcrel
  97 Always keep branches PC-relative.  In the M680x0 architecture all branches
  98 are defined as PC-relative.  However, on some processors they are limited
  99 to word displacements maximum.  When @code{@value{AS}} needs a long branch
 100 that is not available, it normally emits an absolute jump instead.  This
 101 option disables this substitution.  When this option is given and no long
 102 branches are available, only word branches will be emitted.  An error
 103 message will be generated if a word branch cannot reach its target.  This
 104 option has no effect on 68020 and other processors that have long branches.
 105 @pxref{M68K-Branch,,Branch Improvement}.
 106
 107 @cindex @samp{-m68000} and related options
 108 @cindex architecture options, M680x0
 109 @cindex M680x0 architecture options
 110 @item -m68000
 111 @code{@value{AS}} can assemble code for several different members of the
 112 Motorola 680x0 family.  The default depends upon how @code{@value{AS}}
 113 was configured when it was built; normally, the default is to assemble
 114 code for the 68020 microprocessor.  The following options may be used to
 115 change the default.  These options control which instructions and
 116 addressing modes are permitted.  The members of the 680x0 family are
 117 very similar.  For detailed information about the differences, see the
 118 Motorola manuals.
 119
 120 @table @samp
 121 @item -m68000
 122 @itemx -m68ec000
 123 @itemx -m68hc000
 124 @itemx -m68hc001
 125 @itemx -m68008
 126 @itemx -m68302
 127 @itemx -m68306
 128 @itemx -m68307
 129 @itemx -m68322
 130 @itemx -m68356
 131 Assemble for the 68000. @samp{-m68008}, @samp{-m68302}, and so on are synonyms
 132 for @samp{-m68000}, since the chips are the same from the point of view
 133 of the assembler.
 134
 135 @item -m68010
 136 Assemble for the 68010.
 137
 138 @item -m68020
 139 @itemx -m68ec020
 140 Assemble for the 68020.  This is normally the default.
 141
 142 @item -m68030
 143 @itemx -m68ec030
 144 Assemble for the 68030.
 145
 146 @item -m68040
 147 @itemx -m68ec040
 148 Assemble for the 68040.
 149
 150 @item -m68060
 151 @itemx -m68ec060
 152 Assemble for the 68060.
 153
 154 @item -mcpu32
 155 @itemx -m68330
 156 @itemx -m68331
 157 @itemx -m68332
 158 @itemx -m68333
 159 @itemx -m68334
 160 @itemx -m68336
 161 @itemx -m68340
 162 @itemx -m68341
 163 @itemx -m68349
 164 @itemx -m68360
 165 Assemble for the CPU32 family of chips.
 166
 167 @item -m5200
 168 @item -m5202
 169 @item -m5204
 170 @item -m5206
 171 @item -m5206e
 172 @item -m528x
 173 @item -m5307
 174 @item -m5407
 175 @item -mcfv4
 176 @item -mcfv4e
 177 Assemble for the ColdFire family of chips.
 178
 179 @item -m68881
 180 @itemx -m68882
 181 Assemble 68881 floating point instructions.  This is the default for the
 182 68020, 68030, and the CPU32.  The 68040 and 68060 always support
 183 floating point instructions.
 184
 185 @item -mno-68881
 186 Do not assemble 68881 floating point instructions.  This is the default
 187 for 68000 and the 68010.  The 68040 and 68060 always support floating
 188 point instructions, even if this option is used.
 189
 190 @item -m68851
 191 Assemble 68851 MMU instructions.  This is the default for the 68020,
 192 68030, and 68060.  The 68040 accepts a somewhat different set of MMU
 193 instructions; @samp{-m68851} and @samp{-m68040} should not be used
 194 together.
 195
 196 @item -mno-68851
 197 Do not assemble 68851 MMU instructions.  This is the default for the
 198 68000, 68010, and the CPU32.  The 68040 accepts a somewhat different set
 199 of MMU instructions.
 200 @end table
 201 @end table
 202
 203 @node M68K-Syntax
 204 @section Syntax
 205
 206 @cindex @sc{mit}
 207 This syntax for the Motorola 680x0 was developed at @sc{mit}.
 208
 209 @cindex M680x0 syntax
 210 @cindex syntax, M680x0
 211 @cindex M680x0 size modifiers
 212 @cindex size modifiers, M680x0
 213 The 680x0 version of @code{@value{AS}} uses instructions names and
 214 syntax compatible with the Sun assembler.  Intervening periods are
 215 ignored; for example, @samp{movl} is equivalent to @samp{mov.l}.
 216
 217 In the following table @var{apc} stands for any of the address registers
 218 (@samp{%a0} through @samp{%a7}), the program counter (@samp{%pc}), the
 219 zero-address relative to the program counter (@samp{%zpc}), a suppressed
 220 address register (@samp{%za0} through @samp{%za7}), or it may be omitted
 221 entirely.  The use of @var{size} means one of @samp{w} or @samp{l}, and
 222 it may be omitted, along with the leading colon, unless a scale is also
 223 specified.  The use of @var{scale} means one of @samp{1}, @samp{2},
 224 @samp{4}, or @samp{8}, and it may always be omitted along with the
 225 leading colon.
 226
 227 @cindex M680x0 addressing modes
 228 @cindex addressing modes, M680x0
 229 The following addressing modes are understood:
 230 @table @dfn
 231 @item Immediate
 232 @samp{#@var{number}}
 233
 234 @item Data Register
 235 @samp{%d0} through @samp{%d7}
 236
 237 @item Address Register
 238 @samp{%a0} through @samp{%a7}@*
 239 @samp{%a7} is also known as @samp{%sp}, i.e. the Stack Pointer.  @code{%a6}
 240 is also known as @samp{%fp}, the Frame Pointer.
 241
 242 @item Address Register Indirect
 243 @samp{%a0@@} through @samp{%a7@@}
 244
 245 @item Address Register Postincrement
 246 @samp{%a0@@+} through @samp{%a7@@+}
 247
 248 @item Address Register Predecrement
 249 @samp{%a0@@-} through @samp{%a7@@-}
 250
 251 @item Indirect Plus Offset
 252 @samp{@var{apc}@@(@var{number})}
 253
 254 @item Index
 255 @samp{@var{apc}@@(@var{number},@var{register}:@var{size}:@var{scale})}
 256
 257 The @var{number} may be omitted.
 258
 259 @item Postindex
 260 @samp{@var{apc}@@(@var{number})@@(@var{onumber},@var{register}:@var{size}:@var{scale})}
 261
 262 The @var{onumber} or the @var{register}, but not both, may be omitted.
 263
 264 @item Preindex
 265 @samp{@var{apc}@@(@var{number},@var{register}:@var{size}:@var{scale})@@(@var{onumber})}
 266
 267 The @var{number} may be omitted.  Omitting the @var{register} produces
 268 the Postindex addressing mode.
 269
 270 @item Absolute
 271 @samp{@var{symbol}}, or @samp{@var{digits}}, optionally followed by
 272 @samp{:b}, @samp{:w}, or @samp{:l}.
 273 @end table
 274
 275 @node M68K-Moto-Syntax
 276 @section Motorola Syntax
 277
 278 @cindex Motorola syntax for the 680x0
 279 @cindex alternate syntax for the 680x0
 280
 281 The standard Motorola syntax for this chip differs from the syntax
 282 already discussed (@pxref{M68K-Syntax,,Syntax}).  @code{@value{AS}} can
 283 accept Motorola syntax for operands, even if @sc{mit} syntax is used for
 284 other operands in the same instruction.  The two kinds of syntax are
 285 fully compatible.
 286
 287 In the following table @var{apc} stands for any of the address registers
 288 (@samp{%a0} through @samp{%a7}), the program counter (@samp{%pc}), the
 289 zero-address relative to the program counter (@samp{%zpc}), or a
 290 suppressed address register (@samp{%za0} through @samp{%za7}).  The use
 291 of @var{size} means one of @samp{w} or @samp{l}, and it may always be
 292 omitted along with the leading dot.  The use of @var{scale} means one of
 293 @samp{1}, @samp{2}, @samp{4}, or @samp{8}, and it may always be omitted
 294 along with the leading asterisk.
 295
 296 The following additional addressing modes are understood:
 297
 298 @table @dfn
 299 @item Address Register Indirect
 300 @samp{(%a0)} through @samp{(%a7)}@*
 301 @samp{%a7} is also known as @samp{%sp}, i.e. the Stack Pointer.  @code{%a6}
 302 is also known as @samp{%fp}, the Frame Pointer.
 303
 304 @item Address Register Postincrement
 305 @samp{(%a0)+} through @samp{(%a7)+}
 306
 307 @item Address Register Predecrement
 308 @samp{-(%a0)} through @samp{-(%a7)}
 309
 310 @item Indirect Plus Offset
 311 @samp{@var{number}(@var{%a0})} through @samp{@var{number}(@var{%a7})},
 312 or @samp{@var{number}(@var{%pc})}.
 313
 314 The @var{number} may also appear within the parentheses, as in
 315 @samp{(@var{number},@var{%a0})}.  When used with the @var{pc}, the
 316 @var{number} may be omitted (with an address register, omitting the
 317 @var{number} produces Address Register Indirect mode).
 318
 319 @item Index
 320 @samp{@var{number}(@var{apc},@var{register}.@var{size}*@var{scale})}
 321
 322 The @var{number} may be omitted, or it may appear within the
 323 parentheses.  The @var{apc} may be omitted.  The @var{register} and the
 324 @var{apc} may appear in either order.  If both @var{apc} and
 325 @var{register} are address registers, and the @var{size} and @var{scale}
 326 are omitted, then the first register is taken as the base register, and
 327 the second as the index register.
 328
 329 @item Postindex
 330 @samp{([@var{number},@var{apc}],@var{register}.@var{size}*@var{scale},@var{onumber})}
 331
 332 The @var{onumber}, or the @var{register}, or both, may be omitted.
 333 Either the @var{number} or the @var{apc} may be omitted, but not both.
 334
 335 @item Preindex
 336 @samp{([@var{number},@var{apc},@var{register}.@var{size}*@var{scale}],@var{onumber})}
 337
 338 The @var{number}, or the @var{apc}, or the @var{register}, or any two of
 339 them, may be omitted.  The @var{onumber} may be omitted.  The
 340 @var{register} and the @var{apc} may appear in either order.  If both
 341 @var{apc} and @var{register} are address registers, and the @var{size}
 342 and @var{scale} are omitted, then the first register is taken as the
 343 base register, and the second as the index register.
 344 @end table
 345
 346 @node M68K-Float
 347 @section Floating Point
 348
 349 @cindex floating point, M680x0
 350 @cindex M680x0 floating point
 351 Packed decimal (P) format floating literals are not supported.
 352 Feel free to add the code!
 353
 354 The floating point formats generated by directives are these.
 355
 356 @table @code
 357 @cindex @code{float} directive, M680x0
 358 @item .float
 359 @code{Single} precision floating point constants.
 360
 361 @cindex @code{double} directive, M680x0
 362 @item .double
 363 @code{Double} precision floating point constants.
 364
 365 @cindex @code{extend} directive M680x0
 366 @cindex @code{ldouble} directive M680x0
 367 @item .extend
 368 @itemx .ldouble
 369 @code{Extended} precision (@code{long double}) floating point constants.
 370 @end table
 371
 372 @node M68K-Directives
 373 @section 680x0 Machine Directives
 374
 375 @cindex M680x0 directives
 376 @cindex directives, M680x0
 377 In order to be compatible with the Sun assembler the 680x0 assembler
 378 understands the following directives.
 379
 380 @table @code
 381 @cindex @code{data1} directive, M680x0
 382 @item .data1
 383 This directive is identical to a @code{.data 1} directive.
 384
 385 @cindex @code{data2} directive, M680x0
 386 @item .data2
 387 This directive is identical to a @code{.data 2} directive.
 388
 389 @cindex @code{even} directive, M680x0
 390 @item .even
 391 This directive is a special case of the @code{.align} directive; it
 392 aligns the output to an even byte boundary.
 393
 394 @cindex @code{skip} directive, M680x0
 395 @item .skip
 396 This directive is identical to a @code{.space} directive.
 397 @end table
 398
 399 @need 2000
 400 @node M68K-opcodes
 401 @section Opcodes
 402
 403 @cindex M680x0 opcodes
 404 @cindex opcodes, M680x0
 405 @cindex instruction set, M680x0
 406 @c doc@cygnus.com: I don't see any point in the following
 407 @c                   paragraph.  Bugs are bugs; how does saying this
 408 @c                   help anyone?
 409 @ignore
 410 Danger:  Several bugs have been found in the opcode table (and
 411 fixed).  More bugs may exist.  Be careful when using obscure
 412 instructions.
 413 @end ignore
 414
 415 @menu
 416 * M68K-Branch::                 Branch Improvement
 417 * M68K-Chars::                  Special Characters
 418 @end menu
 419
 420 @node M68K-Branch
 421 @subsection Branch Improvement
 422
 423 @cindex pseudo-opcodes, M680x0
 424 @cindex M680x0 pseudo-opcodes
 425 @cindex branch improvement, M680x0
 426 @cindex M680x0 branch improvement
 427 Certain pseudo opcodes are permitted for branch instructions.
 428 They expand to the shortest branch instruction that reach the
 429 target.  Generally these mnemonics are made by substituting @samp{j} for
 430 @samp{b} at the start of a Motorola mnemonic.
 431
 432 The following table summarizes the pseudo-operations.  A @code{*} flags
 433 cases that are more fully described after the table:
 434
 435 @smallexample
 436           Displacement
 437           +------------------------------------------------------------
 438           |                68020           68000/10, not PC-relative OK
 439 Pseudo-Op |BYTE    WORD    LONG            ABSOLUTE LONG JUMP    **
 440           +------------------------------------------------------------
 441      jbsr |bsrs    bsrw    bsrl            jsr
 442       jra |bras    braw    bral            jmp
 443 *     jXX |bXXs    bXXw    bXXl            bNXs;jmp
 444 *    dbXX | N/A    dbXXw   dbXX;bras;bral  dbXX;bras;jmp
 445      fjXX | N/A    fbXXw   fbXXl            N/A
 446
 447 XX: condition
 448 NX: negative of condition XX
 449
 450 @end smallexample
 451 @center @code{*}---see full description below
 452 @center @code{**}---this expansion mode is disallowed by @samp{--pcrel}
 453
 454 @table @code
 455 @item jbsr
 456 @itemx jra
 457 These are the simplest jump pseudo-operations; they always map to one
 458 particular machine instruction, depending on the displacement to the
 459 branch target.  This instruction will be a byte or word branch is that
 460 is sufficient.  Otherwise, a long branch will be emitted if available.
 461 If no long branches are available and the @samp{--pcrel} option is not
 462 given, an absolute long jump will be emitted instead.  If no long
 463 branches are available, the @samp{--pcrel} option is given, and a word
 464 branch cannot reach the target, an error message is generated.
 465
 466 In addition to standard branch operands, @code{@value{AS}} allows these
 467 pseudo-operations to have all operands that are allowed for jsr and jmp,
 468 substituting these instructions if the operand given is not valid for a
 469 branch instruction.
 470
 471 @item j@var{XX}
 472 Here, @samp{j@var{XX}} stands for an entire family of pseudo-operations,
 473 where @var{XX} is a conditional branch or condition-code test.  The full
 474 list of pseudo-ops in this family is:
 475 @smallexample
 476  jhi   jls   jcc   jcs   jne   jeq   jvc
 477  jvs   jpl   jmi   jge   jlt   jgt   jle
 478 @end smallexample
 479
 480 Usually, each of these pseudo-operations expands to a single branch
 481 instruction.  However, if a word branch is not sufficient, no long branches
 482 are available, and the @samp{--pcrel} option is not given, @code{@value{AS}}
 483 issues a longer code fragment in terms of @var{NX}, the opposite condition
 484 to @var{XX}.  For example, under these conditions:
 485 @smallexample
 486     j@var{XX} foo
 487 @end smallexample
 488 gives
 489 @smallexample
 490      b@var{NX}s oof
 491      jmp foo
 492  oof:
 493 @end smallexample
 494
 495 @item db@var{XX}
 496 The full family of pseudo-operations covered here is
 497 @smallexample
 498  dbhi   dbls   dbcc   dbcs   dbne   dbeq   dbvc
 499  dbvs   dbpl   dbmi   dbge   dblt   dbgt   dble
 500  dbf    dbra   dbt
 501 @end smallexample
 502
 503 Motorola @samp{db@var{XX}} instructions allow word displacements only.  When
 504 a word displacement is sufficient, each of these pseudo-operations expands
 505 to the corresponding Motorola instruction.  When a word displacement is not
 506 sufficient and long branches are available, when the source reads
 507 @samp{db@var{XX} foo}, @code{@value{AS}} emits
 508 @smallexample
 509      db@var{XX} oo1
 510      bras oo2
 511  oo1:bral foo
 512  oo2:
 513 @end smallexample
 514
 515 If, however, long branches are not available and the @samp{--pcrel} option is
 516 not given, @code{@value{AS}} emits
 517 @smallexample
 518      db@var{XX} oo1
 519      bras oo2
 520  oo1:jmp foo
 521  oo2:
 522 @end smallexample
 523
 524 @item fj@var{XX}
 525 This family includes
 526 @smallexample
 527  fjne   fjeq   fjge   fjlt   fjgt   fjle   fjf
 528  fjt    fjgl   fjgle  fjnge  fjngl  fjngle fjngt
 529  fjnle  fjnlt  fjoge  fjogl  fjogt  fjole  fjolt
 530  fjor   fjseq  fjsf   fjsne  fjst   fjueq  fjuge
 531  fjugt  fjule  fjult  fjun
 532 @end smallexample
 533
 534 Each of these pseudo-operations always expands to a single Motorola
 535 coprocessor branch instruction, word or long.  All Motorola coprocessor
 536 branch instructions allow both word and long displacements.
 537
 538 @end table
 539
 540 @node M68K-Chars
 541 @subsection Special Characters
 542
 543 @cindex special characters, M680x0
 544 @cindex M680x0 immediate character
 545 @cindex immediate character, M680x0
 546 @cindex M680x0 line comment character
 547 @cindex line comment character, M680x0
 548 @cindex comments, M680x0
 549 The immediate character is @samp{#} for Sun compatibility.  The
 550 line-comment character is @samp{|} (unless the @samp{--bitwise-or}
 551 option is used).  If a @samp{#} appears at the beginning of a line, it
 552 is treated as a comment unless it looks like @samp{# line file}, in
 553 which case it is treated normally.
 554