1 @c Copyright (C) 1991-2014 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
7 @chapter MIPS Dependent Features
10 @node Machine Dependencies
11 @chapter MIPS Dependent Features
14 @cindex MIPS processor
15 @sc{gnu} @code{@value{AS}} for MIPS architectures supports several
16 different MIPS processors, and MIPS ISA levels I through V, MIPS32,
17 and MIPS64. For information about the MIPS instruction set, see
18 @cite{MIPS RISC Architecture}, by Kane and Heindrich (Prentice-Hall).
19 For an overview of MIPS assembly conventions, see ``Appendix D:
20 Assembly Language Programming'' in the same work.
23 * MIPS Options:: Assembler options
24 * MIPS Macros:: High-level assembly macros
25 * MIPS Symbol Sizes:: Directives to override the size of symbols
26 * MIPS Small Data:: Controlling the use of small data accesses
27 * MIPS ISA:: Directives to override the ISA level
28 * MIPS assembly options:: Directives to control code generation
29 * MIPS autoextend:: Directives for extending MIPS 16 bit instructions
30 * MIPS insn:: Directive to mark data as an instruction
31 * MIPS NaN Encodings:: Directives to record which NaN encoding is being used
32 * MIPS Option Stack:: Directives to save and restore options
33 * MIPS ASE Instruction Generation Overrides:: Directives to control
34 generation of MIPS ASE instructions
35 * MIPS Floating-Point:: Directives to override floating-point options
36 * MIPS Syntax:: MIPS specific syntactical considerations
40 @section Assembler options
42 The MIPS configurations of @sc{gnu} @code{@value{AS}} support these
46 @cindex @code{-G} option (MIPS)
48 Set the ``small data'' limit to @var{n} bytes. The default limit is 8 bytes.
49 @xref{MIPS Small Data,, Controlling the use of small data accesses}.
51 @cindex @code{-EB} option (MIPS)
52 @cindex @code{-EL} option (MIPS)
53 @cindex MIPS big-endian output
54 @cindex MIPS little-endian output
55 @cindex big-endian output, MIPS
56 @cindex little-endian output, MIPS
59 Any MIPS configuration of @code{@value{AS}} can select big-endian or
60 little-endian output at run time (unlike the other @sc{gnu} development
61 tools, which must be configured for one or the other). Use @samp{-EB}
62 to select big-endian output, and @samp{-EL} for little-endian.
65 @cindex PIC selection, MIPS
66 @cindex @option{-KPIC} option, MIPS
67 Generate SVR4-style PIC. This option tells the assembler to generate
68 SVR4-style position-independent macro expansions. It also tells the
69 assembler to mark the output file as PIC.
72 @cindex @option{-mvxworks-pic} option, MIPS
73 Generate VxWorks PIC. This option tells the assembler to generate
74 VxWorks-style position-independent macro expansions.
76 @cindex MIPS architecture options
86 Generate code for a particular MIPS Instruction Set Architecture level.
87 @samp{-mips1} corresponds to the R2000 and R3000 processors,
88 @samp{-mips2} to the R6000 processor, @samp{-mips3} to the
89 R4000 processor, and @samp{-mips4} to the R8000 and R10000 processors.
90 @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, @samp{-mips64}, and
91 @samp{-mips64r2} correspond to generic MIPS V, MIPS32, MIPS32 Release 2,
92 MIPS64, and MIPS64 Release 2 ISA processors, respectively. You can also
93 switch instruction sets during the assembly; see @ref{MIPS ISA,
94 Directives to override the ISA level}.
98 Some macros have different expansions for 32-bit and 64-bit registers.
99 The register sizes are normally inferred from the ISA and ABI, but these
100 flags force a certain group of registers to be treated as 32 bits wide at
101 all times. @samp{-mgp32} controls the size of general-purpose registers
102 and @samp{-mfp32} controls the size of floating-point registers.
104 The @code{.set gp=32} and @code{.set fp=32} directives allow the size
105 of registers to be changed for parts of an object. The default value is
106 restored by @code{.set gp=default} and @code{.set fp=default}.
108 On some MIPS variants there is a 32-bit mode flag; when this flag is
109 set, 64-bit instructions generate a trap. Also, some 32-bit OSes only
110 save the 32-bit registers on a context switch, so it is essential never
111 to use the 64-bit registers.
115 Assume that 64-bit registers are available. This is provided in the
116 interests of symmetry with @samp{-mgp32} and @samp{-mfp32}.
118 The @code{.set gp=64} and @code{.set fp=64} directives allow the size
119 of registers to be changed for parts of an object. The default value is
120 restored by @code{.set gp=default} and @code{.set fp=default}.
124 Generate code for the MIPS 16 processor. This is equivalent to putting
125 @code{.set mips16} at the start of the assembly file. @samp{-no-mips16}
126 turns off this option.
129 @itemx -mno-micromips
130 Generate code for the microMIPS processor. This is equivalent to putting
131 @code{.set micromips} at the start of the assembly file. @samp{-mno-micromips}
132 turns off this option. This is equivalent to putting @code{.set nomicromips}
133 at the start of the assembly file.
136 @itemx -mno-smartmips
137 Enables the SmartMIPS extensions to the MIPS32 instruction set, which
138 provides a number of new instructions which target smartcard and
139 cryptographic applications. This is equivalent to putting
140 @code{.set smartmips} at the start of the assembly file.
141 @samp{-mno-smartmips} turns off this option.
145 Generate code for the MIPS-3D Application Specific Extension.
146 This tells the assembler to accept MIPS-3D instructions.
147 @samp{-no-mips3d} turns off this option.
151 Generate code for the MDMX Application Specific Extension.
152 This tells the assembler to accept MDMX instructions.
153 @samp{-no-mdmx} turns off this option.
157 Generate code for the DSP Release 1 Application Specific Extension.
158 This tells the assembler to accept DSP Release 1 instructions.
159 @samp{-mno-dsp} turns off this option.
163 Generate code for the DSP Release 2 Application Specific Extension.
164 This option implies -mdsp.
165 This tells the assembler to accept DSP Release 2 instructions.
166 @samp{-mno-dspr2} turns off this option.
170 Generate code for the MT Application Specific Extension.
171 This tells the assembler to accept MT instructions.
172 @samp{-mno-mt} turns off this option.
176 Generate code for the MCU Application Specific Extension.
177 This tells the assembler to accept MCU instructions.
178 @samp{-mno-mcu} turns off this option.
182 Generate code for the MIPS SIMD Architecture Extension.
183 This tells the assembler to accept MSA instructions.
184 @samp{-mno-msa} turns off this option.
188 Generate code for the Virtualization Application Specific Extension.
189 This tells the assembler to accept Virtualization instructions.
190 @samp{-mno-virt} turns off this option.
194 Only use 32-bit instruction encodings when generating code for the
195 microMIPS processor. This option inhibits the use of any 16-bit
196 instructions. This is equivalent to putting @code{.set insn32} at
197 the start of the assembly file. @samp{-mno-insn32} turns off this
198 option. This is equivalent to putting @code{.set noinsn32} at the
199 start of the assembly file. By default @samp{-mno-insn32} is
200 selected, allowing all instructions to be used.
204 Cause nops to be inserted if the read of the destination register
205 of an mfhi or mflo instruction occurs in the following two instructions.
208 @itemx -mno-fix-rm7000
209 Cause nops to be inserted if a dmult or dmultu instruction is
210 followed by a load instruction.
212 @item -mfix-loongson2f-jump
213 @itemx -mno-fix-loongson2f-jump
214 Eliminate instruction fetch from outside 256M region to work around the
215 Loongson2F @samp{jump} instructions. Without it, under extreme cases,
216 the kernel may crash. The issue has been solved in latest processor
217 batches, but this fix has no side effect to them.
219 @item -mfix-loongson2f-nop
220 @itemx -mno-fix-loongson2f-nop
221 Replace nops by @code{or at,at,zero} to work around the Loongson2F
222 @samp{nop} errata. Without it, under extreme cases, the CPU might
223 deadlock. The issue has been solved in later Loongson2F batches, but
224 this fix has no side effect to them.
227 @itemx -mno-fix-vr4120
228 Insert nops to work around certain VR4120 errata. This option is
229 intended to be used on GCC-generated code: it is not designed to catch
230 all problems in hand-written assembler code.
233 @itemx -mno-fix-vr4130
234 Insert nops to work around the VR4130 @samp{mflo}/@samp{mfhi} errata.
238 Insert nops to work around the 24K @samp{eret}/@samp{deret} errata.
241 @itemx -mno-fix-cn63xxp1
242 Replace @code{pref} hints 0 - 4 and 6 - 24 with hint 28 to work around
243 certain CN63XXP1 errata.
247 Generate code for the LSI R4010 chip. This tells the assembler to
248 accept the R4010-specific instructions (@samp{addciu}, @samp{ffc},
249 etc.), and to not schedule @samp{nop} instructions around accesses to
250 the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this
255 Generate code for the MIPS R4650 chip. This tells the assembler to accept
256 the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop}
257 instructions around accesses to the @samp{HI} and @samp{LO} registers.
258 @samp{-no-m4650} turns off this option.
264 For each option @samp{-m@var{nnnn}}, generate code for the MIPS
265 R@var{nnnn} chip. This tells the assembler to accept instructions
266 specific to that chip, and to schedule for that chip's hazards.
268 @item -march=@var{cpu}
269 Generate code for a particular MIPS CPU. It is exactly equivalent to
270 @samp{-m@var{cpu}}, except that there are more value of @var{cpu}
271 understood. Valid @var{cpu} value are:
357 For compatibility reasons, @samp{@var{n}x} and @samp{@var{b}fx} are
358 accepted as synonyms for @samp{@var{n}f1_1}. These values are
361 @item -mtune=@var{cpu}
362 Schedule and tune for a particular MIPS CPU. Valid @var{cpu} values are
363 identical to @samp{-march=@var{cpu}}.
365 @item -mabi=@var{abi}
366 Record which ABI the source code uses. The recognized arguments
367 are: @samp{32}, @samp{n32}, @samp{o64}, @samp{64} and @samp{eabi}.
373 Equivalent to adding @code{.set sym32} or @code{.set nosym32} to
374 the beginning of the assembler input. @xref{MIPS Symbol Sizes}.
376 @cindex @code{-nocpp} ignored (MIPS)
378 This option is ignored. It is accepted for command-line compatibility with
379 other assemblers, which use it to turn off C style preprocessing. With
380 @sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the
381 @sc{gnu} assembler itself never runs the C preprocessor.
385 Disable or enable floating-point instructions. Note that by default
386 floating-point instructions are always allowed even with CPU targets
387 that don't have support for these instructions.
390 @itemx -mdouble-float
391 Disable or enable double-precision floating-point operations. Note
392 that by default double-precision floating-point operations are always
393 allowed even with CPU targets that don't have support for these
396 @item --construct-floats
397 @itemx --no-construct-floats
398 The @code{--no-construct-floats} option disables the construction of
399 double width floating point constants by loading the two halves of the
400 value into the two single width floating point registers that make up
401 the double width register. This feature is useful if the processor
402 support the FR bit in its status register, and this bit is known (by
403 the programmer) to be set. This bit prevents the aliasing of the double
404 width register by the single width registers.
406 By default @code{--construct-floats} is selected, allowing construction
407 of these floating point constants.
410 @itemx --no-relax-branch
411 The @samp{--relax-branch} option enables the relaxation of out-of-range
412 branches. Any branches whose target cannot be reached directly are
413 converted to a small instruction sequence including an inverse-condition
414 branch to the physically next instruction, and a jump to the original
415 target is inserted between the two instructions. In PIC code the jump
416 will involve further instructions for address calculation.
418 The @code{BC1ANY2F}, @code{BC1ANY2T}, @code{BC1ANY4F}, @code{BC1ANY4T},
419 @code{BPOSGE32} and @code{BPOSGE64} instructions are excluded from
420 relaxation, because they have no complementing counterparts. They could
421 be relaxed with the use of a longer sequence involving another branch,
422 however this has not been implemented and if their target turns out of
423 reach, they produce an error even if branch relaxation is enabled.
425 Also no MIPS16 branches are ever relaxed.
427 By default @samp{--no-relax-branch} is selected, causing any out-of-range
428 branches to produce an error.
430 @cindex @option{-mnan=} command line option, MIPS
431 @item -mnan=@var{encoding}
432 This option indicates whether the source code uses the IEEE 2008
433 NaN encoding (@option{-mnan=2008}) or the original MIPS encoding
434 (@option{-mnan=legacy}). It is equivalent to adding a @code{.nan}
435 directive to the beginning of the source file. @xref{MIPS NaN Encodings}.
437 @option{-mnan=legacy} is the default if no @option{-mnan} option or
438 @code{.nan} directive is used.
442 @c FIXME! (1) reflect these options (next item too) in option summaries;
443 @c (2) stop teasing, say _which_ instructions expanded _how_.
444 @code{@value{AS}} automatically macro expands certain division and
445 multiplication instructions to check for overflow and division by zero. This
446 option causes @code{@value{AS}} to generate code to take a trap exception
447 rather than a break exception when an error is detected. The trap instructions
448 are only supported at Instruction Set Architecture level 2 and higher.
452 Generate code to take a break exception rather than a trap exception when an
453 error is detected. This is the default.
457 Control generation of @code{.pdr} sections. Off by default on IRIX, on
462 When generating code using the Unix calling conventions (selected by
463 @samp{-KPIC} or @samp{-mcall_shared}), gas will normally generate code
464 which can go into a shared library. The @samp{-mno-shared} option
465 tells gas to generate code which uses the calling convention, but can
466 not go into a shared library. The resulting code is slightly more
467 efficient. This option only affects the handling of the
468 @samp{.cpload} and @samp{.cpsetup} pseudo-ops.
472 @section High-level assembly macros
474 MIPS assemblers have traditionally provided a wider range of
475 instructions than the MIPS architecture itself. These extra
476 instructions are usually referred to as ``macro'' instructions
477 @footnote{The term ``macro'' is somewhat overloaded here, since
478 these macros have no relation to those defined by @code{.macro},
479 @pxref{Macro,, @code{.macro}}.}.
481 Some MIPS macro instructions extend an underlying architectural instruction
482 while others are entirely new. An example of the former type is @code{and},
483 which allows the third operand to be either a register or an arbitrary
484 immediate value. Examples of the latter type include @code{bgt}, which
485 branches to the third operand when the first operand is greater than
486 the second operand, and @code{ulh}, which implements an unaligned
489 One of the most common extensions provided by macros is to expand
490 memory offsets to the full address range (32 or 64 bits) and to allow
491 symbolic offsets such as @samp{my_data + 4} to be used in place of
492 integer constants. For example, the architectural instruction
493 @code{lbu} allows only a signed 16-bit offset, whereas the macro
494 @code{lbu} allows code such as @samp{lbu $4,array+32769($5)}.
495 The implementation of these symbolic offsets depends on several factors,
496 such as whether the assembler is generating SVR4-style PIC (selected by
497 @option{-KPIC}, @pxref{MIPS Options,, Assembler options}), the size of symbols
498 (@pxref{MIPS Symbol Sizes,, Directives to override the size of symbols}),
499 and the small data limit (@pxref{MIPS Small Data,, Controlling the use
500 of small data accesses}).
502 @kindex @code{.set macro}
503 @kindex @code{.set nomacro}
504 Sometimes it is undesirable to have one assembly instruction expand
505 to several machine instructions. The directive @code{.set nomacro}
506 tells the assembler to warn when this happens. @code{.set macro}
507 restores the default behavior.
509 @cindex @code{at} register, MIPS
510 @kindex @code{.set at=@var{reg}}
511 Some macro instructions need a temporary register to store intermediate
512 results. This register is usually @code{$1}, also known as @code{$at},
513 but it can be changed to any core register @var{reg} using
514 @code{.set at=@var{reg}}. Note that @code{$at} always refers
515 to @code{$1} regardless of which register is being used as the
518 @kindex @code{.set at}
519 @kindex @code{.set noat}
520 Implicit uses of the temporary register in macros could interfere with
521 explicit uses in the assembly code. The assembler therefore warns
522 whenever it sees an explicit use of the temporary register. The directive
523 @code{.set noat} silences this warning while @code{.set at} restores
524 the default behavior. It is safe to use @code{.set noat} while
525 @code{.set nomacro} is in effect since single-instruction macros
526 never need a temporary register.
528 Note that while the @sc{gnu} assembler provides these macros for compatibility,
529 it does not make any attempt to optimize them with the surrounding code.
531 @node MIPS Symbol Sizes
532 @section Directives to override the size of symbols
534 @kindex @code{.set sym32}
535 @kindex @code{.set nosym32}
536 The n64 ABI allows symbols to have any 64-bit value. Although this
537 provides a great deal of flexibility, it means that some macros have
538 much longer expansions than their 32-bit counterparts. For example,
539 the non-PIC expansion of @samp{dla $4,sym} is usually:
544 daddiu $4,$4,%higher(sym)
545 daddiu $1,$1,%lo(sym)
550 whereas the 32-bit expansion is simply:
554 daddiu $4,$4,%lo(sym)
557 n64 code is sometimes constructed in such a way that all symbolic
558 constants are known to have 32-bit values, and in such cases, it's
559 preferable to use the 32-bit expansion instead of the 64-bit
562 You can use the @code{.set sym32} directive to tell the assembler
563 that, from this point on, all expressions of the form
564 @samp{@var{symbol}} or @samp{@var{symbol} + @var{offset}}
565 have 32-bit values. For example:
574 will cause the assembler to treat @samp{sym}, @code{sym+16} and
575 @code{sym+0x8000} as 32-bit values. The handling of non-symbolic
576 addresses is not affected.
578 The directive @code{.set nosym32} ends a @code{.set sym32} block and
579 reverts to the normal behavior. It is also possible to change the
580 symbol size using the command-line options @option{-msym32} and
583 These options and directives are always accepted, but at present,
584 they have no effect for anything other than n64.
586 @node MIPS Small Data
587 @section Controlling the use of small data accesses
589 @c This section deliberately glosses over the possibility of using -G
590 @c in SVR4-style PIC, as could be done on IRIX. We don't support that.
591 @cindex small data, MIPS
592 @cindex @code{gp} register, MIPS
593 It often takes several instructions to load the address of a symbol.
594 For example, when @samp{addr} is a 32-bit symbol, the non-PIC expansion
595 of @samp{dla $4,addr} is usually:
599 daddiu $4,$4,%lo(addr)
602 The sequence is much longer when @samp{addr} is a 64-bit symbol.
603 @xref{MIPS Symbol Sizes,, Directives to override the size of symbols}.
605 In order to cut down on this overhead, most embedded MIPS systems
606 set aside a 64-kilobyte ``small data'' area and guarantee that all
607 data of size @var{n} and smaller will be placed in that area.
608 The limit @var{n} is passed to both the assembler and the linker
609 using the command-line option @option{-G @var{n}}, @pxref{MIPS Options,,
610 Assembler options}. Note that the same value of @var{n} must be used
611 when linking and when assembling all input files to the link; any
612 inconsistency could cause a relocation overflow error.
614 The size of an object in the @code{.bss} section is set by the
615 @code{.comm} or @code{.lcomm} directive that defines it. The size of
616 an external object may be set with the @code{.extern} directive. For
617 example, @samp{.extern sym,4} declares that the object at @code{sym}
618 is 4 bytes in length, while leaving @code{sym} otherwise undefined.
620 When no @option{-G} option is given, the default limit is 8 bytes.
621 The option @option{-G 0} prevents any data from being automatically
624 It is also possible to mark specific objects as small by putting them
625 in the special sections @code{.sdata} and @code{.sbss}, which are
626 ``small'' counterparts of @code{.data} and @code{.bss} respectively.
627 The toolchain will treat such data as small regardless of the
630 On startup, systems that support a small data area are expected to
631 initialize register @code{$28}, also known as @code{$gp}, in such a
632 way that small data can be accessed using a 16-bit offset from that
633 register. For example, when @samp{addr} is small data,
634 the @samp{dla $4,addr} instruction above is equivalent to:
637 daddiu $4,$28,%gp_rel(addr)
640 Small data is not supported for SVR4-style PIC.
643 @section Directives to override the ISA level
645 @cindex MIPS ISA override
646 @kindex @code{.set mips@var{n}}
647 @sc{gnu} @code{@value{AS}} supports an additional directive to change
648 the MIPS Instruction Set Architecture level on the fly: @code{.set
649 mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 64
651 The values other than 0 make the assembler accept instructions
652 for the corresponding ISA level, from that point on in the
653 assembly. @code{.set mips@var{n}} affects not only which instructions
654 are permitted, but also how certain macros are expanded. @code{.set
655 mips0} restores the ISA level to its original level: either the
656 level you selected with command line options, or the default for your
657 configuration. You can use this feature to permit specific MIPS III
658 instructions while assembling in 32 bit mode. Use this directive with
661 @cindex MIPS CPU override
662 @kindex @code{.set arch=@var{cpu}}
663 The @code{.set arch=@var{cpu}} directive provides even finer control.
664 It changes the effective CPU target and allows the assembler to use
665 instructions specific to a particular CPU. All CPUs supported by the
666 @samp{-march} command line option are also selectable by this directive.
667 The original value is restored by @code{.set arch=default}.
669 The directive @code{.set mips16} puts the assembler into MIPS 16 mode,
670 in which it will assemble instructions for the MIPS 16 processor. Use
671 @code{.set nomips16} to return to normal 32 bit mode.
673 Traditional MIPS assemblers do not support this directive.
675 The directive @code{.set micromips} puts the assembler into microMIPS mode,
676 in which it will assemble instructions for the microMIPS processor. Use
677 @code{.set nomicromips} to return to normal 32 bit mode.
679 Traditional MIPS assemblers do not support this directive.
681 @node MIPS assembly options
682 @section Directives to control code generation
684 @cindex MIPS 32-bit microMIPS instruction generation override
685 @kindex @code{.set insn32}
686 @kindex @code{.set noinsn32}
687 The directive @code{.set insn32} makes the assembler only use 32-bit
688 instruction encodings when generating code for the microMIPS processor.
689 This directive inhibits the use of any 16-bit instructions from that
690 point on in the assembly. The @code{.set noinsn32} directive allows
691 16-bit instructions to be accepted.
693 Traditional MIPS assemblers do not support this directive.
695 @node MIPS autoextend
696 @section Directives for extending MIPS 16 bit instructions
698 @kindex @code{.set autoextend}
699 @kindex @code{.set noautoextend}
700 By default, MIPS 16 instructions are automatically extended to 32 bits
701 when necessary. The directive @code{.set noautoextend} will turn this
702 off. When @code{.set noautoextend} is in effect, any 32 bit instruction
703 must be explicitly extended with the @code{.e} modifier (e.g.,
704 @code{li.e $4,1000}). The directive @code{.set autoextend} may be used
705 to once again automatically extend instructions when necessary.
707 This directive is only meaningful when in MIPS 16 mode. Traditional
708 MIPS assemblers do not support this directive.
711 @section Directive to mark data as an instruction
714 The @code{.insn} directive tells @code{@value{AS}} that the following
715 data is actually instructions. This makes a difference in MIPS 16 and
716 microMIPS modes: when loading the address of a label which precedes
717 instructions, @code{@value{AS}} automatically adds 1 to the value, so
718 that jumping to the loaded address will do the right thing.
720 @kindex @code{.global}
721 The @code{.global} and @code{.globl} directives supported by
722 @code{@value{AS}} will by default mark the symbol as pointing to a
723 region of data not code. This means that, for example, any
724 instructions following such a symbol will not be disassembled by
725 @code{objdump} as it will regard them as data. To change this
726 behaviour an optional section name can be placed after the symbol name
727 in the @code{.global} directive. If this section exists and is known
728 to be a code section, then the symbol will be marked as poiting at
729 code not data. Ie the syntax for the directive is:
731 @code{.global @var{symbol}[ @var{section}][, @var{symbol}[ @var{section}]] ...},
733 Here is a short example:
736 .global foo .text, bar, baz .data
746 @node MIPS NaN Encodings
747 @section Directives to record which NaN encoding is being used
749 @cindex MIPS IEEE 754 NaN data encoding selection
750 @cindex @code{.nan} directive, MIPS
751 The IEEE 754 floating-point standard defines two types of not-a-number
752 (NaN) data: ``signalling'' NaNs and ``quiet'' NaNs. The original version
753 of the standard did not specify how these two types should be
754 distinguished. Most implementations followed the i387 model, in which
755 the first bit of the significand is set for quiet NaNs and clear for
756 signalling NaNs. However, the original MIPS implementation assigned the
757 opposite meaning to the bit, so that it was set for signalling NaNs and
758 clear for quiet NaNs.
760 The 2008 revision of the standard formally suggested the i387 choice
761 and as from Sep 2012 the current release of the MIPS architecture
762 therefore optionally supports that form. Code that uses one NaN encoding
763 would usually be incompatible with code that uses the other NaN encoding,
764 so MIPS ELF objects have a flag (@code{EF_MIPS_NAN2008}) to record which
765 encoding is being used.
767 Assembly files can use the @code{.nan} directive to select between the
768 two encodings. @samp{.nan 2008} says that the assembly file uses the
769 IEEE 754-2008 encoding while @samp{.nan legacy} says that the file uses
770 the original MIPS encoding. If several @code{.nan} directives are given,
771 the final setting is the one that is used.
773 The command-line options @option{-mnan=legacy} and @option{-mnan=2008}
774 can be used instead of @samp{.nan legacy} and @samp{.nan 2008}
775 respectively. However, any @code{.nan} directive overrides the
776 command-line setting.
778 @samp{.nan legacy} is the default if no @code{.nan} directive or
779 @option{-mnan} option is given.
781 Note that @sc{gnu} @code{@value{AS}} does not produce NaNs itself and
782 therefore these directives do not affect code generation. They simply
783 control the setting of the @code{EF_MIPS_NAN2008} flag.
785 Traditional MIPS assemblers do not support these directives.
787 @node MIPS Option Stack
788 @section Directives to save and restore options
790 @cindex MIPS option stack
791 @kindex @code{.set push}
792 @kindex @code{.set pop}
793 The directives @code{.set push} and @code{.set pop} may be used to save
794 and restore the current settings for all the options which are
795 controlled by @code{.set}. The @code{.set push} directive saves the
796 current settings on a stack. The @code{.set pop} directive pops the
797 stack and restores the settings.
799 These directives can be useful inside an macro which must change an
800 option such as the ISA level or instruction reordering but does not want
801 to change the state of the code which invoked the macro.
803 Traditional MIPS assemblers do not support these directives.
805 @node MIPS ASE Instruction Generation Overrides
806 @section Directives to control generation of MIPS ASE instructions
808 @cindex MIPS MIPS-3D instruction generation override
809 @kindex @code{.set mips3d}
810 @kindex @code{.set nomips3d}
811 The directive @code{.set mips3d} makes the assembler accept instructions
812 from the MIPS-3D Application Specific Extension from that point on
813 in the assembly. The @code{.set nomips3d} directive prevents MIPS-3D
814 instructions from being accepted.
816 @cindex SmartMIPS instruction generation override
817 @kindex @code{.set smartmips}
818 @kindex @code{.set nosmartmips}
819 The directive @code{.set smartmips} makes the assembler accept
820 instructions from the SmartMIPS Application Specific Extension to the
821 MIPS32 ISA from that point on in the assembly. The
822 @code{.set nosmartmips} directive prevents SmartMIPS instructions from
825 @cindex MIPS MDMX instruction generation override
826 @kindex @code{.set mdmx}
827 @kindex @code{.set nomdmx}
828 The directive @code{.set mdmx} makes the assembler accept instructions
829 from the MDMX Application Specific Extension from that point on
830 in the assembly. The @code{.set nomdmx} directive prevents MDMX
831 instructions from being accepted.
833 @cindex MIPS DSP Release 1 instruction generation override
834 @kindex @code{.set dsp}
835 @kindex @code{.set nodsp}
836 The directive @code{.set dsp} makes the assembler accept instructions
837 from the DSP Release 1 Application Specific Extension from that point
838 on in the assembly. The @code{.set nodsp} directive prevents DSP
839 Release 1 instructions from being accepted.
841 @cindex MIPS DSP Release 2 instruction generation override
842 @kindex @code{.set dspr2}
843 @kindex @code{.set nodspr2}
844 The directive @code{.set dspr2} makes the assembler accept instructions
845 from the DSP Release 2 Application Specific Extension from that point
846 on in the assembly. This dirctive implies @code{.set dsp}. The
847 @code{.set nodspr2} directive prevents DSP Release 2 instructions from
850 @cindex MIPS MT instruction generation override
851 @kindex @code{.set mt}
852 @kindex @code{.set nomt}
853 The directive @code{.set mt} makes the assembler accept instructions
854 from the MT Application Specific Extension from that point on
855 in the assembly. The @code{.set nomt} directive prevents MT
856 instructions from being accepted.
858 @cindex MIPS MCU instruction generation override
859 @kindex @code{.set mcu}
860 @kindex @code{.set nomcu}
861 The directive @code{.set mcu} makes the assembler accept instructions
862 from the MCU Application Specific Extension from that point on
863 in the assembly. The @code{.set nomcu} directive prevents MCU
864 instructions from being accepted.
866 @cindex MIPS SIMD Architecture instruction generation override
867 @kindex @code{.set msa}
868 @kindex @code{.set nomsa}
869 The directive @code{.set msa} makes the assembler accept instructions
870 from the MIPS SIMD Architecture Extension from that point on
871 in the assembly. The @code{.set nomsa} directive prevents MSA
872 instructions from being accepted.
874 @cindex Virtualization instruction generation override
875 @kindex @code{.set virt}
876 @kindex @code{.set novirt}
877 The directive @code{.set virt} makes the assembler accept instructions
878 from the Virtualization Application Specific Extension from that point
879 on in the assembly. The @code{.set novirt} directive prevents Virtualization
880 instructions from being accepted.
882 Traditional MIPS assemblers do not support these directives.
884 @node MIPS Floating-Point
885 @section Directives to override floating-point options
887 @cindex Disable floating-point instructions
888 @kindex @code{.set softfloat}
889 @kindex @code{.set hardfloat}
890 The directives @code{.set softfloat} and @code{.set hardfloat} provide
891 finer control of disabling and enabling float-point instructions.
892 These directives always override the default (that hard-float
893 instructions are accepted) or the command-line options
894 (@samp{-msoft-float} and @samp{-mhard-float}).
896 @cindex Disable single-precision floating-point operations
897 @kindex @code{.set singlefloat}
898 @kindex @code{.set doublefloat}
899 The directives @code{.set singlefloat} and @code{.set doublefloat}
900 provide finer control of disabling and enabling double-precision
901 float-point operations. These directives always override the default
902 (that double-precision operations are accepted) or the command-line
903 options (@samp{-msingle-float} and @samp{-mdouble-float}).
905 Traditional MIPS assemblers do not support these directives.
908 @section Syntactical considerations for the MIPS assembler
910 * MIPS-Chars:: Special Characters
914 @subsection Special Characters
916 @cindex line comment character, MIPS
917 @cindex MIPS line comment character
918 The presence of a @samp{#} on a line indicates the start of a comment
919 that extends to the end of the current line.
921 If a @samp{#} appears as the first character of a line, the whole line
922 is treated as a comment, but in this case the line can also be a
923 logical line number directive (@pxref{Comments}) or a
924 preprocessor control command (@pxref{Preprocessing}).
926 @cindex line separator, MIPS
927 @cindex statement separator, MIPS
928 @cindex MIPS line separator
929 The @samp{;} character can be used to separate statements on the same